change log:

	- update for 2.4.15/2.4.16:
		- add show_trace_task()
		- lots of SGI SN updates (most in "sn" subdirectories)
		- IA-32 brk() fix by Don Dugger
	- drop some of the more cosmetic fixes (they will be in the 2.5 tree instead)
	- fix EARLY_PRINTK (Tony Luck, I think)
	- in iosapic.c, move RTE programming to a saner place (Alex Williamson)
	- fix alignment of bootmap
	- move machvec_init() a little earlier and call platform_cpu_init() at end
	  of cpu_init() (Jack Steiner)
	- swiotlb.c: support "page" member in scatterlist
	- fix asm clobbers in spinlock.h
	- add more ACPI tables to asm-ia64/acpi-ext.h

diff -urN linux-2.4.16/Documentation/Configure.help lia64-2.4/Documentation/Configure.help
--- linux-2.4.16/Documentation/Configure.help	Mon Nov 26 11:18:14 2001
+++ lia64-2.4/Documentation/Configure.help	Mon Nov 26 11:58:46 2001
@@ -3173,6 +3173,16 @@
   You should say Y here if you use XFree86 3.3.6 or 4.x and want to
   use GLX or DRI.  If unsure, say N.
 
+Intel 460GX support
+CONFIG_AGP_I460
+  This option gives you AGP support for the Intel 460GX chipset.  This
+  chipset, the first to support Intel Itanium processors, is new and
+  this option is correspondingly a little experimental.
+
+  If you don't have a 460GX based machine (such as BigSur) with an AGP 
+  slot then this option isn't going to do you much good.  If you're
+  dying to do Direct Rendering on IA-64, this is what you're looking for.
+
 Intel I810/I815 DC100/I810e support
 CONFIG_AGP_I810
   This option gives you AGP support for the Xserver on the Intel 810
@@ -14648,6 +14658,18 @@
   Say Y here if you would like to be able to read the hard disk
   partition table format used by SGI machines.
 
+Intel EFI GUID partition support
+CONFIG_EFI_PARTITION
+  Say Y here if you would like to use hard disks under Linux which
+  were partitioned using EFI GPT.  Presently only useful on the
+  IA-64 platform.
+
+/dev/guid support (EXPERIMENTAL)
+CONFIG_DEVFS_GUID
+  Say Y here if you would like to access disks and partitions by
+  their Globally Unique Identifiers (GUIDs) which will appear as
+  symbolic links in /dev/guid.
+
 Ultrix partition table support
 CONFIG_ULTRIX_PARTITION
   Say Y here if you would like to be able to read the hard disk
@@ -23396,12 +23418,23 @@
 
   HP-simulator   For the HP simulator
                  (<http://software.hp.com/ia64linux/>).
-  SN1-simulator  For the SGI SN1 simulator.
+  SN1            For SGI SN1 Platforms.
+  SN2            For SGI SN2 Platforms.
   DIG-compliant  For DIG ("Developer's Interface Guide") compliant
                  system.
 
   If you don't know what to do, choose "generic".
 
+CONFIG_IA64_SGI_SN_SIM
+  Build a kernel that runs on both the SGI simulator AND on hardware.
+  There is a very slight performance penalty on hardware for including this
+  option.
+
+CONFIG_IA64_SGI_SN_DEBUG
+  This enables addition debug code that helps isolate
+  platform/kernel bugs. There is a small but measurable performance
+  degradation when this option is enabled.
+
 # Choice: pagesize
 Kernel page size
 CONFIG_IA64_PAGE_SIZE_4KB
@@ -23419,53 +23452,13 @@
 
   If you don't know what to do, choose 8KB.
 
-Enable Itanium A-step specific code
-CONFIG_ITANIUM_ASTEP_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with an A-step CPU.  You have an A-step CPU if the "revision" field
-  in /proc/cpuinfo is 0.
-
 Enable Itanium B-step specific code
 CONFIG_ITANIUM_BSTEP_SPECIFIC
   Select this option to build a kernel for an Itanium prototype system
-  with a B-step CPU.  You have a B-step CPU if the "revision" field in
-  /proc/cpuinfo has a value in the range from 1 to 4.
-
-Enable Itanium B0-step specific code
-CONFIG_ITANIUM_B0_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with a B0-step CPU.  You have a B0-step CPU if the "revision" field
-  in /proc/cpuinfo is 1.
-
-Enable Itanium C-step specific code
-CONFIG_ITANIUM_CSTEP_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with a C-step CPU.  You have a C-step CPU if the "revision" field in
-  /proc/cpuinfo is in the range of 5 to 8.
-
-Enable Itanium B1-step specific code
-CONFIG_ITANIUM_B1_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with a B1-step CPU.  You have a B1-step CPU if the "revision" field
-  in /proc/cpuinfo is 2.
-
-Enable Itanium B2-step specific code
-CONFIG_ITANIUM_B2_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with a B2-step CPU.  You have a B2-step CPU if the "revision" field
-  in /proc/cpuinfo is 3.
-
-Enable Itanium C0-step specific code
-CONFIG_ITANIUM_C0_SPECIFIC
-  Select this option to build a kernel for an Itanium prototype system
-  with a C0-step CPU.  You have a C0-step CPU if the "revision" field
-  in /proc/cpuinfo is 5.
-
-Force interrupt redirection
-CONFIG_IA64_HAVE_IRQREDIR
-  Select this option if you know that your system has the ability to
-  redirect interrupts to different CPUs.  Select N here if you're
-  unsure.
+  with a B-step CPU.  Only B3 step CPUs are supported.  You have a B3-step
+  CPU if the "revision" field in /proc/cpuinfo is equal to 4.  If the
+  "revision" field shows a number bigger than 4, you do not have to turn
+  on this option.
 
 Enable IA-64 Machine Check Abort
 CONFIG_IA64_MCA
@@ -23530,6 +23523,15 @@
   Layer) information in /proc/pal.  This contains useful information
   about the processors in your systems, such as cache and TLB sizes
   and the PAL firmware version in use.
+
+  To use this option, you have to check that the "/proc file system
+  support" (CONFIG_PROC_FS) is enabled, too.
+
+/proc/efi/vars support
+CONFIG_EFI_VARS
+  If you say Y here, you are able to get EFI (Extensible Firmware
+  Interface) variable information in /proc/efi/vars.  You may read,
+  write, create, and destroy EFI variables through this interface.
 
   To use this option, you have to check that the "/proc file system
   support" (CONFIG_PROC_FS) is enabled, too.
diff -urN linux-2.4.16/Documentation/kernel-parameters.txt lia64-2.4/Documentation/kernel-parameters.txt
--- linux-2.4.16/Documentation/kernel-parameters.txt	Wed Jun 20 11:21:33 2001
+++ lia64-2.4/Documentation/kernel-parameters.txt	Wed Oct 10 16:44:48 2001
@@ -17,6 +17,7 @@
 	CD	Appropriate CD support is enabled.
 	DEVFS   devfs support is enabled. 
 	DRM	Direct Rendering Management support is enabled. 
+	EFI	EFI Partitioning (GPT) is enabled
 	EIDE	EIDE/ATAPI support is enabled.
 	FB	The frame buffer device is enabled.
 	HW	Appropriate hardware is enabled.
@@ -211,6 +212,9 @@
 	gc_3=		[HW,JOY]
  
 	gdth=		[HW,SCSI]
+
+	gpt             [EFI] Forces disk with valid GPT signature but
+			invalid Protective MBR to be treated as GPT.
 
 	gscd=		[HW,CD]
 
diff -urN linux-2.4.16/Makefile lia64-2.4/Makefile
--- linux-2.4.16/Makefile	Mon Nov 26 11:19:35 2001
+++ lia64-2.4/Makefile	Mon Nov 26 17:13:50 2001
@@ -137,7 +137,8 @@
 	drivers/net/net.o \
 	drivers/media/media.o
 DRIVERS-$(CONFIG_AGP) += drivers/char/agp/agp.o
-DRIVERS-$(CONFIG_DRM) += drivers/char/drm/drm.o
+DRIVERS-$(CONFIG_DRM_NEW) += drivers/char/drm/drm.o
+DRIVERS-$(CONFIG_DRM_OLD) += drivers/char/drm-4.0/drm.o
 DRIVERS-$(CONFIG_NUBUS) += drivers/nubus/nubus.a
 DRIVERS-$(CONFIG_ISDN) += drivers/isdn/isdn.a
 DRIVERS-$(CONFIG_NET_FC) += drivers/net/fc/fc.o
@@ -242,14 +243,14 @@
 
 include arch/$(ARCH)/Makefile
 
-export	CPPFLAGS CFLAGS AFLAGS
+export	CPPFLAGS CFLAGS CFLAGS_KERNEL AFLAGS AFLAGS_KERNEL
 
 export	NETWORKS DRIVERS LIBS HEAD LDFLAGS LINKFLAGS MAKEBOOT ASFLAGS
 
 .S.s:
-	$(CPP) $(AFLAGS) -traditional -o $*.s $<
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -o $*.s $<
 .S.o:
-	$(CC) $(AFLAGS) -traditional -c -o $*.o $<
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -c -o $*.o $<
 
 Version: dummy
 	@rm -f include/linux/compile.h
diff -urN linux-2.4.16/arch/i386/mm/fault.c lia64-2.4/arch/i386/mm/fault.c
--- linux-2.4.16/arch/i386/mm/fault.c	Wed Oct 10 16:31:44 2001
+++ lia64-2.4/arch/i386/mm/fault.c	Wed Oct 24 11:43:30 2001
@@ -27,8 +27,6 @@
 
 extern void die(const char *,struct pt_regs *,long);
 
-extern int console_loglevel;
-
 /*
  * Ugly, ugly, but the goto's result in better assembly..
  */
diff -urN linux-2.4.16/arch/ia64/Makefile lia64-2.4/arch/ia64/Makefile
--- linux-2.4.16/arch/ia64/Makefile	Mon Nov 26 11:18:19 2001
+++ lia64-2.4/arch/ia64/Makefile	Mon Nov 26 17:22:30 2001
@@ -58,7 +58,7 @@
 	CFLAGS		+= -DBRINGUP
         SUBDIRS         :=      arch/$(ARCH)/sn/kernel	\
 				arch/$(ARCH)/sn/io	\
-				arch/$(ARCH)/sn/fprom	\
+				arch/$(ARCH)/sn/fakeprom	\
 				$(SUBDIRS)
         CORE_FILES      :=      arch/$(ARCH)/sn/kernel/sn.o	\
 				arch/$(ARCH)/sn/io/sgiio.o	\
diff -urN linux-2.4.16/arch/ia64/config.in lia64-2.4/arch/ia64/config.in
--- linux-2.4.16/arch/ia64/config.in	Mon Nov 26 11:18:19 2001
+++ lia64-2.4/arch/ia64/config.in	Mon Nov 26 17:16:56 2001
@@ -266,9 +266,7 @@
    bool '  Disable VHPT' CONFIG_DISABLE_VHPT
    bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ
 
-# early printk is currently broken for SMP: the secondary processors get stuck...
-#   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
-
+   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
    bool '  Debug memory allocations' CONFIG_DEBUG_SLAB
    bool '  Spinlock debugging' CONFIG_DEBUG_SPINLOCK
    bool '  Turn on compare-and-exchange bug checking (slow!)' CONFIG_IA64_DEBUG_CMPXCHG
diff -urN linux-2.4.16/arch/ia64/defconfig lia64-2.4/arch/ia64/defconfig
--- linux-2.4.16/arch/ia64/defconfig	Mon Nov 26 11:18:19 2001
+++ lia64-2.4/arch/ia64/defconfig	Mon Nov 26 18:04:47 2001
@@ -299,6 +299,7 @@
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_NCR53C8XX is not set
 # CONFIG_SCSI_SYM53C8XX is not set
 # CONFIG_SCSI_PAS16 is not set
@@ -373,6 +374,7 @@
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_NET_POCKET is not set
 
@@ -554,6 +556,9 @@
 # CONFIG_TUNER_3036 is not set
 # CONFIG_VIDEO_STRADIS is not set
 # CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_ZORAN_BUZ is not set
+# CONFIG_VIDEO_ZORAN_DC10 is not set
+# CONFIG_VIDEO_ZORAN_LML33 is not set
 # CONFIG_VIDEO_ZR36120 is not set
 # CONFIG_VIDEO_MEYE is not set
 
@@ -584,11 +589,15 @@
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
 # CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
 CONFIG_FAT_FS=y
 CONFIG_MSDOS_FS=y
 # CONFIG_UMSDOS_FS is not set
@@ -626,6 +635,7 @@
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_ROOT_NFS is not set
@@ -874,6 +884,7 @@
 CONFIG_IA64_PRINT_HAZARDS=y
 # CONFIG_DISABLE_VHPT is not set
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_IA64_DEBUG_CMPXCHG is not set
diff -urN linux-2.4.16/arch/ia64/ia32/ia32_entry.S lia64-2.4/arch/ia64/ia32/ia32_entry.S
--- linux-2.4.16/arch/ia64/ia32/ia32_entry.S	Mon Nov 26 11:18:19 2001
+++ lia64-2.4/arch/ia64/ia32/ia32_entry.S	Mon Nov 19 20:04:55 2001
@@ -220,7 +220,7 @@
 	data8 sys32_pipe
 	data8 sys32_times
 	data8 sys32_ni_syscall	  /* old prof syscall holder */
-	data8 sys_brk		  /* 45 */
+	data8 sys32_brk		  /* 45 */
 	data8 sys_setgid	/* 16-bit version */
 	data8 sys_getgid	/* 16-bit version */
 	data8 sys32_signal
diff -urN linux-2.4.16/arch/ia64/ia32/sys_ia32.c lia64-2.4/arch/ia64/ia32/sys_ia32.c
--- linux-2.4.16/arch/ia64/ia32/sys_ia32.c	Mon Nov 26 11:18:20 2001
+++ lia64-2.4/arch/ia64/ia32/sys_ia32.c	Mon Nov 19 20:04:55 2001
@@ -82,6 +82,7 @@
 
 /* forward declaration: */
 asmlinkage long sys32_mprotect (unsigned int, unsigned int, int);
+asmlinkage unsigned long sys_brk(unsigned long);
 
 /*
  * Anything that modifies or inspects ia32 user virtual memory must hold this semaphore
@@ -2590,6 +2591,7 @@
 	      default:
 		return -EINVAL;
 	}
+	return -EINVAL;
 }
 
 /*
@@ -3809,6 +3811,19 @@
 		ret = PER_LINUX;
 	return ret;
 }
+
+asmlinkage unsigned long
+sys32_brk(unsigned int brk)
+{
+	unsigned long ret, obrk;
+	struct mm_struct *mm = current->mm;
+
+	obrk = mm->brk;
+	ret = sys_brk(brk);
+	if (ret < obrk)
+		clear_user(ret, PAGE_ALIGN(ret) - ret);
+	return(ret);
+} 
 
 #ifdef	NOTYET  /* UNTESTED FOR IA64 FROM HERE DOWN */
 
diff -urN linux-2.4.16/arch/ia64/kernel/head.S lia64-2.4/arch/ia64/kernel/head.S
--- linux-2.4.16/arch/ia64/kernel/head.S	Mon Nov 26 11:18:20 2001
+++ lia64-2.4/arch/ia64/kernel/head.S	Mon Nov 12 11:44:45 2001
@@ -180,10 +180,12 @@
 	.rodata
 alive_msg:
 	stringz "I'm alive and well\n"
+alive_msg_end:
 	.previous
 
 	alloc r2=ar.pfs,0,0,2,0
 	movl out0=alive_msg
+	movl out1=alive_msg_end-alive_msg-1
 	;;
 	br.call.sptk.many rp=early_printk
 1:	// force new bundle
diff -urN linux-2.4.16/arch/ia64/kernel/iosapic.c lia64-2.4/arch/ia64/kernel/iosapic.c
--- linux-2.4.16/arch/ia64/kernel/iosapic.c	Mon Nov 26 11:18:20 2001
+++ lia64-2.4/arch/ia64/kernel/iosapic.c	Mon Nov 26 16:52:11 2001
@@ -565,17 +565,7 @@
 		       pci_irq.route[i].bus, pci_irq.route[i].pci_id>>16, pci_irq.route[i].pin,
 		       iosapic_irq[vector].base_irq + iosapic_irq[vector].pin, vector);
 # endif
-		irq_type = &irq_type_iosapic_level;
-		idesc = irq_desc(vector);
-		if (idesc->handler != irq_type){
-			if (idesc->handler != &no_irq_type)
-				printk("iosapic_init: changing vector 0x%02x from %s to %s\n",
-				       vector, idesc->handler->typename, irq_type->typename);
-			idesc->handler = irq_type;
-		}
 
-		/* program the IOSAPIC routing table: */
-		set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 	}
 }
 
@@ -585,6 +575,8 @@
 	struct	pci_dev	*dev;
 	unsigned char pin;
 	int vector;
+	struct hw_interrupt_type *irq_type;
+	irq_desc_t *idesc;
 
 	if (phase != 1)
 		return;
@@ -611,19 +603,28 @@
 				if (vector >= 0)
 					printk(KERN_WARNING
 					       "PCI: using PPB(B%d,I%d,P%d) to get vector %02x\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
+					       dev->bus->number, PCI_SLOT(dev->devfn),
 					       pin, vector);
 				else
 					printk(KERN_WARNING
-					       "PCI: Couldn't map irq for (B%d,I%d,P%d)o\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
-					       pin);
+					       "PCI: Couldn't map irq for (B%d,I%d,P%d)\n",
+					       dev->bus->number, PCI_SLOT(dev->devfn), pin);
 			}
 			if (vector >= 0) {
 				printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> 0x%02x\n",
 				       dev->bus->number, PCI_SLOT(dev->devfn), pin, vector);
 				dev->irq = vector;
 
+				irq_type = &irq_type_iosapic_level;
+				idesc = irq_desc(vector);
+				if (idesc->handler != irq_type){
+					if (idesc->handler != &no_irq_type)
+						printk("iosapic_init: changing vector 0x%02x from "
+						       "%s to %s\n", vector,
+						       idesc->handler->typename,
+						       irq_type->typename);
+					idesc->handler = irq_type;
+				}
 #ifdef CONFIG_SMP
 				/*
 				 * For platforms that do not support interrupt redirect
@@ -638,7 +639,16 @@
 					cpu_index++;
 					if (cpu_index >= smp_num_cpus)
 						cpu_index = 0;
+				} else {
+					/*
+					 * Direct the interrupt vector to the current cpu,
+					 * platform redirection will distribute them.
+					 */
+					set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 				}
+#else
+				/* direct the interrupt vector to the running cpu id */
+				set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 #endif
 			}
 		}
diff -urN linux-2.4.16/arch/ia64/kernel/process.c lia64-2.4/arch/ia64/kernel/process.c
--- linux-2.4.16/arch/ia64/kernel/process.c	Mon Nov 26 11:18:21 2001
+++ lia64-2.4/arch/ia64/kernel/process.c	Mon Nov 26 17:23:21 2001
@@ -28,6 +28,10 @@
 #include <asm/unwind.h>
 #include <asm/user.h>
 
+#ifdef CONFIG_IA64_SGI_SN
+#include <asm/sn/idle.h>
+#endif
+
 static void
 do_show_stack (struct unw_frame_info *info, void *arg)
 {
@@ -46,6 +50,15 @@
 }
 
 void
+show_trace_task (struct task_struct *task)
+{
+	struct unw_frame_info info;
+
+	unw_init_from_blocked_task(&info, task);
+	do_show_stack(&info, 0);
+}
+
+void
 show_stack (struct task_struct *task)
 {
 	if (!task)
@@ -122,8 +135,18 @@
 		if (!current->need_resched)
 			min_xtp();
 #endif
-		while (!current->need_resched)
+
+		while (!current->need_resched) {
+#ifdef CONFIG_IA64_SGI_SN
+			snidle();
+#endif
 			continue;
+		}
+
+#ifdef CONFIG_IA64_SGI_SN
+		snidleoff();
+#endif
+
 #ifdef CONFIG_SMP
 		normal_xtp();
 #endif
diff -urN linux-2.4.16/arch/ia64/kernel/setup.c lia64-2.4/arch/ia64/kernel/setup.c
--- linux-2.4.16/arch/ia64/kernel/setup.c	Mon Nov 26 11:18:24 2001
+++ lia64-2.4/arch/ia64/kernel/setup.c	Mon Nov 26 16:34:47 2001
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1998-2001 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998, 1999, 2001 Stephane Eranian <eranian@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
@@ -147,6 +147,10 @@
 }
 
 
+/*
+ * Find a place to put the bootmap and return its starting address in bootmap_start.
+ * This address must be page-aligned.
+ */
 static int
 find_bootmap_location (unsigned long start, unsigned long end, void *arg)
 {
@@ -165,7 +169,7 @@
 
 	for (i = 0; i < num_rsvd_regions; i++) {
 		range_start = MAX(start, free_start);
-		range_end   = MIN(end, rsvd_region[i].start);
+		range_end   = MIN(end, rsvd_region[i].start & PAGE_MASK);
 
 		if (range_end <= range_start) continue;	/* skip over empty range */
 
@@ -177,7 +181,7 @@
 		/* nothing more available in this segment */
 		if (range_end == end) return 0;
 
-		free_start = rsvd_region[i].end;
+		free_start = PAGE_ALIGN(rsvd_region[i].end);
 	}
 	return 0;
 }
@@ -306,6 +310,10 @@
 	/* process SAL system table: */
 	ia64_sal_init(efi.sal_systab);
 
+#ifdef CONFIG_IA64_GENERIC
+	machvec_init(acpi_get_sysname());
+#endif
+
 	/*
 	 *  Set `iobase' to the appropriate address in region 6
 	 *    (uncached access range)
@@ -332,10 +340,6 @@
 
 	cpu_init();	/* initialize the bootstrap CPU */
 
-#ifdef CONFIG_IA64_GENERIC
-	machvec_init(acpi_get_sysname());
-#endif
-
 	if (efi.acpi20) {
 		/* Parse the ACPI 2.0 tables */
 		acpi20_parse(efi.acpi20);
@@ -534,7 +538,7 @@
 				= alloc_bootmem_pages_node(NODE_DATA(numa_node_id()),
 							   sizeof(struct cpuinfo_ia64));
 		for (cpu = 1; cpu < NR_CPUS; ++cpu)
-			memcpy(my_cpu_data->cpu_data[cpu]->cpu_data_ptrs,
+			memcpy(my_cpu_data->cpu_data[cpu]->cpu_data,
 			       my_cpu_data->cpu_data, sizeof(my_cpu_data->cpu_data));
 	} else {
 		order = get_order(sizeof(struct cpuinfo_ia64));
@@ -616,4 +620,6 @@
 		num_phys_stacked = 96;
 	}
 	local_cpu_data->phys_stacked_size_p8 = num_phys_stacked*8 + 8;
+
+	platform_cpu_init();
 }
diff -urN linux-2.4.16/arch/ia64/kernel/smpboot.c lia64-2.4/arch/ia64/kernel/smpboot.c
--- linux-2.4.16/arch/ia64/kernel/smpboot.c	Mon Nov 26 11:18:24 2001
+++ lia64-2.4/arch/ia64/kernel/smpboot.c	Mon Nov 26 12:06:16 2001
@@ -416,9 +416,9 @@
 	if (!idle)
 		panic("No idle process for CPU %d", cpu);
 
-	idle->processor = cpu;
+	task_set_cpu(idle, cpu);	/* we schedule the first task manually */
+
 	ia64_cpu_to_sapicid[cpu] = sapicid;
-	idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */
 
 	del_from_runqueue(idle);
 	unhash_process(idle);
diff -urN linux-2.4.16/arch/ia64/lib/swiotlb.c lia64-2.4/arch/ia64/lib/swiotlb.c
--- linux-2.4.16/arch/ia64/lib/swiotlb.c	Mon Nov 26 11:18:25 2001
+++ lia64-2.4/arch/ia64/lib/swiotlb.c	Mon Nov  5 22:15:32 2001
@@ -27,10 +27,6 @@
 #define ALIGN(val, align) ((unsigned long)	\
 	(((unsigned long) (val) + ((align) - 1)) & ~((align) - 1)))
 
-#define SG_ENT_VIRT_ADDRESS(sg)	((sg)->address ? (sg)->address			\
-				 : page_address((sg)->page) + (sg)->offset)
-#define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
-
 /*
  * log of the size of each IO TLB slab.  The number of slabs is command line controllable.
  */
@@ -396,20 +392,15 @@
 int
 swiotlb_map_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
 {
-	void *addr;
 	int i;
 
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++) {
-		sg->orig_address = SG_ENT_VIRT_ADDRESS(sg);
-		if ((SG_ENT_PHYS_ADDRESS(sg) & ~hwdev->dma_mask) != 0) {
-			addr = map_single(hwdev, sg->address, sg->length, direction);
-			if (sg->address)
-				sg->address = addr;
-			else
-				sg->page = virt_to_page(addr);
+		sg->page = sg->address;
+		if ((virt_to_phys(sg->address) & ~hwdev->dma_mask) != 0) {
+			sg->address = map_single(hwdev, sg->address, sg->length, direction);
 		}
 	}
 	return nelems;
@@ -428,12 +419,9 @@
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++)
-		if (sg->orig_address != SG_ENT_VIRT_ADDRESS(sg)) {
-			unmap_single(hwdev, SG_ENT_VIRT_ADDRESS(sg), sg->length, direction);
-			if (sg->address)
-				sg->address = sg->orig_address;
-			else
-				sg->page = virt_to_page(sg->orig_address);
+		if (sg->page != sg->address) {
+			unmap_single(hwdev, sg->address, sg->length, direction);
+			sg->address = sg->page;
 		} else if (direction == PCI_DMA_FROMDEVICE)
 			mark_clean(sg->address, sg->length);
 }
@@ -454,14 +442,14 @@
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++)
-		if (sg->orig_address != SG_ENT_VIRT_ADDRESS(sg))
-			sync_single(hwdev, SG_ENT_VIRT_ADDRESS(sg), sg->length, direction);
+		if (sg->page != sg->address)
+			sync_single(hwdev, sg->address, sg->length, direction);
 }
 
 unsigned long
 swiotlb_dma_address (struct scatterlist *sg)
 {
-	return SG_ENT_PHYS_ADDRESS(sg);
+	return virt_to_phys(sg->address);
 }
 
 EXPORT_SYMBOL(swiotlb_init);
diff -urN linux-2.4.16/arch/ia64/sn/Makefile lia64-2.4/arch/ia64/sn/Makefile
--- linux-2.4.16/arch/ia64/sn/Makefile	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/Makefile	Wed Dec 31 16:00:00 1969
@@ -1,19 +0,0 @@
-#
-# ia64/sn/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-all: sn.a
-
-O_TARGET        = sn.a
-obj-y           = sn1/sn1.a
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,777 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,772 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-dig-mp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-dig-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-dig-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-dig-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-dig-sp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-dig-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-dig-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-dig-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-generic-mp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-generic-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-generic-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-generic-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-generic-sp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-generic-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-generic-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-generic-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-hp-sp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-hp-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-hp-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-hp-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,334 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+CONFIG_IA64_HP_SIM=y
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Simulated drivers
+#
+CONFIG_SIMETH=y
+CONFIG_SIM_SERIAL=y
+CONFIG_SCSI_SIM=y
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-prom-medusa lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-prom-medusa
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-prom-medusa	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-prom-medusa	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,529 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,738 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-sp lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn1/defconfig-sn1-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn1/defconfig-sn1-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-dig-numa lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-dig-numa
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-dig-numa	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-dig-numa	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_NUMA=y
+CONFIG_DISCONTIGMEM=y
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-mp lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-mp
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-mp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-mp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,732 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+# CONFIG_SERIAL_SGI_L1_PROTOCOL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,537 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -urN linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-sp lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-sp
--- linux-2.4.16/arch/ia64/sn/configs/sn2/defconfig-sn2-sp	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/configs/sn2/defconfig-sn2-sp	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/Makefile lia64-2.4/arch/ia64/sn/fakeprom/Makefile
--- linux-2.4.16/arch/ia64/sn/fakeprom/Makefile	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/Makefile	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,30 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+#  Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+#
+
+TOPDIR=../../../..
+HPATH           = $(TOPDIR)/include
+
+LIB     = ../../lib/lib.a
+
+OBJ=fpromasm.o main.o  fw-emu.o fpmem.o klgraph_init.o
+obj-y=fprom
+
+fprom: $(OBJ)
+	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
+
+.S.o:
+	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+.c.o:
+	$(CC)  $(CFLAGS) $(CFLAGS_KERNEL) -c -o $*.o $<
+
+clean:
+	rm -f *.o fprom
+
+
+include $(TOPDIR)/Rules.make
+
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/README lia64-2.4/arch/ia64/sn/fakeprom/README
--- linux-2.4.16/arch/ia64/sn/fakeprom/README	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/README	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,85 @@
+This directory contains the files required to build
+the fake PROM image that is currently being used to
+boot IA64 kernels running under the SGI Medusa kernel.
+
+The FPROM currently provides the following functions:
+
+	- PAL emulation for all PAL calls we've made so far.
+	- SAL emulation for all SAL calls we've made so far.
+	- EFI emulation for all EFI calls we've made so far.
+	- builds the "ia64_bootparam" structure that is
+	  passed to the kernel from SAL. This structure 
+	  shows the cpu & memory configurations.
+	- supports medusa boottime options for changing
+	  the number of cpus present
+	- supports medusa boottime options for changing
+	  the memory configuration.
+
+
+
+At some point, this fake PROM will be replaced by the
+real PROM.
+
+
+
+
+To build a fake PROM, cd to this directory & type:
+
+	make
+
+This will (or should) build a fake PROM named "fprom".
+
+
+
+
+Use this fprom image when booting the Medusa simulator. The
+control file used to boot Medusa should include the 
+following lines:
+
+	load fprom
+	load vmlinux
+	sr pc 0x100000
+	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
+
+NOTE: There is a script "runsim" in this directory that can be used to
+simplify setting up an environment for running under Medusa.
+
+
+
+
+The following parameters may be passed to the fake PROM to
+control the PAL/SAL/EFI parameters passed to the kernel:
+
+	GR[8] = # of cpus
+	GR[9] = address of primary entry point into the kernel
+	GR[20] = memory configuration for node 0
+	GR[21] = memory configuration for node 1
+	GR[22] = memory configuration for node 2
+	GR[23] = memory configuration for node 3
+
+
+Registers GR[20] - GR[23] contain information to specify the
+amount of memory present on nodes 0-3.
+
+  - if nothing is specified (all registers are 0), the configuration
+    defaults to 8 MB on node 0.
+
+  - a mem config entry for node N is passed in GR[20+N]
+
+  - a mem config entry consists of 8 hex digits. Each digit gives the
+    amount of physical memory available on the node starting at
+    1GB*<dn>, where dn is the digit number. The amount of memory
+    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
+
+    SN1 doesnt support dimms this small but small memory systems 
+    boot faster on Medusa.
+
+
+
+An example helps a lot. The following specifies that node 0 has
+physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
+64MB starting at address 0 of the node which is 8GB.
+
+      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
+      gr[21] = 0x4            # 8GB to 8GB+64MB
+
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/fpmem.c lia64-2.4/arch/ia64/sn/fakeprom/fpmem.c
--- linux-2.4.16/arch/ia64/sn/fakeprom/fpmem.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/fpmem.c	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,256 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+/*
+ * FPROM EFI memory descriptor build routines
+ *
+ * 	- Routines to build the EFI memory descriptor map
+ * 	- Should also be usable by the SGI SN1 prom to convert
+ * 	  klconfig to efi_memmap
+ */
+
+#include <linux/config.h>
+#include <asm/efi.h>
+#include "fpmem.h"
+
+/*
+ * args points to a layout in memory like this
+ *
+ *		32 bit		32 bit
+ *
+ * 		numnodes	numcpus
+ *
+ *		16 bit   16 bit		   32 bit
+ *		nasid0	cpuconf		membankdesc0
+ *		nasid1	cpuconf		membankdesc1
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ */
+
+sn_memmap_t	*sn_memmap ;
+sn_config_t	*sn_config ;
+
+/*
+ * There is a hole in the node 0 address space. Dont put it
+ * in the memory map
+ */
+#define NODE0_HOLE_SIZE         (20*MB)
+#define NODE0_HOLE_END          (4UL*GB)
+
+#define	MB			(1024*1024)
+#define GB			(1024*MB)
+#define KERNEL_SIZE		(4*MB)
+#define PROMRESERVED_SIZE	(1*MB)
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<33L) | (long)_x)
+#define MD_BANK_SHFT 30
+#else
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<38L) | (long)_x | 0x3000000000UL)
+#define MD_BANK_SHFT 34
+#endif
+
+/*
+ * For SN, this may not take an arg and gets the numnodes from 
+ * the prom variable or by traversing klcfg or promcfg
+ */
+int
+GetNumNodes(void)
+{
+	return sn_config->nodes;
+}
+
+int
+GetNumCpus(void)
+{
+	return sn_config->cpus;
+}
+
+/* For SN1, get the index th nasid */
+
+int
+GetNasid(int index)
+{
+	return sn_memmap[index].nasid ;
+}
+
+node_memmap_t
+GetMemBankInfo(int index)
+{
+	return sn_memmap[index].node_memmap ;
+}
+
+int
+IsCpuPresent(int cnode, int cpu)
+{
+	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
+}
+
+
+/*
+ * Made this into an explicit case statement so that
+ * we can assign specific properties to banks like bank0
+ * actually disabled etc.
+ */
+
+#ifdef CONFIG_IA64_SGI_SN1
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return nmemmap.b0;
+		case 1:return nmemmap.b1;
+		case 2:return nmemmap.b2;
+		case 3:return nmemmap.b3;
+		case 4:return nmemmap.b4;
+		case 5:return nmemmap.b5;
+		case 6:return nmemmap.b6;
+		case 7:return nmemmap.b7;
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+        switch (index) {
+                case 0:
+                case 1:return nmemmap.b01size;
+                case 2:
+                case 3:return nmemmap.b23size;
+                case 4:
+                case 5:return nmemmap.b45size;
+                case 6:
+                case 7:return nmemmap.b67size;
+                default:return -1 ;
+        }
+}
+
+#else
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return nmemmap.ena0;
+		case 1:return nmemmap.ena1;
+		case 2:return nmemmap.ena2;
+		case 3:return nmemmap.ena3;
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+        switch (index) {
+                case 0:return (long)nmemmap.b0size + nmemmap.b0dou;
+                case 1:return (long)nmemmap.b1size + nmemmap.b1dou;
+                case 2:return (long)nmemmap.b2size + nmemmap.b2dou;
+                case 3:return (long)nmemmap.b3size + nmemmap.b3dou;
+                default:return -1 ;
+        }
+}
+
+#endif
+
+void
+build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
+{
+        md->type = type;
+        md->phys_addr = paddr;
+        md->virt_addr = 0;
+        md->num_pages = numbytes >> 12;
+        md->attribute = EFI_MEMORY_WB;
+}
+
+int
+build_efi_memmap(void *md, int mdsize)
+{
+	int		numnodes = GetNumNodes() ;
+	int		cnode,bank ;
+	int		nasid ;
+	node_memmap_t	membank_info ;
+	int		bsize;
+	int		count = 0 ;
+	long		paddr, hole, numbytes;
+
+
+	for (cnode=0;cnode<numnodes;cnode++) {
+		nasid = GetNasid(cnode) ;
+		membank_info = GetMemBankInfo(cnode) ;
+		for (bank=0;bank<PLAT_CLUMPS_PER_NODE;bank++) {
+			if (IsBankPresent(bank, membank_info)) {
+				bsize = GetBankSize(bank, membank_info) ;
+                                paddr = PHYS_ADDRESS(nasid, (long)bank<<MD_BANK_SHFT);
+                                numbytes = BankSizeBytes(bsize);
+#ifdef CONFIG_IA64_SGI_SN2
+				numbytes = numbytes * 31 / 32;
+#endif
+
+                                /*
+                                 * Check for the node 0 hole. Since banks cant
+                                 * span the hole, we only need to check if the end of
+                                 * the range is the end of the hole.
+                                 */
+                                if (paddr+numbytes == NODE0_HOLE_END)
+                                        numbytes -= NODE0_HOLE_SIZE;
+                                /*
+                                 * UGLY hack - we must skip overr the kernel and
+                                 * PROM runtime services but we dont exactly where it is.
+                                 * So lets just reserve:
+				 *	node 0
+				 *		0-1MB for PAL
+				 *		1-4MB for SAL
+				 *	node 1-N
+				 *		0-1 for SAL
+                                 */
+                                if (bank == 0) {
+					if (cnode == 0) {
+						hole = 1*1024*1024;
+						build_mem_desc(md, EFI_PAL_CODE, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+						hole = 3*1024*1024;
+						build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					} else {
+						hole = PROMRESERVED_SIZE;
+                                        	build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					}
+                                }
+                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
+
+			        md += mdsize ;
+			        count++ ;
+			}
+		}
+	}
+	return count ;
+}
+
+void
+build_init(unsigned long args)
+{
+	sn_config = (sn_config_t *) (args);	
+	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
+						/* init to klconfig start */
+}
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/fpmem.h lia64-2.4/arch/ia64/sn/fakeprom/fpmem.h
--- linux-2.4.16/arch/ia64/sn/fakeprom/fpmem.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/fpmem.h	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,98 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Structure of the mem config of the node as a SN1 MI reg
+ * Medusa supports this reg config.
+ *
+ * BankSize nibble to bank size mapping
+ *
+ *      1 - 64 MB
+ *      2 - 128 MB
+ *      3 - 256 MB
+ *      4 - 512 MB
+ *      5 - 1024 MB (1GB)
+ */
+
+#define MBSHIFT				20
+
+#ifdef CONFIG_IA64_SGI_SN1
+typedef struct node_memmap_s
+{
+        unsigned int    b0      :1,     /* 0 bank 0 present */
+                        b1      :1,     /* 1 bank 1 present */
+                        r01     :2,     /* 2-3 reserved */
+                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
+                        b2      :1,     /* 8 bank 2 present */
+                        b3      :1,     /* 9 bank 3 present */
+                        r23     :2,     /* 10-11 reserved */
+                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
+                        b4      :1,     /* 16 bank 4 present */
+                        b5      :1,     /* 17 bank 5 present */
+                        r45     :2,     /* 18-19 reserved */
+                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
+                        b6      :1,     /* 24 bank 6 present */
+                        b7      :1,     /* 25 bank 7 present */
+                        r67     :2,     /* 26-27 reserved */
+                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
+} node_memmap_t ;
+
+/* Support the medusa hack for 8M/16M/32M nodes */
+#define SN1_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
+                                         (1<<((bsize-9)+MBSHIFT)))
+#else
+typedef struct node_memmap_s
+{
+        unsigned int    b0size  :3,     /* 0-2   bank 0 size */
+                        b0dou   :1,     /* 3     bank 0 is 2-sided */
+                        ena0    :1,     /* 4     bank 0 enabled */
+                        r0      :3,     /* 5-7   reserved */
+        		b1size  :3,     /* 8-10  bank 1 size */
+                        b1dou   :1,     /* 11    bank 1 is 2-sided */
+                        ena1    :1,     /* 12    bank 1 enabled */
+                        r1      :3,     /* 13-15 reserved */
+        		b2size  :3,     /* 16-18 bank 2 size */
+                        b2dou   :1,     /* 19    bank 1 is 2-sided */
+                        ena2    :1,     /* 20    bank 2 enabled */
+                        r2      :3,     /* 21-23 reserved */
+        		b3size  :3,     /* 24-26 bank 3 size */
+                        b3dou   :1,     /* 27    bank 3 is 2-sided */
+                        ena3    :1,     /* 28    bank 3 enabled */
+                        r3      :3;     /* 29-31 reserved */
+} node_memmap_t ;
+
+#define SN2_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankSizeBytes(bsize)            (1UL<<((bsize)+SN2_BANK_SIZE_SHIFT))
+#endif
+
+typedef struct sn_memmap_s
+{
+	short		nasid ;
+	short		cpuconfig;
+	node_memmap_t 	node_memmap ;
+} sn_memmap_t ;
+
+typedef struct sn_config_s
+{
+	int		cpus;
+	int		nodes;
+	sn_memmap_t	memmap[1];		/* start of array */
+} sn_config_t;
+
+
+
+extern void build_init(unsigned long);
+extern int build_efi_memmap(void *, int);
+extern int GetNumNodes(void);
+extern int GetNumCpus(void);
+extern int IsCpuPresent(int, int);
+extern int GetNasid(int);
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/fprom.lds lia64-2.4/arch/ia64/sn/fakeprom/fprom.lds
--- linux-2.4.16/arch/ia64/sn/fakeprom/fprom.lds	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/fprom.lds	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,96 @@
+
+OUTPUT_FORMAT("elf64-ia64-little")
+OUTPUT_ARCH(ia64)
+ENTRY(_start)
+SECTIONS
+{
+  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
+
+  . = (0x000000000000000  + 0x100000) ;
+
+  _text = .;
+  .text : AT(ADDR(.text) - 0x0000000000000000 )
+    {
+	*(__ivt_section)
+	/* these are not really text pages, but the zero page needs to be in a fixed location: */
+	*(__special_page_section)
+	__start_gate_section = .;
+	*(__gate_section)
+	__stop_gate_section = .;
+	*(.text)
+    }
+
+  /* Global data */
+  _data = .;
+
+  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
+	{ *(.rodata) *(.rodata.*) }
+  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
+	{ *(.opd) }
+  .data : AT(ADDR(.data) - 0x0000000000000000 )
+	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
+
+  __gp = ALIGN (8) + 0x200000;
+
+  .got : AT(ADDR(.got) - 0x0000000000000000 )
+	{ *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
+	{ *(.sdata) }
+  _edata  =  .;
+  _bss = .;
+  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
+	{ *(.sbss) *(.scommon) }
+  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
+	{ *(.bss) *(COMMON) }
+  . = ALIGN(64 / 8);
+  _end = .;
+
+  /* Sections to be discarded */
+  /DISCARD/ : {
+	*(.text.exit)
+	*(.data.exit)
+	}
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+  /* Discard them for now since Intel SoftSDV cannot handle them.
+  .comment 0 : { *(.comment) }
+  .note 0 : { *(.note) }
+  */
+  /DISCARD/ : { *(.comment) }
+  /DISCARD/ : { *(.note) }
+}
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/fpromasm.S lia64-2.4/arch/ia64/sn/fakeprom/fpromasm.S
--- linux-2.4.16/arch/ia64/sn/fakeprom/fpromasm.S	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/fpromasm.S	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,399 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *   (Code copied from or=ther files)
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#define __ASSEMBLY__ 1
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+/*
+ * This file contains additional set up code that is needed to get going on
+ * Medusa.  This code should disappear once real hw is available.
+ *
+ * On entry to this routine, the following register values are assumed:
+ *
+ *	gr[8]	- BSP cpu
+ *	pr[9]	- kernel entry address
+ *	pr[10]	- cpu number on the node
+ *
+ * NOTE:
+ *   This FPROM may be loaded/executed at an address different from the
+ *   address that it was linked at. The FPROM is linked to run on node 0
+ *   at address 0x100000. If the code in loaded into another node, it
+ *   must be loaded at offset 0x100000 of the node. In addition, the
+ *   FPROM does the following things:
+ *		- determine the base address of the node it is loaded on
+ *		- add the node base to _gp.
+ *		- add the node base to all addresses derived from "movl" 
+ *		  instructions. (I couldnt get GPREL addressing to work)
+ *		  (maybe newer versions of the tools will support this)
+ *		- scan the .got section and add the node base to all
+ *		  pointers in this section.
+ *		- add the node base to all physical addresses in the
+ *		  SAL/PAL/EFI table built by the C code. (This is done
+ *		  in the C code - not here)
+ *		- add the node base to the TLB entries for vmlinux
+ */
+
+#define KERNEL_BASE	0xe000000000000000
+#define BOOT_PARAM_ADDR 0x40000
+
+
+/* 
+ * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
+ * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
+ * IOSPEC_BASE value
+ */
+#define IOPB_PA		0x00000a0000000000 /* inv swizzle IOSPEC_BASE */
+
+#define RR_RID		8
+
+
+
+// ====================================================================================	
+        .text
+        .align 16
+	.global _start
+	.proc _start
+_start:
+
+// Setup psr and rse for system init
+	mov		psr.l = r0;;
+	srlz.d;;
+	invala
+	mov		ar.rsc = r0;;
+	loadrs
+	;;
+
+// Isolate node number we are running on.
+	mov		r6 = ip;;
+#ifdef CONFIG_IA64_SGI_SN1
+	shr		r5 = r6,33;;			// r5 = node number
+	shl		r6 = r5,33			// r6 = base memory address of node
+#else
+	shr		r5 = r6,38			// r5 = node number
+	dep		r6 = 0,r6,0,36			// r6 = base memory address of node
+
+#endif
+
+
+// Set & relocate gp.
+	movl		r1= __gp;;			// Add base memory address
+	or 		r1 = r1,r6			// Relocate to boot node
+
+// Lets figure out who we are & put it in the LID register.
+#ifdef CONFIG_IA64_SGI_SN2
+// On SN2, we (currently) pass the cpu number in r10 at boot
+	and		r25=3,r10;;
+	movl		r16=0x8000008110000400		// Allow IPIs
+	mov		r17=-1;;
+	st8		[r16]=r17
+	movl		r16=0x8000008110060580;;	// SHUB_ID
+	ld8		r27=[r16];;
+	extr.u		r27=r27,32,11;;
+	shl 		r26=r25,28;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,16;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#else
+// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
+// This identifies the cpu on the node. 
+// Merge the cpu number with the NASID to generate the LID.
+	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
+	ld8 		r25=[r24]			// Fetch PI_SELF
+	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
+	ld8 		r27=[r27];;
+	extr.u		r27=r27,32,8;;
+	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,24;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#endif
+	mov 		cr.lid=r26			// Now put in in the LID register
+
+	movl		r2=FPSR_DEFAULT;;
+	mov 		ar.fpsr=r2
+	movl		sp = bootstacke-16;;
+	or 		sp = sp,r6			// Relocate to boot node			
+
+// Save the NASID that we are loaded on.
+	movl		r2=base_nasid;;			// Save base_nasid for C code
+	or 		r2 = r2,r6;;			// Relocate to boot node
+  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
+
+// Save the kernel entry address. It is passed in r9 on one of
+// the cpus.
+	movl		r2=bsp_entry_pc
+	cmp.ne		p6,p0=r9,r0;;
+	or 		r2 = r2,r6;;			// Relocate to boot node
+(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
+
+
+// The following can ONLY be done by 1 cpu. Lets set a lock - the
+// cpu that gets it does the initilization. The rest just spin waiting
+// til initilization is complete.
+	movl		r22 = initlock;;
+	or		r22 = r22,r6			// Relocate to boot node
+	mov		r23 = 1;;
+	xchg8		r23 = [r22],r23;;
+	cmp.eq 		p6,p0 = 0,r23
+(p6)	br.cond.spnt.few init
+1:	ld4		r23 = [r22];;
+	cmp.eq		p6,p0 = 1,r23
+(p6)	br.cond.sptk	1b
+	br		initx
+
+// Add base address of node memory to each pointer in the .got section.
+init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
+	or		r16 = r16,r6;;			// Relocate to boot node
+1: 	ld8		r17 = [r16];;
+	cmp.eq		p6,p7=0,r17
+(p6)	br.cond.sptk.few.clr 2f;;
+	or		r17 = r17,r6;;			// Relocate to boot node
+	st8		[r16] = r17,8
+	br		1b
+2:
+	mov		r23 = 2;;			// All done, release the spinning cpus
+	st4		[r22] = r23
+initx:
+
+//
+//	I/O-port space base address:
+//
+	movl		r2 = IOPB_PA;;
+	mov		ar.k0 = r2
+
+
+// Now call main & pass it the current LID value.
+	alloc 		r0=ar.pfs,0,0,2,0
+	mov    		r32=r26
+	mov   		r33=r8;;
+	br.call.sptk.few rp=fmain
+	
+// Initialize Region Registers
+//
+        mov             r10 = r0
+        mov             r2 = (13<<2)
+        mov             r3 = r0;;
+1:      cmp4.gtu        p6,p7 = 7, r3
+        dep             r10 = r3, r10, 61, 3
+        dep             r2 = r3, r2, RR_RID, 4;;
+(p7)    dep             r2 = 0, r2, 0, 1;;
+(p6)    dep             r2 = -1, r2, 0, 1;;
+        mov             rr[r10] = r2
+        add             r3 = 1, r3;;
+        srlz.d;;
+        cmp4.gtu        p6,p0 = 8, r3
+(p6)    br.cond.sptk.few.clr 1b
+
+//
+// Return value indicates if we are the BSP or AP.
+// 	   1 = BSP, 0 = AP
+	mov             cr.tpr=r0;;
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.spnt	slave
+
+//
+// Go to kernel C startup routines
+//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//	This is the only way to set them.
+
+	movl		r28=BOOT_PARAM_ADDR
+	movl		r2=bsp_entry_pc;;
+	or 		r28 = r28,r6;;			// Relocate to boot node
+	or 		r2 = r2,r6;;			// Relocate to boot node
+	ld8		r2=[r2];;
+	or		r2=r2,r6;;
+	dep		r2=0,r2,61,3;;			// convert to phys mode
+
+//
+// Turn on address translation, interrupt collection, psr.ed, protection key.
+// Interrupts (PSR.i) are still off here.
+//
+
+        movl            r3 = (  IA64_PSR_BN | \
+                                IA64_PSR_AC | \
+                                IA64_PSR_DB | \
+                                IA64_PSR_DA | \
+                                IA64_PSR_IC   \
+                             )
+        ;;
+        mov             cr.ipsr = r3
+
+//
+// Go to kernel C startup routines
+//      Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//      This is the only way to set them.
+
+	mov		r8=r28;;
+	bsw.1		;;
+	mov		r28=r8;;
+	bsw.0		;;
+        mov             cr.iip = r2
+        srlz.d;;
+        rfi;;
+
+	.endp		_start
+
+
+
+// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
+// the place ap_entry points. No initialization is necessary - the kernel makes no
+// assumptions about state on this entry.
+//	Note: should verify that the interrupt we got was really the ap_wakeup
+//	      interrupt but this should not be an issue on medusa
+slave:
+	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
+	mov		r8=cr.irr0;;			// Check for interrupt pending.
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.sptk	slave;;
+
+	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
+	srlz.d;;
+	mov		cr.eoi=r0;;			// must write eoi to clear
+	movl		r8=ap_entry;;			// now jump to kernel entry
+	or 		r8 = r8,r6;;			// Relocate to boot node
+	ld8		r9=[r8],8;;
+	ld8		r1=[r8]
+	mov		b0=r9;;
+	br		b0
+
+// Here is the kernel stack used for the fake PROM
+	.bss
+	.align		16384
+bootstack:
+	.skip		16384
+bootstacke:
+initlock:
+	data4
+
+
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////
+// This code emulates the PAL. Only essential interfaces are emulated.
+
+
+	.text
+	.global	pal_emulator
+	.proc	pal_emulator
+pal_emulator:
+	mov	r8=-1
+
+	mov	r9=256
+	;;
+	cmp.gtu p6,p7=r9,r28		/* r28 <= 255? */
+(p6)	br.cond.sptk.few static
+	;;
+	mov	r9=512
+	;;
+	cmp.gtu p6,p7=r9,r28
+(p6)	br.cond.sptk.few stacked
+	;;
+
+static:	cmp.eq	p6,p7=6,r28		/* PAL_PTCE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=0x100000000			/* tc.base */
+	movl	r10=0x0000000200000003		/* count[0], count[1] */
+	movl	r11=0x1000000000002000		/* stride[0], stride[1] */
+	;;
+
+1:	cmp.eq	p6,p7=14,r28		/* PAL_FREQ_RATIOS */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9 =0x100000064			/* proc_ratio (1/100) */
+	movl	r10=0x100000100			/* bus_ratio<<32 (1/256) */
+	movl	r11=0x10000000a			/* itc_ratio<<32 (1/100) */
+	;;
+
+1:	cmp.eq	p6,p7=8,r28		/* PAL_VM_SUMMARY */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+#ifdef CONFIG_IA64_SGI_SN1
+	movl	r9=0x0203083001151059
+	movl	r10=0x1232
+#else
+	movl	r9=0x0203083001151065
+	movl	r10=0x183f
+#endif
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x60
+	movl	r10=0x0
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=15,r28		/* PAL_PERF_MON_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x08122004
+	movl	r10=0x0
+	movl	r11=0
+	mov	r2=ar.lc
+	mov	r3=16;;
+	mov	ar.lc=r3
+	mov	r3=r29;;
+5:	st8	[r3]=r0,8
+	br.cloop.sptk.few 5b;;
+	mov	ar.lc=r2
+	mov	r3=r29
+	movl	r2=0x1fff;;			/* PMC regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x3ffff;;			/* PMD regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0xf0;;			/* cycle regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x10;;			/* retired regs */
+	st8	[r3]=r2
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=96				/* num phys stacked */
+	movl	r10=0				/* hints */
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=1,r28		/* PAL_CACHE_FLUSH */
+(p7)	br.cond.sptk.few 1f
+	mov	r9=ar.lc
+	movl	r8=524288				/* flush 512k million cache lines (16MB) */
+	;;
+	mov	ar.lc=r8
+	movl	r8=0xe000000000000000
+	;;
+.loop:	fc	r8
+	add	r8=32,r8
+	br.cloop.sptk.few .loop
+	sync.i
+	;;
+	srlz.i
+	;;
+	mov	ar.lc=r9
+	mov	r8=r0
+1:	br.cond.sptk.few rp
+
+stacked:
+	br.ret.sptk.few rp
+
+	.endp pal_emulator
+
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/fw-emu.c lia64-2.4/arch/ia64/sn/fakeprom/fw-emu.c
--- linux-2.4.16/arch/ia64/sn/fakeprom/fw-emu.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/fw-emu.c	Mon Nov 19 23:22:49 2001
@@ -0,0 +1,801 @@
+/*
+ * PAL & SAL emulation.
+ *
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+#include <linux/config.h>
+#include <asm/efi.h>
+#include <asm/pal.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/processor.h>
+#include <asm/sn/sn_cpuid.h>
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+#endif
+#include <asm/acpi-ext.h>
+#include "fpmem.h"
+
+#define zzACPI_1_0	1		/* Include ACPI 1.0 tables */
+
+#define OEMID			"SGI"
+#ifdef CONFIG_IA64_SGI_SN1
+#define PRODUCT			"SN1"
+#define PROXIMITY_DOMAIN(nasid)	(nasid)
+#else
+#define PRODUCT			"SN2"
+#define PROXIMITY_DOMAIN(nasid)	(((nasid)>>1) & 255)
+#endif
+
+#define MB	(1024*1024UL)
+#define GB	(MB*1024UL)
+#define BOOT_PARAM_ADDR 0x40000
+#define MAX(i,j)		((i) > (j) ? (i) : (j))
+#define MIN(i,j)		((i) < (j) ? (i) : (j))
+#define ABS(i)			((i) > 0   ? (i) : -(i))
+#define ALIGN8(p)		(((long)(p) +7) & ~7)
+
+#define FPROM_BUG()		do {while (1);} while (0)
+#define MAX_SN_NODES		128
+#define MAX_LSAPICS		512
+#define MAX_CPUS		512
+#define MAX_CPUS_NODE		4
+#define CPUS_PER_NODE		4
+#define CPUS_PER_FSB		2
+#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
+
+#ifdef ACPI_1_0
+#define NUM_EFI_DESCS		3
+#else
+#define NUM_EFI_DESCS		2
+#endif
+
+#define RSDP_CHECKSUM_LENGTH	20
+
+typedef union ia64_nasid_va {
+        struct {
+#if defined(CONFIG_IA64_SGI_SN1)
+                unsigned long off   : 33;       /* intra-region offset */
+		unsigned long nasid :  7;	/* NASID */
+		unsigned long off2  : 21;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#elif defined(CONFIG_IA64_SGI_SN2)
+                unsigned long off   : 36;       /* intra-region offset */
+		unsigned long attr  :  2;
+		unsigned long nasid : 11;	/* NASID */
+		unsigned long off2  : 12;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#endif
+        } f;
+        unsigned long l;
+        void *p;
+} ia64_nasid_va;
+
+typedef struct {
+	unsigned long	pc;
+	unsigned long	gp;
+} func_ptr_t;
+ 
+#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
+#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.f.attr = 3; _v.l;})
+#endif
+
+/*
+ * The following variables are passed thru registersfrom the configuration file and
+ * are set via the _start function.
+ */
+long		base_nasid;
+long		num_cpus;
+long		bsp_entry_pc=0;
+long		num_nodes;
+long		app_entry_pc;
+int		bsp_lid;
+func_ptr_t	ap_entry;
+
+
+extern void pal_emulator(void);
+static efi_runtime_services_t    *efi_runtime_p;
+static char fw_mem[(  sizeof(efi_system_table_t)
+		    + sizeof(efi_runtime_services_t)
+		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
+		    + sizeof(struct ia64_sal_systab)
+		    + sizeof(struct ia64_sal_desc_entry_point)
+		    + sizeof(struct ia64_sal_desc_ap_wakeup)
+#ifdef ACPI_1_0
+		    + sizeof(acpi_rsdp_t)
+		    + sizeof(acpi_rsdt_t)
+		    + sizeof(acpi_sapic_t)
+		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
+#endif
+		    + sizeof(acpi20_rsdp_t)
+		    + sizeof(acpi_xsdt_t)
+		    + sizeof(acpi_slit_t)
+		    +   MAX_SN_NODES*MAX_SN_NODES+8
+		    + sizeof(acpi_madt_t)
+		    +   16*MAX_CPUS
+		    + (1+8*MAX_SN_NODES)*(sizeof(efi_memory_desc_t))
+		    + sizeof(acpi_srat_t)
+		    +   MAX_CPUS*sizeof(srat_cpu_affinity_t)
+		    +   MAX_SN_NODES*sizeof(srat_memory_affinity_t)
+		    + sizeof(ia64_sal_desc_ptc_t) +
+		    + MAX_SN_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
+		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
+		    + 1024)] __attribute__ ((aligned (8)));
+
+
+static efi_status_t
+efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
+{
+	if (tm) {
+		memset(tm, 0, sizeof(*tm));
+		tm->year = 2000;
+		tm->month = 2;
+		tm->day = 13;
+		tm->hour = 10;
+		tm->minute = 11;
+		tm->second = 12;
+	}
+
+	if (tc) {
+		tc->resolution = 10;
+		tc->accuracy = 12;
+		tc->sets_to_zero = 1;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static void
+efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
+{
+	while(1);	/* Is there a pseudo-op to stop medusa */
+}
+
+static efi_status_t
+efi_success (void)
+{
+	return EFI_SUCCESS;
+}
+
+static efi_status_t
+efi_unimplemented (void)
+{
+	return EFI_UNSUPPORTED;
+}
+
+#ifdef CONFIG_IA64_SGI_SN2
+
+#undef cpu_physical_id
+#define cpu_physical_id(cpuid)                  ((ia64_get_lid() >> 16) & 0xffff)
+
+void
+fprom_send_cpei(void) {
+        long            *p, val;
+        long            physid;
+        long            nasid, slice;
+
+        physid = cpu_physical_id(0);
+        nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+        p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+        val =   (1UL<<SH_IPI_INT_SEND_SHFT) |
+                (physid<<SH_IPI_INT_PID_SHFT) |
+                ((long)0<<SH_IPI_INT_TYPE_SHFT) |
+                ((long)0x1e<<SH_IPI_INT_IDX_SHFT) |
+                (0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+        *p = val;
+
+}
+#endif
+
+
+static long
+sal_emulator (long index, unsigned long in1, unsigned long in2,
+	      unsigned long in3, unsigned long in4, unsigned long in5,
+	      unsigned long in6, unsigned long in7)
+{
+	register long r9 asm ("r9") = 0;
+	register long r10 asm ("r10") = 0;
+	register long r11 asm ("r11") = 0;
+	long status;
+
+	/*
+	 * Don't do a "switch" here since that gives us code that
+	 * isn't self-relocatable.
+	 */
+	status = 0;
+	if (index == SAL_FREQ_BASE) {
+		switch (in1) {
+		      case SAL_FREQ_BASE_PLATFORM:
+			r9 = 500000000;
+			break;
+
+		      case SAL_FREQ_BASE_INTERVAL_TIMER:
+			/*
+			 * Is this supposed to be the cr.itc frequency
+			 * or something platform specific?  The SAL
+			 * doc ain't exactly clear on this...
+			 */
+			r9 = 700000000;
+			break;
+
+		      case SAL_FREQ_BASE_REALTIME_CLOCK:
+			r9 = 50000000;
+			break;
+
+		      default:
+			status = -1;
+			break;
+		}
+	} else if (index == SAL_SET_VECTORS) {
+		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
+			func_ptr_t	*fp;
+			fp = ADDR_OF(&ap_entry);
+			fp->pc = in2;
+			fp->gp = in3;
+		} else if (in1 == SAL_VECTOR_OS_MCA || in1 == SAL_VECTOR_OS_INIT) {
+		} else {
+			status = -1;
+		}
+		;
+	} else if (index == SAL_GET_STATE_INFO) {
+		;
+	} else if (index == SAL_GET_STATE_INFO_SIZE) {
+		;
+	} else if (index == SAL_CLEAR_STATE_INFO) {
+		;
+	} else if (index == SAL_MC_RENDEZ) {
+		;
+	} else if (index == SAL_MC_SET_PARAMS) {
+		;
+	} else if (index == SAL_CACHE_FLUSH) {
+		;
+	} else if (index == SAL_CACHE_INIT) {
+		;
+	} else if (index == SAL_UPDATE_PAL) {
+		;
+#ifdef CONFIG_IA64_SGI_SN2
+	} else if (index == SN_SAL_LOG_CE) {
+#ifdef ajmtestcpei
+		fprom_send_cpei();
+#else /* ajmtestcpei */
+		;
+#endif /* ajmtestcpei */
+#endif
+	} else if (index == SN_SAL_PROBE) {
+		r9 = 0UL;
+		if (in2 == 4) {
+			r9 = *(unsigned *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 2) {
+			r9 = *(unsigned short *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 1) {
+			r9 = *(unsigned char *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 8) {
+			r9 = *(unsigned long *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else {
+			status = 2;
+		}
+	} else if (index == SN_SAL_GET_KLCONFIG_ADDR) {
+		r9 = 0x30000;
+	} else {
+		status = -1;
+	}
+
+	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
+	return status;
+}
+
+
+/*
+ * This is here to work around a bug in egcs-1.1.1b that causes the
+ * compiler to crash (seems like a bug in the new alias analysis code.
+ */
+void *
+id (long addr)
+{
+	return (void *) addr;
+}
+
+
+/*
+ * Fix the addresses in a function pointer by adding base node address
+ * to pc & gp.
+ */
+void
+fix_function_pointer(void *fp)
+{
+	func_ptr_t	*_fp;
+
+	_fp = fp;
+	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
+	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
+}
+
+void
+fix_virt_function_pointer(void **fptr)
+{
+        func_ptr_t      *fp;
+	long		*p;
+
+	p = (long*)fptr;
+        fp = *fptr;
+        fp->pc = fp->pc | PAGE_OFFSET;
+        fp->gp = fp->gp | PAGE_OFFSET;
+	*p |= PAGE_OFFSET;
+}
+
+
+int
+efi_set_virtual_address_map(void)
+{
+        efi_runtime_services_t            *runtime;
+
+        runtime = efi_runtime_p;
+        fix_virt_function_pointer((void**)&runtime->get_time);
+        fix_virt_function_pointer((void**)&runtime->set_time);
+        fix_virt_function_pointer((void**)&runtime->get_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_virtual_address_map);
+        fix_virt_function_pointer((void**)&runtime->get_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_variable);
+        fix_virt_function_pointer((void**)&runtime->set_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_high_mono_count);
+        fix_virt_function_pointer((void**)&runtime->reset_system);
+        return EFI_SUCCESS;;
+}
+
+void
+acpi_table_init(acpi_desc_table_hdr_t *p, char *sig, int siglen, int revision, int oem_revision)
+{
+	memcpy(p->signature, sig, siglen);
+	memcpy(p->oem_id, OEMID, 6);
+	memcpy(p->oem_table_id, sig, 4);
+	memcpy(p->oem_table_id+4, PRODUCT, 4);
+	p->revision = revision;
+	p->oem_revision = (revision<<16) + oem_revision;
+	p->creator_id = 1;
+	p->creator_revision = 1;
+}
+
+void
+acpi_checksum(acpi_desc_table_hdr_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+p->length; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+void
+acpi_checksum_rsdp20(acpi20_rsdp_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+int
+nasid_present(int nasid)
+{
+	int	cnode;
+	for (cnode=0; cnode<num_nodes; cnode++)
+		if (GetNasid(cnode) == nasid)
+			return 1;
+	return 0;
+}
+
+void
+sys_fw_init (const char *args, int arglen, int bsp)
+{
+	/*
+	 * Use static variables to keep from overflowing the RSE stack
+	 */
+	static efi_system_table_t *efi_systab;
+	static efi_runtime_services_t *efi_runtime;
+	static efi_config_table_t *efi_tables;
+	static ia64_sal_desc_ptc_t *sal_ptc;
+	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
+	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
+#ifdef ACPI_1_0
+	static acpi_rsdp_t *acpi_rsdp;
+	static acpi_rsdt_t *acpi_rsdt;
+	static acpi_sapic_t *acpi_sapic;
+	static acpi_entry_lsapic_t *acpi_lsapic;
+#endif
+	static acpi20_rsdp_t *acpi20_rsdp;
+	static acpi_xsdt_t *acpi_xsdt;
+	static acpi_slit_t *acpi_slit;
+	static acpi_madt_t *acpi_madt;
+	static acpi20_entry_lsapic_t *lsapic20;
+	static struct ia64_sal_systab *sal_systab;
+	static acpi_srat_t *acpi_srat;
+	static srat_cpu_affinity_t *srat_cpu_affinity;
+	static srat_memory_affinity_t *srat_memory_affinity;
+	static efi_memory_desc_t *efi_memmap, *md;
+	static unsigned long *pal_desc, *sal_desc;
+	static struct ia64_sal_desc_entry_point *sal_ed;
+	static struct ia64_boot_param *bp;
+	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
+	static unsigned char checksum;
+	static char *cp, *cmd_line, *vendor;
+	static void *ptr;
+	static int mdsize, domain, last_domain ;
+	static int i, j, cnode, max_nasid, nasid, cpu, num_memmd, cpus_found;
+
+	/*
+	 * Pass the parameter base address to the build_efi_xxx routines.
+	 */
+#if defined(CONFIG_IA64_SGI_SN1)
+	build_init(8LL*GB*base_nasid);
+#else
+	build_init(0x3000000000UL | ((long)base_nasid<<38));
+#endif
+
+	num_nodes = GetNumNodes();
+	num_cpus = GetNumCpus();
+	for (max_nasid=0, cnode=0; cnode<num_nodes; cnode++)
+		max_nasid = MAX(max_nasid, GetNasid(cnode));
+
+
+	memset(fw_mem, 0, sizeof(fw_mem));
+
+	pal_desc = (unsigned long *) &pal_emulator;
+	sal_desc = (unsigned long *) &sal_emulator;
+	fix_function_pointer(&pal_emulator);
+	fix_function_pointer(&sal_emulator);
+
+	/* Align this to 16 bytes, probably EFI does this  */
+	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
+
+	cp = fw_mem;
+	efi_systab  = (void *) cp; cp += ALIGN8(sizeof(*efi_systab));
+	efi_runtime_p = efi_runtime = (void *) cp; cp += ALIGN8(sizeof(*efi_runtime));
+	efi_tables  = (void *) cp; cp += ALIGN8(NUM_EFI_DESCS*sizeof(*efi_tables));
+	sal_systab  = (void *) cp; cp += ALIGN8(sizeof(*sal_systab));
+	sal_ed      = (void *) cp; cp += ALIGN8(sizeof(*sal_ed));
+	sal_ptc     = (void *) cp; cp += ALIGN8(sizeof(*sal_ptc));
+	sal_apwake  = (void *) cp; cp += ALIGN8(sizeof(*sal_apwake));
+	acpi20_rsdp = (void *) cp; cp += ALIGN8(sizeof(*acpi20_rsdp));
+	acpi_xsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_xsdt) + 64); 
+			/* save space for more OS defined table pointers. */
+
+#ifdef ACPI_1_0
+	acpi_rsdp   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdp));
+	acpi_rsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdt));
+	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
+	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
+#endif
+	acpi_slit   = (void *) cp; cp += ALIGN8(sizeof(*acpi_slit) + 8 + (max_nasid+1)*(max_nasid+1));
+	acpi_madt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_madt) + 8 * num_cpus+ 8);
+	acpi_srat   = (void *) cp; cp += ALIGN8(sizeof(acpi_srat_t));
+	cp         += sizeof(srat_cpu_affinity_t)*num_cpus + sizeof(srat_memory_affinity_t)*num_nodes;
+	vendor 	    = (char *) cp; cp += ALIGN8(40);
+	efi_memmap  = (void *) cp; cp += ALIGN8(8*32*sizeof(*efi_memmap));
+	sal_ptcdi   = (void *) cp; cp += ALIGN8(CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi));
+	sal_ptclid  = (void *) cp; cp += ALIGN8(((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8);
+	cmd_line    = (void *) cp;
+
+	if (args) {
+		if (arglen >= 1024)
+			arglen = 1023;
+		memcpy(cmd_line, args, arglen);
+	} else {
+		arglen = 0;
+	}
+	cmd_line[arglen] = '\0';
+#ifdef BRINGUP
+	/* for now, just bring up bash */
+	strcpy(cmd_line, "init=/bin/bash");
+#else
+	strcpy(cmd_line, "");
+#endif
+
+	memset(efi_systab, 0, sizeof(efi_systab));
+	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
+	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
+	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
+	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
+	efi_systab->fw_revision = 1;
+	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
+	efi_systab->nr_tables = 2;
+	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
+	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 40);
+
+	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
+	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
+	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
+	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
+	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
+	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
+
+	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
+	efi_tables++;
+#ifdef ACPI_1_0
+	efi_tables->guid = ACPI_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi_rsdp);
+	efi_tables++;
+#endif
+	efi_tables->guid = ACPI_20_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi20_rsdp);
+	efi_tables++;
+
+	fix_function_pointer(&efi_unimplemented);
+	fix_function_pointer(&efi_get_time);
+	fix_function_pointer(&efi_success);
+	fix_function_pointer(&efi_reset_system);
+	fix_function_pointer(&efi_set_virtual_address_map);
+
+#ifdef ACPI_1_0
+	/* fill in the ACPI system table - has a pointer to the ACPI table header */
+	memcpy(acpi_rsdp->signature, "RSD PTR ", 8);
+	acpi_rsdp->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
+
+	acpi_table_init(&acpi_rsdt->header, ACPI_RSDT_SIG, ACPI_RSDT_SIG_LEN, 1, 1);
+	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
+	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
+
+	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
+	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
+			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
+			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
+			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			acpi_lsapic->eid = cpu;
+			acpi_lsapic->id = nasid;
+#else
+			acpi_lsapic->eid = nasid&0xffff;
+			acpi_lsapic->id = (cpu<<4) | (nasid>>16);
+#endif
+			acpi_lsapic++;
+		}
+	}
+#endif
+
+
+	/* fill in the ACPI20 system table - has a pointer to the ACPI table header */
+	memcpy(acpi20_rsdp->signature, "RSD PTR ", 8);
+	acpi20_rsdp->xsdt = (struct acpi_xsdt*)__fwtab_pa(base_nasid, acpi_xsdt);
+	acpi20_rsdp->revision = 2;
+	acpi_checksum_rsdp20(acpi20_rsdp, sizeof(acpi20_rsdp_t));
+
+	/* Set up the XSDT table  - contains pointers to the other ACPI tables */
+	acpi_table_init(&acpi_xsdt->header, ACPI_XSDT_SIG, ACPI_XSDT_SIG_LEN, 1, 1);
+	acpi_xsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_madt);
+	acpi_xsdt->entry_ptrs[1] = __fwtab_pa(base_nasid, acpi_slit);
+	acpi_xsdt->entry_ptrs[2] = __fwtab_pa(base_nasid, acpi_srat);
+	acpi_checksum(&acpi_xsdt->header, sizeof(acpi_xsdt_t) + 16);
+
+	/* Set up the MADT table */
+	acpi_table_init(&acpi_madt->header, ACPI_MADT_SIG, ACPI_MADT_SIG_LEN, 1, 1);
+	lsapic20 = (acpi20_entry_lsapic_t*) (acpi_madt + 1);
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			lsapic20->type = ACPI20_ENTRY_LOCAL_SAPIC;
+			lsapic20->length = sizeof(acpi_entry_lsapic_t);
+			lsapic20->acpi_processor_id = cnode*4+cpu;
+			lsapic20->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			lsapic20->eid = cpu;
+			lsapic20->id = nasid;
+#else
+			lsapic20->eid = nasid&0xffff;
+			lsapic20->id = (cpu<<4) | (nasid>>16);
+#endif
+			lsapic20 = (acpi20_entry_lsapic_t*) ((long)lsapic20+sizeof(acpi_entry_lsapic_t));
+		}
+	}
+	acpi_checksum(&acpi_madt->header, (char*)lsapic20 - (char*)acpi_madt);
+
+	/* Set up the SRAT table */
+	acpi_table_init(&acpi_srat->header, ACPI_SRAT_SIG, ACPI_SRAT_SIG_LEN, ACPI_SRAT_REVISION, 1);
+	ptr = acpi_srat+1;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		srat_memory_affinity = ptr;
+		ptr = srat_memory_affinity+1;
+		srat_memory_affinity->type = SRAT_MEMORY_STRUCTURE;
+		srat_memory_affinity->length = sizeof(srat_memory_affinity_t);
+		srat_memory_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+		srat_memory_affinity->base_addr_lo = 0;
+		srat_memory_affinity->length_lo = 0;
+#if defined(CONFIG_IA64_SGI_SN1)
+		srat_memory_affinity->base_addr_hi = nasid<<1;
+		srat_memory_affinity->length_hi = SN1_NODE_SIZE>>32;
+#else
+		srat_memory_affinity->base_addr_hi = (nasid<<6) | (3<<4);
+		srat_memory_affinity->length_hi = SN2_NODE_SIZE>>32;
+#endif
+		srat_memory_affinity->memory_type = ACPI_ADDRESS_RANGE_MEMORY;
+		srat_memory_affinity->flags = SRAT_MEMORY_FLAGS_ENABLED;
+	}
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			srat_cpu_affinity = ptr;
+			ptr = srat_cpu_affinity + 1;
+			srat_cpu_affinity->type = SRAT_CPU_STRUCTURE;
+			srat_cpu_affinity->length = sizeof(srat_cpu_affinity_t);
+			srat_cpu_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+			srat_cpu_affinity->flags = SRAT_CPU_FLAGS_ENABLED;
+#if defined(CONFIG_IA64_SGI_SN1)
+			srat_cpu_affinity->apic_id = nasid;
+			srat_cpu_affinity->local_sapic_eid = cpu;
+#else
+			srat_cpu_affinity->local_sapic_eid = nasid&0xffff;
+			srat_cpu_affinity->apic_id = (cpu<<4) | (nasid>>16);
+#endif
+		}
+	}
+	acpi_checksum(&acpi_srat->header, (char*)ptr - (char*)acpi_srat);
+
+
+	/* Set up the SLIT table */
+	acpi_table_init(&acpi_slit->header, ACPI_SLIT_SIG, ACPI_SLIT_SIG_LEN, ACPI_SLIT_REVISION, 1);
+	acpi_slit->localities = PROXIMITY_DOMAIN(max_nasid)+1;
+	cp=acpi_slit->entries;
+	memset(cp, 255, acpi_slit->localities*acpi_slit->localities);
+
+	for (i=0; i<=max_nasid; i++)
+		for (j=0; j<=max_nasid; j++)
+			if (nasid_present(i) && nasid_present(j))
+				*(cp+PROXIMITY_DOMAIN(i)*acpi_slit->localities+PROXIMITY_DOMAIN(j)) = 10 + MIN(254, 5*ABS(i-j));
+
+	cp = acpi_slit->entries + acpi_slit->localities*acpi_slit->localities;
+	acpi_checksum(&acpi_slit->header, cp - (char*)acpi_slit);
+
+
+	/* fill in the SAL system table: */
+	memcpy(sal_systab->signature, "SST_", 4);
+	sal_systab->size = sizeof(*sal_systab);
+	sal_systab->sal_rev_minor = 1;
+	sal_systab->sal_rev_major = 0;
+	sal_systab->entry_count = 3;
+
+	strcpy(sal_systab->oem_id, "SGI");
+	strcpy(sal_systab->product_id, "SN1");
+
+	/* fill in an entry point: */	
+	sal_ed->type = SAL_DESC_ENTRY_POINT;
+	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
+	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
+	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
+
+	/* kludge the PTC domain info */
+	sal_ptc->type = SAL_DESC_PTC;
+	sal_ptc->num_domains = 0;
+	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
+	cpus_found = 0;
+	last_domain = -1;
+	sal_ptcdi--;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (IsCpuPresent(cnode, cpu)) {
+				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
+				if (domain != last_domain) {
+					sal_ptc->num_domains++;
+					sal_ptcdi++;
+					sal_ptcdi->proc_count = 0;
+					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
+					last_domain = domain;
+				}
+				sal_ptcdi->proc_count++;
+				sal_ptclid->id = nasid;
+				sal_ptclid->eid = cpu;
+				sal_ptclid++;
+				cpus_found++;
+			}
+		}
+	}
+
+	if (cpus_found != num_cpus)
+		FPROM_BUG();
+
+	/* Make the AP WAKEUP entry */
+	sal_apwake->type = SAL_DESC_AP_WAKEUP;
+	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
+	sal_apwake->vector = 18;
+
+	for (checksum=0, cp=(char*)sal_systab; cp < (char *)efi_memmap; ++cp)
+		checksum += *cp;
+	sal_systab->checksum = -checksum;
+
+	/* If the checksum is correct, the kernel tries to use the
+	 * table. We dont build enough table & the kernel aborts.
+	 * Note that the PROM hasd thhhe same problem!!
+	 */
+#ifdef DOESNT_WORK
+	for (checksum=0, cp=(char*)acpi_rsdp, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; ++cp)
+		checksum += *cp;
+	acpi_rsdp->checksum = -checksum;
+#endif
+
+	md = &efi_memmap[0];
+	num_memmd = build_efi_memmap((void *)md, mdsize) ;
+
+	bp = (struct ia64_boot_param*) __fwtab_pa(base_nasid, BOOT_PARAM_ADDR);
+	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
+	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
+	bp->efi_memmap_size = num_memmd*mdsize;
+	bp->efi_memdesc_size = mdsize;
+	bp->efi_memdesc_version = 0x101;
+	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
+	bp->console_info.num_cols = 80;
+	bp->console_info.num_rows = 25;
+	bp->console_info.orig_x = 0;
+	bp->console_info.orig_y = 24;
+	bp->fpswa = 0;
+
+	/*
+	 * Now pick the BSP & store it LID value in
+	 * a global variable. Note if BSP is greater than last cpu,
+	 * pick the last cpu.
+	 */
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+#ifdef CONFIG_IA64_SGI_SN1
+			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
+#else
+			bsp_lid = (GetNasid(cnode)<<16) | (cpu<<28);
+#endif
+			if (bsp-- > 0)
+				continue;
+			return;
+		}
+	}
+}
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/klgraph_init.c lia64-2.4/arch/ia64/sn/fakeprom/klgraph_init.c
--- linux-2.4.16/arch/ia64/sn/fakeprom/klgraph_init.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/klgraph_init.c	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,291 @@
+/* $Id: klgraph_init.c,v 1.1 2001/11/01 19:24:59 jh Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+
+/*
+ * This is a temporary file that statically initializes the expected 
+ * initial klgraph information that is normally provided by prom.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <asm/sn/sgi.h>
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+#define WIDGET4                 ((char *)0xc0000a0000000004)
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+
+#define convert(a,b,c) temp = (u64 *)a; *temp = b; temp++; *temp = c
+void
+klgraph_init(void)
+{
+
+	u64	*temp;
+
+	/*
+	 * Initialize some hub/xbow registers that allows access to 
+	 * Xbridge etc.  These are normally done in PROM.
+	 */
+
+        /* Write IOERR clear to clear the CRAZY bit in the status */
+#ifdef CONFIG_IA64_SGI_SN1
+        *(volatile uint64_t *)0xc0000a0001c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to b */
+        *(volatile uint64_t *)0xc0000a0001c00020 = (uint64_t)0x801b;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+        *(volatile uint64_t *)0xc0000a0001e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+        *(volatile u32 *)0xc0000a000f000280L = 0xba98;
+        *(volatile u32 *)0xc0000a000f000288L = 0xba98;
+#elif CONFIG_IA64_SGI_SN2
+        *(volatile uint64_t *)0xc000000801c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to a */
+        *(volatile uint64_t *)0xc000000801c00020 = (uint64_t)0x801a;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+// [LB]        *(volatile uint64_t *)0xc000000801e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+// [PI]       *(volatile u32 *)0xc00000080f000280L = 0xba98;
+// [PI]       *(volatile u32 *)0xc00000080f000288L = 0xba98;
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+	/*
+	 * kldir entries initialization - mankato
+	 */
+	convert(0x8000000000002000, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002010, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002020, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002030, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002040, 0x434d5f53505f5357, 0x0000000000030000);
+	convert(0x8000000000002050, 0x0000000000000000, 0x0000000000010000);
+	convert(0x8000000000002060, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002070, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002080, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002090, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020a0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020b0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020c0, 0x434d5f53505f5357, 0x0000000000000000);
+	convert(0x80000000000020d0, 0x0000000000002400, 0x0000000000000400);
+	convert(0x80000000000020e0, 0x0000000000000001, 0x0000000000000000);
+	convert(0x80000000000020f0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002100, 0x434d5f53505f5357, 0x0000000000040000);
+	convert(0x8000000000002110, 0x0000000000000000, 0xffffffffffffffff);
+	convert(0x8000000000002120, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002130, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002140, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002150, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002160, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002170, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002180, 0x434d5f53505f5357, 0x0000000000020000);
+	convert(0x8000000000002190, 0x0000000000000000, 0x0000000000010000);
+	convert(0x80000000000021a0, 0x0000000000000001, 0x0000000000000000); 
+
+	/*
+	 * klconfig entries initialization - mankato
+	 */
+	convert(0x0000000000030000, 0x00000000beedbabe, 0x0000004800000000);
+	convert(0x0000000000030010, 0x0003007000000018, 0x800002000f820178);
+	convert(0x0000000000030020, 0x80000a000f024000, 0x800002000f800000);
+	convert(0x0000000000030030, 0x0300fafa00012580, 0x00000000040f0000);
+	convert(0x0000000000030040, 0x0000000000000000, 0x0003097000030070);
+	convert(0x0000000000030050, 0x00030970000303b0, 0x0003181000033f70);
+	convert(0x0000000000030060, 0x0003d51000037570, 0x0000000000038330);
+	convert(0x0000000000030070, 0x0203110100030140, 0x0001000000000101);
+	convert(0x0000000000030080, 0x0900000000000000, 0x000000004e465e67);
+	convert(0x0000000000030090, 0x0003097000000000, 0x00030b1000030a40);
+	convert(0x00000000000300a0, 0x00030cb000030be0, 0x000315a0000314d0);
+	convert(0x00000000000300b0, 0x0003174000031670, 0x0000000000000000);
+	convert(0x0000000000030100, 0x000000000000001a, 0x3350490000000000);
+	convert(0x0000000000030110, 0x0000000000000037, 0x0000000000000000);
+	convert(0x0000000000030140, 0x0002420100030210, 0x0001000000000101);
+	convert(0x0000000000030150, 0x0100000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030160, 0x00030d8000000000, 0x0000000000030e50);
+	convert(0x00000000000301c0, 0x0000000000000000, 0x0000000000030070);
+	convert(0x00000000000301d0, 0x0000000000000025, 0x424f490000000000);
+	convert(0x00000000000301e0, 0x000000004b434952, 0x0000000000000000);
+	convert(0x0000000000030210, 0x00027101000302e0, 0x00010000000e4101);
+	convert(0x0000000000030220, 0x0200000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030230, 0x00030f2000000000, 0x0000000000030ff0);
+	convert(0x0000000000030290, 0x0000000000000000, 0x0000000000030140);
+	convert(0x00000000000302a0, 0x0000000000000026, 0x7262490000000000);
+	convert(0x00000000000302b0, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x00000000000302e0, 0x0002710100000000, 0x00010000000f3101);
+	convert(0x00000000000302f0, 0x0500000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030300, 0x000310c000000000, 0x0003126000031190);
+	convert(0x0000000000030310, 0x0003140000031330, 0x0000000000000000);
+	convert(0x0000000000030360, 0x0000000000000000, 0x0000000000030140);
+	convert(0x0000000000030370, 0x0000000000000029, 0x7262490000000000);
+	convert(0x0000000000030380, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x0000000000030970, 0x0000000002010102, 0x0000000000000000);
+	convert(0x0000000000030980, 0x000000004e465e67, 0xffffffff00000000);
+	/* convert(0x00000000000309a0, 0x0000000000037570, 0x0000000100000000); */
+	convert(0x00000000000309a0, 0x0000000000037570, 0xffffffff00000000);
+	convert(0x00000000000309b0, 0x0000000000030070, 0x0000000000000000);
+	convert(0x00000000000309c0, 0x000000000003f420, 0x0000000000000000);
+	convert(0x0000000000030a40, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030a50, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030a70, 0x0000000000037b78, 0x0000000000000000);
+	convert(0x0000000000030b10, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030b20, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030b40, 0x0000000000037d30, 0x0000000000000001);
+	convert(0x0000000000030be0, 0x00000000ff010203, 0x0000000000000000);
+	convert(0x0000000000030bf0, 0xffffffffffffffff, 0xffffffff000000ff);
+	convert(0x0000000000030c10, 0x0000000000037ee8, 0x0100010000000200);
+	convert(0x0000000000030cb0, 0x00000000ff310111, 0x0000000000000000);
+	convert(0x0000000000030cc0, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030d80, 0x0000000002010104, 0x0000000000000000);
+	convert(0x0000000000030d90, 0xffffffffffffffff, 0x00000000000000ff);
+	convert(0x0000000000030db0, 0x0000000000037f18, 0x0000000000000000);
+	convert(0x0000000000030dc0, 0x0000000000000000, 0x0003007000060000);
+	convert(0x0000000000030de0, 0x0000000000000000, 0x0003021000050000);
+	convert(0x0000000000030df0, 0x000302e000050000, 0x0000000000000000);
+	convert(0x0000000000030e30, 0x0000000000000000, 0x000000000000000a);
+	convert(0x0000000000030e50, 0x00000000ff00011a, 0x0000000000000000);
+	convert(0x0000000000030e60, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030e80, 0x0000000000037fe0, 0x9e6e9e9e9e9e9e9e);
+	convert(0x0000000000030e90, 0x000000000000bc6e, 0x0000000000000000);
+	convert(0x0000000000030f20, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x0000000000030f30, 0xffffffffffffffff, 0x0000000e0000000e);
+	convert(0x0000000000030f40, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000030f50, 0x0000000000038010, 0x00000000000007ff);
+	convert(0x0000000000030f70, 0x0000000000000000, 0x0000000022001077);
+	convert(0x0000000000030fa0, 0x0000000000000000, 0x000000000003f4a8);
+	convert(0x0000000000030ff0, 0x0000000000310120, 0x0000000000000000);
+	convert(0x0000000000031000, 0xffffffffffffffff, 0xffffffff00000002);
+	convert(0x0000000000031010, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000031020, 0x0000000000038088, 0x0000000000000000);
+	convert(0x00000000000310c0, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x00000000000310d0, 0xffffffffffffffff, 0x0000000f0000000f);
+	convert(0x00000000000310e0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000310f0, 0x00000000000380b8, 0x00000000000007ff);
+	convert(0x0000000000031120, 0x0000000022001077, 0x00000000000310a9);
+	convert(0x0000000000031130, 0x00000000580211c1, 0x000000008009104c);
+	convert(0x0000000000031140, 0x0000000000000000, 0x000000000003f4c0);
+	convert(0x0000000000031190, 0x0000000000310120, 0x0000000000000000);
+	convert(0x00000000000311a0, 0xffffffffffffffff, 0xffffffff00000003);
+	convert(0x00000000000311b0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000311c0, 0x0000000000038130, 0x0000000000000000);
+	convert(0x0000000000031260, 0x0000000000110106, 0x0000000000000000);
+	convert(0x0000000000031270, 0xffffffffffffffff, 0xffffffff00000004);
+	convert(0x0000000000031280, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312a0, 0x00000000ff110013, 0x0000000000000000);
+	convert(0x00000000000312b0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x00000000000312c0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312e0, 0x0000000000110012, 0x0000000000000000);
+	convert(0x00000000000312f0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031300, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031310, 0x0000000000038160, 0x0000000000000000);
+	convert(0x0000000000031330, 0x00000000ff310122, 0x0000000000000000);
+	convert(0x0000000000031340, 0xffffffffffffffff, 0xffffffff00000005);
+	convert(0x0000000000031350, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031360, 0x0000000000038190, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031410, 0xffffffffffffffff, 0xffffffff00000006);
+	convert(0x0000000000031420, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031430, 0x00000000000381c0, 0x0000000000000000);
+	convert(0x00000000000314d0, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x00000000000314e0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031500, 0x00000000000381f0, 0x000030430000ffff);
+	convert(0x0000000000031510, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x00000000000315a0, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x00000000000315b0, 0xffffffffffffffff, 0xffffffff00000001);
+	convert(0x00000000000315d0, 0x0000000000038240, 0x00003f3f0000ffff);
+	convert(0x00000000000315e0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031670, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x0000000000031680, 0xffffffffffffffff, 0x0000000100000002);
+	convert(0x00000000000316a0, 0x0000000000038290, 0x000030430000ffff);
+	convert(0x00000000000316b0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031740, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x0000000000031750, 0xffffffffffffffff, 0x0000000500000003);
+	convert(0x0000000000031770, 0x00000000000382e0, 0x00003f3f0000ffff);
+	convert(0x0000000000031780, 0x000000000000ffff, 0x0000000000000000);
+
+	/*
+	 * GDA initialization - mankato
+	 */
+	convert(0x8000000000002400, 0x0000000258464552, 0x000000000ead0000);
+	convert(0x8000000000002480, 0xffffffff00010000, 0xffffffffffffffff);
+	convert(0x8000000000002490, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024a0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024b0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024c0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024d0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024e0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024f0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002500, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002510, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002520, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002530, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002540, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002550, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002560, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002570, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002580, 0x000000000000ffff, 0x0000000000000000);
+	
+}
+
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/main.c lia64-2.4/arch/ia64/sn/fakeprom/main.c
--- linux-2.4.16/arch/ia64/sn/fakeprom/main.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/main.c	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,125 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/bitops.h>
+
+extern void klgraph_init(void);
+void bedrock_init(int);
+void synergy_init(int, int);
+void sys_fw_init (const char *args, int arglen, int bsp);
+
+volatile int	bootmaster=0;		/* Used to pick bootmaster */
+volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
+int		init_done=0;
+extern int	bsp_lid;
+
+#define get_bit(b,p)	(((*p)>>(b))&1)
+
+int
+fmain(int lid, int bsp) {
+	int	syn, nasid, cpu;
+
+	/*
+	 * First lets figure out who we are. This is done from the
+	 * LID passed to us.
+	 */
+
+#ifdef CONFIG_IA64_SGI_SN1
+	nasid = (lid>>24);
+	syn = (lid>>17)&1;
+	cpu = (lid>>16)&1;
+
+	/*
+	 * Now pick a synergy master to initialize synergy registers.
+	 */
+	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
+		synergy_init(nasid, syn);
+		test_and_set_bit(syn+2, &nasidmaster[nasid]);
+	} else
+		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
+#else
+	nasid = (lid>>16)&0xfff;
+	cpu = (lid>>28)&3;
+	syn = 0;
+#endif
+	
+	/*
+	 * Now pick a nasid master to initialize Bedrock registers.
+	 */
+	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
+		bedrock_init(nasid);
+		test_and_set_bit(9, &nasidmaster[nasid]);
+	} else
+		while (get_bit(9, &nasidmaster[nasid]) == 0);
+	
+
+	/*
+	 * Now pick a BSP & finish init.
+	 */
+	if (test_and_set_bit(0, &bootmaster) == 0) {
+		sys_fw_init(0, 0, bsp);
+		test_and_set_bit(1, &bootmaster);
+	} else
+		while (get_bit(1, &bootmaster) == 0);
+
+	return (lid == bsp_lid);
+}
+
+
+void
+bedrock_init(int nasid)
+{
+	nasid = nasid;		/* to quiet gcc */
+#if 0
+	/*
+	 * Undef if you need fprom to generate a 1 node klgraph
+	 * information .. only works for 1 node for nasid 0.
+	 */
+	klgraph_init();
+#endif
+}
+
+
+void
+synergy_init(int nasid, int syn)
+{
+	long	*base;
+	long	off;
+
+	/*
+	 * Enable all FSB flashed interrupts.
+	 * ZZZ - I'd really like defines for this......
+	 */
+	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
+	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
+		*(base+off/8) = -1LL;
+
+	/*
+	 * Set the NASID in the FSB_CONFIG register.
+	 */
+	base = (long*)0x80000e0000000450LL;
+	*base = (long)((nasid<<16)|(syn<<9));
+}
+
+
+/* Why isnt there a bcopy/memcpy in lib64.a */
+
+void* 
+memcpy(void * dest, const void *src, size_t count)
+{
+	char *s, *se, *d;
+
+	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
+		*d = *s;
+	return dest;
+}
diff -urN linux-2.4.16/arch/ia64/sn/fakeprom/runsim lia64-2.4/arch/ia64/sn/fakeprom/runsim
--- linux-2.4.16/arch/ia64/sn/fakeprom/runsim	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/fakeprom/runsim	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,387 @@
+#!/bin/sh
+
+# Script for running PROMs and LINUX kernwls on medusa. 
+# Type "sim -H" for instructions.
+
+MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
+
+# ------------------ err -----------------------
+err() {
+	echo "ERROR - $1"
+	exit 1
+}
+
+# ----------------  help ----------------------
+help() {
+cat <<END
+Script for running a PROM or LINUX kernel under medusa.
+This script creates a control file, creates links to the appropriate
+linux/prom files, and/or calls medusa to make simulation runs.
+
+Usage:  
+   Initial setup:
+   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
+		-p	Create PROM control file & links
+		-k	Create LINUX control file & links
+		-c<cf>	Control file name				[Default: cf]
+		<work_dir> Path to directory that contains the linux or PROM files.
+		    The directory can be any of the following:
+		       (linux simulations)
+		       		worktree
+				worktree/linux
+				any directory with vmlinux, vmlinux.sym & fprom files
+			(prom simulations)
+				worktree
+				worktree/stand/arcs/IP37prom/dev
+				any directory with fw.bin & fw.sim files
+
+    Simulations:
+	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
+		-c<cf>	Control file name				[Default: cf]
+		-M	Pipe output thru fmtmedusa
+		-o	Output filename (copy of all commands/output)	[Default: simout]
+		-X	Specifies number of instructions to execute	[Default: 0]
+			(Used only in auto test mode - not described here)
+
+Examples:
+	sim -p <promtree>	# create control file (cf) & links for prom simulations
+	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
+	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
+
+	sim			# run medusa using previously created links &
+				#   control file (cf).
+END
+exit 1
+}
+
+# ----------------------- create control file header --------------------
+create_cf_header() {
+cat <<END >>$CF
+#
+# Template for a control file for running linux kernels under medusa. 
+# You probably want to make mods here but this is a good starting point.
+#
+
+# Preferences
+setenv cpu_stepping A
+setenv exceptionPrint off
+setenv interrupt_messages off
+setenv lastPCsize 100000
+setenv low_power_mode on
+setenv partialIntelChipSet on
+setenv printIntelMessages off
+setenv prom_write_action halt
+setenv prom_write_messages on
+setenv step_quantum 100
+setenv swizzling on
+setenv tsconsole on
+setenv uart_echo on
+symbols on
+
+# IDE disk params
+setenv diskCylinders 611
+setenv bootDrive C
+setenv diskHeads 16
+setenv diskPath idedisk
+setenv diskPresent 1
+setenv diskSpt 63
+
+# Hardware config
+setenv coherency_type nasid
+setenv cpu_cache_type default
+setenv synergy_cache_type syn_cac_64m_8w
+setenv l4_uc_snoop off
+
+# Numalink config
+setenv route_enable on
+setenv network_type router		# Select [xbar|router]
+setenv network_warning 0xff
+
+END
+}
+
+
+# ------------------ create control file entries for linux simulations -------------
+create_cf_linux() {
+cat <<END >>$CF
+# Kernel specific options
+setenv calias_size 0
+setenv mca_on_memory_failure off
+setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
+setenv symbol_table vmlinux.sym
+load fprom
+load vmlinux
+
+# Useful breakpoints to always have set. Add more if desired.
+break 0xe000000000505e00	all	# dispatch_to_fault_handler
+break panic			all	# stop on panic
+break die_if_kernel		all	# may as well stop
+
+END
+}
+
+# ------------------ create control file entries for prom simulations ---------------
+create_cf_prom() {
+	SYM2=""
+	ADDR="0x80000000ff800000"
+	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
+	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
+	cat <<END >>$CF
+# PROM specific options
+setenv mca_on_memory_failure on
+setenv LOADPC 0x80000000ffffffb0
+setenv promFile fw.bin
+setenv promAddr $ADDR
+setenv symbol_table fw.sym
+$SYM2
+
+# Useful breakpoints to always have set. Add more if desired.
+break ivt_gexx 		all
+break ivt_brk		all
+break PROM_Panic_Spin	all
+break PROM_Panic	all
+break PROM_C_Panic	all
+break fled_die		all
+break ResetNow		all
+break zzzbkpt		all
+
+END
+}
+
+
+# ------------------ create control file entries for memory configuration -------------
+create_cf_memory() {
+cat <<END >>$CF
+# CPU/Memory map format:
+#	setenv nodeN_memory_config 0xBSBSBSBS
+#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
+#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
+#		  rightmost digits are for bank 0, the lowest address.
+#	setenv nodeN_nasid <nasid>
+#		specifies the NASID for the node. This is used ONLY if booting the kernel.
+#		On PROM configurations, set to 0 - PROM will change it later.
+#	setenv nodeN_cpu_config <cpu_mask>
+#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
+#
+# Repeat the above 3 commands for each node.
+#
+# For kernel, default to 32MB. Although this is not a valid hardware configuration,
+# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
+
+setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
+END
+
+if [ $LINUX -eq 1 ] ; then
+cat <<END >>$CF
+setenv node0_nasid		0	# cnode 0 has NASID 0
+setenv node0_memory_config 	0xe1	# 32MB
+END
+else
+cat <<END >>$CF
+setenv node0_memory_config 	0x31	# 256MB
+END
+fi
+}
+
+# -------------------- set links to linux files -------------------------
+set_linux_links() {
+	if [ -d $D/linux/arch ] ; then
+		D=$D/linux
+	elif [ -d $D/arch -o -e vmlinux.sym -o -e $D/vmlinux ] ; then
+		D=$D
+	else
+		err "cant determine directory for linux binaries"
+	fi
+	rm -rf vmlinux vmlinux.sym fprom
+	ln -s $D/vmlinux vmlinux
+	if [ -f $D/vmlinux.sym ] ; then
+		ln -s $D/vmlinux.sym vmlinux.sym
+	elif  [ -f $D/System.map ] ; then
+		ln -s $D/System.map vmlinux.sym
+	fi
+	if [ -d $D/arch ] ; then
+		ln -s $D/arch/ia64/sn/fprom/fprom fprom
+	else
+		ln -s $D/fprom fprom
+	fi
+	echo "  .. Created links to linux files"	
+}
+
+# -------------------- set links to prom files -------------------------
+set_prom_links() {
+	if [ -d $D/stand ] ; then
+		D=$D/stand/arcs/IP37prom/dev
+	elif [ -d $D/sal ] ; then
+		D=$D
+	else
+		err "cant determine directory for PROM binaries"
+	fi
+	SETUP="/tmp/tmp.$$"
+	rm -r -f $SETUP
+	sed 's/export/setenv/' < $D/../../../../.setup | sed 's/=/ /' >$SETUP
+	egrep -q '^ *setenv *PROMSIZE *8MB|^ *export' $SETUP
+	if [ $? -eq 0 ] ; then
+		SIZE="8MB"
+	else
+		SIZE="4MB"
+	fi
+	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
+	EMBEDDED_LINUX=$?
+	PRODUCT=`grep '^ *setenv *PRODUCT' $SETUP | cut -d" " -f3`
+	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom $SETUP
+	SDIR="${PRODUCT}${SIZE}.O"
+	BIN="${PRODUCT}ip37prom${SIZE}"
+	ln -s $D/$SDIR/$BIN.bin fw.bin
+	ln -s $D/$SDIR/$BIN.map fw.map
+	ln -s $D/$SDIR/$BIN.sym fw.sym
+	echo "  .. Created links to $SIZE prom files"
+	if [ $EMBEDDED_LINUX -eq 0 ] ; then
+		ln -s $D/linux/vmlinux vmlinux
+		ln -s $D/linux/vmlinux.sym vmlinux.sym
+		if [ -d linux/arch ] ; then
+			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
+		else
+			ln -s $D/linux/fprom fprom
+		fi
+		echo "  .. Created links to embedded linux files in prom tree"
+	fi
+}
+
+# --------------- start of shell script --------------------------------
+OUT="simout"
+FMTMED=0
+STEPCNT=0
+PROM=0
+LINUX=0
+NCF="cf"
+while getopts "HMX:c:o:pk" c ; do
+        case ${c} in
+                H) help;;
+		M) FMTMED=1;;
+		X) STEPCNT=${OPTARG};;
+		c) NCF=${OPTARG};;
+		k) PROM=0;LINUX=1;;
+		p) PROM=1;LINUX=0;;
+		o) OUT=${OPTARG};;
+                \?) exit 1;;
+        esac
+done
+shift `expr ${OPTIND} - 1`
+
+# Check if command is for creating control file and/or links to images.
+if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
+	CF=$NCF
+	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
+	if [ $# -gt 0 ] ; then
+		D=$1
+		[ -d $D ] || err "cannot find directory $D"
+		[ $PROM -eq 0 ]  || set_prom_links
+		[ $LINUX -eq 0 ] || set_linux_links
+	fi
+	create_cf_header
+	[ $PROM -eq 0 ]  || create_cf_prom
+	[ $LINUX -eq 0 ] || create_cf_linux
+	[ ! -f ../idedisk ] || ln -s ../idedisk .
+	create_cf_memory
+	echo "  .. Basic control file created (in $CF). You might want to edit"
+	echo "     this file (at least, look at it)."
+	exit 0
+fi
+
+# Verify that the control file exists
+CF=${1:-$NCF}
+[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
+
+# Build the .cf files from the user control file. The .cf file is
+# identical except that the actual start & load addresses are inserted
+# into the file. In addition, the FPROM commands for configuring memory
+# and LIDs are generated. 
+
+rm -f .cf .cf1 .cf2
+awk '
+function strtonum(n) {
+	 if (substr(n,1,2) != "0x")
+	 	return int(n)
+	 n = substr(n,3)
+	 r=0
+	 while (length(n) > 0) {
+	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
+		n = substr(n,2)
+	 }
+	 return r
+	}
+/^#/   	{next}
+/^$/	{next}
+/^setenv *LOADPC/               {loadpc = $3; next}
+/^setenv *node.._cpu_config/	{n=int(substr($2,5,2)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node.._memory_config/	{n=int(substr($2,5,2)); memconf[n] = strtonum($3); print; next}
+/^setenv *node.._nasid/		{n=int(substr($2,5,2)); nasid[n] = strtonum($3); print; next}
+/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
+/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
+		{print}
+END	{
+	 # Generate the memmap info that starts at the beginning of
+	 # the node the kernel was loaded on.
+	 loadnasid = nasid[0]
+	 cnode = 0
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
+				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
+			cnodes++
+			cpus += substr("0112122312232334", cpuconf[i]+1,1)
+		}
+	 }
+	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
+	 printf "setenv number_of_nodes %d\n", cnodes
+
+	 # Now set the starting PC for each cpu.
+	 cnode = 0
+	 lowcpu=-1
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "setnode %d\n", cnode
+			conf = cpuconf[i]
+			for (j=0; j<4; j++) {
+				if (conf != int(conf/2)*2) {
+	 				printf "setcpu %d\n", j
+					if (length(loadpc) == 18)
+						printf "sr pc %s\n", loadpc
+					else
+						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
+					if (lowcpu == -1)
+						lowcpu = j
+				}
+				conf = int(conf/2)
+			}
+			cnode++
+		}
+	 }
+	 printf "setnode 0\n"
+	 printf "setcpu %d\n", lowcpu
+	}
+' <$CF >.cf
+
+# Now build the .cf1 & .cf2 control files.
+CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
+egrep  "$CF2_LINES" .cf >.cf2
+egrep -v "$CF2_LINES" .cf >.cf1
+if [ $STEPCNT -ne 0 ] ; then
+	echo "s $STEPCNT" >>.cf2
+	echo "lastpc 1000" >>.cf2
+	echo "q" >>.cf2
+fi
+if [ -f vmlinux.sym ] ; then
+	awk '/ _start$/ {print "sr g 9 0x" $3}' < vmlinux.sym >> .cf2
+fi
+echo "script-on $OUT" >>.cf2
+
+# Now start medusa....
+if [ $FMTMED -ne 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
+elif [ $STEPCNT -eq 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
+else
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
+fi
diff -urN linux-2.4.16/arch/ia64/sn/fprom/Makefile lia64-2.4/arch/ia64/sn/fprom/Makefile
--- linux-2.4.16/arch/ia64/sn/fprom/Makefile	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/fprom/Makefile	Wed Dec 31 16:00:00 1969
@@ -1,31 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2000 Silicon Graphics, Inc.
-# Copyright (C) Jack Steiner (steiner@sgi.com)
-#
-
-TOPDIR=../../../..
-HPATH           = $(TOPDIR)/include
-
-LIB     = ../../lib/lib.a
-
-OBJ=fpromasm.o main.o  fw-emu.o fpmem.o
-obj-y=fprom
-
-fprom: $(OBJ)
-	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
-
-.S.o:
-	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-.c.o:
-	$(CC)  $(CFLAGS) $(CFLAGS_KERNEL) -c -o $*.o $<
-
-clean:
-	rm -f *.o fprom
-
-
-include $(TOPDIR)/Rules.make
-
diff -urN linux-2.4.16/arch/ia64/sn/fprom/README lia64-2.4/arch/ia64/sn/fprom/README
--- linux-2.4.16/arch/ia64/sn/fprom/README	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/README	Wed Dec 31 16:00:00 1969
@@ -1,85 +0,0 @@
-This directory contains the files required to build
-the fake PROM image that is currently being used to
-boot IA64 kernels running under the SGI Medusa kernel.
-
-The FPROM currently provides the following functions:
-
-	- PAL emulation for all PAL calls we've made so far.
-	- SAL emulation for all SAL calls we've made so far.
-	- EFI emulation for all EFI calls we've made so far.
-	- builds the "ia64_bootparam" structure that is
-	  passed to the kernel from SAL. This structure 
-	  shows the cpu & memory configurations.
-	- supports medusa boottime options for changing
-	  the number of cpus present
-	- supports medusa boottime options for changing
-	  the memory configuration.
-
-
-
-At some point, this fake PROM will be replaced by the
-real PROM.
-
-
-
-
-To build a fake PROM, cd to this directory & type:
-
-	make
-
-This will (or should) build a fake PROM named "fprom".
-
-
-
-
-Use this fprom image when booting the Medusa simulator. The
-control file used to boot Medusa should include the 
-following lines:
-
-	load fprom
-	load vmlinux
-	sr pc 0x100000
-	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
-
-NOTE: There is a script "runsim" in this directory that can be used to
-simplify setting up an environment for running under Medusa.
-
-
-
-
-The following parameters may be passed to the fake PROM to
-control the PAL/SAL/EFI parameters passed to the kernel:
-
-	GR[8] = # of cpus
-	GR[9] = address of primary entry point into the kernel
-	GR[20] = memory configuration for node 0
-	GR[21] = memory configuration for node 1
-	GR[22] = memory configuration for node 2
-	GR[23] = memory configuration for node 3
-
-
-Registers GR[20] - GR[23] contain information to specify the
-amount of memory present on nodes 0-3.
-
-  - if nothing is specified (all registers are 0), the configuration
-    defaults to 8 MB on node 0.
-
-  - a mem config entry for node N is passed in GR[20+N]
-
-  - a mem config entry consists of 8 hex digits. Each digit gives the
-    amount of physical memory available on the node starting at
-    1GB*<dn>, where dn is the digit number. The amount of memory
-    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
-
-    SN1 doesnt support dimms this small but small memory systems 
-    boot faster on Medusa.
-
-
-
-An example helps a lot. The following specifies that node 0 has
-physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
-64MB starting at address 0 of the node which is 8GB.
-
-      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
-      gr[21] = 0x4            # 8GB to 8GB+64MB
-
diff -urN linux-2.4.16/arch/ia64/sn/fprom/fpmem.c lia64-2.4/arch/ia64/sn/fprom/fpmem.c
--- linux-2.4.16/arch/ia64/sn/fprom/fpmem.c	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/fpmem.c	Wed Dec 31 16:00:00 1969
@@ -1,200 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-/*
- * FPROM EFI memory descriptor build routines
- *
- * 	- Routines to build the EFI memory descriptor map
- * 	- Should also be usable by the SGI SN1 prom to convert
- * 	  klconfig to efi_memmap
- */
-
-#include <asm/efi.h>
-#include "fpmem.h"
-
-/*
- * args points to a layout in memory like this
- *
- *		32 bit		32 bit
- *
- * 		numnodes	numcpus
- *
- *		16 bit   16 bit		   32 bit
- *		nasid0	cpuconf		membankdesc0
- *		nasid1	cpuconf		membankdesc1
- *			   .
- *			   .
- *			   .
- *			   .
- *			   .
- */
-
-sn_memmap_t	*sn_memmap ;
-sn_config_t	*sn_config ;
-
-/*
- * There is a hole in the node 0 address space. Dont put it
- * in the memory map
- */
-#define NODE0_HOLE_SIZE         (20*MB)
-#define NODE0_HOLE_END          (4UL*GB)
-
-#define	MB			(1024*1024)
-#define GB			(1024*MB)
-#define KERNEL_SIZE		(4*MB)
-#define PROMRESERVED_SIZE	(1*MB)
-#define MD_BANK_SHFT 30
-
-#define TO_NODE(_n, _x)		(((long)_n<<33L) | (long)_x)
-
-/*
- * For SN, this may not take an arg and gets the numnodes from 
- * the prom variable or by traversing klcfg or promcfg
- */
-int
-GetNumNodes(void)
-{
-	return sn_config->nodes;
-}
-
-int
-GetNumCpus(void)
-{
-	return sn_config->cpus;
-}
-
-/* For SN1, get the index th nasid */
-
-int
-GetNasid(int index)
-{
-	return sn_memmap[index].nasid ;
-}
-
-node_memmap_t
-GetMemBankInfo(int index)
-{
-	return sn_memmap[index].node_memmap ;
-}
-
-int
-IsCpuPresent(int cnode, int cpu)
-{
-	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
-}
-
-
-/*
- * Made this into an explicit case statement so that
- * we can assign specific properties to banks like bank0
- * actually disabled etc.
- */
-
-int
-IsBankPresent(int index, node_memmap_t nmemmap)
-{
-	switch (index) {
-		case 0:return nmemmap.b0;
-		case 1:return nmemmap.b1;
-		case 2:return nmemmap.b2;
-		case 3:return nmemmap.b3;
-		case 4:return nmemmap.b4;
-		case 5:return nmemmap.b5;
-		case 6:return nmemmap.b6;
-		case 7:return nmemmap.b7;
-		default:return -1 ;
-	}
-}
-
-int
-GetBankSize(int index, node_memmap_t nmemmap)
-{
-        switch (index) {
-                case 0:
-                case 1:return nmemmap.b01size;
-                case 2:
-                case 3:return nmemmap.b23size;
-                case 4:
-                case 5:return nmemmap.b45size;
-                case 6:
-                case 7:return nmemmap.b67size;
-                default:return -1 ;
-        }
-}
-
-void
-build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
-{
-        md->type = type;
-        md->phys_addr = paddr;
-        md->virt_addr = 0;
-        md->num_pages = numbytes >> 12;
-        md->attribute = EFI_MEMORY_WB;
-}
-
-int
-build_efi_memmap(void *md, int mdsize)
-{
-	int		numnodes = GetNumNodes() ;
-	int		cnode,bank ;
-	int		nasid ;
-	node_memmap_t	membank_info ;
-	int		bsize;
-	int		count = 0 ;
-	long		paddr, hole, numbytes;
-
-
-	for (cnode=0;cnode<numnodes;cnode++) {
-		nasid = GetNasid(cnode) ;
-		membank_info = GetMemBankInfo(cnode) ;
-		for (bank=0;bank<SN1_MAX_BANK_PER_NODE;bank++) {
-			if (IsBankPresent(bank, membank_info)) {
-				bsize = GetBankSize(bank, membank_info) ;
-                                paddr = TO_NODE(nasid, (long)bank<<MD_BANK_SHFT);
-                                numbytes = BankSizeBytes(bsize);
-
-                                /*
-                                 * Check for the node 0 hole. Since banks cant
-                                 * span the hole, we only need to check if the end of
-                                 * the range is the end of the hole.
-                                 */
-                                if (paddr+numbytes == NODE0_HOLE_END)
-                                        numbytes -= NODE0_HOLE_SIZE;
-                                /*
-                                 * UGLY hack - we must skip overr the kernel and
-                                 * PROM runtime services but we dont exactly where it is.
-                                 * So lets just reserve 0-12MB.
-                                 */
-                                if (bank == 0) {
-					hole = (cnode == 0) ? KERNEL_SIZE : PROMRESERVED_SIZE;
-					numbytes -= hole;
-                                        build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
-                                        paddr += hole;
-			        	count++ ;
-                                        md += mdsize;
-                                }
-                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
-
-			        md += mdsize ;
-			        count++ ;
-			}
-		}
-	}
-	return count ;
-}
-
-void
-build_init(unsigned long args)
-{
-	sn_config = (sn_config_t *) (args);	
-	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
-						/* init to klconfig start */
-}
diff -urN linux-2.4.16/arch/ia64/sn/fprom/fpmem.h lia64-2.4/arch/ia64/sn/fprom/fpmem.h
--- linux-2.4.16/arch/ia64/sn/fprom/fpmem.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/fpmem.h	Wed Dec 31 16:00:00 1969
@@ -1,35 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <asm/sn/mmzone_sn1.h>
-
-typedef struct sn_memmap_s
-{
-	short		nasid ;
-	short		cpuconfig;
-	node_memmap_t 	node_memmap ;
-} sn_memmap_t ;
-
-typedef struct sn_config_s
-{
-	int		cpus;
-	int		nodes;
-	sn_memmap_t	memmap[1];		/* start of array */
-} sn_config_t;
-
-
-extern void build_init(unsigned long);
-extern int build_efi_memmap(void *, int);
-extern int GetNumNodes(void);
-extern int GetNumCpus(void);
-extern int IsCpuPresent(int, int);
-extern int GetNasid(int);
diff -urN linux-2.4.16/arch/ia64/sn/fprom/fprom.lds lia64-2.4/arch/ia64/sn/fprom/fprom.lds
--- linux-2.4.16/arch/ia64/sn/fprom/fprom.lds	Mon Jul  2 14:40:14 2001
+++ lia64-2.4/arch/ia64/sn/fprom/fprom.lds	Wed Dec 31 16:00:00 1969
@@ -1,96 +0,0 @@
-
-OUTPUT_FORMAT("elf64-ia64-little")
-OUTPUT_ARCH(ia64)
-ENTRY(_start)
-SECTIONS
-{
-  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
-
-  . = (0x000000000000000  + 0x100000) ;
-
-  _text = .;
-  .text : AT(ADDR(.text) - 0x0000000000000000 )
-    {
-	*(__ivt_section)
-	/* these are not really text pages, but the zero page needs to be in a fixed location: */
-	*(__special_page_section)
-	__start_gate_section = .;
-	*(__gate_section)
-	__stop_gate_section = .;
-	*(.text)
-    }
-
-  /* Global data */
-  _data = .;
-
-  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
-	{ *(.rodata) *(.rodata.*) }
-  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
-	{ *(.opd) }
-  .data : AT(ADDR(.data) - 0x0000000000000000 )
-	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
-
-  __gp = ALIGN (8) + 0x200000;
-
-  .got : AT(ADDR(.got) - 0x0000000000000000 )
-	{ *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
-	{ *(.sdata) }
-  _edata  =  .;
-  _bss = .;
-  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
-	{ *(.sbss) *(.scommon) }
-  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
-	{ *(.bss) *(COMMON) }
-  . = ALIGN(64 / 8);
-  _end = .;
-
-  /* Sections to be discarded */
-  /DISCARD/ : {
-	*(.text.exit)
-	*(.data.exit)
-	}
-
-  /* Stabs debugging sections.  */
-  .stab 0 : { *(.stab) }
-  .stabstr 0 : { *(.stabstr) }
-  .stab.excl 0 : { *(.stab.excl) }
-  .stab.exclstr 0 : { *(.stab.exclstr) }
-  .stab.index 0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* These must appear regardless of  .  */
-  /* Discard them for now since Intel SoftSDV cannot handle them.
-  .comment 0 : { *(.comment) }
-  .note 0 : { *(.note) }
-  */
-  /DISCARD/ : { *(.comment) }
-  /DISCARD/ : { *(.note) }
-}
diff -urN linux-2.4.16/arch/ia64/sn/fprom/fpromasm.S lia64-2.4/arch/ia64/sn/fprom/fpromasm.S
--- linux-2.4.16/arch/ia64/sn/fprom/fpromasm.S	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/fpromasm.S	Wed Dec 31 16:00:00 1969
@@ -1,314 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- *   (Code copied from or=ther files)
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#define __ASSEMBLY__ 1
-#include "asm/processor.h"
-
-/*
- * This file contains additional set up code that is needed to get going on
- * Medusa.  This code should disappear once real hw is available.
- *
- * On entry to this routine, the following register values are assumed:
- *
- *	gr[8]	- BSP cpu
- *	pr[9]	- kernel entry address
- *
- * NOTE:
- *   This FPROM may be loaded/executed at an address different from the
- *   address that it was linked at. The FPROM is linked to run on node 0
- *   at address 0x100000. If the code in loaded into another node, it
- *   must be loaded at offset 0x100000 of the node. In addition, the
- *   FPROM does the following things:
- *		- determine the base address of the node it is loaded on
- *		- add the node base to _gp.
- *		- add the node base to all addresses derived from "movl" 
- *		  instructions. (I couldnt get GPREL addressing to work)
- *		  (maybe newer versions of the tools will support this)
- *		- scan the .got section and add the node base to all
- *		  pointers in this section.
- *		- add the node base to all physical addresses in the
- *		  SAL/PAL/EFI table built by the C code. (This is done
- *		  in the C code - not here)
- *		- add the node base to the TLB entries for vmlinux
- */
-
-#define KERNEL_BASE	0xe000000000000000
-#define PAGESIZE_256M	28
-
-/* 
- * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
- * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
- * IOSPEC_BASE value
- */
-#define IOPB_PA		0x00000a0000000000 /* inv swizzle IOSPEC_BASE */
-
-#define RR_RID		8
-
-
-
-// ====================================================================================	
-        .text
-        .align 16
-	.global _start
-	.proc _start
-_start:
-
-// Setup psr and rse for system init
-	mov		psr.l = r0;;
-	srlz.d;;
-	invala
-	mov		ar.rsc = r0;;
-	loadrs
-	;;
-
-// Set CALIAS size to zero. We dont use it.
-	movl		r24=0x80000a0001000028;;	// BR_PI_CALIAS_SIZE
-	st8 		[r24]=r0
-
-// Isolate node number we are running on.
-	mov		r6 = ip;;
-	shr		r5 = r6,33;;			// r5 = node number
-	shl		r6 = r5,33			// r6 = base memory address of node
-
-// Set & relocate gp.
-	movl		r1= __gp;;			// Add base memory address
-	add 		r1 = r1,r6			// Relocate to boot node
-
-// Lets figure out who we are & put it in the LID register.
-// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
-// This identifies the cpu on the node. 
-// Merge the cpu number with the NASID to generate the LID.
-	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
-	ld8 		r25=[r24]			// Fetch PI_SELF
-	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
-	ld8 		r27=[r27];;
-	extr.u		r27=r27,32,8
-	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
-	shl 		r27=r27,24;;			// Align NASID to lid.id
-	or  		r26=r26,r27;;			// build the LID
-	mov 		cr.lid=r26			// Now put in in the LID register
-	
-	movl		r2=FPSR_DEFAULT;;
-	mov 		ar.fpsr=r2
-	movl		sp = bootstacke-16;;
-	add 		sp = sp,r6			// Relocate to boot node			
-
-// Save the NASID that we are loaded on.
-	movl		r2=base_nasid;;			// Save base_nasid for C code
-	add 		r2 = r2,r6;;			// Relocate to boot node
-  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
-
-// Save the kernel entry address. It is passed in r9 on one of
-// the cpus.
-	movl		r2=bsp_entry_pc
-	cmp.ne		p6,p0=r9,r0;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
-
-
-// The following can ONLY be done by 1 cpu. Lets set a lock - the
-// cpu that gets it does the initilization. The rest just spin waiting
-// til initilization is complete.
-	movl		r22 = initlock;;
-	add		r22 = r22,r6			// Relocate to boot node
-	mov		r23 = 1;;
-	xchg8		r23 = [r22],r23;;
-	cmp.eq 		p6,p0 = 0,r23
-(p6)	br.cond.spnt.few init
-1:	ld4		r23 = [r22];;
-	cmp.eq		p6,p0 = 1,r23
-(p6)	br.cond.sptk	1b
-	br		initx
-
-// Add base address of node memory to each pointer in the .got section.
-init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
-	add		r16 = r16,r6;;			// Relocate to boot node
-1: 	ld8		r17 = [r16];;
-	cmp.eq		p6,p7=0,r17
-(p6)	br.cond.sptk.few.clr 2f;;
-	add		r17 = r17,r6;;			// Relocate to boot node
-	st8		[r16] = r17,8
-	br		1b
-2:
-	mov		r23 = 2;;			// All done, release the spinning cpus
-	st4		[r22] = r23
-initx:
-
-//
-//	I/O-port space base address:
-//
-	movl		r2 = IOPB_PA;;
-	mov		ar.k0 = r2
-
-
-// Now call main & pass it the current LID value.
-	alloc 		r0=ar.pfs,0,0,2,0
-	mov    		r32=r26
-	mov   		r33=r8;;
-	br.call.sptk.few rp=fmain
-	
-// Initialize Region Registers
-//
-	mov		r10 = r0
-	mov		r2 = (13<<2) 
-	mov		r3 = r0;;
-1:	cmp4.gtu	p6,p7 = 7, r3
-	dep		r10 = r3, r10, 61, 3
-	dep		r2 = r3, r2, RR_RID, 4;;
-(p7)	dep		r2 = 0, r2, 0, 1;;
-(p6)	dep		r2 = -1, r2, 0, 1;;
-	mov		rr[r10] = r2
-	add		r3 = 1, r3;;
-	srlz.d;;
-	cmp4.gtu	p6,p0 = 8, r3
-(p6)	br.cond.sptk.few.clr 1b
-
-//
-// Return value indicates if we are the BSP or AP.
-// 	   1 = BSP, 0 = AP
-	mov             cr.tpr=r0;;
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.spnt	slave
-
-//
-// Initialize the protection key registers with only pkr[0] = valid.
-//
-// Should be initialized in accordance with the OS.
-//
-	mov		r2 = 1
-	mov		r3 = r0;;
-	mov		pkr[r3] = r2;;
-	srlz.d;;
-	mov		r2 = r0
-
-1:	add		r3 = r3, r0, 1;;		// increment PKR
-	cmp.gtu		p6, p0 = 16, r3;;
-(p6)	mov		pkr[r3] = r2
-(p6)	br.cond.sptk.few.clr 1b
-
-	mov		ar.rnat = r0			// clear RNAT register
-
-//
-// Setup system address translation for kernel
-//
-// Note: The setup of Kernel Virtual address space can be done by the
-// C code of the boot loader.
-//
-//
-
-#define LINUX_PAGE_OFFSET       0xe000000000000000
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define ITRGR(ed,ar,ma)         ((ed<<52) | (ar<<9) | (ma<<2) | 0x61)
-
-#define AR_RX                   1                       // RX permission
-#define AR_RW                   4                       // RW permission
-#define MA_WB                   0                       // WRITEBACK memory attribute
-
-#define TLB_PAGESIZE		28			// Use 256MB pages for now.
-	mov		r16=r5
-
-//
-//     text section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RX,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.i           itr[r0] = r10;;                   // Dropin ITR entry
-	srlz.i;;
-
-//
-//     data section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RW,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.d           dtr[r0] = r10;;                 // Dropin DTR entry
-	srlz.d;;
-
-
-
-
-//
-// Turn on address translation, interrupt collection, psr.ed, protection key.
-// Interrupts (PSR.i) are still off here.
-//
-
-	movl		r3 = (	IA64_PSR_BN | \
-				IA64_PSR_AC | \
-				IA64_PSR_IT | \
-				IA64_PSR_DB | \
-				IA64_PSR_DA | \
-				IA64_PSR_RT | \
-				IA64_PSR_DT | \
-				IA64_PSR_IC   \
-			     )
-	;;
-	mov		cr.ipsr = r3
-
-//
-// Go to kernel C startup routines
-//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
-//	This is the only way to set them.
-
-	movl		r2=bsp_entry_pc;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-	ld8		r2=[r2];;
-	mov		cr.iip = r2
-	srlz.d;;
-	rfi;;
-	.endp		_start
-
-// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
-// the place ap_entry points. No initialization is necessary - the kernel makes no
-// assumptions about state on this entry.
-//	Note: should verify that the interrupt we got was really the ap_wakeup
-//	      interrupt but this should not be an issue on medusa
-slave:
-	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
-	mov		r8=cr.irr0;;			// Check for interrupt pending.
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.sptk	slave;;
-
-	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
-	srlz.d;;
-	mov		cr.eoi=r0;;			// must write eoi to clear
-	movl		r8=ap_entry;;			// now jump to kernel entry
-	add 		r8 = r8,r6;;			// Relocate to boot node
-	ld8		r9=[r8],8;;
-	ld8		r1=[r8]
-	mov		b0=r9;;
-	br		b0
-
-// Here is the kernel stack used for the fake PROM
-	.bss
-	.align		16384
-bootstack:
-	.skip		16384
-bootstacke:
-initlock:
-	data4
diff -urN linux-2.4.16/arch/ia64/sn/fprom/fw-emu.c lia64-2.4/arch/ia64/sn/fprom/fw-emu.c
--- linux-2.4.16/arch/ia64/sn/fprom/fw-emu.c	Tue Jul 31 10:30:09 2001
+++ lia64-2.4/arch/ia64/sn/fprom/fw-emu.c	Wed Dec 31 16:00:00 1969
@@ -1,524 +0,0 @@
-/*
- * PAL & SAL emulation.
- *
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-#include <asm/efi.h>
-#include <asm/pal.h>
-#include <asm/sal.h>
-#include <asm/processor.h>
-#include <asm/acpi-ext.h>
-#include "fpmem.h"
-
-#define MB	(1024*1024UL)
-#define GB	(MB*1024UL)
-
-#define FPROM_BUG()		do {while (1);} while (0)
-#define MAX_NODES		128
-#define MAX_LSAPICS		512
-#define MAX_CPUS		512
-#define MAX_CPUS_NODE		4
-#define CPUS_PER_NODE		4
-#define CPUS_PER_FSB		2
-#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
-
-#define NUM_EFI_DESCS		2
-
-typedef union ia64_nasid_va {
-        struct {
-                unsigned long off   : 33;       /* intra-region offset */
-		unsigned long nasid :  7;	/* NASID */
-		unsigned long off2  : 21;	/* fill */
-                unsigned long reg   :  3;       /* region number */
-        } f;
-        unsigned long l;
-        void *p;
-} ia64_nasid_va;
-
-typedef struct {
-	unsigned long	pc;
-	unsigned long	gp;
-} func_ptr_t;
- 
-#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
-#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
-#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
-
-/*
- * The following variables are passed thru registersfrom the configuration file and
- * are set via the _start function.
- */
-long		base_nasid;
-long		num_cpus;
-long		bsp_entry_pc=0;
-long		num_nodes;
-long		app_entry_pc;
-int		bsp_lid;
-func_ptr_t	ap_entry;
-
-
-static efi_runtime_services_t    *efi_runtime_p;
-static char fw_mem[(  sizeof(efi_system_table_t)
-		    + sizeof(efi_runtime_services_t)
-		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
-		    + sizeof(struct ia64_sal_systab)
-		    + sizeof(struct ia64_sal_desc_entry_point)
-		    + sizeof(struct ia64_sal_desc_ap_wakeup)
-		    + sizeof(acpi_rsdp_t)
-		    + sizeof(acpi_rsdt_t)
-		    + sizeof(acpi_sapic_t)
-		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
-		    + (1+8*MAX_NODES)*(sizeof(efi_memory_desc_t))
-		    + sizeof(ia64_sal_desc_ptc_t) +
-		    + MAX_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
-		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
-		    + 1024)] __attribute__ ((aligned (8)));
-
-/*
- * Very ugly, but we need this in the simulator only.  Once we run on
- * real hw, this can all go away.
- */
-extern void pal_emulator_static (void);
-
-asm ("
-	.text
-	.proc pal_emulator_static
-pal_emulator_static:
-	mov r8=-1;;
-	cmp.eq p6,p7=6,r28;;		/* PAL_PTCE_INFO */
-(p7)	br.cond.sptk.few 1f
-	;;
-	mov r8=0			/* status = 0 */
-	movl r9=0x500000000		/* tc.base */
-	movl r10=0x0000000200000003	/* count[0], count[1] */
-	movl r11=0x1000000000002000	/* stride[0], stride[1] */
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=14,r28;;		/* PAL_FREQ_RATIOS */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0			/* status = 0 */
-	movl r9 =0x100000064		/* proc_ratio (1/100) */
-	movl r10=0x100000100		/* bus_ratio<<32 (1/256) */
-	movl r11=0x10000000a		/* itc_ratio<<32 (1/100) */
-
-1:	cmp.eq p6,p7=22,r28;;		/* PAL_MC_DRAIN */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=23,r28;;		/* PAL_MC_EXPECTED */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	br.cond.sptk.few rp
-	.endp pal_emulator_static\n");
-
-
-static efi_status_t
-efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
-{
-	if (tm) {
-		memset(tm, 0, sizeof(*tm));
-		tm->year = 2000;
-		tm->month = 2;
-		tm->day = 13;
-		tm->hour = 10;
-		tm->minute = 11;
-		tm->second = 12;
-	}
-
-	if (tc) {
-		tc->resolution = 10;
-		tc->accuracy = 12;
-		tc->sets_to_zero = 1;
-	}
-
-	return EFI_SUCCESS;
-}
-
-static void
-efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
-{
-	while(1);	/* Is there a pseudo-op to stop medusa */
-}
-
-static efi_status_t
-efi_success (void)
-{
-	return EFI_SUCCESS;
-}
-
-static efi_status_t
-efi_unimplemented (void)
-{
-	return EFI_UNSUPPORTED;
-}
-
-static long
-sal_emulator (long index, unsigned long in1, unsigned long in2,
-	      unsigned long in3, unsigned long in4, unsigned long in5,
-	      unsigned long in6, unsigned long in7)
-{
-	register long r9 asm ("r9") = 0;
-	register long r10 asm ("r10") = 0;
-	register long r11 asm ("r11") = 0;
-	long status;
-
-	/*
-	 * Don't do a "switch" here since that gives us code that
-	 * isn't self-relocatable.
-	 */
-	status = 0;
-	if (index == SAL_FREQ_BASE) {
-		switch (in1) {
-		      case SAL_FREQ_BASE_PLATFORM:
-			r9 = 500000000;
-			break;
-
-		      case SAL_FREQ_BASE_INTERVAL_TIMER:
-			/*
-			 * Is this supposed to be the cr.itc frequency
-			 * or something platform specific?  The SAL
-			 * doc ain't exactly clear on this...
-			 */
-			r9 = 700000000;
-			break;
-
-		      case SAL_FREQ_BASE_REALTIME_CLOCK:
-			r9 = 1;
-			break;
-
-		      default:
-			status = -1;
-			break;
-		}
-	} else if (index == SAL_SET_VECTORS) {
-		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
-			func_ptr_t	*fp;
-			fp = ADDR_OF(&ap_entry);
-			fp->pc = in2;
-			fp->gp = in3;
-		} else {
-			status = -1;
-		}
-		;
-	} else if (index == SAL_GET_STATE_INFO) {
-		;
-	} else if (index == SAL_GET_STATE_INFO_SIZE) {
-		;
-	} else if (index == SAL_CLEAR_STATE_INFO) {
-		;
-	} else if (index == SAL_MC_RENDEZ) {
-		;
-	} else if (index == SAL_MC_SET_PARAMS) {
-		;
-	} else if (index == SAL_CACHE_FLUSH) {
-		;
-	} else if (index == SAL_CACHE_INIT) {
-		;
-	} else if (index == SAL_UPDATE_PAL) {
-		;
-	} else {
-		status = -1;
-	}
-	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
-	return status;
-}
-
-
-/*
- * This is here to work around a bug in egcs-1.1.1b that causes the
- * compiler to crash (seems like a bug in the new alias analysis code.
- */
-void *
-id (long addr)
-{
-	return (void *) addr;
-}
-
-
-/*
- * Fix the addresses in a function pointer by adding base node address
- * to pc & gp.
- */
-void
-fix_function_pointer(void *fp)
-{
-	func_ptr_t	*_fp;
-
-	_fp = fp;
-	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
-	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
-}
-
-void
-fix_virt_function_pointer(void *fptr)
-{
-        func_ptr_t      *fp;
-
-        fp = fptr;
-        fp->pc = fp->pc | PAGE_OFFSET;
-        fp->gp = fp->gp | PAGE_OFFSET;
-}
-
-
-int
-efi_set_virtual_address_map(void)
-{
-        efi_runtime_services_t            *runtime;
-
-        runtime = efi_runtime_p;
-        fix_virt_function_pointer((void*)runtime->get_time);
-        fix_virt_function_pointer((void*)runtime->set_time);
-        fix_virt_function_pointer((void*)runtime->get_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_virtual_address_map);
-        fix_virt_function_pointer((void*)runtime->get_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_variable);
-        fix_virt_function_pointer((void*)runtime->set_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_high_mono_count);
-        fix_virt_function_pointer((void*)runtime->reset_system);
-        return EFI_SUCCESS;;
-}
-
-
-void
-sys_fw_init (const char *args, int arglen, int bsp)
-{
-	/*
-	 * Use static variables to keep from overflowing the RSE stack
-	 */
-	static efi_system_table_t *efi_systab;
-	static efi_runtime_services_t *efi_runtime;
-	static efi_config_table_t *efi_tables;
-	static ia64_sal_desc_ptc_t *sal_ptc;
-	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
-	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
-	static acpi_rsdp_t *acpi_systab;
-	static acpi_rsdt_t *acpi_rsdt;
-	static acpi_sapic_t *acpi_sapic;
-	static acpi_entry_lsapic_t *acpi_lsapic;
-	static struct ia64_sal_systab *sal_systab;
-	static efi_memory_desc_t *efi_memmap, *md;
-	static unsigned long *pal_desc, *sal_desc;
-	static struct ia64_sal_desc_entry_point *sal_ed;
-	static struct ia64_boot_param *bp;
-	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
-	static unsigned char checksum = 0;
-	static char *cp, *cmd_line, *vendor;
-	static int mdsize, domain, last_domain ;
-	static int cnode, nasid, cpu, num_memmd, cpus_found;
-
-	/*
-	 * Pass the parameter base address to the build_efi_xxx routines.
-	 */
-	build_init(8LL*GB*base_nasid);
-
-	num_nodes = GetNumNodes();
-	num_cpus = GetNumCpus();
-
-
-	memset(fw_mem, 0, sizeof(fw_mem));
-
-	pal_desc = (unsigned long *) &pal_emulator_static;
-	sal_desc = (unsigned long *) &sal_emulator;
-	fix_function_pointer(&pal_emulator_static);
-	fix_function_pointer(&sal_emulator);
-
-	/* Align this to 16 bytes, probably EFI does this  */
-	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
-
-	cp = fw_mem;
-	efi_systab  = (void *) cp; cp += sizeof(*efi_systab);
-	efi_runtime_p = efi_runtime = (void *) cp; cp += sizeof(*efi_runtime);
-	efi_tables  = (void *) cp; cp += NUM_EFI_DESCS*sizeof(*efi_tables);
-	sal_systab  = (void *) cp; cp += sizeof(*sal_systab);
-	sal_ed      = (void *) cp; cp += sizeof(*sal_ed);
-	sal_ptc     = (void *) cp; cp += sizeof(*sal_ptc);
-	sal_apwake  = (void *) cp; cp += sizeof(*sal_apwake);
-	acpi_systab = (void *) cp; cp += sizeof(*acpi_systab);
-	acpi_rsdt   = (void *) cp; cp += sizeof(*acpi_rsdt);
-	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
-	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
-	vendor 	    = (char *) cp; cp += 32;
-	efi_memmap  = (void *) cp; cp += 8*32*sizeof(*efi_memmap);
-	sal_ptcdi   = (void *) cp; cp += CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi);
-	sal_ptclid  = (void *) cp; cp += ((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8;
-	cmd_line    = (void *) cp;
-
-	if (args) {
-		if (arglen >= 1024)
-			arglen = 1023;
-		memcpy(cmd_line, args, arglen);
-	} else {
-		arglen = 0;
-	}
-	cmd_line[arglen] = '\0';
-#ifdef BRINGUP
-	/* for now, just bring up bash */
-	strcpy(cmd_line, "init=/bin/bash");
-#else
-	strcpy(cmd_line, "");
-#endif
-
-	memset(efi_systab, 0, sizeof(efi_systab));
-	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
-	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
-	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
-	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
-	efi_systab->fw_revision = 1;
-	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
-	efi_systab->nr_tables = 2;
-	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
-	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 32);
-
-	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
-	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
-	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
-	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
-	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
-	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
-
-	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
-	efi_tables++;
-	efi_tables->guid = ACPI_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, acpi_systab);
-	fix_function_pointer(&efi_unimplemented);
-	fix_function_pointer(&efi_get_time);
-	fix_function_pointer(&efi_success);
-	fix_function_pointer(&efi_reset_system);
-	fix_function_pointer(&efi_set_virtual_address_map);
-
-	/* fill in the ACPI system table: */
-	memcpy(acpi_systab->signature, "RSD PTR ", 8);
-	acpi_systab->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
-
-	memcpy(acpi_rsdt->header.signature, "RSDT",4);
-	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
-	memcpy(acpi_rsdt->header.oem_id, "SGI", 3);
-	memcpy(acpi_rsdt->header.oem_table_id, "SN1", 3);
-	acpi_rsdt->header.oem_revision = 0x00010001;
-	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
-
-	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
-	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
-			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
-			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
-			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
-			acpi_lsapic->eid = cpu;
-			acpi_lsapic->id = nasid;
-			acpi_lsapic++;
-		}
-	}
-
-
-	/* fill in the SAL system table: */
-	memcpy(sal_systab->signature, "SST_", 4);
-	sal_systab->size = sizeof(*sal_systab);
-	sal_systab->sal_rev_minor = 1;
-	sal_systab->sal_rev_major = 0;
-	sal_systab->entry_count = 3;
-
-	strcpy(sal_systab->oem_id, "SGI");
-	strcpy(sal_systab->product_id, "SN1");
-
-	/* fill in an entry point: */	
-	sal_ed->type = SAL_DESC_ENTRY_POINT;
-	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
-	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
-	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
-
-	/* kludge the PTC domain info */
-	sal_ptc->type = SAL_DESC_PTC;
-	sal_ptc->num_domains = 0;
-	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
-	cpus_found = 0;
-	last_domain = -1;
-	sal_ptcdi--;
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (IsCpuPresent(cnode, cpu)) {
-				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
-				if (domain != last_domain) {
-					sal_ptc->num_domains++;
-					sal_ptcdi++;
-					sal_ptcdi->proc_count = 0;
-					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
-					last_domain = domain;
-				}
-				sal_ptcdi->proc_count++;
-				sal_ptclid->id = nasid;
-				sal_ptclid->eid = cpu;
-				sal_ptclid++;
-				cpus_found++;
-			}
-		}
-	}
-
-	if (cpus_found != num_cpus)
-		FPROM_BUG();
-
-	/* Make the AP WAKEUP entry */
-	sal_apwake->type = SAL_DESC_AP_WAKEUP;
-	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
-	sal_apwake->vector = 18;
-
-	for (cp = (char *) sal_systab; cp < (char *) efi_memmap; ++cp)
-		checksum += *cp;
-
-	sal_systab->checksum = -checksum;
-
-	md = &efi_memmap[0];
-	num_memmd = build_efi_memmap((void *)md, mdsize) ;
-
-	bp = id(ZERO_PAGE_ADDR + (((long)base_nasid)<<33));
-	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
-	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
-	bp->efi_memmap_size = num_memmd*mdsize;
-	bp->efi_memdesc_size = mdsize;
-	bp->efi_memdesc_version = 0x101;
-	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
-	bp->console_info.num_cols = 80;
-	bp->console_info.num_rows = 25;
-	bp->console_info.orig_x = 0;
-	bp->console_info.orig_y = 24;
-	bp->num_pci_vectors = 0;
-	bp->fpswa = 0;
-
-	/*
-	 * Now pick the BSP & store it LID value in
-	 * a global variable. Note if BSP is greater than last cpu,
-	 * pick the last cpu.
-	 */
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
-			if (bsp-- > 0)
-				continue;
-			return;
-		}
-	}
-}
diff -urN linux-2.4.16/arch/ia64/sn/fprom/main.c lia64-2.4/arch/ia64/sn/fprom/main.c
--- linux-2.4.16/arch/ia64/sn/fprom/main.c	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/main.c	Wed Dec 31 16:00:00 1969
@@ -1,110 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <linux/types.h>
-#include <asm/bitops.h>
-
-void bedrock_init(int);
-void synergy_init(int, int);
-void sys_fw_init (const char *args, int arglen, int bsp);
-
-volatile int	bootmaster=0;		/* Used to pick bootmaster */
-volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
-int		init_done=0;
-extern int	bsp_lid;
-
-#define get_bit(b,p)	(((*p)>>(b))&1)
-
-int
-fmain(int lid, int bsp) {
-	int	syn, nasid, cpu;
-
-	/*
-	 * First lets figure out who we are. This is done from the
-	 * LID passed to us.
-	 */
-	nasid = (lid>>24);
-	syn = (lid>>17)&1;
-	cpu = (lid>>16)&1;
-
-	/*
-	 * Now pick a synergy master to initialize synergy registers.
-	 */
-	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
-		synergy_init(nasid, syn);
-		test_and_set_bit(syn+2, &nasidmaster[nasid]);
-	} else
-		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
-	
-	/*
-	 * Now pick a nasid master to initialize Bedrock registers.
-	 */
-	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
-		bedrock_init(nasid);
-		test_and_set_bit(9, &nasidmaster[nasid]);
-	} else
-		while (get_bit(9, &nasidmaster[nasid]) == 0);
-	
-
-	/*
-	 * Now pick a BSP & finish init.
-	 */
-	if (test_and_set_bit(0, &bootmaster) == 0) {
-		sys_fw_init(0, 0, bsp);
-		test_and_set_bit(1, &bootmaster);
-	} else
-		while (get_bit(1, &bootmaster) == 0);
-
-	return (lid == bsp_lid);
-}
-
-
-void
-bedrock_init(int nasid)
-{
-	nasid = nasid;		/* to quiet gcc */
-}
-
-
-void
-synergy_init(int nasid, int syn)
-{
-	long	*base;
-	long	off;
-
-	/*
-	 * Enable all FSB flashed interrupts.
-	 * ZZZ - I'd really like defines for this......
-	 */
-	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
-	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
-		*(base+off/8) = -1LL;
-
-	/*
-	 * Set the NASID in the FSB_CONFIG register.
-	 */
-	base = (long*)0x80000e0000000450LL;
-	*base = (long)((nasid<<16)|(syn<<9));
-}
-
-
-/* Why isnt there a bcopy/memcpy in lib64.a */
-
-void* 
-memcpy(void * dest, const void *src, size_t count)
-{
-	char *s, *se, *d;
-
-	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
-		*d = *s;
-	return dest;
-}
diff -urN linux-2.4.16/arch/ia64/sn/fprom/runsim lia64-2.4/arch/ia64/sn/fprom/runsim
--- linux-2.4.16/arch/ia64/sn/fprom/runsim	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/fprom/runsim	Wed Dec 31 16:00:00 1969
@@ -1,372 +0,0 @@
-#!/bin/sh
-
-# Script for running PROMs and LINUX kernwls on medusa. 
-# Type "sim -H" for instructions.
-
-MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
-
-# ------------------ err -----------------------
-err() {
-	echo "ERROR - $1"
-	exit 1
-}
-
-# ----------------  help ----------------------
-help() {
-cat <<END
-Script for running a PROM or LINUX kernel under medusa.
-This script creates a control file, creates links to the appropriate
-linux/prom files, and/or calls medusa to make simulation runs.
-
-Usage:  
-   Initial setup:
-   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
-		-p	Create PROM control file & links
-		-k	Create LINUX control file & links
-		-c<cf>	Control file name				[Default: cf]
-		<work_dir> Path to directory that contains the linux or PROM files.
-		    The directory can be any of the following:
-		       (linux simulations)
-		       		worktree
-				worktree/linux
-				any directory with vmlinux, vmlinux.sym & fprom files
-			(prom simulations)
-				worktree
-				worktree/stand/arcs/IP37prom/dev
-				any directory with fw.bin & fw.sim files
-
-    Simulations:
-	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
-		-c<cf>	Control file name				[Default: cf]
-		-M	Pipe output thru fmtmedusa
-		-o	Output filename (copy of all commands/output)	[Default: simout]
-		-X	Specifies number of instructions to execute	[Default: 0]
-			(Used only in auto test mode - not described here)
-
-Examples:
-	sim -p <promtree>	# create control file (cf) & links for prom simulations
-	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
-	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
-
-	sim			# run medusa using previously created links &
-				#   control file (cf).
-END
-exit 1
-}
-
-# ----------------------- create control file header --------------------
-create_cf_header() {
-cat <<END >>$CF
-#
-# Template for a control file for running linux kernels under medusa. 
-# You probably want to make mods here but this is a good starting point.
-#
-
-# Preferences
-setenv cpu_stepping A
-setenv exceptionPrint off
-setenv interrupt_messages off
-setenv lastPCsize 100000
-setenv low_power_mode on
-setenv partialIntelChipSet on
-setenv printIntelMessages off
-setenv prom_write_action halt
-setenv prom_write_messages on
-setenv step_quantum 100
-setenv swizzling on
-setenv tsconsole on
-setenv uart_echo on
-symbols on
-
-# IDE disk params
-setenv diskCylinders 611
-setenv bootDrive C
-setenv diskHeads 16
-setenv diskPath idedisk
-setenv diskPresent 1
-setenv diskSpt 63
-
-# Hardware config
-setenv coherency_type nasid
-setenv cpu_cache_type default
-setenv synergy_cache_type syn_cac_64m_8w
-
-# Numalink config
-setenv route_enable on
-setenv network_type xbar		# Select [xbar|router]
-setenv network_warning 0xff
-
-END
-}
-
-
-# ------------------ create control file entries for linux simulations -------------
-create_cf_linux() {
-cat <<END >>$CF
-# Kernel specific options
-setenv mca_on_memory_failure off
-setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
-sr g 9 0xe000000000520000		# Kernel entry point
-setenv symbol_table vmlinux.sym
-load fprom
-load vmlinux
-
-# Useful breakpoints to always have set. Add more if desired.
-break 0xe000000000505e00	all	# dispatch_to_fault_handler
-break panic			all	# stop on panic
-break die_if_kernel		all	# may as well stop
-
-END
-}
-
-# ------------------ create control file entries for prom simulations ---------------
-create_cf_prom() {
-	SYM2=""
-	ADDR="0x80000000ff800000"
-	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
-	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
-	cat <<END >>$CF
-# PROM specific options
-setenv mca_on_memory_failure on
-setenv LOADPC 0x80000000ffffffb0
-setenv promFile fw.bin
-setenv promAddr $ADDR
-setenv symbol_table fw.sym
-$SYM2
-
-# Useful breakpoints to always have set. Add more if desired.
-break Pr_ivt_gexx 		all
-break Pr_ivt_brk		all
-break Pr_PROM_Panic_Spin	all
-break Pr_PROM_Panic		all
-break Pr_PROM_C_Panic		all
-break Pr_fled_die		all
-break Pr_ResetNow		all
-break Pr_zzzbkpt		all
-
-END
-}
-
-
-# ------------------ create control file entries for memory configuration -------------
-create_cf_memory() {
-cat <<END >>$CF
-# CPU/Memory map format:
-#	setenv nodeN_memory_config 0xBSBSBSBS
-#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
-#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
-#		  rightmost digits are for bank 0, the lowest address.
-#	setenv nodeN_nasid <nasid>
-#		specifies the NASID for the node. This is used ONLY if booting the kernel.
-#		On PROM configurations, set to 0 - PROM will change it later.
-#	setenv nodeN_cpu_config <cpu_mask>
-#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
-#
-# Repeat the above 3 commands for each node.
-#
-# For kernel, default to 32MB. Although this is not a valid hardware configuration,
-# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
-
-setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
-END
-
-if [ $LINUX -eq 1 ] ; then
-cat <<END >>$CF
-setenv node0_nasid		0	# cnode 0 has NASID 0
-setenv node0_memory_config 	0xe1	# 32MB
-END
-else
-cat <<END >>$CF
-setenv node0_memory_config 	0x11	# 64MB
-END
-fi
-}
-
-# -------------------- set links to linux files -------------------------
-set_linux_links() {
-	if [ -d $D/linux/arch ] ; then
-		D=$D/linux
-	elif [ -d $D/arch -o -e vmlinux.sym ] ; then
-		D=$D
-	else
-		err "cant determine directory for linux binaries"
-	fi
-	rm -rf vmlinux vmlinux.sym fprom
-	ln -s $D/vmlinux vmlinux
-	ln -s $D/vmlinux.sym vmlinux.sym
-	if [ -d $D/arch ] ; then
-		ln -s $D/arch/ia64/sn/fprom/fprom fprom
-	else
-		ln -s $D/fprom fprom
-	fi
-	echo "  .. Created links to linux files"	
-}
-
-# -------------------- set links to prom files -------------------------
-set_prom_links() {
-	if [ -d $D/stand ] ; then
-		D=$D/stand/arcs/IP37prom/dev
-	elif [ -d $D/sal ] ; then
-		D=$D
-	else
-		err "cant determine directory for PROM binaries"
-	fi
-	SETUP="$D/../../../../.setup"
-	grep -q '^ *setenv *PROMSIZE *8MB' $SETUP
-	if [ $? -eq 0 ] ; then
-		SIZE="8MB"
-	else
-		SIZE="4MB"
-	fi
-	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
-	EMBEDDED_LINUX=$?
-	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom
-	SDIR="SN1IA${SIZE}.O"
-	BIN="SN1IAip37prom${SIZE}"
-	ln -s $D/$SDIR/$BIN.bin fw.bin
-	ln -s $D/$SDIR/$BIN.map fw.map
-	ln -s $D/$SDIR/$BIN.sym fw.sym
-	echo "  .. Created links to $SIZE prom files"
-	if [ $EMBEDDED_LINUX -eq 0 ] ; then
-		ln -s $D/linux/vmlinux vmlinux
-		ln -s $D/linux/vmlinux.sym vmlinux.sym
-		if [ -d linux/arch ] ; then
-			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
-		else
-			ln -s $D/linux/fprom fprom
-		fi
-		echo "  .. Created links to embedded linux files in prom tree"
-	fi
-}
-
-# --------------- start of shell script --------------------------------
-OUT="simout"
-FMTMED=0
-STEPCNT=0
-PROM=0
-LINUX=0
-NCF="cf"
-while getopts "HMX:c:o:pk" c ; do
-        case ${c} in
-                H) help;;
-		M) FMTMED=1;;
-		X) STEPCNT=${OPTARG};;
-		c) NCF=${OPTARG};;
-		k) PROM=0;LINUX=1;;
-		p) PROM=1;LINUX=0;;
-		o) OUT=${OPTARG};;
-                \?) exit 1;;
-        esac
-done
-shift `expr ${OPTIND} - 1`
-
-# Check if command is for creating control file and/or links to images.
-if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
-	CF=$NCF
-	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
-	if [ $# -gt 0 ] ; then
-		D=$1
-		[ -d $D ] || err "cannot find directory $D"
-		[ $PROM -eq 0 ]  || set_prom_links
-		[ $LINUX -eq 0 ] || set_linux_links
-	fi
-	create_cf_header
-	[ $PROM -eq 0 ]  || create_cf_prom
-	[ $LINUX -eq 0 ] || create_cf_linux
-	create_cf_memory
-	echo "  .. Basic control file created (in $CF). You might want to edit"
-	echo "     this file (at least, look at it)."
-	exit 0
-fi
-
-# Verify that the control file exists
-CF=${1:-$NCF}
-[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
-
-# Build the .cf files from the user control file. The .cf file is
-# identical except that the actual start & load addresses are inserted
-# into the file. In addition, the FPROM commands for configuring memory
-# and LIDs are generated. 
-
-rm -f .cf .cf1 .cf2
-awk '
-function strtonum(n) {
-	 if (substr(n,1,2) != "0x")
-	 	return int(n)
-	 n = substr(n,3)
-	 r=0
-	 while (length(n) > 0) {
-	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
-		n = substr(n,2)
-	 }
-	 return r
-	}
-/^#/   	{next}
-/^$/	{next}
-/^setenv *LOADPC/               {loadpc = $3; next}
-/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
-/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
-/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
-		{print}
-END	{
-	 # Generate the memmap info that starts at the beginning of
-	 # the node the kernel was loaded on.
-	 loadnasid = nasid[0]
-	 cnode = 0
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
-				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
-			cnodes++
-			cpus += substr("0112122312232334", cpuconf[i]+1,1)
-		}
-	 }
-	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
-	 printf "setenv number_of_nodes %d\n", cnodes
-
-	 # Now set the starting PC for each cpu.
-	 cnode = 0
-	 lowcpu=-1
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "setnode %d\n", cnode
-			conf = cpuconf[i]
-			for (j=0; j<4; j++) {
-				if (conf != int(conf/2)*2) {
-	 				printf "setcpu %d\n", j
-					if (length(loadpc) == 18)
-						printf "sr pc %s\n", loadpc
-					else
-						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
-					if (lowcpu == -1)
-						lowcpu = j
-				}
-				conf = int(conf/2)
-			}
-			cnode++
-		}
-	 }
-	 printf "setnode 0\n"
-	 printf "setcpu %d\n", lowcpu
-	}
-' <$CF >.cf
-
-# Now build the .cf1 & .cf2 control files.
-CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
-egrep  "$CF2_LINES" .cf >.cf2
-egrep -v "$CF2_LINES" .cf >.cf1
-if [ $STEPCNT -ne 0 ] ; then
-	echo "s $STEPCNT" >>.cf2
-	echo "lastpc 1000" >>.cf2
-	echo "q" >>.cf2
-fi
-echo "script-on $OUT" >>.cf2
-
-# Now start medusa....
-if [ $FMTMED -ne 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
-elif [ $STEPCNT -eq 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
-else
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
-fi
diff -urN linux-2.4.16/arch/ia64/sn/io/Makefile lia64-2.4/arch/ia64/sn/io/Makefile
--- linux-2.4.16/arch/ia64/sn/io/Makefile	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/Makefile	Mon Nov 19 23:22:51 2001
@@ -3,7 +3,7 @@
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
-# Copyright (C) 2000 Silicon Graphics, Inc.
+# Copyright (C) 2000-2001 Silicon Graphics, Inc.
 # Copyright (C) Jack Steiner (steiner@sgi.com)
 #
 #
@@ -15,18 +15,34 @@
 #
 # Note 2! The CFLAGS definitions are now in the main makefile...
 
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
+EXTRA_CFLAGS	:= -DSN -I. -DBRINGUP \
+		   -DNUMA_BASE -DSIMULATED_KLGRAPH \
+		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN
+# -DSN1_IOPORTS
 O_TARGET := sgiio.o
-obj-y   := stubs.o sgi_if.o pciio.o pcibr.o xtalk.o xbow.o xswitch.o hubspc.o \
-		klgraph_hack.o io.o hubdev.o huberror.o \
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = pciio.o hcl.o
+endif
+
+obj-y  := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \
 		hcl.o labelcl.o invent.o klgraph.o klconflib.o sgi_io_sim.o \
 		module.o sgi_io_init.o klgraph_hack.o ml_SN_init.o \
-		ml_SN_intr.o ip37.o pciba.o \
-		ml_iograph.o hcl_util.o cdl.o \
-		mem_refcnt.o devsupport.o alenlist.o pci_bus_cvlink.o \
-		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o
+		ml_iograph.o hcl_util.o cdl.o hubdev.o hubspc.o \
+		alenlist.o pci_bus_cvlink.o \
+		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o \
+		ifconfig_net.o efi-rtc.o io.o
+
+obj-$(CONFIG_IA64_SGI_SN1)   += sn1/ml_SN_intr.o sn1/mem_refcnt.o sn1/hubcounters.o \
+				sn1/ip37.o sn1/huberror.o sn1/hub_intr.o sn1/pcibr.o
+
+obj-$(CONFIG_IA64_SGI_SN2)   += sn2/ml_SN_intr.o sn2/shub_intr.o \
+				sn2/pcibr/pcibr_dvr.o sn2/pcibr/pcibr_ate.o \
+				sn2/pcibr/pcibr_config.o sn2/pcibr/pcibr_dvr.o \
+				sn2/pcibr/pcibr_hints.o \
+				sn2/pcibr/pcibr_idbg.o sn2/pcibr/pcibr_intr.o \
+				sn2/pcibr/pcibr_rrb.o sn2/pcibr/pcibr_slot.o 
+
+obj-$(CONFIG_PCIBA) += pciba.o
 
 include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/io/alenlist.c lia64-2.4/arch/ia64/sn/io/alenlist.c
--- linux-2.4.16/arch/ia64/sn/io/alenlist.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/alenlist.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /* Implementation of Address/Length Lists. */
@@ -13,9 +12,9 @@
 
 #include <linux/types.h>
 #include <linux/slab.h>
+#include <linux/mmzone.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/alenlist.h>
-#include <asm/sn/mmzone_sn1.h>
 
 /*
  * Logically, an Address/Length List is a list of Pairs, where each pair
@@ -218,9 +217,9 @@
 void
 alenlist_init(void)
 {
-	alenlist_zone = kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
-	alenlist_chunk_zone = kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
-	alenlist_cursor_zone = kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
+	alenlist_zone = snia_kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
+	alenlist_chunk_zone = snia_kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
+	alenlist_cursor_zone = snia_kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
 #if DEBUG
 	idbg_addfunc("alenshow", alenlist_show);
 #endif /* DEBUG */
@@ -250,7 +249,7 @@
 {
 	alenlist_t alenlist;
 
-	alenlist = kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	alenlist = snia_kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (alenlist) {
 		INCR_COUNT(&alenlist_count);
 
@@ -334,7 +333,7 @@
 		while (chunk) {
 			freechunk = chunk;
 			chunk = chunk->alc_next;
-			kmem_zone_free(alenlist_chunk_zone, freechunk);
+			snia_kmem_zone_free(alenlist_chunk_zone, freechunk);
 			DECR_COUNT(&alenlist_chunk_count);
 		}
 		alenlist->al_actual_size = ALEN_CHUNK_SZ;
@@ -407,7 +406,7 @@
 		alenlist_clear(alenlist);
 
 	/* Now, free the alenlist itself */
-	kmem_zone_free(alenlist_zone, alenlist);
+	snia_kmem_zone_free(alenlist_zone, alenlist);
 	DECR_COUNT(&alenlist_count);
 }
 
@@ -473,7 +472,7 @@
 			} else {
 				alenlist_chunk_t new_chunk;
 
-				new_chunk = kmem_zone_alloc(alenlist_chunk_zone, 
+				new_chunk = snia_kmem_zone_alloc(alenlist_chunk_zone, 
 							flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 
 				if (new_chunk == NULL)
@@ -656,7 +655,7 @@
 	alenlist_cursor_t cursorp;
 
 	ASSERT(alenlist != NULL);
-	cursorp = kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	cursorp = snia_kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (cursorp) {
 		INCR_COUNT(&alenlist_cursor_count);
 		alenlist_cursor_init(alenlist, 0, cursorp);
@@ -671,7 +670,7 @@
 alenlist_cursor_destroy(alenlist_cursor_t cursorp)
 {
 	DECR_COUNT(&alenlist_cursor_count);
-	kmem_zone_free(alenlist_cursor_zone, cursorp);
+	snia_kmem_zone_free(alenlist_cursor_zone, cursorp);
 }
 
 
@@ -752,7 +751,7 @@
 			maxlength -= 
 			   ((alenp->al_addr + cursorp->al_bcount) & maxlen1);
 
-		length = MIN(maxlength, length);
+		length = min(maxlength, length);
 	}
 
 	/* Update the cursor, if desired. */
@@ -842,7 +841,7 @@
 	offset = poff(kvaddr);
 
 	/* Handle first page */
-	piece_length = MIN(NBPP - offset, length);
+	piece_length = min(NBPP - offset, length);
 	if (alenlist_append(alenlist, paddr, piece_length, flags) == ALENLIST_FAILURE)
 		goto failure;
 	length -= piece_length;
diff -urN linux-2.4.16/arch/ia64/sn/io/ate_utils.c lia64-2.4/arch/ia64/sn/io/ate_utils.c
--- linux-2.4.16/arch/ia64/sn/io/ate_utils.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/ate_utils.c	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,206 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/ioerror_handling.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/sn_private.h>
+
+#define ulong_t uint64_t
+#include <asm/sn/ate_utils.h>
+
+/*
+ * Allocate the map needed to allocate the ATE entries.
+ */
+struct map *
+atemapalloc(ulong_t mapsiz)
+{
+	struct map *mp;
+	ulong_t size;
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	} *sync;
+
+	if (mapsiz == 0)
+		return(NULL);
+	size = sizeof(struct map) * (mapsiz + 2);
+	if ((mp = (struct map *) kmalloc(size, GFP_KERNEL)) == NULL)
+		return(NULL);
+	memset(mp, 0x0, size);
+
+	sync = kmalloc(sizeof(struct a), GFP_KERNEL);
+	if (sync == NULL) {
+		kfree(mp);
+		return(NULL);
+	}
+	memset(sync, 0x0, sizeof(struct a));
+
+	mutex_spinlock_init(&sync->lock);
+	sv_init( &(sync->sema), &(sync->lock), SV_MON_SPIN | SV_ORDER_FIFO /*| SV_INTS*/);
+	mp[1].m_size = (unsigned long) &sync->lock;
+	mp[1].m_addr = (unsigned long) &sync->sema;
+	mapsize(mp) = mapsiz - 1;
+	return(mp);
+}
+
+/*
+ * free a map structure previously allocated via rmallocmap().
+ */
+void
+atemapfree(struct map *mp)
+{
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	};
+	/* ASSERT(sv_waitq(mapout(mp)) == 0); */
+	/* sv_destroy(mapout(mp)); */
+	spin_lock_destroy(maplock(mp));
+	kfree((void *)mp[1].m_size);
+	kfree(mp);
+}
+
+/*
+ * Allocate 'size' units from the given map.
+ * Return the base of the allocated space.
+ * In a map, the addresses are increasing and the
+ * list is terminated by a 0 size.
+ * Algorithm is first-fit.
+ */
+
+ulong_t
+atealloc(
+	struct map *mp,
+	size_t size)
+{
+	register unsigned int a;
+	register struct map *bp;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return((ulong_t) NULL);
+
+	s = mutex_spinlock(maplock(mp));
+
+	for (bp = mapstart(mp); bp->m_size; bp++) {
+		if (bp->m_size >= size) {
+			a = bp->m_addr;
+			bp->m_addr += size;
+			if ((bp->m_size -= size) == 0) {
+				do {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+				} while ((((bp-1)->m_size) = (bp->m_size)));
+				mapsize(mp)++;
+			}
+
+			ASSERT(bp->m_size < 0x80000000);
+			mutex_spinunlock(maplock(mp), s);
+			return(a);
+		}
+	}
+
+	/*
+	 * We did not get what we need .. we cannot sleep .. 
+	 */
+	mutex_spinunlock(maplock(mp), s);
+	return(0);
+}
+
+/*
+ * Free the previously allocated space a of size units into the specified map.
+ * Sort ``a'' into map and combine on one or both ends if possible.
+ * Returns 0 on success, 1 on failure.
+ */
+void
+atefree(struct map *mp, size_t size, ulong_t a)
+{
+	register struct map *bp;
+	register unsigned int t;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return;
+
+	bp = mapstart(mp);
+	s = mutex_spinlock(maplock(mp));
+
+	for ( ; bp->m_addr<=a && bp->m_size!=0; bp++)
+		;
+	if (bp>mapstart(mp) && (bp-1)->m_addr+(bp-1)->m_size == a) {
+		(bp-1)->m_size += size;
+		if (bp->m_addr) {	
+			/* m_addr==0 end of map table */
+			ASSERT(a+size <= bp->m_addr);
+			if (a+size == bp->m_addr) { 
+
+				/* compress adjacent map addr entries */
+				(bp-1)->m_size += bp->m_size;
+				while (bp->m_size) {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+					(bp-1)->m_size = bp->m_size;
+				}
+				mapsize(mp)++;
+			}
+		}
+	} else {
+		if (a+size == bp->m_addr && bp->m_size) {
+			bp->m_addr -= size;
+			bp->m_size += size;
+		} else {
+			ASSERT(size);
+			if (mapsize(mp) == 0) {
+				mutex_spinunlock(maplock(mp), s);
+				printk("atefree : map overflow 0x%p Lost 0x%lx items at 0x%lx",
+						(void *)mp, size, a) ;
+				return ;
+			}
+			do {
+				t = bp->m_addr;
+				bp->m_addr = a;
+				a = t;
+				t = bp->m_size;
+				bp->m_size = size;
+				bp++;
+			} while ((size = t));
+			mapsize(mp)--;
+		}
+	}
+	mutex_spinunlock(maplock(mp), s);
+	/*
+	 * wake up everyone waiting for space
+	 */
+	if (mapout(mp))
+		;
+		/* sv_broadcast(mapout(mp)); */
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/cdl.c lia64-2.4/arch/ia64/sn/io/cdl.c
--- linux-2.4.16/arch/ia64/sn/io/cdl.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/cdl.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -17,11 +16,9 @@
 #include "asm/sn/ioerror_handling.h"
 #include <asm/sn/xtalk/xbow.h>
 
-#ifdef BRINGUP
 /* these get called directly in cdl_add_connpt in fops bypass hack */
 extern int pcibr_attach(devfs_handle_t);
 extern int xbow_attach(devfs_handle_t);
-#endif /* BRINGUP */
 
 /*
  *    cdl: Connection and Driver List
diff -urN linux-2.4.16/arch/ia64/sn/io/devsupport.c lia64-2.4/arch/ia64/sn/io/devsupport.c
--- linux-2.4.16/arch/ia64/sn/io/devsupport.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/devsupport.c	Wed Dec 31 16:00:00 1969
@@ -1,1289 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/iograph.h>
-
-/* 
- * Interfaces in this file are all platform-independent AND IObus-independent.
- * Be aware that there may be macro equivalents to each of these hiding in
- * header files which supercede these functions.
- */
-
-/* =====Generic iobus support===== */
-
-/* String table to hold names of interrupts. */
-#ifdef LATER
-static struct string_table device_desc_string_table;
-#endif
-
-/* One time initialization for device descriptor support. */
-static void
-device_desc_init(void)
-{
-#ifdef LATER
-	string_table_init(&device_desc_string_table);
-#endif
-	FIXME("device_desc_init");
-}
-
-
-/* Drivers use these interfaces to manage device descriptors */
-static device_desc_t
-device_desc_alloc(void)
-{
-#ifdef LATER
-	device_desc_t device_desc;
-
-	device_desc = (device_desc_t)kmem_zalloc(sizeof(struct device_desc_s), 0);
-	device_desc->intr_target = GRAPH_VERTEX_NONE;
-
-	ASSERT(device_desc->intr_policy == 0);
-	device_desc->intr_swlevel = -1;
-	ASSERT(device_desc->intr_name == NULL);
-	ASSERT(device_desc->flags == 0);
-
-	ASSERT(!(device_desc->flags & D_IS_ASSOC));
-	return(device_desc);
-#else
-	FIXME("device_desc_alloc");
-	return((device_desc_t)0);
-#endif
-}
-
-void
-device_desc_free(device_desc_t device_desc)
-{
-#ifdef LATER
-	if (!(device_desc->flags & D_IS_ASSOC)) /* sanity */
-		kfree(device_desc);
-#endif
-	FIXME("device_desc_free");
-}
-
-device_desc_t
-device_desc_dup(devfs_handle_t dev)
-{
-#ifdef LATER
-	device_desc_t orig_device_desc, new_device_desc;
-
-
-	new_device_desc = device_desc_alloc();
-	orig_device_desc = device_desc_default_get(dev);
-	if (orig_device_desc)
-		*new_device_desc = *orig_device_desc;/* small structure copy */
-	else {
-		device_driver_t		driver;
-		ilvl_t			pri;		
-		/* 
-		 * Use the driver's thread priority in 
-		 * case the device thread priority has not
-		 * been given.
-		 */
-		if (driver = device_driver_getbydev(dev)) {
-			pri = device_driver_thread_pri_get(driver);
-			device_desc_intr_swlevel_set(new_device_desc,pri);
-		}
-	}		
-	new_device_desc->flags &= ~D_IS_ASSOC;
-	return(new_device_desc);
-#else
-	FIXME("device_desc_dup");
-	return((device_desc_t)0);
-#endif
-}
-
-device_desc_t	
-device_desc_default_get(devfs_handle_t dev)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t device_desc;
-
-	rc = hwgraph_info_get_LBL(dev, INFO_LBL_DEVICE_DESC, (arbitrary_info_t *)&device_desc);
-
-	if (rc == GRAPH_SUCCESS)
-		return(device_desc);
-	else
-		return(NULL);
-#else
-	FIXME("device_desc_default_get");
-	return((device_desc_t)0);
-#endif
-}
-
-void		
-device_desc_default_set(devfs_handle_t dev, device_desc_t new_device_desc)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t old_device_desc = NULL;
-
-	if (new_device_desc) {
-		new_device_desc->flags |= D_IS_ASSOC;
-		rc = hwgraph_info_add_LBL(dev, INFO_LBL_DEVICE_DESC, 
-						(arbitrary_info_t)new_device_desc);
-		if (rc == GRAPH_DUP) {
-			rc = hwgraph_info_replace_LBL(dev, INFO_LBL_DEVICE_DESC, 
-				(arbitrary_info_t)new_device_desc, 
-				(arbitrary_info_t *)&old_device_desc);
-
-			ASSERT(rc == GRAPH_SUCCESS);
-		}
-		hwgraph_info_export_LBL(dev, INFO_LBL_DEVICE_DESC,
-					sizeof(struct device_desc_s));
-	} else {
-		rc = hwgraph_info_remove_LBL(dev, INFO_LBL_DEVICE_DESC,
-					(arbitrary_info_t *)&old_device_desc);
-	}
-
-	if (old_device_desc) {
-		ASSERT(old_device_desc->flags & D_IS_ASSOC);
-		old_device_desc->flags &= ~D_IS_ASSOC;
-		device_desc_free(old_device_desc);
-	}
-#endif
-	FIXME("device_desc_default_set");
-}
-
-devfs_handle_t
-device_desc_intr_target_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_target);
-#else
-	FIXME("device_desc_intr_target_get");
-	return((devfs_handle_t)0);
-#endif
-}
-
-int
-device_desc_intr_policy_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_policy);
-#else
-	FIXME("device_desc_intr_policy_get");
-	return(0);
-#endif
-}
-
-ilvl_t
-device_desc_intr_swlevel_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_swlevel);
-#else
-	FIXME("device_desc_intr_swlevel_get");
-	return((ilvl_t)0);
-#endif
-}
-
-char *
-device_desc_intr_name_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_name);
-#else
-	FIXME("device_desc_intr_name_get");
-	return(NULL);
-#endif
-}
-
-int
-device_desc_flags_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->flags);
-#else
-	FIXME("device_desc_flags_get");
-	return(0);
-#endif
-}
-
-void
-device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_target = target;
-}
-
-void
-device_desc_intr_policy_set(device_desc_t device_desc, int policy)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_policy = policy;
-}
-
-void
-device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_swlevel = swlevel;
-}
-
-void
-device_desc_intr_name_set(device_desc_t device_desc, char *name)
-{
-#ifdef LATER
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_name = string_table_insert(&device_desc_string_table, name);
-#else
-	FIXME("device_desc_intr_name_set");
-#endif
-}
-
-void
-device_desc_flags_set(device_desc_t device_desc, int flags)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->flags = flags;
-}
-
-
-
-/*============= device admin registry routines ===================== */
-
-/* Linked list of <admin-name,admin-val> pairs */
-typedef struct dev_admin_list_s {
-	struct dev_admin_list_s		*admin_next; 	/* next entry in the
-							 * list 
-							 */
-	char				*admin_name;	/* info label */
-	char				*admin_val;	/* actual info */
-} dev_admin_list_t;
-
-/* Device/Driver administration registry */
-typedef struct dev_admin_registry_s {
-	mrlock_t			reg_lock;	/* To allow
-							 * exclusive
-							 * access
-							 */
-	dev_admin_list_t		*reg_first;	/* first entry in 
-							 * the list
-							 */
-	dev_admin_list_t		**reg_last;	/* pointer to the
-							 * next to last entry
-							 * in the last which 
-							 * is also the place
-							 * where the new
-							 * entry gets
-							 * inserted
-							 */
-} dev_admin_registry_t;
-
-/*
-** device_driver_s associates a device driver prefix with device switch entries.
-*/
-struct device_driver_s {
-	struct device_driver_s	*dd_next;	/* next element on hash chain */
-	struct device_driver_s	*dd_prev;	/* previous element on hash chain */
-	char			*dd_prefix;	/* driver prefix string */
-	struct bdevsw		*dd_bdevsw;	/* driver's bdevsw */
-	struct cdevsw		*dd_cdevsw;	/* driver's cdevsw */
-	
-	/* driver administration specific data structures need to
-	 * maintain the list of <driver-paramater,value> pairs
-	 */
-	dev_admin_registry_t	dd_dev_admin_registry;
-	ilvl_t			dd_thread_pri;	/* default thread priority for
-						 *  all this driver's
-						 * threads.
-						 */
-
-};
-
-#define	NEW(_p)		(_p = kmalloc(sizeof(*_p), GFP_KERNEL))
-#define FREE(_p)	(kmem_free(_p))
-	
-/*
- * helpful lock macros
- */
-
-#define DEV_ADMIN_REGISTRY_INITLOCK(lockp,name)	mrinit(lockp,name)
-#define DEV_ADMIN_REGISTRY_RDLOCK(lockp)	mraccess(lockp)	       
-#define DEV_ADMIN_REGISTRY_WRLOCK(lockp)	mrupdate(lockp)	       
-#define DEV_ADMIN_REGISTRY_UNLOCK(lockp)	mrunlock(lockp)
-
-/* Initialize the registry 
- */
-static void
-dev_admin_registry_init(dev_admin_registry_t *registry)
-{
-#ifdef LATER
-	if ( registry != (dev_admin_registry_t *)0 )
-		DEV_ADMIN_REGISTRY_INITLOCK(&registry->reg_lock,
-				    "dev_admin_registry_lock");
-		registry->reg_first = NULL;
-		registry->reg_last = &registry->reg_first;
-	}
-#else
-	FIXME("dev_admin_registry_init");
-#endif
-}
-
-/*
- * add an <name , value > entry to the dev admin registry.
- * if the name already exists in the registry then change the
- * value iff the new value differs from the old value.
- * if the name doesn't exist a new list entry is created and put
- * at the end.
- */
-static void
-dev_admin_registry_add(dev_admin_registry_t	*registry,
-		       char			*name,
-		       char			*val)
-{
-#ifdef LATER
-	dev_admin_list_t	*reg_entry;
-	dev_admin_list_t	*scan = 0;
-
-	DEV_ADMIN_REGISTRY_WRLOCK(&registry->reg_lock);
-
-	/* check if the name already exists in the registry */
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			/* name is there in the registry */
-			if (strcmp(scan->admin_val,val)) {
-				/* old value != new value 
-				 * reallocate  memory and copy the new value
-				 */
-				FREE(scan->admin_val);
-				scan->admin_val = 
-					(char *)kern_calloc(1,strlen(val)+1);
-				strcpy(scan->admin_val,val);
-				goto out;
-			}
-			goto out;	/* old value == new value */
-		}
-		scan = scan->admin_next;
-	}
-
-	/* name is not there in the registry.
-	 * allocate memory for the new registry entry 
-	 */
-	NEW(reg_entry);
-	
-	reg_entry->admin_next   	= 0;
-	reg_entry->admin_name	= (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(reg_entry->admin_name,name);
-	reg_entry->admin_val	= (char *)kern_calloc(1,strlen(val)+1);
-	strcpy(reg_entry->admin_val,val);
-
-	/* add the entry at the end of the registry */
-
-	*(registry->reg_last)	= reg_entry;
-	registry->reg_last	= &reg_entry->admin_next;
-
-out:	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-#endif
-	FIXME("dev_admin_registry_add");
-}
-/*
- * check if there is an info corr. to a particular
- * name starting from the cursor position in the 
- * registry
- */
-static char *
-dev_admin_registry_find(dev_admin_registry_t *registry,char *name)
-{
-#ifdef LATER
-	dev_admin_list_t	*scan = 0;
-	
-	DEV_ADMIN_REGISTRY_RDLOCK(&registry->reg_lock);
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-			return scan->admin_val;
-		}
-		scan = scan->admin_next;
-	}
-	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-	return 0;
-#else
-	FIXME("dev_admin_registry_find");
-	return(NULL);
-#endif
-}
-/*============= MAIN DEVICE/ DRIVER ADMINISTRATION INTERFACE================ */
-/*
- * return any labelled info associated with a device.
- * called by any kernel code including device drivers.
- */
-char *
-device_admin_info_get(devfs_handle_t	dev_vhdl,
-		      char		*info_lbl)
-{
-#ifdef LATER
-	char		*info = 0;
-
-	/* return value need not be GRAPH_SUCCESS as the labelled
-	 * info may not be present
-	 */
-	(void)hwgraph_info_get_LBL(dev_vhdl,info_lbl,
-				   (arbitrary_info_t *)&info);
-
-	
-	return info;
-#else
-	FIXME("device_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device.
- * called by hwgraph infrastructure . may also be called
- * by device drivers etc.
- */
-int
-device_admin_info_set(devfs_handle_t	dev_vhdl,
-		      char		*dev_info_lbl,
-		      char		*dev_info_val)
-{
-#ifdef LATER
-	graph_error_t		rv;
-	arbitrary_info_t	old_info;
-
-	/* Handle the labelled info
-	 *		intr_target
-	 *		sw_level 
-	 * in a special way. These are part of device_desc_t
-	 * Right now this is the only case where we have 
-	 * a set of related device_admin attributes which 
-	 * are grouped together.
-	 * In case there is a need for another set we need to
-	 * take a more generic approach to solving this.
-	 * Basically a registry should be implemented. This
-	 * registry is initialized with the callbacks for the
-	 * attributes which need to handled in a special way
-	 * For example:
-	 * Consider
-	 * 		device_desc
-	 *			intr_target
-	 *			intr_swlevel
-	 * register "do_intr_target" for intr_target
-	 * register "do_intr_swlevel" for intr_swlevel.
-	 * When the device_admin interface layer gets an <attr,val> pair
-	 * it looks in the registry to see if there is a function registered to
-	 * handle "attr. If not follow the default path of setting the <attr,val>
-	 * as labelled information hanging off the vertex.
-	 * In the above example:
-	 * "do_intr_target" does what is being done below for the ADMIN_LBL_INTR_TARGET
-	 * case
-	 */		
-	if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET) ||
-	    !strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-
-		device_desc_t	device_desc;
-		
-		/* Check if there is a default device descriptor
-		 * information for this vertex. If not dup one .
-		 */
-		if (!(device_desc = device_desc_default_get(dev_vhdl))) {
-			device_desc = device_desc_dup(dev_vhdl);
-			device_desc_default_set(dev_vhdl,device_desc);
-
-		}
-		if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET)) {
-			/* Check if a target cpu has been specified
-			 * for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_TARGET
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " target = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       hwgraph_path_to_vertex(dev_info_val));
-#endif	
-
-			device_desc->intr_target = 
-				hwgraph_path_to_vertex(dev_info_val);
-		} else if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-			/* Check if the ithread priority level  has been 
-			 * specified for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_SWLEVEL
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " sw level = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       atoi(dev_info_val));
-#endif	
-			device_desc->intr_swlevel = atoi(dev_info_val);
-		}
-
-	}
-	if (!dev_info_val)
-		rv = hwgraph_info_remove_LBL(dev_vhdl,
-					     dev_info_lbl,
-					     &old_info);
-	else {
-
-		rv = hwgraph_info_add_LBL(dev_vhdl,
-					  dev_info_lbl,
-					  (arbitrary_info_t)dev_info_val);
-	
-		if (rv == GRAPH_DUP)  {
-			rv = hwgraph_info_replace_LBL(dev_vhdl,
-					      dev_info_lbl,
-					      (arbitrary_info_t)dev_info_val,
-					      &old_info);
-		}
-	}
-	ASSERT(rv == GRAPH_SUCCESS);
-#endif
-	FIXME("device_admin_info_set");
-	return 0;
-}
-
-/*
- * return labelled info associated with a device driver
- * called by kernel code including device drivers
- */
-char *
-device_driver_admin_info_get(char		*driver_prefix,
-			     char		*driver_info_lbl)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	return (dev_admin_registry_find(&driver->dd_dev_admin_registry,
-					driver_info_lbl));
-#else
-	FIXME("device_driver_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device driver.
- * called by hwgraph infrastructure . may also be called
- * from drivers etc.
- */
-int
-device_driver_admin_info_set(char		*driver_prefix,
-			     char		*driver_info_lbl,
-			     char		*driver_info_val)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	dev_admin_registry_add(&driver->dd_dev_admin_registry,	
-			       driver_info_lbl,
-			       driver_info_val);
-#endif
-	FIXME("device_driver_admin_info_set");
-	return 0;
-}
-/*================== device / driver  admin support routines================*/
-
-/* static tables created by lboot */
-extern dev_admin_info_t	dev_admin_table[];
-extern dev_admin_info_t	drv_admin_table[];
-extern int		dev_admin_table_size;
-extern int		drv_admin_table_size;
-
-/* Extend the device admin table to allow the kernel startup code to 
- * provide some device specific administrative hints
- */
-#define ADMIN_TABLE_CHUNK	100
-static dev_admin_info_t extended_dev_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_dev_admin_table_size = 0;
-static mrlock_t		extended_dev_admin_table_lock;
-
-/* Initialize the extended device admin table */
-void
-device_admin_table_init(void)
-{
-#ifdef LATER
-	extended_dev_admin_table_size = 0;
-	mrinit(&extended_dev_admin_table_lock,
-	       "extended_dev_admin_table_lock");
-#endif
-	FIXME("device_admin_table_init");
-}
-/* Add <device-name , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_dev_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_dev_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_dev_admin_table[extended_dev_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_dev_admin_table_lock);
-#endif
-	FIXME("device_admin_table_update");
-}
-/* Extend the device driver  admin table to allow the kernel startup code to 
- * provide some device driver specific administrative hints
- */
-
-static dev_admin_info_t extended_drv_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_drv_admin_table_size = 0;
-mrlock_t		extended_drv_admin_table_lock;
-
-/* Initialize the extended device driver admin table */
-void
-device_driver_admin_table_init(void)
-{
-#ifdef LATER
-	extended_drv_admin_table_size = 0;
-	mrinit(&extended_drv_admin_table_lock,
-	       "extended_drv_admin_table_lock");
-#endif
-	FIXME("device_driver_admin_table_init");
-}
-/* Add <device-driver prefix , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_driver_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_drv_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_drv_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_drv_admin_table[extended_drv_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_drv_admin_table_lock);
-#endif
-	FIXME("device_driver_admin_table_update");
-}
-/*
- * keeps on adding the labelled info for each new (lbl,value) pair
- * that it finds in the static dev admin table (  created by lboot)
- * and the extended dev admin table ( created if at all by the kernel startup
- *  code) corresponding to a device in the hardware graph.
- */
-void
-device_admin_info_update(devfs_handle_t	dev_vhdl)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-	devfs_handle_t		scan_vhdl;
-	
-	/* Check the static device administration info table */
-	scan = dev_admin_table;
-	while (i < dev_admin_table_size) {
-		
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-	i = 0;
-	/* Check the extended device administration info table */
-	scan = extended_dev_admin_table;
-	while (i < extended_dev_admin_table_size) {
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-
-
-#endif
-	FIXME("device_admin_info_update");
-}
-
-/* looks up the static drv admin table ( created by the lboot) and the extended
- * drv admin table (created if at all by the kernel startup code) 
- * for this driver specific administration info and adds it to the admin info 
- * associated with this device driver's object
- */
-void
-device_driver_admin_info_update(device_driver_t	driver)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-
-	/* Check the static device driver administration info table */
-	scan = drv_admin_table;
-	while (i < drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-	i = 0;
-	/* Check the extended device driver administration info table */
-	scan = extended_drv_admin_table;
-	while (i < extended_drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-#endif
-	FIXME("device_driver_admin_info_update");
-}
-
-/* =====Device Driver Support===== */
-
-
-
-/*
-** Generic device driver support routines for use by kernel modules that
-** deal with device drivers (but NOT for use by the drivers themselves).
-** EVERY registered driver currently in the system -- static or loadable --
-** has an entry in the device_driver_hash table.  A pointer to such an entry
-** serves as a generic device driver handle.
-*/
-
-#define DEVICE_DRIVER_HASH_SIZE 32
-#ifdef LATER
-lock_t device_driver_lock[DEVICE_DRIVER_HASH_SIZE];
-device_driver_t device_driver_hash[DEVICE_DRIVER_HASH_SIZE];
-static struct string_table driver_prefix_string_table;
-#endif
-
-/*
-** Initialize device driver infrastructure.
-*/
-void
-device_driver_init(void)
-{
-#ifdef LATER
-	int i;
-	extern void alenlist_init(void);
-	extern void hwgraph_init(void);
-	extern void device_desc_init(void);
-
-	ASSERT(DEVICE_DRIVER_NONE == NULL);
-	alenlist_init();
-	hwgraph_init();
-	device_desc_init();
-
-	string_table_init(&driver_prefix_string_table);
-
-	for (i=0; i<DEVICE_DRIVER_HASH_SIZE; i++) {
-		spin_lock_init(&device_driver_lock[i]);
-		device_driver_hash[i] = NULL;
-	}
-
-	/* Initialize static drivers from master.c table */
-	for (i=0; i<static_devsw_count; i++) {
-		device_driver_t driver;
-		static_device_driver_desc_t desc;
-		int pri;
-
-		desc = &static_device_driver_table[i];
-		driver = device_driver_get(desc->sdd_prefix);
-		if (!driver)
-			driver = device_driver_alloc(desc->sdd_prefix);
-		pri = device_driver_sysgen_thread_pri_get(desc->sdd_prefix);
-		device_driver_thread_pri_set(driver, pri);
-		device_driver_devsw_put(driver, desc->sdd_bdevsw, desc->sdd_cdevsw);
-	}
-#endif
-	FIXME("device_driver_init");
-}
-
-/*
-** Hash a prefix string into a hash table chain.
-*/
-static int
-driver_prefix_hash(char *prefix)
-{
-#ifdef LATER
-	int accum = 0;
-	char nextchar;
-
-	while (nextchar = *prefix++)
-		accum = accum ^ nextchar;
-
-	return(accum % DEVICE_DRIVER_HASH_SIZE);
-#else
-	FIXME("driver_prefix_hash");
-	return(0);
-#endif
-}
-
-
-/*
-** Allocate a driver handle.
-** Returns the driver handle, or NULL if the driver prefix 
-** already has a handle.
-** 
-** Upper layers prevent races among device_driver_alloc,
-** device_driver_free, and device_driver_get*.
-*/
-device_driver_t
-device_driver_alloc(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t new_driver;
-	unsigned long s;
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	new_driver = kern_calloc(1, sizeof(*new_driver));
-	ASSERT(new_driver != NULL);
-	new_driver->dd_prev = NULL;
-	new_driver->dd_prefix = string_table_insert(&driver_prefix_string_table, prefix);
-	new_driver->dd_bdevsw = NULL;
-	new_driver->dd_cdevsw = NULL;
-
-	dev_admin_registry_init(&new_driver->dd_dev_admin_registry);
-	device_driver_admin_info_update(new_driver);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we haven't already added a driver with this prefix */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && 
-		        strcmp(drvscan->dd_prefix, prefix)) {
-			drvscan = drvscan->dd_next;
-		}
-
-		ASSERT(!drvscan);
-	}
-#endif /* DEBUG */
-
-
-	/* Add new_driver to front of hash chain. */
-	new_driver->dd_next = device_driver_hash[which_hash];
-	if (new_driver->dd_next)
-		new_driver->dd_next->dd_prev = new_driver;
-	device_driver_hash[which_hash] = new_driver;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(new_driver);
-#else
-	FIXME("device_driver_alloc");
-	return((device_driver_t)0);
-#endif
-}
-
-/*
-** Free a driver handle.
-**
-** Statically loaded drivers should never device_driver_free.
-** Dynamically loaded drivers device_driver_free when either an
-** unloaded driver is unregistered, or when an unregistered driver
-** is unloaded.
-*/
-void
-device_driver_free(device_driver_t driver)
-{
-#ifdef LATER
-	int which_hash;
-	unsigned long s;
-
-	if (!driver)
-		return;
-
-	which_hash = driver_prefix_hash(driver->dd_prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we're dealing with the right list */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && (drvscan != driver))
-			drvscan = drvscan->dd_next;
-
-		ASSERT(drvscan);
-	}
-#endif /* DEBUG */
-
-	if (driver->dd_next)
-		driver->dd_next->dd_prev = driver->dd_prev;
-
-	if (driver->dd_prev)
-		driver->dd_prev->dd_next = driver->dd_next;
-	else
-		device_driver_hash[which_hash] = driver->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	driver->dd_next = NULL;		/* sanity */
-	driver->dd_prev = NULL;		/* sanity */
-	driver->dd_prefix = NULL;	/* sanity */
-
-	if (driver->dd_bdevsw) {
-		driver->dd_bdevsw->d_driver = NULL;
-		driver->dd_bdevsw = NULL;
-	}
-
-	if (driver->dd_cdevsw) {
-		if (driver->dd_cdevsw->d_str) {
-			str_free_mux_node(driver);
-		}
-		driver->dd_cdevsw->d_driver = NULL;
-		driver->dd_cdevsw = NULL;
-	}
-
-	kern_free(driver);
-#endif
-	FIXME("device_driver_free");
-}
-
-
-/*
-** Given a device driver prefix, return a handle to the caller.
-*/
-device_driver_t
-device_driver_get(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t drvscan;
-	unsigned long s;
-
-	if (prefix == NULL)
-		return(NULL);
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-	drvscan = device_driver_hash[which_hash];
-	while (drvscan && strcmp(drvscan->dd_prefix, prefix))
-		drvscan = drvscan->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(drvscan);
-#else
-	FIXME("device_driver_get");
-	return((device_driver_t)0);
-#endif
-}
-
-
-/*
-** Given a block or char special file devfs_handle_t, find the 
-** device driver that controls it.
-*/
-device_driver_t
-device_driver_getbydev(devfs_handle_t device)
-{
-#ifdef LATER
-	struct bdevsw *my_bdevsw;
-	struct cdevsw *my_cdevsw;
-
-	my_cdevsw = get_cdevsw(device);
-	if (my_cdevsw != NULL)
-		return(my_cdevsw->d_driver);
-
-	my_bdevsw = get_bdevsw(device);
-	if (my_bdevsw != NULL)
-		return(my_bdevsw->d_driver);
-
-#endif
-	FIXME("device_driver_getbydev");
-	return((device_driver_t)0);
-}
-
-
-/*
-** Associate a driver with bdevsw/cdevsw pointers.
-**
-** Statically loaded drivers are permanently and automatically associated
-** with the proper bdevsw/cdevsw.  Dynamically loaded drivers associate
-** themselves when the driver is registered, and disassociate when the
-** driver unregisters.
-**
-** Returns 0 on success, -1 on failure (devsw already associated with driver)
-*/
-int
-device_driver_devsw_put(device_driver_t driver,
-			struct bdevsw *my_bdevsw,
-			struct cdevsw *my_cdevsw)
-{
-#ifdef LATER
-	int i;
-
-	if (!driver)
-		return(-1);
-
-	/* Trying to re-register data?  */
-	if (((my_bdevsw != NULL) && (driver->dd_bdevsw != NULL)) ||
-	    ((my_cdevsw != NULL) && (driver->dd_cdevsw != NULL)))
-		return(-1);
-
-	if (my_bdevsw != NULL) {
-		driver->dd_bdevsw = my_bdevsw;
-		my_bdevsw->d_driver = driver;
-		for (i = 0; i < bdevmax; i++) {
-			if (driver->dd_bdevsw->d_flags == bdevsw[i].d_flags) {
-				bdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-
-	if (my_cdevsw != NULL) {
-		driver->dd_cdevsw = my_cdevsw;
-		my_cdevsw->d_driver = driver;
-		for (i = 0; i < cdevmax; i++) {
-			if (driver->dd_cdevsw->d_flags == cdevsw[i].d_flags) {
-				cdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-#endif
-	FIXME("device_driver_devsw_put");
-	return(0);
-}
-
-
-/*
-** Given a driver, return the corresponding bdevsw and cdevsw pointers.
-*/
-void
-device_driver_devsw_get(	device_driver_t driver, 
-				struct bdevsw **bdevswp,
-				struct cdevsw **cdevswp)
-{
-	if (!driver) {
-		*bdevswp = NULL;
-		*cdevswp = NULL;
-	} else {
-		*bdevswp = driver->dd_bdevsw;
-		*cdevswp = driver->dd_cdevsw;
-	}
-}
-
-/*
- * device_driver_thread_pri_set
- *	Given a driver try to set its thread priority.
- *	Returns 0 on success , -1 on failure.
- */ 
-int
-device_driver_thread_pri_set(device_driver_t driver,ilvl_t pri)
-{
-	if (!driver)
-		return(-1);
-	driver->dd_thread_pri = pri;
-	return(0);
-}
-/*
- * device_driver_thread_pri_get
- * 	Given a driver return the driver thread priority.
- * 	If the driver is NULL return invalid driver thread
- * 	priority.
- */
-ilvl_t
-device_driver_thread_pri_get(device_driver_t driver)
-{
-	if (driver)
-		return(driver->dd_thread_pri);
-	else
-		return(DRIVER_THREAD_PRI_INVALID);
-}
-/*
-** Given a device driver, return it's handle (prefix).
-*/
-void
-device_driver_name_get(device_driver_t driver, char *buffer, int length)
-{
-	if (driver == NULL)
-		return;
-
-	strncpy(buffer, driver->dd_prefix, length);
-}
-
-
-/*
-** Associate a pointer-sized piece of information with a device.
-*/
-void 
-device_info_set(devfs_handle_t device, void *info)
-{
-#ifdef LATER
-	hwgraph_fastinfo_set(device, (arbitrary_info_t)info);
-#endif
-	FIXME("device_info_set");
-}
-
-
-/*
-** Retrieve a pointer-sized piece of information associated with a device.
-*/
-void *
-device_info_get(devfs_handle_t device)
-{
-#ifdef LATER
-	return((void *)hwgraph_fastinfo_get(device));
-#else
-	FIXME("device_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * Find the thread priority for a device, from the various
- * sysgen files.
- */
-int
-device_driver_sysgen_thread_pri_get(char *dev_prefix)
-{
-#ifdef LATER
-	int pri;
-	char *pri_s;
-	char *class;
-
-	extern default_intr_pri;
-	extern disk_intr_pri;
-	extern serial_intr_pri;
-	extern parallel_intr_pri;
-	extern tape_intr_pri;
-	extern graphics_intr_pri;
-	extern network_intr_pri;
-	extern scsi_intr_pri;
-	extern audio_intr_pri;
-	extern video_intr_pri;
-	extern external_intr_pri;
-	extern tserialio_intr_pri;
-
-	/* Check if there is a thread priority specified for
-	 * this driver's thread thru admin hints. If so 
-	 * use that value. Otherwise set it to its default
-	 * class value, otherwise set it to the default
-	 * value.
-	 */
-
-	if (pri_s = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_PRI)) {
-		pri = atoi(pri_s);
-	} else if (class = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_CLASS)) {
-		if (strcmp(class, "disk") == 0)
-			pri = disk_intr_pri;
-		else if (strcmp(class, "serial") == 0)
-			pri = serial_intr_pri;
-		else if (strcmp(class, "parallel") == 0)
-			pri = parallel_intr_pri;
-		else if (strcmp(class, "tape") == 0)
-			pri = tape_intr_pri;
-		else if (strcmp(class, "graphics") == 0)
-			pri = graphics_intr_pri;
-		else if (strcmp(class, "network") == 0)
-			pri = network_intr_pri;
-		else if (strcmp(class, "scsi") == 0)
-			pri = scsi_intr_pri;
-		else if (strcmp(class, "audio") == 0)
-			pri = audio_intr_pri;
-		else if (strcmp(class, "video") == 0)
-			pri = video_intr_pri;
-		else if (strcmp(class, "external") == 0)
-			pri = external_intr_pri;
-		else if (strcmp(class, "tserialio") == 0)
-			pri = tserialio_intr_pri;
-		else
-			pri = default_intr_pri;
-	} else
-		pri = default_intr_pri;
-
-	if (pri > 255)
-		pri = 255;
-	else if (pri < 0)
-		pri = 0;
-	return pri;
-#else
-	FIXME("device_driver_sysgen_thread_pri_get");
-	return(-1);
-#endif
-}
diff -urN linux-2.4.16/arch/ia64/sn/io/eeprom.c lia64-2.4/arch/ia64/sn/io/eeprom.c
--- linux-2.4.16/arch/ia64/sn/io/eeprom.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/eeprom.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -46,19 +45,20 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
-/* #include <sys/SN/SN1/ip27log.h> */
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
 
 #if defined(EEPROM_DEBUG)
 #define db_printf(x) printk x
@@ -421,7 +421,7 @@
     }
     else {
 	scp = &sc;
-	sc_init( &sc, nasid, BRL1_LOCALUART );
+	sc_init( &sc, nasid, BRL1_LOCALHUB_UART );
     }
 
     /* fill in msg with the opcode & params */
@@ -1068,7 +1068,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_chassis_ia: bad checksum\n" ));
-	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%lx\n",
 			   sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
@@ -1199,7 +1199,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_board_ia: bad checksum\n" ));
-	db_printf(( "read_board_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_board_ia: target 0x%x  uart 0x%lx\n",
 		    sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
diff -urN linux-2.4.16/arch/ia64/sn/io/efi-rtc.c lia64-2.4/arch/ia64/sn/io/efi-rtc.c
--- linux-2.4.16/arch/ia64/sn/io/efi-rtc.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/efi-rtc.c	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2001 by Ralf Baechle
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <asm/efi.h>
+#include <asm/sn/klclock.h>
+
+/*
+ * No locking necessary when this is called from efirtc which protects us
+ * from racing by efi_rtc_lock.
+ */
+#define __swizzle(addr) ((u8 *)((unsigned long)(addr) ^ 3))
+#define read_io_port(addr) (*(volatile u8 *) __swizzle(addr))
+#define write_io_port(addr, data) (*(volatile u8 *) __swizzle(addr) = (data))
+
+#define TOD_SGS_M48T35		1
+#define TOD_DALLAS_DS1386	2
+
+static unsigned long nvram_base = 0;
+static int tod_chip_type;
+
+static int
+get_tod_chip_type(void)
+{
+	unsigned char testval;
+
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+	write_io_port(RTC_DAL_DAY_ADDR, 0xff);
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+
+	testval = read_io_port(RTC_DAL_DAY_ADDR);
+	if (testval == 0xff)
+		return TOD_SGS_M48T35;
+
+	return TOD_DALLAS_DS1386;
+}
+
+efi_status_t
+ioc3_get_time(efi_time_t *time, efi_time_cap_t *caps)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	memset(time, 0, sizeof(*time));
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_READ_PROTECT);
+
+		time->year = BCD_TO_INT(read_io_port(RTC_SGS_YEAR_ADDR)) + YRREF;
+		time->month = BCD_TO_INT(read_io_port(RTC_SGS_MONTH_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_SGS_DATE_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_SGS_HOUR_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_SGS_MIN_ADDR));
+		time->second = BCD_TO_INT(read_io_port(RTC_SGS_SEC_ADDR));
+		time->nanosecond = 0;
+
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+
+		time->nanosecond = 0;
+		time->second = BCD_TO_INT(read_io_port(RTC_DAL_SEC_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_DAL_MIN_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_DAL_HOUR_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_DAL_DATE_ADDR));
+		time->month = BCD_TO_INT(read_io_port(RTC_DAL_MONTH_ADDR));
+		time->year = BCD_TO_INT(read_io_port(RTC_DAL_YEAR_ADDR)) + YRREF;
+
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	if (caps) {
+		caps->resolution = 50000000;	/*  50PPM */
+		caps->accuracy = 1000;		/*  1ms */
+		caps->sets_to_zero = 0;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t ioc3_set_time (efi_time_t *t)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_WRITE_ENABLE);
+        	write_io_port(RTC_SGS_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_SGS_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_SGS_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_SGS_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_SGS_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_SGS_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+		write_io_port(RTC_DAL_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_DAL_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_DAL_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_DAL_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_DAL_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_DAL_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	return EFI_SUCCESS;
+}
+
+/* The following two are not supported atm.  */
+static efi_status_t
+ioc3_get_wakeup_time (efi_bool_t *enabled, efi_bool_t *pending, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+static efi_status_t
+ioc3_set_wakeup_time (efi_bool_t enabled, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/*
+ * It looks like the master IOC3 is usually on bus 0, device 4.  Hope
+ * that's right
+ */
+static __init int efi_ioc3_time_init(void)
+{
+	struct pci_dev *dev;
+	static struct ioc3 *ioc3;
+
+	dev = pci_find_slot(0, PCI_DEVFN(4, 0));
+	if (!dev) {
+		printk(KERN_CRIT "Couldn't find master IOC3\n");
+
+		return -ENODEV;
+	}
+
+	ioc3 = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
+	nvram_base = (unsigned long) ioc3 + IOC3_BYTEBUS_DEV0;
+
+	tod_chip_type = get_tod_chip_type();
+	if (tod_chip_type == 1)
+		printk(KERN_NOTICE "TOD type is SGS M48T35\n");
+	else if (tod_chip_type == 2)
+		printk(KERN_NOTICE "TOD type is Dallas DS1386\n");
+	else
+		printk(KERN_CRIT "No or unknown TOD\n");
+
+	efi.get_time = ioc3_get_time;
+	efi.set_time = ioc3_set_time;
+	efi.get_wakeup_time = ioc3_get_wakeup_time;
+	efi.set_wakeup_time = ioc3_set_wakeup_time;
+
+	return 0;
+}
+
+module_init(efi_ioc3_time_init);
diff -urN linux-2.4.16/arch/ia64/sn/io/hcl.c lia64-2.4/arch/ia64/sn/io/hcl.c
--- linux-2.4.16/arch/ia64/sn/io/hcl.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/hcl.c	Mon Nov 19 23:22:50 2001
@@ -6,8 +6,7 @@
  *
  *  hcl - SGI's Hardware Graph compatibility layer.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -49,7 +48,6 @@
 /*
  * Some Global definitions.
  */
-spinlock_t hcl_spinlock;
 devfs_handle_t hcl_handle = NULL;
 
 invplace_t invplace_none = {
@@ -142,6 +140,7 @@
 {
 	extern void string_table_init(struct string_table *);
 	extern struct string_table label_string_table;
+	extern int init_ifconfig_net(void);
 	int rv = 0;
 
 #if defined(CONFIG_HCL_DEBUG) && !defined(MODULE)
@@ -153,8 +152,6 @@
 	printk ("\n%s: boot_options: 0x%0x\n", HCL_NAME, boot_options);
 #endif
 
-	spin_lock_init(&hcl_spinlock);
-
 	/*
 	 * Create the hwgraph_root on devfs.
 	 */
@@ -192,6 +189,12 @@
 		return(0);
 	}
 
+	/*
+	 * Initialize the ifconfgi_net driver that does network devices 
+	 * Persistent Naming.
+	 */
+	init_ifconfig_net();
+
 	return(0);
 
 }
@@ -238,8 +241,7 @@
 {
 
 	if (hcl_debug) {
-		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n",
-			de, fastinfo);
+		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n", (void *)de, fastinfo);
 	}
 		
 	labelcl_info_replace_IDX(de, HWGRAPH_FASTINFO, fastinfo, NULL);
@@ -466,7 +468,7 @@
 		 * We need to clean up!
 		 */
 		printk(KERN_WARNING "HCL: Unable to set the connect point to it's parent 0x%p\n",
-			new_devfs_handle);
+			(void *)new_devfs_handle);
 	}
 
         /*
@@ -1044,24 +1046,6 @@
 }
 
 /*
- * hwgraph_cdevsw_get - returns the fops of the given devfs entry.
- */
-struct file_operations *
-hwgraph_cdevsw_get(devfs_handle_t de)
-{
-	return(devfs_get_ops(de));
-}
-
-/*
- * hwgraph_bdevsw_get - returns the fops of the given devfs entry.
-*/
-struct file_operations *
-hwgraph_bdevsw_get(devfs_handle_t de)
-{
-	return(devfs_get_ops(de));
-}
-
-/*
 ** Inventory is now associated with a vertex in the graph.  For items that
 ** belong in the inventory but have no vertex 
 ** (e.g. old non-graph-aware drivers), we create a bogus vertex under the 
@@ -1544,6 +1528,4 @@
 EXPORT_SYMBOL(hwgraph_path_to_dev);
 EXPORT_SYMBOL(hwgraph_block_device_get);
 EXPORT_SYMBOL(hwgraph_char_device_get);
-EXPORT_SYMBOL(hwgraph_cdevsw_get);
-EXPORT_SYMBOL(hwgraph_bdevsw_get);
 EXPORT_SYMBOL(hwgraph_vertex_name_get);
diff -urN linux-2.4.16/arch/ia64/sn/io/hcl_util.c lia64-2.4/arch/ia64/sn/io/hcl_util.c
--- linux-2.4.16/arch/ia64/sn/io/hcl_util.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/hcl_util.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -14,6 +13,7 @@
 #include <linux/devfs_fs_kernel.h>
 #include <asm/sn/sgi.h>
 #include <asm/io.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -urN linux-2.4.16/arch/ia64/sn/io/hubdev.c lia64-2.4/arch/ia64/sn/io/hubdev.c
--- linux-2.4.16/arch/ia64/sn/io/hubdev.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/hubdev.c	Mon Nov 19 23:22:50 2001
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/sn1/hubdev.h>
 #include <asm/sn/sn_private.h>
@@ -42,7 +43,7 @@
         
         ASSERT(attach_method);
 
-        callout =  (hubdev_callout_t *)kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
+        callout =  (hubdev_callout_t *)snia_kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
         ASSERT(callout);
         
 	mutex_lock(&hubdev_callout_mutex);
@@ -104,6 +105,9 @@
  * Given a hub vertex, return the base address of the Hspec space
  * for that hub.
  */
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
 caddr_t
 hubdev_prombase_get(devfs_handle_t hub)
 {
@@ -124,3 +128,5 @@
 
 	return hinfo->h_cnodeid;
 }
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
diff -urN linux-2.4.16/arch/ia64/sn/io/huberror.c lia64-2.4/arch/ia64/sn/io/huberror.c
--- linux-2.4.16/arch/ia64/sn/io/huberror.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/huberror.c	Wed Dec 31 16:00:00 1969
@@ -1,475 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-extern void hubni_eint_init(cnodeid_t cnode);
-extern void hubii_eint_init(cnodeid_t cnode);
-extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
-extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-extern int maxcpus;
-
-#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
-
-
-void
-hub_error_clear(nasid_t nasid)
-{
-	int i;
-	hubreg_t idsr;
-	int sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
-	}
-
-	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
-
-    /*
-     * Make sure spurious write response errors are cleared
-     * (values are from hub_set_prb())
-     */
-    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
-        iprb_t prb;
-
-	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
-
-        /* Clear out some fields */
-        prb.iprb_ovflow = 1;
-        prb.iprb_bnakctr = 0;
-        prb.iprb_anakctr = 0;
-
-	/*
-	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
-	 * frob the credit count properly, making the responses appear
-	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
-	 */
-        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
-
-        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
-
-        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
-    }
-
-    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
-    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
-    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
-
-    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
-    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
-
-    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
-    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
-
-    /* Clear XB error regs, in order */
-    for (i = 0;
-         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
-         i += sizeof(hubreg_t)) {
-        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
-    }
-}
-
-
-/*
- * Function	: hub_error_init
- * Purpose	: initialize the error handling requirements for a given hub.
- * Parameters	: cnode, the compact nodeid.
- * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
- *			remote cpu, when this hub is headless.(cpuless)
- * Returns	: None
- */
-
-void
-hub_error_init(cnodeid_t cnode)
-{
-	nasid_t nasid;
-
-    nasid = cnodeid_to_nasid(cnode);
-    hub_error_clear(nasid);
-
-#ifdef ajm
-    if (cnode == 0) {
-	/*
-	 * Allocate log for storing the node specific error info
-	 */
-	for (i = 0; i < numnodes; i++) {
-	    kl_error_log[i]  = kmem_zalloc_node(sizeof(sn0_error_log_t), 
-						KM_NOSLEEP, i);
-	    hub_err_count[i] = kmem_zalloc_node(sizeof(hub_errcnt_t),
-						VM_DIRECT | KM_NOSLEEP, i);
-	    ASSERT_ALWAYS(kl_error_log[i] && hub_err_count[i]);
-	}
-    }
-
-    /*
-     * Assumption: There will be only one cpu who will initialize
-     * a hub. we need to setup the ii and each pi error interrupts.
-     * The SN1 hub (bedrock) has two PI, one for up to two processors.
-     */
-
-    if (cpuid_to_cnodeid(smp_processor_id()) == cnode) { 
-	int generic_intr_mask = PI_ERR_GENERIC; /* These interrupts are sent to only 1 CPU per NODE */
-
-	ASSERT_ALWAYS(kl_error_log[cnode]);
-	ASSERT_ALWAYS(hub_err_count[cnode]);
-	MD_ERR_LOG_INIT(kl_error_log[cnode]);
-
-	/* One for each CPU */
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 0));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 1));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 2));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 3));
-
-	/*
-	 * Setup error intr masks.
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		int cpuA_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_A);
-		int cpuB_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_B);
-
-		if (cpuA_present) {
-			if (cpuB_present) {		/* A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_A|generic_intr_mask));
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_B));
-
-			} else {			/* A && !B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_A|generic_intr_mask));
-			}
-			generic_intr_mask = 0;
-		} else {
-			if (cpuB_present) {		/* !A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_B|generic_intr_mask));
-				generic_intr_mask = 0;
-
-			} else {			/* !A && !B */
-				/* nothing to set up */
-			}
-		}
-	}
-
-	/*
-	 * Turn off UNCAC_UNCORR interrupt in the masks. Anyone interested
-	 * in these errors will peek at the int pend register to see if its
-	 * set.
-	 */ 
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_A);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, (misc & ~PI_ERR_UNCAC_UNCORR_A));
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_B);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, (misc & ~PI_ERR_UNCAC_UNCORR_B));
-	}
-
-	/*
-	 * enable all error indicators to turn on, in case of errors.
-	 *
-	 * This is not good on single cpu node boards.
-	 **** LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_A_CLR, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_B_CLR, 0);
-	}
-
-	/* Set up stack for each present processor */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_A)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[0] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[0] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-		}
-	    
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-		}
-	}
-
-
-	PI_SPOOL_SIZE_BYTES = 
-	    ERR_STACK_SIZE_BYTES(REMOTE_HUB_L(nasid, PI_ERR_STACK_SIZE));
-
-#ifdef BRINGUP
-/* BRINGUP: The following code looks like a check to make sure
-the prom set up the error spool correctly for 2 processors.  I
-don't think it is needed.  */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-			__psunsigned_t addr_a = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-			__psunsigned_t addr_b = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-			if ((addr_a & ~0xff) == (addr_b & ~0xff)) {
-			    REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STACK_ADDR_B, 	
-					addr_b + PI_SPOOL_SIZE_BYTES);
-	
-			    SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-				SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-				    REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-	
-		    }
-		}
-	}
-#endif /* BRINGUP */
-
-	/* programming our own hub. Enable error_int_pend intr.
-	 * If both present, CPU A takes CPU b's error interrupts and any
-	 * generic ones. CPU B takes CPU A error ints.
-	 */
-	if (cause_intr_connect (SRB_ERR_IDX,
-				(intr_func_t)(hubpi_eint_handler),
-				SR_ALL_MASK|SR_IE)) {
-	    cmn_err(ERR_WARN, 
-		    "hub_error_init: cause_intr_connect failed on %d", cnode);
-	}
-    }
-    else {
-	/* programming remote hub. The only valid reason that this
-	 * is called will be on headless hubs. No interrupts 
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, 0); /* not necessary */
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, 0); /* not necessary */
-	}
-    }
-#endif /* ajm */
-    /*
-     * Now setup the hub ii and ni error interrupt handler.
-     */
-
-    hubii_eint_init(cnode);
-    hubni_eint_init(cnode);
-
-#ifdef ajm
-    /*** XXX FIXME XXX resolve the following***/
-    /* INT_PEND1 bits set up for one hub only:
-     *	SHUTDOWN_INTR
-     *	MD_COR_ERR_INTR
-     *  COR_ERR_INTR_A and COR_ERR_INTR_B should be sent to the
-     *  appropriate CPU only.
-     */
-
-    if (cnode == 0) {
-	    error_consistency_check.eps_state = 0;
-	    error_consistency_check.eps_cpuid = -1;
-	    spinlock_init(&error_consistency_check.eps_lock, "error_dump_lock");
-    }
-#endif
-
-    nodepda->huberror_ticks = HUB_ERROR_PERIOD;
-    return;
-}
-
-/*
- * Function	: hubii_eint_init
- * Parameters	: cnode
- * Purpose	: to initialize the hub iio error interrupt.
- * Assumptions	: Called once per hub, by the cpu which will ultimately
- *			handle this interrupt.
- * Returns	: None.
- */
-
-
-void
-hubii_eint_init(cnodeid_t cnode)
-{
-    int			bit, rv;
-    ii_iidsr_u_t    	hubio_eint;
-    hubinfo_t		hinfo; 
-    cpuid_t		intr_cpu;
-    devfs_handle_t 	hub_v;
-    ii_ilcsr_u_t	ilcsr;
-
-    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
-    ASSERT_ALWAYS(hub_v);
-    hubinfo_get(hub_v, &hinfo);
-
-    ASSERT(hinfo);
-    ASSERT(hinfo->h_cnodeid == cnode);
-
-    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
-
-    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
-	/* 
-	 * HUB II link is not up. 
-	 * Just disable LLP, and don't connect any interrupts.
-	 */
-	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
-	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
-	return;
-    }
-    /* Select a possible interrupt target where there is a free interrupt
-     * bit and also reserve the interrupt bit for this IO error interrupt
-     */
-    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
-			      "HUB IO error interrupt",&bit);
-    if (intr_cpu == CPU_NONE) {
-	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
-	return;
-    }
-	
-    rv = intr_connect_level(intr_cpu, bit, 0,(intr_func_t)(NULL),
-			    (void *)(long)hub_v, NULL);
-    synergy_intr_connect(bit, intr_cpu);
-    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, NULL, (void *)hub_v);
-    ASSERT_ALWAYS(rv >= 0);
-    hubio_eint.ii_iidsr_regval = 0;
-    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
-    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
-    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
-    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
-
-}
-
-void
-hubni_eint_init(cnodeid_t cnode)
-{
-    int intr_bit;
-    cpuid_t targ;
-
-
-    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
-	return;
-
-	/* The prom chooses which cpu gets these interrupts, but we
-	*  don't know which one it chose.  We will register all of the 
-	*  cpus to be sure.  This only costs us an irqaction per cpu.
-	*/
-    for (; targ < CPUS_PER_NODE; targ++) {
-	if (!cpu_enabled(targ) ) continue;
-	/* connect the INTEND1 bits. */
-	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
-		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL, NULL, NULL);
-	}
-	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, NULL, NULL);
-	/* synergy masks are initialized in the prom to enable all interrupts. */
-	/* We'll just leave them that way, here, for these interrupts. */
-    }
-}
-
-
-/*ARGSUSED*/
-void
-hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
-{
-    devfs_handle_t	hub_v;
-    hubinfo_t		hinfo; 
-    ii_wstat_u_t	wstat;
-    hubreg_t		idsr;
-
-	panic("Hubii interrupt\n");
-#ifdef ajm
-    /*
-     * If the NI has a problem, everyone has a problem.  We shouldn't
-     * even attempt to handle other errors when an NI error is present.
-     */
-    if (check_ni_errors()) {
-	hubni_error_handler("II interrupt", 1);
-	/* NOTREACHED */
-    }
-
-    /* two levels of casting avoids compiler warning.!! */
-    hub_v = (devfs_handle_t)(long)(arg); 
-    ASSERT(hub_v);
-
-    hubinfo_get(hub_v, &hinfo);
-    
-    /* 
-     * Identify the reason for error. 
-     */
-    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
-
-    if (wstat.ii_wstat_fld_s.w_crazy) {
-	char	*reason;
-	/*
-	 * We can do a couple of things here. 
-	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
-	 * which of these caused the CRAZY bit to be set. 
-	 * You may be able to check if the Link is up really.
-	 */
-	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
-		reason = "Micro Packet Retry Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
-		reason = "Crosstalk Tail Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
-		reason = "Crosstalk Credit Timeout";
-	else {
-		hubreg_t	hubii_imem;
-		/*
-		 * Check if widget 0 has been marked as shutdown, or
-		 * if BTE 0/1 has been marked.
-		 */
-		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
-		if (hubii_imem & IIO_IMEM_W0ESD)
-			reason = "Hub Widget 0 has been Shutdown";
-		else if (hubii_imem & IIO_IMEM_B0ESD)
-			reason = "BTE 0 has been shutdown";
-		else if (hubii_imem & IIO_IMEM_B1ESD)
-			reason = "BTE 1 has been shutdown";
-		else	reason = "Unknown";
-	
-	}
-	/*
-	 * Note: we may never be able to print this, if the II talking
-	 * to Xbow which hosts the console is dead. 
-	 */
-	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
-		hinfo->h_cnodeid, reason);
-    }
-
-    /* 
-     * It's a toss as to which one among PRB/CRB to check first. 
-     * Current decision is based on the severity of the errors. 
-     * IO CRB errors tend to be more severe than PRB errors.
-     *
-     * It is possible for BTE errors to have been handled already, so we
-     * may not see any errors handled here. 
-     */
-    (void)hubiio_crb_error_handler(hub_v, hinfo);
-    (void)hubiio_prb_error_handler(hub_v, hinfo);
-    /*
-     * If we reach here, it indicates crb/prb handlers successfully
-     * handled the error. So, re-enable II to send more interrupt
-     * and return.
-     */
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
-    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
-#endif /* ajm */
-}
diff -urN linux-2.4.16/arch/ia64/sn/io/hubspc.c lia64-2.4/arch/ia64/sn/io/hubspc.c
--- linux-2.4.16/arch/ia64/sn/io/hubspc.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/hubspc.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,8 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */
 
 /*
@@ -19,6 +19,8 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <linux/devfs_fs.h>
 #include <linux/devfs_fs_kernel.h>
 #include <asm/io.h>
@@ -26,18 +28,12 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn1/mem_refcnt.h>
 #include <asm/sn/addrs.h>
-
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/sn1/hubspc.h>
 #include <asm/sn/ksys/elsc.h>
-#endif
-
-#include <asm/sn/hubspc.h>
+#include <asm/sn/simulator.h>
 
 
 /* Uncomment the following line for tracing */
@@ -45,10 +41,6 @@
 
 int hubspc_devflag = D_MP;
 
-extern void *device_info_get(devfs_handle_t device);
-extern void device_info_set(devfs_handle_t device, void *info);
-
-
 
 /***********************************************************************/
 /* CPU Prom Space 						       */
@@ -127,9 +119,8 @@
 	return 0;
 }
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1)
 #define	SN_PROMVERSION		INV_IP35PROM
-#endif
 
 /* Add "detailed" labelled inventory information to the
  * prom vertex 
@@ -159,7 +150,6 @@
 	cpuprom_inventory_info->im_rev = IP27CONFIG.pvers_rev;
 	cpuprom_inventory_info->im_version = IP27CONFIG.pvers_vers;
 
-
 	/* Store this info as labelled information hanging off the
 	 * prom device vertex
 	 */
@@ -172,41 +162,17 @@
 				sizeof(invent_miscinfo_t));
 }
 
-int
-cpuprom_attach(devfs_handle_t node)
-{
-        devfs_handle_t prom_dev;
-
-        hwgraph_char_device_add(node, EDGE_LBL_PROM, "hubspc_", &prom_dev);
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc: prom_attach hub: 0x%x prom: 0x%x\n", node, prom_dev);
-#endif	/* HUBSPC_DEBUG */
-	device_inventory_add(prom_dev, INV_PROM, SN_PROMVERSION,
-				(major_t)0, (minor_t)0, 0);
-
-	/* Add additional inventory info about the cpu prom like
-	 * revision & version numbers etc.
-	 */
-	cpuprom_detailed_inventory_info_add(prom_dev,node);
-        device_info_set(prom_dev, (void*)(ulong)HUBSPC_PROM);
-	prominfo_add(node, prom_dev);
-
-        return (0);
-}
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #define FPROM_CONFIG_ADDR	MD_JUNK_BUS_TIMING
 #define FPROM_ENABLE_MASK	MJT_FPROM_ENABLE_MASK
 #define FPROM_ENABLE_SHFT	MJT_FPROM_ENABLE_SHFT
 #define FPROM_SETUP_MASK	MJT_FPROM_SETUP_MASK
 #define FPROM_SETUP_SHFT	MJT_FPROM_SETUP_SHFT
-#endif
 
 /*ARGSUSED*/
 int
 cpuprom_map(devfs_handle_t dev, vhandl_t *vt, off_t addr, size_t len)
 {
-        int 		errcode;
+        int 		errcode = 0;
 	caddr_t 	kvaddr;
 	devfs_handle_t		node;
 	cnodeid_t 	cnode;
@@ -220,7 +186,7 @@
 	kvaddr = hubdev_prombase_get(node);
 	cnode  = hubdev_cnodeid_get(node);
 #ifdef	HUBSPC_DEBUG
-	printf("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
+	printk("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
 #endif
 
 	if (len > RBOOT_SIZE)
@@ -251,6 +217,7 @@
 	}
         return (errcode);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 /*ARGSUSED*/
 int
@@ -263,8 +230,6 @@
 /* Base Hub Space Driver                                               */
 /***********************************************************************/
 
-// extern int l1_attach( devfs_handle_t );
-
 /*
  * hubspc_init
  * Registration of the hubspc devices with the hub manager
@@ -277,24 +242,21 @@
          */
 
         /* The reference counters */
+#if defined(CONFIG_IA64_SGI_SN1)
         hubdev_register(mem_refcnt_attach);
-
-	/* Prom space */
-	hubdev_register(cpuprom_attach);
+#endif
 
 #if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
 	/* L1 system controller link */
 	if ( !IS_RUNNING_ON_SIMULATOR() ) {
 		/* initialize the L1 link */
-		void l1_cons_init( l1sc_t *sc );
-		elsc_t *get_elsc(void);
-
-		l1_cons_init((l1sc_t *)get_elsc());
+		extern void l1_init(void);
+		l1_init();
 	}
 #endif
 
 #ifdef	HUBSPC_DEBUG
-	printf("hubspc_init: Completed\n");
+	printk("hubspc_init: Completed\n");
 #endif	/* HUBSPC_DEBUG */
 	/* Initialize spinlocks */
 	mutex_spinlock_init(&cpuprom_spinlock);
@@ -304,26 +266,7 @@
 int
 hubspc_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(*devp)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_open(devp, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_open: Completed open for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(*devp));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 
@@ -331,25 +274,7 @@
 int
 hubspc_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_close(dev, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_close: Completed close for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(dev));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 /* ARGSUSED */
@@ -357,7 +282,6 @@
 hubspc_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
 {
 	/*REFERENCED*/
-        hubspc_subdevice_t subdevice;
         int errcode = 0;
 
 	/* check validity of request */
@@ -365,30 +289,6 @@
 		return ENXIO;
         }
 
-        subdevice = (hubspc_subdevice_t)(ulong)device_info_get(dev);
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map: subdevice: %d vaddr: 0x%x phyaddr: 0x%x len: 0x%x\n",
-	       subdevice, v_getaddr(vt), off, len);
-#endif /* HUBSPC_DEBUG */
-
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_mmap(dev, vt, off, len, prot);
-                break;
-
-        case HUBSPC_PROM:
-		errcode = cpuprom_map(dev, vt, off, len);
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map finished: spctype: %d vaddr: 0x%x len: 0x%x\n",
-	       (hubspc_subdevice_t)(ulong)device_info_get(dev), v_getaddr(vt), len);
-#endif /* HUBSPC_DEBUG */
-
 	return errcode;
 }
 
@@ -396,21 +296,7 @@
 int
 hubspc_unmap(devfs_handle_t dev, vhandl_t *vt)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_unmap(dev, vt);
-                break;
-
-        case HUBSPC_PROM:
-                errcode = cpuprom_unmap(dev, vt);
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
 
@@ -423,19 +309,6 @@
              cred_t *cred_p,
              int *rvalp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_ioctl(dev, cmd, arg, mode, cred_p, rvalp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
diff -urN linux-2.4.16/arch/ia64/sn/io/ifconfig_net.c lia64-2.4/arch/ia64/sn/io/ifconfig_net.c
--- linux-2.4.16/arch/ia64/sn/io/ifconfig_net.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/ifconfig_net.c	Mon Nov 19 23:22:50 2001
@@ -0,0 +1,297 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *  ifconfig_net - SGI's Persistent Network Device names.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
+ * All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <asm/sn/sgi.h>
+#include <linux/devfs_fs.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/ifconfig_net.h>
+
+#define SGI_IFCONFIG_NET "SGI-PERSISTENT NETWORK DEVICE NAME DRIVER"
+#define SGI_IFCONFIG_NET_VERSION "1.0"
+
+/*
+ * Some Global definitions.
+ */
+devfs_handle_t ifconfig_net_handle = NULL;
+unsigned long ifconfig_net_debug = 0;
+
+/*
+ * ifconfig_net_open - Opens the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_open(struct inode * inode, struct file * filp)
+{
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_open called.\n");
+	}
+
+        return(0);
+
+}
+
+/*
+ * ifconfig_net_close - Closes the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_close(struct inode * inode, struct file * filp)
+{
+
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_close called.\n");
+	}
+
+        return(0);
+}
+
+/*
+ * assign_ifname - Assign the next available interface name from the persistent list.
+ */
+void
+assign_ifname(struct net_device *dev,
+		  struct ifname_num *ifname_num)
+
+{
+
+	/*
+	 * Handle eth devices.
+	 */
+        if ( (memcmp(dev->name, "eth", 3) == 0) ) {
+		if (ifname_num->next_eth != -1) {
+			/*
+			 * Assign it the next available eth interface number. 
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "eth%d", (int)ifname_num->next_eth);
+			ifname_num->next_eth++;
+		} 
+
+                return;
+        }
+
+	/*
+	 * Handle fddi devices.
+	 */
+	if ( (memcmp(dev->name, "fddi", 4) == 0) ) {
+		if (ifname_num->next_fddi != -1) {
+			/*
+			 * Assign it the next available fddi interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fddi%d", (int)ifname_num->next_fddi);
+			ifname_num->next_fddi++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle hip devices.
+	 */
+	if ( (memcmp(dev->name, "hip", 3) == 0) ) {
+		if (ifname_num->next_hip != -1) {
+			/*
+			 * Assign it the next available hip interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "hip%d", (int)ifname_num->next_hip);
+			ifname_num->next_hip++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle tr devices.
+	 */
+	if ( (memcmp(dev->name, "tr", 2) == 0) ) {
+		if (ifname_num->next_tr != -1) {
+			/*
+			 * Assign it the next available tr interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "tr%d", (int)ifname_num->next_tr);
+			ifname_num->next_tr++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle fc devices.
+	 */
+	if ( (memcmp(dev->name, "fc", 2) == 0) ) {
+		if (ifname_num->next_fc != -1) {
+			/*
+			 * Assign it the next available fc interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fc%d", (int)ifname_num->next_fc);
+			ifname_num->next_fc++;
+		}
+
+		return;
+	}
+}
+
+/*
+ * find_persistent_ifname: Returns the entry that was seen in previous boot.
+ */
+struct ifname_MAC *
+find_persistent_ifname(struct net_device *dev,
+	struct ifname_MAC *ifname_MAC)
+
+{
+
+	while (ifname_MAC->addr_len) {
+		if (memcmp(dev->dev_addr, ifname_MAC->dev_addr, dev->addr_len) == 0)
+			return(ifname_MAC);
+
+		ifname_MAC++;
+	}
+
+	return(NULL);
+}
+
+/*
+ * ifconfig_net_ioctl: ifconfig_net driver ioctl interface.
+ */
+static int ifconfig_net_ioctl(struct inode * inode, struct file * file,
+        unsigned int cmd, unsigned long arg)
+{
+
+	extern struct net_device *__dev_get_by_name(const char *);
+	struct net_device *dev;
+	struct ifname_MAC *found;
+	char temp[64];
+	struct ifname_MAC *ifname_MAC;
+	struct ifname_MAC *new_devices, *temp_new_devices;
+	struct ifname_num *ifname_num;
+	unsigned long size;
+
+
+	if (ifconfig_net_debug) {
+		printk("HCL: hcl_ioctl called.\n");
+	}
+
+	/*
+	 * Read in the header and see how big of a buffer we really need to 
+	 * allocate.
+	 */
+	ifname_num = (struct ifname_num *) kmalloc(sizeof(struct ifname_num), 
+			GFP_KERNEL);
+	copy_from_user( ifname_num, (char *) arg, sizeof(struct ifname_num));
+	size = ifname_num->size;
+	kfree(ifname_num);
+	ifname_num = (struct ifname_num *) kmalloc(size, GFP_KERNEL);
+	ifname_MAC = (struct ifname_MAC *) ((char *)ifname_num + (sizeof(struct ifname_num)) );
+
+	copy_from_user( ifname_num, (char *) arg, size);
+	new_devices =  kmalloc(size - sizeof(struct ifname_num), GFP_KERNEL);
+	temp_new_devices = new_devices;
+
+	memset(new_devices, 0, size - sizeof(struct ifname_num));
+
+#ifdef CONFIG_NET
+	/*
+	 * Go through the net device entries and make them persistent!
+	 */
+	for (dev = dev_base; dev != NULL; dev = dev->next) {
+		/*
+		 * Skip NULL entries or "lo"
+		 */
+		if ( (dev->addr_len == 0) || ( !strncmp(dev->name, "lo", strlen(dev->name))) ){
+			continue;
+		}
+
+		/*
+		 * See if we have a persistent interface name for this device.
+		 */
+		found = NULL;
+		found = find_persistent_ifname(dev, ifname_MAC);
+		if (found) {
+			strcpy(dev->name, found->name);
+		} else {
+			/* Never seen this before .. */
+			assign_ifname(dev, ifname_num);
+
+			/* 
+			 * Save the information for the next boot.
+			 */
+ 			sprintf(temp,"%s %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
+				dev->dev_addr[0],  dev->dev_addr[1],  dev->dev_addr[2],
+				dev->dev_addr[3],  dev->dev_addr[4],  dev->dev_addr[5]);
+			strcpy(temp_new_devices->name, dev->name);
+			temp_new_devices->addr_len = dev->addr_len;
+			memcpy(temp_new_devices->dev_addr, dev->dev_addr, dev->addr_len);
+			temp_new_devices++;
+		}
+		
+	}
+#endif
+
+	/*
+	 * Copy back to the User Buffer area any new devices encountered.
+	 */
+	copy_to_user((char *)arg + (sizeof(struct ifname_num)), new_devices, 
+			size - sizeof(struct ifname_num));
+
+	return(0);
+
+}
+
+struct file_operations ifconfig_net_fops = {
+	ioctl:ifconfig_net_ioctl,	/* ioctl */
+	open:ifconfig_net_open,		/* open */
+	release:ifconfig_net_close	/* release */
+};
+
+
+/*
+ * init_ifconfig_net() - Boot time initialization.  Ensure that it is called 
+ *	after devfs has been initialized.
+ *
+ */
+#ifdef MODULE
+int init_module (void)
+#else
+int __init init_ifconfig_net(void)
+#endif
+{
+	ifconfig_net_handle = NULL;
+	ifconfig_net_handle = hwgraph_register(hwgraph_root, ".ifconfig_net",
+			0, DEVFS_FL_AUTO_DEVNUM,
+			0, 0,
+			S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+			&ifconfig_net_fops, NULL);
+
+	if (ifconfig_net_handle == NULL) {
+		panic("Unable to create SGI PERSISTENT NETWORK DEVICE Name Driver.\n");
+	}
+
+	return(0);
+
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/invent.c lia64-2.4/arch/ia64/sn/io/invent.c
--- linux-2.4.16/arch/ia64/sn/io/invent.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/invent.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
diff -urN linux-2.4.16/arch/ia64/sn/io/io.c lia64-2.4/arch/ia64/sn/io/io.c
--- linux-2.4.16/arch/ia64/sn/io/io.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/io.c	Mon Nov 19 23:22:50 2001
@@ -1,10 +1,10 @@
-/* $Id$
+/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 
@@ -13,24 +13,40 @@
 #include <linux/slab.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
 #include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
-#include <asm/sn/io.h>
 #include <asm/sn/sn_cpuid.h>
 
 extern xtalk_provider_t hub_provider;
+extern void hub_intr_init(devfs_handle_t hubv);
+
+
+/*      
+ * hub_device_desc_update               
+ *      Update the passed in device descriptor with the actual the
+ *      target cpu number and interrupt priority level.
+ *      NOTE : These might be the same as the ones passed in thru
+ *      the descriptor.
+ */     
+void
+hub_device_desc_update(device_desc_t    dev_desc,
+                       ilvl_t           intr_swlevel, 
+                       cpuid_t          cpu)
+{       
+}
+
 
 /*
  * Perform any initializations needed to support hub-based I/O.
@@ -63,7 +79,7 @@
 /*
  * Setup pio structures needed for a particular hub.
  */
-static void
+void
 hub_pio_init(devfs_handle_t hubv)
 {
 	xwidgetnum_t widget;
@@ -386,7 +402,7 @@
 
 
 /* ARGSUSED */
-static void
+void
 hub_dma_init(devfs_handle_t hubv)
 {
 }
@@ -411,7 +427,7 @@
 	xwidgetnum_t widget = xwidget_info_id_get(widget_info);
 	devfs_handle_t hubv = xwidget_info_master_get(widget_info);
 
-	dmamap = kern_malloc(sizeof(struct hub_dmamap_s));
+	dmamap = kmalloc(sizeof(struct hub_dmamap_s), GFP_ATOMIC);
 	dmamap->hdma_xtalk_info.xd_dev = dev;
 	dmamap->hdma_xtalk_info.xd_target = widget;
 	dmamap->hdma_hub = hubv;
@@ -454,9 +470,9 @@
 	    if (!(dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_addr re-uses dmamap.\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_addr re-uses dmamap.\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -487,9 +503,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_list re-uses dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_list re-uses dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_list re-uses dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_list re-uses dmamap\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -516,9 +532,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_done already done with dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_done already done with dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_done already done with dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_done already done with dmamap\n", (void *)vhdl);
 #endif
 	    }
 	}
@@ -581,329 +597,6 @@
 
 
 
-/* INTERRUPT MANAGEMENT */
-
-/* ARGSUSED */
-static void
-hub_intr_init(devfs_handle_t hubv)
-{
-}
-
-/*
- * hub_device_desc_update
- *	Update the passed in device descriptor with the actual the
- * 	target cpu number and interrupt priority level.
- *	NOTE : These might be the same as the ones passed in thru
- *	the descriptor.
- */
-static void
-hub_device_desc_update(device_desc_t 	dev_desc, 
-		       ilvl_t 		intr_swlevel,
-		       cpuid_t		cpu)
-{
-	char	cpuname[40];
-	
-	/* Store the interrupt priority level in the device descriptor */
-	device_desc_intr_swlevel_set(dev_desc, intr_swlevel);
-
-	/* Convert the cpuid to the vertex handle in the hwgraph and
-	 * save it in the device descriptor.
-	 */
-	sprintf(cpuname,"/hw/cpunum/%ld",cpu);
-	device_desc_intr_target_set(dev_desc, 
-				    hwgraph_path_to_dev(cpuname));
-}
-
-int allocate_my_bit = INTRCONNECT_ANYBIT;
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-static hub_intr_t
-do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
-		  device_desc_t dev_desc,	/* device descriptor */
-		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
-		  int uncond_nothread)		/* unconditionally non-threaded */
-{
-	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
-        int cpupicked = 0;
-	int bit;			/* interrupt vector */
-	/*REFERENCED*/
-	int intr_resflags = 0;
-	hub_intr_t intr_hdl;
-	cnodeid_t nodeid;		/* node to receive interrupt */
-	/*REFERENCED*/
-	nasid_t nasid;			/* nasid to receive interrupt */
-	struct xtalk_intr_s *xtalk_info;
-	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
-	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
-	char *intr_name = NULL;
-	ilvl_t intr_swlevel;
-	extern int default_intr_pri;
-#ifdef CONFIG_IA64_SGI_SN1 
-	extern void synergy_intr_alloc(int, int);
-#endif
-	
-	/*
-	 * If caller didn't explicily specify a device descriptor, see if there's
-	 * a default descriptor associated with the device.
-	 */
-	if (!dev_desc) 
-		dev_desc = device_desc_default_get(dev);
-
-	if (dev_desc) {
-		intr_name = device_desc_intr_name_get(dev_desc);
-		intr_swlevel = device_desc_intr_swlevel_get(dev_desc);
-		if (dev_desc->flags & D_INTR_ISERR) {
-			intr_resflags = II_ERRORINT;
-		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
-			intr_resflags = II_THREADED;
-		} else {
-			/* Neither an error nor a thread. */
-			intr_resflags = 0;
-		}
-	} else {
-		intr_swlevel = default_intr_pri;
-		if (!uncond_nothread)
-			intr_resflags = II_THREADED;
-	}
-
-	/* XXX - Need to determine if the interrupt should be threaded. */
-
-	/* If the cpu has not been picked already then choose a candidate 
-	 * interrupt target and reserve the interrupt bit 
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (!cpupicked) {
-		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
-				     intr_resflags,owner_dev,
-				     intr_name,&bit);
-	}
-#endif
-
-	/* At this point we SHOULD have a valid cpu */
-	if (cpu == CPU_NONE) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#else
-		PRINT_WARNING("0x%x hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#endif
-		return(0);
-
-	}
-
-	/* If the cpu has been picked already (due to the bridge data 
-	 * corruption bug) then try to reserve an interrupt bit .
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (cpupicked) {
-		bit = intr_reserve_level(cpu, allocate_my_bit, 
-					 intr_resflags, 
-					 owner_dev, intr_name);
-		if (bit < 0) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev %v\n",
-				cpu,owner_dev);
-#else
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev 0x%x\n",
-				cpu, owner_dev);
-#endif
-				
-			return(0);
-		}
-	}
-#endif	/* NEW_INTERRUPTS */
-
-	nodeid = cpuid_to_cnodeid(cpu);
-	nasid = cpuid_to_nasid(cpu);
-	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
-
-	/*
-	 * Allocate an interrupt handle, and fill it in.  There are two
-	 * pieces to an interrupt handle: the piece needed by generic
-	 * xtalk code which is used by crosstalk device drivers, and
-	 * the piece needed by low-level IP27 hardware code.
-	 */
-	intr_hdl = kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
-	ASSERT_ALWAYS(intr_hdl);
-
-	/* 
-	 * Fill in xtalk information for generic xtalk interfaces that
-	 * operate on xtalk_intr_hdl's.
-	 */
-	xtalk_info = &intr_hdl->i_xtalk_info;
-	xtalk_info->xi_dev = dev;
-	xtalk_info->xi_vector = bit;
-	xtalk_info->xi_addr = xtalk_addr;
-
-	/*
-	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
-	 * widget always handles interrupts (and PIO and DMA) through its 
-	 * designated "master" crosstalk provider.
-	 */
-	xwidget_info = xwidget_info_get(dev);
-	if (xwidget_info)
-		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
-
-	/* Fill in low level hub information for hub_* interrupt interface */
-	intr_hdl->i_swlevel = intr_swlevel;
-	intr_hdl->i_cpuid = cpu;
-	intr_hdl->i_bit = bit;
-	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
-
-	/* Store the actual interrupt priority level & interrupt target
-	 * cpu back in the device descriptor.
-	 */
-	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
-#ifdef CONFIG_IA64_SGI_SN1
-	synergy_intr_alloc((int)bit, (int)cpu);
-#endif
-	return(intr_hdl);
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Uncondtionally request non-threaded, regardless of what the device
- * descriptor might say.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
-}
-
-/*
- * Free resources consumed by intr_alloc.
- */
-void
-hub_intr_free(hub_intr_t intr_hdl)
-{
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_t xtalk_info;
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
-		/* Setting the following fields in the xtalk interrupt info
-	 	 * clears the interrupt target register in the xtalk user
-	 	 */
-		xtalk_info = &intr_hdl->i_xtalk_info;
-		xtalk_info->xi_dev = NODEV;
-		xtalk_info->xi_vector = 0;
-		xtalk_info->xi_addr = 0;
-		hub_intr_disconnect(intr_hdl);
-	}
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
-		kfree(intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	intr_unreserve_level(cpu, bit);
-#endif
-}
-
-
-/*
- * Associate resources allocated with a previous hub_intr_alloc call with the
- * described handler, arg, name, etc.
- */
-/*ARGSUSED*/
-int
-hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
-			intr_func_t intr_func,		/* xtalk intr handler */
-			void *intr_arg,			/* arg to intr handler */
-			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-			void *setfunc_arg,		/* arg to setfunc */
-			void *thread)			/* intr thread to use */
-{
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-#ifdef CONFIG_IA64_SGI_SN1
-	extern int synergy_intr_connect(int, int);
-#endif
-
-	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, 
-					intr_func, intr_arg, NULL);
-	if (rv < 0)
-		return(rv);
-
-#endif
-	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
-	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
-
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
-#ifdef CONFIG_IA64_SGI_SN1
-	return(synergy_intr_connect((int)bit, (int)cpu));
-#endif
-}
-
-
-/*
- * Disassociate handler with the specified interrupt.
- */
-void
-hub_intr_disconnect(hub_intr_t intr_hdl)
-{
-	/*REFERENCED*/
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_setfunc_t setfunc;
-
-	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
-
-	/* TBD: send disconnected interrupts somewhere harmless */
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_disconnect_level(cpu, bit);
-	ASSERT(rv == 0);
-#endif
-
-	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
-}
-
-
-/*
- * Return a hwgraph vertex that represents the CPU currently
- * targeted by an interrupt.
- */
-devfs_handle_t
-hub_intr_cpu_get(hub_intr_t intr_hdl)
-{
-	cpuid_t cpuid = intr_hdl->i_cpuid;
-	ASSERT(cpuid != CPU_NONE);
-
-	return(cpuid_to_vertex(cpuid));
-}
-
-
-
 /* CONFIGURATION MANAGEMENT */
 
 /*
@@ -912,6 +605,9 @@
 void
 hub_provider_startup(devfs_handle_t hubv)
 {
+	extern void hub_dma_init(devfs_handle_t hubv);
+	extern void hub_pio_init(devfs_handle_t hubv);
+
 	hub_pio_init(hubv);
 	hub_dma_init(hubv);
 	hub_intr_init(hubv);
@@ -1170,7 +866,7 @@
 	return rv;
 }
 
-#if ((defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP))
+#if defined(BRINGUP)
 /* BRINGUP:  This ought to be useful for IP27 too but, for now,
  * make it SN1 only because `ii_ixtt_u_t' is not in IP27/hubio.h
  * (or anywhere else :-).
@@ -1220,7 +916,7 @@
 	mutex_spinunlock(&hub_info->h_bwlock, s);
 	return 0;
 }
-#endif /* CONFIG_IA64_SGI_SN1 */
+#endif /* BRINGUP */
 
 /*
  * hub_device_inquiry
@@ -1259,7 +955,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	printk("Inquiry Info for %v\n", xconn);
 #else
-	printk("Inquiry Info for 0x%x\n", xconn);
+	printk("Inquiry Info for %p\n", (void *)xconn);
 #endif
 
 	printk("\tDevices shutdown [ ");
diff -urN linux-2.4.16/arch/ia64/sn/io/ip37.c lia64-2.4/arch/ia64/sn/io/ip37.c
--- linux-2.4.16/arch/ia64/sn/io/ip37.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/ip37.c	Wed Dec 31 16:00:00 1969
@@ -1,121 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-/*
- * ip37.c
- *	Support for IP35/IP37 machines
- */
-
-#include <linux/types.h>
-#include <linux/config.h>
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sgi.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/pci/bridge.h>     /* for bridge_t */
-
-
-xwidgetnum_t
-hub_widget_id(nasid_t nasid)
-{
-	hubii_wcr_t	ii_wcr;	/* the control status register */
-		
-	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
-
-	return ii_wcr.wcr_fields_s.wcr_widget_id;
-}
-
-/*
- * get_nasid() returns the physical node id number of the caller.
- */
-nasid_t
-get_nasid(void)
-{
-	return (nasid_t)((LOCAL_HUB_L(LB_REV_ID) & LRI_NODEID_MASK) >> LRI_NODEID_SHFT);
-}
-
-int
-get_slice(void)
-{
-	return LOCAL_HUB_L(PI_CPU_NUM);
-}
-
-int
-is_fine_dirmode(void)
-{
-	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
-		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
-
-}
-
-hubreg_t
-get_hub_chiprev(nasid_t nasid)
-{
-
-	return ((REMOTE_HUB_L(nasid, LB_REV_ID) & LRI_REV_MASK)
-		                                         >> LRI_REV_SHFT);
-}
-
-int
-verify_snchip_rev(void)
-{
-	int hub_chip_rev;
-	int i;
-	static int min_hub_rev = 0;
-	nasid_t nasid;
-	static int first_time = 1;
-	extern int maxnodes;
-
-        
-	if (first_time) {
-	    for (i = 0; i < maxnodes; i++) {	
-		nasid = COMPACT_TO_NASID_NODEID(i);
-		hub_chip_rev = get_hub_chiprev(nasid);
-
-		if ((hub_chip_rev < min_hub_rev) || (i == 0))
-		    min_hub_rev = hub_chip_rev;
-	    }
-
-	
-	    first_time = 0;
-	}
-
-	return min_hub_rev;
-	
-}
-
-#ifdef SN1_USE_POISON_BITS
-int
-hub_bte_poison_ok(void)
-{
-	/*
-	 * For now, assume poisoning is ok. If it turns out there are chip
-	 * bugs that prevent its use in early revs, there is some neat code
-	 * to steal from the IP27 equivalent of this code.
-	 */
-
-#ifdef BRINGUP	/* temp disable BTE poisoning - might be sw bugs in this area */
-	return 0;
-#else
-	return 1;
-#endif
-}
-#endif /* SN1_USE_POISON_BITS */
-                
-
-void
-ni_reset_port(void)
-{
-	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
-	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
-}
-
-#endif	/* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
diff -urN linux-2.4.16/arch/ia64/sn/io/klconflib.c lia64-2.4/arch/ia64/sn/io/klconflib.c
--- linux-2.4.16/arch/ia64/sn/io/klconflib.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/klconflib.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -13,12 +12,13 @@
 #include <linux/config.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/module.h>
@@ -213,14 +213,13 @@
 {
 	lboard_t	*board;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 /* BRINGUP: If this works then look for callers of is_master_baseio()
  * (e.g. iograph.c) and let them pass in a slot if they want
  */
 	board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid), module);
 #else
-	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    module, slot);
+	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid), module, slot);
 #endif
 
 #ifndef _STANDALONE
@@ -228,7 +227,7 @@
 		cnodeid_t cnode = NASID_TO_COMPACT_NODEID(nasid);
 
 		if (!board && (NODEPDA(cnode)->xbow_peer != INVALID_NASID))
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 			board = find_lboard_module((lboard_t *)
 				    KL_CONFIG_INFO(NODEPDA(cnode)->xbow_peer),
 				    module);
@@ -366,10 +365,6 @@
 {
 	moduleid_t modnum;
 	char *board_name;
-#if !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-	slotid_t slot;
-	char slot_name[SLOTNUM_MAXLENGTH];
-#endif
 
 	ASSERT(brd);
 
@@ -431,7 +426,7 @@
 {
 	lboard_t *brd;
 
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 
 	if (!brd)
 		return INVALID_MODULE;
@@ -569,8 +564,8 @@
 		if (component_serial_number_get(board,
 						hub->hub_mfg_nic,
 						serial_number,
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-						"IP35"))
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+						"IP37"))
 #else
 						"IP27"))
 			/* Try with IP31 key if IP27 key fails */
@@ -578,7 +573,7 @@
 							hub->hub_mfg_nic,
 							serial_number,
 							"IP31"))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 				return(1);
 		break;
 	}
@@ -875,10 +870,11 @@
 }
 
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 
 char brick_types[MAX_BRICK_TYPES + 1] = "crikxdp789012345";
 
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
 /*
  * Format a module id for printing.
  */
@@ -1009,7 +1005,7 @@
 	return (int)(unsigned short)m;
 }
 
-#else /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#else /* CONFIG_IA64_SGI_SN1 */
 
 /*
  * Format a module id for printing.
@@ -1038,8 +1034,8 @@
     if (strstr(buffer, EDGE_LBL_MODULE "/") == buffer)
 	buffer += strlen(EDGE_LBL_MODULE "/");
 
-    m = 0;
-    while(c = *buffer++) {
+    for (m = 0; *buffer; buffer++) {
+	c = *buffer;
 	if (!isdigit(c))
 	    return -1;
 	m = 10 * m + (c - '0');
@@ -1049,6 +1045,6 @@
     return (int)(unsigned short)m;
 }
 
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 
diff -urN linux-2.4.16/arch/ia64/sn/io/klgraph.c lia64-2.4/arch/ia64/sn/io/klgraph.c
--- linux-2.4.16/arch/ia64/sn/io/klgraph.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/klgraph.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
@@ -18,12 +17,12 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/kldir.h>
 #include <asm/sn/gda.h> 
 #include <asm/sn/klconfig.h>
@@ -43,8 +42,6 @@
 #include <asm/sn/sn_private.h>
 
 extern char arg_maxnodes[];
-extern int maxnodes;
-
 
 /*
  * Support for verbose inventory via hardware graph. 
@@ -139,38 +136,61 @@
 void
 klhwg_add_hub(devfs_handle_t node_vertex, klhub_t *hub, cnodeid_t cnode)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	devfs_handle_t myhubv;
+	devfs_handle_t hub_mon;
+	devfs_handle_t synergy;
+	devfs_handle_t fsb0;
+	devfs_handle_t fsb1;
 	int rc;
+	extern struct file_operations hub_mon_fops;
 
 	GRPRINTF(("klhwg_add_hub: adding %s\n", EDGE_LBL_HUB));
 
 	(void) hwgraph_path_add(node_vertex, EDGE_LBL_HUB, &myhubv);
 	rc = device_master_set(myhubv, node_vertex);
 
-#ifdef	LATER
 	/*
-	 * Activate when we support hub stats.
+	 * hub perf stats.
 	 */
 	rc = hwgraph_info_add_LBL(myhubv, INFO_LBL_HUB_INFO,
                         (arbitrary_info_t)(&NODEPDA(cnode)->hubstats));
-#endif
 
 	if (rc != GRAPH_SUCCESS) {
-		PRINT_WARNING("klhwg_add_hub: Can't add hub info label 0x%p, code %d",
-			myhubv, rc);
+		printk(KERN_WARNING  "klhwg_add_hub: Can't add hub info label 0x%p, code %d",
+			(void *)myhubv, rc);
 	}
 
 	klhwg_hub_invent_info(myhubv, cnode, hub);
 
-#ifndef BRINGUP
+	hub_mon = hwgraph_register(myhubv, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &hub_mon_fops,
+	    (void *)(long)cnode);
+
 	init_hub_stats(cnode, NODEPDA(cnode));
-	sndrv_attach(myhubv);
-#else
+
 	/*
-	 * Need to call our driver to do the attach?
+	 * synergy perf
 	 */
-	FIXME("klhwg_add_hub: Need to add code to do the attach.\n");
-#endif
+	(void) hwgraph_path_add(myhubv, EDGE_LBL_SYNERGY, &synergy);
+	(void) hwgraph_path_add(synergy, "0", &fsb0);
+	(void) hwgraph_path_add(synergy, "1", &fsb1);
+
+	fsb0 = hwgraph_register(fsb0, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 0));
+
+	fsb1 = hwgraph_register(fsb1, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 1));
+#endif /* CONFIG_IA64_SGI_SN1 */
 }
 
 #ifndef BRINGUP
@@ -338,11 +358,8 @@
 	/*REFERENCED*/
 	graph_error_t err;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || defined(CONFIG_IA64_GENERIC)
-	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IOBRICK_XBOW)) == NULL)
+	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IOBRICK_XBOW)) == NULL)
 			return;
-#endif
 
 	if (KL_CONFIG_DUPLICATE_BOARD(brd))
 	    return;
@@ -372,7 +389,7 @@
 
 		hub_nasid = XBOW_PORT_NASID(xbow_p, widgetnum);
 		if (hub_nasid == INVALID_NASID) {
-			PRINT_WARNING("hub widget %d, skipping xbow graph\n", widgetnum);
+			printk(KERN_WARNING  "hub widget %d, skipping xbow graph\n", widgetnum);
 			continue;
 		}
 
@@ -387,13 +404,13 @@
 		err = hwgraph_path_add(hubv, EDGE_LBL_XTALK, &xbow_v);
                 if (err != GRAPH_SUCCESS) {
                         if (err == GRAPH_DUP)
-                                PRINT_WARNING("klhwg_add_xbow: Check for "
+                                printk(KERN_WARNING  "klhwg_add_xbow: Check for "
                                         "working routers and router links!");
 
                         PRINT_PANIC("klhwg_add_xbow: Failed to add "
-                                "edge: vertex 0x%p (0x%p) to vertex 0x%p (0x%p),"
+                                "edge: vertex 0x%p to vertex 0x%p,"
                                 "error %d\n",
-                                hubv, hubv, xbow_v, xbow_v, err);
+                                (void *)hubv, (void *)xbow_v, err);
                 }
 		xswitch_vertex_init(xbow_v); 
 
@@ -416,7 +433,7 @@
 		err = hwgraph_edge_add(hubv, xbow_v, EDGE_LBL_XTALK);
 		if (err != GRAPH_SUCCESS) {
 			if (err == GRAPH_DUP)
-				PRINT_WARNING("klhwg_add_xbow: Check for "
+				printk(KERN_WARNING  "klhwg_add_xbow: Check for "
 					"working routers and router links!");
 
 			PRINT_PANIC("klhwg_add_xbow: Failed to add "
@@ -443,7 +460,7 @@
 	int board_disabled = 0;
 
 	nasid = COMPACT_TO_NASID_NODEID(cnode);
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	GRPRINTF(("klhwg_add_node: Adding cnode %d, nasid %d, brd 0x%p\n",
                 cnode, nasid, brd));
 	ASSERT(brd);
@@ -471,7 +488,7 @@
 		
 		if(!board_disabled) {
 			mark_nodevertex_as_node(node_vertex,
-					    cnode + board_disabled * numnodes);
+					    cnode + board_disabled * num_compact_nodes);
 
 			s = dev_to_name(node_vertex, path_buffer, sizeof(path_buffer));
 			NODEPDA(cnode)->hwg_node_name =
@@ -495,7 +512,7 @@
 		
 		brd = KLCF_NEXT(brd);
 		if (brd)
-			brd = find_lboard(brd, KLTYPE_IP27);
+			brd = find_lboard(brd, KLTYPE_SNIA);
 		else
 			break;
 	} while(brd);
@@ -513,7 +530,7 @@
 	char path_buffer[100];
 	int rv;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_add_all_routers: adding router on cnode %d\n",
@@ -594,7 +611,7 @@
 			return;
 
 	if (rc != GRAPH_SUCCESS)
-		PRINT_WARNING("Can't find router: %s", path_buffer);
+		printk(KERN_WARNING  "Can't find router: %s", path_buffer);
 
 	/* We don't know what to do with multiple router components */
 	if (brd->brd_numcompts != 1) {
@@ -650,7 +667,7 @@
 
 		if (rc != GRAPH_SUCCESS && !is_specified(arg_maxnodes))
 			PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 		
 	}
 }
@@ -663,7 +680,7 @@
 	cnodeid_t cnode;
 	lboard_t *brd;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_routers: Connecting routers on cnode %d\n",
@@ -703,14 +720,13 @@
 	char dest_path[50];
 	graph_error_t rc;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_hubs: Connecting hubs on cnode %d\n",
 			cnode));
 
-		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IP27);
+		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 		ASSERT(brd);
 
 		hub = (klhub_t *)find_first_component(brd, KLSTRUCT_HUB);
@@ -732,7 +748,7 @@
 		rc = hwgraph_traverse(hwgraph_root, path_buffer, &hub_hndl);
 
 		if (rc != GRAPH_SUCCESS)
-			PRINT_WARNING("Can't find hub: %s", path_buffer);
+			printk(KERN_WARNING  "Can't find hub: %s", path_buffer);
 
 		dest_brd = (lboard_t *)NODE_OFFSET_TO_K0(
 				hub->hub_port.port_nasid,
@@ -757,7 +773,7 @@
 
 			if (rc != GRAPH_SUCCESS)
 				PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p, error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 
 		}
 	}
@@ -782,7 +798,7 @@
 #ifdef	LATER
 	device_admin_table_init();
 #endif
-	for(cnode = 0; cnode < numnodes; cnode++) {
+	for(cnode = 0; cnode < num_compact_nodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 		board = (lboard_t *)KL_CONFIG_INFO(nasid);
 		/* Check out all the board info stored  on a node */
@@ -904,12 +920,12 @@
 
 	FIXME("klhwg_add_all_nodes: FIX GDA\n");
 
-	for (cnode = 0; cnode < numnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		ASSERT(gdap->g_nasidtable[cnode] != INVALID_NASID);
 		klhwg_add_node(hwgraph_root, cnode, gdap);
 	}
 
-	for (cnode = 0; cnode < numnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		ASSERT(gdap->g_nasidtable[cnode] != INVALID_NASID);
 
 		klhwg_add_xbow(cnode, gdap->g_nasidtable[cnode]);
diff -urN linux-2.4.16/arch/ia64/sn/io/klgraph_hack.c lia64-2.4/arch/ia64/sn/io/klgraph_hack.c
--- linux-2.4.16/arch/ia64/sn/io/klgraph_hack.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/klgraph_hack.c	Mon Nov 19 23:22:50 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -18,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/klconfig.h>
 
 void * real_port;
@@ -45,115 +45,10 @@
 #define HUBREG                  ((char *)0xc0000a0001e00000)
 #define WIDGET0                 ((char *)0xc0000a0000000000)
 
-int test = 0;
-
-/*
- * Hack to loop for test.
- */
-void
-test_io_regs(void)
-{
-
-	uint32_t reg_32bits;
-	uint64_t reg_64bits;
-
-	while (test) {
-
-		reg_32bits = (uint32_t)(*(volatile uint32_t *) SYNERGY_WIDGET);
-		reg_64bits = (uint64_t) (*(volatile uint64_t *) SYNERGY_WIDGET);
-
-	}
-
-        printk("Synergy Widget Address = 0x%p, Value = 0x%lx\n", SYNERGY_WIDGET, (uint64_t)*(SYNERGY_WIDGET));
-
-        printk("Synergy swizzle Address = 0x%p, Value = 0x%lx\n", SYNERGY_SWIZZLE, (uint64_t)*(SYNERGY_SWIZZLE));
-        printk("HUBREG  Address = 0x%p, Value = 0x%lx\n",  HUBREG, (uint64_t)*(HUBREG));
-        printk("WIDGET0 Address = 0x%p, Value = 0x%lx\n", WIDGET0, (uint64_t)*(WIDGET0));
-        printk("WIDGET4 Address = 0x%p, Value = 0x%x\n", WIDGET4, (uint32_t)*(WIDGET4));
-
-}
-
 void
 klgraph_hack_init(void)
 {
 
-	kl_config_hdr_t *kl_hdr_ptr;
-	lboard_t	*lb_ptr;
-	lboard_t	*temp_ptr;
-	klhub_t		*klhub_ptr;
-	klioc3_t	*klioc3_ptr;
-	klbri_t		*klbri_ptr;
-	klxbow_t	*klxbow_ptr;
-	klinfo_t	*klinfo_ptr;
-	klcomp_t	*klcomp_ptr;
-#if 0
-	uint64_t	*tmp;
-	volatile u32	*tmp32;
-
-	/* Preset some values */
-	/* Write IOERR clear to clear the CRAZY bit in the status */
-	tmp = (uint64_t *)0xc0000a0001c001f8; *tmp = (uint64_t)0xffffffff;
-	/* set widget control register...setting bedrock widget id to b */
-	/* tmp = (uint64_t *)0xc0000a0001c00020; *tmp = (uint64_t)0x801b; */
-	/* set io outbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00110; *tmp = (uint64_t)0xff01;
-	/* set io inbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00118; *tmp = (uint64_t)0xff01;
-	/* set io crb timeout to max */
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	
-	/* set local block io permission...allow all */
-	tmp = (uint64_t *)0xc0000a0001e04010; *tmp = (uint64_t)0xfffffffffffffff;
-
-	/* clear any errors */
-	clear_ii_error();
-
-	/* set default read response buffers in bridge */
-	tmp32 = (volatile u32 *)0xc0000a000f000280L;
-	*tmp32 = 0xba98;
-	tmp32 = (volatile u32 *)0xc0000a000f000288L;
-	*tmp32 = 0xba98;
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001c00000, *( (volatile uint64_t *)0xc0000a0001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001e00000, *( (volatile uint64_t *)0xc000020001e00000) );
-
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001c00000, *( (volatile uint64_t *)0xc000020001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc0000a0000000000, *( (volatile uint32_t *)0xc0000a0000000000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc000020000000004, *( (volatile uint32_t *)0xc000020000000004) );
-
-#endif
-
-	if ( test )
-		test_io_regs();
-	/*
-	 * Klconfig header.
-	 */
-	kl_hdr_ptr = kmalloc(sizeof(kl_config_hdr_t), GFP_KERNEL);
-        kl_hdr_ptr->ch_magic = 0xbeedbabe;
-        kl_hdr_ptr->ch_version = 0x0;
-        kl_hdr_ptr->ch_malloc_hdr_off = 0x48;
-        kl_hdr_ptr->ch_cons_off = 0x18;
-        kl_hdr_ptr->ch_board_info = 0x0;
-        kl_hdr_ptr->ch_cons_info.uart_base = 0x920000000f820178;
-        kl_hdr_ptr->ch_cons_info.config_base = 0x920000000f024000;
-        kl_hdr_ptr->ch_cons_info.memory_base = 0x920000000f800000;
-        kl_hdr_ptr->ch_cons_info.baud = 0x2580;
-        kl_hdr_ptr->ch_cons_info.flag = 0x1;
-        kl_hdr_ptr->ch_cons_info.type = 0x300fafa;
-        kl_hdr_ptr->ch_cons_info.nasid = 0x0;
-        kl_hdr_ptr->ch_cons_info.wid = 0xf;
-        kl_hdr_ptr->ch_cons_info.npci = 0x4;
-        kl_hdr_ptr->ch_cons_info.baseio_nic = 0x0;
-
 	/*
 	 * We need to know whether we are booting from PROM or 
 	 * boot from disk.
@@ -162,483 +57,9 @@
 	if (linux_klcfg->ch_magic == 0xbeedbabe) {
 		return;
 	} else {
-		linux_klcfg = kl_hdr_ptr;
+		panic("klgraph_hack_init: Unable to locate KLCONFIG TABLE\n");
 	}
 
-	/*
-	 * lboard KLTYPE_IP35
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	kl_hdr_ptr->ch_board_info = (klconf_off_t) lb_ptr;
-	temp_ptr = lb_ptr;
-	printk("First Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x11;
-        lb_ptr->brd_sversion = 0x3;
-        lb_ptr->brd_brevision = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x0;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x5;
-        lb_ptr->brd_nic = 0x2a0aed35;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = 0x0;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0x26;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * Hub Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klhub_ptr = (klhub_t *)klcomp_ptr;
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("hub info = %p lboard = %p\n", klhub_ptr, lb_ptr);
-
-	klinfo_ptr = (klinfo_t *)klhub_ptr;
-        klinfo_ptr->struct_type = 0x2;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0x2a0aed35;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klhub_ptr->hub_flags = 0x0;
-        klhub_ptr->hub_port.port_nasid = (nasid_t)0x0ffffffff;
-        klhub_ptr->hub_port.port_flag = 0x0;
-        klhub_ptr->hub_port.port_offset = 0x0;
-        klhub_ptr->hub_box_nic = 0x0;
-        klhub_ptr->hub_mfg_nic = 0x3f420;
-        klhub_ptr->hub_speed = 0xbebc200;
-
-	/*
-	 * Memory Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x3;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0xffffffff;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_HUB_UART Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x11;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x1;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[5] = 0; /* Set the next one to 0 .. end */
-	lb_ptr->brd_numcompts = 5; /* 0 to 4 */
-
-	/*
-	 * lboard(0x42) KLTYPE_PBRICK_XBOW
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Second Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x42;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0xffffffffffffffff;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030070;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-        memcpy(&lb_ptr->brd_name[0], "IOBRICK", 7);
-
-	/*
-	 * KLSTRUCT_XBOW Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	memset(klcomp_ptr, 0, sizeof(klcomp_t));
-        klxbow_ptr = (klxbow_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("xbow_p 0x%p\n", klcomp_ptr);
-
-        klinfo_ptr->struct_type = 0x4;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klxbow_ptr->xbow_master_hub_link = 0xb;
-        klxbow_ptr->xbow_port_info[0].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[1].port_nasid = 0x401;
-        klxbow_ptr->xbow_port_info[1].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[1].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[2].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[3].port_nasid = 0x0; /* ffffffff */
-        klxbow_ptr->xbow_port_info[3].port_flag = 0x6;
-        klxbow_ptr->xbow_port_info[3].port_offset = 0x30070;
-
-        klxbow_ptr->xbow_port_info[4].port_nasid = 0x0; /* ffffff00; */
-        klxbow_ptr->xbow_port_info[4].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[4].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[5].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_offset = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[6].port_offset = 0x30210;
-        klxbow_ptr->xbow_port_info[7].port_nasid = 0x3;
-        klxbow_ptr->xbow_port_info[7].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[7].port_offset = 0x302e0;
-	
-	lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Third Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x41;
-        lb_ptr->brd_slot = 0xe;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xe;
-        klinfo_ptr->virtid = 0xe;
-        klinfo_ptr->widid = 0xe;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f4a8;
-
-        lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Fourth Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0x0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x31;
-        lb_ptr->brd_slot = 0xf;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x6;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xf;
-        klinfo_ptr->virtid = 0xf;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f528;
-
-	/*
-	 * KLSTRUCT_SCSI component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x5;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_IOC3 Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klioc3_ptr = (klioc3_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x6;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x4;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klioc3_ptr->ioc3_ssram = 0x0;
-        klioc3_ptr->ioc3_nvram = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x5;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_SCSI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x6;
-        klinfo_ptr->virtid = 0x5;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[5] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x7;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[6] = 0;
-	lb_ptr->brd_numcompts = 6;
-
 }
 
 
@@ -658,7 +79,7 @@
 	volatile long long *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%p\n", xx, *xx);
+		printk("0x%p : 0x%p\n", (void *)xx, (void *)*xx);
 	}
 }
 
@@ -669,7 +90,7 @@
 	volatile unsigned int *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%0x\n", xx, *xx);
+		printk("0x%p : 0x%0x\n", (void *)xx, (int)*xx);
 	}
 }
 
diff -urN linux-2.4.16/arch/ia64/sn/io/l1.c lia64-2.4/arch/ia64/sn/io/l1.c
--- linux-2.4.16/arch/ia64/sn/io/l1.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/l1.c	Mon Nov 19 23:22:51 2001
@@ -4,8 +4,8 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */
 
 /* In general, this file is organized in a hierarchy from lower-level
@@ -16,18 +16,12 @@
  *	System controller "message" interface (allows multiplexing
  *		of various kinds of requests and responses with
  *		console I/O)
- *	Console interfaces (there are two):
- *	  (1) "elscuart", used in the IP35prom and (maybe) some
- *		debugging situations elsewhere, and
- *	  (2) "l1_cons", the glue that allows the L1 to act
+ *	Console interface:
+ *	  "l1_cons", the glue that allows the L1 to act
  *		as the system console for the stdio libraries
  *
  * Routines making use of the system controller "message"-style interface
- * can be found in l1_command.c.  Their names are leftover from early SN0, 
- * when the "module system controller" (msc) was known as the "entry level
- * system controller" (elsc).  The names and signatures of those functions 
- * remain unchanged in order to keep the SN0 -> SN1 system controller
- * changes fairly localized.
+ * can be found in l1_command.c.
  */
 
 
@@ -36,44 +30,27 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/uart16550.h>
+#include <asm/sn/simulator.h>
 
-#include <asm/sn/sn1/uart16550.h>
 
-/*
- * Delete this when atomic_clear is part of atomic.h.
- */
-static __inline__ int
-atomic_clear (int i, atomic_t *v)
-{
-	__s32 old, new;
-
-	do {
-		old = atomic_read(v);
-		new = old & ~i;
-	} while (ia64_cmpxchg("acq", v, old, new, sizeof(atomic_t)) != old);
-	return new;
-}
-
-#if defined(EEPROM_DEBUG)
-#define db_printf(x) printk x
-#else
-#define db_printf(x)
-#endif
+/* Make all console writes atomic */
+#define SYNC_CONSOLE_WRITE	1
 
-// From irix/kern/sys/SN/SN1/bdrkhspecregs.h
-#define    HSPEC_UART_0              0x00000080    /* UART Registers         */
 
 /*********************************************************************
  * Hardware-level (UART) driver routines.
@@ -81,28 +58,33 @@
 
 /* macros for reading/writing registers */
 
-#define LD(x)		(*(volatile uint64_t *)(x))
-#define SD(x, v)        (LD(x) = (uint64_t) (v))
+#define LD(x)			(*(volatile uint64_t *)(x))
+#define SD(x, v)        	(LD(x) = (uint64_t) (v))
 
 /* location of uart receive/xmit data register */
-#define L1_UART_BASE(n)	((ulong)REMOTE_HSPEC_ADDR((n), HSPEC_UART_0))
-#define LOCAL_HUB	LOCAL_HUB_ADDR
-#define LOCK_HUB	REMOTE_HUB_ADDR
-
-#define ADDR_L1_REG(n, r)	\
-    (L1_UART_BASE(n) | ( (r) << 3 ))
+#if defined(CONFIG_IA64_SGI_SN1)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HSPEC_ADDR((n), 0x00000080))
+#define LOCK_HUB		REMOTE_HUB_ADDR
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HUB((n), SH_JUNK_BUS_UART0))
+#define LOCK_HUB		REMOTE_HUB
+typedef u64 rtc_time_t;
+#endif
 
-#define READ_L1_UART_REG(n, r) \
-    ( LD(ADDR_L1_REG((n), (r))) )
 
-#define WRITE_L1_UART_REG(n, r, v) \
-    ( SD(ADDR_L1_REG((n), (r)), (v)) )
+#define ADDR_L1_REG(n, r)	( L1_UART_BASE(n) | ( (r) << 3 ) )
+#define READ_L1_UART_REG(n, r)	( LD(ADDR_L1_REG((n), (r))) )
+#define WRITE_L1_UART_REG(n, r, v) ( SD(ADDR_L1_REG((n), (r)), (v)) )
+
+/* upper layer interface calling methods */
+#define SERIAL_INTERRUPT_MODE	0
+#define SERIAL_POLLED_MODE	1
 
 
 /* UART-related #defines */
 
 #define UART_BAUD_RATE		57600
-#define UART_FIFO_DEPTH		0xf0
+#define UART_FIFO_DEPTH		16
 #define UART_DELAY_SPAN		10
 #define UART_PUTC_TIMEOUT	50000
 #define UART_INIT_TIMEOUT	100000
@@ -115,16 +97,35 @@
 #define UART_VECTOR		(-4)
 
 #ifdef BRINGUP
-#define UART_DELAY(x)	{ int i; i = x * 1000; while (--i); }
+#define UART_DELAY(x)		{ int iii; iii = x * 1000; while (--iii); }
 #else
-#define UART_DELAY(x)	us_delay(x)
+#define UART_DELAY(x)		us_delay(x)
 #endif
 
+/* Some debug counters */
+#define L1C_INTERRUPTS		0
+#define L1C_OUR_R_INTERRUPTS	1
+#define L1C_OUR_X_INTERRUPTS	2
+#define L1C_SEND_CALLUPS	3
+#define L1C_RECEIVE_CALLUPS	4
+#define L1C_SET_BAUD		5
+#define L1C_ALREADY_LOCKED	L1C_SET_BAUD
+#define L1C_R_IRQ		6
+#define L1C_R_IRQ_RET		7
+#define L1C_LOCK_TIMEOUTS	8
+#define L1C_LOCK_COUNTER	9
+#define L1C_UNLOCK_COUNTER	10
+#define L1C_REC_STALLS		11
+#define L1C_CONNECT_CALLS	12
+#define L1C_SIZE		L1C_CONNECT_CALLS	/* Set to the last one */
+
+uint64_t L1_collectibles[L1C_SIZE + 1];
+
+
 /*
  *	Some macros for handling Endian-ness
  */
 
-#ifdef	LITTLE_ENDIAN
 #define COPY_INT_TO_BUFFER(_b, _i, _n)		\
 	{					\
 		_b[_i++] = (_n >> 24) & 0xff;	\
@@ -149,41 +150,61 @@
 	    _xyz[1] = _b[_i++];			\
 	    _xyz[0] = _b[_i++];			\
 	}
-#else	/* BIG_ENDIAN */
 
-extern char *bcopy(const char * src, char * dest, int count);
-
-#define COPY_INT_TO_BUFFER(_b, _i, _n)			\
-	{						\
-		bcopy((char *)&_n, _b, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
+void snia_kmem_free(void *where, int size);
 
-#define COPY_BUFFER_TO_INT(_b, _i, _n)			\
-	{						\
-		bcopy(&_b[_i], &_n, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
+#define ALREADY_LOCKED		1
+#define NOT_LOCKED		0
+static int early_l1_serial_out(nasid_t, char *, int, int /* defines above*/ );
 
-#define COPY_BUFFER_TO_BUFFER(_b, _i, _bn)		\
-	{						\
-            bcopy(&(_b[_i]), _bn, sizeof(int));		\
-            _i += sizeof(int);				\
-	}
-#endif	/* LITTLE_ENDIAN */
+#define BCOPY(x,y,z)	memcpy(y,x,z)
 
-void kmem_free(void *where, int size);
+uint8_t L1_interrupts_connected;		/* Non-zero when we are in interrupt mode */
 
-#define BCOPY(x,y,z)	memcpy(y,x,z)
 
 /*
  * Console locking defines and functions.
  *
  */
 
-#ifdef BRINGUP
-#define FORCE_CONSOLE_NASID
-#endif
+uint8_t L1_cons_is_inited = 0;			/* non-zero when console is init'd */
+nasid_t Master_console_nasid = (nasid_t)-1;
+extern nasid_t console_nasid;
+
+u64 ia64_sn_get_console_nasid(void);
+
+inline nasid_t
+get_master_nasid(void)
+{
+#if defined(CONFIG_IA64_SGI_SN1)
+	nasid_t nasid = Master_console_nasid;
+
+	if ( nasid == (nasid_t)-1 ) {
+		nasid = (nasid_t)ia64_sn_get_console_nasid();
+		if ( (nasid < 0) || (nasid >= MAX_NASIDS) ) {
+			/* Out of bounds, use local */
+			console_nasid = nasid = get_nasid();
+		}
+		else {
+			/* Got a valid nasid, set the console_nasid */
+			char xx[100];
+/* zzzzzz - force nasid to 0 for now */
+			sprintf(xx, "Master console is set to nasid %d (%d)\n", 0, (int)nasid);
+nasid = 0;
+/* end zzzzzz */
+			xx[99] = (char)0;
+			early_l1_serial_out(nasid, xx, strlen(xx), NOT_LOCKED);
+			Master_console_nasid = console_nasid = nasid;
+		}
+	}
+	return(nasid);
+#else
+	return((nasid_t)0);
+#endif	/* CONFIG_IA64_SGI_SN1 */
+}
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
 
 #define HUB_LOCK		16
 
@@ -199,7 +220,6 @@
 
 #define RTC_TIME_MAX		((rtc_time_t) ~0ULL)
 
-
 /*
  * primary_lock
  *
@@ -295,26 +315,37 @@
 
 #define LOCK_TIMEOUT	(0x1500000 * 1) /* 0x1500000 is ~30 sec */
 
-inline void
+void
 lock_console(nasid_t nasid)
 {
 	int ret;
 
+	/* If we already have it locked, just return */
+	L1_collectibles[L1C_LOCK_COUNTER]++;
+
 	ret = hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
 	if ( ret != 0 ) {
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 		/* timeout */
 		hub_unlock(nasid, HUB_LOCK);
 		/* If the 2nd lock fails, just pile ahead.... */
 		hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 	}
 }
 
 inline void
 unlock_console(nasid_t nasid)
 {
+	L1_collectibles[L1C_UNLOCK_COUNTER]++;
 	hub_unlock(nasid, HUB_LOCK);
 }
 
+#else /* SN2 */
+inline void lock_console(nasid_t n)	{}
+inline void unlock_console(nasid_t n)	{}
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 int 
 get_L1_baud(void)
@@ -325,27 +356,18 @@
 
 /* uart driver functions */
 
-static void
+static inline void
 uart_delay( rtc_time_t delay_span )
 {
     UART_DELAY( delay_span );
 }
 
-#define UART_PUTC_READY(n)      ( (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE) && (READ_L1_UART_REG((n), REG_MSR) & MSR_CTS) )
+#define UART_PUTC_READY(n)      (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE)
 
 static int
 uart_putc( l1sc_t *sc ) 
 {
-#ifdef BRINGUP
-    /* need a delay to avoid dropping chars */
-    UART_DELAY(57);
-#endif
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    sc->nasid = 0;
-#endif
-    WRITE_L1_UART_REG( sc->nasid, REG_DAT,
-		       sc->send[sc->sent] );
+    WRITE_L1_UART_REG( sc->nasid, REG_DAT, sc->send[sc->sent] );
     return UART_SUCCESS;
 }
 
@@ -356,10 +378,6 @@
     u_char lsr_reg = 0;
     nasid_t nasid = sc->nasid;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     if( (lsr_reg = READ_L1_UART_REG( nasid, REG_LSR )) & 
 	(LSR_RCA | LSR_PARERR | LSR_FRMERR) ) 
     {
@@ -396,9 +414,10 @@
 	}
     }
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	lock_console(nasid);
 
+    /* Setup for the proper baud rate */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_DLAB );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_DLH, (clkdiv >> 8) & 0xff );
@@ -407,6 +426,8 @@
 	uart_delay( UART_DELAY_SPAN );
 
     /* set operating parameters and set DLAB to 0 */
+
+    /* 8bit, one stop, clear request to send, auto flow control */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_BITS8 | LCR_STOP1 );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_MCR, MCR_RTS | MCR_AFE );
@@ -416,23 +437,28 @@
     WRITE_L1_UART_REG( nasid, REG_ICR, 0x0 );
 	uart_delay( UART_DELAY_SPAN );
 
-    /* enable FIFO mode and reset both FIFOs */
+    /* enable FIFO mode and reset both FIFOs, trigger on 1 */
     WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN );
 	uart_delay( UART_DELAY_SPAN );
-    WRITE_L1_UART_REG( nasid, REG_FCR,
-	FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO );
+    WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL0);
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	unlock_console(nasid);
 }
 
 /* This requires the console lock */
+
+#if	defined(CONFIG_IA64_SGI_SN1)
+
 static void
 uart_intr_enable( l1sc_t *sc, u_char mask )
 {
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -444,6 +470,9 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg |= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
 
 /* This requires the console lock */
@@ -453,6 +482,9 @@
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -464,7 +496,11 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg &= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 #define uart_enable_xmit_intr(sc) \
 	uart_intr_enable((sc), ICR_TIEN)
@@ -511,10 +547,6 @@
     net_vec_t path = sc->uart;
     rtc_time_t expire = rtc_time() + RTR_UART_PUTC_TIMEOUT;
 
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    nasid = sc->nasid = 0;
-#endif
     c = (sc->send[sc->sent] & 0xffULL);
     
     while( 1 ) 
@@ -543,10 +575,6 @@
     nasid_t nasid = sc->nasid;
     net_vec_t path = sc->uart;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     READ_RTR_L1_UART_REG( path, nasid, REG_LSR, &regval );
     if( regval & (LSR_RCA | LSR_PARERR | LSR_FRMERR) )
     {
@@ -617,6 +645,15 @@
     return 0;
 }
 
+/*********************************************************************
+ * locking macros 
+ */
+
+#define L1SC_SEND_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->send_lock),p); }
+#define L1SC_SEND_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->send_lock), p); }
+#define L1SC_RECV_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->recv_lock), p); } 
+#define L1SC_RECV_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->recv_lock), p); }
+
 
 /*********************************************************************
  * subchannel manipulation 
@@ -626,31 +663,43 @@
  * associated with particular subchannels (e.g., receive queues).
  *
  */
-
-#ifdef SPINLOCKS_WORK
-#define SUBCH_LOCK(sc)			spin_lock_irq( &((sc)->subch_lock) )
-#define SUBCH_UNLOCK(sc)		spin_unlock_irq( &((sc)->subch_lock) )
-#define SUBCH_DATA_LOCK(sbch) 		spin_lock_irq( &((sbch)->data_lock) )
-#define SUBCH_DATA_UNLOCK(sbch)		spin_unlock_irq( &((sbch)->data_lock) )
-#else
-#define SUBCH_LOCK(sc)
-#define SUBCH_UNLOCK(sc)
-#define SUBCH_DATA_LOCK(sbch)
-#define SUBCH_DATA_UNLOCK(sbch)
-#endif
+#define SUBCH_LOCK(sc, p)		spin_lock_irqsave( &((sc)->subch_lock), p )
+#define SUBCH_UNLOCK(sc, p)		spin_unlock_irqrestore( &((sc)->subch_lock), p )
+#define SUBCH_DATA_LOCK(sbch, p) 	spin_lock_irqsave( &((sbch)->data_lock), p )
+#define SUBCH_DATA_UNLOCK(sbch, p)	spin_unlock_irqrestore( &((sbch)->data_lock), p )
 
 
-/* get_myid is an internal function that reads the PI_CPU_NUM
- * register of the local bedrock to determine which of the
- * four possible CPU's "this" one is
+/*
+ * set a function to be called for subchannel ch in the event of
+ * a transmission low-water interrupt from the uart
  */
-static int
-get_myid( void )
+void
+subch_set_tx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
 {
-    return( LD(LOCAL_HUB(PI_CPU_NUM)) );
+    unsigned long pl = 0;
+
+    L1SC_SEND_LOCK( sc, pl );
+#if	!defined(SYNC_CONSOLE_WRITE)
+    if ( func && !sc->send_in_use )
+	uart_enable_xmit_intr( sc );
+#endif
+    sc->subch[ch].tx_notify = func;
+    L1SC_SEND_UNLOCK(sc, pl );
 }
 
+/*
+ * set a function to be called for subchannel ch when data is received
+ */
+void
+subch_set_rx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
+{
+    unsigned long pl = 0;
+    brl1_sch_t *subch = &(sc->subch[ch]);
 
+    SUBCH_DATA_LOCK( subch, pl );
+    sc->subch[ch].rx_notify = func;
+    SUBCH_DATA_UNLOCK( subch, pl );
+}
 
 /*********************************************************************
  * Queue manipulation macros
@@ -767,14 +816,16 @@
  * brl1_discard_packet is a dummy "receive callback" used to get rid
  * of packets we don't want
  */
-void brl1_discard_packet( l1sc_t *sc, int ch )
+void brl1_discard_packet( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch = &sc->subch[ch];
+
     sc_cq_t *q = subch->iqp;
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     q->opos = q->ipos;
-    atomic_clear( &(subch->packet_arrived), ~((unsigned)0) );
-    SUBCH_DATA_UNLOCK( subch );
+    atomic_set(&(subch->packet_arrived), 0);
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 
@@ -789,17 +840,15 @@
 static int
 brl1_send_chars( l1sc_t *sc )
 {
-    /* In the kernel, we track the depth of the C brick's UART's
+    /* We track the depth of the C brick's UART's
      * fifo in software, and only check if the UART is accepting
      * characters when our count indicates that the fifo should
      * be full.
      *
-     * For remote (router) UARTs, and also for the local (C brick)
-     * UART in the prom, we check with the UART before sending every
+     * For remote (router) UARTs, we check with the UART before sending every
      * character.
      */
-    if( sc->uart == BRL1_LOCALUART ) 
-    {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	if( !(sc->fifo_space) && UART_PUTC_READY( sc->nasid ) )
 	    sc->fifo_space = UART_FIFO_DEPTH;
 	
@@ -809,16 +858,10 @@
 	    sc->sent++;
 	}
     }
+    else {
 
-    else
-
-    /* The following applies to all UARTs in the prom, and to remote
-     * (router) UARTs in the kernel...
-     */
-
-#define TIMEOUT_RETRIES	30
+	/* remote (router) UARTs */
 
-    {
 	int result;
 	int tries = 0;
 
@@ -831,7 +874,7 @@
 	    if( result == UART_TIMEOUT ) {
 		tries++;
 		/* send this character in TIMEOUT_RETRIES... */
-		if( tries < TIMEOUT_RETRIES ) {
+		if( tries < 30 /* TIMEOUT_RETRIES */ ) {
 		    continue;
 		}
 		/* ...or else... */
@@ -864,33 +907,39 @@
 static int
 brl1_send( l1sc_t *sc, char *msg, int len, u_char type_and_subch, int wait )
 {
+    unsigned long pl = 0;
     int index;
     int pkt_len = 0;
     unsigned short crc = INIT_CRC;
     char *send_ptr = sc->send;
 
-#ifdef BRINGUP
-    /* We want to be sure that we are sending the entire packet before returning */
-    wait = 1;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
 
-    if( sc->send_in_use ) {
-	if( !wait ) {
-    	    if ( sc->uart == BRL1_LOCALUART )
-	    	unlock_console(sc->nasid);
-	    return 0; /* couldn't send anything; wait for buffer to drain */
-	}
-	else {
-	    /* buffer's in use, but we're synchronous I/O, so we're going
-	     * to send whatever's in there right now and take the buffer
-	     */
-	    while( sc->sent < sc->send_len )
+    if( sc->send_in_use && !(wait) ) {
+	/* We are in the middle of sending, but can wait until done */
+	return 0;
+    }
+    else if( sc->send_in_use ) {
+	/* buffer's in use, but we're synchronous I/O, so we're going
+	 * to send whatever's in there right now and take the buffer
+	 */
+	int counter = 0;
+
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
+	while( sc->sent < sc->send_len ) {
 		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (1)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
 	}
     }
     else {
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
 	sc->send_in_use = 1;
     }
     *send_ptr++ = BRL1_FLAG_CH;
@@ -948,23 +997,100 @@
     sc->send_len = pkt_len;
     sc->sent = 0;
 
-    do {
-	brl1_send_chars( sc );
-    } while( (sc->sent < sc->send_len) && wait );
+    {
+	int counter = 0;
+	do {
+		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (2)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
+	} while( (sc->sent < sc->send_len) && wait );
+    }
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
 
     if( sc->sent == sc->send_len ) {
-	/* success! release the send buffer */
+	/* success! release the send buffer and call the callup */
+#if	!defined(SYNC_CONSOLE_WRITE)
+	brl1_notif_t callup;
+#endif
+
 	sc->send_in_use = 0;
+	/* call any upper layer that's asked for notification */
+#if	defined(XX_SYNC_CONSOLE_WRITE)
+	/*
+	 * This is probably not a good idea - since the l1_ write func can be called multiple
+	 * time within the callup function.
+	 */
+	callup = subch->tx_notify;
+	if( callup && (SUBCH(type_and_subch) == SC_CONS_SYSTEM) ) {
+		L1_collectibles[L1C_SEND_CALLUPS]++;
+		(*callup)(sc->subch[SUBCH(type_and_subch)].irq_frame.bf_irq,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_regs, sc, SUBCH(type_and_subch));
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
     }
-    else if( !wait ) {
+#if	!defined(SYNC_CONSOLE_WRITE)
+    else if ( !wait ) {
 	/* enable low-water interrupts so buffer will be drained */
 	uart_enable_xmit_intr(sc);
     }
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+#endif
+
+    L1SC_SEND_UNLOCK(sc, pl);
+
     return len;
 }
 
+/* brl1_send_cont is intended to be called as an interrupt service
+ * routine.  It sends until the UART won't accept any more characters,
+ * or until an error is encountered (in which case we surrender the
+ * send buffer and give up trying to send the packet).  Once the
+ * last character in the packet has been sent, this routine releases
+ * the send buffer and calls any previously-registered "low-water"
+ * output routines.
+ */
+
+#if	!defined(SYNC_CONSOLE_WRITE)
+
+int
+brl1_send_cont( l1sc_t *sc )
+{
+    unsigned long pl = 0;
+    int done = 0;
+    brl1_notif_t callups[BRL1_NUM_SUBCHANS];
+    brl1_notif_t *callup;
+    brl1_sch_t *subch;
+    int index;
+
+    /*
+     * I'm not sure how I think this is to be handled - whether the lock is held
+     * over the interrupt - but it seems like it is a bad idea....
+     */
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(sc->nasid);
+    L1SC_SEND_LOCK(sc, pl);
+    brl1_send_chars( sc );
+    done = (sc->sent == sc->send_len);
+    if( done ) {
+	sc->send_in_use = 0;
+#if	!defined(SYNC_CONSOLE_WRITE)
+	uart_disable_xmit_intr(sc);
+#endif
+    }
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
+    /* Release the lock */
+    L1SC_SEND_UNLOCK(sc, pl);
+
+    return 0;
+}
+#endif	/* SYNC_CONSOLE_WRITE */
 
 /* internal function -- used by brl1_receive to read a character 
  * from the uart and check whether errors occurred in the process.
@@ -1046,40 +1172,33 @@
  * error (parity error, bad header, bad CRC, etc.).
  */
 
-#define STATE_SET(l,s)	((l)->brl1_state = (s))
-#define STATE_GET(l)	((l)->brl1_state)
+#define STATE_SET(l,s)		((l)->brl1_state = (s))
+#define STATE_GET(l)		((l)->brl1_state)
 
 #define LAST_HDR_SET(l,h)	((l)->brl1_last_hdr = (h))
 #define LAST_HDR_GET(l)		((l)->brl1_last_hdr)
 
-#define SEQSTAMP_INCR(l)
-#define SEQSTAMP_GET(l)
-
 #define VALID_HDR(c)				\
     ( SUBCH((c)) <= SC_CONS_SYSTEM		\
 	? PKT_TYPE((c)) == BRL1_REQUEST		\
 	: ( PKT_TYPE((c)) == BRL1_RESPONSE ||	\
 	    PKT_TYPE((c)) == BRL1_EVENT ) )
 
-#define IS_TTY_PKT(l) \
-         ( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
+#define IS_TTY_PKT(l)		( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
 
 
 int
-brl1_receive( l1sc_t *sc )
+brl1_receive( l1sc_t *sc, int mode )
 {
     int result;		/* value to be returned by brl1_receive */
     int c;		/* most-recently-read character	     	*/
     int done;		/* set done to break out of recv loop	*/
+    unsigned long pl = 0, cpl = 0;
     sc_cq_t *q;		/* pointer to queue we're working with	*/
 
     result = BRL1_NO_MESSAGE;
 
-#ifdef FORCE_CONSOLE_NASID
-    sc->nasid = 0;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
+    L1SC_RECV_LOCK(sc, cpl);
 
     done = 0;
     while( !done )
@@ -1210,8 +1329,7 @@
 		 * starting a new packet
 		 */
 		STATE_SET( sc, BRL1_FLAG );
-		SEQSTAMP_INCR(sc); /* bump the packet sequence counter */
-		
+
 		/* if the packet body has less than 2 characters,
 		 * it can't be a well-formed packet.  Discard it.
 		 */
@@ -1258,7 +1376,7 @@
 
 		/* get the subchannel and lock it */
 		subch = &(sc->subch[SUBCH( LAST_HDR_GET(sc) )]);
-		SUBCH_DATA_LOCK( subch );
+		SUBCH_DATA_LOCK( subch, pl );
 		
 		/* if this isn't a console packet, we need to record
 		 * a length byte
@@ -1276,14 +1394,16 @@
 		 */
 		atomic_inc(&(subch->packet_arrived));
 		callup = subch->rx_notify;
-		SUBCH_DATA_UNLOCK( subch );
+		SUBCH_DATA_UNLOCK( subch, pl );
 
-		if( callup ) {
-		    if ( sc->uart == BRL1_LOCALUART )
-			unlock_console(sc->nasid);
-		    (*callup)( sc, SUBCH(LAST_HDR_GET(sc)) );
-		    if ( sc->uart == BRL1_LOCALUART )
-			lock_console(sc->nasid);
+		if( callup && (mode == SERIAL_INTERRUPT_MODE) ) {
+		    L1SC_RECV_UNLOCK( sc, cpl );
+		    L1_collectibles[L1C_RECEIVE_CALLUPS]++;
+		    (*callup)( sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_irq,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_regs,
+				sc, SUBCH(LAST_HDR_GET(sc)) );
+		    L1SC_RECV_LOCK( sc, cpl );
 		}
 		continue;	/* go back for more! */
 	    }
@@ -1351,9 +1471,8 @@
 
 	} /* end of switch( STATE_GET(sc) ) */
     } /* end of while(!done) */
-    
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+
+    L1SC_RECV_UNLOCK( sc, cpl );
 
     return result;
 }	    
@@ -1370,13 +1489,10 @@
     brl1_sch_t *subch;
 
     bzero( sc, sizeof( *sc ) );
-#ifdef FORCE_CONSOLE_NASID
-    nasid = (nasid_t)0;
-#endif
     sc->nasid = nasid;
     sc->uart = uart;
-    sc->getc_f = (uart == BRL1_LOCALUART ? uart_getc : rtr_uart_getc);
-    sc->putc_f = (uart == BRL1_LOCALUART ? uart_putc : rtr_uart_putc);
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
     sc->sol = 1;
     subch = sc->subch;
 
@@ -1403,9 +1519,8 @@
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &subch->data_lock, SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */ );
     subch->tx_notify = NULL;
-    if( sc->uart == BRL1_LOCALUART ) {
-	subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
-				       NASID_TO_COMPACT_NODEID(nasid) );
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP, NASID_TO_COMPACT_NODEID(nasid) );
 	ASSERT( subch->iqp );
 	cq_init( subch->iqp );
 	subch->rx_notify = NULL;
@@ -1440,8 +1555,10 @@
     /* initialize synchronization structures
      */
     spin_lock_init( &(sc->subch_lock) );
+    spin_lock_init( &(sc->send_lock) );
+    spin_lock_init( &(sc->recv_lock) );
 
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	uart_init( sc, UART_BAUD_RATE );
     }
     else {
@@ -1461,106 +1578,496 @@
     }
 }
 
+/*********************************************************************
+ * These are interrupt-related functions used in the kernel to service
+ * the L1.
+ */
 
-/* These are functions to use from serial_in/out when in protocol
- * mode to send and receive uart control regs. These are external
- * interfaces into the protocol driver.
+/*
+ * brl1_intrd is the function which is called on a console interrupt.
+ */
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
+static void
+brl1_intrd(int irq, void *dev_id, struct pt_regs *stuff)
+{
+    u_char isr_reg;
+    l1sc_t *sc = get_elsc();
+    int ret;
+
+    L1_collectibles[L1C_INTERRUPTS]++;
+    isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+
+    /* Save for callup args in console */
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_irq = irq;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_dev_id = dev_id;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_regs = stuff;
+
+#if	defined(SYNC_CONSOLE_WRITE)
+    while( isr_reg & ISR_RxRDY )
+#else
+    while( isr_reg & (ISR_RxRDY | ISR_TxRDY) )
+#endif
+    {
+	if( isr_reg & ISR_RxRDY ) {
+	    L1_collectibles[L1C_OUR_R_INTERRUPTS]++;
+	    ret = brl1_receive(sc, SERIAL_INTERRUPT_MODE);
+	    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+		L1_collectibles[L1C_REC_STALLS] = ret;
+	}
+#if	!defined(SYNC_CONSOLE_WRITE)
+	if( (isr_reg & ISR_TxRDY) || (sc->send_in_use && UART_PUTC_READY(sc->nasid)) ) {
+	    L1_collectibles[L1C_OUR_X_INTERRUPTS]++;
+	    brl1_send_cont(sc);
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
+	isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+    }
+}
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+
+/*
+ * Install a callback function for the system console subchannel 
+ * to allow an upper layer to be notified when the send buffer 
+ * has been emptied.
+ */
+static inline void
+l1_tx_notif( brl1_notif_t func )
+{
+	subch_set_tx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+			SC_CONS_SYSTEM, func );
+}
+
+
+/*
+ * Install a callback function for the system console subchannel
+ * to allow an upper layer to be notified when a packet has been
+ * received.
+ */
+static inline void
+l1_rx_notif( brl1_notif_t func )
+{
+	subch_set_rx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+				SC_CONS_SYSTEM, func );
+}
+
+
+/* brl1_intr is called directly from the uart interrupt; after it runs, the
+ * interrupt "daemon" xthread is signalled to continue.
  */
 void
-l1_control_out(int offset, int value)
+brl1_intr( void )
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
-	WRITE_L1_UART_REG(nasid, offset, value); 
 }
 
+#define BRL1_INTERRUPT_LEVEL	65	/* linux request_irq() value */
+
+/* Return the current interrupt level */
+
+//#define CONSOLE_POLLING_ALSO
+
 int
-l1_control_in(int offset)
+l1_get_intr_value( void )
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
-	return(READ_L1_UART_REG(nasid, offset)); 
+#ifdef	CONSOLE_POLLING_ALSO
+	return(0);
+#else
+	return(BRL1_INTERRUPT_LEVEL);
+#endif
 }
 
-#define PUTCHAR(ch) \
-    { \
-        while( (!(READ_L1_UART_REG( nasid, REG_LSR ) & LSR_XHRE)) || \
-                (!(READ_L1_UART_REG( nasid, REG_MSR ) & MSR_CTS)) ); \
-        WRITE_L1_UART_REG( nasid, REG_DAT, (ch) ); \
-    }
+/* Disconnect the callup functions - throw away interrupts */
 
-int
-l1_serial_out( char *str, int len )
+void
+l1_unconnect_intr(void)
 {
-    int sent = len;
-    char crc_char;
-    unsigned short crc = INIT_CRC;
-    nasid_t nasid = 0; //(get_elsc())->nasid;
+	/* UnRegister the upper-level callup functions */
+	l1_rx_notif((brl1_notif_t)NULL);
+	l1_tx_notif((brl1_notif_t)NULL);
+	/* We do NOT unregister the interrupts */
+}
 
-    lock_console(nasid);
+/* Set up uart interrupt handling for this node's uart */
 
-    PUTCHAR( BRL1_FLAG_CH );
-    PUTCHAR( BRL1_EVENT | SC_CONS_SYSTEM );
-    crc = crc16_calc( crc, (BRL1_EVENT | SC_CONS_SYSTEM) );
+void
+l1_connect_intr(void *rx_notify, void *tx_notify)
+{
+	l1sc_t *sc;
+	nasid_t nasid;
+#if defined(CONFIG_IA64_SGI_SN1)
+	int tmp;
+#endif
+	nodepda_t *console_nodepda;
+	int intr_connect_level(cpuid_t, int, ilvl_t, intr_func_t);
 
-    while( len ) {
+	if ( L1_interrupts_connected ) {
+		/* Interrupts are connected, so just register the callups */
+		l1_rx_notif((brl1_notif_t)rx_notify);
+		l1_tx_notif((brl1_notif_t)tx_notify);
 
-	if( (*str == BRL1_FLAG_CH) || (*str == BRL1_ESC_CH) ) {
-	    PUTCHAR( BRL1_ESC_CH );
-	    PUTCHAR( (*str) ^ BRL1_XOR_CH );
+		L1_collectibles[L1C_CONNECT_CALLS]++;
+		return;
+	}
+	else
+		L1_interrupts_connected = 1;
+
+	nasid = get_master_nasid();
+	console_nodepda = NODEPDA(NASID_TO_COMPACT_NODEID(nasid));
+	sc = &console_nodepda->module->elsc;
+	sc->intr_cpu = console_nodepda->node_first_cpu;
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( intr_connect_level(sc->intr_cpu, UART_INTR, INTPEND0_MAXMASK, (intr_func_t)brl1_intr) ) {
+		L1_interrupts_connected = 0; /* FAILS !! */
 	}
 	else {
-	    PUTCHAR( *str );
+		void synergy_intr_connect(int, int);
+
+		synergy_intr_connect(UART_INTR, sc->intr_cpu);
+		L1_collectibles[L1C_R_IRQ]++;
+		tmp = request_irq(BRL1_INTERRUPT_LEVEL, brl1_intrd, SA_INTERRUPT | SA_SHIRQ, "l1_protocol_driver", (void *)sc);
+		L1_collectibles[L1C_R_IRQ_RET] = (uint64_t)tmp;
+		if ( tmp ) {
+			L1_interrupts_connected = 0; /* FAILS !! */
+		}
+		else {
+			/* Register the upper-level callup functions */
+			l1_rx_notif((brl1_notif_t)rx_notify);
+			l1_tx_notif((brl1_notif_t)tx_notify);
+
+			/* Set the uarts the way we like it */
+			uart_enable_recv_intr( sc );
+			uart_disable_xmit_intr( sc );
+		}
 	}
-	
-	crc = crc16_calc( crc, *str );
+#endif	/* CONFIG_IA64_SGI_SN1 */
+}
 
-	str++; len--;
-    }
-    
-    crc ^= 0xffff;
-    crc_char = crc & 0xff;
-    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
-	crc_char ^= BRL1_XOR_CH;
-	PUTCHAR( BRL1_ESC_CH );
-    }
-    PUTCHAR( crc_char );
-    crc_char = (crc >> 8) & 0xff;
-    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
-	crc_char ^= BRL1_XOR_CH;
-	PUTCHAR( BRL1_ESC_CH );
-    }
-    PUTCHAR( crc_char );
-    PUTCHAR( BRL1_FLAG_CH );
 
-    unlock_console(nasid);
-    return sent - len;
-}
+/* Set the line speed */
 
-int
-l1_serial_in(void)
+void
+l1_set_baud(int baud)
 {
-	static int l1_cons_getc( l1sc_t *sc );
+#if 0
+	nasid_t nasid;
+	static void uart_init(l1sc_t *, int);
+#endif
 
-	return(l1_cons_getc(get_elsc()));
+	L1_collectibles[L1C_SET_BAUD]++;
+
+#if 0
+	if ( L1_cons_is_inited ) {
+		nasid = get_master_nasid();
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 )
+			uart_init(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, baud);
+	}
+#endif
+	return;
 }
 
 
-/*********************************************************************
- * l1_cons functions
- *
- * These allow the L1 to act as the system console.  They're intended
- * to abstract away most of the br/l1 internal details from the
- * _L1_cons_* functions (in the prom-- see "l1_console.c") and
- * l1_* functions (in the kernel-- see "sio_l1.c") that they support.
- *
+/* These are functions to use from serial_in/out when in protocol
+ * mode to send and receive uart control regs. These are external
+ * interfaces into the protocol driver.
  */
 
-static int
-l1_cons_poll( l1sc_t *sc )
+void
+l1_control_out(int offset, int value)
 {
-    /* in case this gets called before the l1sc_t structure for the module_t
-     * struct for this node is initialized (i.e., if we're called with a
-     * zero l1sc_t pointer)...
-     */
+	nasid_t nasid = get_master_nasid();
+	WRITE_L1_UART_REG(nasid, offset, value); 
+}
+
+/* Console input exported interface. Return a register value.  */
+
+int
+l1_control_in_polled(int offset)
+{
+	static int l1_control_in_local(int, int);
+
+	return(l1_control_in_local(offset, SERIAL_POLLED_MODE));
+}
+
+int
+l1_control_in(int offset)
+{
+	static int l1_control_in_local(int, int);
+
+	return(l1_control_in_local(offset, SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_control_in_local(int offset, int mode)
+{
+	nasid_t nasid;
+	int ret, input;
+	static int l1_poll(l1sc_t *, int);
+
+	nasid = get_master_nasid();
+	ret = READ_L1_UART_REG(nasid, offset); 
+
+	if ( offset == REG_LSR ) {
+		ret |= (LSR_XHRE | LSR_XSRE);	/* can send anytime */
+		if ( L1_cons_is_inited ) {
+			if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+				input = l1_poll(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, mode);
+				if ( input ) {
+					ret |= LSR_RCA;
+				}
+			}
+		}
+	}
+	return(ret);
+}
+
+/*
+ * Console input exported interface. Return a character (if one is available)
+ */
+
+int
+l1_serial_in_polled(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_POLLED_MODE));
+}
+
+int
+l1_serial_in(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_serial_in_local(int mode)
+{
+	nasid_t nasid;
+	l1sc_t *sc;
+	int value;
+	static int l1_getc( l1sc_t *, int );
+	static inline l1sc_t *early_sc_init(nasid_t);
+
+	nasid = get_master_nasid();
+	sc = early_sc_init(nasid);
+	if ( L1_cons_is_inited ) {
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+			sc = &NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc;
+		}
+	}
+	value = l1_getc(sc, mode);
+	return(value);
+}
+
+/* Console output exported interface. Write message to the console.  */
+
+int
+l1_serial_out( char *str, int len )
+{
+	nasid_t nasid = get_master_nasid();
+	int l1_write(l1sc_t *, char *, int, int);
+
+	if ( L1_cons_is_inited ) {
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 )
+			return(l1_write(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, str, len,
+#if	defined(SYNC_CONSOLE_WRITE)
+					1
+#else
+					!L1_interrupts_connected
+#endif
+							));
+	}
+	return(early_l1_serial_out(nasid, str, len, NOT_LOCKED));
+}
+
+
+/*
+ * These are the 'early' functions - when we need to do things before we have
+ * all the structs setup.
+ */
+
+static l1sc_t Early_console;		/* fake l1sc_t */
+static int Early_console_inited = 0;
+
+static void
+early_brl1_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
+{
+    int i;
+    brl1_sch_t *subch;
+
+    bzero( sc, sizeof( *sc ) );
+    sc->nasid = nasid;
+    sc->uart = uart;
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
+    sc->sol = 1;
+    subch = sc->subch;
+
+    /* initialize L1 subchannels
+     */
+
+    /* assign processor TTY channels */
+    for( i = 0; i < CPUS_PER_NODE; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_RSVD;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* assign system TTY channel (first free subchannel after each
+     * processor's individual TTY channel has been assigned)
+     */
+    subch->use = BRL1_SUBCH_RSVD;
+    subch->packet_arrived = ATOMIC_INIT(0);
+    subch->tx_notify = NULL;
+    subch->rx_notify = NULL;
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	static sc_cq_t x_iqp;
+
+	subch->iqp = &x_iqp;
+	ASSERT( subch->iqp );
+	cq_init( subch->iqp );
+    }
+    else {
+	/* we shouldn't be getting console input from remote UARTs */
+	subch->iqp = &sc->garbage_q;
+    }
+    subch++; i++;
+
+    /* "reserved" subchannels (0x05-0x0F); for now, throw away
+     * incoming packets
+     */
+    for( ; i < 0x10; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* remaining subchannels are free */
+    for( ; i < BRL1_NUM_SUBCHANS; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+}
+
+static inline l1sc_t *
+early_sc_init(nasid_t nasid)
+{
+	/* This is for early I/O */
+	if ( Early_console_inited == 0 ) {
+    		early_brl1_init(&Early_console, nasid,  BRL1_LOCALHUB_UART);
+		Early_console_inited = 1;
+	}
+	return(&Early_console);
+}
+
+#define PUTCHAR(ch) \
+    { \
+        while( (!(READ_L1_UART_REG( nasid, REG_LSR ) & LSR_XHRE)) || \
+                (!(READ_L1_UART_REG( nasid, REG_MSR ) & MSR_CTS)) ); \
+        WRITE_L1_UART_REG( nasid, REG_DAT, (ch) ); \
+    }
+
+static int
+early_l1_serial_out( nasid_t nasid, char *str, int len, int lock_state )
+{
+	int ret, sent = 0;
+	char *msg = str;
+	static int early_l1_send( nasid_t nasid, char *str, int len, int lock_state );
+
+	while ( sent < len ) {
+		ret = early_l1_send(nasid, msg, len - sent, lock_state);
+		sent += ret;
+		msg += ret;
+	}
+	return(len);
+}
+
+static inline int
+early_l1_send( nasid_t nasid, char *str, int len, int lock_state )
+{
+    int sent;
+    char crc_char;
+    unsigned short crc = INIT_CRC;
+
+    if( len > (BRL1_QSIZE - 1) )
+	len = (BRL1_QSIZE - 1);
+
+    sent = len;
+    if ( lock_state == NOT_LOCKED )
+    	lock_console(nasid);
+
+    PUTCHAR( BRL1_FLAG_CH );
+    PUTCHAR( BRL1_EVENT | SC_CONS_SYSTEM );
+    crc = crc16_calc( crc, (BRL1_EVENT | SC_CONS_SYSTEM) );
+
+    while( len ) {
+
+	if( (*str == BRL1_FLAG_CH) || (*str == BRL1_ESC_CH) ) {
+	    PUTCHAR( BRL1_ESC_CH );
+	    PUTCHAR( (*str) ^ BRL1_XOR_CH );
+	}
+	else {
+	    PUTCHAR( *str );
+	}
+	
+	crc = crc16_calc( crc, *str );
+
+	str++; len--;
+    }
+    
+    crc ^= 0xffff;
+    crc_char = crc & 0xff;
+    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
+	crc_char ^= BRL1_XOR_CH;
+	PUTCHAR( BRL1_ESC_CH );
+    }
+    PUTCHAR( crc_char );
+    crc_char = (crc >> 8) & 0xff;
+    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
+	crc_char ^= BRL1_XOR_CH;
+	PUTCHAR( BRL1_ESC_CH );
+    }
+    PUTCHAR( crc_char );
+    PUTCHAR( BRL1_FLAG_CH );
+
+    if ( lock_state == NOT_LOCKED )
+    	unlock_console(nasid);
+    return sent;
+}
+
+
+/*********************************************************************
+ * l1_cons functions
+ *
+ * These allow the L1 to act as the system console.  They're intended
+ * to abstract away most of the br/l1 internal details from the
+ * _L1_cons_* functions (in the prom-- see "l1_console.c") and
+ * l1_* functions (in the kernel-- see "sio_l1.c") that they support.
+ *
+ */
+
+static int
+l1_poll( l1sc_t *sc, int mode )
+{
+    int ret;
+
+    /* in case this gets called before the l1sc_t structure for the module_t
+     * struct for this node is initialized (i.e., if we're called with a
+     * zero l1sc_t pointer)...
+     */
+
+
     if( !sc ) {
 	return 0;
     }
@@ -1569,7 +2076,9 @@
 	return 1;
     }
 
-    brl1_receive( sc );
+    ret = brl1_receive( sc, mode );
+    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+	L1_collectibles[L1C_REC_STALLS] = ret;
 
     if( atomic_read(&sc->subch[SC_CONS_SYSTEM].packet_arrived) ) {
 	return 1;
@@ -1581,43 +2090,65 @@
 /* pull a character off of the system console queue (if one is available)
  */
 static int
-l1_cons_getc( l1sc_t *sc )
+l1_getc( l1sc_t *sc, int mode )
 {
+    unsigned long pl = 0;
     int c;
 
     brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
     sc_cq_t *q = subch->iqp;
 
-    if( !l1_cons_poll( sc ) ) {
+    if( !l1_poll( sc, mode ) ) {
 	return 0;
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     if( cq_empty( q ) ) {
 	atomic_set(&subch->packet_arrived, 0);
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return 0;
     }
     cq_rem( q, c );
     if( cq_empty( q ) )
 	atomic_set(&subch->packet_arrived, 0);
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return c;
 }
 
+/*
+ * Write a message to the L1 on the system console subchannel.
+ *
+ * Danger: don't use a non-zero value for the wait parameter unless you're
+ * someone important (like a kernel error message).
+ */
+
+int
+l1_write( l1sc_t *sc, char *msg, int len, int wait )
+{
+	int sent = 0, ret = 0;
+
+	if ( wait ) {
+		while ( sent < len ) {
+			ret = brl1_send( sc, msg, len - sent, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+			sent += ret;
+			msg += ret;
+		}
+		ret = len;
+	}
+	else {
+		ret = brl1_send( sc, msg, len, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+	}
+	return(ret);
+}
 
 /* initialize the system console subchannel
  */
 void
-l1_cons_init( l1sc_t *sc )
+l1_init(void)
 {
-    brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
-
-    SUBCH_DATA_LOCK( subch );
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    SUBCH_DATA_UNLOCK( subch );
+	/* All we do now is remember that we have been called */
+	L1_cons_is_inited = 1;
 }
 
 
@@ -1637,16 +2168,18 @@
 #define L1_DBG_PRF(x)
 #endif
 
-/* sc_data_ready is called to signal threads that are blocked on 
- * l1 input.
+/*
+ * sc_data_ready is called to signal threads that are blocked on l1 input.
  */
 void
-sc_data_ready( l1sc_t *sc, int ch )
+sc_data_ready( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
+
     brl1_sch_t *subch = &(sc->subch[ch]);
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     sv_signal( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 /* sc_open reserves a subchannel to send a request to the L1 (the
@@ -1661,9 +2194,10 @@
      * subchannel assignment.
      */
     int ch;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
 
     /* Look for a free subchannel. Subchannels 0-15 are reserved
      * for other purposes.
@@ -1676,12 +2210,12 @@
 
     if( ch == BRL1_NUM_SUBCHANS ) {
         /* there were no subchannels available! */
-        SUBCH_UNLOCK( sc );
+        SUBCH_UNLOCK( sc, pl );
         return SC_NSUBCH;
     }
 
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
     subch->target = target;
@@ -1689,7 +2223,7 @@
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
@@ -1703,29 +2237,31 @@
 int
 sc_close( l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[ch]);
     if( subch->use != BRL1_SUBCH_RSVD ) {
         /* we're trying to close a subchannel that's not open */
+	SUBCH_UNLOCK( sc, pl );
         return SC_NOPEN;
     }
 
     atomic_set(&subch->packet_arrived, 0);
     subch->use = BRL1_SUBCH_FREE;
 
-    SUBCH_DATA_LOCK( subch );
     sv_broadcast( &(subch->arrive_sv) );
     sv_destroy( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
     spin_lock_destroy( &(subch->data_lock) );
 
     ASSERT( subch->iqp && (subch->iqp != &sc->garbage_q) );
-    kmem_free( subch->iqp, sizeof(sc_cq_t) );
+    snia_kmem_free( subch->iqp, sizeof(sc_cq_t) );
     subch->iqp = &sc->garbage_q;
+    subch->tx_notify = NULL;
+    subch->rx_notify = brl1_discard_packet;
 
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     return SC_SUCCESS;
 }
@@ -2033,11 +2569,10 @@
 
     /* Verify that this is an open subchannel
      */
-    if( sc->subch[ch].use == BRL1_SUBCH_FREE )
-    {
+    if( sc->subch[ch].use == BRL1_SUBCH_FREE ) {
         return SC_NOPEN;
     }
-       
+
     type_and_subch = (BRL1_REQUEST | ((u_char)ch));
     result = brl1_send( sc, msg, len, type_and_subch, wait );
 
@@ -2115,6 +2650,7 @@
 sc_recv_poll( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     rtc_time_t exp_time = rtc_time() + block;
@@ -2127,7 +2663,7 @@
 
         /* kick the next lower layer and see if it pulls anything in
          */
-	brl1_receive( sc );
+	brl1_receive( sc, SERIAL_POLLED_MODE );
 	is_msg = atomic_read(&subch->packet_arrived);
 
     } while( block && !is_msg && (rtc_time() < exp_time) );
@@ -2137,9 +2673,9 @@
 	return( SC_NMSG );
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2156,10 +2692,11 @@
 sc_recv_intr( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     do {
-	SUBCH_DATA_LOCK(subch);
+	SUBCH_DATA_LOCK(subch, pl);
 	is_msg = atomic_read(&subch->packet_arrived);
 	if( !is_msg && block ) {
 	    /* wake me when you've got something */
@@ -2178,12 +2715,12 @@
 
     if( !is_msg ) {
 	/* no message and we didn't care to wait for one */
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return( SC_NMSG );
     }
 
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2206,7 +2743,7 @@
  * rewriting of the L1 command interface anyway.)
  */
 #define __RETRIES	50
-#define __WAIT_SEND	( sc->uart != BRL1_LOCALUART )
+#define __WAIT_SEND	1	// ( sc->uart != BRL1_LOCALHUB_UART )
 #define __WAIT_RECV	10000000
 
 
@@ -2237,13 +2774,10 @@
     }
     
     /* block on sc_recv_* */
-#ifdef LATER
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( (sc->uart == BRL1_LOCALHUB_UART) && L1_interrupts_connected ) {
 	return( sc_recv_intr( sc, ch, resp, len, __WAIT_RECV ) );
     }
-    else
-#endif	/* LATER */
-    {
+    else {
 	return( sc_recv_poll( sc, ch, resp, len, __WAIT_RECV ) );
     }
 #endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
@@ -2254,6 +2788,7 @@
  * delayed until the send buffer clears.  sc_command should be used instead
  * under most circumstances.
  */
+
 int
 sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len )
 {
@@ -2282,6 +2817,7 @@
  * Returns 1 if input is available on the given queue,
  * 0 otherwise.
  */
+
 int
 sc_poll( l1sc_t *sc, int ch )
 {
@@ -2290,7 +2826,7 @@
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
 
-    brl1_receive( sc );
+    brl1_receive( sc, SERIAL_POLLED_MODE );
 
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
@@ -2298,8 +2834,8 @@
     return 0;
 }
 
-/* for now, sc_init just calls brl1_init
- */
+/* for now, sc_init just calls brl1_init */
+
 void
 sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
 {
@@ -2311,7 +2847,7 @@
  * network's environmental monitor tasks.
  */
 
-#ifdef LINUX_KERNEL_THREADS
+#if	defined(LINUX_KERNEL_THREADS)
 
 static void
 sc_dispatch_env_event( uint code, int argc, char *args, int maxlen )
@@ -2366,14 +2902,12 @@
 	     i++ );
     }
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 
 /* sc_event waits for events to arrive from the system controller, and
  * prints appropriate messages to the syslog.
  */
 
-#ifdef LINUX_KERNEL_THREADS
 static void
 sc_event( l1sc_t *sc, int ch )
 {
@@ -2394,7 +2928,7 @@
 	 */
 	result = sc_recv_intr( sc, ch, event, &event_len, 1 );
 	if( result != SC_SUCCESS ) {
-	    PRINT_WARNING("Error receiving sysctl event on nasid %d\n",
+	    printk(KERN_WARNING  "Error receiving sysctl event on nasid %d\n",
 		     sc->nasid );
 	}
 	else {
@@ -2438,53 +2972,50 @@
 	
     }			
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 /* sc_listen sets up a service thread to listen for incoming events.
  */
+
 void
 sc_listen( l1sc_t *sc )
 {
     int result;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
     char        msg[BRL1_QSIZE];
     int         len;    /* length of message being sent */
     int         ch;     /* system controller subchannel used */
 
-#ifdef LINUX_KERNEL_THREADS
     extern int msc_shutdown_pri;
-#endif
 
     /* grab the designated "event subchannel" */
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[BRL1_EVENT_SUBCH]);
     if( subch->use != BRL1_SUBCH_FREE ) {
-	SUBCH_UNLOCK( sc );
-	PRINT_WARNING("sysctl event subchannel in use! "
+	SUBCH_UNLOCK( sc, pl );
+	printk(KERN_WARNING  "sysctl event subchannel in use! "
 		 "Not monitoring sysctl events.\n" );
 	return;
     }
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
-    subch->target = BRL1_LOCALUART;
+    subch->target = BRL1_LOCALHUB_UART;
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
 
-#ifdef LINUX_KERNEL_THREADS
     /* set up a thread to listen for events */
     sthread_create( "sysctl event handler", 0, 0, 0, msc_shutdown_pri,
 		    KT_PS, (st_func_t *) sc_event,
 		    (void *)sc, (void *)(uint64_t)BRL1_EVENT_SUBCH, 0, 0 );
-#endif
 
     /* signal the L1 to begin sending events */
     bzero( msg, BRL1_QSIZE );
@@ -2522,276 +3053,8 @@
 	
 err_return:
     /* there was a problem; complain */
-    PRINT_WARNING("failed to set sysctl event-monitoring subchannel.  "
+    printk(KERN_WARNING  "failed to set sysctl event-monitoring subchannel.  "
 	     "Sysctl events will not be monitored.\n" );
 }
 
-
-/*********************************************************************
- * elscuart functions.  These provide a uart-like interface to the
- * bedrock/l1 protocol console channels.  They are similar in form
- * and intent to the elscuart_* functions defined for SN0 in elsc.c.
- *
- */
-
-int _elscuart_flush( l1sc_t *sc );
-
-/* Leave room in queue for CR/LF */
-#define ELSCUART_LINE_MAX       (BRL1_QSIZE - 2)
-
-
-/*
- * _elscuart_putc provides an entry point to the L1 interface driver;
- * writes a single character to the output queue.  Flushes at the
- * end of each line, and translates newlines into CR/LF.
- *
- * The kernel should generally use l1_cons_write instead, since it assumes
- * buffering, translation, prefixing, etc. are done at a higher
- * level.
- *
- */
-int
-_elscuart_putc( l1sc_t *sc, int c )
-{
-    sc_cq_t *q;
-    
-    q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    if( c != '\n' && c != '\r' && cq_used(q) >= ELSCUART_LINE_MAX ) {
-        cq_add( q, '\r' );
-        cq_add( q, '\n' );
-         _elscuart_flush( sc );
-        sc->sol = 1;
-    }
-
-    if( sc->sol && c != '\r' ) {
-        char            prefix[16], *s;
-
-        if( cq_room( q ) < 8 && _elscuart_flush(sc) < 0 )
-        {
-            return -1;
-        }
-	
-	if( sc->verbose )
-	{
-#ifdef  SUPPORT_PRINTING_M_FORMAT
-	    sprintf( prefix,
-		     "%c %d%d%d %M:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#else
-	    sprintf( prefix,
-		     "%c %d%d%d 0x%x:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#endif
-	    
-	    for( s = prefix; *s; s++ )
-		cq_add( q, *s );
-	}	    
-	sc->sol = 0;
-
-    }
-
-    if( cq_room( q ) < 2 && _elscuart_flush(sc) < 0 )
-    {
-        return -1;
-    }
-
-    if( c == '\n' ) {
-        cq_add( q, '\r' );
-        sc->sol = 1;
-    }
-
-    cq_add( q, (u_char) c );
-
-    if( c == '\n' ) {
-        /* flush buffered line */
-        if( _elscuart_flush( sc ) < 0 )
-        {
-            return -1;
-        }
-    }
-
-    if( c== '\r' )
-    {
-        sc->sol = 1;
-    }
-
-    return 0;
-}
-
-
-/*
- * _elscuart_getc reads a character from the input queue.  This
- * routine blocks.
- */
-int
-_elscuart_getc( l1sc_t *sc )
-{
-    int r;
-
-    while( (r = _elscuart_poll( sc )) == 0 );
-
-    if( r < 0 ) {
-	/* some error occurred */
-	return r;
-    }
-
-    return _elscuart_readc( sc );
-}
-
-
-
-/*
- * _elscuart_poll returns 1 if characters are ready for the
- * calling processor, 0 if they are not
- */
-int
-_elscuart_poll( l1sc_t *sc )
-{
-    int result;
-
-    if( sc->cons_listen ) {
-        result = l1_cons_poll( sc );
-        if( result )
-            return result;
-    }
-
-    return sc_poll( sc, L1_ELSCUART_SUBCH(get_myid()) );
-}
-
-
-
-/* _elscuart_readc is to be used only when _elscuart_poll has
- * indicated that a character is waiting.  Pulls a character
- * of this processor's console queue and returns it.
- *
- */
-int
-_elscuart_readc( l1sc_t *sc )
-{
-    int c;
-    sc_cq_t *q;
-    brl1_sch_t *subch;
-
-    if( sc->cons_listen ) {
-	subch = &(sc->subch[ SC_CONS_SYSTEM ]);
-	q = subch->iqp;
-	
-	SUBCH_DATA_LOCK( subch );
-        if( !cq_empty( q ) ) {
-            cq_rem( q, c );
-	    if( cq_empty( q ) ) {
-		atomic_set(&subch->packet_arrived, 0);
-	    }
-	    SUBCH_DATA_UNLOCK( subch );
-            return c;
-        }
-	SUBCH_DATA_UNLOCK( subch );
-    }
-
-    subch = &(sc->subch[ L1_ELSCUART_SUBCH(get_myid()) ]);
-    q = subch->iqp;
-
-    SUBCH_DATA_LOCK( subch );
-    if( cq_empty( q ) ) {
-	SUBCH_DATA_UNLOCK( subch );
-        return -1;
-    }
-
-    cq_rem( q, c );
-    if( cq_empty ( q ) ) {
-	atomic_set(&subch->packet_arrived, 0);
-    }
-    SUBCH_DATA_UNLOCK( subch );
-
-    return c;
-}
-
-
-/*
- * _elscuart_flush flushes queued output to the L1.
- * This routine blocks until the queue is flushed.
- */
-int
-_elscuart_flush( l1sc_t *sc )
-{
-    int r, n;
-    char buf[BRL1_QSIZE];
-    sc_cq_t *q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    while( (n = cq_used(q)) ) {
-
-        /* buffer queue contents */
-        r = BRL1_QSIZE - q->opos;
-
-        if( n > r ) {
-            BCOPY( q->buf + q->opos, buf, r  );
-            BCOPY( q->buf, buf + r, n - r  );
-        } else {
-            BCOPY( q->buf + q->opos, buf, n  );
-        }
-
-        /* attempt to send buffer contents */
-        r = brl1_send( sc, buf, cq_used( q ), 
-		       (BRL1_EVENT | L1_ELSCUART_SUBCH(get_myid())), 1 );
-
-        /* if no error, dequeue the sent characters; otherwise,
-         * return the error
-         */
-        if( r >= SC_SUCCESS ) {
-            q->opos = (q->opos + r) % BRL1_QSIZE;
-        }
-        else {
-            return r;
-        }
-    }
-
-    return 0;
-}
-
-
-
-/* _elscuart_probe returns non-zero if the L1 (and
- * consequently the elscuart) can be accessed
- */
-int
-_elscuart_probe( l1sc_t *sc )
-{
-#ifndef CONFIG_SERIAL_SGI_L1_PROTOCOL
-    return 0;
-#else
-    char ver[BRL1_QSIZE];
-    extern int elsc_version( l1sc_t *, char * );
-
-    if ( IS_RUNNING_ON_SIMULATOR() )
-    	return 0;
-    return( elsc_version(sc, ver) >= 0 );
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
-}
-
-
-
-/* _elscuart_init zeroes out the l1sc_t console
- * queues for this processor's console subchannel.
- */
-void
-_elscuart_init( l1sc_t *sc )
-{
-    brl1_sch_t *subch = &sc->subch[L1_ELSCUART_SUBCH(get_myid())];
-
-    SUBCH_DATA_LOCK(subch);
-
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    cq_init( &sc->oq[MAP_OQ(L1_ELSCUART_SUBCH(get_myid()))] );
-
-    SUBCH_DATA_UNLOCK(subch);
-}
+#endif	/* LINUX_KERNEL_THREADS */
diff -urN linux-2.4.16/arch/ia64/sn/io/l1_command.c lia64-2.4/arch/ia64/sn/io/l1_command.c
--- linux-2.4.16/arch/ia64/sn/io/l1_command.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/l1_command.c	Mon Nov 19 23:22:51 2001
@@ -4,20 +4,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */ 
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
@@ -27,7 +27,6 @@
 #define ELSC_TIMEOUT	1000000		/* ELSC response timeout (usec) */
 #define LOCK_TIMEOUT	5000000		/* Hub lock timeout (usec) */
 
-#define LOCAL_HUB	LOCAL_HUB_ADDR
 #define LD(x)		(*(volatile uint64_t *)(x))
 #define SD(x, v)	(LD(x) = (uint64_t) (v))
 
@@ -75,7 +74,7 @@
 
 void elsc_init(elsc_t *e, nasid_t nasid)
 {
-    sc_init((l1sc_t *)e, nasid, BRL1_LOCALUART);
+    sc_init((l1sc_t *)e, nasid, BRL1_LOCALHUB_UART);
 }
 
 
@@ -1376,85 +1375,4 @@
     sprintf( result, "%d.%d.%d", major, minor, bugfix );
 
     return 0;
-}
-
-
-
-/* elscuart routines 
- *
- * Most of the elscuart functionality is implemented in l1.c.  The following
- * is directly "recycled" from elsc.c.
- */
-
-
-/*
- * _elscuart_puts
- */
-
-int _elscuart_puts(elsc_t *e, char *s)
-{
-    int			c;
-
-    if (s == 0)
-	s = "<NULL>";
-
-    while ((c = LBYTE(s)) != 0) {
-	if (_elscuart_putc(e, c) < 0)
-	    return -1;
-	s++;
-    }
-
-    return 0;
-}
-
-
-/*
- * elscuart wrapper routines
- *
- *   The following routines are similar to their counterparts in l1.c,
- *   except instead of taking an elsc_t pointer directly, they call
- *   a global routine "get_elsc" to obtain the pointer.
- *   This is useful when the elsc is employed for stdio.
- */
-
-int elscuart_probe(void)
-{
-    return _elscuart_probe(get_elsc());
-}
-
-void elscuart_init(void *init_data)
-{
-    _elscuart_init(get_elsc());
-    /* dummy variable included for driver compatability */
-    init_data = init_data;
-}
-
-int elscuart_poll(void)
-{
-    return _elscuart_poll(get_elsc());
-}
-
-int elscuart_readc(void)
-{
-    return _elscuart_readc(get_elsc());
-}
-
-int elscuart_getc(void)
-{
-    return _elscuart_getc(get_elsc());
-}
-
-int elscuart_puts(char *s)
-{
-    return _elscuart_puts(get_elsc(), s);
-}
-
-int elscuart_putc(int c)
-{
-    return _elscuart_putc(get_elsc(), c);
-}
-
-int elscuart_flush(void)
-{
-    return _elscuart_flush(get_elsc());
 }
diff -urN linux-2.4.16/arch/ia64/sn/io/labelcl.c lia64-2.4/arch/ia64/sn/io/labelcl.c
--- linux-2.4.16/arch/ia64/sn/io/labelcl.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/labelcl.c	Mon Nov 19 23:22:51 2001
@@ -1,21 +1,10 @@
 /*  labelcl - SGI's Hwgraph Compatibility Layer.
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Colin Ngam may be reached by email at cngam@sgi.com
-
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
 */
 
 #include <linux/types.h>
@@ -286,7 +275,7 @@
 		if (!strcmp(info_name, old_label_list[i].name)) {
 			/* Not allowed to add duplicate labelled info names. */
 			kfree(new_label_list);
-			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, de);
+			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, (void *)de);
 			return(-1);
 		}
 		new_label_list[i] = old_label_list[i]; /* structure copy */
diff -urN linux-2.4.16/arch/ia64/sn/io/mem_refcnt.c lia64-2.4/arch/ia64/sn/io/mem_refcnt.c
--- linux-2.4.16/arch/ia64/sn/io/mem_refcnt.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/mem_refcnt.c	Wed Dec 31 16:00:00 1969
@@ -1,222 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/hcl_util.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/hubspc.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/hwcntrs.h>
-// From numa_hw.h
-
-#define MIGR_COUNTER_MAX_GET(nodeid) \
-        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
-/*
- * Get the Absolute Theshold
- */
-#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
-        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
-/*
- * Get the current Differential Threshold
- */
-#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
-        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
-
-#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
-
-// #include "migr_control.h"
-
-int
-mem_refcnt_attach(devfs_handle_t hub)
-{
-        devfs_handle_t refcnt_dev;
-        
-        hwgraph_char_device_add(hub,
-                                "refcnt",
-                                "hubspc_", 
-				&refcnt_dev);
-        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
-
-        return (0);
-}
-
-
-/*ARGSUSED*/
-int
-mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
-{
-        cnodeid_t node;
-
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(*devp) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(*devp);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
-                return (ENODEV);
-        }
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
-
-        return (0);
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-        return 0;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-        cnodeid_t node;
-        int errcode;
-        char* buffer;
-        size_t blen;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        /*
-         * XXXX deal with prot's somewhere around here....
-         */
-
-        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
-        blen = NODEPDA(node)->migr_refcnt_cbsize;
-
-        /*
-         * Force offset to be a multiple of sizeof(refcnt_t)
-         * We round up.
-         */
-
-        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
-
-        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
-                return (EPERM);
-        }
-
-        errcode = v_mapphys(vt,
-                            buffer + off,
-                            len);
-
-        return errcode;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-        return 0;
-}
-
-/* ARGSUSED */
-int
-mem_refcnt_ioctl(devfs_handle_t dev,
-                 int cmd,
-                 void *arg,
-                 int mode,
-                 cred_t *cred_p,
-                 int *rvalp)
-{
-        cnodeid_t node;
-        int errcode;
-	extern int numnodes;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        errcode = 0;
-        
-        switch (cmd) {
-        case RCB_INFO_GET:
-        {
-                rcb_info_t rcb;
-                
-                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
-                
-                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
-                rcb.rcb_sw_counters_per_set = numnodes;
-                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
-
-                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
-                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
-                rcb.rcb_base_page_size = NBPP;
-                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
-                
-                rcb.rcb_cnodeid = node;
-                rcb.rcb_granularity = MD_PAGE_SIZE;
-#ifdef LATER
-                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
-                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
-#endif
-                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
-                rcb.rcb_num_slots = node_getnumslots(node);
-
-                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
-                        errcode = EFAULT;
-                }
-
-                break;
-        }
-        case RCB_SLOT_GET:
-        {
-                rcb_slot_t slot[MAX_MEM_SLOTS];
-                int s;
-                int nslots;
-
-                nslots = node_getnumslots(node);
-                ASSERT(nslots <= MAX_MEM_SLOTS);
-                for (s = 0; s < nslots; s++) {
-                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
-#ifdef LATER
-                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
-#else
-                        slot[s].size  = (uint64_t)1;
-#endif
-                }
-                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
-                        errcode = EFAULT;
-                }
-                
-                *rvalp = nslots;
-                break;
-        }
-                
-        default:
-                errcode = EINVAL;
-                break;
-
-        }
-        
-        return errcode;
-}
diff -urN linux-2.4.16/arch/ia64/sn/io/ml_SN_init.c lia64-2.4/arch/ia64/sn/io/ml_SN_init.c
--- linux-2.4.16/arch/ia64/sn/io/ml_SN_init.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/ml_SN_init.c	Mon Nov 19 23:22:51 2001
@@ -4,37 +4,30 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_cpuid.h>
-#include <asm/sn/synergy.h>
-
-
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/sn1/sn1.h>
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
+#include <asm/sn/snconfig.h>
 
 extern int numcpus;
 extern char arg_maxnodes[];
 extern cpuid_t master_procid;
-extern void * kmem_alloc_node(register size_t, register int , cnodeid_t);
+#if defined(CONFIG_IA64_SGI_SN1)
 extern synergy_da_t    *Synergy_da_indr[];
+#endif
 
 extern int hasmetarouter;
 
@@ -45,18 +38,8 @@
 
 extern xwidgetnum_t hub_widget_id(nasid_t);
 
-static int	fine_mode = 0;
-
-static cnodemask_t	hub_init_mask;	/* Mask of cpu in a node doing init */
-static volatile cnodemask_t hub_init_done_mask;
-					/* Node mask where we wait for
-					 * per hub initialization
-					 */
-spinlock_t		hub_mask_lock;  /* Lock for hub_init_mask above. */
-
 extern int valid_icache_reasons;	/* Reasons to flush the icache */
 extern int valid_dcache_reasons;	/* Reasons to flush the dcache */
-extern int numnodes;
 extern u_char miniroot;
 extern volatile int	need_utlbmiss_patch;
 extern void iograph_early_init(void);
@@ -83,20 +66,6 @@
 		 */ 
 		master_nasid = get_nasid();
 		set_master_bridge_base();
-		FIXME("mlreset: Enable when we support ioc3 ..");
-#ifdef	LATER
-		if (get_console_nasid() == master_nasid) 
-			/* Set up the IOC3 */
-			ioc3_mlreset((ioc3_cfg_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->config_base,
-				     (ioc3_mem_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
-
-		/*
-		 * Initialize Master nvram base.
-		 */
-		nvram_baseinit();
-
-		fine_mode = is_fine_dirmode();
-#endif /* LATER */
 
 		/* We're the master processor */
 		master_procid = smp_processor_id();
@@ -108,75 +77,12 @@
 		 */
 		ASSERT_ALWAYS(master_nasid == get_nasid());
 
-#ifdef	LATER
-
-	/*
-	 * Activate when calias is implemented.
-	 */
-		/* Set all nodes' calias sizes to 8k */
-		for (i = 0; i < maxnodes; i++) {
-			nasid_t nasid;
-			int	sn;
-
-			nasid = COMPACT_TO_NASID_NODEID(i);
-
-			/*
-			 * Always have node 0 in the region mask, otherwise CALIAS accesses
-			 * get exceptions since the hub thinks it is a node 0 address.
-			 */
-			for (sn=0; sn<NUM_SUBNODES; sn++) {
-				REMOTE_HUB_PI_S(nasid, sn, PI_REGION_PRESENT, (region_mask | 1));
-				REMOTE_HUB_PI_S(nasid, sn, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K);
-			}
-
-			/*
-			 * Set up all hubs to havew a big window pointing at
-			 * widget 0.
-			 * Memory mode, widget 0, offset 0
-			 */
-			REMOTE_HUB_S(nasid, IIO_ITTE(SWIN0_BIGWIN),
-				((HUB_PIO_MAP_TO_MEM << IIO_ITTE_IOSP_SHIFT) |
-				(0 << IIO_ITTE_WIDGET_SHIFT)));
-		}
-#endif /* LATER */
-
-		/* Set up the hub initialization mask and init the lock */
-		CNODEMASK_CLRALL(hub_init_mask);
-		CNODEMASK_CLRALL(hub_init_done_mask);
-
-		spin_lock_init(&hub_mask_lock);
-
 		/* early initialization of iograph */
 		iograph_early_init();
 
 		/* Initialize Hub Pseudodriver Management */
 		hubdev_init();
 
-#ifdef	LATER
-		/*
-		 * Our IO system doesn't require cache writebacks.  Set some
-		 * variables appropriately.
-		 */
-		cachewrback = 0;
-		valid_icache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-		valid_dcache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-
-		/*
-		 * make sure we are running with the right rev of chips
-		 */
-		verify_snchip_rev();
-
-		/*
-                 * Since we've wiped out memory at this point, we
-                 * need to reset the ARCS vector table so that it
-                 * points to appropriate functions in the kernel
-                 * itself.  In this way, we can maintain the ARCS
-                 * vector table conventions without having to actually
-                 * keep redundant PROM code in memory.
-                 */
-		he_arcs_set_vectors();
-#endif /* LATER */
-
 	} else { /* slave != 0 */
 		/*
 		 * This code is performed ONLY by slave processors.
@@ -194,33 +100,14 @@
 {
 	hubinfo_t hubinfo;
 	int	  sn;
-	cnodeid_t i;
-	ushort *numcpus_p;
 
 	extern void router_map_init(nodepda_t *);
 	extern void router_queue_init(nodepda_t *,cnodeid_t);
 	extern void intr_init_vecblk(nodepda_t *, cnodeid_t, int);
 
-#if defined(DEBUG)
-	extern spinlock_t	intr_dev_targ_map_lock;
-	extern uint64_t 	intr_dev_targ_map_size;
-
-	/* Initialize the lock to access the device - target cpu mapping
-	 * table. This table is explicitly for debugging purposes only and
-	 * to aid the "intrmap" idbg command
-	 */
-	if (node == 0) {
-		/* Make sure we do this only once .
-		 * There is always a cnode 0 present.
-		 */
-		intr_dev_targ_map_size = 0;
-		spin_lock_init(&intr_dev_targ_map_lock);
-	}
-#endif	/* DEBUG */
 	/* Allocate per-node platform-dependent data */
-	hubinfo = (hubinfo_t)kmem_alloc_node(sizeof(struct hubinfo_s), GFP_ATOMIC, node);
+	hubinfo = (hubinfo_t)alloc_bootmem_node(NODE_DATA(node), sizeof(struct hubinfo_s));
 
-	ASSERT_ALWAYS(hubinfo);
 	npda->pdinfo = (void *)hubinfo;
 	hubinfo->h_nodepda = npda;
 	hubinfo->h_cnodeid = node;
@@ -230,92 +117,37 @@
 
 	hubinfo->h_widgetid = hub_widget_id(hubinfo->h_nasid);
 	npda->xbow_peer = INVALID_NASID;
-	/* Initialize the linked list of
+
+	/* 
+	 * Initialize the linked list of
 	 * router info pointers to the dependent routers
 	 */
 	npda->npda_rip_first = NULL;
-	/* npda_rip_last always points to the place
+
+	/*
+	 * npda_rip_last always points to the place
 	 * where the next element is to be inserted
 	 * into the list 
 	 */
 	npda->npda_rip_last = &npda->npda_rip_first;
-	npda->dependent_routers = 0;
 	npda->module_id = INVALID_MODULE;
 
+#ifdef CONFIG_IA64_SGI_SN1
 	/*
-	 * Initialize the subnodePDA.
-	 */
+	* Initialize the interrupts.
+	* On sn2, this is done at pci init time,
+	* because sn2 needs the cpus checked in
+	* when it initializes interrupts.  This is
+	* so we don't see all the nodes as headless.
+	*/
 	for (sn=0; sn<NUM_SUBNODES; sn++) {
-		SNPDA(npda,sn)->prof_count = 0;
-		SNPDA(npda,sn)->next_prof_timeout = 0;
 		intr_init_vecblk(npda, node, sn);
 	}
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-	npda->vector_unit_busy = 0;
-
-	spin_lock_init(&npda->vector_lock);
 	mutex_init_locked(&npda->xbow_sema); /* init it locked? */
-	spin_lock_init(&npda->fprom_lock);
 
-	spin_lock_init(&npda->node_utlbswitchlock);
-	npda->ni_error_print = 0;
 #ifdef	LATER
-	if (need_utlbmiss_patch) {
-		npda->node_need_utlbmiss_patch = 1;
-		npda->node_utlbmiss_patched = 1;
-	}
-#endif
-
-	/*
-	 * Clear out the nasid mask.
-	 */
-	for (i = 0; i < NASID_MASK_BYTES; i++)
-		npda->nasid_mask[i] = 0;
-
-	for (i = 0; i < numnodes; i++) {
-		nasid_t nasid = COMPACT_TO_NASID_NODEID(i);
-
-		/* Set my mask bit */
-		npda->nasid_mask[nasid / 8] |= (1 << nasid % 8);
-	}
-
-#ifdef	LATER
-	npda->node_first_cpu = get_cnode_cpu(node);
-#endif
-
-	if (npda->node_first_cpu != CPU_NONE) {
-		/*
-		 * Count number of cpus only if first CPU is valid.
-		 */
-		numcpus_p = &npda->node_num_cpus;
-		*numcpus_p = 0;
-		for (i = npda->node_first_cpu; i < MAXCPUS; i++) {
-			if (CPUID_TO_COMPACT_NODEID(i) != node)
-			    break;
-			else
-			    (*numcpus_p)++;
-		}
-	} else {
-		npda->node_num_cpus = 0; 
-	}
-
-	/* Allocate memory for the dump stack on each node 
-	 * This is useful during nmi handling since we
-	 * may not be guaranteed shared memory at that time
-	 * which precludes depending on a global dump stack
-	 */
-#ifdef	LATER
-	npda->dump_stack = (uint64_t *)kmem_zalloc_node(DUMP_STACK_SIZE,VM_NOSLEEP,
-							  node);
-	ASSERT_ALWAYS(npda->dump_stack);
-	ASSERT(npda->dump_stack);
-#endif
-	/* Initialize the counter which prevents
-	 * both the cpus on a node to proceed with nmi
-	 * handling.
-	 */
-#ifdef	LATER
-	npda->dump_count = 0;
 
 	/* Setup the (module,slot) --> nic mapping for all the routers
 	 * in the system. This is useful during error handling when
@@ -325,17 +157,9 @@
 
 	/* Allocate memory for the per-node router traversal queue */
 	router_queue_init(npda,node);
-	npda->sbe_info = kmem_zalloc_node_hint(sizeof (sbe_info_t), 0, node);
+	npda->sbe_info = alloc_bootmem_node(NODE_DATA(node), sizeof (sbe_info_t));
 	ASSERT(npda->sbe_info);
 
-#ifdef CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-	/*
-	 * Initialize bte info pointers to NULL
-	 */
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		npda->node_bte_info[i] = (bteinfo_t *)NULL;
-	}
-#endif
 #endif /* LATER */
 }
 
@@ -345,260 +169,48 @@
  * Must be done _after_ init_platform_nodepda().
  * If we need a lock here, something else is wrong!
  */
-// void init_platform_pda(pda_t *ppda, cpuid_t cpu)
 void init_platform_pda(cpuid_t cpu)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	hub_intmasks_t *intmasks;
-#ifdef	LATER
-	cpuinfo_t cpuinfo;
-#endif
-	int i;
+	int i, subnode;
 	cnodeid_t	cnode;
 	synergy_da_t	*sda;
 	int	which_synergy;
 
-#ifdef	LATER
-	/* Allocate per-cpu platform-dependent data */
-	cpuinfo = (cpuinfo_t)kmem_alloc_node(sizeof(struct cpuinfo_s), GFP_ATOMIC, cputocnode(cpu));
-	ASSERT_ALWAYS(cpuinfo);
-	ppda->pdinfo = (void *)cpuinfo;
-	cpuinfo->ci_cpupda = ppda;
-	cpuinfo->ci_cpuid = cpu;
-#endif
 
 	cnode = cpuid_to_cnodeid(cpu);
 	which_synergy = cpuid_to_synergy(cpu);
+
 	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	// intmasks = &ppda->p_intmasks;
 	intmasks = &sda->s_intmasks;
 
-#ifdef	LATER
-	ASSERT_ALWAYS(&ppda->p_nodepda);
-#endif
-
 	/* Clear INT_PEND0 masks. */
 	for (i = 0; i < N_INTPEND0_MASKS; i++)
 		intmasks->intpend0_masks[i] = 0;
 
 	/* Set up pointer to the vector block in the nodepda. */
 	/* (Cant use SUBNODEPDA - not working yet) */
-	intmasks->dispatch0 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
-	intmasks->dispatch1 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	subnode = cpuid_to_subnode(cpu);
+	intmasks->dispatch0 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
+	intmasks->dispatch1 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	if (intmasks->dispatch0 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch0 ||
+	   intmasks->dispatch1 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch1)
+	   	panic("xxx");
+	intmasks->dispatch0 = &SUBNODEPDA(cnode, subnode)->intr_dispatch0;
+	intmasks->dispatch1 = &SUBNODEPDA(cnode, subnode)->intr_dispatch1;
 
 	/* Clear INT_PEND1 masks. */
 	for (i = 0; i < N_INTPEND1_MASKS; i++)
 		intmasks->intpend1_masks[i] = 0;
-
-
-#ifdef	LATER
-	/* Don't read the routers unless we're the master. */
-	ppda->p_routertick = 0;
-#endif
-
+#endif	/* CONFIG_IA64_SGI_SN1 */
 }
 
-#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && !defined(BRINGUP)	/* protect low mem for IP35/7 */
+#if (defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && !defined(BRINGUP)	/* protect low mem */
 #error "need protect_hub_calias, protect_nmi_handler_data"
 #endif
 
-#ifdef	LATER
-/*
- * For now, just protect the first page (exception handlers). We
- * may want to protect more stuff later.
- */
-void
-protect_hub_calias(nasid_t nasid)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + 0; /* page 0 on node nasid */
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-
-/*
- * Protect the page of low memory used to communicate with the NMI handler.
- */
 void
-protect_nmi_handler_data(nasid_t nasid, int slice)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + NMI_OFFSET(nasid, slice);
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-#endif /* LATER */
-
-
-#ifdef LATER
-/*
- * Protect areas of memory that we access uncached by marking them as
- * poisoned so the T5 can't read them speculatively and erroneously
- * mark them dirty in its cache only to write them back with old data
- * later.
- */
-static void
-protect_low_memory(nasid_t nasid)
-{
-	/* Protect low memory directory */
-	poison_state_alter_range(KLDIR_ADDR(nasid), KLDIR_SIZE, 1);
-
-	/* Protect klconfig area */
-	poison_state_alter_range(KLCONFIG_ADDR(nasid), KLCONFIG_SIZE(nasid), 1);
-
-	/* Protect the PI error spool area. */
-	poison_state_alter_range(PI_ERROR_ADDR(nasid), PI_ERROR_SIZE(nasid), 1);
-
-	/* Protect CPU A's cache error eframe area. */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME),
-				CACHE_ERR_AREA_SIZE, 1);
-
-	/* Protect CPU B's area */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME)
-				^ UALIAS_FLIP_BIT,
-				CACHE_ERR_AREA_SIZE, 1);
-#error "SN1 not handled correctly"
-}
-#endif	/* LATER */
-
-/*
- * per_hub_init
- *
- * 	This code is executed once for each Hub chip.
- */
-void
-per_hub_init(cnodeid_t cnode)
-{
-	uint64_t	done;
-	nasid_t		nasid;
-	nodepda_t	*npdap;
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)	/* SN1 specific */
-	ii_icmr_u_t	ii_icmr;
-	ii_ibcr_u_t	ii_ibcr;
-#endif
-#ifdef	LATER
-	int i;
-#endif
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	ASSERT(nasid != INVALID_NASID);
-	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
-
-	/* Grab the hub_mask lock. */
-	spin_lock(&hub_mask_lock);
-
-	/* Test our bit. */
-	if (!(done = CNODEMASK_TSTB(hub_init_mask, cnode))) {
-
-		/* Turn our bit on in the mask. */
-		CNODEMASK_SETB(hub_init_mask, cnode);
-	}
-
-#if defined(SN0_HWDEBUG)
-	hub_config_setup();
-#endif
-	/* Release the hub_mask lock. */
-	spin_unlock(&hub_mask_lock);
-
-	/*
-	 * Do the actual initialization if it hasn't been done yet.
-	 * We don't need to hold a lock for this work.
-	 */
-	if (!done) {
-		npdap = NODEPDA(cnode);
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-		/* initialize per-node synergy perf instrumentation */
-		npdap->synergy_perf_enabled = 0; /* off by default */
-		npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
-		npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
-		npdap->synergy_inactive_intervals = 0;
-		npdap->synergy_active_intervals = 0;
-		npdap->synergy_perf_data = NULL;
-		npdap->synergy_perf_first = NULL;
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
-		npdap->hub_chip_rev = get_hub_chiprev(nasid);
-
-#ifdef	LATER
-		for (i = 0; i < CPUS_PER_NODE; i++) {
-			cpu = cnode_slice_to_cpuid(cnode, i);
-			if (!cpu_enabled(cpu))
-			    SET_CPU_LEDS(nasid, i, 0xf);
-		}
-#endif /* LATER */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) /* SN1 specific */
-
-		/*
-		 * Set the total number of CRBs that can be used.
-		 */
-		ii_icmr.ii_icmr_regval= 0x0;
-		ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
-		REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
-
-		/*
-		 * Set the number of CRBs that both of the BTEs combined
-		 * can use minus 1.
-		 */
-		ii_ibcr.ii_ibcr_regval= 0x0;
-		ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
-		REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
-
-		/*
-		 * Set CRB timeout to be 10ms.
-		 */
-		REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
-		REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
-
-#endif /* SN0_HWDEBUG */
-
-
-
-		/* Reserve all of the hardwired interrupt levels. */
-		intr_reserve_hardwired(cnode);
-
-		/* Initialize error interrupts for this hub. */
-		hub_error_init(cnode);
-
-#ifdef LATER
-		/* Set up correctable memory/directory ECC error interrupt. */
-		install_eccintr(cnode);
-
-		/* Protect our exception vectors from accidental corruption. */
-		protect_hub_calias(nasid);
-
-		/* Enable RT clock interrupts */
-		hub_rtc_init(cnode);
-		hub_migrintr_init(cnode); /* Enable migration interrupt */
-#endif	/* LATER */
-
-		spin_lock(&hub_mask_lock);
-		CNODEMASK_SETB(hub_init_done_mask, cnode);
-		spin_unlock(&hub_mask_lock);
-
-	} else {
-		/*
-		 * Wait for the other CPU to complete the initialization.
-		 */
-		while (CNODEMASK_TSTB(hub_init_done_mask, cnode) == 0) {
-			/*
-			 * On SNIA64 we should never get here ..
-			 */
-			printk("WARNING: per_hub_init: Should NEVER get here!\n");
-			/* LOOP */
-			;
-		}
-	}
-}
-
-extern void
 update_node_information(cnodeid_t cnodeid)
 {
 	nodepda_t *npda = NODEPDA(cnodeid);
@@ -623,22 +235,3 @@
 		npda_rip = npda_rip->router_next;
 	}
 }
-
-hubreg_t
-get_region(cnodeid_t cnode)
-{
-	if (fine_mode)
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_FINEREG_SHFT;
-	else
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_COARSEREG_SHFT;
-}
-
-hubreg_t
-nasid_to_region(nasid_t nasid)
-{
-	if (fine_mode)
-		return nasid >> NASID_TO_FINEREG_SHFT;
-	else
-		return nasid >> NASID_TO_COARSEREG_SHFT;
-}
-
diff -urN linux-2.4.16/arch/ia64/sn/io/ml_SN_intr.c lia64-2.4/arch/ia64/sn/io/ml_SN_intr.c
--- linux-2.4.16/arch/ia64/sn/io/ml_SN_intr.c	Tue Jul 31 10:30:09 2001
+++ lia64-2.4/arch/ia64/sn/io/ml_SN_intr.c	Wed Dec 31 16:00:00 1969
@@ -1,1728 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-/*
- * intr.c-
- *	This file contains all of the routines necessary to set up and
- *	handle interrupts on an IP27 board.
- */
-
-#ident  "$Revision: 1.167 $"
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-#include <sys/debug.h>
-#include <sys/idbg.h>
-#include <sys/inst.h>
-void do_splx_log(int, int);
-void spldebug_log_event(int);
-#endif
-
-// FIXME - BRINGUP
-#ifdef CONFIG_SMP
-extern unsigned long cpu_online_map;
-#endif
-#define cpu_allows_intr(cpu)	(1)
-// If I understand what's going on with this, 32 should work.
-// physmem_maxradius seems to be the maximum number of router
-// hops to get from one end of the system to the other.  With
-// a maximally configured machine, with the dumbest possible
-// topology, we would make 32 router hops.  For what we're using
-// it for, the dumbest possible should suffice.
-#define physmem_maxradius()	32
-
-#define SUBNODE_ANY -1
-
-extern int	nmied;
-extern int	hub_intr_wakeup_cnt;
-extern synergy_da_t	*Synergy_da_indr[];
-extern cpuid_t         master_procid;
-
-extern cnodeid_t master_node_get(devfs_handle_t vhdl);
-
-extern snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-
-#define INTR_LOCK(vecblk) \
-     (s = mutex_spinlock(&(vecblk)->vector_lock))
-#define INTR_UNLOCK(vecblk) \
-      mutex_spinunlock(&(vecblk)->vector_lock, s)
-
-/*
- * REACT/Pro
- */
-
-
-
-/* 
- * Find first bit set 
- * Used outside this file also 
- */
-int ms1bit(unsigned long x)
-{
-    int			b;
-
-    if (x >> 32)	b  = 32, x >>= 32;
-    else		b  =  0;
-    if (x >> 16)	b += 16, x >>= 16;
-    if (x >>  8)	b +=  8, x >>=  8;
-    if (x >>  4)	b +=  4, x >>=  4;
-    if (x >>  2)	b +=  2, x >>=  2;
-
-    return b + (int) (x >> 1);
-}
-
-/* ARGSUSED */
-void
-intr_stray(void *lvl)
-{
-    PRINT_WARNING("Stray Interrupt - level %ld to cpu %d", (long)lvl, cpuid());
-}
-
-#if defined(DEBUG)
-
-/* Infrastructure  to gather the device - target cpu mapping info */
-#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
-				 * the exact maximum # devices possible.
-				 */
-#define MAX_NAME	100	
-typedef struct {
-	dev_t		dev;	/* device */
-	cpuid_t		cpuid;	/* target cpu */
-	cnodeid_t	cnodeid;/* node on which the target cpu is present */
-	int		bit;	/* intr bit reserved */
-	char		intr_name[MAX_NAME]; /* name of the interrupt */
-} intr_dev_targ_map_t;
-
-intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
-uint64_t		intr_dev_targ_map_size;
-spinlock_t		intr_dev_targ_map_lock;
-
-/* Print out the device - target cpu mapping.
- * This routine is used only in the idbg command
- * "intrmap" 
- */
-void
-intr_dev_targ_map_print(cnodeid_t cnodeid)
-{
-	int  i,j,size = 0;
-	int  print_flag = 0,verbose = 0;	
-	char node_name[10];
-	
-	if (cnodeid != CNODEID_NONE) {
-		nodepda_t 	*npda;
-
-		npda = NODEPDA(cnodeid);
-		for (j=0; j<NUM_SUBNODES; j++) {
-			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
-			qprintf("\n INT_PEND1: ");
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
-		}
-		verbose = 1;
-	}
-	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
-		(verbose ? "All" : "Non-hardwired"),
-		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
-		
-	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
-	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
-
-		print_flag = 0;
-		if (verbose) {
-			if (cnodeid != CNODEID_NONE) {
-				if (cnodeid == intr_dev_targ_map[i].cnodeid)
-					print_flag = 1;
-			} else {
-				print_flag = 1;
-			}
-		} else {
-			if (intr_dev_targ_map[i].dev != 0) {
-				if (cnodeid != CNODEID_NONE) {
-					if (cnodeid == 
-					    intr_dev_targ_map[i].cnodeid)
-						print_flag = 1;
-				} else {
-					print_flag = 1;
-				}
-			}
-		}
-		if (print_flag) {
-			size++;
-			qprintf("%d\t%d\t%d\t%d\t%s\n",
-				intr_dev_targ_map[i].dev,
-				intr_dev_targ_map[i].cpuid,
-				intr_dev_targ_map[i].cnodeid,
-				intr_dev_targ_map[i].bit,
-				intr_dev_targ_map[i].intr_name);
-		}
-
-	}
-	qprintf("\nTotal : %d\n",size);
-}
-#endif /* DEBUG */
-
-/*
- * The spinlocks have already been initialized.  Now initialize the interrupt
- * vectors.  One processor on each hub does the work.
- */
-void
-intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
-{
-    int			i, ip=0;
-    intr_vecblk_t	*vecblk;
-    subnode_pda_t	*snpda;
-
-
-    snpda = SNPDA(npda,sn);
-    do {
-	if (ip == 0) {
-	    vecblk = &snpda->intr_dispatch0;
-	} else {
-	    vecblk = &snpda->intr_dispatch1;
-	}
-
-	/* Initialize this vector. */
-	for (i = 0; i < N_INTPEND_BITS; i++) {
-		vecblk->vectors[i].iv_func = intr_stray;
-		vecblk->vectors[i].iv_prefunc = NULL;
-		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
-
-		vecblk->info[i].ii_owner_dev = 0;
-		strcpy(vecblk->info[i].ii_name, "Unused");
-		vecblk->info[i].ii_flags = 0;	/* No flags */
-		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
-
-	    }
-
-	mutex_spinlock_init(&vecblk->vector_lock);
-
-	vecblk->vector_count = 0;    
-	for (i = 0; i < CPUS_PER_SUBNODE; i++)
-		vecblk->cpu_count[i] = 0;
-
-	vecblk->vector_state = VECTOR_UNINITED;
-
-    } while (++ip < 2);
-
-}
-
-
-/*
- * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
- *					devfs_handle_t owner_dev, char *name)
- *	Internal work routine to reserve or unreserve an interrupt level.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to reserve.  -1 means any level
- *		resflags should include II_ERRORINT if this is an
- *			error interrupt, II_THREADED if the interrupt handler
- *			will be threaded, or 0 otherwise.
- *		reserve should be set to II_RESERVE or II_UNRESERVE
- *			to get or clear a reservation.
- *		owner_dev is the device that "owns" this interrupt, if supplied
- *		name is a human-readable name for this interrupt, if supplied
- *	intr_reserve_level returns the bit reserved or -1 to indicate an error
- */
-static int
-do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
-					devfs_handle_t owner_dev, char *name)
-{
-    intr_vecblk_t	*vecblk;
-    hub_intmasks_t 	*hub_intmasks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-    synergy_da_t	*sda;
-    int		which_synergy;
-    cnodeid_t	cnode;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    cnode = cpuid_to_cnodeid(cpu);
-    which_synergy = cpuid_to_synergy(cpu);
-    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-    hub_intmasks = &sda->s_intmasks;
-    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-    // if (pdaindr[cpu].pda == NULL) return -1;
-    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
-	vecblk = hub_intmasks->dispatch0;
-	ip = 0;
-    } else {
-	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
-	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
-	vecblk = hub_intmasks->dispatch1;
-	ip = 1;
-    }
-
-    INTR_LOCK(vecblk);
-
-    if (bit <= -1) {
-	bit = 0;
-	ASSERT(reserve == II_RESERVE);
-	/* Choose any available level */
-	for (; bit < N_INTPEND_BITS; bit++) {
-	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
-		rv = bit;
-		break;
-	    }
-	}
-
-	/* Return -1 if all interrupt levels int this register are taken. */
-	if (bit == N_INTPEND_BITS)
-	    rv = -1;
-
-    } else {
-	/* Reserve a particular level if it's available. */
-	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
-	    /* Can't (un)reserve a level that's already (un)reserved. */
-	    rv = -1;
-	} else {
-	    rv = bit;
-	}
-    }
-
-    /* Reserve the level and bump the count. */
-    if (rv != -1) {
-	if (reserve) {
-	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
-	    int namelen;
-	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
-	    vecblk->info[bit].ii_owner_dev = owner_dev;
-	    /* Copy in the name. */
-	    namelen = name ? strlen(name) : 0;
-	    strncpy(vecblk->info[bit].ii_name, name, MIN(namelen, maxlen)); 
-	    vecblk->info[bit].ii_name[maxlen] = '\0';
-	    vecblk->vector_count++;
-	} else {
-	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
-	    vecblk->info[bit].ii_owner_dev = 0;
-	    /* Clear the name. */
-	    vecblk->info[bit].ii_name[0] = '\0';
-	    vecblk->vector_count--;
-	}
-    }
-
-    INTR_UNLOCK(vecblk);
-
-#if defined(DEBUG)
-    if (rv >= 0) {
-	    int namelen = name ? strlen(name) : 0;
-	    /* Gather this device - target cpu mapping information
-	     * in a table which can be used later by the idbg "intrmap"
-	     * command
-	     */
-	    s = mutex_spinlock(&intr_dev_targ_map_lock);
-	    if (intr_dev_targ_map_size < MAX_DEVICES) {
-		    intr_dev_targ_map_t	*p;
-
-		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
-		    p->dev  	= owner_dev;
-		    p->cpuid 	= cpu; 
-		    p->cnodeid 	= cputocnode(cpu); 
-		    p->bit 	= ip * N_INTPEND_BITS + rv;
-		    strncpy(p->intr_name,
-			    name,
-			    MIN(MAX_NAME,namelen));
-		    intr_dev_targ_map_size++;
-	    }
-	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
-    }
-#endif /* DEBUG */
-
-    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Reserve an interrupt level.
- */
-int
-intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
-{
-	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Unreserve an interrupt level.
- */
-void
-intr_unreserve_level(cpuid_t cpu, int bit)
-{
-	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
-}
-
-/*
- * Get values that vary depending on which CPU and bit we're operating on
- */
-static hub_intmasks_t *
-intr_get_ptrs(cpuid_t cpu, int bit,
-	      int *new_bit,		/* Bit relative to the register */
-	      hubreg_t **intpend_masks, /* Masks for this register */
-	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
-	      int *ip)			/* Which intpend register */
-{
-	hub_intmasks_t *hub_intmasks;
-	synergy_da_t	*sda;
-	int		which_synergy;
-	cnodeid_t	cnode;
-
-	ASSERT(bit < N_INTPEND_BITS * 2);
-
-	cnode = cpuid_to_cnodeid(cpu);
-	which_synergy = cpuid_to_synergy(cpu);
-	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	hub_intmasks = &sda->s_intmasks;
-
-	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-	if (bit < N_INTPEND_BITS) {
-		*intpend_masks = hub_intmasks->intpend0_masks;
-		*vecblk = hub_intmasks->dispatch0;
-		*ip = 0;
-		*new_bit = bit;
-	} else {
-		*intpend_masks = hub_intmasks->intpend1_masks;
-		*vecblk = hub_intmasks->dispatch1;
-		*ip = 1;
-		*new_bit = bit - N_INTPEND_BITS;
-	}
-
-	return hub_intmasks;
-}
-
-
-/*
- * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
- *		intr_func_t intr_func, void *intr_arg);
- *	This is the lowest-level interface to the interrupt code.  It shouldn't
- *	be called from outside the ml/SN directory.
- *	intr_connect_level hooks up an interrupt to a particular bit in
- *	the INT_PEND0/1 masks.  Returns 0 on success.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to connect to
- *		intr_swlevel tells which software level to use
- *		intr_func is the interrupt handler
- *		intr_arg is an arbitrary argument interpreted by the handler
- *		intr_prefunc is a prologue function, to be called
- *			with interrupts disabled, to disable
- *			the interrupt at source.  It is called
- *			with the same argument.  Should be NULL for
- *			typical interrupts, which can be masked
- *			by the infrastructure at the level bit.
- *	intr_connect_level returns 0 on success or nonzero on an error
- */
-/* ARGSUSED */
-int
-intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
-		intr_func_t intr_func, void *intr_arg,
-		intr_func_t intr_prefunc)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    int rv = 0;
-    int ip;
-    unsigned long s;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
-	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
-	/* Can't assign to a level that's in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = intr_func;
-	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
-	vecblk->vectors[bit].iv_arg = intr_arg;
-	vecblk->info[bit].ii_flags |= II_INUSE;
-    }
-
-    /* Now stuff the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu));
-	nasid_t nasid = cpuid_to_nasid(cpu);
-	int	subnode = cpuid_to_subnode(cpu);
-
-	/* Make sure it's not already pending when we connect it. */
-	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
-
-	intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]++;
-#if SN1
-	/*
-	 * On SN1, there are 8 interrupt mask registers per node:
-	 * 	PI_0 MASK_0 A
-	 * 	PI_0 MASK_1 A
-	 * 	PI_0 MASK_0 B
-	 * 	PI_0 MASK_1 B
-	 * 	PI_1 MASK_0 A
-	 * 	PI_1 MASK_1 A
-	 * 	PI_1 MASK_0 B
-	 * 	PI_1 MASK_1 B
-	 */
-#endif
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
-		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
-			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-
-/*
- * intr_disconnect_level(cpuid_t cpu, int bit)
- *
- *	This is the lowest-level interface to the interrupt code.  It should
- *	not be called from outside the ml/SN directory.
- *	intr_disconnect_level removes a particular bit from an interrupt in
- * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
- */
-int
-intr_disconnect_level(cpuid_t cpu, int bit)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
-	((II_RESERVE | II_INUSE))) {
-	/* Can't remove a level that's not in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_arg = 0;
-	vecblk->info[bit].ii_flags &= ~II_INUSE;
-#ifdef BASE_ITHRTEAD
-	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
-#endif
-    }
-
-    /* Now clear the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-
-	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]--;
-	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-				   cpuid_to_subnode(cpu),
-				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
-	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
-					(PI_INT_MASK_OFFSET * lslice));
-	*mask_reg = intpend_masks[0];
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-/*
- * Actually block or unblock an interrupt
- */
-void
-do_intr_block_bit(cpuid_t cpu, int bit, int block)
-{
-	intr_vecblk_t *vecblk;
-	int ip;
-	unsigned long s;
-	hubreg_t *intpend_masks;
-	volatile hubreg_t mask_value;
-	volatile hubreg_t *mask_reg;
-
-	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
-
-	INTR_LOCK(vecblk);
-
-	if (block)
-		/* Block */
-		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	else
-		/* Unblock */
-		intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-
-	/*
-	 * Wait for it to take effect.  (One read should suffice.)
-	 * This is only necessary when blocking an interrupt
-	 */
-	if (block)
-		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
-			;
-
-	INTR_UNLOCK(vecblk);
-}
-
-
-/*
- * Block a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_block_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 1);
-}
-
-
-/*
- * Unblock a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_unblock_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 0);
-}
-
-
-/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
-#define cpu_on_subnode(cpuid, which_subnode) \
-	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
-
-
-/*
- * Choose one of the CPUs on a specified node or subnode to receive
- * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
- *
- * Among all acceptable CPUs, the CPU that has the fewest total number
- * of interrupts targetted towards it is chosen.  Note that we never
- * consider how frequent each of these interrupts might occur, so a rare
- * hardware error interrupt is weighted equally with a disk interrupt.
- */
-static cpuid_t
-do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
-{
-	cpuid_t 	cpu, best_cpu = CPU_NONE;
-	int		slice, min_count=1000;
-
-	min_count = 1000;
-	for (slice=0; slice < CPUS_PER_NODE; slice++) {
-		intr_vecblk_t 	*vecblk0, *vecblk1;
-		int total_intrs_to_slice;
-		subnode_pda_t *snpda;
-		int local_cpu_num;
-
-		cpu = cnode_slice_to_cpuid(cnode, slice);
-		if (cpu == CPU_NONE)
-			continue;
-
-		/* If this cpu isn't enabled for interrupts, skip it */
-		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
-			continue;
-
-		/* If this isn't the right subnode, skip it */
-		if (!cpu_on_subnode(cpu, which_subnode))
-			continue;
-
-		/* OK, this one's a potential CPU for interrupts */
-		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
-		vecblk0 = &snpda->intr_dispatch0;
-		vecblk1 = &snpda->intr_dispatch1;
-		local_cpu_num = LOCALCPU(slice);
-		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
-		              vecblk1->cpu_count[local_cpu_num];
-
-		if (min_count > total_intrs_to_slice) {
-			min_count = total_intrs_to_slice;
-			best_cpu = cpu;
-		}
-	}
-	return best_cpu;
-}
-
-/*
- * Choose an appropriate interrupt target CPU on a specified node.
- * If which_subnode is SUBNODE_ANY, then subnode is not considered.
- * Otherwise, the chosen CPU must be on the specified subnode.
- */
-static cpuid_t
-intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
-{
-	return(do_intr_cpu_choose(cnode, which_subnode));
-}
-
-
-#ifdef	LATER
-/*
- * Convert a subnode vertex into a (cnodeid, which_subnode) pair.
- * Return 0 on success, non-zero on failure.
- */
-static int
-subnodevertex_to_subnode(devfs_handle_t vhdl, cnodeid_t *cnodeidp, int *which_subnodep)
-{
-	arbitrary_info_t which_subnode;
-	cnodeid_t cnodeid;
-
-	/* Try to grab subnode information */
-	if (hwgraph_info_get_LBL(vhdl, INFO_LBL_CPUBUS, &which_subnode) != GRAPH_SUCCESS)
-		return(-1);
-
-	/* On which node? */
-	cnodeid = master_node_get(vhdl);
-	if (cnodeid == CNODEID_NONE)
-		return(-1);
-
-	*which_subnodep = (int)which_subnode;
-	*cnodeidp = cnodeid;
-	return(0); /* success */
-}
-
-#endif /* LATER */
-
-/* Make it easy to identify subnode vertices in the hwgraph */
-void
-mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
-{
-	graph_error_t rv;
-
-	ASSERT(0 <= which_subnode);
-	ASSERT(which_subnode < NUM_SUBNODES);
-
-	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-
-	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-}
-
-
-/*
- * Given a device descriptor, extract interrupt target information and
- * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
- * out of the target information.
- * TBD: Should this be considered platform-independent code?
- */
-
-#ifdef	LATER
-static cpuid_t
-intr_target_from_desc(device_desc_t dev_desc, int favor_subnode)
-{
-	cpuid_t cpuid = CPU_NONE;
-	cnodeid_t cnodeid;
-	int which_subnode;
-	devfs_handle_t intr_target_dev;
-
-	if ((intr_target_dev = device_desc_intr_target_get(dev_desc)) != GRAPH_VERTEX_NONE) {
-		/* 
-		 * A valid device was specified.  If it's a particular
-		 * CPU, then use that CPU as target.  
-		 */
-		cpuid = cpuvertex_to_cpuid(intr_target_dev);
-		if (cpuid != CPU_NONE)
-			goto cpuchosen;
-
-		/* If a subnode vertex was specified, pick a CPU on that subnode. */
-		if (subnodevertex_to_subnode(intr_target_dev, &cnodeid, &which_subnode) == 0) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, which_subnode);
-			goto cpuchosen;
-		}
-
-		/*
-		 * Otherwise, pick a CPU on the node that owns the 
-		 * specified target.  Favor "favor_subnode", if specified.
-		 */
-		cnodeid = master_node_get(intr_target_dev);
-		if (cnodeid != CNODEID_NONE) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-			goto cpuchosen;
-		}
-	}
-
-cpuchosen:
-	return(cpuid);
-}
-#endif	/* LATER */
-
-
-#ifdef	LATER
-/*
- * Check if we had already visited this candidate cnode
- */
-static void *
-intr_cnode_seen(cnodeid_t 	candidate,
-		void 		*arg1,
-		void 		*arg2)
-{
-	int		i;
-	cnodeid_t	*visited_cnodes = (cnodeid_t *)arg1;
-	int		*num_visited_cnodes = (int *)arg2;
-
-	ASSERT(visited_cnodes);
-	ASSERT(*num_visited_cnodes <= numnodes);
-	for(i = 0 ; i < *num_visited_cnodes; i++) {
-		if (candidate == visited_cnodes[i])
-			return(NULL);
-	}
-	return(visited_cnodes);
-}
-
-#endif /* LATER */
-
-
-
-/*
- * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
- *		owner_dev,intr_name,*resp_bit)
- *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
- * 	not both.
- * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
- * 	interrupt target candidate.
- * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
- *	this node which can be a valid interrupt target candidate.
- * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
- * 	reserving an interrupt bit on the corresponding cnode is made.
- *
- * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
- * interrupt target cpu then routine returns CPU_NONE (failure)
- * Otherwise routine returns cpuid of interrupt target (success)
- */
-static cpuid_t
-intr_bit_reserve_test(cpuid_t 		cpuid,
-		      int		favor_subnode,
-		      cnodeid_t 	cnodeid,
-		      int		req_bit,
-		      int 		intr_resflags,
-		      devfs_handle_t 	owner_dev,
-		      char		*intr_name,
-		      int		*resp_bit)
-{
-
-	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
-
-	if (cnodeid != CNODEID_NONE) {
-		/* Try to choose a interrupt cpu candidate */
-		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-	}
-
-	if (cpuid != CPU_NONE) {
-		/* Try to reserve an interrupt bit on the hub 
-		 * corresponding to the canidate cnode. If we
-		 * are successful then we got a cpu which can
-		 * act as an interrupt target for the io device.
-		 * Otherwise we need to continue the search
-		 * further.
-		 */
-		*resp_bit = do_intr_reserve_level(cpuid, 
-						  req_bit,
-						  intr_resflags,
-						  II_RESERVE,
-						  owner_dev, 
-						  intr_name);
-
-		if (*resp_bit >= 0)
-			/* The interrupt target  specified was fine */
-			return(cpuid);
-	}
-	return(CPU_NONE);
-}
-/*
- * intr_heuristic(dev_t dev,device_desc_t dev_desc,
- *		  int req_bit,int intr_resflags,dev_t owner_dev,
- *		  char *intr_name,int *resp_bit)
- *
- * Choose an interrupt destination for an interrupt.
- *	dev is the device for which the interrupt is being set up
- *	dev_desc is a description of hardware and policy that could
- *		help determine where this interrupt should go
- *	req_bit is the interrupt bit requested 
- *		(can be INTRCONNECT_ANY_BIT in which the first available
- * 		 interrupt bit is used)
- *	intr_resflags indicates whether we want to (un)reserve bit
- *	owner_dev is the owner device
- *	intr_name is the readable interrupt name	
- * 	resp_bit indicates whether we succeeded in getting the required
- *		 action  { (un)reservation} done	
- *		 negative value indicates failure
- *
- */
-/* ARGSUSED */
-cpuid_t
-intr_heuristic(devfs_handle_t 		dev,
-	       device_desc_t 	dev_desc,
-	       int		req_bit,
-	       int 		intr_resflags,
-	       devfs_handle_t 		owner_dev,
-	       char		*intr_name,
-	       int		*resp_bit)
-{
-	cpuid_t		cpuid;				/* possible intr targ*/
-	cnodeid_t 	candidate;			/* possible canidate */
-#ifdef LATER
-	cnodeid_t	visited_cnodes[MAX_NASIDS], 	/* nodes seen so far */
-		        center,				/* node we are on */
-		        candidate;			/* possible canidate */
-	int		num_visited_cnodes = 0;		/* # nodes seen */
-
-	int		radius = 1,			/* start looking at the
-							 * current node
-							 */
-		        maxradius = physmem_maxradius();
-	void		*rv;
-#endif /* LATER */
-	int		which_subnode = SUBNODE_ANY;
-
-/* SN1 + pcibr Addressing Limitation */
-	{
-	devfs_handle_t pconn_vhdl;
-	pcibr_soft_t pcibr_soft;
-
-	/*
-	 * This combination of SN1 and Bridge hardware has an odd "limitation".
-	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
-	 * and historical limitations in Bridge, Bridge is unable to
-	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
-	 * to choose one set or the other.  That choice is implicitly
-	 * made when Bridge first attaches its error interrupt.  After
-	 * that point, all subsequent interrupts are restricted to the
-	 * same PI number (though it's possible to send interrupts to
-	 * the same PI number on a different node).
-	 *
-	 * Since neither SN1 nor Bridge designers are willing to admit a
-	 * bug, we can't really call this a "workaround".  It's a permanent
-	 * solution for an SN1-specific and Bridge-specific hardware
-	 * limitation that won't ever be lifted.
-	 */
-        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
-	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
-		/*
-		 * We "know" that the error interrupt is the first
-		 * interrupt set up by pcibr_attach.  Send all interrupts
-		 * on this bridge to the same subnode number.
-		 */
-		if (pcibr_soft->bsi_err_intr) {
-			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
-		}
-	}
-	}
-
-#ifdef	LATER
-	/* 
-	 * If an interrupt target was specified for this
-	 * interrupt allocation, try to use it.
-	 */
-	if (dev_desc) {
-
-		/* Try to see if the interrupt target specified in the
-		 * device descriptor is a legal candidate.
-		 */
-		cpuid = intr_bit_reserve_test(intr_target_from_desc(dev_desc, which_subnode),
-					      which_subnode,
-					      CNODEID_NONE,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-
-			printk("Override explicit interrupt targetting: %v (0x%x)\n",
-				owner_dev, owner_dev);
-
-			intr_unreserve_level(cpuid, *resp_bit);
-		}
-
-		/* Fall through on to the next step in the search for
-		 * the interrupt candidate.
-		 */
-
-	}
-#endif  /* LATER */
-	
-	/* Check if we can find a valid interrupt target candidate on
-	 * the master node for the device.
-	 */
-	cpuid = intr_bit_reserve_test(CPU_NONE,
-				      which_subnode,	
-				      master_node_get(dev),
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);	/* got a valid interrupt target */
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts to closest node(%d): %ld (0x%lx)\n",
-		master_node_get(dev),(long) owner_dev, (unsigned long)owner_dev);
-
-	/* Fall through into the default algorithm
-	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
-	 * for finding the interrupt target
-	 */
-
-#ifndef BRINGUP
-	// Use of this algorithm is deferred until the supporting
-	// code has been implemented.
-	/* 
-	 * No valid interrupt specification exists.
-	 * Try to find a node which is closest to the current node
-	 * which can process interrupts from a device
-	 */
-
-	center = cpuid_to_cnodeid(smp_processor_id());
-	while (radius <= maxradius) {
-
-		/* Try to find a node at the given radius and which
-		 * we haven't seen already.
-		 */
-		rv = physmem_select_neighbor_node(center,radius,&candidate,
-						  intr_cnode_seen,
-						  (void *)visited_cnodes,
-						  (void *)&num_visited_cnodes);
-		if (!rv) {
-			/* We have seen all the nodes at this particular radius
-			 * Go on to the next radius level.
-			 */
-			radius++;
-			continue;
-		}			      
-		/* We are seeing this candidate  cnode for the first time
-		 */
-		visited_cnodes[num_visited_cnodes++] = candidate;
-
-		cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-			else
-				intr_unreserve_level(cpuid, *resp_bit);
-		}
-	}
-#else  /* BRINGUP */
-	{
-	// Do a stupid round-robin assignment of the node.
-		static cnodeid_t last_node = -1;
-
-		if (last_node >= numnodes) last_node = 0;
-		for (candidate = last_node + 1; candidate != last_node; candidate++) {
-			if (candidate == numnodes) candidate = 0;
-			cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-			if (cpuid != CPU_NONE) {
-				if (cpu_on_subnode(cpuid, which_subnode)) {
-					last_node = candidate;
-					return(cpuid);	/* got a valid interrupt target */
-				}
-				else
-					intr_unreserve_level(cpuid, *resp_bit);
-			}
-		}
-		last_node = candidate;
-	}
-#endif
-
-	PRINT_WARNING("Cannot target interrupts to any close node: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	/* In the worst case try to allocate interrupt bits on the
-	 * master processor's node. We may get here during error interrupt
-	 * allocation phase when the topology matrix is not yet setup
-	 * and hence cannot do an exhaustive search.
-	 */
-	ASSERT(cpu_allows_intr(master_procid));
-	cpuid = intr_bit_reserve_test(master_procid,
-				      which_subnode,
-				      CNODEID_NONE,
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	return(CPU_NONE);	/* Should never get here */
-}
-
-
-
-
-#ifndef BRINGUP
-/*
- * Should never receive an exception while running on the idle 
- * stack.  It IS possible to handle *interrupts* while on the
- * idle stack, but a non-interrupt *exception* is a problem.
- */
-void
-idle_err(inst_t *epc, uint cause, void *fep, void *sp)
-{
-	eframe_t *ep = (eframe_t *)fep;
-
-    if ((cause & CAUSE_EXCMASK) == EXC_IBE ||
-	(cause & CAUSE_EXCMASK) == EXC_DBE) {
-	(void)dobuserre((eframe_t *)ep, epc, 0);
-    }
-
-    /* XXX - This will have to change to deal with various SN errors. */
-    panic( "exception on IDLE stack "
-	    "ep:0x%x epc:0x%x cause:0x%w32x sp:0x%x badvaddr:0x%x",
-	    ep, epc, cause, sp, getbadvaddr());
-    /* NOTREACHED */
-}
-
-
-/*
- * earlynofault - handle very early global faults - usually just while
- *      sizing memory
- * Returns: 1 if should do nofault
- *          0 if not
- */
-/* ARGSUSED */
-int
-earlynofault(eframe_t *ep, uint code)
-{
-	switch(code) {
-	case EXC_DBE:
-		return(1);
-	default:
-		return(0);
-	}
-}
-
-
-
-/* ARGSUSED */
-static void
-cpuintr(void *arg1, void *arg2)
-{
-#if RTE
-	static int rte_intrdebug = 1;
-#endif
-	/*
-	 * Frame Scheduler
-	 */
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_CPUINTR, NULL, NULL,
-			 NULL, NULL);
-
-	/*
-	 * Hardware clears the IO interrupts, but we need to clear software-
-	 * generated interrupts.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_ACTION_A + cputolocalslice(cpuid()));
-
-#if 0
-	/* XXX - Handle error interrupts. */
-	if (error_intr_reason)
-		error_intr();
-#endif /* 0 */
-
-	/*
-	 * If we're headed for panicspin and it is due to a NMI, save the
-	 * eframe in the NMI area
-	 */
-	if (private.p_va_panicspin && nmied) {
-		caddr_t	nmi_save_area;
-
-		nmi_save_area = (caddr_t) (TO_UNCAC(TO_NODE(
-			cputonasid(cpuid()), IP27_NMI_EFRAME_OFFSET)) + 
-			cputoslice(cpuid()) * IP27_NMI_EFRAME_SIZE);
-		bcopy((caddr_t) arg2, nmi_save_area, sizeof(eframe_t));
-	}
-
-	doacvec();
-#if RTE
-	if (private.p_flags & PDAF_ISOLATED && !rte_intrdebug)
-		goto end_cpuintr;
-#endif
-	doactions();
-#if RTE
-end_cpuintr:
-#endif
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_INTREXIT, TSTAMP_EV_CPUINTR, NULL, NULL, NULL);
-}
-
-void
-install_cpuintr(cpuid_t cpu)
-{
-	int		intr_bit = CPU_ACTION_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				(intr_func_t) cpuintr, NULL, NULL))
-		panic("install_cpuintr: Can't connect interrupt.");
-}
-#endif /* BRINGUP */
-
-#ifdef DEBUG_INTR_TSTAMP
-/* We allocate an array, but only use element number 64.  This guarantees that
- * the entry is in a cacheline by itself.
- */
-#define DINTR_CNTIDX	32
-#define DINTR_TSTAMP1	48
-#define	DINTR_TSTAMP2	64
-volatile long long dintr_tstamp_cnt[128];
-int dintr_debug_output=0;
-extern void idbg_tstamp_debug(void);
-#ifdef SPLDEBUG
-extern void idbg_splx_log(int);
-#endif
-#if DEBUG_INTR_TSTAMP_DEBUG
-int dintr_enter_symmon=1000;	/* 1000 microseconds is 1 millisecond */
-#endif
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-cpulatintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_INTRLAT_A + cputolocalslice(cpuid()));
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-	dintr_tstamp_cnt[DINTR_TSTAMP2] =  GET_LOCAL_RTC;
-	if ((dintr_tstamp_cnt[DINTR_TSTAMP2] - dintr_tstamp_cnt[DINTR_TSTAMP1])
-	    > dintr_enter_symmon) {
-#ifdef SPLDEBUG
-		extern int spldebug_log_off;
-
-		spldebug_log_off = 1;
-#endif /* SPLDEBUG */
-		debug("ring");
-#ifdef SPLDEBUG
-		spldebug_log_off = 0;
-#endif /* SPLDEBUG */
-	}
-#endif
-	dintr_tstamp_cnt[DINTR_CNTIDX]++;
-
-	return;
-}
-
-static int install_cpulat_first=0;
-
-void
-install_cpulatintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = CPU_INTRLAT_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, II_THREADED,
-					   cpuv, "intrlat"))
-		panic( "install_cpulatintr: Can't reserve interrupt.");
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				cpulatintr, NULL, NULL))
-		panic( "install_cpulatintr: Can't connect interrupt.");
-
-	if (!install_cpulat_first) {
-		install_cpulat_first++;
-		idbg_addfunc("tstamp_debug", (void (*)())idbg_tstamp_debug);
-#if defined(SPLDEBUG) || defined(SPLDEBUG_CPU_EVENTS)
-		idbg_addfunc("splx_log", (void (*)())idbg_splx_log);
-#endif /* SPLDEBUG || SPLDEBUG_CPU_EVENTS */
-	}
-}
-#endif /* BRINGUP */
-
-#endif /* DEBUG_INTR_TSTAMP */
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-dbgintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpuid()));
-
-	debug("zing");
-	return;
-}
-
-
-void
-install_dbgintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_dbgintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				dbgintr, NULL, NULL))
-		panic("install_dbgintr: Can't connect interrupt.");
-
-#ifdef DEBUG_INTR_TSTAMP
-	/* Set up my interrupt latency test interrupt */
-	install_cpulatintr(cpu);
-#endif
-}
-
-/* ARGSUSED */
-static void
-tlbintr(void *arg)
-{
-	extern void tlbflush_rand(void);
-
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpuid()));
-
-	tlbflush_rand();
-	return;
-}
-
-
-void
-install_tlbintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_tlbintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				tlbintr, NULL, NULL))
-		panic("install_tlbintr: Can't connect interrupt.");
-
-}
-
-
-/*
- * Send an interrupt to all nodes.  Don't panic if we get an error.
- * Returns 1 if any exceptions occurred.
- */
-int
-protected_broadcast(hubreg_t intrbit)
-{
-	nodepda_t *npdap = private.p_nodepda;
-	int byte, bit, sn;
-	int error = 0;
-
-	extern int _wbadaddr_val(volatile void *, int, volatile int *);
-
-	/* Send rather than clear an interrupt. */
-	intrbit |= 0x100;
-	
-	for (byte = 0; byte < NASID_MASK_BYTES; byte++) {
-		for (bit = 0; bit < 8; bit++) {
-			if (npdap->nasid_mask[byte] & (1 << bit)) {
-				nasid_t nasid = byte * 8 + bit;
-				for (sn=0; sn<NUM_SUBNODES; sn++) {
-					error += _wbadaddr_val(REMOTE_HUB_PI_ADDR(nasid,
-					      sn, PI_INT_PEND_MOD),
-					      sizeof(hubreg_t),
-					      (volatile int *)&intrbit);
-				}
-			}
-		}
-	}
-
-	return error;
-}
-
-
-/*
- * Poll the interrupt register to see if another cpu has asked us
- * to drop into the debugger (without lowering spl).
- */
-void
-chkdebug(void)
-{
-	if (LOCAL_HUB_L(PI_INT_PEND1) & (1L << (DEBUG_INTR_A + cputolocalslice(cpuid()))))
-		dbgintr((void *)NULL);
-}
-
-
-/*
- * Install special graphics interrupt.
- */
-void
-install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg)
-{
-	int intr_bit = GFX_INTR_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, swlevel,
-				intr_func, intr_arg, NULL))
-		panic("install_gfxintr: Can't connect interrupt.");
-}
-
-
-/*
- * Install page migration interrupt handler.
- */
-void
-hub_migrintr_init(cnodeid_t cnode)
-{
-	cpuid_t cpu = cnodetocpu(cnode);
-	int intr_bit = INT_PEND0_BASELVL + PG_MIG_INTR;
-
-	if (numnodes == 1){
-		/* 
-		 * No migration with just one node..
-		 */
-		return;
-	}
-	
-	if (cpu != -1) {
-		if (intr_connect_level(cpu, intr_bit, 0,
-			       (intr_func_t) migr_intr_handler, 0, (intr_func_t) migr_intr_prologue_handler))
-			panic( "hub_migrintr_init: Can't connect interrupt.");
-	}
-}
-
-
-/*
- * Cause all CPUs to stop by sending them each a DEBUG interrupt.
- * Parameter is actually a (cpumask_t *).
- */
-void
-debug_stop_all_cpus(void *stoplist)
-{
-	int cpu;
-	ulong level;
-
-	for (cpu=0; cpu<maxcpus; cpu++) {
-		if (cpu == cpuid())
-			continue;
-		if (!cpu_enabled(cpu))
-		        continue;
-		/* "-1" is the old style parameter OR could be the new style
-		 * if no-one is currently stopped.  We only stop the
-		 * requested cpus, the others are already stopped (probably
-		 * at a breakpoint).
-		 */
-
-		if (((cpumask_t *)stoplist != (cpumask_t *)-1LL) &&
-		    (!CPUMASK_TSTB(*(cpumask_t*)stoplist, cpu)))
-			continue;
-
-		/*
-		 * CPU lslice A gets level DEBUG_INTR_A
-		 * CPU lslice B gets level DEBUG_INTR_B
-		 */
-		level = DEBUG_INTR_A + LOCALCPU(get_cpu_slice(cpu));
-		/*
-		 * Convert the compact hub number to the NASID to get the
-		 * correct part of the address space.  Then set the interrupt
-		 * bit associated with the CPU we want to send the interrupt
-		 * to.
-		 */
-		REMOTE_CPU_SEND_INTR(cpu, N_INTPEND_BITS + level);
-
-	}
-}
-
-#endif /* BRINGUP */
-
-struct hardwired_intr_s {
-	signed char level;
-	int flags;
-	char *name;
-} const hardwired_intr[] = {
-	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
-	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
-	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
-	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
-	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
-	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
-	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
-	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
-	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
-	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
-	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
-	{ -1, 0, (char *)NULL},
-};
-
-/*
- * Reserve all of the hardwired interrupt levels so they're not used as
- * general purpose bits later.
- */
-void
-intr_reserve_hardwired(cnodeid_t cnode)
-{
-	cpuid_t cpu;
-	int level;
-	int i;
-	char subnode_done[NUM_SUBNODES];
-
-	// cpu = cnodetocpu(cnode);
-	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
-		if (cpuid_to_cnodeid(cpu) == cnode) {
-			break;
-		}
-	}
-	if (cpu == smp_num_cpus) cpu = CPU_NONE;
-	if (cpu == CPU_NONE) {
-		printk("Node %d has no CPUs", cnode);
-		return;
-	}
-
-	for (i=0; i<NUM_SUBNODES; i++)
-		subnode_done[i] = 0;
-
-	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
-		int which_subnode = cpuid_to_subnode(cpu);
-		if (subnode_done[which_subnode])
-			continue;
-		subnode_done[which_subnode] = 1;
-
-		for (i = 0; hardwired_intr[i].level != -1; i++) {
-			level = hardwired_intr[i].level;
-
-			if (level != intr_reserve_level(cpu, level,
-						hardwired_intr[i].flags,
-						(devfs_handle_t) NULL,
-						hardwired_intr[i].name))
-				panic("intr_reserve_hardwired: Can't reserve level %d.", level);
-		}
-	}
-}
-
-
-/*
- * Check and clear interrupts.
- */
-/*ARGSUSED*/
-static void
-intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
-		char *name)
-{
-	volatile hubreg_t bits;
-	int i;
-
-	/* Check pending interrupts */
-	if ((bits = HUB_L(pend)) != 0) {
-		for (i = 0; i < N_INTPEND_BITS; i++) {
-			if (bits & (1 << i)) {
-#ifdef INTRDEBUG
-				PRINT_WARNING("Nasid %d interrupt bit %d set in %s",
-					nasid, i, name);
-#endif
-				LOCAL_HUB_CLR_INTR(base_level + i);
-			}
-		}
-	}
-}
-
-/*
- * Clear out our interrupt registers.
- */
-void
-intr_clear_all(nasid_t nasid)
-{
-	int	sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
-	
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
-				INT_PEND0_BASELVL, "INT_PEND0");
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
-				INT_PEND1_BASELVL, "INT_PEND1");
-	}
-}
-
-/* 
- * Dump information about a particular interrupt vector.
- */
-static void
-dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
-		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
-{
-	hubreg_t value = 1LL << bit;
-
-	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
-		bit, info->ii_name,
-		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
-	pf("   vertex 0x%x %s%s",
-		info->ii_owner_dev,
-		((info->ii_flags) & II_RESERVE) ? "R" : "U",
-		((info->ii_flags) & II_INUSE) ? "C" : "-");
-	pf("%s%s%s%s",
-		ip & value ? "P" : "-",
-		ima & value ? "A" : "-",
-		imb & value ? "B" : "-",
-		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
-	pf("\n");
-}
-
-
-/*
- * Dump information about interrupt vector assignment.
- */
-void
-intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
-{
-	nodepda_t *npda;
-	int ip, sn, bit;
-	intr_vecblk_t *dispatch;
-	hubreg_t ipr, ima, imb;
-	nasid_t nasid;
-
-	if ((cnode < 0) || (cnode >= numnodes)) {
-		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
-		return ;
-	}
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	if (nasid == INVALID_NASID) {
-		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
-		return ;
-	}
-		
-
-	npda = NODEPDA(cnode);
-
-	for (sn = 0; sn < NUM_SUBNODES; sn++) {
-		for (ip = 0; ip < 2; ip++) {
-			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
-			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
-			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
-			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
-	
-			pf("Node %d INT_PEND%d:\n", cnode, ip);
-	
-			if (dispatch->ithreads_enabled)
-				pf(" Ithreads enabled\n");
-			else
-				pf(" Ithreads disabled\n");
-			pf(" vector_count = %d, vector_state = %d\n",
-				dispatch->vector_count,
-				dispatch->vector_state);
-			pf(" CPU A count %d, CPU B count %d\n",
- 		   	dispatch->cpu_count[0],
- 		   	dispatch->cpu_count[1]);
-			pf(" &vector_lock = 0x%x\n",
-				&(dispatch->vector_lock));
-			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
-				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
-			    	(ipr & (1L << bit))) {
-					dump_vector(&(dispatch->info[bit]),
-					    	&(dispatch->vectors[bit]),
-					    	bit, ipr, ima, imb, pf);
-				}
-			}
-			pf("\n");
-		}
-	}
-}
-
diff -urN linux-2.4.16/arch/ia64/sn/io/ml_iograph.c lia64-2.4/arch/ia64/sn/io/ml_iograph.c
--- linux-2.4.16/arch/ia64/sn/io/ml_iograph.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/ml_iograph.c	Mon Nov 19 23:22:51 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -13,6 +12,9 @@
 #include <linux/slab.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
@@ -30,8 +32,6 @@
 #include <asm/sn/xtalk/xtalk_private.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 
-extern int maxnodes;
-
 /* #define IOGRAPH_DEBUG */
 #ifdef IOGRAPH_DEBUG
 #define DBG(x...) printk(x)
@@ -107,10 +107,10 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(master)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("volunteer for widgets: vertex %v has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex %v has no info label",
 			xswitch);
 #else
-		PRINT_WARNING("volunteer for widgets: vertex 0x%x has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex 0x%x has no info label",
 			xswitch);
 #endif
 	    }
@@ -155,11 +155,11 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(hubv)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex %v has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex %v has "
 			" no info label",
 			xswitch);
 #else
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex 0x%x has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex 0x%x has "
 			" no info label",
 			xswitch);
 #endif
@@ -183,7 +183,6 @@
 	 * widgets to hubs.
 	 */
 	for (widgetnum=HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
-
 #ifndef BRINGUP
 		int i;
 #endif
@@ -244,12 +243,12 @@
 	cnodeid_t cnode;
 	nasid_t nasid;
 	lboard_t *board;
-
+	
 	/*
 	 * Init. the board-to-hwgraph link early, so FRU analyzer
 	 * doesn't trip on leftover values if we panic early on.
 	 */
-	for(cnode = 0; cnode < numnodes; cnode++) {
+	for(cnode = 0; cnode < num_compact_nodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 		board = (lboard_t *)KL_CONFIG_INFO(nasid);
 		DBG("iograph_early_init: Found board 0x%p\n", board);
@@ -267,55 +266,6 @@
 	hubio_init();
 }
 
-#ifdef LATER
-/* There is an identical definition of this in os/scheduler/runq.c */
-#define INIT_COOKIE(cookie) cookie.must_run = 0; cookie.cpu = PDA_RUNANYWHERE
-/*
- * These functions absolutely doesn't belong here.  It's  here, though, 
- * until the scheduler provides a platform-independent version
- * that works the way it should.  The interface will definitely change, 
- * too.  Currently used only in this file and by io/cdl.c in order to
- * bind various I/O threads to a CPU on the proper node.
- */
-cpu_cookie_t
-setnoderun(cnodeid_t cnodeid)
-{
-	int i;
-	cpuid_t cpunum;
-	cpu_cookie_t cookie;
-
-	INIT_COOKIE(cookie);
-	if (cnodeid == CNODEID_NONE)
-		return(cookie);
-
-	/*
-	 * Do a setmustrun to one of the CPUs on the specified
-	 * node.
-	 */
-	if ((cpunum = CNODE_TO_CPU_BASE(cnodeid)) == CPU_NONE) {
-		return(cookie);
-	}
-
-	cpunum += CNODE_NUM_CPUS(cnodeid) - 1;
-
-	for (i = 0; i < CNODE_NUM_CPUS(cnodeid); i++, cpunum--) {
-
-		if (cpu_enabled(cpunum)) {
-			cookie = setmustrun(cpunum);
-			break;
-		}
-	}
-
-	return(cookie);
-}
-
-void
-restorenoderun(cpu_cookie_t cookie)
-{
-	restoremustrun(cookie);
-}
-#endif	/* LATER */
-
 #ifdef LINUX_KERNEL_THREADS
 static struct semaphore io_init_sema;
 #endif
@@ -445,6 +395,9 @@
 	slotid_t		slot;
 	lboard_t		*board = NULL;
 	char			buffer[16];
+#ifdef BRINGUP
+	slotid_t get_widget_slotnum(int xbow, int widget);
+#endif
 	
 	DBG("\nio_xswitch_widget_init: hubv 0x%p, xswitchv 0x%p, widgetnum 0x%x\n", hubv, xswitchv, widgetnum);
 	/*
@@ -507,6 +460,7 @@
 {
 		lboard_t dummy;
 
+
 			if (board) {
 				DBG("io_xswitch_widget_init: Found KLTYPE_IOBRICK Board 0x%p brd_type 0x%x\n", board, board->brd_type);
 			} else {
@@ -729,41 +683,25 @@
 		    GRAPH_SUCCESS)
 			continue;
 
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 		board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid),
 				NODEPDA(cnodeid)->module_id);
-#else
-		{
-		slotid_t	slot;
-		slot = get_widget_slotnum(xbow_num, widgetnum);
-		board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    NODEPDA(cnodeid)->module_id, slot);
-		}
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		if (board == NULL && peer_nasid != INVALID_NASID) {
 			/*
 			 * Try to find the board on our peer
 			 */
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 			board = find_lboard_module(
 				(lboard_t *)KL_CONFIG_INFO(peer_nasid),
 				NODEPDA(cnodeid)->module_id);
-
-#else
-			board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(peer_nasid),
-						    NODEPDA(cnodeid)->module_id, slot);
-
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		}
 		if (board == NULL) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not find PROM info for vertex %v, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex %v, "
 				"FRU analyzer may fail",
 				vhdl);
 #else
-			PRINT_WARNING("Could not find PROM info for vertex 0x%x, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex 0x%p, "
 				"FRU analyzer may fail",
-				vhdl);
+				(void *)vhdl);
 #endif
 			return;
 		}
@@ -930,7 +868,7 @@
 	} else { 
 		npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
 
-		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, hubv);
+		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
 
 		/*NOTREACHED*/
 	}
@@ -1037,7 +975,7 @@
 #define __DEVSTR3 	"/lun/0/disk/partition/"
 #define	__DEVSTR4	"/../ef"
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  * Currently, we need to allow for 5 IBrick slots with 1 FC each
  * plus an internal 1394.
@@ -1045,6 +983,8 @@
  * ioconfig starts numbering SCSI's at NUM_BASE_IO_SCSI_CTLR.
  */
 #define NUM_BASE_IO_SCSI_CTLR 6
+#else
+#define NUM_BASE_IO_SCSI_CTLR 6
 #endif
 /*
  * This tells ioconfig where it can start numbering scsi controllers.
@@ -1072,7 +1012,6 @@
 		for (i=0; i<NUM_BASE_IO_SCSI_CTLR; i++)
 			base_io_scsi_ctlr_vhdl[i] = GRAPH_VERTEX_NONE;
 	}
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
 	{
 	/*
 	 * May want to consider changing the SN0 code, above, to work more like
@@ -1129,14 +1068,10 @@
 
 	hwgraph_vertex_unref(base_ibrick_xbridge_vhdl);
 	}
-#else
-#pragma error Bomb!
-#endif
 }
 
 
 #include <asm/sn/ioerror_handling.h>
-extern devfs_handle_t 	ioc3_console_vhdl_get(void);
 devfs_handle_t		sys_critical_graph_root = GRAPH_VERTEX_NONE;
 
 /* Define the system critical vertices and connect them through
@@ -1251,6 +1186,7 @@
 {
 	char 			name[MAXDEVNAME];
 	devfs_handle_t		console_vhdl, pci_vhdl, enet_vhdl;
+	devfs_handle_t		ioc3_console_vhdl_get(void);
 
 
 	DBG("baseio_ctlr_num_set; FIXME\n");
@@ -1335,7 +1271,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 0, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 
 	if ((vendor_list[5] != PCIIO_VENDOR_ID_NONE) && 
 	    (vendor_list[7] != PCIIO_VENDOR_ID_NONE)) {
@@ -1355,7 +1291,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 1, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 }
 
 
@@ -1379,7 +1315,7 @@
 #endif
 
 	active = 0;
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++) {
+	for (cnodeid = 0; cnodeid < num_compact_nodes; cnodeid++) {
 #ifdef LINUX_KERNEL_THREADS
 		char thread_name[16];
 		extern int io_init_pri;
@@ -1428,7 +1364,7 @@
 
 #endif /* LINUX_KERNEL_THREADS */
 
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++)
+	for (cnodeid = 0; cnodeid < num_compact_nodes; cnodeid++)
 		/*
 	 	 * Update information generated by IO init.
 		 */
diff -urN linux-2.4.16/arch/ia64/sn/io/module.c lia64-2.4/arch/ia64/sn/io/module.c
--- linux-2.4.16/arch/ia64/sn/io/module.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/module.c	Mon Nov 19 23:22:51 2001
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
@@ -25,7 +26,7 @@
 #include <asm/sn/sn_cpuid.h>
 
 
-/* #define LDEBUG	1	*/
+/* #define LDEBUG	1 */
 
 #ifdef LDEBUG
 #define DPRINTF		printk
@@ -173,9 +174,35 @@
     lboard_t	       *board;
     klmod_serial_num_t *comp;
     char * bcopy(const char * src, char * dest, int count);
+    char serial_number[16];
+
+    /*
+     * record brick serial number
+     */
+    board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
+
+    if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
+    {
+#if	LDEBUG
+	printf ("module_probe_snum: no IP35 board found!\n");
+#endif
+	return 0;
+    }
+
+    board_serial_number_get( board, serial_number );
+    if( serial_number[0] != '\0' ) {
+	encode_str_serial( serial_number, m->snum.snum_str );
+	m->snum_valid = 1;
+    }
+#if	LDEBUG
+    else {
+	printf("module_probe_snum: brick serial number is null!\n");
+    }
+    printf("module_probe_snum: brick serial number == %s\n", serial_number);
+#endif /* DEBUG */
 
     board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			KLTYPE_MIDPLANE8);
+			KLTYPE_IOBRICK_XBOW);
 
     if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
 	return 0;
@@ -196,13 +223,13 @@
 
 	    if (comp->snum.snum_str[0] != '\0') {
 		bcopy(comp->snum.snum_str,
-		      m->snum.snum_str,
+		      m->sys_snum,
 		      MAX_SERIAL_NUM_SIZE);
-		m->snum_valid = 1;
+		m->sys_snum_valid = 1;
 	    }
     }
 
-    if (m->snum_valid)
+    if (m->sys_snum_valid)
 	return 1;
     else {
 	DPRINTF("Invalid serial number for module %d, "
@@ -224,11 +251,10 @@
 
     nserial = 0;
 
-    for (node = 0; node < numnodes; node++) {
+    for (node = 0; node < num_compact_nodes; node++) {
 	nasid = COMPACT_TO_NASID_NODEID(node);
 
-	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			    KLTYPE_IP27);
+	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	ASSERT(board);
 
 	m = module_add_node(board->brd_module, node);
@@ -241,7 +267,7 @@
 	    nserial);
 
     if (nserial == 0)
-	PRINT_WARNING("io_module_init: No serial number found.\n");
+	printk(KERN_WARNING  "io_module_init: No serial number found.\n");
 }
 
 elsc_t *get_elsc(void)
diff -urN linux-2.4.16/arch/ia64/sn/io/pci.c lia64-2.4/arch/ia64/sn/io/pci.c
--- linux-2.4.16/arch/ia64/sn/io/pci.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/pci.c	Mon Nov 19 23:22:51 2001
@@ -1,12 +1,12 @@
 /* 
  *
+ * SNI64 specific PCI support for SNI IO.
+ *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * SNI64 specific PCI support for SNI IO.
- *
- * Copyright (C) 1997, 1998, 2000 Colin Ngam
+ * Copyright (c) 1997, 1998, 2000-2001 Silicon Graphics, Inc.  All rights reserved.
  */
 #include <linux/init.h>
 #include <linux/types.h>
@@ -14,7 +14,8 @@
 #include <linux/pci.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -237,10 +238,6 @@
 
 	sgi_master_io_infr_init();
 
-#ifdef BRINGUP
-	if ( IS_RUNNING_ON_SIMULATOR() )
-		return;
-#endif
 	/* sn1_io_infrastructure_init(); */
 	pci_conf = snia64_pci_ops;
 }
@@ -251,8 +248,6 @@
         int 		i;
 	unsigned int 	size;
 
-	devfs_handle_t	bridge_vhdl = pci_bus_to_vertex(d->bus->number);
-
         /* IOC3 only decodes 0x20 bytes of the config space, reading
 	 * beyond that is relatively benign but writing beyond that
 	 * (especially the base address registers) will shut down the
@@ -294,5 +289,12 @@
         d->subsystem_device = 0;
 
 }
+
+#else
+void sn1_pci_find_bios(void) {}
+void pci_fixup_ioc3(struct pci_dev *d) {}
+struct list_head pci_root_buses;
+struct list_head pci_root_buses;
+struct list_head pci_devices;
 
 #endif /* CONFIG_PCI */
diff -urN linux-2.4.16/arch/ia64/sn/io/pci_bus_cvlink.c lia64-2.4/arch/ia64/sn/io/pci_bus_cvlink.c
--- linux-2.4.16/arch/ia64/sn/io/pci_bus_cvlink.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/pci_bus_cvlink.c	Mon Nov 19 23:22:51 2001
@@ -4,19 +4,21 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/pci_ids.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <asm/sn/types.h>
 #include <asm/sn/hack.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -26,18 +28,18 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/io.h>
-
+#include <asm/sn/nodepda.h>
 #include <asm/sn/pci/pciio.h>
-// #include <sys/ql.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-extern int bridge_rev_b_data_check_disable;
 #include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
+
+extern int bridge_rev_b_data_check_disable;
 
 #define MAX_PCI_XWIDGET 256
 devfs_handle_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET];
@@ -55,6 +57,8 @@
 struct ioports_to_tlbs_s ioports_to_tlbs[MAX_IOPORTS_CHUNKS];
 unsigned long sn1_allocate_ioports(unsigned long pci_address);
 
+extern void sn1_init_irq_desc(void);
+
 
 
 /*
@@ -104,7 +108,7 @@
 	int func = 0;
 	char	name[16];
 	devfs_handle_t  pci_bus = NULL;
-	devfs_handle_t	device_vertex = NULL;
+	devfs_handle_t	device_vertex = (devfs_handle_t)NULL;
 
 	/*
 	 * Go get the pci bus vertex.
@@ -189,7 +193,7 @@
  *	Address.  This address via the tlb entries generates the PCI Address 
  *	allocated by the SN1 IO Infrastructure Layer.
  */
-static unsigned long sn1_ioport_num = 0x100; /* Reserve room for Legacy stuff */
+static unsigned long sn1_ioport_num = 0x1000; /* Reserve room for Legacy stuff */
 unsigned long
 sn1_allocate_ioports(unsigned long pci_address)
 {
@@ -209,17 +213,19 @@
 	 * Manual for details.
 	 */
 	ioport_index = sn1_ioport_num / SN1_IOPORTS_UNIT;
-	ioports_to_tlbs[ioport_index].ppn = pci_address;
+
 	ioports_to_tlbs[ioport_index].p = 1; /* Present Bit */
-	ioports_to_tlbs[ioport_index].ma = 5; /* Memory Attributes */
-	ioports_to_tlbs[ioport_index].a = 0; /* Set Data Access Bit Fault */
-	ioports_to_tlbs[ioport_index].d = 0; /* Dirty Bit */
-	ioports_to_tlbs[ioport_index].pl = 3;/* Privilege Level - All levels can R/W*/
-	ioports_to_tlbs[ioport_index].ar = 2; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].rv_1 = 0; /* 1 Bit */
+	ioports_to_tlbs[ioport_index].ma = 4; /* Memory Attributes 3 bits*/
+	ioports_to_tlbs[ioport_index].a = 1; /* Set Data Access Bit Fault 1 Bit*/
+	ioports_to_tlbs[ioport_index].d = 1; /* Dirty Bit */
+	ioports_to_tlbs[ioport_index].pl = 0;/* Privilege Level - All levels can R/W*/
+	ioports_to_tlbs[ioport_index].ar = 3; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].ppn = pci_address >> 12; /* 4K page size */
 	ioports_to_tlbs[ioport_index].ed = 0; /* Exception Deferral Bit */
 	ioports_to_tlbs[ioport_index].ig = 0; /* Ignored */
 
-	printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index].ppn);
+	/* printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index]); */
 	
 	sn1_ioport_num += SN1_IOPORTS_UNIT;
 
@@ -241,18 +247,28 @@
 	struct pci_dev *device_dev = NULL;
 	struct sn1_widget_sysdata *widget_sysdata;
 	struct sn1_device_sysdata *device_sysdata;
+#ifdef SN1_IOPORTS
 	unsigned long ioport;
+#endif
 	pciio_intr_t intr_handle;
 	int cpuid, bit;
-	devfs_handle_t *device_vertex;
+	devfs_handle_t device_vertex;
 	pciio_intr_line_t lines;
 	extern void sn1_pci_find_bios(void);
+#ifdef CONFIG_IA64_SGI_SN2
+	extern int num_compact_nodes;
+	int cnode;
+#endif /* CONFIG_IA64_SGI_SN2 */
 
 
-unsigned long   res;
-
 	if (arg == 0) {
+		sn1_init_irq_desc();
 		sn1_pci_find_bios();
+#ifdef CONFIG_IA64_SGI_SN2
+		for (cnode = 0; cnode < num_compact_nodes; cnode++) {
+				intr_init_vecblk(NODEPDA(cnode), cnode, 0);
+		} 
+#endif /* CONFIG_IA64_SGI_SN2 */
 		return;
 	}
 
@@ -274,13 +290,6 @@
 #endif
 	done_probing = 1;
 
-	if ( IS_RUNNING_ON_SIMULATOR() ) {
-		printk("sn1_pci_fixup not supported on simulator.\n");
-		return;
-	}
-
-#ifdef REAL_HARDWARE
-
 	/*
 	 * Initialize the pci bus vertex in the pci_bus struct.
 	 */
@@ -296,8 +305,28 @@
  	 * set the root start and end so that drivers calling check_region()
 	 * won't see a conflict
 	 */
-	ioport_resource.start |= IO_SWIZ_BASE;
+#ifdef SN1_IOPORTS
+	ioport_resource.start  = sn1_ioport_num;
+	ioport_resource.end = 0xffff;
+#else
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( IS_RUNNING_ON_SIMULATOR() ) {
+		/*
+		 * IDE legacy IO PORTs are supported in Medusa.
+		 * Just open up IO PORTs from 0 .. ioport_resource.end.
+		 */
+		ioport_resource.start = 0;
+	} else {
+		/*
+		 * We do not support Legacy IO PORT numbers.
+		 */
+		ioport_resource.start |= IO_SWIZ_BASE;
+	}
 	ioport_resource.end |= (HSPEC_SWIZ_BASE-1);
+#else
+	// Need something here for sn2.... ZXZXZX
+#endif
+#endif
 	/*
 	 * Initialize the device vertex in the pci_dev struct.
 	 */
@@ -307,6 +336,7 @@
 		u16 cmd;
 		devfs_handle_t vhdl;
 		unsigned long size;
+		extern int bit_pos_to_irq(int);
 
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 				device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
@@ -336,11 +366,7 @@
 			size = device_dev->resource[idx].end -
 				device_dev->resource[idx].start;
 			if (size) {
-				res = 0;
-				res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
 				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
-
-/* printk("sn1_pci_fixup: Mapped Address = 0x%p size = 0x%x\n", device_dev->resource[idx].start, size); */
 			}
 			else
 				continue;
@@ -355,15 +381,23 @@
 				device_dev->resource[idx].start & 0xfffff7ffffffffff;
 			device_dev->resource[idx].end = 
 				device_dev->resource[idx].end & 0xfffff7ffffffffff;
-			res = 0;
-			res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
 			if (device_dev->resource[idx].flags & IORESOURCE_IO) {
 				cmd |= PCI_COMMAND_IO;
+#ifdef SN1_IOPORTS
 				ioport = sn1_allocate_ioports(device_dev->resource[idx].start);
-				/* device_dev->resource[idx].start = ioport; */
-				/* device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT */
+				if (ioport < 0) {
+					printk("sn1_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
+					continue;
+				}
+				pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
+
+printk("sn1_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
+
+				device_dev->resource[idx].start = ioport;
+				device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT;
+#endif
 			}
-			else if (device_dev->resource[idx].flags & IORESOURCE_MEM)
+			if (device_dev->resource[idx].flags & IORESOURCE_MEM)
 				cmd |= PCI_COMMAND_MEMORY;
 		}
 		/*
@@ -371,17 +405,20 @@
 		 */
 		size = device_dev->resource[PCI_ROM_RESOURCE].end -
 			device_dev->resource[PCI_ROM_RESOURCE].start;
-		device_dev->resource[PCI_ROM_RESOURCE].start =
+
+		if (size) {
+			device_dev->resource[PCI_ROM_RESOURCE].start =
 			(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 
 				size, 0, PCIIO_BYTE_STREAM);
-		device_dev->resource[PCI_ROM_RESOURCE].end =
+			device_dev->resource[PCI_ROM_RESOURCE].end =
 			device_dev->resource[PCI_ROM_RESOURCE].start + size;
 
-                /*
-                 * go through synergy swizzled space
-                 */
-		device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
-		device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+                	/*
+                 	 * go through synergy swizzled space
+                 	 */
+			device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
+			device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+		}
 
 		/*
 		 * Update the Command Word on the Card.
@@ -390,7 +427,7 @@
 					   /* bit gets dropped .. no harm */
 		pci_write_config_word(device_dev, PCI_COMMAND, cmd);
 
-		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, &lines);
+		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
 #ifdef BRINGUP
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 			device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
@@ -406,13 +443,33 @@
 
 		bit = intr_handle->pi_irq;
 		cpuid = intr_handle->pi_cpu;
+#ifdef CONFIG_IA64_SGI_SN1
 		irq = bit_pos_to_irq(bit);
+#else /* SN2 */
+		irq = bit;
+#endif
 		irq = irq + (cpuid << 8);
-		pciio_intr_connect(intr_handle, NULL, NULL, NULL);
+		pciio_intr_connect(intr_handle);
 		device_dev->irq = irq;
+#ifdef ajmtestintr
+		{
+			int slot = PCI_SLOT(device_dev->devfn);
+			static int timer_set = 0;
+			pcibr_intr_t	pcibr_intr = (pcibr_intr_t)intr_handle;
+			pcibr_soft_t	pcibr_soft = pcibr_intr->bi_soft;
+			extern void intr_test_handle_intr(int, void*, struct pt_regs *);
+
+			if (!timer_set) {
+				intr_test_set_timer();
+				timer_set = 1;
+			}
+			intr_test_register_irq(irq, pcibr_soft, slot);
+			request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
+		}
+#endif
 
 	}
-#endif	/* REAL_HARDWARE */
+
 #if 0
 
 {
@@ -430,6 +487,10 @@
         printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
         printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
 }
+
+printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
+printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
+
 #endif
 
 }
@@ -472,12 +533,14 @@
 	 * Loop throught this vertex and get the Xwidgets ..
 	 */
 	for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {
+#if 0
         {
                 int pos;
                 char dname[256];
                 pos = devfs_generate_path(xtalk, dname, 256);
                 printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
         }
+#endif
 
 		sprintf(pathname, "%d", widgetnum);
 		xwidget = NULL;
@@ -512,12 +575,12 @@
 		 */
 		master_node_vertex = device_master_get(xwidget);
 		if (!master_node_vertex) {
-			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget);
 		}
 	
 		hubinfo_get(master_node_vertex, &hubinfo);
 		if (!hubinfo) {
-			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", master_node_vertex);
+			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex);
 			return(1);
 		} else {
 			busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
@@ -529,7 +592,7 @@
 		busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(
 			sizeof(struct sn1_dma_maps_s) * 512, GFP_KERNEL);
 		if (!busnum_to_atedmamaps[num_bridges - 1])
-			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget);
 
 		memset(busnum_to_atedmamaps[num_bridges - 1], 0x0, 
 			sizeof(struct sn1_dma_maps_s) * 512);
@@ -552,14 +615,10 @@
 {
 
 	devfs_handle_t devfs_hdl = NULL;
-	devfs_handle_t module_comp = NULL;
-	devfs_handle_t node = NULL;
 	devfs_handle_t xtalk = NULL;
-	graph_vertex_place_t placeptr = EDGE_PLACE_WANT_REAL_EDGES;
 	int rv = 0;
 	char name[256];
 	int master_iobrick;
-	moduleid_t iobrick_id;
 	int i;
 
 	/*
@@ -619,66 +678,4 @@
 	}
 
 	return(0);
-}
-
-/*
- * sgi_pci_intr_support -
- */
-int
-sgi_pci_intr_support (unsigned int requested_irq, device_desc_t *dev_desc,
-	devfs_handle_t *bus_vertex, pciio_intr_line_t *lines,
-	devfs_handle_t *device_vertex)
-
-{
-
-	unsigned int bus;
-	unsigned int devfn;
-	struct pci_dev *pci_dev;
-	unsigned char intr_pin = 0;
-	struct sn1_widget_sysdata *widget_sysdata;
-	struct sn1_device_sysdata *device_sysdata;
-
-	if (!dev_desc || !bus_vertex || !device_vertex) {
-		printk("WARNING: sgi_pci_intr_support: Invalid parameter dev_desc 0x%p, bus_vertex 0x%p, device_vertex 0x%p\n", dev_desc, bus_vertex, device_vertex);
-		return(-1);
-	}
-
-	devfn = (requested_irq >> 8) & 0xff;
-	bus = (requested_irq >> 16) & 0xffff;
-	pci_dev = pci_find_slot(bus, devfn);
-	widget_sysdata = (struct sn1_widget_sysdata *)pci_dev->bus->sysdata;
-	*bus_vertex = widget_sysdata->vhdl;
-	device_sysdata = (struct sn1_device_sysdata *)pci_dev->sysdata;
-	*device_vertex = device_sysdata->vhdl;
-#if 0
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(*device_vertex, dname, 256);
-		printk("%s : path= %s pos %d\n", __FUNCTION__, &dname[pos], pos);
-	}
-#endif /* BRINGUP */
-
-
-	/*
-	 * Get the Interrupt PIN.
-	 */
-	pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intr_pin);
-	*lines = (pciio_intr_line_t)intr_pin;
-
-#ifdef BRINGUP
-	/*
-	 * ioc3 can't decode the PCI_INTERRUPT_PIN field of its config
-	 * space so we have to set it here
-	 */
-	if (pci_dev->vendor == PCI_VENDOR_ID_SGI &&
-	    pci_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
-		*lines = 1;
-	}
-#endif /* BRINGUP */
-
-	/* Not supported currently */
-	*dev_desc = NULL;
-	return(0);
-
 }
diff -urN linux-2.4.16/arch/ia64/sn/io/pci_dma.c lia64-2.4/arch/ia64/sn/io/pci_dma.c
--- linux-2.4.16/arch/ia64/sn/io/pci_dma.c	Wed Oct 24 10:17:42 2001
+++ lia64-2.4/arch/ia64/sn/io/pci_dma.c	Mon Nov 19 23:22:51 2001
@@ -3,8 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Leo Dagum
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/config.h>
@@ -15,34 +14,18 @@
 #include <linux/slab.h>
 #include <linux/devfs_fs_kernel.h>
 
-#ifndef LANGUAGE_C 
-#define LANGUAGE_C 99
-#endif
-#ifndef _LANGUAGE_C
-#define _LANGUAGE_C 99
-#endif
-
 #include <asm/io.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/types.h>
 #include <asm/sn/alenlist.h>
 #include <asm/sn/pci/pci_bus_cvlink.h>
-
-/*
- * this is REALLY ugly, blame it on gcc's lame inlining that we
- * have to put procedures in header files
- */
-#if LANGUAGE_C == 99
-#undef LANGUAGE_C
-#endif
-#if CONFIG_IA64_SGI_IO == 99
-#undef CONFIG_IA64_SGI_IO
-#endif
+#include <asm/sn/nag.h>
 
 pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
 struct sn1_dma_maps_s *find_sn1_dma_map(dma_addr_t, unsigned char);
@@ -182,7 +165,7 @@
 }
 
 /*
- * On sn1 we use the orig_address entry of the scatterlist to store
+ * On sn1 we use the page entry of the scatterlist to store
  * the physical address corresponding to the given virtual address
  */
 int
@@ -208,9 +191,33 @@
 	device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata;
 	vhdl = device_sysdata->vhdl;
 	for (i = 0; i < nents; i++, sg++) {
-		sg->orig_address = (char *)NULL;
+		/* this catches incorrectly written drivers that
+                   attempt to map scatterlists that they have
+                   previously mapped.  we print a warning and
+                   continue, but the driver should be fixed */
+		switch (((u64)sg->address) >> 60) {
+		case 0xa:
+		case 0xb:
+#ifdef BRINGUP
+/* This needs to be cleaned up at some point. */
+			NAG("A PCI driver (for device at%8s) has attempted to map "
+			    "a scatterlist that was previously mapped at %p - "
+			     "this is currently being worked around.\n",
+			    hwdev->slot_name, (void *)sg->address);
+#endif
+			temp_ptr = (u64)sg->address & TO_PHYS_MASK;
+			break;
+		case 0xe: /* a good address, we now map it. */
+			temp_ptr = (paddr_t) __pa(sg->address);
+			break;
+		default:
+			printk(KERN_ERR
+			       "Very bad address (%p) passed to sn1_pci_map_sg\n",
+			       (void *)sg->address);
+			BUG();
+		}
+		sg->page = (char *)NULL;
 		dma_addr = 0;
-		temp_ptr = (paddr_t) __pa(sg->address);
 
 		/*
 		 * Handle the most common case 64Bit cards.
@@ -254,7 +261,7 @@
 		dma_addr = (dma_addr_t)pciio_dmamap_addr(dma_map, temp_ptr, sg->length);
 		/* printk("pci_map_sg: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, temp_ptr, dma_addr); */
 		sg->address = (char *)dma_addr;
-		sg->orig_address = (char *)dma_map;
+		sg->page = (char *)dma_map;
 		
 	}
 
@@ -278,19 +285,19 @@
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++)
-		if (sg->orig_address) {
+		if (sg->page) {
 			/*
-			 * We maintain the DMA Map pointer in sg->orig_address if 
+			 * We maintain the DMA Map pointer in sg->page if 
 			 * it is ever allocated.
 			 */
 			/* phys_to_virt((dma_addr_t)sg->address | ~0x80000000); */
-			/* sg->address = sg->orig_address; */
+			/* sg->address = sg->page; */
 			sg->address = (char *)-1;
-			sn1_dma_map = (struct sn1_dma_maps_s *)sg->orig_address;
+			sn1_dma_map = (struct sn1_dma_maps_s *)sg->page;
 			pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map);
 			pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map);
 			sn1_dma_map->dma_addr = 0;
-			sg->orig_address = 0;
+			sg->page = 0;
 		}
 }
 
diff -urN linux-2.4.16/arch/ia64/sn/io/pciba.c lia64-2.4/arch/ia64/sn/io/pciba.c
--- linux-2.4.16/arch/ia64/sn/io/pciba.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/pciba.c	Mon Nov 19 23:22:51 2001
@@ -1,1716 +1,958 @@
-/* $Id$
+/*
+ * arch/ia64/sn/io/pciba.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * IRIX PCIBA-inspired user mode PCI interface
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * requires: devfs
+ *
+ * device nodes show up in /dev/pci/BB/SS.F (where BB is the bus the
+ * device is on, SS is the slot the device is in, and F is the
+ * device's function on a multi-function card).
+ *
+ * when compiled into the kernel, it will only be initialized by the
+ * sgi sn1 specific initialization code.  in this case, device nodes
+ * are under /dev/hw/..../
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * 03262001 - Initial version by Chad Talbott
  */
 
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
 
-#define copyin(_a, _b, _c)	copy_from_user(_b, _a, _c)
+/* jesse's beefs:
 
-#ifndef	DEBUG_PCIBA
-#define	DEBUG_PCIBA		0
+   register_pci_device should be documented
+   
+   grossness with do_swap should be documented
+   
+   big, gross union'ized node_data should be replaced with independent
+   structures
+
+   replace global list of nodes with global lists of resources.  could
+   use object oriented approach of allocating and cleaning up
+   resources.
+   
+*/
+
+
+#include <linux/config.h>
+#ifndef CONFIG_DEVFS_FS
+#  error PCIBA requires devfs
 #endif
 
-/* v_mapphys does not percolate page offset back. */
-#define	PCIBA_ALIGN_CHECK	1
+#include <linux/module.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+
+#include <linux/mm.h>
+#include <linux/malloc.h>
+#include <linux/vmalloc.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+#include <linux/raw.h>
+#include <linux/capability.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/page.h>
 
 #include <asm/sn/pci/pciba.h>
 
-/* grab an unused space code for "User DMA" space */
-#ifndef	PCIBA_SPACE_UDMA
-#define	PCIBA_SPACE_UDMA	(14)
+
+MODULE_DESCRIPTION("User mode PCI interface");
+MODULE_AUTHOR("Chad Talbott");
+
+
+#undef DEBUG_PCIBA
+/* #define DEBUG_PCIBA */
+
+#undef TRACE_PCIBA
+/* #define TRACE_PCIBA */
+
+#if defined(DEBUG_PCIBA)
+#  define DPRINTF(x...) printk(KERN_DEBUG x)
+#else
+#  define DPRINTF(x...)
 #endif
 
-#if DEBUG_REFCT
-extern int		hwgraph_vertex_refct(vertex_hdl_t);
+#if defined(TRACE_PCIBA)
+#  if defined(__GNUC__)
+#    define TRACE()	printk(KERN_DEBUG "%s:%d:%s\n", \
+			       __FILE__, __LINE__, __FUNCTION__)
+#  else
+#    define TRACE()	printk(KERN_DEBUG "%s:%d\n", __LINE__, __FILE__)
+#  endif
+#else
+#  define TRACE()
 #endif
-extern int		pci_user_dma_max_pages;
 
-#define NEW(ptr)	(ptr = kmem_zalloc(sizeof (*(ptr)), KM_SLEEP))
-#define DEL(ptr)	(kfree(ptr))
 
-/* Oops -- no standard "pci address" type! */
-typedef uint64_t        pciaddr_t;
+typedef enum { failure, success } status;
+typedef enum { false, true } boolean;
 
-/* ================================================================
- *            driver types
- */
-typedef struct pciba_slot_s *pciba_slot_t;
-typedef struct pciba_comm_s *pciba_comm_t;
-typedef struct pciba_soft_s *pciba_soft_t;
-typedef struct pciba_map_s *pciba_map_t, **pciba_map_h;
-typedef struct pciba_dma_s *pciba_dma_t, **pciba_dma_h;
-typedef struct pciba_bus_s *pciba_bus_t;
-
-#define	TRACKED_SPACES	16
-struct pciba_comm_s {
-    devfs_handle_t	    conn;
-    pciba_bus_t             bus;
-    int			    refct;
-    pciba_soft_t	    soft[TRACKED_SPACES][2];
-    struct semaphore        lock;
-    pciba_dma_t             dmap;
+
+/* major data structures:
+
+   struct node_data -
+   
+   	one for each file registered with devfs.  contains everything
+   	that any file's fops would need to know about.
+
+   struct dma_allocation -
+
+   	a single DMA allocation.  only the 'dma' nodes care about
+   	these.  they are there primarily to allow the driver to look
+   	up the kernel virtual address of dma buffers allocated by
+   	pci_alloc_consistent, as the application is only given the
+   	physical address (to program the device's dma, presumably) and
+   	cannot supply the kernel virtual address when freeing the
+   	buffer.
+
+	it's also useful to maintain a list of buffers allocated
+	through a specific node to allow some sanity checking by this
+	driver.  this prevents (for example) a broken application from
+	freeing buffers that it didn't allocate, or buffers allocated
+	on another node.
+   
+   global_node_list -
+
+   	a list of all nodes allocated.  this allows the driver to free
+   	all the memory it has 'kmalloc'd in case of an error, or on
+   	module removal.
+
+   global_dma_list -
+
+        a list of all dma buffers allocated by this driver.  this
+	allows the driver to 'pci_free_consistent' all buffers on
+	module removal or error.
+
+*/
+
+
+struct node_data {
+	/* flat list of all the device nodes.  makes it easy to free
+	   them all when we're unregistered */
+	struct list_head global_node_list;
+	devfs_handle_t devfs_handle;
+
+	void (* cleanup)(struct node_data *);
+
+	union {
+		struct {
+			struct pci_dev * dev;
+			struct list_head dma_allocs;
+			boolean mmapped;
+		} dma;
+		struct {
+			struct pci_dev * dev;
+			u32 saved_rom_base_reg;
+			boolean mmapped;
+		} rom;
+		struct {
+			struct resource * res;
+		} base;
+		struct {
+			struct pci_dev * dev;
+		} config;
+	} u;
 };
 
-/* pciba_soft: device_info() for all openables */
-struct pciba_soft_s {
-    pciba_comm_t	    comm;
-    devfs_handle_t          vhdl;
-    int			    refct;
-    pciio_space_t           space;
-    size_t                  size;
-    pciio_space_t           iomem;
-    pciaddr_t               base;
-    unsigned		    flags;
+struct dma_allocation {
+	struct list_head list;
+
+	dma_addr_t handle;
+	void * va;
+	size_t size;
 };
 
-#define	pciba_soft_get(v)	(pciba_soft_t)hwgraph_fastinfo_get(v)
-#define	pciba_soft_set(v,i)	hwgraph_fastinfo_set(v,(arbitrary_info_t)(i))
 
-#define	pciba_soft_lock(soft)	down(&soft->comm->lock)
-#define	pciba_soft_unlock(soft)	up(&soft->comm->lock)
+static LIST_HEAD(global_node_list);
+static LIST_HEAD(global_dma_list);
 
-/* pciba_map: data describing a mapping.
- * (ie. a user mmap request)
- */
-struct pciba_map_s {
-    pciba_map_t             next;
-#ifdef LATER
-    uthread_t              *uthread;
-#endif
-    __psunsigned_t          handle;
-    uvaddr_t                uvaddr;
-    size_t                  size;
-    pciio_piomap_t          map;
-    pciio_space_t           space;
-    pciaddr_t               base;
-    unsigned		    flags;
-};
 
-/* pciba_dma: data describing a DMA mapping.
- */
-struct pciba_dma_s {
-    pciba_dma_t             next;
-    iopaddr_t               paddr;	/* starting phys addr */
-    caddr_t                 kaddr;	/* starting kern addr */
-    pciio_dmamap_t          map;	/* mapping resources (ugh!) */
-    pciaddr_t               daddr;	/* starting pci addr */
-    size_t                  pages;	/* size of block in pages */
-    size_t                  bytes;	/* size of block in bytes */
-    __psunsigned_t          handle;	/* mapping handle */
+/* module entry points */
+int __init pciba_init(void);
+void __exit pciba_exit(void);
+
+static status __init register_with_devfs(void);
+static void __exit unregister_with_devfs(void);
+
+static status __init register_pci_device(devfs_handle_t device_dir_handle,
+					 struct pci_dev * dev);
+
+/* file operations */
+static int generic_open(struct inode * inode, struct file * file);
+static int rom_mmap(struct file * file, struct vm_area_struct * vma);
+static int rom_release(struct inode * inode, struct file * file);
+static int base_mmap(struct file * file, struct vm_area_struct * vma);
+static int config_ioctl(struct inode * inode, struct file * file, 
+			unsigned int cmd, 
+			unsigned long arg);
+static int dma_ioctl(struct inode * inode, struct file * file, 
+		     unsigned int cmd, 
+		     unsigned long arg);
+static int dma_mmap(struct file * file, struct vm_area_struct * vma);
+
+/* support routines */
+static int mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va);
+static int mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va);
+
+#ifdef DEBUG_PCIBA
+static void dump_nodes(struct list_head * nodes);
+static void dump_allocations(struct list_head * dalp);
+#endif
+
+/* file operations for each type of node */
+static struct file_operations rom_fops = {
+	owner:		THIS_MODULE,
+	mmap:		rom_mmap,
+	open:		generic_open,
+	release:	rom_release
 };
+ 
 
-/* pciba_bus: common bus info for all openables
- * descended from the same master vertex.
- */
-struct pciba_bus_s {
-    struct semaphore        lock;
-    pciba_map_t             maps;	/* stack of mappings */
-    int			    refct;
+static struct file_operations base_fops = {
+	owner:		THIS_MODULE,
+	mmap:		base_mmap,
+	open:		generic_open
 };
 
-#define	pciba_bus_lock(bus)	down(&bus->lock)
-#define	pciba_bus_unlock(bus)	up(&bus->lock)
 
-typedef union ioctl_arg_buffer_u {
-    char                    data[IOCPARM_MASK + 1];
-    uint8_t                 uc;
-    uint16_t                us;
-    uint32_t                ui;
-    uint64_t                ud;
-    caddr_t                 ca;
-#if ULI
-    struct uliargs          uli;
-    struct uliargs32	    uli32;
-#endif
-} ioctl_arg_buffer_t;
+static struct file_operations config_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		config_ioctl,
+	open:		generic_open
+};	
 
-/* ================================================================
- *            driver variables
- */
-char                   *pciba_mversion = "mload version 7.0";
-int                     pciba_devflag = 0x1 |
-                                        0x200 |
-                                        0x400;
+static struct file_operations dma_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		dma_ioctl,
+	mmap:		dma_mmap,
+	open:		generic_open
+};	
 
-/* this counts the reasons why we can not
- * currently unload this driver.
- */
-atomic_t                pciba_prevent_unload = ATOMIC_INIT(0);
 
-#if DEBUG_PCIBA
-static struct reg_values space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIBA_SPACE_UDMA, "UDMA"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
+module_init(pciba_init);
+module_exit(pciba_exit);
+
 
-static struct reg_desc  space_desc[] =
+int __init
+pciba_init(void)
 {
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-#endif
+	TRACE();
 
-char                    pciba_edge_lbl_base[] = "base";
-char                    pciba_edge_lbl_cfg[] = "config";
-char                    pciba_edge_lbl_dma[] = "dma";
-char                    pciba_edge_lbl_intr[] = "intr";
-char                    pciba_edge_lbl_io[] = "io";
-char                    pciba_edge_lbl_mem[] = "mem";
-char                    pciba_edge_lbl_rom[] = "rom";
-char                   *pciba_edge_lbl_win[6] =
-{"0", "1", "2", "3", "4", "5"};
-
-#define	PCIBA_EDGE_LBL_BASE	pciba_edge_lbl_base
-#define	PCIBA_EDGE_LBL_CFG	pciba_edge_lbl_cfg
-#define	PCIBA_EDGE_LBL_DMA	pciba_edge_lbl_dma
-#define	PCIBA_EDGE_LBL_INTR	pciba_edge_lbl_intr
-#define	PCIBA_EDGE_LBL_IO	pciba_edge_lbl_io
-#define	PCIBA_EDGE_LBL_MEM	pciba_edge_lbl_mem
-#define	PCIBA_EDGE_LBL_ROM	pciba_edge_lbl_rom
-#define	PCIBA_EDGE_LBL_WIN(n)	pciba_edge_lbl_win[n]
-
-#define	PCIBA_EDGE_LBL_FLIP	pciba_edge_lbl_flip
-
-static char             pciba_info_lbl_bus[] = "pciba_bus";
-
-#define	PCIBA_INFO_LBL_BUS	pciba_info_lbl_bus
-
-struct file_operations pciba_fops = {
-	owner:	THIS_MODULE,
-	llseek: NULL,
-	read: NULL,
-	write: NULL,
-	readdir: NULL,
-	poll: NULL,
-	ioctl: NULL,
-	mmap: NULL,
-	open: NULL,
-	flush: NULL,
-	release: NULL,
-	fsync: NULL,
-	fasync: NULL,
-	lock: NULL,
-	readv: NULL,
-	writev: NULL
-};
-	
-/* ================================================================
- *            function table of contents
- */
+	if (register_with_devfs() == failure)
+		return 1; /* failure */
 
-void                    pciba_init(void);
-int                     pciba_attach(devfs_handle_t);
+	printk("PCIBA (a user mode PCI interface) initialized.\n");
 
-static void		pciba_sub_attach(pciba_comm_t,
-					 pciio_space_t, pciio_space_t, pciaddr_t,
-					 devfs_handle_t, devfs_handle_t, char *);
-
-static pciba_bus_t      pciba_find_bus(devfs_handle_t, int);
-#ifdef LATER
-static void             pciba_map_push(pciba_bus_t, pciba_map_t);
-static pciba_map_t      pciba_map_pop_hdl(pciba_bus_t, __psunsigned_t);
-static void             pciba_sub_detach(devfs_handle_t, char *);
-static pciio_iter_f     pciba_unload_me;
-#endif
+	return 0; /* success */
+}
 
-int                     pciba_unload(void);
-int                     pciba_unreg(void);
-int                     pciba_detach(devfs_handle_t);
-
-int                     pciba_open(dev_t *, int, int, struct cred *);
-int                     pciba_close(dev_t);
-int                     pciba_read(dev_t, cred_t *);
-int                     pciba_write(dev_t, cred_t *);
-int                     pciba_ioctl(dev_t, int, void *, int, cred_t *, int *);
-
-int                     pciba_map(dev_t, vhandl_t *, off_t, size_t, uint32_t);
-int                     pciba_unmap(dev_t, vhandl_t *);
-
-#if ULI
-void                    pciba_clearuli(struct uli *);
-static intr_func_f      pciba_intr;
-#endif /* Undef as it gets implemented */
 
-/* ================================================================
- *            driver load, register, and setup
- */
-void
-pciba_init(void)
+void __exit
+pciba_exit(void)
 {
+	TRACE();
 
-	/*
-	 * What do we need to do here?
-	 */
-#if DEBUG_PCIBA
-    printk("pciba_init()\n");
-#endif
+	/* FIXME: should also free all that memory that we allocated
+           ;) */
+	unregister_with_devfs();
 }
 
-#ifdef LATER
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-void
-pciba_timeout(void *arg1, void *arg2)
-{
-    struct semaphore       *semap = (sema_t *) arg1;
-    unsigned long          *cvalp = (unsigned long *) arg2;
-
-    if (cvalp)
-	cvalp[0] = RAW_COUNT();
-    if (semap)
-	up(semap);
-}
-
-volatile unsigned long  cNval[1];
-struct semaphore        tsema;
-
-void
-pciba_timeout_test(void)
-{
-    unsigned long           c0val, cval;
-    toid_t                  tid;
-
-    extern void             hwg_hprint(unsigned long, char *);
-
-    sema_init(&tsema, 0);
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 1, (void *) cNval);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_ALERT("pciba: one-tick timeout did not happen in a second\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(1)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, 2, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(2)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, HZ, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(HZ)");
-
-    printk("verifying untimeout() cancells ...\n");
-    cNval[0] = 0;
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 2, (void *) cNval);
-    untimeout(tid);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval != 0) {
-	PRINT_ALERT("pciba: unable to cancel two-tick timeout\n");
-	cval -= c0val;
-	hwg_hprint(cval, "CANCELLED timeout(2)");
-    }
-}
-#endif
 
-int
-pciba_reg(void)
+# if 0
+static void __exit
+free_nodes(void)
 {
-#if DEBUG_PCIBA
-    printk("pciba_reg()\n");
-#endif
-    pciio_driver_register(-1, -1, "pciba_", 0);
-
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-    printk("%s %d\n", __FUNCTION__, __LINE__);
-pciba_timeout_test();
-#endif
+	struct node_data * nd;
+	
+	TRACE();
 
-#if DEBUG_REFCT
-    {
-	char	       *cname = "pciba";
-	char	       *dname = "ptv";
-	char           *cpath0 = "node/xtalk/15";
-	char           *uname0 = "0";
-	char           *cpath1 = "node/xtalk/13";
-	char           *uname1 = "1";
-	devfs_handle_t conn;
-	devfs_handle_t conv;
-	devfs_handle_t vhdl;
-	int		ret;
-
-	printk("pciba refct tests:\n");
-
-#define	SHOWREF(vhdl,func)	printk("ref=%d\t%s\t(%d) %v\n", hwgraph_vertex_refct(vhdl), #func, vhdl, vhdl);
-
-	if (GRAPH_SUCCESS != (ret = hwgraph_path_add(hwgraph_root, cname, &conv)))
-	    printk("\tunable to create conv (ret=%d)\n", ret);
-	else {						SHOWREF(conv, hwgraph_path_add);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname0)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname0, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname1)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname1, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname0, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname0, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname1, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname1, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(hwgraph_root, cname, NULL)))
-		printk("\tunable to remove edge %v/%s (ret=%d)\n", hwgraph_root, cname, ret);
-	    else				SHOWREF(conv, hwgraph_edge_remove);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conv)))
-		printk("unable to unref %v\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_unref);
-	    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(conv)))
-		printk("\tvertex %d destroyed OK\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_destroy);
+	list_for_each(nd, &node_list) {
+		kfree(list_entry(nd, struct nd, node_list));
 	}
-    }
-#endif
-
-    return 0;
 }
-
 #endif
-int
-pciba_attach(devfs_handle_t hconn)
-{
-#if defined(PCIIO_SLOT_NONE)
-    pciio_info_t            info = pciio_info_get(hconn);
-    pciio_slot_t            slot = pciio_info_slot_get(info);
-#endif
-    pciba_comm_t	    comm;
-    pciba_bus_t             bus;
-    int                     ht;
-    devfs_handle_t	    hbase;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
-    int                     win;
-    int                     wins;
-    pciio_space_t           space;
-    pciaddr_t               base;
 
-    int                     iwins;
-    int                     mwins;
 
-#if DEBUG_PCIBA
-    printk("pciba_attach(%p)\n", hconn);
-#endif
+static devfs_handle_t pciba_devfs_handle;
 
-    /* Pick up "dualslot guest" vertex,
-     * which gets all functionality except
-     * config space access.
-     */
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(hconn, ".guest", &gconn)) ||
-	(hconn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    bus = pciba_find_bus(hconn, 1);
-    bus->refct ++;
-
-    /* set up data common to all pciba openables
-     * on this connection point.
-     */
-    NEW(comm);
-    comm->conn = hconn;
-    comm->bus = bus;
-    comm->refct = 0;
-    sema_init(&comm->lock, 1);
 
-#if !defined(PCIIO_SLOT_NONE)
-    if (bus->refct == 1)
-#else
-    if (slot == PCIIO_SLOT_NONE)
-#endif
-    {
-	pciio_info_t            pciio_info;
-	devfs_handle_t          master;
-
-	pciio_info = pciio_info_get(hconn);
-	master = pciio_info_master_get(pciio_info);
-
-	pciba_sub_attach(comm, PCIIO_SPACE_IO, PCIIO_SPACE_IO, 0, master, master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_attach(comm, PCIIO_SPACE_MEM, PCIIO_SPACE_MEM, 0, master, master, PCIBA_EDGE_LBL_MEM);
-#if defined(PCIIO_SLOT_NONE)
-	return 0;
-#endif
-    }
+#if !defined(CONFIG_IA64_SGI_SN1)
 
-    ht = 0x7F & pciio_config_get(hconn, PCI_CFG_HEADER_TYPE, 1);
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
+	char devfs_path[40];
 
-    wins = ((ht == 0x00) ? 6 :
-	    (ht == 0x01) ? 2 :
-	    0);
-
-    mwins = iwins = 0;
-
-    hbase = GRAPH_VERTEX_NONE;
-    gbase = GRAPH_VERTEX_NONE;
-
-    for (win = 0; win < wins; win++) {
-
-	base = pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win), 4);
-	if (base & 1) {
-	    space = PCIIO_SPACE_IO;
-	    base &= 0xFFFFFFFC;
-	} else if ((base & 7) == 4) {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	    base |= ((pciaddr_t) pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win + 1), 4)) << 32;
-	} else {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	}
+	TRACE();
 
-	if (!base)
-	    break;
+	pciba_devfs_handle = devfs_mk_dir(NULL, "pci", NULL);
+	if (pciba_devfs_handle == NULL)
+		return failure;
 
-#if PCIBA_ALIGN_CHECK
-	if (base & (_PAGESZ - 1)) {
-#if DEBUG_PCIBA
-	    PRINT_WARNING("%p pciba: BASE%d not page aligned!\n"
-		    "\tmmap this window at offset 0x%x via \".../pci/%s\"\n",
-		    hconn, win, base,
-		    (space == PCIIO_SPACE_IO) ? "io" : "mem");
-#endif
-	    continue;			/* next window */
-	}
-#endif
+	/* FIXME: don't forget /dev/pci/mem & /dev/pci/io */
+
+	pci_for_each_dev(dev) {
+		sprintf(devfs_path, "%02x/%02x.%x",
+			dev->bus->number,
+			PCI_SLOT(dev->devfn),
+			PCI_FUNC(dev->devfn));
+    
+		device_dir_handle =
+			devfs_mk_dir(pciba_devfs_handle, devfs_path, NULL);
+		if (device_dir_handle == NULL)
+			return failure;
 
-	if ((hbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(hconn, PCIBA_EDGE_LBL_BASE, &hbase)) ||
-	     (hbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	if ((gconn != GRAPH_VERTEX_NONE) &&
-	    (gbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(gconn, PCIBA_EDGE_LBL_BASE, &gbase)) ||
-	     (gbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hbase, gbase, PCIBA_EDGE_LBL_WIN(win));
-
-	if (space == PCIIO_SPACE_IO) {
-	    if (!iwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_IO);
-	    }
-	} else {
-	    if (!mwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_MEM);
-	    }
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-	if ((base & 7) == 4)
-	    win++;
-    }
-
-    pciba_sub_attach(comm, PCIIO_SPACE_CFG, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_attach(comm, PCIBA_SPACE_UDMA, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_DMA);
-#if ULI
-    pciba_sub_attach(comm, PCIIO_SPACE_NONE, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_INTR);
-#endif
+	return success;
+}
 
-    /* XXX should ignore if device is an IOC3 */
-    if (ht == 0x01)
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM+8, 4);
-    else
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM, 4);
-
-    base &= 0xFFFFF000;
-
-    if (base) {
-	if (base & (_PAGESZ - 1))
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING("%v pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
 #else
-	    PRINT_WARNING("0x%x pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
-#endif
-	pciba_sub_attach(comm, PCIIO_SPACE_ROM, PCIIO_SPACE_MEM, base, hconn, gconn, PCIBA_EDGE_LBL_ROM);
-    }
 
-#if !FICUS	/* FICUS shorts the refct by one on path_add */
-    if (hbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(hbase);
+extern devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
 
-    if (gbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(gbase);
-#endif
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
 
-    return 0;
-}
+	TRACE();
 
-static void
-pciba_sub_attach2(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t from,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    char		nbuf[128];
-    pciba_soft_t            soft;
-    devfs_handle_t	handle = NULL;
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-#if DEBUG_PCIBA
-    printk("pciba_sub_attach2 %p/%s %p at %p[%x]\n",
-	   from, name, space, space_desc, iomem, space_desc, base, from, name);
-#endif
+	/* FIXME: don't forget /dev/.../pci/mem & /dev/.../pci/io */
 
-    if (space < TRACKED_SPACES)
-	if ((soft = comm->soft[space][bigend]) != NULL) {
-	    soft->refct ++;
-	    hwgraph_edge_add(from, soft->vhdl, name);
-	    return;
+	pci_for_each_dev(dev) {
+		device_dir_handle = devfn_to_vertex(dev->bus->number,
+						    dev->devfn);
+		if (device_dir_handle == NULL)
+			return failure;
+	
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-    NEW(soft);
-    if (!soft)
-	return;
-
-    soft->comm = comm;
-    soft->space = space;
-    soft->size = 0;
-    soft->iomem = iomem;
-    soft->base = base;
-    soft->refct = 1;
-
-    if (space == PCIIO_SPACE_NONE)
-	soft->flags = 0;
-    else if (bigend)
-	soft->flags = PCIIO_BYTE_STREAM;
-    else
-	soft->flags = PCIIO_WORD_VALUES;
-
-    handle = hwgraph_register(from, name,
-		0, DEVFS_FL_AUTO_DEVNUM,
-		0, 0,
-		S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-		&pciba_fops, NULL);
-    soft->vhdl = handle;
-    pciba_soft_set(soft->vhdl, soft);
-    if (space < TRACKED_SPACES)
-	comm->soft[space][bigend] = soft;
-    comm->refct ++;
+	return success;
 }
 
-static void
-pciba_sub_attach1(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t hfrom,
-		  devfs_handle_t gfrom,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    pciba_sub_attach2(comm, space, iomem, base, hfrom, name, suf, bigend);
-    if ((gfrom != GRAPH_VERTEX_NONE) && (gfrom != hfrom))
-	pciba_sub_attach2(comm, space, iomem, base, gfrom, name, suf, bigend);
-}
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+static void __exit
+unregister_with_devfs(void)
+{
+	struct list_head * lhp;
+	struct node_data * nd;
+	
+	TRACE();
+
+	list_for_each(lhp, &global_node_list) {
+		nd = list_entry(lhp, struct node_data, global_node_list);
+		devfs_unregister(nd->devfs_handle);
+	}
 
-static void
-pciba_sub_attach(pciba_comm_t comm,
-		 pciio_space_t space,
-		 pciio_space_t iomem,
-		 pciaddr_t base,
-		 devfs_handle_t hfrom,
-		 devfs_handle_t gfrom,
-		 char *name)
-{
-    pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, NULL, 0);
-    if (iomem != PCIIO_SPACE_NONE) {
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_le", 0);
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_be", 1);
-    }
 }
 
-#ifdef LATER
-static void
-pciba_reload_me(devfs_handle_t pconn_vhdl)
+
+struct node_data * new_node(void)
 {
-    devfs_handle_t            vhdl;
+	struct node_data * node;
+	
+	TRACE();
+	
+	node = kmalloc(sizeof(struct node_data), GFP_KERNEL);
+	if (node == NULL)
+		return NULL;
+	list_add(&node->global_node_list, &global_node_list);
+	return node;
+}
 
-#if DEBUG_PCIBA
-    printf("pciba_reload_me(%v)\n", pconn_vhdl);
-#endif
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &vhdl))
-	return;
+void dma_cleanup(struct node_data * dma_node)
+{
+	TRACE();
 
-    hwgraph_vertex_unref(vhdl);
+	/* FIXME: should free these allocations */
+#ifdef DEBUG_PCIBA
+	dump_allocations(&dma_node->u.dma.dma_allocs);
+#endif
+	devfs_unregister(dma_node->devfs_handle);
 }
-#endif	/* LATER */
 
-static                  pciba_bus_t
-pciba_find_bus(devfs_handle_t pconn, int cflag)
+
+void init_dma_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
 {
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    pciba_bus_t             bus;
+	TRACE();
 
-    pciio_info = pciio_info_get(pconn);
-    master = pciio_info_master_get(pciio_info);
+	node->devfs_handle = dh;
+	node->u.dma.dev = dev;
+	node->cleanup = dma_cleanup;
+	INIT_LIST_HEAD(&node->u.dma.dma_allocs);
+}
 
-    if (GRAPH_SUCCESS ==
-	hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo))
-	return (pciba_bus_t) ainfo;
 
-    if (!cflag)
-	return 0;
+void rom_cleanup(struct node_data * rom_node)
+{
+	TRACE();
 
-    NEW(bus);
-    if (!bus)
-	return 0;
+	if (rom_node->u.rom.mmapped)
+		pci_write_config_dword(rom_node->u.rom.dev,
+				       PCI_ROM_ADDRESS,
+				       rom_node->u.rom.saved_rom_base_reg);
+	devfs_unregister(rom_node->devfs_handle);
+}
 
-    sema_init(&bus->lock, 1);
 
-    ainfo = (arbitrary_info_t) bus;
-    hwgraph_info_add_LBL(master, PCIBA_INFO_LBL_BUS, ainfo);
-    hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
-    if ((pciba_bus_t) ainfo != bus)
-	DEL(bus);
-#if DEBUG_PCIBA
-    else
-	printk("pcbia_find_bus: new bus at %p\n", master);
-#endif
+void init_rom_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
+{
+	TRACE();
 
-    return (pciba_bus_t) ainfo;
+	node->devfs_handle = dh;
+	node->u.rom.dev = dev;
+	node->cleanup = rom_cleanup;
+	node->u.rom.mmapped = false;
 }
 
-#ifdef LATER
-static void
-pciba_map_push(pciba_bus_t bus, pciba_map_t map)
+
+static status __init
+register_pci_device(devfs_handle_t device_dir_handle, struct pci_dev * dev)
 {
-#if DEBUG_PCIBA
-    printk("pciba_map_push(bus=0x%x, map=0x%x, hdl=0x%x\n",
-	   bus, map, map->handle);
-#endif
-    pciba_bus_lock(bus);
-    map->next = bus->maps;
-    bus->maps = map;
-    pciba_bus_unlock(bus);
-}
-
-static                  pciba_map_t
-pciba_map_pop_hdl(pciba_bus_t bus, __psunsigned_t handle)
-{
-    pciba_map_h             hdl;
-    pciba_map_t             map;
-
-    pciba_bus_lock(bus);
-    for (hdl = &bus->maps; map = *hdl; hdl = &map->next)
-	if (map->handle == handle) {
-	    *hdl = map->next;
-	    break;
+	struct node_data * nd;
+	char devfs_path[20];
+	devfs_handle_t node_devfs_handle;
+	int ri;
+
+	TRACE();
+
+
+	/* register nodes for all the device's base address registers */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (pci_resource_len(dev, ri) != 0) {
+			sprintf(devfs_path, "base/%d", ri);
+			if (devfs_register(device_dir_handle, devfs_path,
+					   DEVFS_FL_NONE,
+					   0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+		}
 	}
-    pciba_bus_unlock(bus);
-#if DEBUG_PCIBA
-    printk("pciba_map_pop_va(bus=0x%x, handle=0x%x) returns map=0x%x\n",
-	   bus, handle, map);
+	
+	/* register a node corresponding to the first MEM resource on
+           the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_MEM &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "mem",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* also register a node corresponding to the first IO resource
+           on the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_IO &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "io",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* register a node corresponding to the device's ROM resource,
+           if present */
+	if (pci_resource_len(dev, PCI_ROM_RESOURCE) != 0) {
+		nd = new_node();
+		if (nd == NULL)
+			return failure;
+		node_devfs_handle = devfs_register(device_dir_handle, "rom",
+						   DEVFS_FL_NONE, 0, 0,
+						   S_IFREG | S_IRUSR,
+						   &rom_fops, nd);
+		if (node_devfs_handle == NULL)
+			return failure;
+		init_rom_node(nd, dev, node_devfs_handle);
+	}
+
+	/* register a node that allows ioctl's to read and write to
+           the device's config space */
+	if (devfs_register(device_dir_handle, "config", DEVFS_FL_NONE,
+			   0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			   &config_fops, dev) == NULL)
+		return failure;
+
+
+	/* finally, register a node that allows ioctl's to allocate
+           and free DMA buffers, as well as memory map those
+           buffers. */
+	nd = new_node();
+	if (nd == NULL)
+		return failure;
+	node_devfs_handle =
+		devfs_register(device_dir_handle, "dma", DEVFS_FL_NONE,
+			       0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			       &dma_fops, nd);
+	if (node_devfs_handle == NULL)
+		return failure;
+	init_dma_node(nd, dev, node_devfs_handle);
+
+#ifdef DEBUG_PCIBA
+	dump_nodes(&global_node_list);
 #endif
-    return map;
+	
+	return success;
 }
 
-/* ================================================================
- *            driver teardown, unregister and unload
- */
-int
-pciba_unload(void)
-{
-#if DEBUG_PCIBA
-    printk("pciba_unload()\n");
-#endif
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+static int
+generic_open(struct inode * inode, struct file * file)
+{
+	TRACE();
 
-    pciio_iterate("pciba_", pciba_unload_me);
+	/* FIXME: should check that they're not trying to open the ROM
+           writable */
 
-    return 0;
+	return 0; /* success */
 }
 
-int
-pciba_unreg(void)
+
+static int
+rom_mmap(struct file * file, struct vm_area_struct * vma)
 {
+	unsigned long pci_pa;
+	struct node_data * nd;
 
-#if DEBUG_PCIBA
-    printf("pciba_unreg()\n");
-#endif
+	TRACE();
+
+	nd = (struct node_data * )file->private_data;
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+	pci_pa = pci_resource_start(nd->u.rom.dev, PCI_ROM_RESOURCE);
 
-    pciio_driver_unregister("pciba_");
-    return 0;
+	if (!nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = true;
+		DPRINTF("Enabling ROM address decoder.\n");
+		DPRINTF(
+"rom_mmap: FIXME: some cards do not allow both ROM and memory addresses to\n"
+"rom_mmap: FIXME: be enabled simultaneously, as they share a decoder.\n");
+		pci_read_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				      &nd->u.rom.saved_rom_base_reg);
+		DPRINTF("ROM base address contains %x\n",
+			nd->u.rom.saved_rom_base_reg);
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg |
+				       PCI_ROM_ADDRESS_ENABLE);
+	}
+	
+	return mmap_pci_address(vma, pci_pa);
 }
 
-int
-pciba_detach(devfs_handle_t conn)
+
+static int
+rom_release(struct inode * inode, struct file * file)
 {
-    devfs_handle_t          base;
-    pciba_bus_t             bus;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
+	struct node_data * nd;
 
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    int			    ret;
+	TRACE();
 
-#if DEBUG_PCIBA
-    printf("pciba_detach(%v)\n", conn);
-#endif
+	nd = (struct node_data * )file->private_data;
 
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(conn, ".guest", &gconn)) ||
-	(conn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    if (gconn != GRAPH_VERTEX_NONE) {
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_CFG);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_DMA);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_INTR);
-#endif
-	if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &gbase)) {
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_MEM);
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_IO);
-	    pciba_sub_detach(gbase, "0");
-	    pciba_sub_detach(gbase, "1");
-	    pciba_sub_detach(gbase, "2");
-	    pciba_sub_detach(gbase, "3");
-	    pciba_sub_detach(gbase, "4");
-	    pciba_sub_detach(gbase, "5");
-	    hwgraph_vertex_unref(gbase);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(gbase))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-			conn, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-			conn, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(gbase));
-#endif
-	    }
+	if (nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = false;
+		DPRINTF("Disabling ROM address decoder.\n");
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg);
 	}
-    }
+	return 0; /* indicate success */
+}
 
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_DMA);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_INTR);
-#endif
 
-    if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &base)) {
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(base, "0");
-	pciba_sub_detach(base, "1");
-	pciba_sub_detach(base, "2");
-	pciba_sub_detach(base, "3");
-	pciba_sub_detach(base, "4");
-	pciba_sub_detach(base, "5");
-	hwgraph_vertex_unref(base);
-	if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(base))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-		    conn, ret);
-#else
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-		    conn, ret);
-#endif
-#if DEBUG_REFCT
-	    printk("\tretained refct %d\n", hwgraph_vertex_refct(base));
-#endif
-	}
-    }
+static int
+base_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct resource * resource;
 
-    bus = pciba_find_bus(conn, 0);
-    if (bus && !--(bus->refct)) {
+	TRACE();
 
-	pciio_info = pciio_info_get(conn);
+	resource = (struct resource *)file->private_data;
 
-	master = pciio_info_master_get(pciio_info);
+	return mmap_pci_address(vma, resource->start);
+}
 
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_CFG);
-	hwgraph_info_remove_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
 
-#if DEBUG_PCIBA
-	printf("pcbia_detach: DEL(bus) at %v\n", master);
-#endif
-	DEL(bus);
-    } 
+static int
+config_ioctl(struct inode * inode, struct file * file, 
+	     unsigned int cmd, 
+	     unsigned long arg)
+{
+	struct pci_dev * dev;
 
-    return 0;
-}
+	union cfg_data {
+		uint8_t byte;
+		uint16_t word;
+		uint32_t dword;
+	} read_data, write_data;
 
-static void
-pciba_sub_detach1(devfs_handle_t conn,
-		  char *name,
-		  char *suf)
-{
-    devfs_handle_t         vhdl;
-    pciba_soft_t            soft;
-    pciba_comm_t	    comm;
-    int			    ret;
-    char		nbuf[128];
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-    if ((GRAPH_SUCCESS == hwgraph_edge_remove(conn, name, &vhdl)) &&
-	((soft = pciba_soft_get(vhdl)) != NULL)) {
-#if DEBUG_PCIBA
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	prink("pciba_sub_detach(%v,%s)\n", conn, name);
-#else
-	prink("pciba_sub_detach(0x%x,%s)\n", conn, name);
-#endif
-#endif
+	int dir, size, offset;
 
-	hwgraph_vertex_unref(soft->vhdl);
-#if DEBUG_REFCT
-	printk("\tadjusted refct %d (soft ref: %d)\n",
-		hwgraph_vertex_refct(vhdl),
-		soft->refct);
-#endif
-	if (!--(soft->refct)) {
-	    comm = soft->comm;
-	    if (!--(comm->refct)) {
-		DEL(comm);
-	    }
-	    pciba_soft_set(vhdl, 0);
-	    DEL(soft);
-
-	    hwgraph_vertex_unref(vhdl);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(vhdl))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/%s) failed (%d)",
-			conn, name, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/%s) failed (%d)",
-			conn, name, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(vhdl));
-#endif
-	    }
-	}
-    }
-}
+	TRACE();
 
-static void
-pciba_sub_detach(devfs_handle_t conn,
-		 char *name)
-{
-    pciba_sub_detach1(conn, name, "");
-    pciba_sub_detach1(conn, name, "_le");
-    pciba_sub_detach1(conn, name, "_be");
-}
+	DPRINTF("cmd = %x (DIR = %x, TYPE = %x, NR = %x, SIZE = %x)\n", 
+		cmd, 
+		_IOC_DIR(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
+	DPRINTF("arg = %lx\n", arg);
 
-static void
-pciba_unload_me(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t         c_vhdl;
+	dev = (struct pci_dev *)file->private_data;
 
-#if DEBUG_PCIBA
-    printf("pciba_unload_me(%v)\n", pconn_vhdl);
-#endif
+	/* PCIIOCCFG{RD,WR}: read and/or write PCI configuration
+	   space. If both, the read happens first (this becomes a swap
+	   operation, atomic with respect to other updates through
+	   this path).  */
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &c_vhdl))
-	return;
+	dir = _IOC_DIR(cmd);
 
-    hwgraph_vertex_unref(c_vhdl);
-}
+#define do_swap(suffix, type)	 					\
+	do {								\
+		if (dir & _IOC_READ) {					\
+			pci_read_config_##suffix(dev, _IOC_NR(cmd), 	\
+						 &read_data.suffix);	\
+		}							\
+		if (dir & _IOC_WRITE) {					\
+			get_user(write_data.suffix, (type)arg);		\
+			pci_write_config_##suffix(dev, _IOC_NR(cmd), 	\
+						  write_data.suffix);	\
+		}							\
+		if (dir & _IOC_READ) {					\
+			put_user(read_data.suffix, (type)arg);		\
+		}							\
+	} while (0)
 
-/* ================================================================
- *            standard unix entry points
- */
+	size = _IOC_SIZE(cmd);
+	offset = _IOC_NR(cmd);
 
-/*ARGSUSED */
-int
-pciba_open(dev_t *devp, int flag, int otyp, struct cred *crp)
-{
+	DPRINTF("sanity check\n");
+	if (((size > 0) || (size <= 4)) &&
+	    ((offset + size) <= 256) &&
+	    (dir & (_IOC_READ | _IOC_WRITE))) {
 
-#if DEBUG_PCIBA
-    printf("pciba_open(%V)\n", *devp);
-#endif
-    return 0;
+		switch (size)
+		{
+		case 1:
+			do_swap(byte, uint8_t *);
+			break;
+		case 2:
+			do_swap(word, uint16_t *);
+			break;
+		case 4:
+			do_swap(dword, uint32_t *);
+			break;
+		default:
+			DPRINTF("invalid ioctl\n");
+			return -EINVAL;
+		}
+	} else
+		return -EINVAL;
+		
+	return 0;
 }
 
-/*ARGSUSED */
-int
-pciba_close(dev_t dev)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
 
-#if DEBUG_PCIBA
-    printf("pciba_close(%V)\n", dev);
-#endif
-
-    /* if there is pending DMA for this device, hit the
-     * device over the head with a baseball bat and
-     * release the system memory resources.
-     */
-    if (soft && soft->comm->dmap) {
-	pciba_dma_t             next;
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	if (dmap = soft->comm->dmap) {
-	    soft->comm->dmap = 0;
-
-	    pciio_reset(soft->comm->conn);
-
-	    do {
-		if (!dmap->kaddr)
-		    break;
-		if (!dmap->paddr)
-		    break;
-		if (dmap->bytes < NBPP)
-		    break;
-		next = dmap->next;
-		kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-		dmap->paddr = 0;
-		dmap->bytes = 0;
-		DEL(dmap);
-	    } while (dmap = next);
+#ifdef DEBUG_PCIBA
+static void
+dump_allocations(struct list_head * dalp)
+{
+	struct dma_allocation * dap;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, dalp) {
+		dap = list_entry(p, struct dma_allocation, 
+				 list);
+		printk("  handle = %lx, va = %p\n",
+		       dap->handle, dap->va);
 	}
-	pciba_soft_unlock(soft);
-    }
-    return 0;
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_read(dev_t dev, cred_t *crp)
+static void
+dump_nodes(struct list_head * nodes)
 {
-#if DEBUG_PCIBA
-    printf("pciba_read(%V)\n", dev);
-#endif
-
-    return EINVAL;
+	struct node_data * ndp;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, nodes) {
+		ndp = list_entry(p, struct node_data, 
+				 global_node_list);
+		printk("  %p\n", (void *)ndp);
+	}
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_write(dev_t dev, cred_t *crp)
+
+#if 0
+#define NEW(ptr) (ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+
+static void
+test_list(void)
 {
-#if DEBUG_PCIBA
-    printf("pciba_write(%V)\n", dev);
-#endif
+	u64 i;
+	LIST_HEAD(the_list);
 
-    return EINVAL;
+	for (i = 0; i < 5; i++) {
+		struct dma_allocation * new_alloc;
+		NEW(new_alloc);
+		new_alloc->va = (void *)i;
+		new_alloc->handle = 5*i;
+		printk("%d - the_list->next = %lx\n", i, the_list.next);
+		list_add(&new_alloc->list, &the_list);
+	}
+	dump_allocations(&the_list);
 }
-
-/*ARGSUSED */
-int
-pciba_ioctl(dev_t dev, int cmd, void *uarg, int mode, cred_t *crp, int *rvalp)
-{
-    devfs_handle_t          vhdl;
-    pciba_soft_t            soft;
-    pciio_space_t           space;
-    ioctl_arg_buffer_t      arg;
-    int                     psize;
-    int                     err = 0;
-
-#if ULI
-    char		    abi = get_current_abi();
-    pciio_intr_t            intr=0;
-    device_desc_t           desc;
-    cpuid_t                 intrcpu;
-    unsigned                lines;
-    struct uli             *uli = 0;
 #endif
-    unsigned                flags;
-    void                   *kaddr = 0;
-    iopaddr_t               paddr;
-    pciba_dma_h             dmah;
-    pciba_dma_t             dmap = 0;
-    pciio_dmamap_t          dmamap = 0;
-    size_t                  bytes;
-    int                     pages;
-    pciaddr_t               daddr;
-
-#if DEBUG_PCIBA
-    printf("pciba_ioctl(%V,0x%x)\n", dev, cmd);
 #endif
 
-    psize = (cmd >> 16) & IOCPARM_MASK;
-
-#if ULI
-    ASSERT(sizeof(struct uliargs) > 8);	/* prevent CFG access conflict */
-    ASSERT(sizeof(struct uliargs) <= IOCPARM_MASK);
-#endif
 
-    arg.ca = uarg;
+static LIST_HEAD(dma_buffer_list);
 
-    if ((psize > 0) && (cmd & (IOC_OUT | IOC_IN))) {
-	if (psize > sizeof(arg))
-	    err = EINVAL;		/* "bad parameter size */
-	else {
-	    if (cmd & IOC_OUT)
-		bzero(arg.data, psize);
-	    if ((cmd & IOC_IN) &&
-		(copyin(uarg, arg.data, psize) < 0))
-		err = EFAULT;		/* "parameter copyin failed" */
-	}
-    }
-    vhdl = dev_to_vhdl(dev);
-    soft = pciba_soft_get(vhdl);
-    space = soft->space;
-
-    if (err == 0) {
-	err = EINVAL;			/* "invalid ioctl for this vertex" */
-	switch (space) {
-#if ULI
-	case PCIIO_SPACE_NONE:		/* the "intr" vertex */
-	    /* PCIIOCSETULI: set up user interrupts.
-	     */
-	    lines = cmd & 15;
-	    if (ABI_IS_64BIT(abi)) {
-		if (cmd != PCIIOCSETULI(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-	    }
-	    else {
-		struct uliargs uliargs;
-
-		if (cmd != PCIIOCSETULI32(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-		
-		uliargs32_to_uliargs(&arg.uli32, &uliargs);
-		arg.uli = uliargs;
-	    }
-	    desc = device_desc_dup(soft->comm->conn);
-	    device_desc_flags_set(desc, (device_desc_flags_get(desc) |
-					 D_INTR_NOTHREAD));
-	    device_desc_intr_swlevel_set(desc, INTR_SWLEVEL_NOTHREAD_DEFAULT);
-	    device_desc_intr_name_set(desc, "PCIBA");
-	    device_desc_default_set(soft->comm->conn, desc);
-
-	    /* When designating interrupts, the slot number
-	     * is taken from the connection point.
-	     * Bits 0..3 are used to select INTA..INTD; more
-	     * than one bit can be specified. These should
-	     * be constructed using PCIIO_INTR_LINE_[ABCD].
-	     */
-	    intr = pciio_intr_alloc
-		(soft->comm->conn, desc, lines, soft->vhdl);
-	    if (intr == 0) {
-		err = ENOMEM;		/* "insufficient resources" */
-		break;
-	    }
-	    intrcpu = cpuvertex_to_cpuid(pciio_intr_cpu_get(intr));
 
-	    if (err = new_uli(&arg.uli, &uli, intrcpu)) {
-		break;			/* "unable to set up ULI" */
-	    }
-	    atomic_inc(&pciba_prevent_unload);
-
-	    pciio_intr_connect(intr, pciba_intr, uli, (void *) 0);
-
-	    /* NOTE: don't set the teardown function
-	     * until the interrupt is connected.
-	     */
-	    uli->teardownarg1 = (__psint_t) intr;
-	    uli->teardown = pciba_clearuli;
-
-	    arg.uli.id = uli->index;
-
-	    if (!ABI_IS_64BIT(abi)) {
-		struct uliargs32 uliargs32;
-		uliargs_to_uliargs32(&arg.uli, &uliargs32);
-		arg.uli32 = uliargs32;
-	    }
+static int
+dma_ioctl(struct inode * inode, struct file * file, 
+	  unsigned int cmd, 
+	  unsigned long arg)
+{
+	struct node_data * nd;
+	uint64_t argv;
+	int result;
+	struct dma_allocation * dma_alloc;
+	struct list_head * iterp;
 
-	    err = 0;
-	    break;
-#endif
+	TRACE();
 
-	case PCIBA_SPACE_UDMA:		/* the "dma" vertex */
+	DPRINTF("cmd = %x\n", cmd);
+	DPRINTF("arg = %lx\n", arg);
 
-	    switch (cmd) {
+	nd = (struct node_data *)file->private_data;
 
-	    case PCIIOCDMAALLOC:
-		/* PCIIOCDMAALLOC: allocate a chunk of physical
-		 * memory and set it up for DMA. Return the
-		 * PCI address that gets to it.
-		 * NOTE: this allocates memory local to the
-		 * CPU doing the ioctl, not local to the
-		 * device that will be doing the DMA.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;
-		    break;
-		}
-		/* separate the halves of the incoming parameter */
-		flags = arg.ud >> 32;
-		bytes = arg.ud & 0xFFFFFFFF;
-
-#if DEBUG_PCIBA
-		printf("pciba: user wants 0x%x bytes of DMA, flags 0x%x\n",
-		       bytes, flags);
+#ifdef DEBUG_PCIBA
+	DPRINTF("at dma_ioctl entry\n");
+	dump_allocations(&nd->u.dma.dma_allocs);
 #endif
 
-		/* round up the requested size to the next highest page */
-		pages = (bytes + NBPP - 1) / NBPP;
-
-		/* make sure the requested size is something reasonable */
-		if (pages > pci_user_dma_max_pages) {
-#if DEBUG_PCIBA
-		    printf("pciba: request for too much buffer space\n");
+	switch (cmd) {
+	case PCIIOCDMAALLOC:
+		/* PCIIOCDMAALLOC: allocate a chunk of physical memory
+		   and set it up for DMA. Return the PCI address that
+		   gets to it.  */
+		DPRINTF("case PCIIOCDMAALLOC (%lx)\n", PCIIOCDMAALLOC);
+		
+		if ( (result = get_user(argv, (uint64_t *)arg)) )
+			return result;
+		DPRINTF("argv (size of buffer) = %lx\n", argv);
+
+		dma_alloc = (struct dma_allocation *)
+			kmalloc(sizeof(struct dma_allocation), GFP_KERNEL);
+		if (dma_alloc == NULL)
+			return -ENOMEM;
+
+		dma_alloc->size = (size_t)argv;
+		dma_alloc->va = pci_alloc_consistent(nd->u.dma.dev,
+						     dma_alloc->size,
+						     &dma_alloc->handle);
+		DPRINTF("dma_alloc->va = %p, dma_alloc->handle = %lx\n",
+			dma_alloc->va, dma_alloc->handle);
+		if (dma_alloc->va == NULL) {
+			kfree(dma_alloc);
+			return -ENOMEM;
+		}
+
+		list_add(&dma_alloc->list, &nd->u.dma.dma_allocs);
+		if ( (result = put_user((uint64_t)dma_alloc->handle, 
+				      (uint64_t *)arg)) ) {
+			DPRINTF("put_user failed\n");
+			pci_free_consistent(nd->u.dma.dev, (size_t)argv,
+					    dma_alloc->va, dma_alloc->handle);
+			kfree(dma_alloc);
+			return result;
+		}
+
+#ifdef DEBUG_PCIBA
+		DPRINTF("after insertion\n");
+		dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-		    err = EINVAL;
-		    break;		/* "request for too much buffer space" */
-		}
-		/* "correct" number of bytes */
-		bytes = pages * NBPP;
+		break;
 
-		/* allocate the space */
-		/* XXX- force to same node as the device? */
-		/* XXX- someday, we want to handle user buffers,
-		 *    and noncontiguous pages, but this will
-		 *      require either fancy mapping or handing
-		 *      a list of blocks back to the user. For
-		 *      now, just tell users to allocate a lot of
-		 *      individual single-pages and manage their
-		 *      scatter-gather manually.
-		 */
-		kaddr = kvpalloc(pages, VM_DIRECT | KM_NOSLEEP, 0);
-		if (kaddr == 0) {
-#if DEBUG_PCIBA
-		    printf("pciba: unable to get %d contiguous pages\n", pages);
-#endif
-		    err = EAGAIN;	/* "insufficient resources, try again later" */
-		    break;
-		}
-#if DEBUG_PCIBA
-		printf("pciba: kaddr is 0x%x\n", kaddr);
-#endif
-		paddr = kvtophys(kaddr);
+	case PCIIOCDMAFREE:
+		DPRINTF("case PCIIOCDMAFREE (%lx)\n", PCIIOCDMAFREE);
 
-		daddr = pciio_dmatrans_addr
-		    (soft->comm->conn, 0, paddr, bytes, flags);
-		if (daddr == 0) {	/* "no direct path available" */
-#if DEBUG_PCIBA
-		    printf("pciba: dmatrans failed, trying dmamap\n");
-#endif
-		    dmamap = pciio_dmamap_alloc
-			(soft->comm->conn, 0, bytes, flags);
-		    if (dmamap == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: unable to allocate dmamap\n");
+		if ( (result = get_user(argv, (uint64_t *)arg)) ) {
+			DPRINTF("get_user failed\n");
+			return result;
+		}
+
+		DPRINTF("argv (physical address of DMA buffer) = %lx\n", argv);
+		list_for_each(iterp, &nd->u.dma.dma_allocs) {
+			struct dma_allocation * da =
+				list_entry(iterp, struct dma_allocation, list);
+			if (da->handle == argv) {
+				pci_free_consistent(nd->u.dma.dev, da->size,
+						    da->va, da->handle);
+				list_del(&da->list);
+				kfree(da);
+#ifdef DEBUG_PCIBA
+				DPRINTF("after deletion\n");
+				dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-			err = ENOMEM;
-			break;		/* "out of mapping resources" */
-		    }
-		    daddr = pciio_dmamap_addr
-			(dmamap, paddr, bytes);
-		    if (daddr == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: dmamap_addr failed\n");
-#endif
-			err = EINVAL;
-			break;		/* "can't get there from here" */
-		    }
-		}
-#if DEBUG_PCIBA
-		printf("pciba: daddr is 0x%x\n", daddr);
-#endif
-		NEW(dmap);
-		if (!dmap) {
-		    err = ENOMEM;
-		    break;		/* "no memory available" */
+				return 0; /* success */
+			}
 		}
-		dmap->bytes = bytes;
-		dmap->pages = pages;
-		dmap->paddr = paddr;
-		dmap->kaddr = kaddr;
-		dmap->map = dmamap;
-		dmap->daddr = daddr;
-		dmap->handle = 0;
-
-#if DEBUG_PCIBA
-		printf("pciba: dmap 0x%x contains va 0x%x bytes 0x%x pa 0x%x pages 0x%x daddr 0x%x\n",
-		       dmap, kaddr, bytes, paddr, pages, daddr);
-#endif
+		/* previously allocated dma buffer wasn't found */
+		DPRINTF("attempt to free invalid dma handle\n");
+		return -EINVAL;
 
-		arg.ud = dmap->daddr;
+	default:
+		DPRINTF("undefined ioctl\n");
+		return -EINVAL;
+	}
 
-		err = 0;
-		break;
+	DPRINTF("success\n");
+	return 0;
+}
+		
 
-	    case PCIIOCDMAFREE:
-		/* PCIIOCDMAFREE: Find the chunk of
-		 * User DMA memory, and release its
-		 * resources back to the system.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;	/* "you can't do that" */
-		    break;
-		}
-		if (soft->comm->dmap == NULL) {
-		    err = EINVAL;	/* "no User DMA to free" */
-		    break;
-		}
-		/* find the request. */
-		daddr = arg.ud;
-		err = EINVAL;		/* "block not found" */
-		pciba_soft_lock(soft);
-		for (dmah = &soft->comm->dmap; dmap = *dmah; dmah = &dmap->next) {
-		    if (dmap->daddr == daddr) {
-			if (dmap->handle != 0) {
-			    dmap = 0;	/* don't DEL this dmap! */
-			    err = EINVAL;	/* "please unmap first" */
-			    break;		/* break outa for loop. */
-			}
-			*dmah = dmap->next;
+static int
+dma_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct node_data * nd;
+	struct list_head * iterp;
+	int result;
+	
+	TRACE();
 
-			if (dmamap = dmap->map) {
-			    pciio_dmamap_free(dmamap);
-			    dmamap = 0;	/* don't free it twice! */
+	nd = (struct node_data *)file->private_data;
+	
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
+	DPRINTF("offset = %lx\n", vma->vm_pgoff);
+
+	/* get kernel virtual address for the dma buffer (necessary
+	 * for the mmap). */
+	list_for_each(iterp, &nd->u.dma.dma_allocs) {
+		struct dma_allocation * da =
+			list_entry(iterp, struct dma_allocation, list);
+		/* why does mmap shift its offset argument? */
+		if (da->handle == vma->vm_pgoff << PAGE_SHIFT) {
+			DPRINTF("found dma handle\n");
+			if ( (result = mmap_kernel_address(vma,
+							   da->va)) ) {
+				return result; /* failure */
+			} else {
+				/* it seems like at least one of these
+				   should show up in user land....
+				   I'm missing something */
+				*(char *)da->va = 0xaa;
+				strncpy(da->va, "        Toastie!", da->size);
+				if (put_user(0x18badbeeful,
+					     (u64 *)vma->vm_start))
+					DPRINTF("put_user failed?!\n");
+				return 0; /* success */
 			}
-			kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-			DEL(dmap);
-			dmap = 0;	/* don't link this back into the list! */
-			err = 0;	/* "all done" */
-			break;		/* break outa for loop. */
-		    }
-		}
-		pciba_soft_unlock(soft);
-		break;		/* break outa case PCIIOCDMAFREE: */
-	    }
-	    break;		/* break outa case PCIBA_SPACE_UDMA: */
-
-	case PCIIO_SPACE_CFG:
-
-	    /* PCIIOCCFG{RD,WR}: read and/or write
-	     * PCI configuration space. If both,
-	     * the read happens first (this becomes
-	     * a swap operation, atomic with respect
-	     * to other updates through this path).
-	     *
-	     * Should be *last* IOCTl command checked,
-	     * so other patterns can nip useless codes
-	     * out of the space this decodes.
-	     */
-	    err = EINVAL;
-	    if ((psize > 0) || (psize <= 8) &&
-		(((cmd & 0xFF) + psize) <= 256) &&
-		(cmd & (IOC_IN | IOC_OUT))) {
-
-		uint64_t                rdata;
-		uint64_t                wdata;
-		int                     shft;
-
-		shft = 64 - (8 * psize);
-
-		wdata = arg.ud >> shft;
-
-		pciba_soft_lock(soft);
-
-		if (cmd & IOC_OUT)
-		    rdata = pciio_config_get(soft->comm->conn, cmd & 0xFFFF, psize);
-		if (cmd & IOC_IN)
-		    pciio_config_set(soft->comm->conn, cmd & 0xFFFF, psize, wdata);
 
-		pciba_soft_unlock(soft);
-
-		arg.ud = rdata << shft;
-		err = 0;
-		break;
-	    }
-	    break;
-	}
-    }
-    /* done: come here if all went OK.
-     */
-    if ((err == 0) &&
-	((cmd & IOC_OUT) && (psize > 0)) &&
-	copyout(arg.data, uarg, psize))
-	err = EFAULT;
-
-    /* This gets delayed until after the copyout so we
-     * do not free the dmap on a copyout error, or
-     * alternately end up with a dangling allocated
-     * buffer that the user never got back.
-     */
-    if ((err == 0) && dmap) {
-	pciba_soft_lock(soft);
-	dmap->next = soft->comm->dmap;
-	soft->comm->dmap = dmap;
-	pciba_soft_unlock(soft);
-    }
-    if (err) {
-	/* Things went badly. Clean up.
-	 */
-#if ULI
-	if (intr) {
-	    pciio_intr_disconnect(intr);
-	    pciio_intr_free(intr);
-	}
-	if (uli)
-	    free_uli(uli);
-#endif
-	if (dmap) {
-	    if (dmap->map && (dmap->map != dmamap))
-		pciio_dmamap_free(dmap->map);
-	    DEL(dmap);
+		}
 	}
-	if (dmamap)
-	    pciio_dmamap_free(dmamap);
-	if (kaddr)
-	    kvpfree(kaddr, pages);
-    }
-    return *rvalp = err;
+	DPRINTF("attempt to mmap an invalid dma handle\n");
+	return -EINVAL;
 }
 
-/* ================================================================
- *            mapping support
- */
-
-/*ARGSUSED */
-int
-pciba_map(dev_t dev, vhandl_t *vt,
-	  off_t off, size_t len, uint32_t prot)
-{
-    devfs_handle_t          vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    devfs_handle_t          conn = soft->comm->conn;
-    pciio_space_t           space = soft->space;
-    size_t                  pages = (len + NBPP - 1) / NBPP;
-    pciio_piomap_t          pciio_piomap = 0;
-    caddr_t                 kaddr;
-    pciba_map_t             map;
-    pciba_dma_t             dmap;
-
-#if DEBUG_PCIBA
-    printf("pciba_map(%V,vt=0x%x)\n", dev, vt);
-#endif
 
-    if (space == PCIBA_SPACE_UDMA) {
-	pciba_soft_lock(soft);
+static int
+mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va)
+{
+	unsigned long pci_pa;
 
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next) {
-	    if (off == dmap->daddr) {
-		if (pages != dmap->pages) {
-		    pciba_soft_unlock(soft);
-		    return EINVAL;	/* "size mismatch" */
-		}
-		v_mapphys(vt, dmap->kaddr, dmap->bytes);
-		dmap->handle = v_gethandle(vt);
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: mapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, dmap->handle);
-#endif
-		return 0;
-	    }
-	}
-	pciba_soft_unlock(soft);
-	return EINVAL;			/* "block not found" */
-    }
-    if (soft->iomem == PCIIO_SPACE_NONE)
-	return EINVAL;			/* "mmap not supported" */
-
-    kaddr = (caddr_t) pciio_pio_addr
-	(conn, 0, space, off, len, &pciio_piomap, soft->flags | PCIIO_FIXED );
-
-#if DEBUG_PCIBA
-    printf("pciba: mapped %R[0x%x..0x%x] via map 0x%x to kaddr 0x%x\n",
-	   space, space_desc, off, off + len - 1, pciio_piomap, kaddr);
-#endif
+	TRACE();
 
-    if (kaddr == NULL)
-	return EINVAL;			/* "you can't get there from here" */
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-    NEW(map);
-    if (map == NULL) {
-	if (pciio_piomap)
-	    pciio_piomap_free(pciio_piomap);
-	return ENOMEM;			/* "unable to get memory resources */
-    }
-#ifdef LATER
-    map->uthread = curuthread;
-#endif
-    map->handle = v_gethandle(vt);
-    map->uvaddr = v_getaddr(vt);
-    map->map = pciio_piomap;
-    map->space = soft->iomem;
-    map->base = soft->base + off;
-    map->size = len;
-    pciba_map_push(soft->comm->bus, map);
-
-    /* Inform the system of the correct
-     * kvaddr corresponding to the thing
-     * that is being mapped.
-     */
-    v_mapphys(vt, kaddr, len);
-
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pciba_unmap(dev_t dev, vhandl_t *vt)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    pciba_bus_t             bus = soft->comm->bus;
-    pciba_map_t             map;
-    __psunsigned_t          handle = v_gethandle(vt);
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-#if DEBUG_PCIBA
-    printf("pciba_unmap(%V,vt=%x)\n", dev, vt);
-#endif
+	DPRINTF("PCI base at virtual address %lx\n", pci_va);
+	/* the __pa macro is intended for region 7 on IA64, so it
+	   doesn't work for region 6 */
+  	/* pci_pa = __pa(pci_va); */
+	/* should be replaced by __tpa or equivalent (preferably a
+	   generic equivalent) */
+	pci_pa = pci_va & ~0xe000000000000000ul;
+	DPRINTF("PCI base at physical address %lx\n", pci_pa);
 
-    /* If this is a userDMA buffer,
-     * make a note that it has been unmapped
-     * so it can be released.
-     */
-    if (soft->comm->dmap) {
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next)
-	    if (handle == dmap->handle) {
-		dmap->handle = 0;
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: unmapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, handle);
-#endif
-		return 0;		/* found userPCI */
-	    }
-	pciba_soft_unlock(soft);
-    }
-    map = pciba_map_pop_hdl(bus, handle);
-    if (map == NULL)
-	return EINVAL;			/* no match */
+	/* there are various arch-specific versions of this function
+           defined in linux/drivers/char/mem.c, but it would be nice
+           if all architectures put it in pgtable.h.  it's defined
+           there for ia64.... */
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
-    if (map->map)
-	pciio_piomap_free(map->map);
-    DEL(map);
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-    return (0);				/* all done OK */
+	return io_remap_page_range(vma->vm_start, pci_pa, 
+				   vma->vm_end-vma->vm_start,
+				   vma->vm_page_prot);
 }
 
-#if ULI
-void
-pciba_clearuli(struct uli *uli)
+
+static int
+mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va)
 {
-    pciio_intr_t            intr = (pciio_intr_t) uli->teardownarg1;
+	unsigned long kernel_pa;
 
-#if DEBUG_PCIBA
-    printf("pciba_clearuli(0x%x)\n", uli);
-#endif
+	TRACE();
 
-    pciio_intr_disconnect(intr);
-    pciio_intr_free(intr);
-    atomic_dec(&pciba_prevent_unload);
-}
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-void
-pciba_intr(intr_arg_t arg)
-{
-    struct uli             *uli = (struct uli *) arg;
-    int                     ulinum = uli->index;
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-    extern void frs_handle_uli(void);
+	DPRINTF("mapping virtual address %p\n", kernel_va);
+	kernel_pa = __pa(kernel_va);
+	DPRINTF("mapping physical address %lx\n", kernel_pa);
 
-    if (ulinum >= 0 && ulinum < MAX_ULIS) {
-	    uli_callup(ulinum);
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-	    if (private.p_frs_flags)
-		    frs_handle_uli();
-    }
-}
-#endif
-#endif /* LATER - undef as we implement each routine */
+	return remap_page_range(vma->vm_start, kernel_pa, 
+				vma->vm_end-vma->vm_start,
+				vma->vm_page_prot);
+}	
diff -urN linux-2.4.16/arch/ia64/sn/io/pcibr.c lia64-2.4/arch/ia64/sn/io/pcibr.c
--- linux-2.4.16/arch/ia64/sn/io/pcibr.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/pcibr.c	Wed Dec 31 16:00:00 1969
@@ -1,9824 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifdef BRINGUP
-int NeedXbridgeSwap = 0;
-#endif
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
-
-#ifdef __ia64
-#define rmallocmap atemapalloc
-#define rmfreemap atemapfree
-#define rmfree atefree
-#define rmalloc atealloc
-#endif
-
-#undef PCIBR_ATE_DEBUG
-#if defined(BRINGUP)
-#if 0
-#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
-#endif
-#define PCI_DEBUG 1
-#define ATTACH_DEBUG 1
-#define PCIBR_SOFT_LIST 1
-#endif
-
-#ifndef	LOCAL
-#define	LOCAL		static
-#endif
-
-/*
- * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
- * appears that if the lucent part can get into a retry loop if it sees a
- * DAC on the bus during a pio read retry.  The loop is broken after about
- * 1ms, so we need to set up bridges holding this part to allow at least
- * 1ms for pio.
- */
-
-#define USS302_TIMEOUT_WAR
-
-#ifdef USS302_TIMEOUT_WAR
-#include <asm/sn/io.h>
-#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
-#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
-#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
-#define USS302_BRIDGE_TIMEOUT_HLD	4
-#endif
-
-#define PCIBR_LLP_CONTROL_WAR
-#if defined (PCIBR_LLP_CONTROL_WAR)
-int                     pcibr_llp_control_war_cnt;
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#define	NEWAf(ptr,n,f)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))
-#define NEWA(ptr,n)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))
-#define DELA(ptr,n)	(kfree(ptr))
-
-#define NEWf(ptr,f)	NEWAf(ptr,1,f)
-#define NEW(ptr)	NEWA(ptr,1)
-#define DEL(ptr)	DELA(ptr,1)
-
-int                     pcibr_devflag = D_MP;
-
-#ifdef LATER
-#define F(s,n)		{ 1l<<(s),-(s), n }
-
-struct reg_desc         bridge_int_status_desc[] =
-{
-    F(31, "MULTI_ERR"),
-    F(30, "PMU_ESIZE_EFAULT"),
-    F(29, "UNEXPECTED_RESP"),
-    F(28, "BAD_XRESP_PACKET"),
-    F(27, "BAD_XREQ_PACKET"),
-    F(26, "RESP_XTALK_ERROR"),
-    F(25, "REQ_XTALK_ERROR"),
-    F(24, "INVALID_ADDRESS"),
-    F(23, "UNSUPPORTED_XOP"),
-    F(22, "XREQ_FIFO_OFLOW"),
-    F(21, "LLP_REC_SNERROR"),
-    F(20, "LLP_REC_CBERROR"),
-    F(19, "LLP_RCTY"),
-    F(18, "LLP_TX_RETRY"),
-    F(17, "LLP_TCTY"),
-    F(16, "SSRAM_PERR"),
-    F(15, "PCI_ABORT"),
-    F(14, "PCI_PARITY"),
-    F(13, "PCI_SERR"),
-    F(12, "PCI_PERR"),
-    F(11, "PCI_MASTER_TOUT"),
-    F(10, "PCI_RETRY_CNT"),
-    F(9, "XREAD_REQ_TOUT"),
-    F(8, "GIO_BENABLE_ERR"),
-    F(7, "INT7"),
-    F(6, "INT6"),
-    F(5, "INT5"),
-    F(4, "INT4"),
-    F(3, "INT3"),
-    F(2, "INT2"),
-    F(1, "INT1"),
-    F(0, "INT0"),
-    {0}
-};
-
-struct reg_values       space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
-
-struct reg_desc         space_desc[] =
-{
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-
-#if DEBUG
-#define	device_desc	device_bits
-LOCAL struct reg_desc   device_bits[] =
-{
-    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
-    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
-    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
-    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
-    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
-    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
-    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
-    {BRIDGE_DEV_RT, 0, "RT"},
-    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
-    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
-    {BRIDGE_DEV_PREF, 0, "PREF"},
-    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
-    {BRIDGE_DEV_COH, 0, "COH"},
-    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
-    {BRIDGE_DEV_GBR, 0, "GBR"},
-    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
-    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
-    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
-    {0}
-};
-#endif	/* DEBUG */
-
-#ifdef SUPPORT_PRINTING_R_FORMAT
-LOCAL struct reg_values xio_cmd_pactyp[] =
-{
-    {0x0, "RdReq"},
-    {0x1, "RdResp"},
-    {0x2, "WrReqWithResp"},
-    {0x3, "WrResp"},
-    {0x4, "WrReqNoResp"},
-    {0x5, "Reserved(5)"},
-    {0x6, "FetchAndOp"},
-    {0x7, "Reserved(7)"},
-    {0x8, "StoreAndOp"},
-    {0x9, "Reserved(9)"},
-    {0xa, "Reserved(a)"},
-    {0xb, "Reserved(b)"},
-    {0xc, "Reserved(c)"},
-    {0xd, "Reserved(d)"},
-    {0xe, "SpecialReq"},
-    {0xf, "SpecialResp"},
-    {0}
-};
-
-LOCAL struct reg_desc   xio_cmd_bits[] =
-{
-    {WIDGET_DIDN, -28, "DIDN", "%x"},
-    {WIDGET_SIDN, -24, "SIDN", "%x"},
-    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
-    {WIDGET_TNUM, -15, "TNUM", "%x"},
-    {WIDGET_COHERENT, 0, "COHERENT"},
-    {WIDGET_DS, 0, "DS"},
-    {WIDGET_GBR, 0, "GBR"},
-    {WIDGET_VBPM, 0, "VBPM"},
-    {WIDGET_ERROR, 0, "ERROR"},
-    {WIDGET_BARRIER, 0, "BARRIER"},
-    {0}
-};
-#endif	/* SUPPORT_PRINTING_R_FORMAT */
-
-#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
-LOCAL struct reg_desc   ate_bits[] =
-{
-    {0xFFFF000000000000ull, -48, "RMF", "%x"},
-    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
-     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
-    {0x0000000000000F00ull, -8, "port", "%x"},
-    {0x0000000000000010ull, 0, "Barrier"},
-    {0x0000000000000008ull, 0, "Prefetch"},
-    {0x0000000000000004ull, 0, "Precise"},
-    {0x0000000000000002ull, 0, "Coherent"},
-    {0x0000000000000001ull, 0, "Valid"},
-    {0}
-};
-#endif
-
-#if PCIBR_ATE_DEBUG
-LOCAL struct reg_values ssram_sizes[] =
-{
-    {BRIDGE_CTRL_SSRAM_512K, "512k"},
-    {BRIDGE_CTRL_SSRAM_128K, "128k"},
-    {BRIDGE_CTRL_SSRAM_64K, "64k"},
-    {BRIDGE_CTRL_SSRAM_1K, "1k"},
-    {0}
-};
-
-LOCAL struct reg_desc   control_bits[] =
-{
-    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
-    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
-    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
-    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
-    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
-    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
-    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
-    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
-    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
-    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
-    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
-    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
-    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
-    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
-    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
-    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
-    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
-    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
-    {0}
-};
-#endif
-#endif	/* LATER */
-
-/* kbrick widgetnum-to-bus layout */
-int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
-        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
-        2,                                      /* 0x8          */
-        1,                                      /* 0x9          */
-        0, 0,                                   /* 0xa - 0xb    */
-        5,                                      /* 0xc          */
-        6,                                      /* 0xd          */
-        4,                                      /* 0xe          */
-        3,                                      /* 0xf          */
-};
-
-/*
- * Additional PIO spaces per slot are
- * recorded in this structure.
- */
-struct pciio_piospace_s {
-    pciio_piospace_t        next;	/* another space for this device */
-    char                    free;	/* 1 if free, 0 if in use               */
-    pciio_space_t           space;	/* Which space is in use                */
-    iopaddr_t               start;	/* Starting address of the PIO space    */
-    size_t                  count;	/* size of PIO space                    */
-};
-
-/* Use io spin locks. This ensures that all the PIO writes from a particular
- * CPU to a particular IO device are synched before the start of the next
- * set of PIO operations to the same device.
- */
-#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)
-#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)
-
-#if PCIBR_SOFT_LIST
-typedef struct pcibr_list_s *pcibr_list_p;
-struct pcibr_list_s {
-    pcibr_list_p            bl_next;
-    pcibr_soft_t            bl_soft;
-    devfs_handle_t            bl_vhdl;
-};
-pcibr_list_p            pcibr_list = 0;
-#endif
-
-typedef volatile unsigned *cfg_p;
-typedef volatile bridgereg_t *reg_p;
-
-#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
-
-#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
-#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
-
-#define PCIBR_VALID_SLOT(s)	(s < 8)
-
-#ifdef SN_XXX
-extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
-                                     hub_widget_flags_t flags);
-#endif
-extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
-
-/*
- * This is the file operation table for the pcibr driver.
- * As each of the functions are implemented, put the 
- * appropriate function name below.
- */
-struct file_operations pcibr_fops = {
-        owner:  THIS_MODULE,
-        llseek: NULL,
-        read: NULL,
-        write: NULL,
-        readdir: NULL,
-        poll: NULL,
-        ioctl: NULL,
-        mmap: NULL,
-        open: NULL,
-        flush: NULL,
-        release: NULL,
-        fsync: NULL,
-        fasync: NULL,
-        lock: NULL,
-        readv: NULL,
-        writev: NULL
-};
-
-extern devfs_handle_t hwgraph_root;
-extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
-extern int cap_able(uint64_t x);
-extern uint64_t rmalloc(struct map *mp, size_t size);
-extern void rmfree(struct map *mp, size_t size, uint64_t a);
-extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
-extern long atoi(register char *p);
-extern void *swap_ptr(void **loc, void *new);
-extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
-extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
-extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
-extern struct map *rmallocmap(uint64_t mapsiz);
-extern void rmfreemap(struct map *mp);
-extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
-extern int io_path_map_widget(devfs_handle_t vertex);
-
-
-
-/* =====================================================================
- *    Function Table of Contents
- *
- *      The order of functions in this file has stopped
- *      making much sense. We might want to take a look
- *      at it some time and bring back some sanity, or
- *      perhaps bust this file into smaller chunks.
- */
-
-LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
-LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
-LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
-LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
-
-LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
-
-int			pcibr_wrb_flush(devfs_handle_t);
-int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
-int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
-int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
-void                    pcibr_rrb_flush(devfs_handle_t);
-
-LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
-void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
-
-LOCAL void              pcibr_clearwidint(bridge_t *);
-LOCAL void              pcibr_setwidint(xtalk_intr_t);
-LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
-
-void                    pcibr_init(void);
-int                     pcibr_attach(devfs_handle_t);
-int			pcibr_detach(devfs_handle_t);
-int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
-int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
-int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
-int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
-int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
-
-void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
-
-LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
-LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
-LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
-
-LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
-LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
-LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
-LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-
-pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
-void                    pcibr_piomap_free(pcibr_piomap_t);
-caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
-void                    pcibr_piomap_done(pcibr_piomap_t);
-caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
-void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
-
-LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
-LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
-
-pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
-void                    pcibr_dmamap_free(pcibr_dmamap_t);
-LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
-LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
-iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
-alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_done(pcibr_dmamap_t);
-cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
-iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
-alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_drain(pcibr_dmamap_t);
-void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
-void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
-iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
-
-static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
-pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
-void                    pcibr_intr_free(pcibr_intr_t);
-LOCAL void              pcibr_setpciint(xtalk_intr_t);
-int                     pcibr_intr_connect(pcibr_intr_t, intr_func_t, intr_arg_t, void *);
-void                    pcibr_intr_disconnect(pcibr_intr_t);
-
-devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
-void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
-void                    pcibr_intr_func(intr_arg_t);
-
-LOCAL void              print_bridge_errcmd(uint32_t, char *);
-
-void                    pcibr_error_dump(pcibr_soft_t);
-uint32_t              pcibr_errintr_group(uint32_t);
-LOCAL void		pcibr_pioerr_check(pcibr_soft_t);
-LOCAL void              pcibr_error_intr_handler(intr_arg_t);
-
-LOCAL int               pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
-LOCAL void              pcibr_error_cleanup(pcibr_soft_t, int);
-void                    pcibr_device_disable(pcibr_soft_t, int);
-LOCAL int               pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-LOCAL int               pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_error_devenable(devfs_handle_t, int);
-
-void                    pcibr_provider_startup(devfs_handle_t);
-void                    pcibr_provider_shutdown(devfs_handle_t);
-
-int                     pcibr_reset(devfs_handle_t);
-pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
-int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
-pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
-int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
-
-LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
-uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
-LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
-void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
-LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
-
-LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
-void                    pcibr_hints_fix_rrbs(devfs_handle_t);
-void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
-void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
-void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
-void                    pcibr_hints_handsoff(devfs_handle_t);
-void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
-
-LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
-
-#ifdef LATER
-LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
-                                               pcibr_slot_info_resp_t);
-LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
-                                                    pcibr_slot_func_info_resp_t);
-#endif	/* LATER */
-
-LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
-LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
-						      pciio_slot_t, int);
-LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
-						      pciio_slot_t, int);
-
-LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
-LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
-#ifdef LATER
-LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
-#endif
-
-/* =====================================================================
- *    RRB management
- */
-
-#define LSBIT(word)		((word) &~ ((word)-1))
-
-#define PCIBR_RRB_SLOT_VIRTUAL	8
-
-LOCAL void
-do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
-{
-    bridgereg_t             status;
-
-    /* bridge_lock must be held;
-     * this RRB must be disabled.
-     */
-
-    /* wait until RRB has no outstanduing XIO packets. */
-    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
-	;				/* XXX- beats on bridge. bad idea? */
-    }
-
-    /* if the RRB has data, drain it. */
-    if (status & BRIDGE_RRB_VALID(rrb)) {
-	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
-
-	/* wait until RRB is no longer valid. */
-	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
-	    ;				/* XXX- beats on bridge. bad idea? */
-	}
-    }
-}
-
-LOCAL void
-do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
-{
-    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
-    bridgereg_t             rrbv;
-    int                     shft = 4 * (rrbn >> 1);
-    unsigned                ebit = BRIDGE_RRB_EN << shft;
-
-    rrbv = *rrbp;
-    if (rrbv & ebit)
-	*rrbp = rrbv & ~ebit;
-
-    do_pcibr_rrb_clear(bridge, rrbn);
-
-    if (rrbv & ebit)
-	*rrbp = rrbv;
-}
-
-/*
- *    pcibr_rrb_count_valid: count how many RRBs are
- *      marked valid for the specified PCI slot on this
- *      bridge.
- *
- *      NOTE: The "slot" parameter for all pcibr_rrb
- *      management routines must include the "virtual"
- *      bit; when manageing both the normal and the
- *      virtual channel, separate calls to these
- *      routines must be made. To denote the virtual
- *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
- *      number.
- *
- *      IMPL NOTE: The obvious algorithm is to iterate
- *      through the RRB fields, incrementing a count if
- *      the RRB is valid and matches the slot. However,
- *      it is much simpler to use an algorithm derived
- *      from the "partitioned add" idea. First, XOR in a
- *      pattern such that the fields that match this
- *      slot come up "all ones" and all other fields
- *      have zeros in the mismatching bits. Then AND
- *      together the bits in the field, so we end up
- *      with one bit turned on for each field that
- *      matched. Now we need to count these bits. This
- *      can be done either with a series of shift/add
- *      instructions or by using "tmp % 15"; I expect
- *      that the cascaded shift/add will be faster.
- */
-
-LOCAL int
-do_pcibr_rrb_count_valid(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp ^= 0x11111111 * (7 - slot / 2);
-    tmp &= (0xCCCCCCCC & tmp) >> 2;
-    tmp &= (0x22222222 & tmp) >> 1;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_count_avail: count how many RRBs are
- *      available to be allocated for the specified slot.
- *
- *      IMPL NOTE: similar to the above, except we are
- *      just counting how many fields have the valid bit
- *      turned off.
- */
-LOCAL int
-do_pcibr_rrb_count_avail(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~tmp) >> 3;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_alloc: allocate some additional RRBs
- *      for the specified slot. Returns -1 if there were
- *      insufficient free RRBs to satisfy the request,
- *      or 0 if the request was fulfilled.
- *
- *      Note that if a request can be partially filled,
- *      it will be, even if we return failure.
- *
- *      IMPL NOTE: again we avoid iterating across all
- *      the RRBs; instead, we form up a word containing
- *      one bit for each free RRB, then peel the bits
- *      off from the low end.
- */
-LOCAL int
-do_pcibr_rrb_alloc(bridge_t *bridge,
-		   pciio_slot_t slot,
-		   int more)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, bit;
-
-    reg = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~reg) >> 3;
-    while (more-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-    return rv;
-}
-
-/*
- *    do_pcibr_rrb_free: release some of the RRBs that
- *      have been allocated for the specified
- *      slot. Returns zero for success, or negative if
- *      it was unable to free that many RRBs.
- *
- *      IMPL NOTE: We form up a bit for each RRB
- *      allocated to the slot, aligned with the VALID
- *      bitfield this time; then we peel bits off one at
- *      a time, releasing the corresponding RRB.
- */
-LOCAL int
-do_pcibr_rrb_free(bridge_t *bridge,
-		  pciio_slot_t slot,
-		  int less)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, clr, bit;
-    int                     i;
-
-    clr = 0;
-    reg = bridge->b_rrb_map[slot & 1].reg;
-
-    /* This needs to be done otherwise the rrb's on the virtual channel
-     * for this slot won't be freed !!
-     */
-    tmp = reg & 0xbbbbbbbb;
-
-    tmp ^= (0x11111111 * (7 - slot / 2));
-    tmp &= (0x33333333 & tmp) << 2;
-    tmp &= (0x44444444 & tmp) << 1;
-    while (less-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg &= ~bit;
-	clr |= bit;
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-
-    for (i = 0; i < 8; i++)
-	if (clr & (8 << (4 * i)))
-	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
-
-    return rv;
-}
-
-LOCAL void
-do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
-		       int slot,
-		       int more_rrbs)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     got;
-
-    for (got = 0; got < more_rrbs; ++got) {
-	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
-	    pcibr_soft->bs_rrb_res[slot & 7]--;
-	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
-	    pcibr_soft->bs_rrb_avail[slot & 1]--;
-	else
-	    break;
-	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
-	    break;
-#if PCIBR_RRB_DEBUG
-	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
-		slot & 7, slot & 8 ? "v" : "");
-#endif
-	pcibr_soft->bs_rrb_valid[slot]++;
-    }
-#if PCIBR_RRB_DEBUG
-    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
-	    pcibr_soft->bs_rrb_avail[0],
-	    pcibr_soft->bs_rrb_avail[1]);
-    for (slot = 0; slot < 8; ++slot)
-	printk("\t%d+%d+%d",
-		0xFFF & pcibr_soft->bs_rrb_valid[slot],
-		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-		pcibr_soft->bs_rrb_res[slot]);
-	printk("\n");
-#endif
-}
-
-/*
- * Device driver interface to flush the write buffers for a specified
- * device hanging off the bridge.
- */
-int
-pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    volatile bridgereg_t   *wrb_flush;
-
-    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
-    while (*wrb_flush);
-
-    return(0);
-}
-/*
- * Device driver interface to request RRBs for a specified device
- * hanging off a Bridge.  The driver requests the total number of
- * RRBs it would like for the normal channel (vchan0) and for the
- * "virtual channel" (vchan1).  The actual number allocated to each
- * channel is returned.
- *
- * If we cannot allocate at least one RRB to a channel that needs
- * at least one, return -1 (failure).  Otherwise, satisfy the request
- * as best we can and return 0.
- */
-int
-pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     desired_vchan0;
-    int                     desired_vchan1;
-    int                     orig_vchan0;
-    int                     orig_vchan1;
-    int                     delta_vchan0;
-    int                     delta_vchan1;
-    int                     final_vchan0;
-    int                     final_vchan1;
-    int                     avail_rrbs;
-    unsigned long           s;
-    int                     error;
-
-    /*
-     * TBD: temper request with admin info about RRB allocation,
-     * and according to demand from other devices on this Bridge.
-     *
-     * One way of doing this would be to allocate two RRBs
-     * for each device on the bus, before any drivers start
-     * asking for extras. This has the weakness that one
-     * driver might not give back an "extra" RRB until after
-     * another driver has already failed to get one that
-     * it wanted.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-
-    /* How many RRBs do we own? */
-    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
-    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-    /* How many RRBs do we want? */
-    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
-    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
-
-    /* How many RRBs are free? */
-    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	+ pcibr_soft->bs_rrb_res[pciio_slot];
-
-    /* Figure desired deltas */
-    delta_vchan0 = desired_vchan0 - orig_vchan0;
-    delta_vchan1 = desired_vchan1 - orig_vchan1;
-
-    /* Trim back deltas to something
-     * that we can actually meet, by
-     * decreasing the ending allocation
-     * for whichever channel wants
-     * more RRBs. If both want the same
-     * number, cut the second channel.
-     * NOTE: do not change the allocation for
-     * a channel that was passed as NULL.
-     */
-    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
-	if (count_vchan0 &&
-	    (!count_vchan1 ||
-	     ((orig_vchan0 + delta_vchan0) >
-	      (orig_vchan1 + delta_vchan1))))
-	    delta_vchan0--;
-	else
-	    delta_vchan1--;
-    }
-
-    /* Figure final RRB allocations
-     */
-    final_vchan0 = orig_vchan0 + delta_vchan0;
-    final_vchan1 = orig_vchan1 + delta_vchan1;
-
-    /* If either channel wants RRBs but our actions
-     * would leave it with none, declare an error,
-     * but DO NOT change any RRB allocations.
-     */
-    if ((desired_vchan0 && !final_vchan0) ||
-	(desired_vchan1 && !final_vchan1)) {
-
-	error = -1;
-
-    } else {
-
-	/* Commit the allocations: free, then alloc.
-	 */
-	if (delta_vchan0 < 0)
-	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
-	if (delta_vchan1 < 0)
-	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
-
-	if (delta_vchan0 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
-	if (delta_vchan1 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
-
-	/* Return final values to caller.
-	 */
-	if (count_vchan0)
-	    *count_vchan0 = final_vchan0;
-	if (count_vchan1)
-	    *count_vchan1 = final_vchan1;
-
-	/* prevent automatic changes to this slot's RRBs
-	 */
-	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
-
-	/* Track the actual allocations, release
-	 * any further reservations, and update the
-	 * number of available RRBs.
-	 */
-
-	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
-	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
-	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
-	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	    + pcibr_soft->bs_rrb_res[pciio_slot]
-	    - delta_vchan0
-	    - delta_vchan1;
-	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
-
-#if PCIBR_RRB_DEBUG
-	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
-		pciio_slot, final_vchan0, final_vchan1,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
-	    printk("\t%d+%d+%d",
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
-		    pcibr_soft->bs_rrb_res[pciio_slot]);
-	printk("\n");
-#endif
-
-	error = 0;
-    }
-
-    pcibr_unlock(pcibr_soft, s);
-    return error;
-}
-
-/*
- * Device driver interface to check the current state
- * of the RRB allocations.
- *
- *   pconn_vhdl is your PCI connection point (specifies which
- *      PCI bus and which slot).
- *
- *   count_vchan0 points to where to return the number of RRBs
- *      assigned to the primary DMA channel, used by all DMA
- *      that does not explicitly ask for the alternate virtual
- *      channel.
- *
- *   count_vchan1 points to where to return the number of RRBs
- *      assigned to the secondary DMA channel, used when
- *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
- *
- *   count_reserved points to where to return the number of RRBs
- *      that have been automatically reserved for your device at
- *      startup, but which have not been assigned to a
- *      channel. RRBs must be assigned to a channel to be used;
- *      this can be done either with an explicit pcibr_rrb_alloc
- *      call, or automatically by the infrastructure when a DMA
- *      translation is constructed. Any call to pcibr_rrb_alloc
- *      will release any unassigned reserved RRBs back to the
- *      free pool.
- *
- *   count_pool points to where to return the number of RRBs
- *      that are currently unassigned and unreserved. This
- *      number can (and will) change as other drivers make calls
- *      to pcibr_rrb_alloc, or automatically allocate RRBs for
- *      DMA beyond their initial reservation.
- *
- * NULL may be passed for any of the return value pointers
- * the caller is not interested in.
- *
- * The return value is "0" if all went well, or "-1" if
- * there is a problem. Additionally, if the wrong vertex
- * is passed in, one of the subsidiary support functions
- * could panic with a "bad pciio fingerprint."
- */
-
-int
-pcibr_rrb_check(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1,
-		int *count_reserved,
-		int *count_pool)
-{
-    pciio_info_t            pciio_info;
-    pciio_slot_t            pciio_slot;
-    pcibr_soft_t            pcibr_soft;
-    unsigned long           s;
-    int                     error = -1;
-
-    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
-	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
-	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
-
-	s = pcibr_lock(pcibr_soft);
-
-	if (count_vchan0)
-	    *count_vchan0 =
-		pcibr_soft->bs_rrb_valid[pciio_slot];
-
-	if (count_vchan1)
-	    *count_vchan1 =
-		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-	if (count_reserved)
-	    *count_reserved =
-		pcibr_soft->bs_rrb_res[pciio_slot];
-
-	if (count_pool)
-	    *count_pool =
-		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
-
-	error = 0;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return error;
-}
-
-/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
- * requested for each of the devies.  The evn_odd argument indicates whether
- * allcoation for the odd or even rrbs is requested and next group of four pairse
- * are the amount to assign to each device (they should sum to <= 8) and
- * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
- * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
- * if even_odd is even we alloc even rrbs else we allocate odd rrbs
- * returns 0 if no errors else returns -1
- */
-
-int
-pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
-		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
-		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
-{
-    devfs_handle_t            pcibr_vhdl;
-    pcibr_soft_t            pcibr_soft = NULL;
-    bridge_t               *bridge = NULL;
-
-    uint32_t              rrb_setting = 0;
-    int                     rrb_shift = 7;
-    uint32_t              cur_rrb;
-    int                     dev_rrbs[4];
-    int                     virt[4];
-    int                     i, j;
-    unsigned long           s;
-
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
-	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-	if (pcibr_soft)
-	    bridge = pcibr_soft->bs_base;
-	hwgraph_vertex_unref(pcibr_vhdl);
-    }
-    if (bridge == NULL)
-	bridge = (bridge_t *) xtalk_piotrans_addr
-	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
-
-    even_odd &= 1;
-
-    dev_rrbs[0] = dev_1_rrbs;
-    dev_rrbs[1] = dev_2_rrbs;
-    dev_rrbs[2] = dev_3_rrbs;
-    dev_rrbs[3] = dev_4_rrbs;
-
-    virt[0] = virt1;
-    virt[1] = virt2;
-    virt[2] = virt3;
-    virt[3] = virt4;
-
-    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
-	return -1;
-    }
-    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
-	return -1;
-    }
-    /* walk through rrbs */
-    for (i = 0; i < 4; i++) {
-	if (virt[i]) {
-	    cur_rrb = i | 0xc;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	    dev_rrbs[i] = dev_rrbs[i] - 1;
-	}
-	for (j = 0; j < dev_rrbs[i]; j++) {
-	    cur_rrb = i | 0x8;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	}
-    }
-
-    if (pcibr_soft)
-	s = pcibr_lock(pcibr_soft);
-
-    bridge->b_rrb_map[even_odd].reg = rrb_setting;
-
-    if (pcibr_soft) {
-
-	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
-
-	/* since we've "FIXED" the allocations
-	 * for these slots, we probably can dispense
-	 * with tracking avail/res/valid data, but
-	 * keeping it up to date helps debugging.
-	 */
-
-	pcibr_soft->bs_rrb_avail[even_odd] =
-	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
-
-	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return 0;
-}
-
-/*
- *    pcibr_rrb_flush: chase down all the RRBs assigned
- *      to the specified connection point, and flush
- *      them.
- */
-void
-pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned long           s;
-    reg_p                   rrbp;
-    unsigned                rrbm;
-    int                     i;
-    int                     rrbn;
-    unsigned                sval;
-    unsigned                mask;
-
-    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
-    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
-    rrbn = pciio_slot & 1;
-    rrbp = &bridge->b_rrb_map[rrbn].reg;
-
-    s = pcibr_lock(pcibr_soft);
-    rrbm = *rrbp;
-    for (i = 0; i < 8; ++i) {
-	if ((rrbm & mask) == sval)
-	    do_pcibr_rrb_flush(bridge, rrbn);
-	rrbm >>= 4;
-	rrbn += 2;
-    }
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Device(x) register management
- */
-
-/* pcibr_try_set_device: attempt to modify Device(x)
- * for the specified slot on the specified bridge
- * as requested in flags, limited to the specified
- * bits. Returns which BRIDGE bits were in conflict,
- * or ZERO if everything went OK.
- *
- * Caller MUST hold pcibr_lock when calling this function.
- */
-LOCAL int
-pcibr_try_set_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     unsigned flags,
-		     bridgereg_t mask)
-{
-    bridge_t               *bridge;
-    pcibr_soft_slot_t       slotp;
-    bridgereg_t             old;
-    bridgereg_t             new;
-    bridgereg_t             chg;
-    bridgereg_t             bad;
-    bridgereg_t             badpmu;
-    bridgereg_t             badd32;
-    bridgereg_t             badd64;
-    bridgereg_t             fix;
-    unsigned long           s;
-    bridgereg_t             xmask;
-
-    xmask = mask;
-    if (pcibr_soft->bs_xbridge) {
-    	if (mask == BRIDGE_DEV_PMU_BITS)
-		xmask = XBRIDGE_DEV_PMU_BITS;
-	if (mask == BRIDGE_DEV_D64_BITS)
-		xmask = XBRIDGE_DEV_D64_BITS;
-    }
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    bridge = pcibr_soft->bs_base;
-
-    old = slotp->bss_device;
-
-    /* figure out what the desired
-     * Device(x) bits are based on
-     * the flags specified.
-     */
-
-    new = old;
-
-    /* Currently, we inherit anything that
-     * the new caller has not specified in
-     * one way or another, unless we take
-     * action here to not inherit.
-     *
-     * This is needed for the "swap" stuff,
-     * since it could have been set via
-     * pcibr_endian_set -- altho note that
-     * any explicit PCIBR_BYTE_STREAM or
-     * PCIBR_WORD_VALUES will freely override
-     * the effect of that call (and vice
-     * versa, no protection either way).
-     *
-     * I want to get rid of pcibr_endian_set
-     * in favor of tracking DMA endianness
-     * using the flags specified when DMA
-     * channels are created.
-     */
-
-#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
-#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
-
-    /* Do not use Barrier, Write Gather,
-     * or Prefetch unless asked.
-     * Leave everything else as it
-     * was from the last time.
-     */
-    new = new
-	& ~BRIDGE_DEV_BARRIER
-	& ~BRIDGE_DEV_WRGA_BITS
-	& ~BRIDGE_DEV_PREF
-	;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {
-	new = (new
-            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
-            | BRIDGE_DEV_PREF;          /* prefetch on */
-
-    }
-    if (flags & PCIIO_DMA_CMD) {
-        new = ((new
-            & ~BRIDGE_DEV_PREF)         /* prefetch off */
-            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
-            | BRIDGE_DEV_BARRIER;       /* barrier on */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIIO_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_BYTE_STREAM)
-	new |= (pcibr_soft->bs_xbridge) ? 
-			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
-    if (flags & PCIIO_WORD_VALUES)
-	new &= (pcibr_soft->bs_xbridge) ? 
-			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	new |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	new &= ~BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	new |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	new &= ~BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	new |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	new &= ~BRIDGE_DEV_DEV_SIZE;
-
-    chg = old ^ new;				/* what are we changing, */
-    chg &= xmask;				/* of the interesting bits */
-
-    if (chg) {
-
-	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
-	if (pcibr_soft->bs_xbridge) {
-		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
-	} else {
-		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
-	}
-	bad = badpmu | badd32 | badd64;
-
-	if (bad) {
-
-	    /* some conflicts can be resolved by
-	     * forcing the bit on. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit off,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
-                             BRIDGE_DEV_BARRIER)) ){
-		bad &= ~fix;
-		/* don't change these bits if
-		 * they are already set in "old"
-		 */
-		chg &= ~(fix & old);
-	    }
-	    /* some conflicts can be resolved by
-	     * forcing the bit off. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit on,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
-			     BRIDGE_DEV_PREF)) ) {
-		bad &= ~fix;
-		/* don't change these bits if
-		 * we wanted to turn them on.
-		 */
-		chg &= ~(fix & new);
-	    }
-	    /* conflicts in other bits mean
-	     * we can not establish this DMA
-	     * channel while the other(s) are
-	     * still present.
-	     */
-	    if (bad) {
-		pcibr_unlock(pcibr_soft, s);
-#if (DEBUG && PCIBR_DEV_DEBUG)
-		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
-#endif
-		return bad;
-	    }
-	}
-    }
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr++;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr++;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr++;
-
-    /* the value we want to write is the
-     * original value, with the bits for
-     * our selected changes flipped, and
-     * with any disabled features turned off.
-     */
-    new = old ^ chg;			/* only change what we want to change */
-
-    if (slotp->bss_device == new) {
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    bridge->b_device[slot].reg = new;
-    slotp->bss_device = new;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
-#endif
-
-    return 0;
-}
-
-void
-pcibr_release_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     bridgereg_t mask)
-{
-    pcibr_soft_slot_t       slotp;
-    unsigned long           s;
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr--;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr--;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr--;
-
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/*
- * flush write gather buffer for slot
- */
-LOCAL void
-pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
-              pciio_slot_t slot)
-{
-    bridge_t               *bridge;
-    unsigned long          s;
-    volatile uint32_t     wrf;
-    s = pcibr_lock(pcibr_soft);
-    bridge = pcibr_soft->bs_base;
-    wrf = bridge->b_wr_req_buf[slot].reg;
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Bridge (pcibr) "Device Driver" entry points
- */
-
-/*
- * pcibr_probe_slot: read a config space word
- * while trapping any errors; reutrn zero if
- * all went OK, or nonzero if there was an error.
- * The value read, if any, is passed back
- * through the valp parameter.
- */
-LOCAL int
-pcibr_probe_slot(bridge_t *bridge,
-		 cfg_p cfg,
-		 unsigned *valp)
-{
-    int                     rv;
-    bridgereg_t             old_enable, new_enable;
-    int badaddr_val(volatile void *, int, volatile void *);
-
-
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-
-    bridge->b_int_enable = new_enable;
-
-	/*
-	 * The xbridge doesn't clear b_err_int_view unless
-	 * multi-err is cleared...
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-	    }
-
-    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
-	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
-	(void) bridge->b_wid_tflush;	/* flushbus */
-    }
-    rv = badaddr_val((void *) cfg, 4, valp);
-
-	/*
-	 * The xbridge doesn't set master timeout in b_int_status
-	 * here.  Fortunately it's in error_interrupt_view.
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-		rv = 1;		/* unoccupied slot */
-	    }
-
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    return rv;
-}
-
-/*
- *    pcibr_init: called once during system startup or
- *      when a loadable driver is loaded.
- *
- *      The driver_register function should normally
- *      be in _reg, not _init.  But the pcibr driver is
- *      required by devinit before the _reg routines
- *      are called, so this is an exception.
- */
-void
-pcibr_init(void)
-{
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_init\n");
-#endif
-
-    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
-			    XBRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
-			    BRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-}
-
-/*
- * open/close mmap/munmap interface would be used by processes
- * that plan to map the PCI bridge, and muck around with the
- * registers. This is dangerous to do, and will be allowed
- * to a select brand of programs. Typically these are
- * diagnostics programs, or some user level commands we may
- * write to do some weird things.
- * To start with expect them to have root priveleges.
- * We will ask for more later.
- */
-/* ARGSUSED */
-int
-pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-    int                     error;
-    devfs_handle_t            vhdl = dev_to_vhdl(dev);
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    ASSERT(pcibr_soft);
-    len = ctob(btoc(len));		/* Make len page aligned */
-    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
-
-    /*
-     * If the offset being mapped corresponds to the flash prom
-     * base, and if the mapping succeeds, and if the user
-     * has requested the protections to be WRITE, enable the
-     * flash prom to be written.
-     *
-     * XXX- deprecate this in favor of using the
-     * real flash driver ...
-     */
-    if (!error &&
-	((off == BRIDGE_EXTERNAL_FLASH) ||
-	 (len > BRIDGE_EXTERNAL_FLASH))) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return error;
-}
-
-/*ARGSUSED */
-int
-pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    /*
-     * If flashprom write was enabled, disable it, as
-     * this is the last unmap.
-     */
-    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return 0;
-}
-
-/* This is special case code used by grio. There are plans to make
- * this a bit more general in the future, but till then this should
- * be sufficient.
- */
-pciio_slot_t
-pcibr_device_slot_get(devfs_handle_t dev_vhdl)
-{
-    char                    devname[MAXDEVNAME];
-    devfs_handle_t            tdev;
-    pciio_info_t            pciio_info;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-
-    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
-
-    /* run back along the canonical path
-     * until we find a PCI connection point.
-     */
-    tdev = hwgraph_connectpt_get(dev_vhdl);
-    while (tdev != GRAPH_VERTEX_NONE) {
-	pciio_info = pciio_info_chk(tdev);
-	if (pciio_info) {
-	    slot = pciio_info_slot_get(pciio_info);
-	    break;
-	}
-	hwgraph_vertex_unref(tdev);
-	tdev = hwgraph_connectpt_get(tdev);
-    }
-    hwgraph_vertex_unref(tdev);
-
-    return slot;
-}
-
-/*==========================================================================
- *	BRIDGE PCI SLOT RELATED IOCTLs
- */
-char *pci_space_name[] = {"NONE", 
-			  "ROM",
-			  "IO",
-			  "",
-			  "MEM",
-			  "MEM32",
-			  "MEM64",
-			  "CFG",
-			  "WIN0",
-			  "WIN1",
-			  "WIN2",
-			  "WIN3",
-			  "WIN4",
-			  "WIN5",
-			  "",
-			  "BAD"};
-
-
-#ifdef LATER
-
-void
-pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
-                            int func,
-                            pcibr_slot_func_info_resp_t funcp)
-{
-    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
-    int                          win;
-
-    funcp->resp_f_status = 0;
-
-    if (!pcibr_info) {
-        return;
-    }
-
-    funcp->resp_f_status |= FUNC_IS_VALID;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
-#else
-    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
-#endif
-
-    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
-        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
-    }
-
-    funcp->resp_f_bus = pcibr_info->f_bus;
-    funcp->resp_f_slot = pcibr_info->f_slot;
-    funcp->resp_f_func = pcibr_info->f_func;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
-#else
-    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
-#endif
-    funcp->resp_f_pops = pcibr_info->f_pops;
-    funcp->resp_f_efunc = pcibr_info->f_efunc;
-    funcp->resp_f_einfo = pcibr_info->f_einfo;
-
-    funcp->resp_f_vendor = pcibr_info->f_vendor;
-    funcp->resp_f_device = pcibr_info->f_device;
-
-    for(win = 0 ; win < 6 ; win++) {
-        funcp->resp_f_window[win].resp_w_base =
-                                  pcibr_info->f_window[win].w_base;
-        funcp->resp_f_window[win].resp_w_size =
-                                  pcibr_info->f_window[win].w_size;
-        sprintf(funcp->resp_f_window[win].resp_w_space,
-                "%s",
-                pci_space_name[pcibr_info->f_window[win].w_space]);
-    }
-
-    funcp->resp_f_rbase = pcibr_info->f_rbase;
-    funcp->resp_f_rsize = pcibr_info->f_rsize;
-
-    for (win = 0 ; win < 4; win++) {
-        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
-    }
-
-    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
-
-}
-
-int
-pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
-                       pciio_slot_t             slot,
-                       pcibr_slot_info_resp_t   respp)
-{
-    pcibr_soft_slot_t            pss;
-    int                          func;
-    bridge_t                    *bridge = pcibr_soft->bs_base;
-    reg_p                        b_respp;
-    pcibr_slot_info_resp_t       slotp;
-    pcibr_slot_func_info_resp_t  funcp;
-
-    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
-    if (slotp == NULL) {
-        return(ENOMEM);
-    }
-
-    pss = &pcibr_soft->bs_slot[slot];
-    
-    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
-
-    slotp->resp_has_host = pss->has_host;
-    slotp->resp_host_slot = pss->host_slot;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
-#else
-    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
-#endif
-    slotp->resp_slot_status = pss->slot_status;
-    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
-
-    if (is_sys_critical_vertex(pss->slot_conn)) {
-        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
-    }
-
-    slotp->resp_bss_ninfo = pss->bss_ninfo;
-
-    for (func = 0; func < pss->bss_ninfo; func++) {
-        funcp = &(slotp->resp_func[func]);
-        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
-    }
-
-    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
-            pci_space_name[pss->bss_devio.bssd_space]);
-    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
-    slotp->resp_bss_device = pss->bss_device;
-
-    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
-    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
-    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
-
-    slotp->resp_bss_d64_base = pss->bss_d64_base;
-    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
-    slotp->resp_bss_d32_base = pss->bss_d32_base;
-    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
-
-    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
-
-    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
-    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
-
-    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
-    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
-                                                      PCIBR_RRB_SLOT_VIRTUAL];
-    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
-
-    if (slot & 1) {
-        b_respp = &bridge->b_odd_resp;
-    } else {
-        b_respp = &bridge->b_even_resp;
-    }
-
-    slotp->resp_b_resp = *b_respp;
-
-    slotp->resp_b_int_device = bridge->b_int_device;
-    slotp->resp_b_int_enable = bridge->b_int_enable;
-    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
-
-    if (COPYOUT(slotp, respp, sizeof(*respp))) {
-        return(EFAULT);
-    }
-
-    kmem_free(slotp, sizeof(*slotp));
-
-    return(0);
-}
-
-/*
- * pcibr_slot_query
- *	Return information about the PCI slot maintained by the infrastructure.
- *	Information is requested in the request structure.
- *
- *      Information returned in the response structure:
- *		Slot hwgraph name
- *		Vendor/Device info
- *		Base register info
- *		Interrupt mapping from device pins to the bridge pins
- *		Devio register
- *		Software RRB info
- *		RRB register info
- *		Host/Gues info
- *		PCI Bus #,slot #, function #
- *		Slot provider hwgraph name
- *		Provider Functions
- *		Error handler
- *		DMA mapping usage counters
- *		DMA direct translation info
- *		External SSRAM workaround info
- */
-int
-pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pciio_slot_t            slot = reqp->req_slot;
-    pciio_slot_t            tmp_slot;
-    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
-    int                     size = reqp->req_size;
-    int                     error;
-
-    /* Make sure that we are dealing with a bridge device vertex */
-    if (!pcibr_soft) {
-        return(EINVAL);
-    }
-
-    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
-    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
-        return(EINVAL);
-    }
-
-#ifdef LATER
-    /* Do not allow a query of a slot in a shoehorn */
-    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
-       return(EPERM);
-    }
-#endif
-
-    /* Return information for the requested PCI slot */
-    if (slot != PCIIO_SLOT_NONE) {
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
-
-        return(error);
-    }
-
-    /* Return information for all the slots */
-    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
-
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
-
-        if (error) {
-            return(error);
-        }
-
-        ++respp;
-        size -= sizeof(*respp);
-    }
-
-    return(error);
-}
-#endif	/* LATER */
-
-
-/*ARGSUSED */
-int
-pcibr_ioctl(devfs_handle_t dev,
-	    int cmd,
-	    void *arg,
-	    int flag,
-	    struct cred *cr,
-	    int *rvalp)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
-#ifdef LATER
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-#endif
-    int                     error = 0;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    switch (cmd) {
-#ifdef LATER
-    case GIOCSETBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
-	    break;
-	}
-
-    case GIOCRELEASEBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
-	    break;
-	}
-
-    case PCIBR_SLOT_POWERUP:
-	{
-	    pciio_slot_t	slot;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_SHUTDOWN:
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_QUERY:
-	{
-	    struct pcibr_slot_info_req_s        req;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-            if (COPYIN(arg, &req, sizeof(req))) {
-                error = EFAULT;
-                break;
-            }
-
-            error = pcibr_slot_query(pcibr_vhdl, &req);
-	    break;
-	}
-#endif	/* LATER */
-    default:
-	break;
-
-    }
-
-    return error;
-}
-
-void
-pcibr_freeblock_sub(iopaddr_t *free_basep,
-		    iopaddr_t *free_lastp,
-		    iopaddr_t base,
-		    size_t size)
-{
-    iopaddr_t               free_base = *free_basep;
-    iopaddr_t               free_last = *free_lastp;
-    iopaddr_t               last = base + size - 1;
-
-    if ((last < free_base) || (base > free_last));	/* free block outside arena */
-
-    else if ((base <= free_base) && (last >= free_last))
-	/* free block contains entire arena */
-	*free_basep = *free_lastp = 0;
-
-    else if (base <= free_base)
-	/* free block is head of arena */
-	*free_basep = last + 1;
-
-    else if (last >= free_last)
-	/* free block is tail of arena */
-	*free_lastp = base - 1;
-
-    /*
-     * We are left with two regions: the free area
-     * in the arena "below" the block, and the free
-     * area in the arena "above" the block. Keep
-     * the one that is bigger.
-     */
-
-    else if ((base - free_base) > (free_last - last))
-	*free_lastp = base - 1;		/* keep lower chunk */
-    else
-	*free_basep = last + 1;		/* keep upper chunk */
-}
-
-/* Convert from ssram_bits in control register to number of SSRAM entries */
-#define ATE_NUM_ENTRIES(n) _ate_info[n]
-
-/* Possible choices for number of ATE entries in Bridge's SSRAM */
-LOCAL int               _ate_info[] =
-{
-    0,					/* 0 entries */
-    8 * 1024,				/* 8K entries */
-    16 * 1024,				/* 16K entries */
-    64 * 1024				/* 64K entries */
-};
-
-#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
-#define ATE_PROBE_VALUE 0x0123456789abcdefULL
-
-/*
- * Determine the size of this bridge's external mapping SSRAM, and set
- * the control register appropriately to reflect this size, and initialize
- * the external SSRAM.
- */
-LOCAL int
-pcibr_init_ext_ate_ram(bridge_t *bridge)
-{
-    int                     largest_working_size = 0;
-    int                     num_entries, entry;
-    int                     i, j;
-    bridgereg_t             old_enable, new_enable;
-    int                     s;
-
-    /* Probe SSRAM to determine its size. */
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-    bridge->b_int_enable = new_enable;
-
-    for (i = 1; i < ATE_NUM_SIZES; i++) {
-	/* Try writing a value */
-	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
-
-	/* Guard against wrap */
-	for (j = 1; j < i; j++)
-	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
-
-	/* See if value was written */
-	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
-	    largest_working_size = i;
-    }
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * ensure that we write and read without any interruption.
-     * The read following the write is required for the Bridge war
-     */
-
-    s = splhi();
-    bridge->b_wid_control = (bridge->b_wid_control
-	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
-	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
-    bridge->b_wid_control;		/* inval addr bug war */
-    splx(s);
-
-    num_entries = ATE_NUM_ENTRIES(largest_working_size);
-
-#if PCIBR_ATE_DEBUG
-    if (num_entries)
-	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
-    else
-	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
-#endif
-
-    /* Initialize external mapping entries */
-    for (entry = 0; entry < num_entries; entry++)
-	bridge->b_ext_ate_ram[entry] = 0;
-
-    return (num_entries);
-}
-
-/*
- * Allocate "count" contiguous Bridge Address Translation Entries
- * on the specified bridge to be used for PCI to XTALK mappings.
- * Indices in rm map range from 1..num_entries.  Indicies returned
- * to caller range from 0..num_entries-1.
- *
- * Return the start index on success, -1 on failure.
- */
-LOCAL int
-pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
-{
-    int                     index = 0;
-
-    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
-/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
-
-    if (!index && pcibr_soft->bs_ext_ate_map)
-	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
-
-    /* rmalloc manages resources in the 1..n
-     * range, with 0 being failure.
-     * pcibr_ate_alloc manages resources
-     * in the 0..n-1 range, with -1 being failure.
-     */
-    return index - 1;
-}
-
-LOCAL void
-pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
-/* Who says there's no such thing as a free meal? :-) */
-{
-    /* note the "+1" since rmalloc handles 1..n but
-     * we start counting ATEs at zero.
-     */
-/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
-
-    rmfree((index < pcibr_soft->bs_int_ate_size)
-	   ? pcibr_soft->bs_int_ate_map
-	   : pcibr_soft->bs_ext_ate_map,
-	   count, index + 1);
-}
-
-LOCAL pcibr_info_t
-pcibr_info_get(devfs_handle_t vhdl)
-{
-    return (pcibr_info_t) pciio_info_get(vhdl);
-}
-
-pcibr_info_t
-pcibr_device_info_new(
-			 pcibr_soft_t pcibr_soft,
-			 pciio_slot_t slot,
-			 pciio_function_t rfunc,
-			 pciio_vendor_id_t vendor,
-			 pciio_device_id_t device)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_function_t        func;
-    int                     ibit;
-
-    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
-
-    NEW(pcibr_info);
-    pciio_device_info_new(&pcibr_info->f_c,
-			  pcibr_soft->bs_vhdl,
-			  slot, rfunc,
-			  vendor, device);
-
-    if (slot != PCIIO_SLOT_NONE) {
-
-	/*
-	 * Currently favored mapping from PCI
-	 * slot number and INTA/B/C/D to Bridge
-	 * PCI Interrupt Bit Number:
-	 *
-	 *     SLOT     A B C D
-	 *      0       0 4 0 4
-	 *      1       1 5 1 5
-	 *      2       2 6 2 6
-	 *      3       3 7 3 7
-	 *      4       4 0 4 0
-	 *      5       5 1 5 1
-	 *      6       6 2 6 2
-	 *      7       7 3 7 3
-	 *
-	 * XXX- allow pcibr_hints to override default
-	 * XXX- allow ADMIN to override pcibr_hints
-	 */
-	for (ibit = 0; ibit < 4; ++ibit)
-	    pcibr_info->f_ibit[ibit] =
-		(slot + 4 * ibit) & 7;
-
-	/*
-	 * Record the info in the sparse func info space.
-	 */
-	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
-	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
-    }
-    return pcibr_info;
-}
-
-void
-pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pcibr_info_t	pcibr_info;
-    pciio_function_t	func;
-    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
-    int			nfunc = slotp->bss_ninfo;
-
-
-    for (func = 0; func < nfunc; func++) {
-	pcibr_info = slotp->bss_infos[func];
-
-	if (!pcibr_info) 
-	    continue;
-
-	slotp->bss_infos[func] = 0;
-	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
-	pciio_device_info_free(&pcibr_info->f_c);
-	DEL(pcibr_info);
-    }
-
-    /* Clear the DEVIO(x) for this slot */
-    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
-    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_device  = 0;
-
-    
-    /* Reset the mapping usage counters */
-    slotp->bss_pmu_uctr = 0;
-    slotp->bss_d32_uctr = 0;
-    slotp->bss_d64_uctr = 0;
-
-    /* Clear the Direct translation info */
-    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
-    slotp->bss_d64_flags = 0;
-    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_d32_flags = 0;
-
-    /* Clear out shadow info necessary for the external SSRAM workaround */
-    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
-    slotp->bss_cmd_pointer = 0;
-    slotp->bss_cmd_shadow = 0;
-
-}
-
-/* 
- * PCI_ADDR_SPACE_LIMITS_LOAD
- *	Gets the current values of 
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
-    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
-    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
-    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
-    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
-    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
-    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
-/*
- * PCI_ADDR_SPACE_LIMITS_STORE
- *	Sets the current values of
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_STORE()			\
-    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
-    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
-    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
-    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
-    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
-    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
-
-#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
-    printf("+++++++++++++++++++++++\n"			\
-	   "IO base 0x%x last 0x%x\n"			\
-	   "SWIN base 0x%x last 0x%x\n"			\
-	   "MEM base 0x%x last 0x%x\n"			\
-	   "+++++++++++++++++++++++\n",			\
-	   pcibr_soft->bs_spinfo.pci_io_base,		\
-	   pcibr_soft->bs_spinfo.pci_io_last,		\
-	   pcibr_soft->bs_spinfo.pci_swin_base,		\
-	   pcibr_soft->bs_spinfo.pci_swin_last,		\
-	   pcibr_soft->bs_spinfo.pci_mem_base,		\
-	   pcibr_soft->bs_spinfo.pci_mem_last);
-
-/*
- * pcibr_slot_info_init
- *	Probe for this slot and see if it is populated.
- *	If it is populated initialize the generic PCI infrastructural
- * 	information associated with this particular PCI device.
- */
-int
-pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
-		     pciio_slot_t 	slot)
-{
-    pcibr_soft_t	    pcibr_soft;
-    pcibr_info_h	    pcibr_infoh;
-    pcibr_info_t	    pcibr_info;
-    bridge_t		   *bridge;
-    cfg_p                   cfgw;
-    unsigned                idword;
-    unsigned                pfail;
-    unsigned                idwords[8];
-    pciio_vendor_id_t       vendor;
-    pciio_device_id_t       device;
-    unsigned                htype;
-#if !defined(CONFIG_IA64_SGI_SN1)
-    int			    nbars;
-#endif
-    cfg_p                   wptr;
-    int                     win;
-    pciio_space_t           space;
-    iopaddr_t		    pci_io_fb,	pci_io_fl;
-    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
-    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
-    int			    nfunc;
-    pciio_function_t	    rfunc;
-    int			    func;
-    devfs_handle_t	    conn_vhdl;
-    pcibr_soft_slot_t	    slotp;
-    
-    /* Get the basic software information required to proceed */
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft)
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-    if (!PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
-     * is done by the host slot then we are done.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);    
-    }
-
-    /* Check for a slot with any system critical functions */
-    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    /* Load the current values of allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-    
-    /* Try to read the device-id/vendor-id from the config space */
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-
-    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
-	return(ENODEV);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-    slotp->slot_status |= SLOT_POWER_UP;
-
-    vendor = 0xFFFF & idword;
-    /* If the vendor id is not valid then the slot is not populated
-     * and we are done.
-     */
-    if (vendor == 0xFFFF) 
-	return(ENODEV);			
-    
-    device = 0xFFFF & (idword >> 16);
-    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-
-    nfunc = 1;
-    rfunc = PCIIO_FUNC_NONE;
-    pfail = 0;
-
-    /* NOTE: if a card claims to be multifunction
-     * but only responds to config space 0, treat
-     * it as a unifunction card.
-     */
-
-    if (htype & 0x80) {		/* MULTIFUNCTION */
-	for (func = 1; func < 8; ++func) {
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    vendor = 0xFFFF & idwords[func];
-	    if (vendor == 0xFFFF) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    nfunc = func + 1;
-	    rfunc = 0;
-	}
-	cfgw = bridge->b_type0_cfg_dev[slot].l;
-    }
-    NEWA(pcibr_infoh, nfunc);
-    
-    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
-    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-    for (func = 0; func < nfunc; ++func) {
-	unsigned                cmd_reg;
-	
-	if (func) {
-	    if (pfail & (1 << func))
-		continue;
-	    
-	    idword = idwords[func];
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    
-	    device = 0xFFFF & (idword >> 16);
-	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-	    rfunc = func;
-	}
-	htype &= 0x7f;
-	if (htype != 0x00) {
-	    PRINT_WARNING("%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
-		    pcibr_soft->bs_name, slot, func, htype);
-#if defined(CONFIG_IA64_SGI_SN1)
-	    continue;
-#else
-	    nbars = 2;
-	} else {
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-	}
-#if DEBUG && ATTACH_DEBUG
-	PRINT_NOTICE( 
-		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
-		pcibr_soft->bs_name, slot, func, vendor, device);
-#endif	
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, rfunc, vendor, device);
-	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
-	if (func == 0)
-	    slotp->slot_conn = conn_vhdl;
-
-	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
-	
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win)
-#else
-	for (win = 0; win < nbars; ++win)
-#endif
-	{
-	    iopaddr_t               base, mask, code;
-	    size_t                  size;
-
-	    /*
-	     * GET THE BASE & SIZE OF THIS WINDOW:
-	     *
-	     * The low two or four bits of the BASE register
-	     * determines which address space we are in; the
-	     * rest is a base address. BASE registers
-	     * determine windows that are power-of-two sized
-	     * and naturally aligned, so we can get the size
-	     * of a window by writing all-ones to the
-	     * register, reading it back, and seeing which
-	     * bits are used for decode; the least
-	     * significant nonzero bit is also the size of
-	     * the window.
-	     *
-	     * WARNING: someone may already have allocated
-	     * some PCI space to this window, and in fact
-	     * PIO may be in process at this very moment
-	     * from another processor (or even from this
-	     * one, if we get interrupted)! So, if the BASE
-	     * already has a nonzero address, be generous
-	     * and use the LSBit of that address as the
-	     * size; this could overstate the window size.
-	     * Usually, when one card is set up, all are set
-	     * up; so, since we don't bitch about
-	     * overlapping windows, we are ok.
-	     *
-	     * UNFORTUNATELY, some cards do not clear their
-	     * BASE registers on reset. I have two heuristics
-	     * that can detect such cards: first, if the
-	     * decode enable is turned off for the space
-	     * that the window uses, we can disregard the
-	     * initial value. second, if the address is
-	     * outside the range that we use, we can disregard
-	     * it as well.
-	     *
-	     * This is looking very PCI generic. Except for
-	     * knowing how many slots and where their config
-	     * spaces are, this window loop and the next one
-	     * could probably be shared with other PCI host
-	     * adapters. It would be interesting to see if
-	     * this could be pushed up into pciio, when we
-	     * start supporting more PCI providers.
-	     */
-#ifdef LITTLE_ENDIAN
-	    base = wptr[((win*4)^4)/4];
-#else
-	    base = wptr[win];
-#endif
-
-	    if (base & PCI_BA_IO_SPACE) {
-		/* BASE is in I/O space. */
-		space = PCIIO_SPACE_IO;
-		mask = -4;
-		code = base & 3;
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		}
-	    } else {
-		/* BASE is in MEM space. */
-		space = PCIIO_SPACE_MEM;
-		mask = -16;
-		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		} else if (base & 0xC0000000) {
-		    base = 0;	/* outside permissable range */
-		} else if ((code == PCI_BA_MEM_64BIT) &&
-#ifdef LITTLE_ENDIAN
-			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
-#else 
-			   (wptr[win + 1] != 0)) {
-#endif /* LITTLE_ENDIAN */
-		    base = 0;	/* outside permissable range */
-		}
-	    }
-
-	    if (base != 0) {	/* estimate size */
-		size = base & -base;
-	    } else {		/* calculate size */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
-		size = wptr[((win*4)^4)/4];	/* get stored bits */
-#else 
-		wptr[win] = ~0;	/* turn on all bits */
-		size = wptr[win];	/* get stored bits */
-#endif /* LITTLE_ENDIAN */
-		size &= mask;	/* keep addr */
-		size &= -size;	/* keep lsbit */
-		if (size == 0)
-		    continue;
-	    }	
-
-	    pcibr_info->f_window[win].w_space = space;
-	    pcibr_info->f_window[win].w_base = base;
-	    pcibr_info->f_window[win].w_size = size;
-
-	    /*
-	     * If this window already has PCI space
-	     * allocated for it, "subtract" that space from
-	     * our running freeblocks. Don't worry about
-	     * overlaps in existing allocated windows; we
-	     * may be overstating their sizes anyway.
-	     */
-
-	    if (base && size) {
-		if (space == PCIIO_SPACE_IO) {
-		    pcibr_freeblock_sub(&pci_io_fb,
-					&pci_io_fl,
-					base, size);
-		} else {
-		    pcibr_freeblock_sub(&pci_lo_fb,
-					&pci_lo_fl,
-					base, size);
-		    pcibr_freeblock_sub(&pci_hi_fb,
-					&pci_hi_fl,
-					base, size);
-		}	
-	    }
-#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
-	    /*
-	     * IOC3 BASE_ADDR* BUG WORKAROUND
-	     *
-	     
-	     * If we write to BASE1 on the IOC3, the
-	     * data in BASE0 is replaced. The
-	     * original workaround was to remember
-	     * the value of BASE0 and restore it
-	     * when we ran off the end of the BASE
-	     * registers; however, a later
-	     * workaround was added (I think it was
-	     * rev 1.44) to avoid setting up
-	     * anything but BASE0, with the comment
-	     * that writing all ones to BASE1 set
-	     * the enable-parity-error test feature
-	     * in IOC3's SCR bit 14.
-	     *
-	     * So, unless we defer doing any PCI
-	     * space allocation until drivers
-	     * attach, and set up a way for drivers
-	     * (the IOC3 in paricular) to tell us
-	     * generically to keep our hands off
-	     * BASE registers, we gotta "know" about
-	     * the IOC3 here.
-	     *
-	     * Too bad the PCI folks didn't reserve the
-	     * all-zero value for 'no BASE here' (it is a
-	     * valid code for an uninitialized BASE in
-	     * 32-bit PCI memory space).
-	     */
-	    
-	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
-		(device == IOC3_DEVICE_ID_NUM))
-		break;
-#endif
-	    if (code == PCI_BA_MEM_64BIT) {
-		win++;		/* skip upper half */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
-#else 
-		wptr[win] = 0;	/* which must be zero */
-#endif /* LITTLE_ENDIAN */
-	    }
-	}				/* next win */
-    }				/* next func */
-
-    /* Store back the values for allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}					
-
-/*
- * pcibr_slot_info_free
- *	Remove all the PCI infrastructural information associated
- * 	with a particular PCI device.
- */
-int
-pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
-                     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    int			nfunc;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-    /* Clean out all the base registers */
-    bridge = pcibr_soft->bs_base;
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-    wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-    
-    for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) 
-#ifdef LITTLE_ENDIAN
-	wptr[((win*4)^4)/4] = 0;
-#else
-	wptr[win] = 0;
-#endif  /* LITTLE_ENDIAN */
-#endif	/* !CONFIG_IA64_SGI_SN1 */
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-
-    pcibr_device_info_free(pcibr_vhdl, slot);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    DELA(pcibr_infoh,nfunc);
-    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
-
-    return(0);
-}
-
-int as_debug = 0;
-/*
- * pcibr_slot_addr_space_init
- *	Reserve chunks of PCI address space as required by 
- * 	the base registers in the card.
- */
-int
-pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    iopaddr_t		pci_io_fb, pci_io_fl;
-    iopaddr_t		pci_lo_fb, pci_lo_fl;
-    iopaddr_t		pci_hi_fb, pci_hi_fl;
-    size_t              align;
-    iopaddr_t           mask;
-    int		    	nbars;
-    int		       	nfunc;
-    int			func;
-    int			win;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* Get the current values for the allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-
-    if (as_debug)
-#ifdef LATER
-    PCI_ADDR_SPACE_LIMITS_PRINT();
-#endif
-    /* allocate address space,
-     * for windows that have not been
-     * previously assigned.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);
-    }
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    if (nfunc < 1)
-	return(EINVAL);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    if (!pcibr_infoh)
-	return(EINVAL);
-
-    /*
-     * Try to make the DevIO windows not
-     * overlap by pushing the "io" and "hi"
-     * allocation areas up to the next one
-     * or two megabyte bound. This also
-     * keeps them from being zero.
-     *
-     * DO NOT do this with "pci_lo" since
-     * the entire "lo" area is only a
-     * megabyte, total ...
-     */
-    align = (slot < 2) ? 0x200000 : 0x100000;
-    mask = -align;
-    pci_io_fb = (pci_io_fb + align - 1) & mask;
-    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
-
-    for (func = 0; func < nfunc; ++func) {
-	cfg_p                   cfgw;
-	cfg_p                   wptr;
-	pciio_space_t           space;
-	iopaddr_t               base;
-	size_t                  size;
-	cfg_p                   pci_cfg_cmd_reg_p;
-	unsigned                pci_cfg_cmd_reg;
-	unsigned                pci_cfg_cmd_reg_add = 0;
-
-	pcibr_info = pcibr_infoh[func];
-
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-	
-	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	nbars = PCI_CFG_BASE_ADDRS;
-#else
-	if ((do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0)
-	    nbars = 2;
-	else
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-
-	for (win = 0; win < nbars; ++win) {
-
-	    space = pcibr_info->f_window[win].w_space;
-	    base = pcibr_info->f_window[win].w_base;
-	    size = pcibr_info->f_window[win].w_size;
-	    
-	    if (size < 1)
-		continue;
-
-	    if (base >= size) {
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
-			slot, func, win, space, base, base + size - 1);
-#endif
-		continue;		/* already allocated */
-	    }
-	    align = size;		/* ie. 0x00001000 */
-	    if (align < _PAGESZ)
-		align = _PAGESZ;	/* ie. 0x00004000 */
-	    mask = -align;		/* ie. 0xFFFFC000 */
-
-	    switch (space) {
-	    case PCIIO_SPACE_IO:
-		base = (pci_io_fb + align - 1) & mask;
-		if ((base + size) > pci_io_fl) {
-		    base = 0;
-		    break;
-		}
-		pci_io_fb = base + size;
-		break;
-		
-	    case PCIIO_SPACE_MEM:
-#ifdef LITTLE_ENDIAN
-		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
-#else
-		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
-#endif  /* LITTLE_ENDIAN */
-		    PCI_BA_MEM_1MEG) {
-		    /* allocate from 20-bit PCI space */
-		    base = (pci_lo_fb + align - 1) & mask;
-		    if ((base + size) > pci_lo_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_lo_fb = base + size;
-		} else {
-		    /* allocate from 32-bit or 64-bit PCI space */
-		    base = (pci_hi_fb + align - 1) & mask;
-		    if ((base + size) > pci_hi_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_hi_fb = base + size;
-		}
-		break;
-		
-	    default:
-		base = 0;
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d window %d had bad space code %d\n",
-			slot, win, space);
-#endif
-	    }
-	    pcibr_info->f_window[win].w_base = base;
-#ifdef LITTLE_ENDIAN
-	    wptr[((win*4)^4)/4] = base;
-#if DEBUG && PCI_DEBUG
-		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
-#endif
-#else
-	    wptr[win] = base;
-#endif  /* LITTLE_ENDIAN */
-
-#if DEBUG && PCI_DEBUG
-	    if (base >= size)
-		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
-			slot, func, win, space, base, base + size - 1);
-	    else
-		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
-			slot, func, win, size, space);
-#endif
-	}				/* next base */
-
-	/*
-	 * Allocate space for the EXPANSION ROM
-	 * NOTE: DO NOT DO THIS ON AN IOC3,
-	 * as it blows the system away.
-	 */
-	base = size = 0;
-	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
-	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
-
-	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
-#ifdef LITTLE_ENDIAN
-	    wptr[1] = 0xFFFFF000;
-	    mask = wptr[1];
-#else
-	    *wptr = 0xFFFFF000;
-	    mask = *wptr;
-#endif  /* LITTLE_ENDIAN */
-	    if (mask & 0xFFFFF000) {
-		size = mask & -mask;
-		align = size;
-		if (align < _PAGESZ)
-		    align = _PAGESZ;
-		mask = -align;
-		base = (pci_hi_fb + align - 1) & mask;
-		if ((base + size) > pci_hi_fl)
-		    base = size = 0;
-		else {
-		    pci_hi_fb = base + size;
-#ifdef LITTLE_ENDIAN
-		    wptr[1] = base;
-#else
-		    *wptr = base;
-#endif  /* LITTLE_ENDIAN */
-#if DEBUG && PCI_DEBUG
-		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
-			    pcibr_soft->bs_name, slot,
-			    base, base + size - 1);
-#endif
-		}
-	    }
-	}
-	pcibr_info->f_rbase = base;
-	pcibr_info->f_rsize = size;
-	
-	/*
-	 * if necessary, update the board's
-	 * command register to enable decoding
-	 * in the windows we added.
-	 *
-	 * There are some bits we always want to
-	 * be sure are set.
-	 */
-	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
-
-	/*
-	 * The Adaptec 1160 FC Controller WAR #767995:
-	 * The part incorrectly ignores the upper 32 bits of a 64 bit
-	 * address when decoding references to it's registers so to
-	 * keep it from responding to a bus cycle that it shouldn't
-	 * we only use I/O space to get at it's registers.  Don't
-	 * enable memory space accesses on that PCI device.
-	 */
-	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
-	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
-
-	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
-	    (pcibr_info->f_device != FCADP_DEVID))
-	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
-
-	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
-
-	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
-	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
-#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
-	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
-	    fast_back_to_back_enable = 0;
-#endif
-	pci_cfg_cmd_reg &= 0xFFFF;
-	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
-	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
-	
-    }				/* next func */
-
-    /* Now that we have allocated new chunks of PCI address spaces to this
-     * card we need to update the bookkeeping values which indicate
-     * the current PCI address space allocations.
-     */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}
-
-/*
- * pcibr_slot_device_init
- * 	Setup the device register in the bridge for this PCI slot.
- */
-int
-pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
-		       pciio_slot_t slot)
-{
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    bridgereg_t		 devreg;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * Adjustments to Device(x)
-     * and init of bss_device shadow
-     */
-    devreg = bridge->b_device[slot].reg;
-    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
-    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
-#ifdef LITTLE_ENDIAN
-    devreg |= BRIDGE_DEV_DEV_SWAP;
-#endif
-    pcibr_soft->bs_slot[slot].bss_device = devreg;
-    bridge->b_device[slot].reg = devreg;
-
-#if DEBUG && PCI_DEBUG
-	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
-#endif
-
-#if DEBUG && PCI_DEBUG
-    printk("pcibr: PCI space allocation done.\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_guest_info_init
- *	Setup the host/guest relations for a PCI slot.
- */
-int
-pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    pcibr_soft_slot_t	slotp;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    /* create info and verticies for guest slots;
-     * for compatibilitiy macros, create info
-     * for even unpopulated slots (but do not
-     * build verticies for them).
-     */
-    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
-	NEWA(pcibr_infoh, 1);
-	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
-	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
-	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-
-	if (pcibr_soft->bs_slot[slot].has_host) {
-	    slotp->slot_conn = pciio_device_info_register
-		(pcibr_vhdl, &pcibr_info->f_c);
-	}
-    }
-
-    /* generate host/guest relations
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	int  host = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
-
-	hwgraph_edge_add(slotp->slot_conn,
-			 host_slotp->slot_conn,
-			 EDGE_LBL_HOST);
-
-	/* XXX- only gives us one guest edge per
-	 * host. If/when we have a host with more than
-	 * one guest, we will need to figure out how
-	 * the host finds all its guests, and sorts
-	 * out which one is which.
-	 */
-	hwgraph_edge_add(host_slotp->slot_conn,
-			 slotp->slot_conn,
-			 EDGE_LBL_GUEST);
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_slot_initial_rrb_alloc
- *	Allocate a default number of rrbs for this slot on 
- * 	the two channels.  This is dictated by the rrb allocation
- * 	strategy routine defined per platform.
- */
-
-int
-pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
-			     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    int                 c0, c1;
-    int			r;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* How may RRBs are on this slot?
-     */
-    c0 = do_pcibr_rrb_count_valid(bridge, slot);
-    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
-
-#if PCIBR_RRB_DEBUG
-    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
-#endif
-
-    /* Do we really need any?
-     */
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    pcibr_info = pcibr_infoh[0];
-    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
-	!pcibr_soft->bs_slot[slot].has_host) {
-	if (c0 > 0)
-	    do_pcibr_rrb_free(bridge, slot, c0);
-	if (c1 > 0)
-	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
-	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
-	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
-	return(ENODEV);
-    }
-
-    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
-    pcibr_soft->bs_rrb_valid[slot] = c0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
-
-    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
-    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
-
-    r = 3 - (c0 + c1);
-
-    if (r > 0) {
-	pcibr_soft->bs_rrb_res[slot] = r;
-	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
-    }
-
-#if PCIBR_RRB_DEBUG
-    printk("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-    printk("\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_call_device_attach
- *	This calls the associated driver attach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    async_attach_t	aa = NULL;
-    int			func;
-    devfs_handle_t	xconn_vhdl,conn_vhdl;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-        return(EPERM);
-    }
-    
-    xconn_vhdl = pcibr_soft->bs_conn;
-    aa = async_attach_get_info(xconn_vhdl);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	/* If the PCI device has been disabled in the prom,
-	 * do not set it up for driver attach. NOTE: usrpci
-	 * and pciba will not "see" this connection point!
-	 */
-	if (device_admin_info_get(conn_vhdl, ADMIN_LBL_DISABLED)) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-	    PRINT_WARNING("pcibr_slot_call_device_attach: %v disabled\n", 
-		    conn_vhdl);
-#endif
-	    continue;
-	}
-#ifdef LATER
-	/*
-	 * Activate if and when we support cdl.
-	 */
-	if (aa)
-	    async_attach_add_info(conn_vhdl, aa);
-#endif	/* LATER */
-
-	error_func = pciio_device_attach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-        error = error_slot;
-
-    }				/* next func */
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
-    } else {
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_call_device_detach
- *	This calls the associated driver detach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    int			func;
-    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    if (pcibr_soft->bs_slot[slot].has_host)
-        return(EPERM);
-
-    /* Make sure that we do not detach a system critical function vertex */
-    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	error_func = pciio_device_detach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-	error = error_slot;
-
-    }				/* next func */
-
-    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
-    } else {
-        if (conn_vhdl != GRAPH_VERTEX_NONE) 
-            pcibr_device_unregister(conn_vhdl);
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_detach
- *	This is a place holder routine to keep track of all the
- *	slot-specific freeing that needs to be done.
- */
-int
-pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
-		  pciio_slot_t slot,
-		  int          drv_flags)
-{
-    int		  error;
-    
-    /* Call the device detach function */
-    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
-    return (error);
-
-}
-
-/*
- * pcibr_is_slot_sys_critical
- *      Check slot for any functions that are system critical.
- *      Return 1 if any are system critical or 0 otherwise.
- *
- *      This function will always return 0 when called by 
- *      pcibr_attach() because the system critical vertices 
- *      have not yet been set in the hwgraph.
- */
-int
-pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
-                      pciio_slot_t slot)
-{
-    pcibr_soft_t        pcibr_soft;
-    pcibr_info_h        pcibr_infoh;
-    pcibr_info_t        pcibr_info;
-    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
-    int                 nfunc;
-    int                 func;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-        return(0);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-        pcibr_info = pcibr_infoh[func];
-        if (!pcibr_info)
-            continue;
-
-        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-            continue;
-
-        conn_vhdl = pcibr_info->f_vertex;
-        if (is_sys_critical_vertex(conn_vhdl)) { 
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-            PRINT_WARNING("%v is a system critical device vertex\n", conn_vhdl);
-#else
-            PRINT_WARNING("%p is a system critical device vertex\n", conn_vhdl);
-#endif
-            return(1); 
-        }
-
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_device_unregister
- *	This frees up any hardware resources reserved for this PCI device
- * 	and removes any PCI infrastructural information setup for it.
- *	This is usually used at the time of shutting down of the PCI card.
- */
-int
-pcibr_device_unregister(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t	 pciio_info;
-    devfs_handle_t	 pcibr_vhdl;
-    pciio_slot_t	 slot;
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    int			 error_call;
-    int			 error = 0;
-
-    pciio_info = pciio_info_get(pconn_vhdl);
-
-    pcibr_vhdl = pciio_info_master_get(pciio_info);
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Clear all the hardware xtalk resources for this device */
-    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
-
-    /* Flush all the rrbs */
-    pcibr_rrb_flush(pconn_vhdl);
-
-    /* Free the rrbs allocated to this slot */
-    error_call = do_pcibr_rrb_free(bridge, slot, 
-		                   pcibr_soft->bs_rrb_valid[slot] +
-		                   pcibr_soft->bs_rrb_valid[slot + 
-                                   PCIBR_RRB_SLOT_VIRTUAL]);
-
-    if (error_call)
-        error = ERANGE;
-
-    pcibr_soft->bs_rrb_valid[slot] = 0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
-    pcibr_soft->bs_rrb_res[slot] = 0;
-
-    /* Flush the write buffers !! */
-    error_call = pcibr_wrb_flush(pconn_vhdl);
-
-    if (error_call)
-        error = error_call;
-
-    /* Clear the information specific to the slot */
-    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
-
-    if (error_call)
-        error = error_call;
-
-    return(error);
-    
-}
-
-/* 
- * build a convenience link path in the
- * form of ".../<iobrick>/bus/<busnum>"
- * 
- * returns 1 on success, 0 otherwise
- *
- * depends on hwgraph separator == '/'
- */
-int
-pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
-{
-        char dst[MAXDEVNAME];
-	char *dp = dst;
-        char *cp, *xp;
-        int widgetnum;
-        char pcibus[8];
-	devfs_handle_t nvtx, svtx;
-	int rv;
-
-#if DEBUG
-	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
-		slot, f_c);
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(f_c, dname, 256);
-		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
-	}
-#endif
-
-	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
-		return 0;
-
-	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
-
-	/* find the widget number */
-	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
-	if (xp == NULL)
-		return 0;
-	widgetnum = atoi(xp+7);
-	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
-		return 0;
-
-	/* remove "/pci/direct" from path */
-	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
-	if (cp == NULL)
-		return 0;
-	*cp = (char)NULL;
-
-	/* get the vertex for the widget */
-	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
-		return 0;
-
-	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
-
-	/* dst example now == /hw/module/001c02/Pbrick */
-
-	/* get the bus number */
-        strcat(dst, "/bus");
-        sprintf(pcibus, "%d", p_busnum[widgetnum]);
-
-	/* link to bus to widget */
-	rv = hwgraph_path_add(NULL, dp, &nvtx);
-	if (GRAPH_SUCCESS == rv)
-		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
-
-	return (rv == GRAPH_SUCCESS);
-}
-
-
-/*
- *    pcibr_attach: called every time the crosstalk
- *      infrastructure is asked to initialize a widget
- *      that matches the part number we handed to the
- *      registration routine above.
- */
-/*ARGSUSED */
-int
-pcibr_attach(devfs_handle_t xconn_vhdl)
-{
-    /* REFERENCED */
-    graph_error_t           rc;
-    devfs_handle_t            pcibr_vhdl;
-    devfs_handle_t            ctlr_vhdl;
-    bridge_t               *bridge = NULL;
-    bridgereg_t             id;
-    int                     rev;
-    pcibr_soft_t            pcibr_soft;
-    pcibr_info_t            pcibr_info;
-    xwidget_info_t          info;
-    xtalk_intr_t            xtalk_intr;
-    device_desc_t           dev_desc;
-    int                     slot;
-    int                     ibit;
-    devfs_handle_t            noslot_conn;
-    char                    devnm[MAXDEVNAME], *s;
-    pcibr_hints_t           pcibr_hints;
-    bridgereg_t             b_int_enable;
-    unsigned                rrb_fixed = 0;
-
-    iopaddr_t               pci_io_fb, pci_io_fl;
-    iopaddr_t               pci_lo_fb, pci_lo_fl;
-    iopaddr_t               pci_hi_fb, pci_hi_fl;
-
-    int                     spl_level;
-#ifdef LATER
-    char		    *nicinfo = (char *)0;
-#endif
-
-#if PCI_FBBE
-    int                     fast_back_to_back_enable;
-#endif
-    l1sc_t		    *scp;
-    nasid_t		    nasid;
-
-    async_attach_t          aa = NULL;
-
-    aa = async_attach_get_info(xconn_vhdl);
-
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
-    {
-	int pos;
-	char dname[256];
-	pos = devfs_generate_path(xconn_vhdl, dname, 256);
-	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
-    }
-#endif
-
-    /* Setup the PRB for the bridge in CONVEYOR BELT
-     * mode. PRBs are setup in default FIRE-AND-FORGET
-     * mode during the initialization.
-     */
-    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
-
-    bridge = (bridge_t *)
-	xtalk_piotrans_addr(xconn_vhdl, NULL,
-			    0, sizeof(bridge_t), 0);
-
-#ifndef MEDUSA_HACK
-    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
-	return -1;			/* someone else handles GIO bridges. */
-#endif
-
-#ifdef BRINGUP
-    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
-	NeedXbridgeSwap = 1;
-#endif
-
-    /*
-     * Create the vertex for the PCI bus, which we
-     * will also use to hold the pcibr_soft and
-     * which will be the "master" vertex for all the
-     * pciio connection points we will hang off it.
-     * This needs to happen before we call nic_bridge_vertex_info
-     * as we are some of the *_vmc functions need access to the edges.
-     *
-     * Opening this vertex will provide access to
-     * the Bridge registers themselves.
-     */
-    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
-    ASSERT(rc == GRAPH_SUCCESS);
-
-    ctlr_vhdl = NULL;
-    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
-                0, DEVFS_FL_AUTO_DEVNUM,
-                0, 0,
-                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-                &pcibr_fops, NULL);
-
-    ASSERT(ctlr_vhdl != NULL);
-
-    /*
-     * decode the nic, and hang its stuff off our
-     * connection point where other drivers can get
-     * at it.
-     */
-#ifdef LATER
-    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
-#endif
-
-    /*
-     * Get the hint structure; if some NIC callback
-     * marked this vertex as "hands-off" then we
-     * just return here, before doing anything else.
-     */
-    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
-
-    if (pcibr_hints && pcibr_hints->ph_hands_off)
-	return -1;			/* generic operations disabled */
-
-    id = bridge->b_wid_id;
-    rev = XWIDGET_PART_REV_NUM(id);
-
-    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
-
-    /*
-     * allocate soft state structure, fill in some
-     * fields, and hook it up to our vertex.
-     */
-    NEW(pcibr_soft);
-    BZERO(pcibr_soft, sizeof *pcibr_soft);
-    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
-
-    pcibr_soft->bs_conn = xconn_vhdl;
-    pcibr_soft->bs_vhdl = pcibr_vhdl;
-    pcibr_soft->bs_base = bridge;
-    pcibr_soft->bs_rev_num = rev;
-    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
-    if (is_xbridge(bridge)) {
-	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 1;
-    } else {
-	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 0;
-    }
-
-    nasid = NASID_GET(bridge);
-    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
-    pcibr_soft->bs_l1sc = scp;
-    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
-    pcibr_soft->bsi_err_intr = 0;
-
-    /* Bridges up through REV C
-     * are unable to set the direct
-     * byteswappers to BYTE_STREAM.
-     */
-    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
-	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
-	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
-    }
-#if PCIBR_SOFT_LIST
-    {
-	pcibr_list_p            self;
-
-	NEW(self);
-	self->bl_soft = pcibr_soft;
-	self->bl_vhdl = pcibr_vhdl;
-	self->bl_next = pcibr_list;
-	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
-    }
-#endif
-
-    /*
-     * get the name of this bridge vertex and keep the info. Use this
-     * only where it is really needed now: like error interrupts.
-     */
-    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
-    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
-    strcpy(pcibr_soft->bs_name, s);
-
-#if SHOW_REVS || DEBUG
-#if !DEBUG
-    if (kdebug)
-#endif
-	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
-		is_xbridge(bridge) ? "X" : "",
-		(rev == BRIDGE_PART_REV_A) ? "A" :
-		(rev == BRIDGE_PART_REV_B) ? "B" :
-		(rev == BRIDGE_PART_REV_C) ? "C" :
-		(rev == BRIDGE_PART_REV_D) ? "D" :
-		(rev == XBRIDGE_PART_REV_A) ? "A" :
-		(rev == XBRIDGE_PART_REV_B) ? "B" :
-		"unknown",
-		rev, pcibr_soft->bs_name);
-#endif
-
-    info = xwidget_info_get(xconn_vhdl);
-    pcibr_soft->bs_xid = xwidget_info_id_get(info);
-    pcibr_soft->bs_master = xwidget_info_master_get(info);
-    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
-
-    /*
-     * Init bridge lock.
-     */
-    spin_lock_init(&pcibr_soft->bs_lock);
-
-    /*
-     * If we have one, process the hints structure.
-     */
-    if (pcibr_hints) {
-	rrb_fixed = pcibr_hints->ph_rrb_fixed;
-
-	pcibr_soft->bs_rrb_fixed = rrb_fixed;
-
-	if (pcibr_hints->ph_intr_bits)
-	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
-
-	for (slot = 0; slot < 8; ++slot) {
-	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
-
-	    if (hslot < 0) {
-		pcibr_soft->bs_slot[slot].host_slot = slot;
-	    } else {
-		pcibr_soft->bs_slot[slot].has_host = 1;
-		pcibr_soft->bs_slot[slot].host_slot = hslot;
-	    }
-	}
-    }
-    /*
-     * set up initial values for state fields
-     */
-    for (slot = 0; slot < 8; ++slot) {
-	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
-	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
-    }
-
-    for (ibit = 0; ibit < 8; ++ibit) {
-	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
-							&(bridge->b_int_status);
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
-    }
-
-    /*
-     * connect up our error handler
-     */
-    xwidget_error_register(xconn_vhdl, pcibr_error_handler, pcibr_soft);
-
-    /*
-     * Initialize various Bridge registers.
-     */
-
-    /*
-     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
-     * to zero to avoid dropping stores. (#475347)
-     */
-    if (rev < BRIDGE_PART_REV_D)
-	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
-
-    /*
-     * Clear all pending interrupts.
-     */
-    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
-
-    /*
-     * Until otherwise set up,
-     * assume all interrupts are
-     * from slot 7.
-     */
-    bridge->b_int_device = (uint32_t) 0xffffffff;
-
-    {
-	bridgereg_t             dirmap;
-	paddr_t                 paddr;
-	iopaddr_t               xbase;
-	xwidgetnum_t            xport;
-	iopaddr_t               offset;
-	int                     num_entries = 0;
-	int                     entry;
-	cnodeid_t		cnodeid;
-	nasid_t			nasid;
-	char		       *node_val;
-	devfs_handle_t		node_vhdl;
-	char			vname[MAXDEVNAME];
-
-	/* Set the Bridge's 32-bit PCI to XTalk
-	 * Direct Map register to the most useful
-	 * value we can determine.  Note that we
-	 * must use a single xid for all of:
-	 *      direct-mapped 32-bit DMA accesses
-	 *      direct-mapped 64-bit DMA accesses
-	 *      DMA accesses through the PMU
-	 *      interrupts
-	 * This is the only way to guarantee that
-	 * completion interrupts will reach a CPU
-	 * after all DMA data has reached memory.
-	 * (Of course, there may be a few special
-	 * drivers/controllers that explicitly manage
-	 * this ordering problem.)
-	 */
-
-	cnodeid = 0;  /* default node id */
-	/*
-	 * Determine the base address node id to be used for all 32-bit
-	 * Direct Mapping I/O. The default is node 0, but this can be changed
-	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
-	 * attribute in the irix.sm config file. A device driver can obtain
-	 * this node value via a call to pcibr_get_dmatrans_node().
-	 */
-	node_val = device_admin_info_get(pcibr_vhdl, ADMIN_LBL_DMATRANS_NODE);
-	if (node_val != NULL) {
-	    node_vhdl = hwgraph_path_to_vertex(node_val);
-	    if (node_vhdl != GRAPH_VERTEX_NONE) {
-		cnodeid = nodevertex_to_cnodeid(node_vhdl);
-	    }
-	    if ((node_vhdl == GRAPH_VERTEX_NONE) || (cnodeid == CNODEID_NONE)) {
-		cnodeid = 0;
-		vertex_to_name(pcibr_vhdl, vname, sizeof(vname));
-		PRINT_WARNING( "Invalid hwgraph node path specified:\n     DEVICE_ADMIN: %s %s=%s\n",
-			vname, ADMIN_LBL_DMATRANS_NODE, node_val);
-	    }
-	}
-	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
-	paddr = NODE_OFFSET(nasid) + 0;
-
-	/* currently, we just assume that if we ask
-	 * for a DMA mapping to "zero" the XIO
-	 * host will transmute this into a request
-	 * for the lowest hunk of memory.
-	 */
-	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
-				    paddr, _PAGESZ, 0);
-
-	if (xbase != XIO_NOWHERE) {
-	    if (XIO_PACKED(xbase)) {
-		xport = XIO_PORT(xbase);
-		xbase = XIO_ADDR(xbase);
-	    } else
-		xport = pcibr_soft->bs_mxid;
-
-	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
-	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
-
-	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
-
-	    if (xbase)
-		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
-	    else if (offset >= (512 << 20))
-		dirmap |= BRIDGE_DIRMAP_ADD512;
-
-	    bridge->b_dir_map = dirmap;
-	}
-	/*
-	 * Set bridge's idea of page size according to the system's
-	 * idea of "IO page size".  TBD: The idea of IO page size
-	 * should really go away.
-	 */
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	spl_level = splhi();
-#if IOPGSIZE == 4096
-	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
-#elif IOPGSIZE == 16384
-	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
-#else
-	<<<Unable to deal with IOPGSIZE >>>;
-#endif
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(spl_level);
-
-	/* Initialize internal mapping entries */
-	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
-	    bridge->b_int_ate_ram[entry].wr = 0;
-
-	/*
-	 * Determine if there's external mapping SSRAM on this
-	 * bridge.  Set up Bridge control register appropriately,
-	 * inititlize SSRAM, and set software up to manage RAM
-	 * entries as an allocatable resource.
-	 *
-	 * Currently, we just use the rm* routines to manage ATE
-	 * allocation.  We should probably replace this with a
-	 * Best Fit allocator.
-	 *
-	 * For now, if we have external SSRAM, avoid using
-	 * the internal ssram: we can't turn PREFETCH on
-	 * when we use the internal SSRAM; and besides,
-	 * this also guarantees that no allocation will
-	 * straddle the internal/external line, so we
-	 * can increment ATE write addresses rather than
-	 * recomparing against BRIDGE_INTERNAL_ATES every
-	 * time.
-	 */
-	if (is_xbridge(bridge))
-		num_entries = 0;
-	else
-		num_entries = pcibr_init_ext_ate_ram(bridge);
-
-	/* we always have 128 ATEs (512 for Xbridge) inside the chip
-	 * even if disabled for debugging.
-	 */
-	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
-	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
-#endif
-
-	if (num_entries > pcibr_soft->bs_int_ate_size) {
-#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
-	    printk("pcibr_attach: disabling internal ATEs.\n");
-	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
-#endif
-	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
-	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
-			   num_entries - pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
-		    num_entries - pcibr_soft->bs_int_ate_size);
-#endif
-	}
-    }
-
-    {
-	bridgereg_t             dirmap;
-	iopaddr_t               xbase;
-
-	/*
-	 * now figure the *real* xtalk base address
-	 * that dirmap sends us to.
-	 */
-	dirmap = bridge->b_dir_map;
-	if (dirmap & BRIDGE_DIRMAP_OFF)
-	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
-			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
-	else if (dirmap & BRIDGE_DIRMAP_ADD512)
-	    xbase = 512 << 20;
-	else
-	    xbase = 0;
-
-	pcibr_soft->bs_dir_xbase = xbase;
-
-	/* it is entirely possible that we may, at this
-	 * point, have our dirmap pointing somewhere
-	 * other than our "master" port.
-	 */
-	pcibr_soft->bs_dir_xport =
-	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
-    }
-
-    /* pcibr sources an error interrupt;
-     * figure out where to send it.
-     *
-     * If any interrupts are enabled in bridge,
-     * then the prom set us up and our interrupt
-     * has already been reconnected in mlreset
-     * above.
-     *
-     * Need to set the D_INTR_ISERR flag
-     * in the dev_desc used for allocating the
-     * error interrupt, so our interrupt will
-     * be properly routed and prioritized.
-     *
-     * If our crosstalk provider wants to
-     * fix widget error interrupts to specific
-     * destinations, D_INTR_ISERR is how it
-     * knows to do this.
-     */
-
-    dev_desc = device_desc_dup(pcibr_vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Bridge error");
-
-    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
-    ASSERT(xtalk_intr != NULL);
-
-    device_desc_free(dev_desc);
-
-    pcibr_soft->bsi_err_intr = xtalk_intr;
-
-    /*
-     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
-     * in order to work around some addressing limitations.  In order
-     * for that fire wall to work properly, we need to make sure we
-     * start from a known clean state.
-     */
-    pcibr_clearwidint(bridge);
-
-    xtalk_intr_connect(xtalk_intr,
-		       (intr_func_t) pcibr_error_intr_handler,
-		       (intr_arg_t) pcibr_soft,
-		       (xtalk_intr_setfunc_t) pcibr_setwidint,
-		       (void *) bridge,
-		       (void *) 0);
-
-    /*
-     * now we can start handling error interrupts;
-     * enable all of them.
-     * NOTE: some PCI ints may already be enabled.
-     */
-    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
-
-
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
-
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * Depending on the rev of bridge, disable certain features.
-     * Easiest way seems to be to force the PCIBR_NOwhatever
-     * flag to be on for all DMA calls, which overrides any
-     * PCIBR_whatever flag or even the setting of whatever
-     * from the PCIIO_DMA_class flags (or even from the other
-     * PCIBR flags, since NO overrides YES).
-     */
-    pcibr_soft->bs_dma_flags = 0;
-
-    /* PREFETCH:
-     * Always completely disabled for REV.A;
-     * at "pcibr_prefetch_enable_rev", anyone
-     * asking for PCIIO_PREFETCH gets it.
-     * Between these two points, you have to ask
-     * for PCIBR_PREFETCH, which promises that
-     * your driver knows about known Bridge WARs.
-     */
-    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
-	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
-    else if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
-
-    /* WRITE_GATHER:
-     * Disabled up to but not including the
-     * rev number in pcibr_wg_enable_rev. There
-     * is no "WAR range" as with prefetch.
-     */
-    if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
-
-    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
-    pciio_provider_startup(pcibr_vhdl);
-
-    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
-    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
-
-    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
-    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
-
-    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
-    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
-
-
-    PCI_ADDR_SPACE_LIMITS_STORE();
-
-    /* build "no-slot" connection point
-     */
-    pcibr_info = pcibr_device_info_new
-	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
-	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-    noslot_conn = pciio_device_info_register
-	(pcibr_vhdl, &pcibr_info->f_c);
-
-    /* Remember the no slot connection point info for tearing it
-     * down during detach.
-     */
-    pcibr_soft->bs_noslot_conn = noslot_conn;
-    pcibr_soft->bs_noslot_info = pcibr_info;
-#if PCI_FBBE
-    fast_back_to_back_enable = 1;
-#endif
-
-#if PCI_FBBE
-    if (fast_back_to_back_enable) {
-	/*
-	 * All devices on the bus are capable of fast back to back, so
-	 * we need to set the fast back to back bit in all devices on
-	 * the bus that are capable of doing such accesses.
-	 */
-    }
-#endif
-
-#ifdef LATER
-    /* If the bridge has been reset then there is no need to reset
-     * the individual PCI slots.
-     */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Reset all the slots */
-	(void)pcibr_slot_reset(pcibr_vhdl, slot);
-#endif
-
-    for (slot = 0; slot < 8; ++slot)
-	/* Find out what is out there */
-	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up the address space for this slot in the pci land */
-	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup the device register */
-	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
-
-#ifndef __ia64
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up convenience links */
-	if (is_xbridge(bridge))
-		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
-			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
-#endif
-#endif
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup host/guest relations */
-	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Initial RRB management */
-	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
-
-    /* driver attach routines should be called out from generic linux code */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Call the device attach */
-	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
-
-    /*
-     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
-     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
-     */
-    if (pcibr_soft->bs_moduleid > 0) {
-	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
-	case 'p':		/* Pbrick */
-		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		break;
-	case 'i':		/* Ibrick */
-	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
-		if (pcibr_soft->bs_xid == 0xe) {
-			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		}
-		else {
-		    	/* allocate one RRB for the serial port */
-			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
-		}
-		break;
-	} /* switch */
-    }
-
-#ifdef LATER
-    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
-	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-#if PCIBR_RRB_DEBUG
-	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
-
-	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
-		pcibr_vhdl,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-
-	for (slot = 0; slot < 8; ++slot)
-	    printf("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-
-	printf("\n");
-#endif
-    }
-#else
-	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
-#endif
-
-    if (aa)
-	    async_attach_add_info(noslot_conn, aa);
-
-    pciio_device_attach(noslot_conn, 0);
-
-
-    /* 
-     * Tear down pointer to async attach info -- async threads for
-     * bridge's descendants may be running but the bridge's work is done.
-     */
-    if (aa)
-	    async_attach_del_info(xconn_vhdl);
-
-    return 0;
-}
-/*
- * pcibr_detach:
- *	Detach the bridge device from the hwgraph after cleaning out all the 
- *	underlying vertices.
- */
-int
-pcibr_detach(devfs_handle_t xconn)
-{
-    pciio_slot_t	slot;
-    devfs_handle_t	pcibr_vhdl;
-    pcibr_soft_t	pcibr_soft;
-    bridge_t		*bridge;
-
-    /* Get the bridge vertex from its xtalk connection point */
-    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
-	return(1);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Disable the interrupts from the bridge */
-    bridge->b_int_enable = 0;
-
-    /* Detach all the PCI devices talking to this bridge */
-    for(slot = 0; slot < 8; slot++) {
-#ifdef DEBUG
-	printk("pcibr_device_detach called for %p/%d\n",
-		pcibr_vhdl,slot);
-#endif
-	pcibr_slot_detach(pcibr_vhdl, slot, 0);
-    }
-
-    /* Unregister the no-slot connection point */
-    pciio_device_info_unregister(pcibr_vhdl,
-				 &(pcibr_soft->bs_noslot_info->f_c));
-
-    spin_lock_destroy(&pcibr_soft->bs_lock);
-    kfree(pcibr_soft->bs_name);
-    
-    /* Error handler gets unregistered when the widget info is 
-     * cleaned 
-     */
-    /* Free the soft ATE maps */
-    if (pcibr_soft->bs_int_ate_map)
-	rmfreemap(pcibr_soft->bs_int_ate_map);
-    if (pcibr_soft->bs_ext_ate_map)
-	rmfreemap(pcibr_soft->bs_ext_ate_map);
-
-    /* Disconnect the error interrupt and free the xtalk resources 
-     * associated with it.
-     */
-    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
-    xtalk_intr_free(pcibr_soft->bsi_err_intr);
-
-    /* Clear the software state maintained by the bridge driver for this
-     * bridge.
-     */
-    DEL(pcibr_soft);
-    /* Remove the Bridge revision labelled info */
-    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
-    /* Remove the character device associated with this bridge */
-    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
-    /* Remove the PCI bridge vertex */
-    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
-
-    return(0);
-}
-
-int
-pcibr_asic_rev(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t            pcibr_vhdl;
-    arbitrary_info_t        ainfo;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
-	return -1;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
-	return -1;
-
-    return (int) ainfo;
-}
-
-int
-pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t  slot;
-    slot = pciio_info_slot_get(pciio_info);
-    pcibr_device_write_gather_flush(pcibr_soft, slot);
-    return 0;
-}
-
-/* =====================================================================
- *    PIO MANAGEMENT
- */
-
-LOCAL iopaddr_t
-pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
-		      pciio_slot_t slot,
-		      pciio_space_t space,
-		      iopaddr_t pci_addr,
-		      size_t req_size,
-		      unsigned flags)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    unsigned                bar;	/* which BASE reg on device is decoding */
-    iopaddr_t               xio_addr = XIO_NOWHERE;
-
-    pciio_space_t           wspace;	/* which space device is decoding */
-    iopaddr_t               wbase;	/* base of device decode on PCI */
-    size_t                  wsize;	/* size of device decode on PCI */
-
-    int                     try;	/* DevIO(x) window scanning order control */
-    int                     win;	/* which DevIO(x) window is being used */
-    pciio_space_t           mspace;	/* target space for devio(x) register */
-    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
-    size_t                  msize;	/* size of devio(x) mapped area on PCI */
-    size_t                  mmask;	/* addr bits stored in Device(x) */
-
-    unsigned long           s;
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	slot = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
-    }
-    if (space == PCIIO_SPACE_NONE)
-	goto done;
-
-    if (space == PCIIO_SPACE_CFG) {
-	/*
-	 * Usually, the first mapping
-	 * established to a PCI device
-	 * is to its config space.
-	 *
-	 * In any case, we definitely
-	 * do NOT need to worry about
-	 * PCI BASE registers, and
-	 * MUST NOT attempt to point
-	 * the DevIO(x) window at
-	 * this access ...
-	 */
-	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
-	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
-	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
-
-	goto done;
-    }
-    if (space == PCIIO_SPACE_ROM) {
-	/* PIO to the Expansion Rom.
-	 * Driver is responsible for
-	 * enabling and disabling
-	 * decodes properly.
-	 */
-	wbase = pcibr_info->f_rbase;
-	wsize = pcibr_info->f_rsize;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	pci_addr += wbase;
-	space = PCIIO_SPACE_MEM;
-    }
-    /*
-     * reduce window mappings to raw
-     * space mappings (maybe allocating
-     * windows), and try for DevIO(x)
-     * usage (setting it if it is available).
-     */
-    bar = space - PCIIO_SPACE_WIN0;
-    if (bar < 6) {
-	wspace = pcibr_info->f_window[bar].w_space;
-	if (wspace == PCIIO_SPACE_NONE)
-	    goto done;
-
-	/* get PCI base and size */
-	wbase = pcibr_info->f_window[bar].w_base;
-	wsize = pcibr_info->f_window[bar].w_size;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	/* shift from window relative to
-	 * decoded space relative.
-	 */
-	pci_addr += wbase;
-	space = wspace;
-    } else
-	bar = -1;
-
-    /* Scan all the DevIO(x) windows twice looking for one
-     * that can satisfy our request. The first time through,
-     * only look at assigned windows; the second time, also
-     * look at PCIIO_SPACE_NONE windows. Arrange the order
-     * so we always look at our own window first.
-     *
-     * We will not attempt to satisfy a single request
-     * by concatinating multiple windows.
-     */
-    for (try = 0; try < 16; ++try) {
-	bridgereg_t             devreg;
-	unsigned                offset;
-
-	win = (try + slot) % 8;
-
-	/* If this DevIO(x) mapping area can provide
-	 * a mapping to this address, use it.
-	 */
-	msize = (win < 2) ? 0x200000 : 0x100000;
-	mmask = -msize;
-	if (space != PCIIO_SPACE_IO)
-	    mmask &= 0x3FFFFFFF;
-
-	offset = pci_addr & (msize - 1);
-
-	/* If this window can't possibly handle that request,
-	 * go on to the next window.
-	 */
-	if (((pci_addr & (msize - 1)) + req_size) > msize)
-	    continue;
-
-	devreg = pcibr_soft->bs_slot[win].bss_device;
-
-	/* Is this window "nailed down"?
-	 * If not, maybe we can use it.
-	 * (only check this the second time through)
-	 */
-	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
-	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
-
-	    /* If this is the primary DevIO(x) window
-	     * for some other device, skip it.
-	     */
-	    if ((win != slot) &&
-		(PCIIO_VENDOR_ID_NONE !=
-		 pcibr_soft->bs_slot[win].bss_vendor_id))
-		continue;
-
-	    /* It's a free window, and we fit in it.
-	     * Set up Device(win) to our taste.
-	     */
-	    mbase = pci_addr & mmask;
-
-	    /* check that we would really get from
-	     * here to there.
-	     */
-	    if ((mbase | offset) != pci_addr)
-		continue;
-
-	    devreg &= ~BRIDGE_DEV_OFF_MASK;
-	    if (space != PCIIO_SPACE_IO)
-		devreg |= BRIDGE_DEV_DEV_IO_MEM;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
-	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
-
-	    /* default is WORD_VALUES.
-	     * if you specify both,
-	     * operation is undefined.
-	     */
-	    if (flags & PCIIO_BYTE_STREAM)
-		devreg |= BRIDGE_DEV_DEV_SWAP;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_SWAP;
-
-	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
-		bridge->b_device[win].reg = devreg;
-		pcibr_soft->bs_slot[win].bss_device = devreg;
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-
-#if DEBUG && PCI_DEBUG
-		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
-#endif
-	    }
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
-	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
-		    __FUNCTION__, __LINE__, space, space_desc,
-		    pci_addr, pci_addr + req_size - 1,
-		    slot, win, devreg);
-#endif
-
-	    goto done;
-	}				/* endif DevIO(x) not pointed */
-	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
-
-	/* Now check for request incompat with DevIO(x)
-	 */
-	if ((mspace != space) ||
-	    (pci_addr < mbase) ||
-	    ((pci_addr + req_size) > (mbase + msize)) ||
-	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
-	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
-	    continue;
-
-	/* DevIO(x) window is pointed at PCI space
-	 * that includes our target. Calculate the
-	 * final XIO address, release the lock and
-	 * return.
-	 */
-	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
-		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
-#endif
-	goto done;
-    }
-
-    switch (space) {
-	/*
-	 * Accesses to device decode
-	 * areas that do a not fit
-	 * within the DevIO(x) space are
-	 * modified to be accesses via
-	 * the direct mapping areas.
-	 *
-	 * If necessary, drivers can
-	 * explicitly ask for mappings
-	 * into these address spaces,
-	 * but this should never be needed.
-	 */
-    case PCIIO_SPACE_MEM:		/* "mem space" */
-    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM32_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
-	break;
-
-    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM64_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
-	break;
-
-    case PCIIO_SPACE_IO:		/* "i/o space" */
-	/* Bridge Hardware Bug WAR #482741:
-	 * The 4G area that maps directly from
-	 * XIO space to PCI I/O space is busted
-	 * until Bridge Rev D.
-	 */
-	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
-	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
-	     BRIDGE_PCI_IO_LIMIT))
-	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
-	break;
-    }
-
-    /* Check that "Direct PIO" byteswapping matches,
-     * try to change it if it does not.
-     */
-    if (xio_addr != XIO_NOWHERE) {
-	unsigned                bst;	/* nonzero to set bytestream */
-	unsigned               *bfp;	/* addr of record of how swapper is set */
-	unsigned                swb;	/* which control bit to mung */
-	unsigned                bfo;	/* current swapper setting */
-	unsigned                bfn;	/* desired swapper setting */
-
-	bfp = ((space == PCIIO_SPACE_IO)
-	       ? (&pcibr_soft->bs_pio_end_io)
-	       : (&pcibr_soft->bs_pio_end_mem));
-
-	bfo = *bfp;
-
-	bst = flags & PCIIO_BYTE_STREAM;
-
-	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
-
-	if (bfn == bfo) {		/* we already match. */
-	    ;
-	} else if (bfo != 0) {		/* we have a conflict. */
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
-		    space, 
-		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	    xio_addr = XIO_NOWHERE;
-	} else {			/* OK to make the change. */
-	    bridgereg_t             octl, nctl;
-
-	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
-	    octl = bridge->b_wid_control;
-	    nctl = bst ? octl | swb : octl & ~swb;
-
-	    if (octl != nctl)		/* make the change if any */
-		bridge->b_wid_control = nctl;
-
-	    *bfp = bfn;			/* record the assignment */
-
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
-		    space, 
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	}
-    }
-  done:
-    pcibr_unlock(pcibr_soft, s);
-    return xio_addr;
-}
-
-/*ARGSUSED6 */
-pcibr_piomap_t
-pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   pciio_space_t space,
-		   iopaddr_t pci_addr,
-		   size_t req_size,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    pcibr_piomap_t         *mapptr;
-    pcibr_piomap_t          maplist;
-    pcibr_piomap_t          pcibr_piomap;
-    iopaddr_t               xio_addr;
-    xtalk_piomap_t          xtalk_piomap;
-    unsigned long           s;
-
-    /* Make sure that the req sizes are non-zero */
-    if ((req_size < 1) || (req_size_max < 1))
-	return NULL;
-
-    /*
-     * Code to translate slot/space/addr
-     * into xio_addr is common between
-     * this routine and pcibr_piotrans_addr.
-     */
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    /* Check the piomap list to see if there is already an allocated
-     * piomap entry but not in use. If so use that one. Otherwise
-     * allocate a new piomap entry and add it to the piomap list
-     */
-    mapptr = &(pcibr_info->f_piomap);
-
-    s = pcibr_lock(pcibr_soft);
-    for (pcibr_piomap = *mapptr;
-	 pcibr_piomap != NULL;
-	 pcibr_piomap = pcibr_piomap->bp_next) {
-	if (pcibr_piomap->bp_mapsz == 0)
-	    break;
-    }
-
-    if (pcibr_piomap)
-	mapptr = NULL;
-    else {
-	pcibr_unlock(pcibr_soft, s);
-	NEW(pcibr_piomap);
-    }
-
-    pcibr_piomap->bp_dev = pconn_vhdl;
-    pcibr_piomap->bp_slot = pciio_slot;
-    pcibr_piomap->bp_flags = flags;
-    pcibr_piomap->bp_space = space;
-    pcibr_piomap->bp_pciaddr = pci_addr;
-    pcibr_piomap->bp_mapsz = req_size;
-    pcibr_piomap->bp_soft = pcibr_soft;
-    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
-
-    if (mapptr) {
-	s = pcibr_lock(pcibr_soft);
-	maplist = *mapptr;
-	pcibr_piomap->bp_next = maplist;
-	*mapptr = pcibr_piomap;
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-
-    if (pcibr_piomap) {
-	xtalk_piomap =
-	    xtalk_piomap_alloc(xconn_vhdl, 0,
-			       xio_addr,
-			       req_size, req_size_max,
-			       flags & PIOMAP_FLAGS);
-	if (xtalk_piomap) {
-	    pcibr_piomap->bp_xtalk_addr = xio_addr;
-	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
-	} else {
-	    pcibr_piomap->bp_mapsz = 0;
-	    pcibr_piomap = 0;
-	}
-    }
-    return pcibr_piomap;
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
-    pcibr_piomap->bp_xtalk_pio = 0;
-    pcibr_piomap->bp_mapsz = 0;
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
-		  iopaddr_t pci_addr,
-		  size_t req_size)
-{
-    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
-			     pcibr_piomap->bp_xtalk_addr +
-			     pci_addr - pcibr_piomap->bp_pciaddr,
-			     req_size);
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    pciio_space_t space,
-		    iopaddr_t pci_addr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    iopaddr_t               xio_addr;
-
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
-}
-
-/*
- * PIO Space allocation and management.
- *      Allocate and Manage the PCI PIO space (mem and io space)
- *      This routine is pretty simplistic at this time, and
- *      does pretty trivial management of allocation and freeing..
- *      The current scheme is prone for fragmentation..
- *      Change the scheme to use bitmaps.
- */
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
-		     device_desc_t dev_desc,
-		     pciio_space_t space,
-		     size_t req_size,
-		     size_t alignment)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-
-    iopaddr_t              *pciaddr, *pcilast;
-    iopaddr_t               start_addr;
-    size_t                  align_mask;
-
-    /*
-     * Check for proper alignment
-     */
-    ASSERT(alignment >= NBPP);
-    ASSERT((alignment & (alignment - 1)) == 0);
-
-    align_mask = alignment - 1;
-    s = pcibr_lock(pcibr_soft);
-
-    /*
-     * First look if a previously allocated chunk exists.
-     */
-    if ((piosp = pcibr_info->f_piospace)) {
-	/*
-	 * Look through the list for a right sized free chunk.
-	 */
-	do {
-	    if (piosp->free &&
-		(piosp->space == space) &&
-		(piosp->count >= req_size) &&
-		!(piosp->start & align_mask)) {
-		piosp->free = 0;
-		pcibr_unlock(pcibr_soft, s);
-		return piosp->start;
-	    }
-	    piosp = piosp->next;
-	} while (piosp);
-    }
-    ASSERT(!piosp);
-
-    switch (space) {
-    case PCIIO_SPACE_IO:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
-	break;
-    case PCIIO_SPACE_MEM:
-    case PCIIO_SPACE_MEM32:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
-	break;
-    default:
-	ASSERT(0);
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-
-    start_addr = *pciaddr;
-
-    /*
-     * Align start_addr.
-     */
-    if (start_addr & align_mask)
-	start_addr = (start_addr + align_mask) & ~align_mask;
-
-    if ((start_addr + req_size) > *pcilast) {
-	/*
-	 * If too big a request, reject it.
-	 */
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    *pciaddr = (start_addr + req_size);
-
-    NEW(piosp);
-    piosp->free = 0;
-    piosp->space = space;
-    piosp->start = start_addr;
-    piosp->count = req_size;
-    piosp->next = pcibr_info->f_piospace;
-    pcibr_info->f_piospace = piosp;
-
-    pcibr_unlock(pcibr_soft, s);
-    return start_addr;
-}
-
-/*ARGSUSED */
-void
-pcibr_piospace_free(devfs_handle_t pconn_vhdl,
-		    pciio_space_t space,
-		    iopaddr_t pciaddr,
-		    size_t req_size)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-    char                    name[1024];
-
-    /*
-     * Look through the bridge data structures for the pciio_piospace_t
-     * structure corresponding to  'pciaddr'
-     */
-    s = pcibr_lock(pcibr_soft);
-    piosp = pcibr_info->f_piospace;
-    while (piosp) {
-	/*
-	 * Piospace free can only be for the complete
-	 * chunk and not parts of it..
-	 */
-	if (piosp->start == pciaddr) {
-	    if (piosp->count == req_size)
-		break;
-	    /*
-	     * Improper size passed for freeing..
-	     * Print a message and break;
-	     */
-	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
-	    PRINT_WARNING("pcibr_piospace_free: error");
-	    PRINT_WARNING("Device %s freeing size (0x%lx) different than allocated (0x%lx)",
-					name, req_size, piosp->count);
-	    PRINT_WARNING("Freeing 0x%lx instead", piosp->count);
-	    break;
-	}
-	piosp = piosp->next;
-    }
-
-    if (!piosp) {
-	PRINT_WARNING(
-		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
-		pciaddr, req_size);
-	pcibr_unlock(pcibr_soft, s);
-	return;
-    }
-    piosp->free = 1;
-    pcibr_unlock(pcibr_soft, s);
-    return;
-}
-
-/* =====================================================================
- *    DMA MANAGEMENT
- *
- *      The Bridge ASIC provides three methods of doing
- *      DMA: via a "direct map" register available in
- *      32-bit PCI space (which selects a contiguous 2G
- *      address space on some other widget), via
- *      "direct" addressing via 64-bit PCI space (all
- *      destination information comes from the PCI
- *      address, including transfer attributes), and via
- *      a "mapped" region that allows a bunch of
- *      different small mappings to be established with
- *      the PMU.
- *
- *      For efficiency, we most prefer to use the 32-bit
- *      direct mapping facility, since it requires no
- *      resource allocations. The advantage of using the
- *      PMU over the 64-bit direct is that single-cycle
- *      PCI addressing can be used; the advantage of
- *      using 64-bit direct over PMU addressing is that
- *      we do not have to allocate entries in the PMU.
- */
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Direct Map attribute bits.
- */
-LOCAL iopaddr_t
-pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
-{
-    iopaddr_t               attributes = 0;
-
-    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
-#ifdef LATER
-    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
-#endif
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
-	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
-	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    /* the swap bit is in the address attributes for xbridge */
-    if (pcibr_soft->bs_xbridge) {
-    	if (flags & PCIIO_BYTE_STREAM)
-        	attributes |= PCI64_ATTR_SWAP;
-    	if (flags & PCIIO_WORD_VALUES)
-        	attributes &= ~PCI64_ATTR_SWAP;
-    }
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= PCI64_ATTR_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~PCI64_ATTR_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= PCI64_ATTR_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~PCI64_ATTR_PREC;
-
-    if (flags & PCIBR_VCHAN1)
-	attributes |= PCI64_ATTR_VIRTUAL;
-    if (flags & PCIBR_VCHAN0)
-	attributes &= ~PCI64_ATTR_VIRTUAL;
-
-    return (attributes);
-}
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Address Translation Entry attribute bits.
- */
-LOCAL bridge_ate_t
-pcibr_flags_to_ate(unsigned flags)
-{
-    bridge_ate_t            attributes;
-
-    /* default if nothing specified:
-     * NOBARRIER
-     * NOPREFETCH
-     * NOPRECISE
-     * COHERENT
-     * Plus the valid bit
-     */
-    attributes = ATE_CO | ATE_V;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~ATE_BAR;		/* no barrier */
-	attributes |= ATE_PREF;		/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= ATE_BAR;		/* barrier bit on */
-	attributes &= ~ATE_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= ATE_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~ATE_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= ATE_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~ATE_PREC;
-
-    return (attributes);
-}
-
-/*ARGSUSED */
-pcibr_dmamap_t
-pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            slot;
-    xwidgetnum_t            xio_port;
-
-    xtalk_dmamap_t          xtalk_dmamap;
-    pcibr_dmamap_t          pcibr_dmamap;
-    int                     ate_count;
-    int                     ate_index;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-#ifdef IRIX
-    NEWf(pcibr_dmamap, flags);
-#else
-    /*
-     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
-     * can be called within an interrupt thread.
-     */
-    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
-#endif
-
-    if (!pcibr_dmamap)
-	return 0;
-
-    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
-				      flags & DMAMAP_FLAGS);
-    if (!xtalk_dmamap) {
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
-#endif
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    xio_port = pcibr_soft->bs_mxid;
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_dmamap->bd_dev = pconn_vhdl;
-    pcibr_dmamap->bd_slot = slot;
-    pcibr_dmamap->bd_soft = pcibr_soft;
-    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
-    pcibr_dmamap->bd_max_size = req_size_max;
-    pcibr_dmamap->bd_xio_port = xio_port;
-
-    if (flags & PCIIO_DMA_A64) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    iopaddr_t               pci_addr;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-	    /* Device is capable of A64 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     */
-
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_pci_addr = pci_addr;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct64\n");
-#endif
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct64\n");
-#endif
-	flags &= ~PCIIO_DMA_A64;
-    }
-    if (flags & PCIIO_FIXED) {
-	/* warning: mappings may fail later,
-	 * if direct32 can't get to the address.
-	 */
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
-	    /* User desires DIRECT A32 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     * Mapping calls may fail if target
-	     * is outside the direct32 range.
-	     */
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct32\n");
-#endif
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
-	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct32\n");
-#endif
-	/* If the user demands FIXED and we can't
-	 * give it to him, fail.
-	 */
-	xtalk_dmamap_free(xtalk_dmamap);
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    /*
-     * Allocate Address Translation Entries from the mapping RAM.
-     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
-     * the maximum number of ATEs is based on the worst-case
-     * scenario, where the requested target is in the
-     * last byte of an ATE; thus, mapping IOPGSIZE+2
-     * does end up requiring three ATEs.
-     */
-    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
-	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
-		     +req_size_max	/* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    } else {	/* assume requested target is page aligned */
-	ate_count = IOPG(req_size_max   /* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    }
-
-    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
-
-    if (ate_index != -1) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
-	    bridge_ate_t            ate_proto;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using PMU\n");
-#endif
-
-	    ate_proto = pcibr_flags_to_ate(flags);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_pci_addr =
-		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
-	    /*
-	     * for xbridge the byte-swap bit == bit 29 of PCI address
-	     */
-	    if (pcibr_soft->bs_xbridge) {
-		    if (flags & PCIIO_BYTE_STREAM)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    /*
-		     * If swap was set in bss_device in pcibr_endian_set()
-		     * we need to change the address bit.
-		     */
-		    if (pcibr_soft->bs_slot[slot].bss_device & 
-							BRIDGE_DEV_SWAP_PMU)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    if (flags & PCIIO_WORD_VALUES)
-			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
-	    }
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
-	    pcibr_dmamap->bd_ate_index = ate_index;
-	    pcibr_dmamap->bd_ate_count = ate_count;
-	    pcibr_dmamap->bd_ate_proto = ate_proto;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (ate_proto & ATE_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
-				!pcibr_soft->bs_xbridge) {
-		bridge_t               *bridge = pcibr_soft->bs_base;
-		volatile unsigned      *cmd_regp;
-		unsigned                cmd_reg;
-		unsigned long           s;
-
-		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
-
-		s = pcibr_lock(pcibr_soft);
-		cmd_regp = &(bridge->
-			     b_type0_cfg_dev[slot].
-			     l[PCI_CFG_COMMAND / 4]);
-		cmd_reg = *cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
-		pcibr_unlock(pcibr_soft, s);
-	    }
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use PMU\n");
-#endif
-	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
-    }
-    /* total failure: sorry, you just can't
-     * get from here to there that way.
-     */
-#if PCIBR_ATE_DEBUG
-    printk("pcibr_dmamap_alloc: complete failure.\n");
-#endif
-    xtalk_dmamap_free(xtalk_dmamap);
-    DEL(pcibr_dmamap);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
-
-    unsigned                flags = pcibr_dmamap->bd_flags;
-
-    /* Make sure that bss_ext_ates_active
-     * is properly kept up to date.
-     */
-
-    if (PCIBR_DMAMAP_BUSY & flags)
-	if (PCIBR_DMAMAP_SSRAM & flags)
-	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
-
-    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
-
-    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
-    }
-    if (pcibr_dmamap->bd_ate_count) {
-	pcibr_ate_free(pcibr_dmamap->bd_soft,
-		       pcibr_dmamap->bd_ate_index,
-		       pcibr_dmamap->bd_ate_count);
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
-    }
-#ifdef IRIX
-    DEL(pcibr_dmamap);
-#endif
-}
-
-/*
- * Setup an Address Translation Entry as specified.  Use either the Bridge
- * internal maps or the external map RAM, as appropriate.
- */
-LOCAL bridge_ate_p
-pcibr_ate_addr(pcibr_soft_t pcibr_soft,
-	       int ate_index)
-{
-    bridge_t *bridge = pcibr_soft->bs_base;
-
-    return (ate_index < pcibr_soft->bs_int_ate_size)
-	? &(bridge->b_int_ate_ram[ate_index].wr)
-	: &(bridge->b_ext_ate_ram[ate_index]);
-}
-
-/*
- *    pcibr_addr_xio_to_pci: given a PIO range, hand
- *      back the corresponding base PCI MEM address;
- *      this is used to short-circuit DMA requests that
- *      loop back onto this PCI bus.
- */
-LOCAL iopaddr_t
-pcibr_addr_xio_to_pci(pcibr_soft_t soft,
-		      iopaddr_t xio_addr,
-		      size_t req_size)
-{
-    iopaddr_t               xio_lim = xio_addr + req_size - 1;
-    iopaddr_t               pci_addr;
-    pciio_slot_t            slot;
-
-    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
-	return pci_addr;
-    }
-    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
-	return pci_addr;
-    }
-    for (slot = 0; slot < 8; ++slot)
-	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
-	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
-	    bridgereg_t             dev;
-
-	    dev = soft->bs_slot[slot].bss_device;
-	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
-	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
-	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
-	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
-	}
-    return 0;
-}
-
-/* We are starting to get more complexity
- * surrounding writing ATEs, so pull
- * the writing code into this new function.
- */
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
-#else
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
-#endif
-
-LOCAL unsigned
-ate_freeze(pcibr_dmamap_t pcibr_dmamap,
-#if PCIBR_FREEZE_TIME
-	   unsigned *freeze_time_ptr,
-#endif
-	   unsigned *cmd_regs)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-#ifdef LATER
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-#endif
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-    int                     slot;
-
-    unsigned long           s;
-    unsigned                cmd_reg;
-    volatile unsigned      *cmd_lwa;
-    unsigned                cmd_lwd;
-
-    if (!ext_ates)
-	return 0;
-
-    /* Bridge Hardware Bug WAR #484930:
-     * Bridge can't handle updating External ATEs
-     * while DMA is occuring that uses External ATEs,
-     * even if the particular ATEs involved are disjoint.
-     */
-
-    /* need to prevent anyone else from
-     * unfreezing the grant while we
-     * are working; also need to prevent
-     * this thread from being interrupted
-     * to keep PCI grant freeze time
-     * at an absolute minimum.
-     */
-    s = pcibr_lock(pcibr_soft);
-
-#ifdef LATER
-    /* just in case pcibr_dmamap_done was not called */
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-    }
-#endif	/* LATER */
-#if PCIBR_FREEZE_TIME
-    *freeze_time_ptr = get_timestamp();
-#endif
-
-    cmd_lwa = 0;
-    for (slot = 0; slot < 8; ++slot)
-	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-	    cmd_reg = pcibr_soft->
-		bs_slot[slot].
-		bss_cmd_shadow;
-	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
-		cmd_lwa = pcibr_soft->
-		    bs_slot[slot].
-		    bss_cmd_pointer;
-		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
-		cmd_lwa[0] = cmd_lwd;
-	    }
-	    cmd_regs[slot] = cmd_reg;
-	} else
-	    cmd_regs[slot] = 0;
-
-    if (cmd_lwa) {
-	    bridge_t	*bridge = pcibr_soft->bs_base;
-
-	    /* Read the last master bit that has been cleared. This PIO read
-	     * on the PCI bus is to ensure the completion of any DMAs that
-	     * are due to bus requests issued by PCI devices before the
-	     * clearing of master bits.
-	     */
-	    cmd_lwa[0];
-
-	    /* Flush all the write buffers in the bridge */
-	    for (slot = 0; slot < 8; ++slot)
-		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-			    /* Flush the write buffer associated with this
-			     * PCI device which might be using dma map RAM.
-			     */
-			    bridge->b_wr_req_buf[slot].reg;
-		    }
-    }
-    return s;
-}
-
-#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
-
-LOCAL void
-ate_write(bridge_ate_p ate_ptr,
-	  int ate_count,
-	  bridge_ate_t ate)
-{
-    while (ate_count-- > 0) {
-	*ate_ptr++ = ate;
-	ate += IOPGSIZE;
-    }
-}
-
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
-#else
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
-#endif
-
-LOCAL void
-ate_thaw(pcibr_dmamap_t pcibr_dmamap,
-	 int ate_index,
-#if PCIBR_FREEZE_TIME
-	 bridge_ate_t ate,
-	 int ate_total,
-	 unsigned freeze_time_start,
-#endif
-	 unsigned *cmd_regs,
-	 unsigned s)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-    int                     slot;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-
-    unsigned                cmd_reg;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-    static unsigned         max_freeze_time = 0;
-    static unsigned         max_ate_total;
-#endif
-
-    if (!ext_ates)
-	return;
-
-    /* restore cmd regs */
-    for (slot = 0; slot < 8; ++slot)
-	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
-	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
-
-    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
-    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-
-#if PCIBR_FREEZE_TIME
-    freeze_time = get_timestamp() - freeze_time_start;
-
-    if ((max_freeze_time < freeze_time) ||
-	(max_ate_total < ate_total)) {
-	if (max_freeze_time < freeze_time)
-	    max_freeze_time = freeze_time;
-	if (max_ate_total < ate_total)
-	    max_ate_total = ate_total;
-	pcibr_unlock(pcibr_soft, s);
-	printk("%s: pci freeze time %d usec for %d ATEs\n"
-		"\tfirst ate: %R\n",
-		pcibr_soft->bs_name,
-		freeze_time * 1000 / 1250,
-		ate_total,
-		ate, ate_bits);
-    } else
-#endif
-	pcibr_unlock(pcibr_soft, s);
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
-		  paddr_t paddr,
-		  size_t req_size)
-{
-    pcibr_soft_t            pcibr_soft;
-    iopaddr_t               xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    unsigned                flags;
-
-    ASSERT(pcibr_dmamap != NULL);
-    ASSERT(req_size > 0);
-    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    flags = pcibr_dmamap->bd_flags;
-
-    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
-    if (XIO_PACKED(xio_addr)) {
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-    } else
-	xio_port = pcibr_dmamap->bd_xio_port;
-
-    /* If this DMA is to an address that
-     * refers back to this Bridge chip,
-     * reduce it back to the correct
-     * PCI MEM address.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-    } else if (flags & PCIIO_DMA_A64) {
-	/* A64 DMA:
-	 * always use 64-bit direct mapping,
-	 * which always works.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	/* attributes are already bundled up into bd_pci_addr.
-	 */
-	pci_addr = pcibr_dmamap->bd_pci_addr
-	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
-	    | xio_addr;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    pci_addr &= ~PCI64_ATTR_PREF;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct64):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else if (flags & PCIIO_FIXED) {
-	/* A32 direct DMA:
-	 * always use 32-bit direct mapping,
-	 * which may fail.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	if (xio_port != pcibr_soft->bs_dir_xport)
-	    pci_addr = 0;		/* wrong DIDN */
-	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
-	    pci_addr = 0;		/* out of range */
-	else if ((xio_addr + req_size) >
-		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
-	    pci_addr = 0;		/* out of range */
-	else
-	    pci_addr = pcibr_dmamap->bd_pci_addr +
-		xio_addr - pcibr_dmamap->bd_xio_addr;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct32):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-	iopaddr_t               offset = IOPGOFF(xio_addr);
-	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
-	int                     ate_count = IOPG(offset + req_size - 1) + 1;
-
-	int                     ate_index = pcibr_dmamap->bd_ate_index;
-	unsigned                cmd_regs[8];
-	unsigned                s;
-
-#if PCIBR_FREEZE_TIME
-	int                     ate_total = ate_count;
-	unsigned                freeze_time;
-#endif
-
-#if PCIBR_ATE_DEBUG
-	bridge_ate_t            ate_cmp;
-	bridge_ate_p            ate_cptr;
-	unsigned                ate_lo, ate_hi;
-	int                     ate_bad = 0;
-	int                     ate_rbc = 0;
-#endif
-	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	bridge_ate_t            ate;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    ate_proto &= ~ATE_PREF;
-
-	ate = ate_proto
-	    | (xio_port << ATE_TIDSHIFT)
-	    | (xio_addr - offset);
-
-	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
-
-	/* Fill in our mapping registers
-	 * with the appropriate xtalk data,
-	 * and hand back the PCI address.
-	 */
-
-	ASSERT(ate_count > 0);
-	if (ate_count <= pcibr_dmamap->bd_ate_count) {
-		ATE_FREEZE();
-		ATE_WRITE();
-		ATE_THAW();
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	} else {
-		/* The number of ATE's required is greater than the number
-		 * allocated for this map. One way this can happen is if
-		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
-		 * flag, and then when that map is used (right now), the
-		 * target address tells us we really did need to roundup.
-		 * The other possibility is that the map is just plain too
-		 * small to handle the requested target area.
-		 */
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_addr :\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\tate_count 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			paddr, paddr + req_size - 1,
-			ate_count, pcibr_dmamap->bd_ate_count);
-#endif
-		pci_addr = 0;
-	}
-
-    }
-    return pci_addr;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
-		  alenlist_t palenlist,
-		  unsigned flags)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge=NULL;
-
-    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-    int                     inplace = flags & PCIIO_INPLACE;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist;
-    size_t                  length;
-    iopaddr_t               offset;
-    unsigned                direct64;
-    int                     ate_index = 0;
-    int                     ate_count = 0;
-    int                     ate_total = 0;
-    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
-    bridge_ate_t            ate_proto = (bridge_ate_t)0;
-    bridge_ate_t            ate_prev;
-    bridge_ate_t            ate;
-    alenaddr_t              xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    alenaddr_t              new_addr;
-
-    unsigned                cmd_regs[8];
-    unsigned                s = 0;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-#endif
-    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
-							 * with an ATE_FREEZE
-							 */
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
-				       flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
-    if (!direct64) {
-	bridge = pcibr_soft->bs_base;
-	ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	ate_index = pcibr_dmamap->bd_ate_index;
-	ate_proto = pcibr_dmamap->bd_ate_proto;
-	ATE_FREEZE();
-	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
-    }
-    pci_addr = pcibr_dmamap->bd_pci_addr;
-
-    ate_prev = 0;			/* matches no valid ATEs */
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &length, al_flags)) {
-	if (XIO_PACKED(xio_addr)) {
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_dmamap->bd_xio_port;
-
-	if (xio_port == pcibr_soft->bs_xid) {
-	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
-	    if (new_addr == PCI_NOWHERE)
-		goto fail;
-	} else if (direct64) {
-	    new_addr = pci_addr | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Bridge Hardware WAR #482836:
-	     * If the transfer is not cache aligned
-	     * and the Bridge Rev is <= B, force
-	     * prefetch to be off.
-	     */
-	    if (flags & PCIBR_NOPREFETCH)
-		new_addr &= ~PCI64_ATTR_PREF;
-
-	} else {
-	    /* calculate the ate value for
-	     * the first address. If it
-	     * matches the previous
-	     * ATE written (ie. we had
-	     * multiple blocks in the
-	     * same IOPG), then back up
-	     * and reuse that ATE.
-	     *
-	     * We are NOT going to
-	     * aggressively try to
-	     * reuse any other ATEs.
-	     */
-	    offset = IOPGOFF(xio_addr);
-	    ate = ate_proto
-		| (xio_port << ATE_TIDSHIFT)
-		| (xio_addr - offset);
-	    if (ate == ate_prev) {
-#if PCIBR_ATE_DEBUG
-		printk("pcibr_dmamap_list: ATE share\n");
-#endif
-		ate_ptr--;
-		ate_index--;
-		pci_addr -= IOPGSIZE;
-	    }
-	    new_addr = pci_addr + offset;
-
-	    /* Fill in the hardware ATEs
-	     * that contain this block.
-	     */
-	    ate_count = IOPG(offset + length - 1) + 1;
-	    ate_total += ate_count;
-
-	    /* Ensure that this map contains enough ATE's */
-	    if (ate_total > pcibr_dmamap->bd_ate_count) {
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_list :\n"
-			"\twanted xio_addr [0x%x..0x%x]\n"
-			"\tate_total 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			xio_addr, xio_addr + length - 1,
-			ate_total, pcibr_dmamap->bd_ate_count);
-#endif
-		goto fail;
-	    }
-
-	    ATE_WRITE();
-
-	    ate_index += ate_count;
-	    ate_ptr += ate_count;
-
-	    ate_count <<= IOPFNSHIFT;
-	    ate += ate_count;
-	    pci_addr += ate_count;
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &new_addr, &length, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				new_addr, length, al_flags))
-		goto fail;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-
-
-    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
-     * changes that ATE_FREEZE has done to implement the external SSRAM
-     * bug workaround.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    return pciio_alenlist;
-
-  fail:
-    /* There are various points of failure after doing an ATE_FREEZE
-     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
-     * The decision to do an ATE_THAW needs to be based on whether a
-     * an ATE_FREEZE was done before.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;
-    }
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
-{
-    /*
-     * We could go through and invalidate ATEs here;
-     * for performance reasons, we don't.
-     * We also don't enforce the strict alternation
-     * between _addr/_list and _done, but Hub does.
-     */
-
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
-    }
-
-    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-}
-
-
-/*
- * For each bridge, the DIR_OFF value in the Direct Mapping Register
- * determines the PCI to Crosstalk memory mapping to be used for all
- * 32-bit Direct Mapping memory accesses. This mapping can be to any
- * node in the system. This function will return that compact node id.
- */
-
-/*ARGSUSED */
-cnodeid_t
-pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
-{
-
-	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
-	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    paddr_t paddr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-
-    xwidgetnum_t            xio_port;
-    iopaddr_t               xio_addr;
-    iopaddr_t               pci_addr;
-
-    int                     have_rrbs;
-    int                     min_rrbs;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
-				   flags & DMAMAP_FLAGS);
-
-    if (!xio_addr) {
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-	return 0;
-    }
-    /*
-     * find which XIO port this goes to.
-     */
-    if (XIO_PACKED(xio_addr)) {
-	if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	    return 0;
-	}
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-
-    } else
-	xio_port = pcibr_soft->bs_mxid;
-
-    /*
-     * If this DMA comes back to us,
-     * return the PCI MEM address on
-     * which it would land, or NULL
-     * if the target is something
-     * on bridge other than PCI MEM.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-	return pci_addr;
-    }
-    /* If the caller can use A64, try to
-     * satisfy the request with the 64-bit
-     * direct map. This can fail if the
-     * configuration bits in Device(x)
-     * conflict with our flags.
-     */
-
-    if (flags & PCIIO_DMA_A64) {
-	pci_addr = slotp->bss_d64_base;
-	if (!(flags & PCIBR_VCHAN1))
-	    flags |= PCIBR_VCHAN0;
-	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-#if DEBUG && PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr);
-#endif
-	    return (pci_addr);
-	}
-	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_addr;
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n"
-			"\tnew flags: 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr, (uint64_t) flags);
-#endif
-	    return (pci_addr);
-	}
-	/* our flags conflict with Device(x).
-	 */
-	flags = flags
-	    & ~PCIIO_DMA_A64
-	    & ~PCIBR_VCHAN0
-	    ;
-
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n"
-		"\tUnable to set Device(x) bits for Direct-64\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-    }
-    /* Try to satisfy the request with the 32-bit direct
-     * map. This can fail if the configuration bits in
-     * Device(x) conflict with our flags, or if the
-     * target address is outside where DIR_OFF points.
-     */
-    {
-	size_t                  map_size = 1ULL << 31;
-	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
-	iopaddr_t               offset = xio_addr - xio_base;
-	iopaddr_t               endoff = req_size + offset;
-
-	if ((req_size > map_size) ||
-	    (xio_addr < xio_base) ||
-	    (xio_port != pcibr_soft->bs_dir_xport) ||
-	    (endoff > map_size)) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\txio region outside direct32 target\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	} else {
-	    pci_addr = slotp->bss_d32_base;
-	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
-		(flags == slotp->bss_d32_flags)) {
-
-		pci_addr |= offset;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tmapped via direct32 offset 0x%x\n"
-			"\twill DMA via pci addr 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, offset, pci_addr);
-#endif
-		return (pci_addr);
-	    }
-	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
-
-		pci_addr = PCI32_DIRECT_BASE;
-		slotp->bss_d32_flags = flags;
-		slotp->bss_d32_base = pci_addr;
-		pci_addr |= offset;
-
-		/* Make sure we have an RRB (or two).
-		 */
-		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		    if (have_rrbs < 2) {
-			if (slotp->bss_device & BRIDGE_DEV_PREF)
-			    min_rrbs = 2;
-			else
-			    min_rrbs = 1;
-			if (have_rrbs < min_rrbs)
-			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		    }
-		}
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-		if (xio_addr != 0x20000000)
-#endif
-		    printk("pcibr_dmatrans_addr:\n"
-			    "\tpciio connection point %v\n"
-			    "\txtalk connection point %v\n"
-			    "\twanted paddr [0x%x..0x%x]\n"
-			    "\txtalk_dmatrans_addr returned 0x%x\n"
-			    "\tmapped via direct32 offset 0x%x\n"
-			    "\twill DMA via pci addr 0x%x\n"
-			    "\tnew flags: 0x%x\n",
-			    pconn_vhdl, xconn_vhdl,
-			    paddr, paddr + req_size - 1,
-			    xio_addr, offset, pci_addr, (uint64_t) flags);
-#endif
-		return (pci_addr);
-	    }
-	    /* our flags conflict with Device(x).
-	     */
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\tUnable to set Device(x) bits for Direct-32\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	}
-    }
-
-#if PCIBR_DMA_DEBUG
-    printk("pcibr_dmatrans_addr:\n"
-	    "\tpciio connection point %v\n"
-	    "\txtalk connection point %v\n"
-	    "\twanted paddr [0x%x..0x%x]\n"
-	    "\txtalk_dmatrans_addr returned 0x%x\n"
-	    "\tno acceptable PCI address found or constructable\n",
-	    pconn_vhdl, xconn_vhdl,
-	    paddr, paddr + req_size - 1,
-	    xio_addr);
-#endif
-
-    return 0;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    alenlist_t palenlist,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-    xwidgetnum_t            xio_port;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist = 0;
-
-    int                     inplace;
-    unsigned                direct64;
-    unsigned                al_flags;
-
-    iopaddr_t               xio_base;
-    alenaddr_t              xio_addr;
-    size_t                  xio_size;
-
-    size_t                  map_size;
-    iopaddr_t               pci_base;
-    alenaddr_t              pci_addr;
-
-    unsigned                relbits = 0;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    inplace = flags & PCIIO_INPLACE;
-    direct64 = flags & PCIIO_DMA_A64;
-    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-
-    if (direct64) {
-	map_size = 1ull << 48;
-	xio_base = 0;
-	pci_base = slotp->bss_d64_base;
-	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D64_BITS;
-	    pci_base =
-		pcibr_flags_to_d64(flags, pcibr_soft);
-	}
-    } else {
-	xio_base = pcibr_soft->bs_dir_xbase;
-	map_size = 1ull << 31;
-	pci_base = slotp->bss_d32_base;
-	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
-	    (flags == slotp->bss_d32_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D32_BITS;
-	    pci_base = PCI32_DIRECT_BASE;
-	}
-    }
-
-    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
-					 flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &xio_size, al_flags)) {
-
-	/*
-	 * find which XIO port this goes to.
-	 */
-	if (XIO_PACKED(xio_addr)) {
-	    if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr);
-#endif
-		return 0;
-	    }
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_soft->bs_mxid;
-
-	/*
-	 * If this DMA comes back to us,
-	 * return the PCI MEM address on
-	 * which it would land, or NULL
-	 * if the target is something
-	 * on bridge other than PCI MEM.
-	 */
-	if (xio_port == pcibr_soft->bs_xid) {
-	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
-	    if ( (pci_addr == (alenaddr_t)NULL) )
-		goto fail;
-	} else if (direct64) {
-	    ASSERT(xio_port != 0);
-	    pci_addr = pci_base | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-	} else {
-	    iopaddr_t               offset = xio_addr - xio_base;
-	    iopaddr_t               endoff = xio_size + offset;
-
-	    if ((xio_size > map_size) ||
-		(xio_addr < xio_base) ||
-		(xio_port != pcibr_soft->bs_dir_xport) ||
-		(endoff > map_size))
-		goto fail;
-
-	    pci_addr = pci_base + (xio_addr - xio_base);
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &pci_addr, &xio_size, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				pci_addr, xio_size, al_flags))
-		goto fail;
-	}
-    }
-
-    if (relbits) {
-	if (direct64) {
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_base;
-	} else {
-	    slotp->bss_d32_flags = flags;
-	    slotp->bss_d32_base = pci_base;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-    return pciio_alenlist;
-
-  fail:
-    if (relbits)
-	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-void
-pcibr_dmamap_drain(pcibr_dmamap_t map)
-{
-    xtalk_dmamap_drain(map->bd_xtalk);
-}
-
-void
-pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
-		    paddr_t paddr,
-		    size_t bytes)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
-}
-
-void
-pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
-		    alenlist_t list)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmalist_drain(xconn_vhdl, list);
-}
-
-/*
- * Get the starting PCIbus address out of the given DMA map.
- * This function is supposed to be used by a close friend of PCI bridge
- * since it relies on the fact that the starting address of the map is fixed at
- * the allocation time in the current implementation of PCI bridge.
- */
-iopaddr_t
-pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
-{
-    return (pcibr_dmamap->bd_pci_addr);
-}
-
-/* =====================================================================
- *    INTERRUPT MANAGEMENT
- */
-
-static unsigned
-pcibr_intr_bits(pciio_info_t info,
-		pciio_intr_line_t lines)
-{
-    pciio_slot_t            slot = pciio_info_slot_get(info);
-    unsigned		    bbits = 0;
-
-    /*
-     * Currently favored mapping from PCI
-     * slot number and INTA/B/C/D to Bridge
-     * PCI Interrupt Bit Number:
-     *
-     *     SLOT     A B C D
-     *      0       0 4 0 4
-     *      1       1 5 1 5
-     *      2       2 6 2 6
-     *      3       3 7 3 7
-     *      4       4 0 4 0
-     *      5       5 1 5 1
-     *      6       6 2 6 2
-     *      7       7 3 7 3
-     */
-
-    if (slot < 8) {
-	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
-	    bbits |= 1 << slot;
-	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
-	    bbits |= 1 << (slot ^ 4);
-    }
-    return bbits;
-}
-
-
-/*
- *	Get the next wrapper pointer queued in the interrupt circular buffer.
- */
-#ifdef KERNEL_THREADS
-pcibr_intr_wrap_t
-pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	if (cbuf->ib_in == cbuf->ib_out)
-	    PRINT_PANIC("pcibr intr circular buffer empty, cbuf=0x%x, ib_in=ib_out=%d\n",
-		cbuf, cbuf->ib_out);
-
-	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
-	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
-	return(wrap);
-}
-
-/* 
- *	Queue a wrapper pointer in the interrupt circular buffer.
- */
-void
-pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
-{
-	int	in;
-	unsigned long	s;
-
-	/*
-	 * Multiple CPUs could be executing this code simultaneously
-	 * if a handler has registered multiple interrupt lines and
-	 * the interrupts are directed to different CPUs.
-	 */
-	s = mutex_spinlock(&cbuf->ib_lock);
-	in = (cbuf->ib_in + 1) % IBUFSIZE;
-	if (in == cbuf->ib_out) 
-	    PRINT_PANIC("pcibr intr circular buffer full, cbuf=0x%x, ib_in=%d\n",
-		cbuf, cbuf->ib_in);
-
-	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
-	cbuf->ib_in = in;
-	mutex_spinunlock(&cbuf->ib_lock, s);
-	return;
-}
-#endif	/* KERNEL_THREADS */
-
-/*
- *	There are end cases where a deadlock can occur if interrupt 
- *	processing completes and the Bridge b_int_status bit is still set.
- *
- *	One scenerio is if a second PCI interrupt occurs within 60ns of
- *	the previous interrupt being cleared. In this case the Bridge
- *	does not detect the transition, the Bridge b_int_status bit
- *	remains set, and because no transition was detected no interrupt
- *	packet is sent to the Hub/Heart.
- *
- *	A second scenerio is possible when a b_int_status bit is being
- *	shared by multiple devices:
- *						Device #1 generates interrupt
- *						Bridge b_int_status bit set
- *						Device #2 generates interrupt
- *		interrupt processing begins
- *		  ISR for device #1 runs and
- *			clears interrupt
- *						Device #1 generates interrupt
- *		  ISR for device #2 runs and
- *			clears interrupt
- *						(b_int_status bit still set)
- *		interrupt processing completes
- *		  
- *	Interrupt processing is now complete, but an interrupt is still
- *	outstanding for Device #1. But because there was no transition of
- *	the b_int_status bit, no interrupt packet will be generated and
- *	a deadlock will occur.
- *
- *	To avoid these deadlock situations, this function is used
- *	to check if a specific Bridge b_int_status bit is set, and if so,
- *	cause the setting of the corresponding interrupt bit.
- *
- *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
- *	Interrupt register.
- */
-void
-pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
-{
-	unsigned	bit;
-	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
-	bridge_t       *bridge = pcibr_soft->bs_base;
-	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
-
-	bit = wrap->iw_intr;
-
-	if (pcibr_soft->bs_xbridge) {
-	    bridge->b_force_pin[bit].intr = 1;
-	} else if ((1 << bit) & *wrap->iw_stat) {
-	    cpuid_t	    cpu;
-	    unsigned        intr_bit;
-	    xtalk_intr_t    xtalk_intr =
-				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
-
-	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
-	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
-	}
-}
-
-/* Wrapper for pcibr interrupt threads. */
-#ifdef KERNEL_THREADS
-static void
-pcibr_intrd(pcibr_intr_t intr)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	/* Called on each restart */
-	ASSERT(cpuid() == intr->bi_mustruncpu);
-
-#ifdef ITHREAD_LATENCY
-	xthread_update_latstats(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-
-	ASSERT(intr->bi_func != NULL);
-	intr->bi_func(intr->bi_arg);		/* Invoke the interrupt handler */
-
-	/*
-	 * The pcibr_intrd thread needs access to the wrapper struct
-	 * specific to the current interrupt it is processing. Because
-	 * multiple calls/wakeups to the thread could be queued, each
-	 * potentially from a different interrupt line (PCIIO_INTR_LINE_A,
-	 * etc), multiple wrapper struct pointers need to be queued. This 
-	 * is done via a circular buffer of wrapper struct pointers. 
-	 */
-	wrap = pcibr_wrap_get(&intr->bi_ibuf);
-
-	/* 
-	 * The interrupt handler has completed. Now decrement the running
-	 * count tracking the number of handlers still running for this line.
-	 * If this was the last handler to complete (i.e., iw_hdlrcnt == 0),
-	 * avoid a potential deadlock condition and ensure that another
-	 * interrupt will occur if the Bridge b_int_status bit is still
-	 * set. 
-	 */
-	atomicAddInt(&(wrap->iw_hdlrcnt), -1);
-	if (wrap->iw_hdlrcnt == 0)
-		pcibr_force_interrupt(wrap);
-
-	ipsema(&intr->bi_tinfo.thd_isync);	/* Sleep 'till next interrupt */
-	/* NOTREACHED */
-}
-
-static void
-pcibr_intrd_start(pcibr_intr_t intr)
-{
-	ASSERT(intr->bi_mustruncpu >= 0);
-	setmustrun(intr->bi_mustruncpu);
-
-	xthread_set_func(KT_TO_XT(curthreadp), (xt_func_t *)pcibr_intrd, (void *)intr);
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_INIT);
-	ipsema(&intr->bi_tinfo.thd_isync);  /* Comes out in pcibr_intrd */
-	/* NOTREACHED */
-}
-
-
-static void
-pcibr_thread_setup(pcibr_intr_t intr, int bridge_levels, ilvl_t intr_swlevel)
-{
-	char thread_name[32];
-
-	sprintf(thread_name, "pcibr_intrd[0x%x]", bridge_levels);
-	thread_name[IT_NAMELEN-1] = '\0';
-
-	/* XXX need to adjust priority whenever an interrupt is connected */
-	intr->bi_tinfo.thd_pri = intr_swlevel;
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_ISTHREAD | THD_REG);
-	xthread_setup(thread_name, intr_swlevel, &intr->bi_tinfo,
-			(xt_func_t *)pcibr_intrd_start,
-			(void *)intr);
-}
-#endif	/* KERNEL_THREADS */
-
-
-
-/*ARGSUSED */
-pcibr_intr_t
-pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
-		 device_desc_t dev_desc,
-		 pciio_intr_line_t lines,
-		 devfs_handle_t owner_dev)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     is_threaded = 0;
-#ifdef KERNEL_THREADS
-    cpuid_t		    mustruncpu = CPU_NONE;
-    cpuid_t		    old_intrcpu = CPU_NONE;
-#endif
-    int                     thread_swlevel;
-
-    xtalk_intr_t           *xtalk_intr_p;
-    pcibr_intr_t           *pcibr_intr_p;
-    pcibr_intr_list_t      *intr_list_p;
-
-    unsigned                pcibr_int_bits;
-    unsigned                pcibr_int_bit;
-    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
-    hub_intr_t		    hub_intr;
-    pcibr_intr_t            pcibr_intr;
-    pcibr_intr_list_t       intr_entry;
-    pcibr_intr_list_t       intr_list;
-    bridgereg_t             int_dev;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_alloc\n"
-	    "%v:%s%s%s%s%s\n",
-	    owner_dev, pconn_vhdl,
-	    !(lines & 15) ? " No INTs?" : "",
-	    lines & 1 ? " INTA" : "",
-	    lines & 2 ? " INTB" : "",
-	    lines & 4 ? " INTC" : "",
-	    lines & 8 ? " INTD" : "");
-#endif
-
-    NEW(pcibr_intr);
-    if (!pcibr_intr)
-	return NULL;
-
-    if (dev_desc) {
-	cpuid_t intr_target_from_desc(device_desc_t, int);
-
-#ifdef KERNEL_THREADS
-	is_threaded = !(device_desc_flags_get(dev_desc) & D_INTR_NOTHREAD);
-	if (is_threaded) {
-	    /*
-	     * If the device descriptor contains interrupt target info,
-	     * save the CPU requested. This is the CPU the pcibr_intrd
-	     * thread will be set to run on. 
-	     *
-	     * We need to get the interrupt target info at this time, because
-	     * the original intr_target value can be overwritten, as part of
-	     * the xtalk_intr_alloc_nothd() call, with the actual interrupt CPU.
-	     * This can be different than the requested CPU if the lower layers
-	     * could not direct the hardware interrupt to the requested CPU. 
-	     * Regardless of which CPU processes the hardware interrupt, the 
-	     * ISR thread will still be setup to run on the CPU originally 
-	     * requested.
-	     */
-		mustruncpu = intr_target_from_desc(dev_desc, SUBNODE_ANY);
-		thread_swlevel = device_desc_intr_swlevel_get(dev_desc);
-	}
-#endif	/* KERNEL_THREADS */
-    } else {
-	extern int default_intr_pri;
-
-	is_threaded = 1; /* PCI interrupts are threaded, by default */
-	thread_swlevel = default_intr_pri;
-    }
-
-    pcibr_intr->bi_dev = pconn_vhdl;
-    pcibr_intr->bi_lines = lines;
-    pcibr_intr->bi_soft = pcibr_soft;
-    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
-    pcibr_intr->bi_func = 0;		/* unset until connect */
-    pcibr_intr->bi_arg = 0;		/* unset until connect */
-    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
-    pcibr_intr->bi_mustruncpu = CPU_NONE;
-#ifdef KERNEL_THREADS
-    pcibr_intr->bi_ibuf.ib_in = 0;
-    pcibr_intr->bi_ibuf.ib_out = 0;
-#endif
-    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
-
-    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
-
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-#if DEBUG && INTR_DEBUG
-    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
-#endif 
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    xtalk_intr = *xtalk_intr_p;
-
-	    if (xtalk_intr == NULL) {
-		/*
-		 * This xtalk_intr_alloc is constrained for two reasons:
-		 * 1) Normal interrupts and error interrupts need to be delivered
-		 *    through a single xtalk target widget so that there aren't any
-		 *    ordering problems with DMA, completion interrupts, and error
-		 *    interrupts. (Use of xconn_vhdl forces this.)
-		 *
-		 * 2) On IP35, addressing constraints on IP35 and Bridge force
-		 *    us to use a single PI number for all interrupts from a
-		 *    single Bridge. (IP35-specific code forces this, and we
-		 *    verify in pcibr_setwidint.)
-		 */
-
-		/*
-		 * All code dealing with threaded PCI interrupt handlers
-		 * is located at the pcibr level. Because of this,
-		 * we always want the lower layers (hub/heart_intr_alloc, 
-		 * intr_level_connect) to treat us as non-threaded so we
-		 * don't set up a duplicate threaded environment. We make
-		 * this happen by calling a special xtalk interface.
-		 */
-		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
-			owner_dev);
-#if DEBUG && INTR_DEBUG
-		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
-#endif
-
-		/* both an assert and a runtime check on this:
-		 * we need to check in non-DEBUG kernels, and
-		 * the ASSERT gets us more information when
-		 * we use DEBUG kernels.
-		 */
-		ASSERT(xtalk_intr != NULL);
-		if (xtalk_intr == NULL) {
-		    /* it is quite possible that our
-		     * xtalk_intr_alloc failed because
-		     * someone else got there first,
-		     * and we can find their results
-		     * in xtalk_intr_p.
-		     */
-		    if (!*xtalk_intr_p) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
-				xconn_vhdl);
-#endif
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
-		    /*
-		     * now tell the bridge which slot is
-		     * using this interrupt line.
-		     */
-		    int_dev = bridge->b_int_device;
-		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
-		    bridge->b_int_device = int_dev;	/* XXXMP */
-
-#if DEBUG && INTR_DEBUG
-		    printk("%v: bridge intr bit %d clears my wrb\n",
-			    pconn_vhdl, pcibr_int_bit);
-#endif
-		} else {
-		    /* someone else got one allocated first;
-		     * free the one we just created, and
-		     * retrieve the one they allocated.
-		     */
-		    xtalk_intr_free(xtalk_intr);
-		    xtalk_intr = *xtalk_intr_p;
-#if PARANOID
-		    /* once xtalk_intr is set, we never clear it,
-		     * so if the CAS fails above, this condition
-		     * can "never happen" ...
-		     */
-		    if (!xtalk_intr) {
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
-				xconn_vhdl);
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-#endif
-		}
-	    }
-
-#ifdef KERNEL_THREADS
-	    if (is_threaded) {
-		cpuid_t intrcpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-
-		/*
-		 * It is possible that 2 (or more) interrupts originating on a
-		 * single Bridge and used by a single device were assigned to
-		 * different CPUs. If this occurs issue a warning message for
-		 * this sub-optimal configuration. There are two ways this 
-		 * could happen:
-		 *
-		 *  - There were insufficient xtalk interrupt resources to
-		 *    allow all interrupts to be assigned to the same CPU.
-		 *    This is an unlikely case, but could happen if someone
-		 *    tries to target a lot of interrupts to a single CPU.
-		 *
-		 * - If there is no device descriptor associated with this
-		 *   device, the xtalk/hub/heart layers will not know to
-		 *   assign the same CPU to any additional interrupts this
-		 *   driver has specified, and will perform the normal load
-		 *   leveling of interrupts across CPUs.
-		 *   (The lower layers store the CPU assigned to the first
-		 *   interrupt in the device desc, if present, and then when
-		 *   called again for additional interrupts for the same device,
-		 *   use this information to assign the same CPU to these
-		 *   interrupts.)
-		 */
-		if ((old_intrcpu != CPU_NONE) && (old_intrcpu != intrcpu)) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Conflict on where to schedule interrupts for %v\n", pconn_vhdl);
-#else
-			PRINT_WARNING("Conflict on where to schedule interrupts for 0x%x\n", pconn_vhdl);
-#endif
-			PRINT_WARNING("(on cpu %d or on cpu %d), cpu %d used\n", old_intrcpu, intrcpu, intrcpu);
-		}
-		if (old_intrcpu == CPU_NONE)
-			old_intrcpu = intrcpu;
-	    /*
-	     * For threaded drivers, set the interrupt thread to run wherever
-	     * the interrupt is targeted, or where requested in the dev_desc.
-	     */
-		if (mustruncpu != CPU_NONE) {
-			pcibr_intr->bi_mustruncpu = mustruncpu;
-			if (mustruncpu != intrcpu) {
-				PRINT_WARNING("Request to target PCI interrupts to CPU %d could not\n"
-                		"      be satisfied, CPU %d used. However, interrupt thread\n"
-                		"      pcibr_intrd will run on CPU %d as requested.\n"
-                		"      %v (0x%x)\n",
-                		mustruncpu, intrcpu, mustruncpu, owner_dev,
-				owner_dev);
-			}
-		} else {
-			pcibr_intr->bi_mustruncpu = intrcpu;
-		}
-		ASSERT(pcibr_intr->bi_mustruncpu >= 0);
-
-	    }
-#endif	/* KERNEL_THREADS */
-
-	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
-
-	    NEW(intr_entry);
-	    intr_entry->il_next = NULL;
-	    intr_entry->il_intr = pcibr_intr;
-	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
-	    intr_list_p = 
-		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-#if DEBUG && INTR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#else
-	    printk("%v: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#endif
-#endif
-
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the first interrupt on this bridge bit.
-		 */
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list = *intr_list_p;
-	    pcibr_intr_p = &intr_list->il_intr;
-	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		/* first entry on list was erased,
-		 * and we replaced it, so we
-		 * don't need our intr_entry.
-		 */
-		DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list_p = &intr_list->il_next;
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the new second interrupt on this bit.
-		 */
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    while (1) {
-		pcibr_intr_p = &intr_list->il_intr;
-		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		    /* an entry on list was erased,
-		     * and we replaced it, so we
-		     * don't need our intr_entry.
-		     */
-		    DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		intr_list_p = &intr_list->il_next;
-		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		    /* entry appended to share list
-		     */
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		/* step to next record in chain
-		 */
-		intr_list = *intr_list_p;
-	    }
-	}
-    }
-
-#ifdef KERNEL_THREADS
-    if (is_threaded) {
-	/* Set pcibr_intr->bi_tinfo */
-	pcibr_thread_setup(pcibr_intr, pcibr_int_bits, thread_swlevel);
-	ASSERT(!(pcibr_intr->bi_flags & PCIIO_INTR_CONNECTED));
-    }
-#endif	/* KERNEL_THREADS */
-
-#if DEBUG && INTR_DEBUG
-    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
-#endif
-    hub_intr = (hub_intr_t)xtalk_intr;
-    pcibr_intr->bi_irq = hub_intr->i_bit;
-    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
-    return pcibr_intr;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_free(pcibr_intr_t pcibr_intr)
-{
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_list_t       intr_list;
-    int			    intr_shared;
-    xtalk_intr_t	    *xtalk_intrp;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    for (intr_list = 
-		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-		 intr_list != NULL;
-		 intr_list = intr_list->il_next)
-		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
-					 pcibr_intr, 
-					 NULL)) {
-#if DEBUG && INTR_DEBUG
-		    printk("%s: cleared a handler from bit %d\n",
-			    pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-		}
-	    /* If this interrupt line is not being shared between multiple
-	     * devices release the xtalk interrupt resources.
-	     */
-	    intr_shared = 
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
-	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    if ((!intr_shared) && (*xtalk_intrp)) {
-
-		bridge_t 	*bridge = pcibr_soft->bs_base;
-		bridgereg_t	int_dev;
-
-		xtalk_intr_free(*xtalk_intrp);
-		*xtalk_intrp = 0;
-
-		/* Clear the PCI device interrupt to bridge interrupt pin
-		 * mapping.
-		 */
-		int_dev = bridge->b_int_device;
-		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		bridge->b_int_device = int_dev;
-
-	    }
-	}
-    }
-    DEL(pcibr_intr);
-}
-
-LOCAL void
-pcibr_setpciint(xtalk_intr_t xtalk_intr)
-{
-    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
-    bridgereg_t            *int_addr = (bridgereg_t *)
-    xtalk_intr_sfarg_get(xtalk_intr);
-
-    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-		 (BRIDGE_INT_ADDR_FLD & vect));
-}
-
-/*ARGSUSED */
-int
-pcibr_intr_connect(pcibr_intr_t pcibr_intr,
-		   intr_func_t intr_func,
-		   intr_arg_t intr_arg,
-		   void *thread)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    if (pcibr_intr == NULL)
-	return -1;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_connect 0x%X(0x%X)\n",
-	    pcibr_intr->bi_dev, intr_func, intr_arg);
-#endif
-
-    pcibr_intr->bi_func = intr_func;
-    pcibr_intr->bi_arg = intr_arg;
-    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    pcibr_intr_wrap_t       intr_wrap;
-	    xtalk_intr_t            xtalk_intr;
-
-	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    /*
-	     * If this interrupt line is being shared and the connect has
-	     * already been done, no need to do it again.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
-		continue;
-
-
-	    /*
-	     * Use the pcibr wrapper function to handle all Bridge interrupts
-	     * regardless of whether the interrupt line is shared or not.
-	     */
-	    xtalk_intr_connect(xtalk_intr,
-				pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%v bridge bit %d wrapper connected\n",
-		    pcibr_intr->bi_dev, pcibr_int_bit);
-#endif
-	}
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable |= pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_wrap_t	    intr_wrap;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    /* Stop calling the function. Now.
-     */
-    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
-    pcibr_intr->bi_func = 0;
-    pcibr_intr->bi_arg = 0;
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and disconnect the interrupt.
-     */
-
-    /* don't disable interrupts for lines that
-     * are shared between devices.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
-	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
-	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
-    if (!pcibr_int_bits)
-	return;
-
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable &= ~pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    /* if the interrupt line is now shared,
-	     * do not disconnect it.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
-		pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-
-	    /* if we are sharing the interrupt line,
-	     * connect us up; this closes the hole
-	     * where the another pcibr_intr_alloc()
-	     * was in progress as we disconnected.
-	     */
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-
-	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
-			       pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	}
-}
-
-/*ARGSUSED */
-devfs_handle_t
-pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit))
-	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-    return 0;
-}
-
-/* =====================================================================
- *    INTERRUPT HANDLING
- */
-LOCAL void
-pcibr_clearwidint(bridge_t *bridge)
-{
-    bridge->b_wid_int_upper = 0;
-    bridge->b_wid_int_lower = 0;
-}
-
-
-LOCAL void
-pcibr_setwidint(xtalk_intr_t intr)
-{
-    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
-    iopaddr_t               addr = xtalk_intr_addr_get(intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
-    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
-    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
-
-    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
-
-    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-			       XTALK_ADDR_TO_UPPER(addr));
-    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-
-    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
-    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    /* Verify that all interrupts from this Bridge are using a single PI */
-    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
-	/*
-	 * Once set, these registers shouldn't change; they should
-	 * be set multiple times with the same values.
-	 *
-	 * If we're attempting to change these registers, it means
-	 * that our heuristics for allocating interrupts in a way
-	 * appropriate for IP35 have failed, and the admin needs to
-	 * explicitly direct some interrupts (or we need to make the
-	 * heuristics more clever).
-	 *
-	 * In practice, we hope this doesn't happen very often, if
-	 * at all.
-	 */
-	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
-	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
-		PRINT_WARNING("Interrupt allocation is too complex.\n");
-		PRINT_WARNING("Use explicit administrative interrupt targetting.\n");
-		PRINT_WARNING("bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
-		PRINT_WARNING("NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
-			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
-			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
-		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
-	}
-    }
-#endif /* CONFIG_SGI_IP35 */
-
-    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
-    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
-    bridge->b_int_host_err = vect;
-}
-
-/*
- * pcibr_intr_preset: called during mlreset time
- * if the platform specific code needs to route
- * one of the Bridge's xtalk interrupts before the
- * xtalk infrastructure is available.
- */
-void
-pcibr_xintr_preset(void *which_widget,
-		   int which_widget_intr,
-		   xwidgetnum_t targ,
-		   iopaddr_t addr,
-		   xtalk_intr_vector_t vect)
-{
-    bridge_t               *bridge = (bridge_t *) which_widget;
-
-    if (which_widget_intr == -1) {
-	/* bridge widget error interrupt */
-	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-				   XTALK_ADDR_TO_UPPER(addr));
-	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-	bridge->b_int_host_err = vect;
-
-	/* turn on all interrupts except
-	 * the PCI interrupt requests,
-	 * at least at heart.
-	 */
-	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
-
-    } else {
-	/* routing a PCI device interrupt.
-	 * targ and low 38 bits of addr must
-	 * be the same as the already set
-	 * value for the widget error interrupt.
-	 */
-	bridge->b_int_addr[which_widget_intr].addr =
-	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-	     (BRIDGE_INT_ADDR_FLD & vect));
-	/*
-	 * now bridge can let it through;
-	 * NB: still should be blocked at
-	 * xtalk provider end, until the service
-	 * function is set.
-	 */
-	bridge->b_int_enable |= 1 << vect;
-    }
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-}
-
-
-/*
- * pcibr_intr_func()
- *
- * This is the pcibr interrupt "wrapper" function that is called,
- * in interrupt context, to initiate the interrupt handler(s) registered
- * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
- * handlers will be called directly, and threaded handlers will have their 
- * thread woken up.
- */
-void
-pcibr_intr_func(intr_arg_t arg)
-{
-    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
-    reg_p                   wrbf;
-    intr_func_t             func;
-    pcibr_intr_t            intr;
-    pcibr_intr_list_t       list;
-    int                     clearit;
-#ifdef KERNEL_THREADS
-    int			    do_nonthreaded = 0;
-    int			    do_threaded = 1;
-    int			    is_threaded = 0;
-#else
-    int			    do_nonthreaded = 1;
-    int			    do_threaded = 0;
-    int			    is_threaded = 0;
-#endif
-    int			    nonthreaded_count = 0;
-    int			    x = 0;
-
-	/*
-	 * If any handler is still running from a previous interrupt
-	 * just return. If there's a need to call the handler(s) again,
-	 * another interrupt will be generated either by the device or by
-	 * pcibr_force_interrupt().
-	 */
-
-	if (wrap->iw_hdlrcnt) {
-		return;
-	}
-
-    /*
-     * Call all interrupt handlers registered.
-     * First, the pcibr_intrd threads for any threaded handlers will be
-     * awoken, then any non-threaded handlers will be called sequentially.
-     */
-	
-	clearit = 1;
-	while (do_threaded || do_nonthreaded) {
-	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
-		if ((intr = list->il_intr) &&
-		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
-
-		    ASSERT(intr->bi_func);
-
-		/*
-		 * This device may have initiated write
-		 * requests since the bridge last saw
-		 * an edge on this interrupt input; flushing
-		 * the buffer prior to invoking the handler
-		 * should help but may not be sufficient if we 
-		 * get more requests after the flush, followed
-		 * by the card deciding it wants service, before
-		 * the interrupt handler checks to see if things need
-		 * to be done.
-		 *
-		 * There is a similar race condition if
-		 * an interrupt handler loops around and
-		 * notices further service is requred.
-		 * Perhaps we need to have an explicit
-		 * call that interrupt handlers need to
-		 * do between noticing that DMA to memory
-		 * has completed, but before observing the
-		 * contents of memory?
-		 */
-
-#ifdef KERNEL_THREADS
-		    is_threaded = !(intr->bi_flags & PCIIO_INTR_NOTHREAD);
-		    if (!is_threaded) {
-			nonthreaded_count++;
-		    }
-
-		    if ((do_threaded) && (is_threaded)) {
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if (x = *wrbf)	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func 0x%x: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			/*
-			 * Keep a running count of the number of interrupt
-			 * handlers that have yet to complete. 
-			 */
-			atomicAddInt(&(wrap->iw_hdlrcnt), 1);
-
-			/* 
-			 * Prior to waking up pcibr_intrd, a pointer to the 
-			 * wrapper struct corresponding to the interrupt taken
-			 * needs to be queued in the interrupt circular buffer.
-			 * The pcibr_intrd thread needs the wrapper pointer in
-			 * order to decrement the handler count (iw_hdlrcnt).
-			 */
-			pcibr_wrap_put(wrap, &intr->bi_ibuf);
-#ifdef ITHREAD_LATENCY
-			xthread_set_istamp(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-		     	up(&intr->bi_tinfo.thd_isync); 
-		    } else
-#endif	/* KERNEL_THREADS */
-			if ((do_nonthreaded) && (!is_threaded)) {
-			/* Non-threaded. 
-			 * Call the interrupt handler at interrupt level
-			 */
-
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if ((x = *wrbf))	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func %p: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			func = intr->bi_func;
-			func(intr->bi_arg);
-		    }
-
-		    clearit = 0;
-		}
-	    }
-
-	    if (do_threaded) {
-		/* 
-		 * All threaded handlers have been called;
-		 * next do non-threaded, if any.
-		 */
-		do_threaded = 0;
-
-		if (nonthreaded_count)
-			do_nonthreaded = 1;
-	    } else {
-		do_nonthreaded = 0;
-		/*
-		 * If the non-threaded handler was the last to complete,
-		 * (i.e., no threaded handlers still running) force an
-		 * interrupt to avoid a potential deadlock situation.
-		 */
-		if (wrap->iw_hdlrcnt == 0) {
-			pcibr_force_interrupt(wrap);
-		}
-	    }
-	}
-
-	/* If there were no handlers,
-	 * disable the interrupt and return.
-	 * It will get enabled again after
-	 * a handler is connected.
-	 * If we don't do this, we would
-	 * sit here and spin through the
-	 * list forever.
-	 */
-	if (clearit) {
-	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-	    bridgereg_t             b_int_enable;
-	    bridgereg_t		    mask = 1 << wrap->iw_intr;
-	    unsigned long           s;
-
-	    s = pcibr_lock(pcibr_soft);
-	    b_int_enable = bridge->b_int_enable;
-	    b_int_enable &= ~mask;
-	    bridge->b_int_enable = b_int_enable;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	    pcibr_unlock(pcibr_soft, s);
-	    return;
-	}
-}
-
-/* =====================================================================
- *    ERROR HANDLING
- */
-
-#ifdef	DEBUG
-#ifdef	ERROR_DEBUG
-#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
-#else
-#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
-#endif
-#else
-#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
-#endif
-
-LOCAL void
-print_bridge_errcmd(uint32_t cmdword, char *errtype)
-{
-#ifdef SUPPORT_PRINTING_R_FORMAT
-    PRINT_WARNING(
-	    "	Bridge %s error command word register %R",
-	    errtype, cmdword, xio_cmd_bits);
-#else
-    PRINT_WARNING(
-	    "	Bridge %s error command word register 0x%x",
-	    errtype, cmdword);
-#endif
-}
-
-LOCAL char             *pcibr_isr_errs[] =
-{
-    "", "", "", "", "", "", "", "",
-    "08: GIO non-contiguous byte enable in crosstalk packet",
-    "09: PCI to Crosstalk read request timeout",
-    "10: PCI retry operation count exhausted.",
-    "11: PCI bus device select timeout",
-    "12: PCI device reported parity error",
-    "13: PCI Address/Cmd parity error ",
-    "14: PCI Bridge detected parity error",
-    "15: PCI abort condition",
-    "16: SSRAM parity error",
-    "17: LLP Transmitter Retry count wrapped",
-    "18: LLP Transmitter side required Retry",
-    "19: LLP Receiver retry count wrapped",
-    "20: LLP Receiver check bit error",
-    "21: LLP Receiver sequence number error",
-    "22: Request packet overflow",
-    "23: Request operation not supported by bridge",
-    "24: Request packet has invalid address for bridge widget",
-    "25: Incoming request xtalk command word error bit set or invalid sideband",
-    "26: Incoming response xtalk command word error bit set or invalid sideband",
-    "27: Framing error, request cmd data size does not match actual",
-    "28: Framing error, response cmd data size does not match actual",
-    "29: Unexpected response arrived",
-    "30: Access to SSRAM beyond device limits",
-    "31: Multiple errors occurred",
-};
-
-/*
- * PCI Bridge Error interrupt handling.
- * This routine gets invoked from system interrupt dispatcher
- * and is responsible for invoking appropriate error handler,
- * depending on the type of error.
- * This IS a duplicate of bridge_errintr defined specfic to IP30.
- * There are some minor differences in terms of the return value and
- * parameters passed. One of these two should be removed at some point
- * of time.
- */
-/*ARGSUSED */
-void
-pcibr_error_dump(pcibr_soft_t pcibr_soft)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             int_status;
-    int                     i;
-
-    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-
-    PRINT_ALERT( "%s PCI BRIDGE ERROR: int_status is 0x%X",
-	    pcibr_soft->bs_name, int_status);
-
-    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
-	if (int_status & (1 << i)) {
-	    PRINT_WARNING( "%s", pcibr_isr_errs[i]);
-	}
-    }
-
-    if (int_status & BRIDGE_ISR_XTALK_ERROR) {
-	print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
-
-	PRINT_WARNING("   Bridge error address 0x%lx",
-		(((uint64_t) bridge->b_wid_err_upper << 32) |
-		 bridge->b_wid_err_lower));
-
-	print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
-
-	if (int_status & (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR)) {
-	    PRINT_WARNING("	Bridge response buffer: dev-num %d buff-num %d addr 0x%lx\n",
-		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
-		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
-		    (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32) |
-		     bridge->b_wid_resp_lower));
-	}
-    }
-    if (int_status & BRIDGE_ISR_SSRAM_PERR)
-	PRINT_WARNING("   Bridge SSRAM parity error register 0x%x",
-		bridge->b_ram_perr);
-
-    if (int_status & BRIDGE_ISR_PCIBUS_ERROR) {
-	PRINT_WARNING("   PCI/GIO error upper address register 0x%x",
-		bridge->b_pci_err_upper);
-
-	PRINT_WARNING("   PCI/GIO error lower address register 0x%x",
-		bridge->b_pci_err_lower);
-    }
-    if (int_status & BRIDGE_ISR_ERROR_FATAL) {
-	PRINT_PANIC("PCI Bridge Error interrupt killed the system");
-	/*NOTREACHED */
-    } else {
-	PRINT_ALERT( "Non-fatal Error in Bridge..");
-    }
-}
-
-#define PCIBR_ERRINTR_GROUP(error)	\
-		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
-
-uint32_t
-pcibr_errintr_group(uint32_t error)
-{
-    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
-
-    if (error & BRIDGE_IRR_PCI_GRP)
-	group |= BRIDGE_IRR_PCI_GRP_CLR;
-    if (error & BRIDGE_IRR_SSRAM_GRP)
-	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
-    if (error & BRIDGE_IRR_LLP_GRP)
-	group |= BRIDGE_IRR_LLP_GRP_CLR;
-    if (error & BRIDGE_IRR_REQ_DSP_GRP)
-	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
-    if (error & BRIDGE_IRR_RESP_BUF_GRP)
-	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
-    if (error & BRIDGE_IRR_CRP_GRP)
-	group |= BRIDGE_IRR_CRP_GRP_CLR;
-
-    return group;
-
-}
-
-
-/* pcibr_pioerr_check():
- *	Check to see if this pcibr has a PCI PIO
- *	TIMEOUT error; if so, clear it and bump
- *	the timeout-count on any piomaps that
- *	could cover the address.
- */
-static void
-pcibr_pioerr_check(pcibr_soft_t soft)
-{
-    bridge_t		   *bridge;
-    bridgereg_t		    b_int_status;
-    bridgereg_t		    b_pci_err_lower;
-    bridgereg_t		    b_pci_err_upper;
-    iopaddr_t		    pci_addr;
-    pciio_slot_t	    slot;
-    pcibr_piomap_t	    map;
-    iopaddr_t		    base;
-    size_t		    size;
-    unsigned		    win;
-    int			    func;
-
-    bridge = soft->bs_base;
-    b_int_status = bridge->b_int_status;
-    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	b_pci_err_lower = bridge->b_pci_err_lower;
-	b_pci_err_upper = bridge->b_pci_err_upper;
-	b_int_status = bridge->b_int_status;
-	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	    bridge->b_int_rst_stat = (BRIDGE_IRR_PCI_GRP_CLR|
-				      BRIDGE_IRR_MULTI_CLR);
-
-	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
-	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
-
-	    slot = 8;
-	    while (slot-- > 0) {
-		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
-		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
-
-		for (func = 0; func < nfunc; func++) {
-		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
-
-		    if (!pcibr_info)
-			continue;
-
-		    for (map = pcibr_info->f_piomap;
-			 map != NULL; map = map->bp_next) {
-			base = map->bp_pciaddr;
-			size = map->bp_mapsz;
-			win = map->bp_space - PCIIO_SPACE_WIN(0);
-			if (win < 6)
-			    base += 
-				soft->bs_slot[slot].bss_window[win].bssw_base;
-			else if (map->bp_space == PCIIO_SPACE_ROM)
-			    base += pcibr_info->f_rbase;
-			if ((pci_addr >= base) && (pci_addr < (base + size)))
-			    atomic_inc(map->bp_toc);
-		    }
-		}
-	    }
-	}
-    }
-}
-
-/*
- * PCI Bridge Error interrupt handler.
- *      This gets invoked, whenever a PCI bridge sends an error interrupt.
- *      Primarily this servers two purposes.
- *              - If an error can be handled (typically a PIO read/write
- *                error, we try to do it silently.
- *              - If an error cannot be handled, we die violently.
- *      Interrupt due to PIO errors:
- *              - Bridge sends an interrupt, whenever a PCI operation
- *                done by the bridge as the master fails. Operations could
- *                be either a PIO read or a PIO write.
- *                PIO Read operation also triggers a bus error, and it's
- *                We primarily ignore this interrupt in that context..
- *                For PIO write errors, this is the only indication.
- *                and we have to handle with the info from here.
- *
- *                So, there is no way to distinguish if an interrupt is
- *                due to read or write error!.
- */
-
-
-LOCAL void
-pcibr_error_intr_handler(intr_arg_t arg)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    bridgereg_t             int_status;
-    bridgereg_t             err_status;
-    int                     i;
-
-    /* REFERENCED */
-    bridgereg_t             disable_errintr_mask = 0;
-
-#if PCIBR_SOFT_LIST
-    /* IP27 seems to be handing us junk.
-     */
-    {
-	pcibr_list_p            entry;
-
-	entry = pcibr_list;
-	while (1) {
-	    if (entry == NULL) {
-		printk("pcibr_error_intr_handler:\n"
-			"\tparameter (0x%p) is not a pcibr_soft!",
-			arg);
-		PRINT_PANIC("Invalid parameter to pcibr_error_intr_handler");
-	    }
-	    if ((intr_arg_t) entry->bl_soft == arg)
-		break;
-	    entry = entry->bl_next;
-	}
-    }
-#endif
-    pcibr_soft = (pcibr_soft_t) arg;
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * pcibr_error_intr_handler gets invoked whenever bridge encounters
-     * an error situation, and the interrupt for that error is enabled.
-     * This routine decides if the error is fatal or not, and takes
-     * action accordingly.
-     *
-     * In one case there is a need for special action.
-     * In case of PIO read/write timeouts due to user level, we do
-     * get an error interrupt. In this case, way to handle would
-     * be to start a timeout. If the error was due to "read", bus
-     * error handling code takes care of it. If error is due to write,
-     * it's handled at timeout
-     */
-
-    /* int_status is which bits we have to clear;
-     * err_status is the bits we haven't handled yet.
-     */
-
-    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
-    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
-
-    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
-	/*
-	 * No error bit set!!.
-	 */
-	return;
-    }
-    /* If we have a PCIBUS_PIOERR,
-     * hand it to the logger but otherwise
-     * ignore the event.
-     */
-    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	pcibr_pioerr_check(pcibr_soft);
-	err_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-	int_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-    }
-
-
-    if (err_status) {
-	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
-
-	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
-	    if (err_status & (1 << i)) {
-		uint32_t              errrate = 0;
-		uint32_t              errcount = 0;
-		uint32_t              errinterval = 0, current_tick = 0;
-		int                     panic_on_llp_tx_retry = 0;
-		int                     is_llp_tx_retry_intr = 0;
-
-		bs_estat->bs_errcount_total++;
-
-#ifdef LATER
-		current_tick = lbolt;
-#else
-		current_tick = 0;
-#endif
-		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
-		errcount = (bs_estat->bs_errcount_total -
-			    bs_estat->bs_lasterr_snapshot);
-
-		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
-
-		/* On a non-zero error rate (which is equivalent to
-		 * to 100 errors /sec at least) for the LLP transmitter
-		 * retry interrupt we need to panic the system
-		 * to prevent potential data corruption .
-		 * NOTE : errcount is being compared to PCIBR_ERRTIME_THRESHOLD
-		 * to make sure that we are not seing cases like x error
-		 * interrupts per y ticks for very low x ,y (x > y ) which
-		 * makes error rate be > 100 /sec.
-		 */
-
-		/* Check for the divide by zero condition while
-		 * calculating the error rates.
-		 */
-
-		if (errinterval) {
-		    errrate = errcount / errinterval;
-		    /* If able to calculate error rate
-		     * on a LLP transmitter retry interrupt check
-		     * if the error rate is nonzero and we have seen
-		     * a certain minimum number of errors.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			errrate &&
-			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		} else {
-		    errrate = 0;
-		    /* Since we are not able to calculate the
-		     * error rate check if we exceeded a certain
-		     * minimum number of errors for LLP transmitter
-		     * retries. Note that this can only happen
-		     * within the first tick after the last snapshot.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		}
-		if (panic_on_llp_tx_retry) {
-		    static uint32_t       last_printed_rate;
-
-		    if (errrate > last_printed_rate) {
-			last_printed_rate = errrate;
-			/* Print the warning only if the error rate
-			 * for the transmitter retry interrupt
-			 * exceeded the previously printed rate.
-			 */
-			PRINT_WARNING(
-				"%s: %s, Excessive error interrupts : %d/tick\n",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-
-		    }
-		    /*
-		     * Update snapshot, and time
-		     */
-		    bs_estat->bs_lasterr_timestamp = current_tick;
-		    bs_estat->bs_lasterr_snapshot =
-			bs_estat->bs_errcount_total;
-
-		}
-		/*
-		 * If the error rate is high enough, print the error rate.
-		 */
-		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
-
-		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
-			PRINT_NOTICE( "%s: %s, Error rate %d/tick",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-			/*
-			 * Update snapshot, and time
-			 */
-			bs_estat->bs_lasterr_timestamp = current_tick;
-			bs_estat->bs_lasterr_snapshot =
-			    bs_estat->bs_errcount_total;
-		    }
-		}
-		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
-		    /*
-		     * We have seen a fairly large number of errors of
-		     * this type. Let's disable the interrupt. But flash
-		     * a message about the interrupt being disabled.
-		     */
-		    PRINT_NOTICE(
-			    "%s Disabling error interrupt type %s. Error count %d",
-			    pcibr_soft->bs_name,
-			    pcibr_isr_errs[i],
-			    bs_estat->bs_errcount_total);
-		    disable_errintr_mask |= (1 << i);
-		}
-	    }
-	}
-    }
-
-    if (disable_errintr_mask) {
-	/*
-	 * Disable some high frequency errors as they
-	 * could eat up too much cpu time.
-	 */
-	bridge->b_int_enable &= ~disable_errintr_mask;
-    }
-    /*
-     * If we leave the PROM cacheable, T5 might
-     * try to do a cache line sized writeback to it,
-     * which will cause a BRIDGE_ISR_INVLD_ADDR.
-     */
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	(0x00000000 == bridge->b_wid_err_upper) &&
-	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
-	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#if defined (PCIBR_LLP_CONTROL_WAR)
-    /*
-     * The bridge bug, where the llp_config or control registers
-     * need to be read back after being written, affects an MP
-     * system since there could be small windows between writing
-     * the register and reading it back on one cpu while another
-     * cpu is fielding an interrupt. If we run into this scenario,
-     * workaround the problem by ignoring the error. (bug 454474)
-     * pcibr_llp_control_war_cnt keeps an approximate number of
-     * times we saw this problem on a system.
-     */
-
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
-	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
-#ifdef LATER
-	if (kdebug)
-	    PRINT_NOTICE( "%s bridge: ignoring llp/control address interrupt",
-		    pcibr_soft->bs_name);
-#endif
-	pcibr_llp_control_war_cnt++;
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#ifdef	DEBUG
-	if (err_status & BRIDGE_ISR_ERROR_DUMP)
-	    pcibr_error_dump(pcibr_soft);
-#else	
-	if (err_status & BRIDGE_ISR_ERROR_FATAL) {
-	    printk("BRIDGE ERR STATUS 0x%x\n", err_status);
-	    pcibr_error_dump(pcibr_soft);
-	}
-#endif
-
-    /*
-     * We can't return without re-enabling the interrupt, since
-     * it would cause problems for devices like IOC3 (Lost
-     * interrupts ?.). So, just cleanup the interrupt, and
-     * use saved values later..
-     */
-    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
-}
-
-/*
- * pcibr_addr_toslot
- *      Given the 'pciaddr' find out which slot this address is
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      function number, space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- */
-LOCAL int
-pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
-		  iopaddr_t pciaddr,
-		  pciio_space_t *spacep,
-		  iopaddr_t *offsetp,
-		  pciio_function_t *funcp)
-{
-    int                     s, f=0, w;
-    iopaddr_t               base;
-    size_t                  size;
-    pciio_piospace_t        piosp;
-
-    /*
-     * Check if the address is in config space
-     */
-
-    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
-
-	if (pciaddr >= BRIDGE_CONFIG1_BASE)
-	    pciaddr -= BRIDGE_CONFIG1_BASE;
-	else
-	    pciaddr -= BRIDGE_CONFIG_BASE;
-
-	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
-	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
-
-	if (funcp) {
-	    f = pciaddr / 0x100;
-	    pciaddr %= 0x100;
-	}
-	if (spacep)
-	    *spacep = PCIIO_SPACE_CFG;
-	if (offsetp)
-	    *offsetp = pciaddr;
-	if (funcp)
-	    *funcp = f;
-
-	return s;
-    }
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    for (w = 0; w < 6; w++) {
-		if (pcibr_info->f_window[w].w_space
-		    == PCIIO_SPACE_NONE) {
-		    continue;
-		}
-		base = pcibr_info->f_window[w].w_base;
-		size = pcibr_info->f_window[w].w_size;
-
-		if ((pciaddr >= base) && (pciaddr < (base + size))) {
-		    if (spacep)
-			*spacep = PCIIO_SPACE_WIN(w);
-		    if (offsetp)
-			*offsetp = pciaddr - base;
-		    if (funcp)
-			*funcp = f;
-		    return s;
-		}			/* endif match */
-	    }				/* next window */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Check if the address was allocated as part of the
-     * pcibr_piospace_alloc calls.
-     */
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    piosp = pcibr_info->f_piospace;
-	    while (piosp) {
-		if ((piosp->start <= pciaddr) &&
-		    ((piosp->count + piosp->start) > pciaddr)) {
-		    if (spacep)
-			*spacep = piosp->space;
-		    if (offsetp)
-			*offsetp = pciaddr - piosp->start;
-		    return s;
-		}			/* endif match */
-		piosp = piosp->next;
-	    }				/* next piosp */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Some other random address on the PCI bus ...
-     * we have no way of knowing whether this was
-     * a MEM or I/O access; so, for now, we just
-     * assume that the low 1G is MEM, the next
-     * 3G is I/O, and anything above the 4G limit
-     * is obviously MEM.
-     */
-
-    if (spacep)
-	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
-		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
-		   PCIIO_SPACE_MEM);
-    if (offsetp)
-	*offsetp = pciaddr;
-
-    return PCIIO_SLOT_NONE;
-
-}
-
-LOCAL void
-pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    ASSERT(error_code & IOECODE_PIO);
-    error_code = error_code;
-
-    bridge->b_int_rst_stat =
-	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
-    (void) bridge->b_wid_tflush;	/* flushbus */
-}
-
-/*
- * pcibr_error_extract
- *      Given the 'pcibr vertex handle' find out which slot
- *      the bridge status error address (from pcibr_soft info
- *      hanging off the vertex)
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- *
- * XXX- this interface has no way to return the function
- * number on a multifunction card, even though that data
- * is available.
- */
-
-pciio_slot_t
-pcibr_error_extract(devfs_handle_t pcibr_vhdl,
-		    pciio_space_t *spacep,
-		    iopaddr_t *offsetp)
-{
-    pcibr_soft_t            pcibr_soft = 0;
-    iopaddr_t               bserr_addr;
-    bridge_t               *bridge;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-    arbitrary_info_t	    rev;
-
-    /* Do a sanity check as to whether we really got a 
-     * bridge vertex handle.
-     */
-    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
-	GRAPH_SUCCESS) 
-	return(slot);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (pcibr_soft) {
-	bridge = pcibr_soft->bs_base;
-	bserr_addr =
-	    bridge->b_pci_err_lower |
-	    ((uint64_t) (bridge->b_pci_err_upper &
-			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
-				 spacep, offsetp, NULL);
-    }
-    return slot;
-}
-
-/*ARGSUSED */
-void
-pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
-{
-    /*
-     * XXX
-     * Device failed to handle error. Take steps to
-     * disable this device ? HOW TO DO IT ?
-     *
-     * If there are any Read response buffers associated
-     * with this device, it's time to get them back!!
-     *
-     * We can disassociate any interrupt level associated
-     * with this device, and disable that interrupt level
-     *
-     * For now it's just a place holder
-     */
-}
-
-/*
- * pcibr_pioerror
- *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
- *
- *      Queries the Bus interface attached to see if the device driver
- *      mapping the device-number that caused error can handle the
- *      situation. If so, it will clean up any error, and return
- *      indicating the error was handled. If the device driver is unable
- *      to handle the error, it expects the bus-interface to disable that
- *      device, and takes any steps needed here to take away any resources
- *      associated with this device.
- */
-
-#define BEM_ADD_STR(s)	printk("%s", (s))
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
-#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
-
-#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
-#else
-#define BEM_ADD_VAR(v)	
-#define BEM_ADD_REG(r)	
-#define BEM_ADD_NSPC(n,s)
-#endif
-#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
-
-/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
- * decodes the PCI specific portions -- we count on our
- * callers to dump the raw IOE data.
- */
-#ifdef LATER
-#define BEM_ADD_IOE(ioe)						\
-	do {								\
-	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
-		unsigned		spc;				\
-		unsigned		win;				\
-									\
-		spc = IOERROR_GETVALUE(ioe, busspace);			\
-		win = spc - PCIIO_SPACE_WIN(0);				\
-									\
-		switch (spc) {						\
-		case PCIIO_SPACE_CFG:					\
-		    printk("\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_IO:					\
-		    printk("\tPCI I/O space  Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_MEM:					\
-		case PCIIO_SPACE_MEM32:					\
-		case PCIIO_SPACE_MEM64:					\
-		    printk("\tPCI MEM space Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		default:						\
-		    if (win < 6) {					\
-		    printk("\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    win,					\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    }							\
-		    break;						\
-		}							\
-	    }								\
-	} while (0)
-#else
-#define BEM_ADD_IOE(ioe)
-#endif
-
-/*ARGSUSED */
-LOCAL int
-pcibr_pioerror(
-		  pcibr_soft_t pcibr_soft,
-		  int error_code,
-		  ioerror_mode_t mode,
-		  ioerror_t *ioe)
-{
-    int                     retval = IOERROR_HANDLED;
-
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    bridgereg_t             bridge_int_status;
-    bridgereg_t             bridge_pci_err_lower;
-    bridgereg_t             bridge_pci_err_upper;
-    bridgereg_t             bridge_pci_err_addr;
-
-    iopaddr_t               bad_xaddr;
-
-    pciio_space_t           raw_space;	/* raw PCI space */
-    iopaddr_t               raw_paddr;	/* raw PCI address */
-
-    pciio_space_t           space;	/* final PCI space */
-    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
-    pciio_function_t        func;	/* final PCI func, if appropriate */
-    iopaddr_t               offset;	/* final PCI offset */
-    
-    int                     cs, cw, cf;
-    pciio_space_t           wx;
-    iopaddr_t               wb;
-    size_t                  ws;
-    iopaddr_t               wl;
-
-
-    /*
-     * We expect to have an "xtalkaddr" coming in,
-     * and need to construct the slot/space/offset.
-     */
-
-#ifdef LATER
-    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
-#else
-    bad_xaddr = -1;
-#endif
-
-    slot = PCIIO_SLOT_NONE;
-    func = PCIIO_FUNC_NONE;
-    raw_space = PCIIO_SPACE_NONE;
-    raw_paddr = 0;
-
-    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
-	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
-	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
-	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
-	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
-	/* Type 1 config space:
-	 * slot and function numbers not known.
-	 * Perhaps we can read them back?
-	 */
-	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
-	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
-	int                     x;
-
-	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
-	x = raw_paddr / BRIDGE_DEVIO_OFF;
-	raw_paddr %= BRIDGE_DEVIO_OFF;
-	/* first two devio windows are double-sized */
-	if ((x == 1) || (x == 3))
-	    raw_paddr += BRIDGE_DEVIO_OFF;
-	if (x > 0)
-	    x--;
-	if (x > 1)
-	    x--;
-	/* x is which devio reg; no guarantee
-	 * PCI slot x will be responding.
-	 * still need to figure out who decodes
-	 * space/offset on the bus.
-	 */
-	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
-	if (raw_space == PCIIO_SPACE_NONE) {
-	    /* Someone got an error because they
-	     * accessed the PCI bus via a DevIO(x)
-	     * window that pcibr has not yet assigned
-	     * to any specific PCI address. It is
-	     * quite possible that the Device(x)
-	     * register has been changed since they
-	     * made their access, but we will give it
-	     * our best decode shot.
-	     */
-	    raw_space = pcibr_soft->bs_slot[x].bss_device
-		& BRIDGE_DEV_DEV_IO_MEM
-		? PCIIO_SPACE_MEM
-		: PCIIO_SPACE_IO;
-	    raw_paddr +=
-		(pcibr_soft->bs_slot[x].bss_device &
-		 BRIDGE_DEV_OFF_MASK) <<
-		BRIDGE_DEV_OFF_ADDR_SHFT;
-	} else
-	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM32;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM64;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
-	raw_space = PCIIO_SPACE_IO;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
-    }
-    space = raw_space;
-    offset = raw_paddr;
-
-    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
-	/* we've got a space/offset but not which
-	 * PCI slot decodes it. Check through our
-	 * notions of which devices decode where.
-	 *
-	 * Yes, this "duplicates" some logic in
-	 * pcibr_addr_toslot; the difference is,
-	 * this code knows which space we are in,
-	 * and can really really tell what is
-	 * going on (no guessing).
-	 */
-
-	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
-	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
-		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
-
-		if (!pcibr_info)
-		    continue;
-		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
-		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
-			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
-			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
-			((wl = wb + ws) > wb) &&
-			((wb <= offset) && (wl > offset))) {
-			/* MEM, MEM32 and MEM64 need to
-			 * compare as equal ...
-			 */
-			if ((wx == space) ||
-			    (((wx == PCIIO_SPACE_MEM) ||
-			      (wx == PCIIO_SPACE_MEM32) ||
-			      (wx == PCIIO_SPACE_MEM64)) &&
-			     ((space == PCIIO_SPACE_MEM) ||
-			      (space == PCIIO_SPACE_MEM32) ||
-			      (space == PCIIO_SPACE_MEM64)))) {
-			    slot = cs;
-			    func = cf;
-			    space = PCIIO_SPACE_WIN(cw);
-			    offset -= wb;
-			}		/* endif window space match */
-		    }			/* endif window valid and addr match */
-		}			/* next window unless slot set */
-	    }				/* next func unless slot set */
-	}				/* next slot unless slot set */
-	/* XXX- if slot is still -1, no PCI devices are
-	 * decoding here using their standard PCI BASE
-	 * registers. This would be a really good place
-	 * to cross-coordinate with the pciio PCI
-	 * address space allocation routines, to find
-	 * out if this address is "allocated" by any of
-	 * our subsidiary devices.
-	 */
-    }
-    /* Scan all piomap records on this PCI bus to update
-     * the TimeOut Counters on all matching maps. If we
-     * don't already know the slot number, take it from
-     * the first matching piomap. Note that we have to
-     * compare maps against raw_space and raw_paddr
-     * since space and offset could already be
-     * window-relative.
-     *
-     * There is a chance that one CPU could update
-     * through this path, and another CPU could also
-     * update due to an interrupt. Closing this hole
-     * would only result in the possibility of some
-     * errors never getting logged at all, and since the
-     * use for bp_toc is as a logical test rather than a
-     * strict count, the excess counts are not a
-     * problem.
-     */
-    for (cs = 0; cs < 8; ++cs) {
-	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	for (cf = 0; cf < nf; cf++) {
-	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
-	    pcibr_piomap_t	map;    
-
-	    if (!pcibr_info)
-		continue;
-
-	    for (map = pcibr_info->f_piomap;
-	     map != NULL; map = map->bp_next) {
-	    wx = map->bp_space;
-	    wb = map->bp_pciaddr;
-	    ws = map->bp_mapsz;
-	    cw = wx - PCIIO_SPACE_WIN(0);
-	    if (cw < 6) {
-		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
-	    }
-	    if (wx == PCIIO_SPACE_ROM) {
-		wb += pcibr_info->f_rbase;
-		wx = PCIIO_SPACE_MEM;
-	    }
-	    if ((wx == PCIIO_SPACE_MEM32) ||
-		(wx == PCIIO_SPACE_MEM64))
-		wx = PCIIO_SPACE_MEM;
-	    wl = wb + ws;
-	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
-		atomic_inc(map->bp_toc);
-		if (slot == PCIIO_SLOT_NONE) {
-		    slot = cs;
-		    space = map->bp_space;
-		    if (cw < 6)
-			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		}
-	    }
-	    }
-	}
-    }
-
-    if (space != PCIIO_SPACE_NONE) {
-	if (slot != PCIIO_SLOT_NONE) {
-#ifdef LATER
-	    if (func != PCIIO_FUNC_NONE)
-		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,func));
-	    else
-    		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,0));
-#else
-            if (func != PCIIO_FUNC_NONE) {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,func));
-            } else {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,0));
-	    }
-#endif
-	}
-
-	IOERROR_SETVALUE(ioe, busspace, space);
-	IOERROR_SETVALUE(ioe, busaddr, offset);
-    }
-    if (mode == MODE_DEVPROBE) {
-	/*
-	 * During probing, we don't really care what the
-	 * error is. Clean up the error in Bridge, notify
-	 * subsidiary devices, and return success.
-	 */
-	pcibr_error_cleanup(pcibr_soft, error_code);
-
-	/* if appropriate, give the error handler for this slot
-	 * a shot at this probe access as well.
-	 */
-	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
-	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    }
-    /*
-     * If we don't know what "PCI SPACE" the access
-     * was targeting, we may have problems at the
-     * Bridge itself. Don't touch any bridge registers,
-     * and do complain loudly.
-     */
-
-    if (space == PCIIO_SPACE_NONE) {
-	printk("XIO Bus Error at %s\n"
-		"\taccess to XIO bus offset 0x%lx\n"
-		"\tdoes not correspond to any PCI address\n",
-		pcibr_soft->bs_name, bad_xaddr);
-
-	/* caller will dump contents of ioe struct */
-	return IOERROR_XTALKLEVEL;
-    }
-    /*
-     * Read the PCI Bridge error log registers.
-     */
-    bridge_int_status = bridge->b_int_status;
-    bridge_pci_err_upper = bridge->b_pci_err_upper;
-    bridge_pci_err_lower = bridge->b_pci_err_lower;
-
-    bridge_pci_err_addr =
-	bridge_pci_err_lower
-	| (((iopaddr_t) bridge_pci_err_upper
-	    & BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-    /*
-     * Actual PCI Error handling situation.
-     * Typically happens when a user level process accesses
-     * PCI space, and it causes some error.
-     *
-     * Due to PCI Bridge implementation, we get two indication
-     * for a read error: an interrupt and a Bus error.
-     * We like to handle read error in the bus error context.
-     * But the interrupt comes and goes before bus error
-     * could make much progress. (NOTE: interrupd does
-     * come in _after_ bus error processing starts. But it's
-     * completed by the time bus error code reaches PCI PIO
-     * error handling.
-     * Similarly write error results in just an interrupt,
-     * and error handling has to be done at interrupt level.
-     * There is no way to distinguish at interrupt time, if an
-     * error interrupt is due to read/write error..
-     */
-
-    /* We know the xtalk addr, the raw PCI bus space,
-     * the raw PCI bus address, the decoded PCI bus
-     * space, the offset within that space, and the
-     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
-     * is known to be involved).
-     */
-
-    /*
-     * Hand the error off to the handler registered
-     * for the slot that should have decoded the error,
-     * or to generic PCI handling (if pciio decides that
-     * such is appropriate).
-     */
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-    if (retval != IOERROR_HANDLED) {
-
-	/* Generate a generic message for IOERROR_UNHANDLED
-	 * since the subsidiary handlers were silent, and
-	 * did no recovery.
-	 */
-	if (retval == IOERROR_UNHANDLED) {
-	    retval = IOERROR_PANIC;
-
-	    /* we may or may not want to print some of this,
-	     * depending on debug level and which error code.
-	     */
-
-	    PRINT_ALERT(
-		    "PIO Error on PCI Bus %s",
-		    pcibr_soft->bs_name);
-	    /* this decodes part of the ioe; our caller
-	     * will dump the raw details in DEBUG and
-	     * kdebug kernels.
-	     */
-	    BEM_ADD_IOE(ioe);
-	}
-#if defined(FORCE_ERRORS)
-	if (0) {
-#elif !DEBUG
-	if (kdebug) {
-#endif
-	    /*
-	       * dump raw data from bridge
-	     */
-
-	    BEM_ADD_STR("DEBUG DATA -- raw info from Bridge ASIC:\n");
-	    BEM_ADD_REG(bridge_int_status);
-	    BEM_ADD_VAR(bridge_pci_err_upper);
-	    BEM_ADD_VAR(bridge_pci_err_lower);
-	    BEM_ADD_VAR(bridge_pci_err_addr);
-	    BEM_ADD_SPC(raw_space);
-	    BEM_ADD_VAR(raw_paddr);
-	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
-
-#ifdef LATER
-		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-#else
-		slot = -1;
-		func = -1;
-#endif
-		if (slot < 8) {
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-		    bridgereg_t             device = bridge->b_device[slot].reg;
-#endif
-
-		    BEM_ADD_VAR(slot);
-		    BEM_ADD_VAR(func);
-		    BEM_ADD_REG(device);
-		}
-	    }
-#if !DEBUG || defined(FORCE_ERRORS)
-	}
-#endif
-
-	/*
-	 * Since error could not be handled at lower level,
-	 * error data logged has not  been cleared.
-	 * Clean up errors, and
-	 * re-enable bridge to interrupt on error conditions.
-	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
-	 * dependent on INT_ENABLE register. This write just makes sure
-	 * that if the interrupt was enabled, we do get the interrupt.
-	 *
-	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
-	 *      a group of interrupts. If while handling this error,
-	 *      some other error has occurred, that would be
-	 *      implicitly cleared by this write.
-	 *      Need a way to ensure we don't inadvertently clear some
-	 *      other errors.
-	 */
-#ifdef LATER
-	if (IOERROR_FIELDVALID(ioe, widgetdev))
-	    pcibr_device_disable(pcibr_soft, 
-				 pciio_widgetdev_slot_get(
-					  IOERROR_GETVALUE(ioe, widgetdev)));
-#endif
-
-	if (mode == MODE_DEVUSERERROR)
-	    pcibr_error_cleanup(pcibr_soft, error_code);
-    }
-    return retval;
-}
-
-/*
- * bridge_dmaerror
- *      Some error was identified in a DMA transaction.
- *      This routine will identify the <device, address> that caused the error,
- *      and try to invoke the appropriate bus service to handle this.
- */
-
-#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
-
-int
-pcibr_dmard_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             bus_lowaddr, bus_uppraddr;
-    int                     retval = 0;
-    int                     bufnum;
-
-    /*
-     * In case of DMA errors, bridge should have logged the
-     * address that caused the error.
-     * Look up the address, in the bridge error registers, and
-     * take appropriate action
-     */
-#ifdef LATER
-    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
-    ASSERT(bridge);
-#endif
-
-    /*
-     * read error log registers
-     */
-    bus_lowaddr = bridge->b_wid_resp_lower;
-    bus_uppraddr = bridge->b_wid_resp_upper;
-
-    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
-    IOERROR_SETVALUE(ioe, widgetdev, 
-		     pciio_widgetdev_create(
-				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
-				    0));
-    IOERROR_SETVALUE(ioe, busaddr,
-		     (bus_lowaddr |
-		      ((iopaddr_t)
-		       (bus_uppraddr &
-			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
-
-    /*
-     * need to ensure that the xtalk address in ioe
-     * maps to PCI error address read from bridge.
-     * How to convert PCI address back to Xtalk address ?
-     * (better idea: convert XTalk address to PCI address
-     * and then do the compare!)
-     */
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    if (retval != IOERROR_HANDLED)
-#ifdef LATER
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe,widgetdev)));
-#else
-	pcibr_device_disable(pcibr_soft,
-			     pciio_widgetdev_slot_get(-1));
-#endif
-
-    /*
-     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
-     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
-     * not is dependent on INT_ENABLE register. This write just makes sure
-     * that if the interrupt was enabled, we do get the interrupt.
-     */
-    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
-
-    /*
-     * Also, release the "bufnum" back to buffer pool that could be re-used.
-     * This is done by "disabling" the buffer for a moment, then restoring
-     * the original assignment.
-     */
-
-    {
-	reg_p                   regp;
-	bridgereg_t             regv;
-	bridgereg_t             mask;
-
-	regp = (bufnum & 1)
-	    ? &bridge->b_odd_resp
-	    : &bridge->b_even_resp;
-
-	mask = 0xF << ((bufnum >> 1) * 4);
-
-	regv = *regp;
-	*regp = regv & ~mask;
-	*regp = regv;
-    }
-
-    return retval;
-}
-
-/*
- * pcibr_dmawr_error:
- *      Handle a dma write error caused by a device attached to this bridge.
- *
- *      ioe has the widgetnum, widgetdev, and memaddr fields updated
- *      But we don't know the PCI address that corresponds to "memaddr"
- *      nor do we know which device driver is generating this address.
- *
- *      There is no easy way to find out the PCI address(es) that map
- *      to a specific system memory address. Bus handling code is also
- *      of not much help, since they don't keep track of the DMA mapping
- *      that have been handed out.
- *      So it's a dead-end at this time.
- *
- *      If translation is available, we could invoke the error handling
- *      interface of the device driver.
- */
-/*ARGSUSED */
-int
-pcibr_dmawr_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    int                     retval;
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-#ifdef LATER
-    if (retval != IOERROR_HANDLED) {
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe, widgetdev)));
-
-    }
-#endif
-    return retval;
-}
-
-/*
- * Bridge error handler.
- *      Interface to handle all errors that involve bridge in some way.
- *
- *      This normally gets called from xtalk error handler.
- *      ioe has different set of fields set depending on the error that
- *      was encountered. So, we have a bit field indicating which of the
- *      fields are valid.
- *
- * NOTE: This routine could be operating in interrupt context. So,
- *      don't try to sleep here (till interrupt threads work!!)
- */
-LOCAL int
-pcibr_error_handler(
-		       error_handler_arg_t einfo,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioe)
-{
-    pcibr_soft_t            pcibr_soft;
-    int                     retval = IOERROR_BADERRORCODE;
-
-    pcibr_soft = (pcibr_soft_t) einfo;
-
-    /* If we are in the action handling phase clean out the error state
-     * on the xswitch.
-     */
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    if (e_state == ERROR_STATE_ACTION)
-	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
-#endif
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
-#endif
-
-    ASSERT(pcibr_soft != NULL);
-
-    if (error_code & IOECODE_PIO)
-	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
-
-    if (error_code & IOECODE_DMA) {
-	if (error_code & IOECODE_READ) {
-	    /*
-	     * DMA read error occurs when a device attached to the bridge
-	     * tries to read some data from system memory, and this
-	     * either results in a timeout or access error.
-	     * First case is indicated by the bit "XREAD_REQ_TOUT"
-	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
-	     * interrupt status register.
-	     *
-	     * pcibr_error_intr_handler would get invoked first, and it has
-	     * the responsibility of calling pcibr_error_handler with
-	     * suitable parameters.
-	     */
-
-	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-	if (error_code & IOECODE_WRITE) {
-	    /*
-	     * A device attached to this bridge has been generating
-	     * bad DMA writes. Find out the device attached, and
-	     * slap on it's wrist.
-	     */
-
-	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-    }
-    return retval;
-
-}
-
-/*
- * Reenable a device after handling the error.
- * This is called by the lower layers when they wish to be reenabled
- * after an error.
- * Note that each layer would be calling the previous layer to reenable
- * first, before going ahead with their own re-enabling.
- */
-
-int
-pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    ASSERT(error_code & IOECODE_PIO);
-
-    /* If the error is not known to be a write,
-     * we have to call devenable.
-     * write errors are isolated to the bridge.
-     */
-    if (!(error_code & IOECODE_WRITE)) {
-	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-	int                     rc;
-
-	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
-	if (rc != IOERROR_HANDLED)
-	    return rc;
-    }
-    pcibr_error_cleanup(pcibr_soft, error_code);
-    return IOERROR_HANDLED;
-}
-
-/* =====================================================================
- *    CONFIGURATION MANAGEMENT
- */
-/*ARGSUSED */
-void
-pcibr_provider_startup(devfs_handle_t pcibr)
-{
-}
-
-/*ARGSUSED */
-void
-pcibr_provider_shutdown(devfs_handle_t pcibr)
-{
-}
-
-int
-pcibr_reset(devfs_handle_t conn)
-{
-    pciio_info_t            pciio_info = pciio_info_get(conn);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             ctlreg;
-    unsigned                cfgctl[8];
-    unsigned long           s;
-    int                     f, nf;
-    pcibr_info_h            pcibr_infoh;
-    pcibr_info_t            pcibr_info;
-    int                     win;
-
-    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
-	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
-    }
-    if (pciio_slot < 4) {
-	s = pcibr_lock(pcibr_soft);
-	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
-	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
-
-	ctlreg = bridge->b_wid_control;
-	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
-	/* XXX delay? */
-	bridge->b_wid_control = ctlreg;
-	/* XXX delay? */
-
-	for (f = 0; f < nf; ++f)
-	    if ((pcibr_info = pcibr_infoh[f]))
-		for (win = 0; win < 6; ++win)
-		    if (pcibr_info->f_window[win].w_base != 0)
-			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
-			    pcibr_info->f_window[win].w_base;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
-	pcibr_unlock(pcibr_soft, s);
-
-	return 0;
-    }
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING( "%v: pcibr_reset unimplemented for slot %d\n",
-	    conn, pciio_slot);
-#endif
-    return -1;
-}
-
-pciio_endian_t
-pcibr_endian_set(devfs_handle_t pconn_vhdl,
-		 pciio_endian_t device_end,
-		 pciio_endian_t desired_end)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             devreg;
-    unsigned long           s;
-
-    /*
-     * Bridge supports hardware swapping; so we can always
-     * arrange for the caller's desired endianness.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_end != desired_end)
-	devreg |= BRIDGE_DEV_SWAP_BITS;
-    else
-	devreg &= ~BRIDGE_DEV_SWAP_BITS;
-
-    /* NOTE- if we ever put SWAP bits
-     * onto the disabled list, we will
-     * have to change the logic here.
-     */
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
-#endif
-
-    return desired_end;
-}
-
-/* This (re)sets the GBR and REALTIME bits and also keeps track of how
- * many sets are outstanding. Reset succeeds only if the number of outstanding
- * sets == 1.
- */
-int
-pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
-			pciio_slot_t pciio_slot,
-			pciio_priority_t device_prio)
-{
-    unsigned long           s;
-    int                    *counter;
-    bridgereg_t             rtbits = 0;
-    bridgereg_t             devreg;
-    int                     rc = PRIO_SUCCESS;
-
-    /* in dual-slot configurations, the host and the
-     * guest have separate DMA resources, so they
-     * have separate requirements for priority bits.
-     */
-
-    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
-
-    /*
-     * Bridge supports PCI notions of LOW and HIGH priority
-     * arbitration rings via a "REAL_TIME" bit in the per-device
-     * Bridge register. The "GBR" bit controls access to the GBR
-     * ring on the xbow. These two bits are (re)set together.
-     *
-     * XXX- Bug in Rev B Bridge Si:
-     * Symptom: Prefetcher starts operating incorrectly. This happens
-     * due to corruption of the address storage ram in the prefetcher
-     * when a non-real time PCI request is pulled and a real-time one is
-     * put in it's place. Workaround: Use only a single arbitration ring
-     * on PCI bus. GBR and RR can still be uniquely used per
-     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
-     */
-
-    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
-	rtbits |= BRIDGE_DEV_RT;
-
-    /* NOTE- if we ever put DEV_RT or DEV_GBR on
-     * the disabled list, we will have to take
-     * it into account here.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_prio == PCI_PRIO_HIGH) {
-	if ((++*counter == 1)) {
-	    if (rtbits)
-		devreg |= rtbits;
-	    else
-		rc = PRIO_FAIL;
-	}
-    } else if (device_prio == PCI_PRIO_LOW) {
-	if (*counter <= 0)
-	    rc = PRIO_FAIL;
-	else if (--*counter == 0)
-	    if (rtbits)
-		devreg &= ~rtbits;
-    }
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-    return rc;
-}
-
-pciio_priority_t
-pcibr_priority_set(devfs_handle_t pconn_vhdl,
-		   pciio_priority_t device_prio)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
-
-    return device_prio;
-}
-
-/*
- * Interfaces to allow special (e.g. SGI) drivers to set/clear
- * Bridge-specific device flags.  Many flags are modified through
- * PCI-generic interfaces; we don't allow them to be directly
- * manipulated here.  Only flags that at this point seem pretty
- * Bridge-specific can be set through these special interfaces.
- * We may add more flags as the need arises, or remove flags and
- * create PCI-generic interfaces as the need arises.
- *
- * Returns 0 on failure, 1 on success
- */
-int
-pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
-		       pcibr_device_flags_t flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             set = 0;
-    bridgereg_t             clr = 0;
-
-    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_PMU_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_PMU_WRGA_EN;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_DIR_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_DIR_WRGA_EN;
-
-    if (flags & PCIBR_PREFETCH)
-	set |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	clr |= BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	set |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	clr |= BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	set |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	clr |= BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	set |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	clr |= BRIDGE_DEV_DEV_SIZE;
-
-    if (set || clr) {
-	bridgereg_t             devreg;
-	unsigned long           s;
-
-	s = pcibr_lock(pcibr_soft);
-	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-	devreg = (devreg & ~clr) | set;
-	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-
-	    bridge->b_device[pciio_slot].reg = devreg;
-	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	}
-	pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
-#endif
-    }
-    return (1);
-}
-
-#ifdef LITTLE_ENDIAN
-/*
- * on sn-ia we need to twiddle the addresses going out
- * the pci bus because we use the unswizzled synergy space
- * (the alternative is to use the swizzled synergy space
- * and byte swap the data)
- */
-#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
-#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
-#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
-#else
-#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
-#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
-#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
-#endif /* LITTLE_ENDIAN */
-
-
-LOCAL                   cfg_p
-pcibr_config_addr(devfs_handle_t conn,
-		  unsigned reg)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_slot_t            pciio_slot;
-    pciio_function_t        pciio_func;
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    cfg_p                   cfgbase = (cfg_p)0;
-
-    pcibr_info = pcibr_info_get(conn);
-
-    pciio_slot = pcibr_info->f_slot;
-    if (pciio_slot == PCIIO_SLOT_NONE)
-	pciio_slot = PCI_TYPE1_SLOT(reg);
-
-    pciio_func = pcibr_info->f_func;
-    if (pciio_func == PCIIO_FUNC_NONE)
-	pciio_func = PCI_TYPE1_FUNC(reg);
-
-    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    bridge = pcibr_soft->bs_base;
-
-    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
-
-    return cfgbase;
-}
-
-uint64_t
-pcibr_config_get(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size)
-{
-    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
-			       PCI_TYPE1_REG(reg), size);
-}
-
-LOCAL uint64_t
-do_pcibr_config_get(
-		       cfg_p cfgbase,
-		       unsigned reg,
-		       unsigned size)
-{
-    unsigned                value;
-
-   
-    value = CW(cfgbase, reg);
-
-    if (reg & 3)
-	value >>= 8 * (reg & 3);
-    if (size < 4)
-	value &= (1 << (8 * size)) - 1;
-
-    return value;
-}
-
-void
-pcibr_config_set(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size,
-		 uint64_t value)
-{
-    do_pcibr_config_set(pcibr_config_addr(conn, reg),
-			PCI_TYPE1_REG(reg), size, value);
-}
-
-LOCAL void
-do_pcibr_config_set(cfg_p cfgbase,
-		    unsigned reg,
-		    unsigned size,
-		    uint64_t value)
-{
-    switch (size) {
-    case 1:
-	CB(cfgbase, reg) = value;
-	break;
-    case 2:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 1) = value >> 8;
-	} else
-	    CS(cfgbase, reg) = value;
-	break;
-    case 3:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CS(cfgbase, (reg + 1)) = value >> 8;
-	} else {
-	    CS(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 2) = value >> 16;
-	}
-	break;
-
-    case 4:
-	CW(cfgbase, reg) = value;
-	break;
-    }
-}
-
-pciio_provider_t        pcibr_provider =
-{
-    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
-    (pciio_piomap_free_f *) pcibr_piomap_free,
-    (pciio_piomap_addr_f *) pcibr_piomap_addr,
-    (pciio_piomap_done_f *) pcibr_piomap_done,
-    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
-    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
-    (pciio_piospace_free_f *) pcibr_piospace_free,
-
-    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
-    (pciio_dmamap_free_f *) pcibr_dmamap_free,
-    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
-    (pciio_dmamap_list_f *) pcibr_dmamap_list,
-    (pciio_dmamap_done_f *) pcibr_dmamap_done,
-    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
-    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
-    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
-    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
-    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
-
-    (pciio_intr_alloc_f *) pcibr_intr_alloc,
-    (pciio_intr_free_f *) pcibr_intr_free,
-    (pciio_intr_connect_f *) pcibr_intr_connect,
-    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
-    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
-
-    (pciio_provider_startup_f *) pcibr_provider_startup,
-    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
-    (pciio_reset_f *) pcibr_reset,
-    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
-    (pciio_endian_set_f *) pcibr_endian_set,
-    (pciio_priority_set_f *) pcibr_priority_set,
-    (pciio_config_get_f *) pcibr_config_get,
-    (pciio_config_set_f *) pcibr_config_set,
-
-    (pciio_error_devenable_f *) pcibr_error_devenable,
-    (pciio_error_extract_f *) pcibr_error_extract,
-
-#ifdef LATER
-    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
-    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
-#else
-    (pciio_driver_reg_callback_f *) 0,
-    (pciio_driver_unreg_callback_f *) 0,
-#endif
-    (pciio_device_unregister_f 	*) pcibr_device_unregister,
-    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
-};
-
-LOCAL                   pcibr_hints_t
-pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
-{
-    arbitrary_info_t        ainfo = 0;
-    graph_error_t	    rv;
-    pcibr_hints_t           hint;
-
-    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-
-    if (alloc && (rv != GRAPH_SUCCESS)) {
-
-	NEW(hint);
-	hint->rrb_alloc_funct = NULL;
-	hint->ph_intr_bits = NULL;
-	rv = hwgraph_info_add_LBL(xconn_vhdl, 
-				  INFO_LBL_PCIBR_HINTS, 	
-				  (arbitrary_info_t) hint);
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-	
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	if (ainfo != (arbitrary_info_t) hint)
-	    goto abnormal_exit;
-    }
-    return (pcibr_hints_t) ainfo;
-
-abnormal_exit:
-#ifdef LATER
-    printf("SHOULD NOT BE HERE\n");
-#endif
-    DEL(hint);
-    return(NULL);
-
-}
-
-void
-pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_rrb_fixed = mask;
-#if DEBUG
-    else
-	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
-}
-
-void
-pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
-		     pciio_slot_t host,
-		     pciio_slot_t guest)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_host_slot[guest] = host + 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
-		      pcibr_intr_bits_f *xxx_intr_bits)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_intr_bits = xxx_intr_bits;
-#if DEBUG
-    else
-	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
-	       "\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->rrb_alloc_funct = rrb_alloc_funct;
-}
-
-void
-pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_hands_off = 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
-		    pciio_slot_t slot,
-		    uint64_t subdevs)
-{
-    arbitrary_info_t        ainfo = 0;
-    char                    sdname[16];
-    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
-
-    sprintf(sdname, "pci/%d", slot);
-    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
-    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
-#if DEBUG
-	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
-		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
-#endif
-	return;
-    }
-    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-    if (ainfo == 0) {
-	uint64_t                *subdevp;
-
-	NEW(subdevp);
-	if (!subdevp) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-	*subdevp = subdevs;
-	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
-	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-	if (ainfo == (arbitrary_info_t) subdevp)
-	    return;
-	DEL(subdevp);
-	if (ainfo == (arbitrary_info_t) NULL) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-#if DEBUG
-	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
-		"\t%p\n", pconn_vhdl);
-#endif
-    }
-    *(uint64_t *) ainfo = subdevs;
-}
-
-
-#ifdef LATER
-
-#include <sys/idbg.h>
-#include <sys/idbgentry.h>
-
-char *pci_space[] = {"NONE", 
-		     "ROM",
-		     "IO",
-		     "",
-		     "MEM",
-		     "MEM32",
-		     "MEM64",
-		     "CFG",
-		     "WIN0",
-		     "WIN1",
-		     "WIN2",
-		     "WIN3",
-		     "WIN4",
-		     "WIN5",
-		     "",
-		     "BAD"};
-
-void
-idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
-{
-    pcibr_info_t	pcibr_info = pcibr_infoh[func];
-    char		name[MAXDEVNAME];
-    int			win;
-    
-    if (!pcibr_info)
-	return;
-    qprintf("Per-slot Function Info\n");
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_vertex);
-#endif
-    qprintf("\tSlot Name : %s\n",name);
-    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
-    qprintf("Slot : %d ", pcibr_info->f_slot);
-    qprintf("Function : %d ", pcibr_info->f_func);
-    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
-    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_master);
-#endif
-    qprintf("\tBus provider : %s\n",name);
-    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
-    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
-	    pcibr_info->f_efunc,pcibr_info->f_einfo);
-    for(win = 0 ; win < 6 ; win++) 
-	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
-		win,pci_space[pcibr_info->f_window[win].w_space],
-		pcibr_info->f_window[win].w_base,
-		pcibr_info->f_window[win].w_size);
-
-    qprintf("\tRom base 0x%x size 0x%x\n", 
-	    pcibr_info->f_rbase,pcibr_info->f_rsize);
-
-    qprintf("\tInterrupt Bit Map\n");
-    qprintf("\t\tPCI Int#\tBridge Pin#\n");
-    for (win = 0 ; win < 4; win++)
-	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
-    qprintf("\n");
-}
-
-
-void
-idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
-{
-    pcibr_soft_slot_t	pss;
-    char		slot_conn_name[MAXDEVNAME];
-    int			func;
-
-    pss = &pcibr_soft->bs_slot[slot];
-    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
-    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
-    qprintf("\tHost Slot : %d\n",pss->host_slot);
-    sprintf(slot_conn_name, "%v", pss->slot_conn);
-    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
-    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
-    for (func = 0; func < pss->bss_ninfo; func++)
-	idbg_pss_func(pss->bss_infos,func);
-    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
-    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
-    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
-    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
-	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
-    
-    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
-	    "d32_base 0x%x d32_flags 0x%x\n",
-	    pss->bss_d64_base, pss->bss_d64_flags,
-	    pss->bss_d32_base, pss->bss_d32_flags);
-    
-    qprintf("\tExt ATEs active ? %s", 
-	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
-    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
-    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
-
-    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
-	    pcibr_soft->bs_rrb_valid[slot],
-	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-		
-}
-
-int	ips = 0;
-
-void
-idbg_pss(pcibr_soft_t pcibr_soft)
-{
-    pciio_slot_t	slot;
-
-    
-    if (ips >= 0 && ips < 8)
-	idbg_pss_info(pcibr_soft,ips);
-    else if (ips < 0)
-	for (slot = 0; slot < 8; slot++) 
-	    idbg_pss_info(pcibr_soft,slot);
-    else
-	qprintf("Invalid ips %d\n",ips);
-}
-
-#endif /* LATER */
-
-int
-pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-	
-
-    return xtalk_dma_enabled(pcibr_soft->bs_conn);
-}
diff -urN linux-2.4.16/arch/ia64/sn/io/pciio.c lia64-2.4/arch/ia64/sn/io/pciio.c
--- linux-2.4.16/arch/ia64/sn/io/pciio.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/pciio.c	Mon Nov 19 23:22:52 2001
@@ -4,14 +4,18 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #define	USRPCI	0
 
+#include <linux/init.h>
 #include <linux/types.h>
 #include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/xtalk/xbow.h>	/* Must be before iograph.h to get MAX_PORT_NUM */
@@ -25,13 +29,15 @@
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pciio_private.h>
 #include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/pci/pci_bus_cvlink.h>
 
 #define DEBUG_PCIIO
 #undef DEBUG_PCIIO	/* turn this on for yet more console output */
 
 
-#define NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
-#define DEL(ptr)	(kfree(ptr))
+#define GET_NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+#define DO_DEL(ptr)	(kfree(ptr))
 
 char                    pciio_info_fingerprint[] = "pciio_info";
 
@@ -105,7 +111,7 @@
  * completely disappear.
  */
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  *    For the moment, we will assume that IP27
  *      only use Bridge ASICs to provide PCI support.
@@ -115,7 +121,7 @@
 #define CAST_PIOMAP(x)		((pcibr_piomap_t)(x))
 #define CAST_DMAMAP(x)		((pcibr_dmamap_t)(x))
 #define CAST_INTR(x)		((pcibr_intr_t)(x))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 /* =====================================================================
  *    Function Table of Contents
@@ -150,14 +156,11 @@
 
 pciio_intr_t            pciio_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
 void                    pciio_intr_free(pciio_intr_t);
-int                     pciio_intr_connect(pciio_intr_t, intr_func_t, intr_arg_t, void *thread);
+int                     pciio_intr_connect(pciio_intr_t);
 void                    pciio_intr_disconnect(pciio_intr_t);
 devfs_handle_t            pciio_intr_cpu_get(pciio_intr_t);
 
 void			pciio_slot_func_to_name(char *, pciio_slot_t, pciio_function_t);
-static pciio_info_t     pciio_cardinfo_get(devfs_handle_t, pciio_slot_t);
-int                     pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
-int                     pciio_error_devenable(devfs_handle_t, int);
 
 void                    pciio_provider_startup(devfs_handle_t);
 void                    pciio_provider_shutdown(devfs_handle_t);
@@ -257,7 +260,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	PRINT_PANIC("%v: provider_fns == NULL", dev);
 #else
-	PRINT_PANIC("0x%x: provider_fns == NULL", dev);
+	PRINT_PANIC("0x%p: provider_fns == NULL", (void *)dev);
 #endif
 
     return provider_fns;
@@ -575,13 +578,10 @@
  * Returns 0 on success, returns <0 on failure.
  */
 int
-pciio_intr_connect(pciio_intr_t intr_hdl,	/* pciio intr resource handle */
-		   intr_func_t intr_func,	/* pciio intr handler */
-		   intr_arg_t intr_arg,	/* arg to intr handler */
-		   void *thread)
-{					/* intr thread to use */
+pciio_intr_connect(pciio_intr_t intr_hdl)	/* pciio intr resource handle */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, thread);
+	(CAST_INTR(intr_hdl));
 }
 
 /*
@@ -605,10 +605,6 @@
 	(CAST_INTR(intr_hdl));
 }
 
-/* =====================================================================
- *          ERROR MANAGEMENT
- */
-
 void
 pciio_slot_func_to_name(char		       *name,
 			pciio_slot_t		slot,
@@ -630,193 +626,6 @@
 	sprintf(name, "%d%c", slot, 'a'+func);
 }
 
-/*
- * pciio_cardinfo_get
- *
- * Get the pciio info structure corresponding to the
- * specified PCI "slot" (we like it when the same index
- * number is used for the PCI IDSEL, the REQ/GNT pair,
- * and the interrupt line being used for INTA. We like
- * it so much we call it the slot number).
- */
-static pciio_info_t
-pciio_cardinfo_get(
-		      devfs_handle_t pciio_vhdl,
-		      pciio_slot_t pci_slot)
-{
-    char                    namebuf[16];
-    pciio_info_t	    info = 0;
-    devfs_handle_t	    conn;
-
-    pciio_slot_func_to_name(namebuf, pci_slot, PCIIO_FUNC_NONE);
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(pciio_vhdl, namebuf, &conn)) {
-	info = pciio_info_chk(conn);
-	hwgraph_vertex_unref(conn);
-    }
-
-    return info;
-}
-
-/*
- * pciio_error_handler:
- * dispatch an error to the appropriate
- * pciio connection point, or process
- * it as a generic pci error.
- * Yes, the first parameter is the
- * provider vertex at the middle of
- * the bus; we get to the pciio connect
- * point using the ioerror widgetdev field.
- *
- * This function is called by the
- * specific PCI provider, after it has figured
- * out where on the PCI bus (including which slot,
- * if it can tell) the error came from.
- */
-/*ARGSUSED */
-int
-pciio_error_handler(
-		       devfs_handle_t pciio_vhdl,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    pciio_info_t            pciio_info;
-    devfs_handle_t            pconn_vhdl;
-#if USRPCI
-    devfs_handle_t            usrpci_v;
-#endif
-    pciio_slot_t            slot;
-
-    int                     retval;
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    error_state_t	    e_state;
-#endif
-
-#if DEBUG && ERROR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    printk("%v: pciio_error_handler\n", pciio_vhdl);
-#else
-    printk("0x%x: pciio_error_handler\n", pciio_vhdl);
-#endif
-#endif
-
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    IOERR_PRINTF(printk("%v: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#else
-    IOERR_PRINTF(printk("0x%x: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#endif
-
-    /* If there is an error handler sitting on
-     * the "no-slot" connection point, give it
-     * first crack at the error. NOTE: it is
-     * quite possible that this function may
-     * do further refining of the ioerror.
-     */
-    pciio_info = pciio_cardinfo_get(pciio_vhdl, PCIIO_SLOT_NONE);
-    if (pciio_info && pciio_info->c_efunc) {
-	pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-	e_state = error_state_get(pciio_vhdl);
-
-	if (e_state == ERROR_STATE_ACTION)
-	    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-	if (error_state_set(pconn_vhdl,e_state) ==
-	    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-	    return(IOERROR_UNHANDLED);
-#endif
-	retval = pciio_info->c_efunc
-	    (pciio_info->c_einfo, error_code, mode, ioerror);
-	if (retval != IOERROR_UNHANDLED)
-	    return retval;
-    }
-
-    /* Is the error associated with a particular slot?
-     */
-    if (IOERROR_FIELDVALID(ioerror, widgetdev)) {
-	/*
-	 * NOTE : 
-	 * widgetdev is a 4byte value encoded as slot in the higher order
-	 * 2 bytes and function in the lower order 2 bytes.
-	 */
-#ifdef LATER
-	slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioerror, widgetdev));
-#else
-	slot = 0;
-#endif
-
-	/* If this slot has an error handler,
-	 * deliver the error to it.
-	 */
-	pciio_info = pciio_cardinfo_get(pciio_vhdl, slot);
-	if (pciio_info != NULL) {
-	    if (pciio_info->c_efunc != NULL) {
-
-		pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-		e_state = error_state_get(pciio_vhdl);
-
-
-		if (e_state == ERROR_STATE_ACTION)
-		    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-
-
-		if (error_state_set(pconn_vhdl,e_state) ==
-		    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-		    return(IOERROR_UNHANDLED);
-#endif
-		retval = pciio_info->c_efunc
-		    (pciio_info->c_einfo, error_code, mode, ioerror);
-		if (retval != IOERROR_UNHANDLED)
-		    return retval;
-	    }
-
-#if USRPCI
-	    /* If the USRPCI driver is available and
-	     * knows about this connection point,
-	     * deliver the error to it.
-	     *
-	     * OK to use pconn_vhdl here, even though we
-	     * have already UNREF'd it, since we know that
-	     * it is not going away.
-	     */
-	    pconn_vhdl = pciio_info_dev_get(pciio_info);
-	    if (GRAPH_SUCCESS ==
-		hwgraph_traverse(pconn_vhdl, EDGE_LBL_USRPCI, &usrpci_v)) {
-		retval = usrpci_error_handler
-		    (usrpci_v, error_code, IOERROR_GETVALUE(ioerror, busaddr));
-		hwgraph_vertex_unref(usrpci_v);
-		if (retval != IOERROR_UNHANDLED) {
-		    /*
-		     * This unref is not needed.  If this code is called often enough,
-		     * the system will crash, due to vertex reference count reaching 0,
-		     * causing vertex to be unallocated.  -jeremy
-		     * hwgraph_vertex_unref(pconn_vhdl);
-		     */
-		    return retval;
-		}
-	    }
-#endif
-	}
-    }
-
-    return (mode == MODE_DEVPROBE)
-	? IOERROR_HANDLED	/* probes are OK */
-	: IOERROR_UNHANDLED;	/* otherwise, foo! */
-}
-
-int
-pciio_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    return DEV_FUNC(pconn_vhdl, error_devenable)
-	(pconn_vhdl, error_code);
-    /* no cleanup specific to this layer. */
-}
-
 /* =====================================================================
  *          CONFIGURATION MANAGEMENT
  */
@@ -856,12 +665,12 @@
 
 #if DEBUG
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-    PRINT_ALERT("%v: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "%v: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
 #else
-    PRINT_ALERT("0x%x: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "0x%x: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
@@ -944,14 +753,6 @@
 /* =====================================================================
  *          GENERIC PCI SUPPORT FUNCTIONS
  */
-pciio_slot_t
-pciio_error_extract(devfs_handle_t 	dev,
-		   pciio_space_t 	*space,
-		   iopaddr_t		*offset)
-{
-	ASSERT(dev != NODEV);
-	return DEV_FUNC(dev,error_extract)(dev,space,offset);
-}
 
 /*
  * Issue a hardware reset to a card.
@@ -1388,7 +1189,7 @@
 		pciio_device_id_t device_id)
 {
     if (!pciio_info)
-	NEW(pciio_info);
+	GET_NEW(pciio_info);
     ASSERT(pciio_info != NULL);
 
     pciio_info->c_slot = slot;
@@ -1420,6 +1221,7 @@
 {
     char		name[32];
     devfs_handle_t	pconn;
+    int device_master_set(devfs_handle_t, devfs_handle_t);
 
     pciio_slot_func_to_name(name,
 			    pciio_info->c_slot,
@@ -1520,7 +1322,6 @@
     pciio_info_t            pciio_info;
     pciio_vendor_id_t       vendor_id;
     pciio_device_id_t       device_id;
-    int pciba_attach(devfs_handle_t);
 
 
     pciio_device_inventory_add(pconn);
@@ -1536,11 +1337,6 @@
      */
     ASSERT(pciio_registry != NULL);
 
-    /*
-     * Since pciba is not called from cdl routines .. call it here.
-     */
-    pciba_attach(pconn);
-
     return(cdl_add_connpt(pciio_registry, vendor_id, device_id, pconn, drv_flags));
 }
 
@@ -1625,3 +1421,71 @@
 {
 	return DEV_FUNC(pconn_vhdl, dma_enabled)(pconn_vhdl);
 }
+
+/*
+ * These are complementary Linux interfaces that takes in a pci_dev * as the 
+ * first arguement instead of devfs_handle_t.
+ */
+iopaddr_t               snia_pciio_dmatrans_addr(struct pci_dev *, device_desc_t, paddr_t, size_t, unsigned);
+pciio_dmamap_t          snia_pciio_dmamap_alloc(struct pci_dev *, device_desc_t, size_t, unsigned);
+void                    snia_pciio_dmamap_free(pciio_dmamap_t);
+iopaddr_t               snia_pciio_dmamap_addr(pciio_dmamap_t, paddr_t, size_t);
+void                    snia_pciio_dmamap_done(pciio_dmamap_t);
+
+#include <linux/module.h>
+EXPORT_SYMBOL(snia_pciio_dmatrans_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_alloc);
+EXPORT_SYMBOL(snia_pciio_dmamap_free);
+EXPORT_SYMBOL(snia_pciio_dmamap_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_done);
+
+iopaddr_t
+snia_pciio_dmatrans_addr(struct pci_dev *pci_dev, /* translate for this device */
+                    device_desc_t dev_desc,     /* device descriptor */
+                    paddr_t paddr,      /* system physical address */
+                    size_t byte_count,  /* length */
+                    unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return DEV_FUNC(dev, dmatrans_addr)
+        (dev, dev_desc, paddr, byte_count, flags);
+}
+
+pciio_dmamap_t
+snia_pciio_dmamap_alloc(struct pci_dev *pci_dev,  /* set up mappings for this device */
+                   device_desc_t dev_desc,      /* device descriptor */
+                   size_t byte_count_max,       /* max size of a mapping */
+                   unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return (pciio_dmamap_t) DEV_FUNC(dev, dmamap_alloc)
+        (dev, dev_desc, byte_count_max, flags);
+}
+
+void
+snia_pciio_dmamap_free(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_free)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
+iopaddr_t
+snia_pciio_dmamap_addr(pciio_dmamap_t pciio_dmamap,  /* use these mapping resources */
+                  paddr_t paddr,        /* map for this address */
+                  size_t byte_count)
+{                                       /* map this many bytes */
+    return DMAMAP_FUNC(pciio_dmamap, dmamap_addr)
+        (CAST_DMAMAP(pciio_dmamap), paddr, byte_count);
+}
+
+void
+snia_pciio_dmamap_done(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_done)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
diff -urN linux-2.4.16/arch/ia64/sn/io/sgi_if.c lia64-2.4/arch/ia64/sn/io/sgi_if.c
--- linux-2.4.16/arch/ia64/sn/io/sgi_if.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/sgi_if.c	Mon Nov 19 23:22:52 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -22,7 +21,7 @@
 #include <asm/sn/slotnum.h>
 
 void *
-kmem_zalloc(size_t size, int flag)
+snia_kmem_zalloc(size_t size, int flag)
 {
         void *ptr = kmalloc(size, GFP_KERNEL);
         BZERO(ptr, size);
diff -urN linux-2.4.16/arch/ia64/sn/io/sgi_io_init.c lia64-2.4/arch/ia64/sn/io/sgi_io_init.c
--- linux-2.4.16/arch/ia64/sn/io/sgi_io_init.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/sgi_io_init.c	Mon Nov 19 23:22:52 2001
@@ -4,26 +4,24 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
+#include <asm/sn/pci/pciba.h>
 #include <linux/smp.h>
 
 extern void mlreset(int );
 extern int init_hcl(void);
 extern void klgraph_hack_init(void);
-extern void per_hub_init(cnodeid_t);
 extern void hubspc_init(void);
-extern void pciba_init(void);
 extern void pciio_init(void);
 extern void pcibr_init(void);
 extern void xtalk_init(void);
@@ -33,23 +31,21 @@
 extern void usrpci_init(void);
 extern void ioc3_init(void);
 extern void initialize_io(void);
-extern void init_platform_nodepda(nodepda_t *, cnodeid_t );
+#if defined(CONFIG_IA64_SGI_SN1)
 extern void intr_clear_all(nasid_t);
+#endif
 extern void klhwg_add_all_modules(devfs_handle_t);
 extern void klhwg_add_all_nodes(devfs_handle_t);
 
 void sn_mp_setup(void);
 extern devfs_handle_t hwgraph_root;
 extern void io_module_init(void);
-extern cnodeid_t nasid_to_compact_node[];
 extern void pci_bus_cvlink_init(void);
 extern void temp_hack(void);
-extern void init_platform_pda(cpuid_t cpu);
 
 extern int pci_bus_to_hcl_cvlink(void);
-extern synergy_da_t	*Synergy_da_indr[];
 
-#define DEBUG_IO_INIT
+/* #define DEBUG_IO_INIT */
 #ifdef DEBUG_IO_INIT
 #define DBG(x...) printk(x)
 #else
@@ -57,20 +53,73 @@
 #endif /* DEBUG_IO_INIT */
 
 /*
- * kern/ml/csu.s calls mlsetup
- *   mlsetup calls mlreset(master) - kern/os/startup.c
- *   j main
- *
- 
- * SN/slave.s start_slave_loop calls slave_entry
- * SN/slave.s slave_entry calls slave_loop
- * SN/slave.s slave_loop calls bootstrap
- * bootstrap in SN1/SN1asm.s calls cboot
- * cboot calls mlreset(slave) - ml/SN/mp.c
+ * per_hub_init
  *
- * sgi_io_infrastructure_init() gets called right before pci_init() 
- * in Linux mainline.  This routine actually mirrors the IO Infrastructure 
- * call sequence in IRIX, ofcourse, nicely modified for Linux.
+ * 	This code is executed once for each Hub chip.
+ */
+static void
+per_hub_init(cnodeid_t cnode)
+{
+	nasid_t		nasid;
+	nodepda_t	*npdap;
+	ii_icmr_u_t	ii_icmr;
+	ii_ibcr_u_t	ii_ibcr;
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	ASSERT(nasid != INVALID_NASID);
+	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
+
+	npdap = NODEPDA(cnode);
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* initialize per-node synergy perf instrumentation */
+	npdap->synergy_perf_enabled = 0; /* off by default */
+	npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
+	npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
+	npdap->synergy_inactive_intervals = 0;
+	npdap->synergy_active_intervals = 0;
+	npdap->synergy_perf_data = NULL;
+	npdap->synergy_perf_first = NULL;
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+	/*
+	 * Set the total number of CRBs that can be used.
+	 */
+	ii_icmr.ii_icmr_regval= 0x0;
+	ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
+	REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
+
+	/*
+	 * Set the number of CRBs that both of the BTEs combined
+	 * can use minus 1.
+	 */
+	ii_ibcr.ii_ibcr_regval= 0x0;
+	ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
+	REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
+
+	/*
+	 * Set CRB timeout to be 10ms.
+	 */
+	REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
+	REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* Reserve all of the hardwired interrupt levels. */
+	intr_reserve_hardwired(cnode);
+
+	/* Initialize error interrupts for this hub. */
+	hub_error_init(cnode);
+#endif
+}
+
+/*
+ * This routine is responsible for the setup of all the IRIX hwgraph style
+ * stuff that's been pulled into linux.  It's called by sn1_pci_find_bios which
+ * is called just before the generic Linux PCI layer does its probing (by 
+ * platform_pci_fixup aka sn1_pci_fixup).
  *
  * It is very IMPORTANT that this call is only made by the Master CPU!
  *
@@ -80,7 +129,6 @@
 sgi_master_io_infr_init(void)
 {
 	int cnode;
-	extern int maxnodes;
 
 	/*
 	 * Do any early init stuff .. einit_tbl[] etc.
@@ -117,7 +165,7 @@
 	sn_mp_setup();
 
 	DBG("--> sgi_master_io_infr_init: calling per_hub_init(0).\n");
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 		per_hub_init(cnode);
 	}
 
@@ -133,9 +181,6 @@
 	DBG("--> sgi_master_io_infr_init: calling hubspc_init()\n");
 	hubspc_init();
 
-	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
-	pciba_init();
-
 	DBG("--> sgi_master_io_infr_init: calling pciio_init()\n");
 	pciio_init();
 
@@ -172,6 +217,11 @@
 	DBG("--> sgi_master_io_infr_init: Setting up SGI IO Links for Linux PCI\n");
 	pci_bus_to_hcl_cvlink();
 
+#ifdef CONFIG_PCIBA
+	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
+	pciba_init();
+#endif
+
 	DBG("--> Leave sgi_master_io_infr_init: DONE setting up SGI Links for PCI\n");
 }
 
@@ -199,76 +249,15 @@
 sn_mp_setup(void)
 {
 	cnodeid_t	cnode;
-	extern int	maxnodes;
 	cpuid_t		cpu;
 
-	DBG("sn_mp_setup: Entered.\n");
-	/*
-	 * NODEPDA(x) Macro depends on nodepda
-	 * subnodepda is also statically set to calias space which we 
-	 * do not currently support yet .. just a hack for now.
-	 */
-#ifdef NUMA_BASE
-        maxnodes = numnodes;
-	DBG("sn_mp_setup(): maxnodes= %d  numnodes= %d\n", maxnodes,numnodes);
-        printk("sn_mp_setup(): Allocating backing store for *Nodepdaindr[%2d] \n",
-                maxnodes);
-
-        /*
-         * Initialize Nodpdaindr and per-node nodepdaindr array
-         */
-        *Nodepdaindr = (nodepda_t *) kmalloc(sizeof(nodepda_t *)*numnodes, GFP_KERNEL);
-        for (cnode=0; cnode<maxnodes; cnode++) {
-            Nodepdaindr[cnode] = (nodepda_t *) kmalloc(sizeof(struct nodepda_s),
-                                                                GFP_KERNEL);
-	    Synergy_da_indr[cnode * 2] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-	    Synergy_da_indr[(cnode * 2) + 1] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-            Nodepdaindr[cnode]->pernode_pdaindr = Nodepdaindr;
-            subnodepda = &Nodepdaindr[cnode]->snpda[cnode];
-        }
-        nodepda = Nodepdaindr[0];
-#else
-        Nodepdaindr = (nodepda_t *) kmalloc(sizeof(struct nodepda_s), GFP_KERNEL);
-        nodepda = Nodepdaindr[0];
-        subnodepda = &Nodepdaindr[0]->snpda[0];
-
-#endif /* NUMA_BASE */
-
-	/*
-	 * Before we let the other processors run, set up the platform specific
-	 * stuff in the nodepda.
-	 *
-	 * ???? maxnodes set in mlreset .. who sets it now ????
-	 * ???? cpu_node_probe() called in mlreset to set up the following:
-	 *      compact_to_nasid_node[] - cnode id gives nasid
-	 *      nasid_to_compact_node[] - nasid gives cnode id
-	 *
-	 *	do_cpumask() sets the following:
-	 *      cpuid_to_compact_node[] - cpuid gives cnode id
-	 *
-	 *      nasid comes from gdap->g_nasidtable[]
-	 *      ml/SN/promif.c
-	 */
-
-#ifdef CONFIG_IA64_SGI_SN1
 	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
 		/* Skip holes in CPU space */
 		if (cpu_enabled(cpu)) {
 			init_platform_pda(cpu);
 		}
 	}
-#endif
-	for (cnode = 0; cnode < maxnodes; cnode++) {
-		/*
-		 * Set up platform-dependent nodepda fields.
-		 * The following routine actually sets up the hubinfo struct
-		 * in nodepda.
-		 */
-		DBG("sn_mp_io_setup: calling init_platform_nodepda(%2d)\n",cnode);
-		init_platform_nodepda(Nodepdaindr[cnode], cnode);
-	}
+
 	/*
 	 * Initialize platform-dependent vertices in the hwgraph:
 	 *	module
@@ -290,24 +279,26 @@
 	klhwg_add_all_nodes(hwgraph_root);
 
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) {
 
 		/*
 		 * This routine clears the Hub's Interrupt registers.
 		 */
-#ifdef CONFIG_IA64_SGI_SN1
 		/*
 		 * We need to move this intr_clear_all() routine 
 		 * from SN/intr.c to a more appropriate file.
 		 * Talk to Al Mayer.
 		 */
+#if defined(CONFIG_IA64_SGI_SN1)
                 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
+#endif
 		/* now init the hub */
 	//	per_hub_init(cnode);
-#endif
+
 	}
 
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
+#if defined(CONFIG_IA64_SGI_SN1)
 	synergy_perf_init();
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
+#endif
+
 }
diff -urN linux-2.4.16/arch/ia64/sn/io/sgi_io_sim.c lia64-2.4/arch/ia64/sn/io/sgi_io_sim.c
--- linux-2.4.16/arch/ia64/sn/io/sgi_io_sim.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/sgi_io_sim.c	Mon Nov 19 23:22:52 2001
@@ -4,31 +4,28 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/module.h>
 #include <asm/sn/nic.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
 
 cpuid_t         master_procid = 0;
-int maxnodes;
 char arg_maxnodes[4];
 
-nodepda_t       *Nodepdaindr[MAX_COMPACT_NODES];
-nodepda_t        *nodepda;
-subnode_pda_t    *subnodepda;
-
-synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
-
 extern void init_all_devices(void);
 
+#if defined(CONFIG_IA64_SGI_SN1)
+synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
+#endif
 
 /*
  * Return non-zero if the given variable was specified
@@ -73,27 +70,23 @@
  * Routines provided by ml/SN/promif.c.
  */
 static __psunsigned_t master_bridge_base = (__psunsigned_t)NULL;
-nasid_t console_nasid;
+nasid_t console_nasid = (nasid_t)-1;
 static char console_wid;
 static char console_pcislot;
 
 void
 set_master_bridge_base(void)
 {
-
-        console_nasid = KL_CONFIG_CH_CONS_INFO(master_nasid)->nasid;
         console_wid = WIDGETID_GET(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
         console_pcislot = KL_CONFIG_CH_CONS_INFO(master_nasid)->npci;
-        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid,
-                                                            console_wid);
-	FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
+        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid, console_wid);
+	// FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
 }
 
 int
 check_nasid_equiv(nasid_t nasida, nasid_t nasidb)
 {
-        if ((nasida == nasidb) ||
-            (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
+        if ((nasida == nasidb) || (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
                 return 1;
         else
                 return 0;
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/hub_intr.c lia64-2.4/arch/ia64/sn/io/sn1/hub_intr.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/hub_intr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/hub_intr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,309 @@
+/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern xtalk_provider_t hub_provider;
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+}
+
+/*
+ * hub_device_desc_update
+ *	Update the passed in device descriptor with the actual the
+ * 	target cpu number and interrupt priority level.
+ *	NOTE : These might be the same as the ones passed in thru
+ *	the descriptor.
+ */
+static void
+hub_device_desc_update(device_desc_t 	dev_desc, 
+		       ilvl_t 		intr_swlevel,
+		       cpuid_t		cpu)
+{
+}
+
+int allocate_my_bit = INTRCONNECT_ANYBIT;
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
+		  device_desc_t dev_desc,	/* device descriptor */
+		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
+		  int uncond_nothread)		/* unconditionally non-threaded */
+{
+	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
+        int cpupicked = 0;
+	int bit;			/* interrupt vector */
+	/*REFERENCED*/
+	int intr_resflags = 0;
+	hub_intr_t intr_hdl;
+	cnodeid_t nodeid;		/* node to receive interrupt */
+	/*REFERENCED*/
+	nasid_t nasid;			/* nasid to receive interrupt */
+	struct xtalk_intr_s *xtalk_info;
+	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
+	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
+	char *intr_name = NULL;
+	ilvl_t intr_swlevel = (ilvl_t)0;
+	extern int default_intr_pri;
+	extern void synergy_intr_alloc(int, int);
+
+
+	if (dev_desc) {
+		if (dev_desc->flags & D_INTR_ISERR) {
+			intr_resflags = II_ERRORINT;
+		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
+			intr_resflags = II_THREADED;
+		} else {
+			/* Neither an error nor a thread. */
+			intr_resflags = 0;
+		}
+	} else {
+		intr_swlevel = default_intr_pri;
+		if (!uncond_nothread)
+			intr_resflags = II_THREADED;
+	}
+
+	/* XXX - Need to determine if the interrupt should be threaded. */
+
+	/* If the cpu has not been picked already then choose a candidate 
+	 * interrupt target and reserve the interrupt bit 
+	 */
+	if (!cpupicked) {
+		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
+				     intr_resflags,owner_dev,
+				     intr_name,&bit);
+	}
+
+	/* At this point we SHOULD have a valid cpu */
+	if (cpu == CPU_NONE) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+		printk(KERN_WARNING  "%v hub_intr_alloc could not allocate interrupt\n",
+			owner_dev);
+#else
+		printk(KERN_WARNING  "%p hub_intr_alloc could not allocate interrupt\n",
+			(void *)owner_dev);
+#endif
+		return(0);
+
+	}
+
+	/* If the cpu has been picked already (due to the bridge data 
+	 * corruption bug) then try to reserve an interrupt bit .
+	 */
+	if (cpupicked) {
+		bit = intr_reserve_level(cpu, allocate_my_bit, 
+					 intr_resflags, 
+					 owner_dev, intr_name);
+		if (bit < 0) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %v\n",
+				cpu,owner_dev);
+#else
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %p\n",
+				(int)cpu, (void *)owner_dev);
+#endif
+				
+			return(0);
+		}
+	}
+
+	nodeid = cpuid_to_cnodeid(cpu);
+	nasid = cpuid_to_nasid(cpu);
+	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
+
+	/*
+	 * Allocate an interrupt handle, and fill it in.  There are two
+	 * pieces to an interrupt handle: the piece needed by generic
+	 * xtalk code which is used by crosstalk device drivers, and
+	 * the piece needed by low-level IP27 hardware code.
+	 */
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
+	ASSERT_ALWAYS(intr_hdl);
+
+	/* 
+	 * Fill in xtalk information for generic xtalk interfaces that
+	 * operate on xtalk_intr_hdl's.
+	 */
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = bit;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	/*
+	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
+	 * widget always handles interrupts (and PIO and DMA) through its 
+	 * designated "master" crosstalk provider.
+	 */
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info)
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+
+	/* Fill in low level hub information for hub_* interrupt interface */
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = bit;
+	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
+
+	/* Store the actual interrupt priority level & interrupt target
+	 * cpu back in the device descriptor.
+	 */
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	synergy_intr_alloc((int)bit, (int)cpu);
+	return(intr_hdl);
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Uncondtionally request non-threaded, regardless of what the device
+ * descriptor might say.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+/*
+ * Free resources consumed by intr_alloc.
+ */
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_t xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		/* Setting the following fields in the xtalk interrupt info
+	 	 * clears the interrupt target register in the xtalk user
+	 	 */
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
+		kfree(intr_hdl);
+
+	intr_unreserve_level(cpu, bit);
+}
+
+
+/*
+ * Associate resources allocated with a previous hub_intr_alloc call with the
+ * described handler, arg, name, etc.
+ */
+/*ARGSUSED*/
+int
+hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
+			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
+			void *setfunc_arg)		/* arg to setfunc */
+{
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	extern int synergy_intr_connect(int, int);
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, NULL);
+	if (rv < 0)
+		return(rv);
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+	return(synergy_intr_connect((int)bit, (int)cpu));
+}
+
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/hubcounters.c lia64-2.4/arch/ia64/sn/io/sn1/hubcounters.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/hubcounters.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/hubcounters.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,283 @@
+/* $Id:$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <asm/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/router.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/clksupport.h>
+#include <asm/sn/sndrv.h>
+
+extern void hubni_error_handler(char *, int); /* huberror.c */
+
+static int hubstats_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+struct file_operations hub_mon_fops = {
+        ioctl:          hubstats_ioctl,
+};
+
+#define HUB_CAPTURE_TICKS	(2 * HZ)
+
+#define HUB_ERR_THRESH		500
+#define USEC_PER_SEC		1000000
+#define NSEC_PER_SEC		USEC_PER_SEC*1000
+
+volatile int hub_print_usecs = 600 * USEC_PER_SEC;
+
+/* Return success if the hub's crosstalk link is working */
+int
+hub_xtalk_link_up(nasid_t nasid)
+{
+	hubreg_t	llp_csr_reg;
+
+	/* Read the IO LLP control status register */
+	llp_csr_reg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);
+
+	/* Check if the xtalk link is working */
+	if (llp_csr_reg & IIO_LLP_CSR_IS_UP) 
+		return(1);
+
+	return(0);
+
+	
+}
+
+static char *error_flag_to_type(unsigned char error_flag)
+{
+    switch(error_flag) {
+    case 0x1: return ("NI retries");
+    case 0x2: return ("NI SN errors");
+    case 0x4: return ("NI CB errors");
+    case 0x8: return ("II CB errors");
+    case 0x10: return ("II SN errors");
+    default: return ("Errors");
+    }
+}
+
+int
+print_hub_error(hubstat_t *hsp, hubreg_t reg,
+		int64_t delta, unsigned char error_flag)
+{
+	int64_t rate;
+
+	reg *= hsp->hs_per_minute;	/* Convert to minutes */
+	rate = reg / delta;
+
+	if (rate > HUB_ERR_THRESH) {
+		
+		if(hsp->hs_maint & error_flag) 
+		{
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		else 
+		{
+		   hsp->hs_maint |= error_flag;
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+
+int
+check_hub_error_rates(hubstat_t *hsp)
+{
+	int64_t delta = hsp->hs_timestamp - hsp->hs_timebase;
+	int printed = 0;
+
+	printed += print_hub_error(hsp, hsp->hs_ni_retry_errors,
+				   delta, 0x1);
+
+#if 0
+	printed += print_hub_error(hsp, hsp->hs_ni_sn_errors,
+				   delta, 0x2);
+#endif
+
+	printed += print_hub_error(hsp, hsp->hs_ni_cb_errors,
+				   delta, 0x4);
+
+
+	/* If the hub's xtalk link is not working there is 
+	 * no need to print the "Excessive..." warning 
+	 * messages
+	 */
+	if (!hub_xtalk_link_up(hsp->hs_nasid))
+		return(printed);
+
+
+	printed += print_hub_error(hsp, hsp->hs_ii_cb_errors,
+				   delta, 0x8);
+
+	printed += print_hub_error(hsp, hsp->hs_ii_sn_errors,
+				   delta, 0x10);
+
+	return printed;
+}
+
+
+void
+capture_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	nasid_t nasid;
+	hubstat_t *hsp = &(npda->hubstats);
+	hubreg_t port_error;
+	ii_illr_u_t illr;
+	int count;
+	int overflow = 0;
+
+	/*
+	 * If our link wasn't up at boot time, don't worry about error rates.
+	 */
+	if (!(hsp->hs_ni_port_status & NPS_LINKUP_MASK)) {
+		printk("capture_hub_stats: cnode=%d hs_ni_port_status=0x%016lx : link is not up\n",
+		cnodeid, hsp->hs_ni_port_status);
+		return;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+
+	hsp->hs_timestamp = GET_RTC_COUNTER();
+
+	port_error = REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+	count = ((port_error & NPE_RETRYCOUNT_MASK) >> NPE_RETRYCOUNT_SHFT);
+	hsp->hs_ni_retry_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_SNERRCOUNT_MASK) >> NPE_SNERRCOUNT_SHFT);
+	hsp->hs_ni_sn_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_CBERRCOUNT_MASK) >> NPE_CBERRCOUNT_SHFT);
+	hsp->hs_ni_cb_errors += count;
+	if (overflow || count == NPE_COUNT_MAX)
+		hsp->hs_ni_overflows++;
+
+	if (port_error & NPE_FATAL_ERRORS) {
+#ifdef ajm
+		hubni_error_handler("capture_hub_stats", 1);
+#else
+		printk("Error: hubni_error_handler in capture_hub_stats");
+#endif
+	}
+
+	illr.ii_illr_regval = REMOTE_HUB_L(nasid, IIO_LLP_LOG);
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	hsp->hs_ii_sn_errors += illr.ii_illr_fld_s.i_sn_cnt;
+	hsp->hs_ii_cb_errors += illr.ii_illr_fld_s.i_cb_cnt;
+	if ((illr.ii_illr_fld_s.i_sn_cnt == IIO_LLP_SN_MAX) ||
+	    (illr.ii_illr_fld_s.i_cb_cnt == IIO_LLP_CB_MAX))
+		hsp->hs_ii_overflows++;
+
+	if (hsp->hs_print) {
+		if (check_hub_error_rates(hsp)) {
+			hsp->hs_last_print = GET_RTC_COUNTER();
+			hsp->hs_print = 0;
+		}
+	} else {
+		if ((GET_RTC_COUNTER() -
+		    hsp->hs_last_print) > hub_print_usecs)
+			hsp->hs_print = 1;
+	}
+		
+	npda->hubticks = HUB_CAPTURE_TICKS;
+}
+
+
+void
+init_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	hubstat_t *hsp = &(npda->hubstats);
+	nasid_t nasid = cnodeid_to_nasid(cnodeid);
+	bzero(&(npda->hubstats), sizeof(hubstat_t));
+
+	hsp->hs_version = HUBSTAT_VERSION;
+	hsp->hs_cnode = cnodeid;
+	hsp->hs_nasid = nasid;
+	hsp->hs_timebase = GET_RTC_COUNTER();
+	hsp->hs_ni_port_status = REMOTE_HUB_L(nasid, NI_PORT_STATUS);
+
+	/* Clear the II error counts. */
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	/* Clear the NI counts. */
+	REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+
+	hsp->hs_per_minute = (long long)RTC_CYCLES_PER_SEC * 60LL;
+
+	npda->hubticks = HUB_CAPTURE_TICKS;
+
+	/* XX should use kmem_alloc_node */
+	hsp->hs_name = (char *)kmalloc(MAX_HUB_PATH, GFP_KERNEL);
+	ASSERT_ALWAYS(hsp->hs_name);
+
+	sprintf(hsp->hs_name, "/dev/hw/" EDGE_LBL_MODULE "/%03d/"
+	        EDGE_LBL_NODE "/" EDGE_LBL_HUB,
+		npda->module_id);
+
+	hsp->hs_last_print = 0;
+	hsp->hs_print = 1;
+
+	hub_print_usecs = hub_print_usecs;
+
+#if 0
+	printk("init_hub_stats: cnode=%d nasid=%d hs_version=%d hs_ni_port_status=0x%016lx\n",
+		cnodeid, nasid, hsp->hs_version, hsp->hs_ni_port_status);
+#endif
+}
+
+static int
+hubstats_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+        cnodeid_t       cnode;
+        nodepda_t       *npdap;
+        uint64_t        longarg;
+        devfs_handle_t  d;
+
+        if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+                return -ENODEV;
+        cnode = (cnodeid_t)hwgraph_fastinfo_get(d);
+        npdap = NODEPDA(cnode);
+
+	if (npdap->hubstats.hs_version != HUBSTAT_VERSION) {
+		init_hub_stats(cnode, npdap);
+	}
+
+        switch (cmd) {
+	case SNDRV_GET_INFOSIZE:
+		longarg = sizeof(hubstat_t);
+		if (copy_to_user((void *)arg, &longarg, sizeof(longarg))) {
+		    return -EFAULT;
+		}
+		break;
+
+	case SNDRV_GET_HUBINFO:
+		/* refresh npda->hubstats */
+		capture_hub_stats(cnode, npdap);
+		if (copy_to_user((void *)arg, &npdap->hubstats, sizeof(hubstat_t))) {
+		    return -EFAULT;
+		}
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/huberror.c lia64-2.4/arch/ia64/sn/io/sn1/huberror.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/huberror.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/huberror.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,476 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+extern void hubni_eint_init(cnodeid_t cnode);
+extern void hubii_eint_init(cnodeid_t cnode);
+extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+extern int maxcpus;
+
+#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
+
+
+void
+hub_error_clear(nasid_t nasid)
+{
+	int i;
+	hubreg_t idsr;
+	int sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
+	}
+
+	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
+
+    /*
+     * Make sure spurious write response errors are cleared
+     * (values are from hub_set_prb())
+     */
+    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
+        iprb_t prb;
+
+	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
+
+        /* Clear out some fields */
+        prb.iprb_ovflow = 1;
+        prb.iprb_bnakctr = 0;
+        prb.iprb_anakctr = 0;
+
+	/*
+	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
+	 * frob the credit count properly, making the responses appear
+	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
+	 */
+        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
+
+        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
+
+        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
+    }
+
+    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
+    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
+    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
+
+    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
+
+    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
+    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
+
+    /* Clear XB error regs, in order */
+    for (i = 0;
+         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
+         i += sizeof(hubreg_t)) {
+        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
+    }
+}
+
+
+/*
+ * Function	: hub_error_init
+ * Purpose	: initialize the error handling requirements for a given hub.
+ * Parameters	: cnode, the compact nodeid.
+ * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
+ *			remote cpu, when this hub is headless.(cpuless)
+ * Returns	: None
+ */
+
+void
+hub_error_init(cnodeid_t cnode)
+{
+	nasid_t nasid;
+
+    nasid = cnodeid_to_nasid(cnode);
+    hub_error_clear(nasid);
+
+#ifdef ajm
+    if (cnode == 0) {
+	/*
+	 * Allocate log for storing the node specific error info
+	 */
+	for (i = 0; i < num_compact_nodes; i++) {
+	    kl_error_log[i]  = kmem_zalloc_node(sizeof(sn0_error_log_t), 
+						KM_NOSLEEP, i);
+	    hub_err_count[i] = kmem_zalloc_node(sizeof(hub_errcnt_t),
+						VM_DIRECT | KM_NOSLEEP, i);
+	    ASSERT_ALWAYS(kl_error_log[i] && hub_err_count[i]);
+	}
+    }
+
+    /*
+     * Assumption: There will be only one cpu who will initialize
+     * a hub. we need to setup the ii and each pi error interrupts.
+     * The SN1 hub (bedrock) has two PI, one for up to two processors.
+     */
+
+    if (cpuid_to_cnodeid(smp_processor_id()) == cnode) { 
+	int generic_intr_mask = PI_ERR_GENERIC; /* These interrupts are sent to only 1 CPU per NODE */
+
+	ASSERT_ALWAYS(kl_error_log[cnode]);
+	ASSERT_ALWAYS(hub_err_count[cnode]);
+	MD_ERR_LOG_INIT(kl_error_log[cnode]);
+
+	/* One for each CPU */
+	recover_error_init(RECOVER_ERROR_TABLE(cnode, 0));
+	recover_error_init(RECOVER_ERROR_TABLE(cnode, 1));
+	recover_error_init(RECOVER_ERROR_TABLE(cnode, 2));
+	recover_error_init(RECOVER_ERROR_TABLE(cnode, 3));
+
+	/*
+	 * Setup error intr masks.
+	 */
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		int cpuA_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_A);
+		int cpuB_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_B);
+
+		if (cpuA_present) {
+			if (cpuB_present) {		/* A && B */
+	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
+					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_A|generic_intr_mask));
+	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
+					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_B));
+
+			} else {			/* A && !B */
+	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
+					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_A|generic_intr_mask));
+			}
+			generic_intr_mask = 0;
+		} else {
+			if (cpuB_present) {		/* !A && B */
+	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
+					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_B|generic_intr_mask));
+				generic_intr_mask = 0;
+
+			} else {			/* !A && !B */
+				/* nothing to set up */
+			}
+		}
+	}
+
+	/*
+	 * Turn off UNCAC_UNCORR interrupt in the masks. Anyone interested
+	 * in these errors will peek at the int pend register to see if its
+	 * set.
+	 */ 
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_A);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, (misc & ~PI_ERR_UNCAC_UNCORR_A));
+		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_B);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, (misc & ~PI_ERR_UNCAC_UNCORR_B));
+	}
+
+	/*
+	 * enable all error indicators to turn on, in case of errors.
+	 *
+	 * This is not good on single cpu node boards.
+	 **** LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
+	 */
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_A_CLR, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_B_CLR, 0);
+	}
+
+	/* Set up stack for each present processor */
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_A)) {
+	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[0] =
+			SN0_ERROR_LOG(cnode)->el_spool_last_addr[0] =
+		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
+		}
+	    
+		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
+	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
+			SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
+		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
+		}
+	}
+
+
+	PI_SPOOL_SIZE_BYTES = 
+	    ERR_STACK_SIZE_BYTES(REMOTE_HUB_L(nasid, PI_ERR_STACK_SIZE));
+
+#ifdef BRINGUP
+/* BRINGUP: The following code looks like a check to make sure
+the prom set up the error spool correctly for 2 processors.  I
+don't think it is needed.  */
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
+			__psunsigned_t addr_a = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
+			__psunsigned_t addr_b = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
+			if ((addr_a & ~0xff) == (addr_b & ~0xff)) {
+			    REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STACK_ADDR_B, 	
+					addr_b + PI_SPOOL_SIZE_BYTES);
+	
+			    SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
+				SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
+				    REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
+	
+		    }
+		}
+	}
+#endif /* BRINGUP */
+
+	/* programming our own hub. Enable error_int_pend intr.
+	 * If both present, CPU A takes CPU b's error interrupts and any
+	 * generic ones. CPU B takes CPU A error ints.
+	 */
+	if (cause_intr_connect (SRB_ERR_IDX,
+				(intr_func_t)(hubpi_eint_handler),
+				SR_ALL_MASK|SR_IE)) {
+	    cmn_err(ERR_WARN, 
+		    "hub_error_init: cause_intr_connect failed on %d", cnode);
+	}
+    }
+    else {
+	/* programming remote hub. The only valid reason that this
+	 * is called will be on headless hubs. No interrupts 
+	 */
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, 0); /* not necessary */
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, 0); /* not necessary */
+	}
+    }
+#endif /* ajm */
+    /*
+     * Now setup the hub ii and ni error interrupt handler.
+     */
+
+    hubii_eint_init(cnode);
+    hubni_eint_init(cnode);
+
+#ifdef ajm
+    /*** XXX FIXME XXX resolve the following***/
+    /* INT_PEND1 bits set up for one hub only:
+     *	SHUTDOWN_INTR
+     *	MD_COR_ERR_INTR
+     *  COR_ERR_INTR_A and COR_ERR_INTR_B should be sent to the
+     *  appropriate CPU only.
+     */
+
+    if (cnode == 0) {
+	    error_consistency_check.eps_state = 0;
+	    error_consistency_check.eps_cpuid = -1;
+	    spinlock_init(&error_consistency_check.eps_lock, "error_dump_lock");
+    }
+#endif
+
+    return;
+}
+
+/*
+ * Function	: hubii_eint_init
+ * Parameters	: cnode
+ * Purpose	: to initialize the hub iio error interrupt.
+ * Assumptions	: Called once per hub, by the cpu which will ultimately
+ *			handle this interrupt.
+ * Returns	: None.
+ */
+
+
+void
+hubii_eint_init(cnodeid_t cnode)
+{
+    int			bit, rv;
+    ii_iidsr_u_t    	hubio_eint;
+    hubinfo_t		hinfo; 
+    cpuid_t		intr_cpu;
+    devfs_handle_t 	hub_v;
+    ii_ilcsr_u_t	ilcsr;
+    int bit_pos_to_irq(int bit);
+    int synergy_intr_connect(int bit, int cpuid);
+
+
+    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
+    ASSERT_ALWAYS(hub_v);
+    hubinfo_get(hub_v, &hinfo);
+
+    ASSERT(hinfo);
+    ASSERT(hinfo->h_cnodeid == cnode);
+
+    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
+
+    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
+	/* 
+	 * HUB II link is not up. 
+	 * Just disable LLP, and don't connect any interrupts.
+	 */
+	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
+	return;
+    }
+    /* Select a possible interrupt target where there is a free interrupt
+     * bit and also reserve the interrupt bit for this IO error interrupt
+     */
+    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
+			      "HUB IO error interrupt",&bit);
+    if (intr_cpu == CPU_NONE) {
+	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
+	return;
+    }
+	
+    rv = intr_connect_level(intr_cpu, bit, 0, NULL);
+    synergy_intr_connect(bit, intr_cpu);
+    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, NULL, (void *)hub_v);
+    ASSERT_ALWAYS(rv >= 0);
+    hubio_eint.ii_iidsr_regval = 0;
+    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
+    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
+    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
+    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
+
+}
+
+void
+hubni_eint_init(cnodeid_t cnode)
+{
+    int intr_bit;
+    cpuid_t targ;
+
+
+    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
+	return;
+
+	/* The prom chooses which cpu gets these interrupts, but we
+	*  don't know which one it chose.  We will register all of the 
+	*  cpus to be sure.  This only costs us an irqaction per cpu.
+	*/
+    for (; targ < CPUS_PER_NODE; targ++) {
+	if (!cpu_enabled(targ) ) continue;
+	/* connect the INTEND1 bits. */
+	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
+		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL);
+	}
+	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, NULL, NULL);
+	/* synergy masks are initialized in the prom to enable all interrupts. */
+	/* We'll just leave them that way, here, for these interrupts. */
+    }
+}
+
+
+/*ARGSUSED*/
+void
+hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
+{
+#ifdef ajm
+    devfs_handle_t	hub_v;
+    hubinfo_t		hinfo; 
+    ii_wstat_u_t	wstat;
+    hubreg_t		idsr;
+#endif
+
+	panic("Hubii interrupt\n");
+#ifdef ajm
+    /*
+     * If the NI has a problem, everyone has a problem.  We shouldn't
+     * even attempt to handle other errors when an NI error is present.
+     */
+    if (check_ni_errors()) {
+	hubni_error_handler("II interrupt", 1);
+	/* NOTREACHED */
+    }
+
+    /* two levels of casting avoids compiler warning.!! */
+    hub_v = (devfs_handle_t)(long)(arg); 
+    ASSERT(hub_v);
+
+    hubinfo_get(hub_v, &hinfo);
+    
+    /* 
+     * Identify the reason for error. 
+     */
+    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
+
+    if (wstat.ii_wstat_fld_s.w_crazy) {
+	char	*reason;
+	/*
+	 * We can do a couple of things here. 
+	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
+	 * which of these caused the CRAZY bit to be set. 
+	 * You may be able to check if the Link is up really.
+	 */
+	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
+		reason = "Micro Packet Retry Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
+		reason = "Crosstalk Tail Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
+		reason = "Crosstalk Credit Timeout";
+	else {
+		hubreg_t	hubii_imem;
+		/*
+		 * Check if widget 0 has been marked as shutdown, or
+		 * if BTE 0/1 has been marked.
+		 */
+		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
+		if (hubii_imem & IIO_IMEM_W0ESD)
+			reason = "Hub Widget 0 has been Shutdown";
+		else if (hubii_imem & IIO_IMEM_B0ESD)
+			reason = "BTE 0 has been shutdown";
+		else if (hubii_imem & IIO_IMEM_B1ESD)
+			reason = "BTE 1 has been shutdown";
+		else	reason = "Unknown";
+	
+	}
+	/*
+	 * Note: we may never be able to print this, if the II talking
+	 * to Xbow which hosts the console is dead. 
+	 */
+	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
+		hinfo->h_cnodeid, reason);
+    }
+
+    /* 
+     * It's a toss as to which one among PRB/CRB to check first. 
+     * Current decision is based on the severity of the errors. 
+     * IO CRB errors tend to be more severe than PRB errors.
+     *
+     * It is possible for BTE errors to have been handled already, so we
+     * may not see any errors handled here. 
+     */
+    (void)hubiio_crb_error_handler(hub_v, hinfo);
+    (void)hubiio_prb_error_handler(hub_v, hinfo);
+    /*
+     * If we reach here, it indicates crb/prb handlers successfully
+     * handled the error. So, re-enable II to send more interrupt
+     * and return.
+     */
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
+    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
+#endif /* ajm */
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/ip37.c lia64-2.4/arch/ia64/sn/io/sn1/ip37.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/ip37.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/ip37.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,67 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * ip37.c
+ *	Support for IP35/IP37 machines
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/pci/bridge.h>     /* for bridge_t */
+
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+	hubii_wcr_t	ii_wcr;	/* the control status register */
+		
+	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+
+	return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+int
+is_fine_dirmode(void)
+{
+	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
+		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
+
+}
+
+
+#ifdef SN1_USE_POISON_BITS
+int
+hub_bte_poison_ok(void)
+{
+	/*
+	 * For now, assume poisoning is ok. If it turns out there are chip
+	 * bugs that prevent its use in early revs, there is some neat code
+	 * to steal from the IP27 equivalent of this code.
+	 */
+
+#ifdef BRINGUP	/* temp disable BTE poisoning - might be sw bugs in this area */
+	return 0;
+#else
+	return 1;
+#endif
+}
+#endif /* SN1_USE_POISON_BITS */
+                
+
+void
+ni_reset_port(void)
+{
+	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
+	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/mem_refcnt.c lia64-2.4/arch/ia64/sn/io/sn1/mem_refcnt.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/mem_refcnt.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/mem_refcnt.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,221 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn1/mem_refcnt.h>
+#include <asm/sn/sn1/hwcntrs.h>
+#include <asm/sn/sn1/hubspc.h>
+// From numa_hw.h
+
+#define MIGR_COUNTER_MAX_GET(nodeid) \
+        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
+/*
+ * Get the Absolute Theshold
+ */
+#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
+        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
+/*
+ * Get the current Differential Threshold
+ */
+#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
+        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
+
+#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
+
+// #include "migr_control.h"
+
+int
+mem_refcnt_attach(devfs_handle_t hub)
+{
+#ifndef CONFIG_IA64_SGI_SN
+        devfs_handle_t refcnt_dev;
+        
+        hwgraph_char_device_add(hub,
+                                "refcnt",
+                                "hubspc_", 
+				&refcnt_dev);
+        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
+#endif
+
+        return (0);
+}
+
+
+/*ARGSUSED*/
+int
+mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
+{
+        cnodeid_t node;
+
+        node = master_node_get(*devp);
+
+        ASSERT( (node >= 0) && (node < num_compact_nodes) );
+
+        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
+                return (ENODEV);
+        }
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
+
+        return (0);
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+        return 0;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+        cnodeid_t node;
+        int errcode;
+        char* buffer;
+        size_t blen;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < num_compact_nodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        /*
+         * XXXX deal with prot's somewhere around here....
+         */
+
+        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
+        blen = NODEPDA(node)->migr_refcnt_cbsize;
+
+        /*
+         * Force offset to be a multiple of sizeof(refcnt_t)
+         * We round up.
+         */
+
+        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
+
+        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
+                return (EPERM);
+        }
+
+        errcode = v_mapphys(vt,
+                            buffer + off,
+                            len);
+
+        return errcode;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+        return 0;
+}
+
+/* ARGSUSED */
+int
+mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp)
+{
+        cnodeid_t node;
+        int errcode;
+	extern int num_compact_nodes;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < num_compact_nodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        errcode = 0;
+        
+        switch (cmd) {
+        case RCB_INFO_GET:
+        {
+                rcb_info_t rcb;
+                
+                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
+                
+                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
+                rcb.rcb_sw_counters_per_set = num_compact_nodes;
+                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
+
+                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
+                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
+                rcb.rcb_base_page_size = NBPP;
+                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
+                
+                rcb.rcb_cnodeid = node;
+                rcb.rcb_granularity = MD_PAGE_SIZE;
+#ifdef LATER
+                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
+                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
+#endif
+                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
+                rcb.rcb_num_slots = MAX_MEM_SLOTS;
+
+                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
+                        errcode = EFAULT;
+                }
+
+                break;
+        }
+        case RCB_SLOT_GET:
+        {
+                rcb_slot_t slot[MAX_MEM_SLOTS];
+                int s;
+                int nslots;
+
+                nslots = MAX_MEM_SLOTS;
+                ASSERT(nslots <= MAX_MEM_SLOTS);
+                for (s = 0; s < nslots; s++) {
+                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
+#ifdef LATER
+                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
+#else
+                        slot[s].size  = (uint64_t)1;
+#endif
+                }
+                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
+                        errcode = EFAULT;
+                }
+                
+                *rvalp = nslots;
+                break;
+        }
+                
+        default:
+                errcode = EINVAL;
+                break;
+
+        }
+        
+        return errcode;
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/ml_SN_intr.c lia64-2.4/arch/ia64/sn/io/sn1/ml_SN_intr.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/ml_SN_intr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/ml_SN_intr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,1548 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IP27 board.
+ */
+
+#ident  "$Revision: 1.167 $"
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+
+#if DEBUG_INTR_TSTAMP_DEBUG
+#include <sys/debug.h>
+#include <sys/idbg.h>
+#include <sys/inst.h>
+void do_splx_log(int, int);
+void spldebug_log_event(int);
+#endif
+
+// FIXME - BRINGUP
+#ifdef CONFIG_SMP
+extern unsigned long cpu_online_map;
+#endif
+#define cpu_allows_intr(cpu)	(1)
+// If I understand what's going on with this, 32 should work.
+// physmem_maxradius seems to be the maximum number of router
+// hops to get from one end of the system to the other.  With
+// a maximally configured machine, with the dumbest possible
+// topology, we would make 32 router hops.  For what we're using
+// it for, the dumbest possible should suffice.
+#define physmem_maxradius()	32
+
+#define SUBNODE_ANY -1
+
+extern int	nmied;
+extern int	hub_intr_wakeup_cnt;
+extern synergy_da_t	*Synergy_da_indr[];
+extern cpuid_t         master_procid;
+
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+
+#define INTR_LOCK(vecblk) \
+     (s = mutex_spinlock(&(vecblk)->vector_lock))
+#define INTR_UNLOCK(vecblk) \
+      mutex_spinunlock(&(vecblk)->vector_lock, s)
+
+/*
+ * REACT/Pro
+ */
+
+
+
+/* 
+ * Find first bit set 
+ * Used outside this file also 
+ */
+int ms1bit(unsigned long x)
+{
+    int			b;
+
+    if (x >> 32)	b  = 32, x >>= 32;
+    else		b  =  0;
+    if (x >> 16)	b += 16, x >>= 16;
+    if (x >>  8)	b +=  8, x >>=  8;
+    if (x >>  4)	b +=  4, x >>=  4;
+    if (x >>  2)	b +=  2, x >>=  2;
+
+    return b + (int) (x >> 1);
+}
+
+/* ARGSUSED */
+void
+intr_stray(void *lvl)
+{
+    printk(KERN_WARNING  "Stray Interrupt - level %ld to cpu %d", (long)lvl, smp_processor_id());
+}
+
+#if defined(DEBUG)
+
+/* Infrastructure  to gather the device - target cpu mapping info */
+#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
+				 * the exact maximum # devices possible.
+				 */
+#define MAX_NAME	100	
+typedef struct {
+	dev_t		dev;	/* device */
+	cpuid_t		cpuid;	/* target cpu */
+	cnodeid_t	cnodeid;/* node on which the target cpu is present */
+	int		bit;	/* intr bit reserved */
+	char		intr_name[MAX_NAME]; /* name of the interrupt */
+} intr_dev_targ_map_t;
+
+intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
+uint64_t		intr_dev_targ_map_size;
+spinlock_t		intr_dev_targ_map_lock;
+
+/* Print out the device - target cpu mapping.
+ * This routine is used only in the idbg command
+ * "intrmap" 
+ */
+void
+intr_dev_targ_map_print(cnodeid_t cnodeid)
+{
+	int  i,j,size = 0;
+	int  print_flag = 0,verbose = 0;	
+	char node_name[10];
+	
+	if (cnodeid != CNODEID_NONE) {
+		nodepda_t 	*npda;
+
+		npda = NODEPDA(cnodeid);
+		for (j=0; j<NUM_SUBNODES; j++) {
+			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
+			qprintf("\n INT_PEND1: ");
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
+		}
+		verbose = 1;
+	}
+	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
+		(verbose ? "All" : "Non-hardwired"),
+		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
+		
+	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
+	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
+
+		print_flag = 0;
+		if (verbose) {
+			if (cnodeid != CNODEID_NONE) {
+				if (cnodeid == intr_dev_targ_map[i].cnodeid)
+					print_flag = 1;
+			} else {
+				print_flag = 1;
+			}
+		} else {
+			if (intr_dev_targ_map[i].dev != 0) {
+				if (cnodeid != CNODEID_NONE) {
+					if (cnodeid == 
+					    intr_dev_targ_map[i].cnodeid)
+						print_flag = 1;
+				} else {
+					print_flag = 1;
+				}
+			}
+		}
+		if (print_flag) {
+			size++;
+			qprintf("%d\t%d\t%d\t%d\t%s\n",
+				intr_dev_targ_map[i].dev,
+				intr_dev_targ_map[i].cpuid,
+				intr_dev_targ_map[i].cnodeid,
+				intr_dev_targ_map[i].bit,
+				intr_dev_targ_map[i].intr_name);
+		}
+
+	}
+	qprintf("\nTotal : %d\n",size);
+}
+#endif /* DEBUG */
+
+/*
+ * The spinlocks have already been initialized.  Now initialize the interrupt
+ * vectors.  One processor on each hub does the work.
+ */
+void
+intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
+{
+    int			i, ip=0;
+    intr_vecblk_t	*vecblk;
+    subnode_pda_t	*snpda;
+
+
+    snpda = SNPDA(npda,sn);
+    do {
+	if (ip == 0) {
+	    vecblk = &snpda->intr_dispatch0;
+	} else {
+	    vecblk = &snpda->intr_dispatch1;
+	}
+
+	/* Initialize this vector. */
+	for (i = 0; i < N_INTPEND_BITS; i++) {
+		vecblk->vectors[i].iv_func = intr_stray;
+		vecblk->vectors[i].iv_prefunc = NULL;
+		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
+
+		vecblk->info[i].ii_owner_dev = 0;
+		strcpy(vecblk->info[i].ii_name, "Unused");
+		vecblk->info[i].ii_flags = 0;	/* No flags */
+		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
+
+	    }
+
+	mutex_spinlock_init(&vecblk->vector_lock);
+
+	vecblk->vector_count = 0;    
+	for (i = 0; i < CPUS_PER_SUBNODE; i++)
+		vecblk->cpu_count[i] = 0;
+
+	vecblk->vector_state = VECTOR_UNINITED;
+
+    } while (++ip < 2);
+
+}
+
+
+/*
+ * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+ *					devfs_handle_t owner_dev, char *name)
+ *	Internal work routine to reserve or unreserve an interrupt level.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to reserve.  -1 means any level
+ *		resflags should include II_ERRORINT if this is an
+ *			error interrupt, II_THREADED if the interrupt handler
+ *			will be threaded, or 0 otherwise.
+ *		reserve should be set to II_RESERVE or II_UNRESERVE
+ *			to get or clear a reservation.
+ *		owner_dev is the device that "owns" this interrupt, if supplied
+ *		name is a human-readable name for this interrupt, if supplied
+ *	intr_reserve_level returns the bit reserved or -1 to indicate an error
+ */
+static int
+do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+					devfs_handle_t owner_dev, char *name)
+{
+    intr_vecblk_t	*vecblk;
+    hub_intmasks_t 	*hub_intmasks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+    synergy_da_t	*sda;
+    int		which_synergy;
+    cnodeid_t	cnode;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    cnode = cpuid_to_cnodeid(cpu);
+    which_synergy = cpuid_to_synergy(cpu);
+    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+    hub_intmasks = &sda->s_intmasks;
+    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+    // if (pdaindr[cpu].pda == NULL) return -1;
+    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
+	vecblk = hub_intmasks->dispatch0;
+	ip = 0;
+    } else {
+	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
+	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
+	vecblk = hub_intmasks->dispatch1;
+	ip = 1;
+    }
+
+    INTR_LOCK(vecblk);
+
+    if (bit <= -1) {
+	bit = 0;
+	ASSERT(reserve == II_RESERVE);
+	/* Choose any available level */
+	for (; bit < N_INTPEND_BITS; bit++) {
+	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
+		rv = bit;
+		break;
+	    }
+	}
+
+	/* Return -1 if all interrupt levels int this register are taken. */
+	if (bit == N_INTPEND_BITS)
+	    rv = -1;
+
+    } else {
+	/* Reserve a particular level if it's available. */
+	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
+	    /* Can't (un)reserve a level that's already (un)reserved. */
+	    rv = -1;
+	} else {
+	    rv = bit;
+	}
+    }
+
+    /* Reserve the level and bump the count. */
+    if (rv != -1) {
+	if (reserve) {
+	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
+	    int namelen;
+	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
+	    vecblk->info[bit].ii_owner_dev = owner_dev;
+	    /* Copy in the name. */
+	    namelen = name ? strlen(name) : 0;
+	    strncpy(vecblk->info[bit].ii_name, name, min(namelen, maxlen)); 
+	    vecblk->info[bit].ii_name[maxlen] = '\0';
+	    vecblk->vector_count++;
+	} else {
+	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
+	    vecblk->info[bit].ii_owner_dev = 0;
+	    /* Clear the name. */
+	    vecblk->info[bit].ii_name[0] = '\0';
+	    vecblk->vector_count--;
+	}
+    }
+
+    INTR_UNLOCK(vecblk);
+
+#if defined(DEBUG)
+    if (rv >= 0) {
+	    int namelen = name ? strlen(name) : 0;
+	    /* Gather this device - target cpu mapping information
+	     * in a table which can be used later by the idbg "intrmap"
+	     * command
+	     */
+	    s = mutex_spinlock(&intr_dev_targ_map_lock);
+	    if (intr_dev_targ_map_size < MAX_DEVICES) {
+		    intr_dev_targ_map_t	*p;
+
+		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
+		    p->dev  	= owner_dev;
+		    p->cpuid 	= cpu; 
+		    p->cnodeid 	= cpuid_to_cnodeid(cpu); 
+		    p->bit 	= ip * N_INTPEND_BITS + rv;
+		    strncpy(p->intr_name,
+			    name,
+			    min(MAX_NAME,namelen));
+		    intr_dev_targ_map_size++;
+	    }
+	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
+    }
+#endif /* DEBUG */
+
+    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Reserve an interrupt level.
+ */
+int
+intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Unreserve an interrupt level.
+ */
+void
+intr_unreserve_level(cpuid_t cpu, int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
+}
+
+/*
+ * Get values that vary depending on which CPU and bit we're operating on
+ */
+static hub_intmasks_t *
+intr_get_ptrs(cpuid_t cpu, int bit,
+	      int *new_bit,		/* Bit relative to the register */
+	      hubreg_t **intpend_masks, /* Masks for this register */
+	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
+	      int *ip)			/* Which intpend register */
+{
+	hub_intmasks_t *hub_intmasks;
+	synergy_da_t	*sda;
+	int		which_synergy;
+	cnodeid_t	cnode;
+
+	ASSERT(bit < N_INTPEND_BITS * 2);
+
+	cnode = cpuid_to_cnodeid(cpu);
+	which_synergy = cpuid_to_synergy(cpu);
+	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+	hub_intmasks = &sda->s_intmasks;
+
+	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+	if (bit < N_INTPEND_BITS) {
+		*intpend_masks = hub_intmasks->intpend0_masks;
+		*vecblk = hub_intmasks->dispatch0;
+		*ip = 0;
+		*new_bit = bit;
+	} else {
+		*intpend_masks = hub_intmasks->intpend1_masks;
+		*vecblk = hub_intmasks->dispatch1;
+		*ip = 1;
+		*new_bit = bit - N_INTPEND_BITS;
+	}
+
+	return hub_intmasks;
+}
+
+
+/*
+ * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
+ *		intr_func_t intr_func, void *intr_arg);
+ *	This is the lowest-level interface to the interrupt code.  It shouldn't
+ *	be called from outside the ml/SN directory.
+ *	intr_connect_level hooks up an interrupt to a particular bit in
+ *	the INT_PEND0/1 masks.  Returns 0 on success.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to connect to
+ *		intr_swlevel tells which software level to use
+ *		intr_func is the interrupt handler
+ *		intr_arg is an arbitrary argument interpreted by the handler
+ *		intr_prefunc is a prologue function, to be called
+ *			with interrupts disabled, to disable
+ *			the interrupt at source.  It is called
+ *			with the same argument.  Should be NULL for
+ *			typical interrupts, which can be masked
+ *			by the infrastructure at the level bit.
+ *	intr_connect_level returns 0 on success or nonzero on an error
+ */
+/* ARGSUSED */
+int
+intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, intr_func_t intr_prefunc)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    int rv = 0;
+    int ip;
+    unsigned long s;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
+	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
+	/* Can't assign to a level that's in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
+	vecblk->info[bit].ii_flags |= II_INUSE;
+    }
+
+    /* Now stuff the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu));
+	nasid_t nasid = cpuid_to_nasid(cpu);
+	int	subnode = cpuid_to_subnode(cpu);
+
+	/* Make sure it's not already pending when we connect it. */
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
+
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+	}
+
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]++;
+#if SN1
+	/*
+	 * On SN1, there are 8 interrupt mask registers per node:
+	 * 	PI_0 MASK_0 A
+	 * 	PI_0 MASK_1 A
+	 * 	PI_0 MASK_0 B
+	 * 	PI_0 MASK_1 B
+	 * 	PI_1 MASK_0 A
+	 * 	PI_1 MASK_1 A
+	 * 	PI_1 MASK_0 B
+	 * 	PI_1 MASK_1 B
+	 */
+#endif
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
+		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
+			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+
+/*
+ * intr_disconnect_level(cpuid_t cpu, int bit)
+ *
+ *	This is the lowest-level interface to the interrupt code.  It should
+ *	not be called from outside the ml/SN directory.
+ *	intr_disconnect_level removes a particular bit from an interrupt in
+ * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
+ */
+int
+intr_disconnect_level(cpuid_t cpu, int bit)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
+	((II_RESERVE | II_INUSE))) {
+	/* Can't remove a level that's not in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_arg = 0;
+	vecblk->info[bit].ii_flags &= ~II_INUSE;
+#ifdef BASE_ITHRTEAD
+	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
+#endif
+    }
+
+    /* Now clear the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+
+	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]--;
+	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+				   cpuid_to_subnode(cpu),
+				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
+	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
+					(PI_INT_MASK_OFFSET * lslice));
+	*mask_reg = intpend_masks[0];
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+/*
+ * Actually block or unblock an interrupt
+ */
+void
+do_intr_block_bit(cpuid_t cpu, int bit, int block)
+{
+	intr_vecblk_t *vecblk;
+	int ip;
+	unsigned long s;
+	hubreg_t *intpend_masks;
+	volatile hubreg_t mask_value;
+	volatile hubreg_t *mask_reg;
+
+	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
+
+	INTR_LOCK(vecblk);
+
+	if (block)
+		/* Block */
+		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	else
+		/* Unblock */
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+
+	/*
+	 * Wait for it to take effect.  (One read should suffice.)
+	 * This is only necessary when blocking an interrupt
+	 */
+	if (block)
+		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
+			;
+
+	INTR_UNLOCK(vecblk);
+}
+
+
+/*
+ * Block a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_block_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 1);
+}
+
+
+/*
+ * Unblock a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_unblock_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 0);
+}
+
+
+/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
+#define cpu_on_subnode(cpuid, which_subnode) \
+	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
+
+
+/*
+ * Choose one of the CPUs on a specified node or subnode to receive
+ * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
+ *
+ * Among all acceptable CPUs, the CPU that has the fewest total number
+ * of interrupts targetted towards it is chosen.  Note that we never
+ * consider how frequent each of these interrupts might occur, so a rare
+ * hardware error interrupt is weighted equally with a disk interrupt.
+ */
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
+{
+	cpuid_t 	cpu, best_cpu = CPU_NONE;
+	int		slice, min_count=1000;
+
+	min_count = 1000;
+	for (slice=0; slice < CPUS_PER_NODE; slice++) {
+		intr_vecblk_t 	*vecblk0, *vecblk1;
+		int total_intrs_to_slice;
+		subnode_pda_t *snpda;
+		int local_cpu_num;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE)
+			continue;
+
+		/* If this cpu isn't enabled for interrupts, skip it */
+		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
+			continue;
+
+		/* If this isn't the right subnode, skip it */
+		if (!cpu_on_subnode(cpu, which_subnode))
+			continue;
+
+		/* OK, this one's a potential CPU for interrupts */
+		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
+		vecblk0 = &snpda->intr_dispatch0;
+		vecblk1 = &snpda->intr_dispatch1;
+		local_cpu_num = LOCALCPU(slice);
+		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
+		              vecblk1->cpu_count[local_cpu_num];
+
+		if (min_count > total_intrs_to_slice) {
+			min_count = total_intrs_to_slice;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+/*
+ * Choose an appropriate interrupt target CPU on a specified node.
+ * If which_subnode is SUBNODE_ANY, then subnode is not considered.
+ * Otherwise, the chosen CPU must be on the specified subnode.
+ */
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
+{
+	return(do_intr_cpu_choose(cnode, which_subnode));
+}
+
+
+/* Make it easy to identify subnode vertices in the hwgraph */
+void
+mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
+{
+	graph_error_t rv;
+
+	ASSERT(0 <= which_subnode);
+	ASSERT(which_subnode < NUM_SUBNODES);
+
+	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+
+	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ * Given a device descriptor, extract interrupt target information and
+ * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
+ * out of the target information.
+ * TBD: Should this be considered platform-independent code?
+ */
+
+
+/*
+ * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
+ *		owner_dev,intr_name,*resp_bit)
+ *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
+ * 	not both.
+ * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
+ * 	interrupt target candidate.
+ * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
+ *	this node which can be a valid interrupt target candidate.
+ * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
+ * 	reserving an interrupt bit on the corresponding cnode is made.
+ *
+ * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
+ * interrupt target cpu then routine returns CPU_NONE (failure)
+ * Otherwise routine returns cpuid of interrupt target (success)
+ */
+static cpuid_t
+intr_bit_reserve_test(cpuid_t 		cpuid,
+		      int		favor_subnode,
+		      cnodeid_t 	cnodeid,
+		      int		req_bit,
+		      int 		intr_resflags,
+		      devfs_handle_t 	owner_dev,
+		      char		*intr_name,
+		      int		*resp_bit)
+{
+
+	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
+
+	if (cnodeid != CNODEID_NONE) {
+		/* Try to choose a interrupt cpu candidate */
+		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
+	}
+
+	if (cpuid != CPU_NONE) {
+		/* Try to reserve an interrupt bit on the hub 
+		 * corresponding to the canidate cnode. If we
+		 * are successful then we got a cpu which can
+		 * act as an interrupt target for the io device.
+		 * Otherwise we need to continue the search
+		 * further.
+		 */
+		*resp_bit = do_intr_reserve_level(cpuid, 
+						  req_bit,
+						  intr_resflags,
+						  II_RESERVE,
+						  owner_dev, 
+						  intr_name);
+
+		if (*resp_bit >= 0)
+			/* The interrupt target  specified was fine */
+			return(cpuid);
+	}
+	return(CPU_NONE);
+}
+/*
+ * intr_heuristic(dev_t dev,device_desc_t dev_desc,
+ *		  int req_bit,int intr_resflags,dev_t owner_dev,
+ *		  char *intr_name,int *resp_bit)
+ *
+ * Choose an interrupt destination for an interrupt.
+ *	dev is the device for which the interrupt is being set up
+ *	dev_desc is a description of hardware and policy that could
+ *		help determine where this interrupt should go
+ *	req_bit is the interrupt bit requested 
+ *		(can be INTRCONNECT_ANY_BIT in which the first available
+ * 		 interrupt bit is used)
+ *	intr_resflags indicates whether we want to (un)reserve bit
+ *	owner_dev is the owner device
+ *	intr_name is the readable interrupt name	
+ * 	resp_bit indicates whether we succeeded in getting the required
+ *		 action  { (un)reservation} done	
+ *		 negative value indicates failure
+ *
+ */
+/* ARGSUSED */
+cpuid_t
+intr_heuristic(devfs_handle_t 		dev,
+	       device_desc_t 	dev_desc,
+	       int		req_bit,
+	       int 		intr_resflags,
+	       devfs_handle_t 		owner_dev,
+	       char		*intr_name,
+	       int		*resp_bit)
+{
+	cpuid_t		cpuid;				/* possible intr targ*/
+	cnodeid_t 	candidate;			/* possible canidate */
+	int		which_subnode = SUBNODE_ANY;
+
+/* SN1 + pcibr Addressing Limitation */
+	{
+	devfs_handle_t pconn_vhdl;
+	pcibr_soft_t pcibr_soft;
+
+	/*
+	 * This combination of SN1 and Bridge hardware has an odd "limitation".
+	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
+	 * and historical limitations in Bridge, Bridge is unable to
+	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
+	 * to choose one set or the other.  That choice is implicitly
+	 * made when Bridge first attaches its error interrupt.  After
+	 * that point, all subsequent interrupts are restricted to the
+	 * same PI number (though it's possible to send interrupts to
+	 * the same PI number on a different node).
+	 *
+	 * Since neither SN1 nor Bridge designers are willing to admit a
+	 * bug, we can't really call this a "workaround".  It's a permanent
+	 * solution for an SN1-specific and Bridge-specific hardware
+	 * limitation that won't ever be lifted.
+	 */
+        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
+		/*
+		 * We "know" that the error interrupt is the first
+		 * interrupt set up by pcibr_attach.  Send all interrupts
+		 * on this bridge to the same subnode number.
+		 */
+		if (pcibr_soft->bsi_err_intr) {
+			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
+		}
+	}
+	}
+
+	/* Check if we can find a valid interrupt target candidate on
+	 * the master node for the device.
+	 */
+	cpuid = intr_bit_reserve_test(CPU_NONE,
+				      which_subnode,	
+				      master_node_get(dev),
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);	/* got a valid interrupt target */
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts to closest node(%d): %ld (0x%lx)\n",
+		master_node_get(dev),(long) owner_dev, (unsigned long)owner_dev);
+
+	/* Fall through into the default algorithm
+	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
+	 * for finding the interrupt target
+	 */
+
+#ifndef BRINGUP
+	// Use of this algorithm is deferred until the supporting
+	// code has been implemented.
+	/* 
+	 * No valid interrupt specification exists.
+	 * Try to find a node which is closest to the current node
+	 * which can process interrupts from a device
+	 */
+
+	center = cpuid_to_cnodeid(smp_processor_id());
+	while (radius <= maxradius) {
+
+		/* Try to find a node at the given radius and which
+		 * we haven't seen already.
+		 */
+		rv = physmem_select_neighbor_node(center,radius,&candidate,
+						  intr_cnode_seen,
+						  (void *)visited_cnodes,
+						  (void *)&num_visited_cnodes);
+		if (!rv) {
+			/* We have seen all the nodes at this particular radius
+			 * Go on to the next radius level.
+			 */
+			radius++;
+			continue;
+		}			      
+		/* We are seeing this candidate  cnode for the first time
+		 */
+		visited_cnodes[num_visited_cnodes++] = candidate;
+
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+					      which_subnode,
+					      candidate,
+					      req_bit,
+					      intr_resflags,
+					      owner_dev,
+					      intr_name,
+					      resp_bit);
+
+		if (cpuid != CPU_NONE) {
+			if (cpu_on_subnode(cpuid, which_subnode))
+				return(cpuid);	/* got a valid interrupt target */
+			else
+				intr_unreserve_level(cpuid, *resp_bit);
+		}
+	}
+#else  /* BRINGUP */
+	{
+	// Do a stupid round-robin assignment of the node.
+		static cnodeid_t last_node = -1;
+
+		if (last_node >= num_compact_nodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == num_compact_nodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+					      which_subnode,
+					      candidate,
+					      req_bit,
+					      intr_resflags,
+					      owner_dev,
+					      intr_name,
+					      resp_bit);
+
+			if (cpuid != CPU_NONE) {
+				if (cpu_on_subnode(cpuid, which_subnode)) {
+					last_node = candidate;
+					return(cpuid);	/* got a valid interrupt target */
+				}
+				else
+					intr_unreserve_level(cpuid, *resp_bit);
+			}
+		}
+		last_node = candidate;
+	}
+#endif
+
+	printk(KERN_WARNING  "Cannot target interrupts to any close node: %ld (0x%lx)\n",
+		(long)owner_dev, (unsigned long)owner_dev);
+
+	/* In the worst case try to allocate interrupt bits on the
+	 * master processor's node. We may get here during error interrupt
+	 * allocation phase when the topology matrix is not yet setup
+	 * and hence cannot do an exhaustive search.
+	 */
+	ASSERT(cpu_allows_intr(master_procid));
+	cpuid = intr_bit_reserve_test(master_procid,
+				      which_subnode,
+				      CNODEID_NONE,
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts: %ld (0x%lx)\n",
+		(long)owner_dev, (unsigned long)owner_dev);
+
+	return(CPU_NONE);	/* Should never get here */
+}
+
+
+
+
+#ifndef BRINGUP
+/*
+ * Should never receive an exception while running on the idle 
+ * stack.  It IS possible to handle *interrupts* while on the
+ * idle stack, but a non-interrupt *exception* is a problem.
+ */
+void
+idle_err(inst_t *epc, uint cause, void *fep, void *sp)
+{
+	eframe_t *ep = (eframe_t *)fep;
+
+    if ((cause & CAUSE_EXCMASK) == EXC_IBE ||
+	(cause & CAUSE_EXCMASK) == EXC_DBE) {
+	(void)dobuserre((eframe_t *)ep, epc, 0);
+    }
+
+    /* XXX - This will have to change to deal with various SN errors. */
+    panic( "exception on IDLE stack "
+	    "ep:0x%x epc:0x%x cause:0x%w32x sp:0x%x badvaddr:0x%x",
+	    ep, epc, cause, sp, getbadvaddr());
+    /* NOTREACHED */
+}
+
+
+/*
+ * earlynofault - handle very early global faults - usually just while
+ *      sizing memory
+ * Returns: 1 if should do nofault
+ *          0 if not
+ */
+/* ARGSUSED */
+int
+earlynofault(eframe_t *ep, uint code)
+{
+	switch(code) {
+	case EXC_DBE:
+		return(1);
+	default:
+		return(0);
+	}
+}
+
+
+
+/* ARGSUSED */
+static void
+cpuintr(void *arg1, void *arg2)
+{
+#if RTE
+	static int rte_intrdebug = 1;
+#endif
+	/*
+	 * Frame Scheduler
+	 */
+	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_CPUINTR, NULL, NULL,
+			 NULL, NULL);
+
+	/*
+	 * Hardware clears the IO interrupts, but we need to clear software-
+	 * generated interrupts.
+	 */
+	LOCAL_HUB_CLR_INTR(CPU_ACTION_A + cpuid_to_localslice(cpuid()));
+
+#if 0
+	/* XXX - Handle error interrupts. */
+	if (error_intr_reason)
+		error_intr();
+#endif /* 0 */
+
+	/*
+	 * If we're headed for panicspin and it is due to a NMI, save the
+	 * eframe in the NMI area
+	 */
+	if (private.p_va_panicspin && nmied) {
+		caddr_t	nmi_save_area;
+
+		nmi_save_area = (caddr_t) (TO_UNCAC(TO_NODE(
+			cpuid_to_nasid(cpuid()), IP27_NMI_EFRAME_OFFSET)) + 
+			cpuid_to_slice(cpuid()) * IP27_NMI_EFRAME_SIZE);
+		bcopy((caddr_t) arg2, nmi_save_area, sizeof(eframe_t));
+	}
+
+	doacvec();
+#if RTE
+	if (private.p_flags & PDAF_ISOLATED && !rte_intrdebug)
+		goto end_cpuintr;
+#endif
+	doactions();
+#if RTE
+end_cpuintr:
+#endif
+	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_INTREXIT, TSTAMP_EV_CPUINTR, NULL, NULL, NULL);
+}
+
+void
+install_cpuintr(cpuid_t cpu)
+{
+	int		intr_bit = CPU_ACTION_A + cpuid_to_localslice(cpu);
+
+	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK, NULL))
+		panic("install_cpuintr: Can't connect interrupt.");
+}
+#endif /* BRINGUP */
+
+#ifdef DEBUG_INTR_TSTAMP
+/* We allocate an array, but only use element number 64.  This guarantees that
+ * the entry is in a cacheline by itself.
+ */
+#define DINTR_CNTIDX	32
+#define DINTR_TSTAMP1	48
+#define	DINTR_TSTAMP2	64
+volatile long long dintr_tstamp_cnt[128];
+int dintr_debug_output=0;
+extern void idbg_tstamp_debug(void);
+#ifdef SPLDEBUG
+extern void idbg_splx_log(int);
+#endif
+#if DEBUG_INTR_TSTAMP_DEBUG
+int dintr_enter_symmon=1000;	/* 1000 microseconds is 1 millisecond */
+#endif
+
+#ifndef BRINGUP
+/* ARGSUSED */
+static void
+cpulatintr(void *arg)
+{
+	/*
+	 * Hardware only clears IO interrupts so we have to clear our level
+	 * here.
+	 */
+	LOCAL_HUB_CLR_INTR(CPU_INTRLAT_A + cpuid_to_localslice(cpuid()));
+
+#if DEBUG_INTR_TSTAMP_DEBUG
+	dintr_tstamp_cnt[DINTR_TSTAMP2] =  GET_LOCAL_RTC();
+	if ((dintr_tstamp_cnt[DINTR_TSTAMP2] - dintr_tstamp_cnt[DINTR_TSTAMP1])
+	    > dintr_enter_symmon) {
+#ifdef SPLDEBUG
+		extern int spldebug_log_off;
+
+		spldebug_log_off = 1;
+#endif /* SPLDEBUG */
+		debug("ring");
+#ifdef SPLDEBUG
+		spldebug_log_off = 0;
+#endif /* SPLDEBUG */
+	}
+#endif
+	dintr_tstamp_cnt[DINTR_CNTIDX]++;
+
+	return;
+}
+
+static int install_cpulat_first=0;
+
+void
+install_cpulatintr(cpuid_t cpu)
+{
+	int		intr_bit;
+	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
+
+	intr_bit = CPU_INTRLAT_A + cpuid_to_localslice(cpu);
+	if (intr_bit != intr_reserve_level(cpu, intr_bit, II_THREADED,
+					   cpuv, "intrlat"))
+		panic( "install_cpulatintr: Can't reserve interrupt.");
+
+	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
+				cpulatintr, NULL, NULL))
+		panic( "install_cpulatintr: Can't connect interrupt.");
+
+	if (!install_cpulat_first) {
+		install_cpulat_first++;
+		idbg_addfunc("tstamp_debug", (void (*)())idbg_tstamp_debug);
+#if defined(SPLDEBUG) || defined(SPLDEBUG_CPU_EVENTS)
+		idbg_addfunc("splx_log", (void (*)())idbg_splx_log);
+#endif /* SPLDEBUG || SPLDEBUG_CPU_EVENTS */
+	}
+}
+#endif /* BRINGUP */
+
+#endif /* DEBUG_INTR_TSTAMP */
+
+#ifndef BRINGUP
+/* ARGSUSED */
+static void
+dbgintr(void *arg)
+{
+	/*
+	 * Hardware only clears IO interrupts so we have to clear our level
+	 * here.
+	 */
+	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + DEBUG_INTR_A + cpuid_to_localslice(cpuid()));
+
+	debug("zing");
+	return;
+}
+
+
+void
+install_dbgintr(cpuid_t cpu)
+{
+	int		intr_bit;
+	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
+
+	intr_bit = N_INTPEND_BITS + DEBUG_INTR_A + cpuid_to_localslice(cpu);
+	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
+		panic("install_dbgintr: Can't reserve interrupt. "
+			" intr_bit %d" ,intr_bit);
+
+	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
+				dbgintr, NULL, NULL))
+		panic("install_dbgintr: Can't connect interrupt.");
+
+#ifdef DEBUG_INTR_TSTAMP
+	/* Set up my interrupt latency test interrupt */
+	install_cpulatintr(cpu);
+#endif
+}
+
+/* ARGSUSED */
+static void
+tlbintr(void *arg)
+{
+	extern void tlbflush_rand(void);
+
+	/*
+	 * Hardware only clears IO interrupts so we have to clear our level
+	 * here.
+	 */
+	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + TLB_INTR_A + cpuid_to_localslice(cpuid()));
+
+	tlbflush_rand();
+	return;
+}
+
+
+void
+install_tlbintr(cpuid_t cpu)
+{
+	int		intr_bit;
+	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
+
+	intr_bit = N_INTPEND_BITS + TLB_INTR_A + cpuid_to_localslice(cpu);
+	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
+		panic("install_tlbintr: Can't reserve interrupt. "
+			" intr_bit %d" ,intr_bit);
+
+	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK, NULL))
+		panic("install_tlbintr: Can't connect interrupt.");
+
+}
+
+
+/*
+ * Poll the interrupt register to see if another cpu has asked us
+ * to drop into the debugger (without lowering spl).
+ */
+void
+chkdebug(void)
+{
+	if (LOCAL_HUB_L(PI_INT_PEND1) & (1L << (DEBUG_INTR_A + cpuid_to_localslice(cpuid()))))
+		dbgintr((void *)NULL);
+}
+
+
+/*
+ * Install special graphics interrupt.
+ */
+void
+install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg)
+{
+	int intr_bit = GFX_INTR_A + cpuid_to_localslice(cpu);
+
+	if (intr_connect_level(cpu, intr_bit, swlevel, NULL))
+		panic("install_gfxintr: Can't connect interrupt.");
+}
+
+
+/*
+ * Install page migration interrupt handler.
+ */
+void
+hub_migrintr_init(cnodeid_t cnode)
+{
+	cpuid_t cpu = cnodetocpu(cnode);
+	int intr_bit = INT_PEND0_BASELVL + PG_MIG_INTR;
+
+	if (num_compact_nodes == 1){
+		/* 
+		 * No migration with just one node..
+		 */
+		return;
+	}
+	
+	if (cpu != -1) {
+		if (intr_connect_level(cpu, intr_bit, 0, (intr_func_t) migr_intr_prologue_handler))
+			panic( "hub_migrintr_init: Can't connect interrupt.");
+	}
+}
+
+
+/*
+ * Cause all CPUs to stop by sending them each a DEBUG interrupt.
+ * Parameter is actually a (cpumask_t *).
+ */
+void
+debug_stop_all_cpus(void *stoplist)
+{
+	int cpu;
+	ulong level;
+
+	for (cpu=0; cpu<maxcpus; cpu++) {
+		if (cpu == cpuid())
+			continue;
+		if (!cpu_enabled(cpu))
+		        continue;
+		/* "-1" is the old style parameter OR could be the new style
+		 * if no-one is currently stopped.  We only stop the
+		 * requested cpus, the others are already stopped (probably
+		 * at a breakpoint).
+		 */
+
+		if (((cpumask_t *)stoplist != (cpumask_t *)-1LL) &&
+		    (!CPUMASK_TSTB(*(cpumask_t*)stoplist, cpu)))
+			continue;
+
+		/*
+		 * CPU lslice A gets level DEBUG_INTR_A
+		 * CPU lslice B gets level DEBUG_INTR_B
+		 */
+		level = DEBUG_INTR_A + LOCALCPU(get_cpu_slice(cpu));
+		/*
+		 * Convert the compact hub number to the NASID to get the
+		 * correct part of the address space.  Then set the interrupt
+		 * bit associated with the CPU we want to send the interrupt
+		 * to.
+		 */
+#if defined(CONFIG_IA64_SGI_SN1)
+		REMOTE_CPU_SEND_INTR(cpu, N_INTPEND_BITS + level);
+#endif
+
+	}
+}
+
+#endif /* BRINGUP */
+
+struct hardwired_intr_s {
+	signed char level;
+	int flags;
+	char *name;
+} const hardwired_intr[] = {
+	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
+	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
+	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
+	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
+	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
+	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
+	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
+	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
+	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
+	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
+	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
+	{ -1, 0, (char *)NULL},
+};
+
+/*
+ * Reserve all of the hardwired interrupt levels so they're not used as
+ * general purpose bits later.
+ */
+void
+intr_reserve_hardwired(cnodeid_t cnode)
+{
+	cpuid_t cpu;
+	int level;
+	int i;
+	char subnode_done[NUM_SUBNODES];
+
+	// cpu = cnodetocpu(cnode);
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+		if (cpuid_to_cnodeid(cpu) == cnode) {
+			break;
+		}
+	}
+	if (cpu == smp_num_cpus) cpu = CPU_NONE;
+	if (cpu == CPU_NONE) {
+		printk("Node %d has no CPUs", cnode);
+		return;
+	}
+
+	for (i=0; i<NUM_SUBNODES; i++)
+		subnode_done[i] = 0;
+
+	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
+		int which_subnode = cpuid_to_subnode(cpu);
+		if (subnode_done[which_subnode])
+			continue;
+		subnode_done[which_subnode] = 1;
+
+		for (i = 0; hardwired_intr[i].level != -1; i++) {
+			level = hardwired_intr[i].level;
+
+			if (level != intr_reserve_level(cpu, level,
+						hardwired_intr[i].flags,
+						(devfs_handle_t) NULL,
+						hardwired_intr[i].name))
+				panic("intr_reserve_hardwired: Can't reserve level %d, cpu %ld.", level, cpu);
+		}
+	}
+}
+
+
+/*
+ * Check and clear interrupts.
+ */
+/*ARGSUSED*/
+static void
+intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
+		char *name)
+{
+	volatile hubreg_t bits;
+	int i;
+
+	/* Check pending interrupts */
+	if ((bits = HUB_L(pend)) != 0) {
+		for (i = 0; i < N_INTPEND_BITS; i++) {
+			if (bits & (1 << i)) {
+#ifdef INTRDEBUG
+				printk(KERN_WARNING  "Nasid %d interrupt bit %d set in %s",
+					nasid, i, name);
+#endif
+				LOCAL_HUB_CLR_INTR(base_level + i);
+			}
+		}
+	}
+}
+
+/*
+ * Clear out our interrupt registers.
+ */
+void
+intr_clear_all(nasid_t nasid)
+{
+	int	sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
+	
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
+				INT_PEND0_BASELVL, "INT_PEND0");
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
+				INT_PEND1_BASELVL, "INT_PEND1");
+	}
+}
+
+/* 
+ * Dump information about a particular interrupt vector.
+ */
+static void
+dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
+		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
+{
+	hubreg_t value = 1LL << bit;
+
+	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
+		bit, info->ii_name,
+		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
+	pf("   vertex 0x%x %s%s",
+		info->ii_owner_dev,
+		((info->ii_flags) & II_RESERVE) ? "R" : "U",
+		((info->ii_flags) & II_INUSE) ? "C" : "-");
+	pf("%s%s%s%s",
+		ip & value ? "P" : "-",
+		ima & value ? "A" : "-",
+		imb & value ? "B" : "-",
+		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
+	pf("\n");
+}
+
+
+/*
+ * Dump information about interrupt vector assignment.
+ */
+void
+intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
+{
+	nodepda_t *npda;
+	int ip, sn, bit;
+	intr_vecblk_t *dispatch;
+	hubreg_t ipr, ima, imb;
+	nasid_t nasid;
+
+	if ((cnode < 0) || (cnode >= num_compact_nodes)) {
+		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
+		return ;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	if (nasid == INVALID_NASID) {
+		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
+		return ;
+	}
+		
+
+	npda = NODEPDA(cnode);
+
+	for (sn = 0; sn < NUM_SUBNODES; sn++) {
+		for (ip = 0; ip < 2; ip++) {
+			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
+			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
+			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
+			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
+	
+			pf("Node %d INT_PEND%d:\n", cnode, ip);
+	
+			if (dispatch->ithreads_enabled)
+				pf(" Ithreads enabled\n");
+			else
+				pf(" Ithreads disabled\n");
+			pf(" vector_count = %d, vector_state = %d\n",
+				dispatch->vector_count,
+				dispatch->vector_state);
+			pf(" CPU A count %d, CPU B count %d\n",
+ 		   	dispatch->cpu_count[0],
+ 		   	dispatch->cpu_count[1]);
+			pf(" &vector_lock = 0x%x\n",
+				&(dispatch->vector_lock));
+			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
+				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
+			    	(ipr & (1L << bit))) {
+					dump_vector(&(dispatch->info[bit]),
+					    	&(dispatch->vectors[bit]),
+					    	bit, ipr, ima, imb, pf);
+				}
+			}
+			pf("\n");
+		}
+	}
+}
+
diff -urN linux-2.4.16/arch/ia64/sn/io/sn1/pcibr.c lia64-2.4/arch/ia64/sn/io/sn1/pcibr.c
--- linux-2.4.16/arch/ia64/sn/io/sn1/pcibr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn1/pcibr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,7941 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifdef BRINGUP
+int NeedXbridgeSwap = 0;
+#endif
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern boolean_t                is_sys_critical_vertex(devfs_handle_t);
+
+#undef PCIBR_ATE_DEBUG
+#if defined(BRINGUP)
+#if 0
+#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
+#endif
+#define PCI_DEBUG 1
+#define ATTACH_DEBUG 1
+#define PCIBR_SOFT_LIST 1
+#endif
+
+#ifndef	LOCAL
+#define	LOCAL		static
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#include <asm/sn/io.h>
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+#define PCIBR_LLP_CONTROL_WAR
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+int                     pcibr_devflag = D_MP;
+
+#ifdef LATER
+#define F(s,n)		{ 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+
+#if DEBUG
+#define	device_desc	device_bits
+LOCAL struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+#endif	/* DEBUG */
+
+#ifdef SUPPORT_PRINTING_R_FORMAT
+LOCAL struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+LOCAL struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+#endif	/* SUPPORT_PRINTING_R_FORMAT */
+
+#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+
+#if PCIBR_ATE_DEBUG
+LOCAL struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+LOCAL struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;	/* another space for this device */
+    char                    free;	/* 1 if free, 0 if in use               */
+    pciio_space_t           space;	/* Which space is in use                */
+    iopaddr_t               start;	/* Starting address of the PIO space    */
+    size_t                  count;	/* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
+
+#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
+#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
+
+#define PCIBR_VALID_SLOT(s)	(s < 8)
+
+#ifdef SN_XXX
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+#endif
+extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the 
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+        owner:  THIS_MODULE,
+        llseek: NULL,
+        read: NULL,
+        write: NULL,
+        readdir: NULL,
+        poll: NULL,
+        ioctl: NULL,
+        mmap: NULL,
+        open: NULL,
+        flush: NULL,
+        release: NULL,
+        fsync: NULL,
+        fasync: NULL,
+        lock: NULL,
+        readv: NULL,
+        writev: NULL
+};
+
+extern devfs_handle_t hwgraph_root;
+extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
+extern int cap_able(uint64_t x);
+extern uint64_t rmalloc(struct map *mp, size_t size);
+extern void rmfree(struct map *mp, size_t size, uint64_t a);
+extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern long atoi(register char *p);
+extern void *swap_ptr(void **loc, void *new);
+extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
+extern struct map *rmallocmap(uint64_t mapsiz);
+extern void rmfreemap(struct map *mp);
+extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
+extern int io_path_map_widget(devfs_handle_t vertex);
+
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
+LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
+LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int			pcibr_wrb_flush(devfs_handle_t);
+int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void                    pcibr_rrb_flush(devfs_handle_t);
+
+LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+LOCAL void              pcibr_clearwidint(bridge_t *);
+LOCAL void              pcibr_setwidint(xtalk_intr_t);
+LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
+
+void                    pcibr_init(void);
+int                     pcibr_attach(devfs_handle_t);
+int			pcibr_detach(devfs_handle_t);
+int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
+LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
+LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
+LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+LOCAL void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
+uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
+
+LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+
+#ifdef LATER
+LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
+                                               pcibr_slot_info_resp_t);
+LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
+                                                    pcibr_slot_func_info_resp_t);
+#endif	/* LATER */
+
+LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
+						      pciio_slot_t, int);
+LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
+						      pciio_slot_t, int);
+
+LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+#ifdef LATER
+LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
+#endif
+
+/* =====================================================================
+ *    RRB management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+#define PCIBR_RRB_SLOT_VIRTUAL	8
+
+LOCAL void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+LOCAL void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+LOCAL int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+LOCAL int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+LOCAL int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+LOCAL int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+LOCAL void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+	printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devies.  The evn_odd argument indicates whether
+ * allcoation for the odd or even rrbs is requested and next group of four pairse
+ * are the amount to assign to each device (they should sum to <= 8) and
+ * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
+ * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
+ * if even_odd is even we alloc even rrbs else we allocate odd rrbs
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t            pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = NULL;
+    bridge_t               *bridge = NULL;
+
+    uint32_t              rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t              cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+	    cur_rrb = i | 0xc;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	    dev_rrbs[i] = dev_rrbs[i] - 1;
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+LOCAL int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+LOCAL void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+LOCAL int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+
+#ifdef LATER
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+#else
+    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
+#endif
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+#else
+    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
+#endif
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = snia_kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+    
+    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+#else
+    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
+#endif
+    slotp->resp_slot_status = pss->slot_status;
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    snia_kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(EINVAL);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(EINVAL);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_POWERUP:
+	{
+	    pciio_slot_t	slot;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_info_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+LOCAL int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+LOCAL int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+LOCAL void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
+
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+LOCAL pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+	DEL(pcibr_info);
+    }
+
+    /* Clear the DEVIO(x) for this slot */
+    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
+    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_device  = 0;
+
+    
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    int                 c0, c1;
+    int			r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /* Free the rrbs allocated to this slot */
+    error_call = do_pcibr_rrb_free(bridge, slot, 
+		                   pcibr_soft->bs_rrb_valid[slot] +
+		                   pcibr_soft->bs_rrb_valid[slot + 
+                                   PCIBR_RRB_SLOT_VIRTUAL]);
+
+    if (error_call)
+        error = ERANGE;
+
+    pcibr_soft->bs_rrb_valid[slot] = 0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
+    pcibr_soft->bs_rrb_res[slot] = 0;
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+#ifndef MEDUSA_HACK
+    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
+	return -1;			/* someone else handles GIO bridges. */
+#endif
+
+#ifdef BRINGUP
+    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
+	NeedXbridgeSwap = 1;
+#endif
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	/*
+	 * Determine the base address node id to be used for all 32-bit
+	 * Direct Mapping I/O. The default is node 0, but this can be changed
+	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
+	 * attribute in the irix.sm config file. A device driver can obtain
+	 * this node value via a call to pcibr_get_dmatrans_node().
+	 */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
+	    bridge->b_int_ate_ram[entry].wr = 0;
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+#ifndef __ia64
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up convenience links */
+	if (is_xbridge(bridge))
+		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
+			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+LOCAL iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+LOCAL iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+LOCAL bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+#ifdef IRIX
+    NEWf(pcibr_dmamap, flags);
+#else
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+#endif
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+	DEL(pcibr_dmamap);
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+	DEL(pcibr_dmamap);
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+    DEL(pcibr_dmamap);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#endif
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+LOCAL bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+LOCAL iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+LOCAL unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+LOCAL void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+LOCAL void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+static unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+LOCAL void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+#ifdef CONFIG_IA64_SGI_SN2
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 26)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#elif CONFIG_IA64_SGI_SN1
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#endif
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+LOCAL void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+LOCAL void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+#ifdef LITTLE_ENDIAN
+/*
+ * on sn-ia we need to twiddle the the addresses going out
+ * the pci bus because we use the unswizzled synergy space
+ * (the alternative is to use the swizzled synergy space
+ * and byte swap the data)
+ */
+#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
+#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
+#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
+#else
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+#endif /* LITTLE_ENDIAN */
+
+
+LOCAL                   cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+LOCAL uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+   
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+LOCAL void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+LOCAL                   pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
+
+
+#ifdef LATER
+
+#include <sys/idbg.h>
+#include <sys/idbgentry.h>
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_vertex);
+#endif
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_master);
+#endif
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+
+#endif /* LATER */
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/ml_SN_intr.c lia64-2.4/arch/ia64/sn/io/sn2/ml_SN_intr.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/ml_SN_intr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/ml_SN_intr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,471 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
+ * Copyright (C) 2001	Alan mayer (ajm@sgi.com)
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IPXX board.
+ */
+
+#ident  "$Revision: 1.167 $"
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <asm/smp.h>
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/sn2/shub_mmr_t.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+
+extern irqpda_t	*irqpdaindr[];
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+extern nasid_t master_nasid;
+
+//  Initialize some shub registers for interrupts, both IO and error.
+
+void
+intr_init_vecblk( nodepda_t *npda,
+		cnodeid_t node,
+		int sn)
+{
+	int 			nasid = cnodeid_to_nasid(node);
+	nasid_t			console_nasid;
+	sh_ii_int0_config_u_t	ii_int_config;
+	cpuid_t			cpu;
+	cpuid_t			cpu0, cpu1;
+	nodepda_t		*lnodepda;
+	sh_ii_int0_enable_u_t	ii_int_enable;
+	sh_local_int0_config_u_t	local_int_config;
+	sh_local_int0_enable_u_t	local_int_enable;
+	sh_fsb_system_agent_config_u_t	fsb_system_agent;
+	sh_int_node_id_config_u_t	node_id_config;
+	int is_console;
+
+	console_nasid = ia64_sn_get_console_nasid();
+	if (console_nasid < 0) {
+		console_nasid = master_nasid;
+	}
+
+	is_console = nasid == console_nasid;
+
+	if (is_headless_node(node) ) {
+		int cnode;
+		struct ia64_sal_retval ret_stuff;
+
+		// retarget all interrupts on this node to the master node.
+		node_id_config.sh_int_node_id_config_regval = 0;
+		node_id_config.sh_int_node_id_config_s.node_id = master_nasid;
+		node_id_config.sh_int_node_id_config_s.id_sel = 1;
+		HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_INT_NODE_ID_CONFIG),
+			node_id_config.sh_int_node_id_config_regval);
+		cnode = nasid_to_cnodeid(master_nasid);
+		lnodepda = NODEPDA(cnode);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+		SAL_CALL(ret_stuff, SN_SAL_REGISTER_CE, nasid, cpu, master_nasid,0,0,0,0);
+		if (ret_stuff.status < 0) {
+			printk("%s: SN_SAL_REGISTER_CE SAL_CALL failed\n",__FUNCTION__);
+		}
+	} else {
+		lnodepda = NODEPDA(node);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+	}
+
+	// Get the physical id's of the cpu's on this node.
+	cpu0 = id_eid_to_cpu_physical_id(nasid, 0);
+	cpu1 = id_eid_to_cpu_physical_id(nasid, 1);
+
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_ERROR_MASK), 0);
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_CRBP_ERROR_MASK), 0);
+
+	// The II_INT_CONFIG register for cpu 0.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu0;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// The II_INT_CONFIG register for cpu 1.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu1;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// Enable interrupts for II_INT0 and 1.
+	ii_int_enable.sh_ii_int0_enable_s.ii_enable = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+
+	// init error regs
+	// LOCAL_INT0 is for the UART only.
+
+	local_int_config.sh_local_int0_config_s.type = 0;
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.pid = cpu;
+	local_int_config.sh_local_int0_config_s.base = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_UART_VECTOR;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// LOCAL_INT1 is for all hardware errors.
+	// It will send a BERR, which will result in an MCA.
+	local_int_config.sh_local_int0_config_s.idx = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// Clear the LOCAL_INT_ENABLE register.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	if (is_console) {
+		// Enable the UART interrupt.  Only applies to the console nasid.
+		local_int_enable.sh_local_int0_enable_s.uart_int = 1;
+
+		HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_ENABLE),
+			local_int_enable.sh_local_int0_enable_regval);
+	}
+
+	// Enable all the error interrupts.
+	local_int_enable.sh_local_int0_enable_s.uart_int = 0;
+	local_int_enable.sh_local_int0_enable_s.pi_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.lb_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.ii_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.pi_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.system_shutdown_int = 1;
+	local_int_enable.sh_local_int0_enable_s.l1_nmi_int = 1;
+	local_int_enable.sh_local_int0_enable_s.stop_clock = 1;
+
+
+	// Send BERR, rather than an interrupt, for shub errors.
+	local_int_config.sh_local_int0_config_s.agt = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure BERR is enabled.
+	fsb_system_agent.sh_fsb_system_agent_config_regval = 
+		HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG) );
+	fsb_system_agent.sh_fsb_system_agent_config_s.berr_assert_en = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG),
+		fsb_system_agent.sh_fsb_system_agent_config_regval);
+
+	// Set LOCAL_INT2 to field CEs
+
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_SHUB_ERROR_VECTOR;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	local_int_enable.sh_local_int0_enable_s.pi_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_ce_int = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure all the rest of the LOCAL_INT regs are disabled.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT3_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT4_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+}
+
+// (Un)Reserve an irq on this cpu.
+
+static int
+do_intr_reserve_level(cpuid_t cpu,
+			int bit,
+			int reserve)
+{
+	int i;
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (reserve) {
+		if (bit < 0) {
+			for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
+				if (irqs->irq_flags[i] == 0) {
+					bit = i;
+					break;
+				}
+			}
+		}
+		if (bit < 0) {
+			return -1;
+		}
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			return -1;
+		} else {
+			irqs->num_irq_used++;
+			irqs->irq_flags[bit] |= SN2_IRQ_RESERVED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			irqs->num_irq_used--;
+			irqs->irq_flags[bit] &= ~SN2_IRQ_RESERVED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+}
+
+int
+intr_reserve_level(cpuid_t cpu,
+		int bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, 1));
+}
+
+void
+intr_unreserve_level(cpuid_t cpu,
+		int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0);
+}
+
+// Mark an irq on this cpu as (dis)connected.
+
+static int
+do_intr_connect_level(cpuid_t cpu,
+			int bit,
+			int connect)
+{
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (connect) {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			return -1;
+		} else {
+			irqs->irq_flags[bit] |= SN2_IRQ_CONNECTED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			irqs->irq_flags[bit] &= ~SN2_IRQ_CONNECTED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+	return(bit);
+}
+
+int
+intr_connect_level(cpuid_t cpu,
+		int bit,
+		ilvl_t is,
+		intr_func_t intr_prefunc)
+{
+	return(do_intr_connect_level(cpu, bit, 1));
+}
+
+int
+intr_disconnect_level(cpuid_t cpu,
+		int bit)
+{
+	return(do_intr_connect_level(cpu, bit, 0));
+}
+
+// Choose a cpu on this node.
+// We choose the one with the least number of int's assigned to it.
+
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode) {
+	cpuid_t		cpu, best_cpu = CPU_NONE;
+	int		slice, min_count = 1000;
+	irqpda_t	*irqs;
+
+	for (slice = 0; slice < CPUS_PER_NODE; slice++) {
+		int intrs;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE) {
+			continue;
+		}
+
+		if (!cpu_enabled(cpu)) {
+			continue;
+		}
+
+		irqs = irqpdaindr[cpu];
+		intrs = irqs->num_irq_used;
+
+		if (min_count > intrs) {
+			min_count = intrs;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode)
+{
+	return(do_intr_cpu_choose(cnode));
+}
+
+// See if we can use this cpu/vect.
+
+static cpuid_t
+intr_bit_reserve_test(cpuid_t cpu,
+			int favor_subnode,
+			cnodeid_t cnode,
+			int req_bit,
+			int resflags,
+			devfs_handle_t owner_dev,
+			char *name,
+			int *resp_bit)
+{
+	ASSERT( (cpu == CPU_NONE) || (cnode == CNODEID_NONE) );
+
+	if (cnode != CNODEID_NONE) {
+		cpu = intr_cpu_choose_from_node(cnode);
+	}
+
+	if (cpu != CPU_NONE) {
+		*resp_bit = do_intr_reserve_level(cpu, req_bit, 1);
+		if (*resp_bit >= 0) {
+			return(cpu);
+		}
+	}
+	return CPU_NONE;
+}
+
+// Find the node to assign for this interrupt.
+
+cpuid_t
+intr_heuristic(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		int	req_bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name,
+		int *resp_bit)
+{
+	cpuid_t		cpuid;
+	cnodeid_t	candidate = -1;
+	devfs_handle_t	pconn_vhdl;
+	pcibr_soft_t	pcibr_soft;
+
+/* SN2 + pcibr addressing limitation */
+/* Due to this limitation, all interrupts from a given bridge must go to the name node.*/
+/* This limitation does not exist on PIC. */
+
+	if ( (hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+		( (pcibr_soft = pcibr_soft_get(pconn_vhdl) ) != NULL) ) {
+			if (pcibr_soft->bsi_err_intr) {
+				candidate = cpuid_to_cnodeid( ((hub_intr_t)pcibr_soft->bsi_err_intr)->i_cpuid);
+			}
+	}
+
+	if (candidate >= 0) {
+		// The node was chosen already when we assigned the error interrupt.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						candidate,
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	} else {
+		// Need to choose one.  Try the controlling c-brick first.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						master_node_get(dev),
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	}
+
+	if (cpuid != CPU_NONE) {
+		return cpuid;
+	}
+
+	if (candidate >= 0) {
+		printk("Cannot target interrupt to target node (%d).\n",candidate);
+		return CPU_NONE;
+	} else {
+		printk("Cannot target interrupt to closest node (%d) 0x%p\n",
+			master_node_get(dev), (void *)owner_dev);
+	}
+
+	// We couldn't put it on the closest node.  Try to find another one.
+	// Do a stupid round-robin assignment of the node.
+
+	{
+		static cnodeid_t last_node = -1;
+		if (last_node >= num_compact_nodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == num_compact_nodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+							0,
+							candidate,
+							req_bit,
+							0,
+							owner_dev,
+							name,
+							resp_bit);
+			if (cpuid != CPU_NONE) {
+				return cpuid;
+			}
+		}
+	}
+
+	printk("cannot target interrupt: 0x%p\n",(void *)owner_dev);
+	return CPU_NONE;
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,455 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+uint64_t atealloc(struct map *mp, size_t size);
+void atefree(struct map *mp, size_t size, uint64_t a);
+void atemapfree(struct map *mp);
+struct map *atemapalloc(uint64_t mapsiz);
+
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+
+#ifdef LATER
+#if (PCIBR_FREEZE_TIME) || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+#ifndef LOCAL
+#define LOCAL           static
+#endif
+
+/*
+ * functions
+ */
+int               pcibr_init_ext_ate_ram(bridge_t *);
+int               pcibr_ate_alloc(pcibr_soft_t, int);
+void              pcibr_ate_free(pcibr_soft_t, int, int);
+bridge_ate_t      pcibr_flags_to_ate(unsigned);
+bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+unsigned 	  ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   			unsigned *freeze_time_ptr,
+#endif
+	   			unsigned *cmd_regs);
+void 	  ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+void ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 			int ate_index,
+#if PCIBR_FREEZE_TIME
+	 			bridge_ate_t ate,
+	 			int ate_total,
+	 			unsigned freeze_time_start,
+#endif
+	 			unsigned *cmd_regs,
+	 			unsigned s);
+
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no external ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,144 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+uint64_t          pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void              pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+
+
+cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,4293 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifdef BRINGUP
+int NeedXbridgeSwap = 0;
+#endif
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+int                     pcibr_devflag = D_MP;
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+	owner:  THIS_MODULE,
+	llseek: NULL,
+	read: NULL,
+	write: NULL,
+	readdir: NULL,
+	poll: NULL,
+	ioctl: NULL,
+	mmap: NULL,
+	open: NULL,
+	flush: NULL,
+	release: NULL,
+	fsync: NULL,
+	fasync: NULL,
+	lock: NULL,
+	readv: NULL,
+	writev: NULL
+};
+
+#ifdef LATER
+
+#if PCIBR_ATE_DEBUG
+static struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+static struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+
+    {BRIDGE_CTRL_BUS_SPEED_MASK, -4, "BUS_SPEED", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;       /* another space for this device */
+    char                    free;       /* 1 if free, 0 if in use               */
+    pciio_space_t           space;      /* Which space is in use                */
+    iopaddr_t               start;      /* Starting address of the PIO space    */
+    size_t                  count;      /* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+extern int              hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern int              hub_device_flags_set(devfs_handle_t widget_dev, hub_widget_flags_t flags);
+extern long             atoi(register char *p);
+extern cnodeid_t        nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern void             *swap_ptr(void **loc, void *new);
+extern char             *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern struct map       *atemapalloc(uint64_t);
+extern void             atefree(struct map *, size_t, uint64_t);
+extern void             atemapfree(struct map *);
+extern pciio_dmamap_t   get_free_pciio_dmamap(devfs_handle_t);
+
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif /* PCIBR_FREEZE_TIME */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+extern void              do_pcibr_rrb_clear(bridge_t *, int);
+extern void              do_pcibr_rrb_flush(bridge_t *, int);
+extern int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+extern int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+extern void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+extern int  		 pcibr_wrb_flush(devfs_handle_t);
+extern int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+extern int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+extern int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+extern void              pcibr_rrb_flush(devfs_handle_t);
+
+static int                pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                     pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+extern void              pcibr_clearwidint(bridge_t *);
+extern void              pcibr_setwidint(xtalk_intr_t);
+
+void                     pcibr_init(void);
+int                      pcibr_attach(devfs_handle_t);
+int			 pcibr_detach(devfs_handle_t);
+int                      pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                      pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                      pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                      pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                      pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                     pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+extern int               pcibr_init_ext_ate_ram(bridge_t *);
+extern int               pcibr_ate_alloc(pcibr_soft_t, int);
+extern void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+extern unsigned          ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   		 unsigned *freeze_time_ptr,
+#endif
+						unsigned *cmd_regs);
+extern void              ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+extern void              ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index,
+#if PCIBR_FREEZE_TIME
+	 				bridge_ate_t ate,
+	 				int ate_total,
+	 				unsigned freeze_time_start,
+#endif
+	 				unsigned *cmd_regs,
+	 				unsigned s);
+
+pcibr_info_t             pcibr_info_get(devfs_handle_t);
+
+static iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+static iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+extern bridge_ate_t     pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+extern bridge_ate_p     pcibr_ate_addr(pcibr_soft_t, int);
+static iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+extern unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+extern pcibr_intr_t     pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+extern void             pcibr_intr_free(pcibr_intr_t);
+extern void             pcibr_setpciint(xtalk_intr_t);
+extern int              pcibr_intr_connect(pcibr_intr_t);
+extern void             pcibr_intr_disconnect(pcibr_intr_t);
+
+extern devfs_handle_t     pcibr_intr_cpu_get(pcibr_intr_t);
+extern void             pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+extern void             pcibr_intr_func(intr_arg_t);
+
+extern void             print_bridge_errcmd(uint32_t, char *);
+
+extern void             pcibr_error_dump(pcibr_soft_t);
+extern uint32_t         pcibr_errintr_group(uint32_t);
+extern void	        pcibr_pioerr_check(pcibr_soft_t);
+extern void             pcibr_error_intr_handler(intr_arg_t);
+
+extern int              pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
+extern void             pcibr_error_cleanup(pcibr_soft_t, int);
+extern void                    pcibr_device_disable(pcibr_soft_t, int);
+extern int              pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_devenable(devfs_handle_t, int);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+extern cfg_p            pcibr_config_addr(devfs_handle_t, unsigned);
+extern uint64_t         pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+extern void             pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+extern void             do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+extern pcibr_hints_t    pcibr_hints_get(devfs_handle_t, int);
+extern void             pcibr_hints_fix_rrbs(devfs_handle_t);
+extern void             pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+extern void	 	pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+extern void             pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+extern void             pcibr_hints_handsoff(devfs_handle_t);
+extern void             pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+#ifdef BRIDGE_B_DATACORR_WAR
+extern int              ql_bridge_rev_b_war(devfs_handle_t);
+extern int              bridge_rev_b_data_check_disable;
+char                   *rev_b_datacorr_warning =
+"***************************** WARNING! ******************************\n";
+char                   *rev_b_datacorr_mesg =
+"UNRECOVERABLE IO LINK ERROR. CONTACT SERVICE PROVIDER\n";
+#endif
+
+extern int		pcibr_slot_reset(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_call_device_attach(devfs_handle_t, pciio_slot_t, int);
+extern int		pcibr_slot_call_device_detach(devfs_handle_t, pciio_slot_t, int);
+extern int              pcibr_slot_attach(devfs_handle_t, pciio_slot_t, int, char *, int *);
+extern int              pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+extern int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+
+#ifdef LATER
+extern int		pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif
+
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_initial_rrb(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+
+
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+static int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+static void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_STARTUP:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_startup(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_shutdown(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+/* pfg - this is new ..... */
+    /* Set PCI bus number */
+    pcibr_info->f_bus = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+
+/* FIXME:  for now this is needed by both pcibr.c and
+ * pcibr_slot.c.  Need to find a better way, the least
+ * of which would be to move it to pcibr_private.h
+ */
+
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int                  count_vchan0, count_vchan1;
+    unsigned             s;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /*
+     * If the RRB configuration for this slot has changed, set it 
+     * back to the boot-time default
+     */
+    if (pcibr_soft->bs_rrb_valid_dflt[slot] >= 0) {
+
+        s = pcibr_lock(pcibr_soft);
+
+        /* Free the rrbs allocated to this slot */
+        error_call = do_pcibr_rrb_free(bridge, slot, 
+		                       pcibr_soft->bs_rrb_valid[slot] +
+		                       pcibr_soft->bs_rrb_valid[slot + 
+                                       PCIBR_RRB_SLOT_VIRTUAL]);
+
+        if (error_call)
+            error = ERANGE;
+   
+         pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot +
+                                        PCIBR_RRB_SLOT_VIRTUAL];
+
+        count_vchan0 = pcibr_soft->bs_rrb_valid_dflt[slot];
+        count_vchan1 = pcibr_soft->bs_rrb_valid_dflt[slot +
+                                                     PCIBR_RRB_SLOT_VIRTUAL];
+
+        pcibr_unlock(pcibr_soft, s);
+
+        pcibr_rrb_alloc(pconn_vhdl, &count_vchan0, &count_vchan1);
+
+    }
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/*
+ * pcibr_driver_reg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being registered.  The device's connection vertex
+ *      and the driver's attach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_reg_callback(devfs_handle_t pconn_vhdl,
+			  int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/*
+ * pcibr_driver_unreg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being unregistered.  The device's connection vertex
+ *      and the driver's detach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_unreg_callback(devfs_handle_t pconn_vhdl, 
+                            int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+#ifdef BRINGUP
+    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
+	NeedXbridgeSwap = 1;
+#endif
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++) {
+	    bridge->b_int_ate_ram[entry].wr = 0;
+	}
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+static iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+static iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+#ifdef IRIX
+    NEWf(pcibr_dmamap, flags);
+#else
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+#endif
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+	DEL(pcibr_dmamap);
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+	DEL(pcibr_dmamap);
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+    DEL(pcibr_dmamap);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#endif
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+static iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,1738 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern int	hubii_check_widget_disabled(nasid_t, int);
+
+/* =====================================================================
+ *    ERROR HANDLING
+ */
+
+#ifdef	DEBUG
+#ifdef	ERROR_DEBUG
+#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
+#else
+#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
+#endif
+#else
+#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
+#endif
+
+#ifdef  DEBUG
+#ifdef ERROR_DEBUG
+bridgereg_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK;
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP;
+#endif
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL |
+                                BRIDGE_ISR_PCIBUS_PIOERR;
+#endif
+
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+/* FIXME: can these arrays be local ? */
+
+#ifdef LATER
+
+struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+
+#define F(s,n)          { 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+#define	device_desc	device_bits
+struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+
+#endif	/* LATER */
+
+void
+print_bridge_errcmd(uint32_t cmdword, char *errtype)
+{
+    printk(
+	    "\t    Bridge %s Error Command Word Register %R\n",
+	    errtype, cmdword, xio_cmd_bits);
+}
+
+char             *pcibr_isr_errs[] =
+{
+    "", "", "", "", "", "", "", "",
+    "08: GIO non-contiguous byte enable in crosstalk packet",
+    "09: PCI to Crosstalk read request timeout",
+    "10: PCI retry operation count exhausted.",
+    "11: PCI bus device select timeout",
+    "12: PCI device reported parity error",
+    "13: PCI Address/Cmd parity error ",
+    "14: PCI Bridge detected parity error",
+    "15: PCI abort condition",
+    "16: SSRAM parity error",
+    "17: LLP Transmitter Retry count wrapped",
+    "18: LLP Transmitter side required Retry",
+    "19: LLP Receiver retry count wrapped",
+    "20: LLP Receiver check bit error",
+    "21: LLP Receiver sequence number error",
+    "22: Request packet overflow",
+    "23: Request operation not supported by bridge",
+    "24: Request packet has invalid address for bridge widget",
+    "25: Incoming request xtalk command word error bit set or invalid sideband",
+    "26: Incoming response xtalk command word error bit set or invalid sideband",
+    "27: Framing error, request cmd data size does not match actual",
+    "28: Framing error, response cmd data size does not match actual",
+    "29: Unexpected response arrived",
+    "30: PMU Access Fault",
+    "31: Multiple errors occurred",
+};
+
+#define BEM_ADD_STR(s)  printk("%s", (s))
+#define BEM_ADD_VAR(v)  printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)  printk("\t%20s: %R\n", #r, (r), r ## _desc)
+#define BEM_ADD_NSPC(n,s)       printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)          BEM_ADD_NSPC(#s, s)
+
+/*
+ * display memory directory state
+ */
+void
+pcibr_show_dir_state(paddr_t paddr, char *prefix)
+{
+	int state;
+	uint64_t vec_ptr;
+	hubreg_t elo;
+	extern char *dir_state_str[];
+	extern void get_dir_ent(paddr_t, int *, uint64_t *, hubreg_t *);
+
+	get_dir_ent(paddr, &state, &vec_ptr, &elo);
+
+	printf("%saddr 0x%x: state 0x%x owner 0x%x (%s)\n", 
+		prefix, paddr, state, vec_ptr, dir_state_str[state]);
+}
+
+
+/*
+ *	Dump relevant error information for Bridge error interrupts.
+ */
+/*ARGSUSED */
+void
+pcibr_error_dump(pcibr_soft_t pcibr_soft)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             int_status;
+    bridgereg_t             mult_int;
+    int			    bit;
+    int                     i;
+    char		    *reg_desc;
+    paddr_t		    addr;
+
+    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
+    if (!int_status) {
+	/* No error bits set */
+	return;
+    }
+
+    /* Check if dumping the same error information multiple times */
+    if (test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat,
+	    int_status) == int_status) {
+	return;
+    }
+
+    printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%X for %s\n"
+	"    Dumping relevant %sBridge registers for each bit set...\n",
+	    int_status, pcibr_soft->bs_name,
+	    (is_xbridge(bridge) ? "X" : ""));
+
+    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	bit = 1 << i;
+
+	/*
+	 * A number of int_status bits are only defined for Bridge.
+	 * Ignore them in the case of an XBridge.
+	 */
+	if (is_xbridge(bridge) && ((bit == BRIDGE_ISR_MULTI_ERR) ||
+		(bit == BRIDGE_ISR_SSRAM_PERR) ||
+		(bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) {
+	    continue;
+	}
+
+	if (int_status & bit) {
+	    printk("\t%s\n", pcibr_isr_errs[i]);
+
+	    switch (bit) {
+	    case BRIDGE_ISR_PAGE_FAULT:		/* PMU_PAGE_FAULT  (XBridge) */
+/*	    case BRIDGE_ISR_PMU_ESIZE_FAULT:	   PMU_ESIZE_FAULT (Bridge) */
+		if (is_xbridge(bridge))
+		    reg_desc = "Map Fault Address";
+		else
+		    reg_desc = "SSRAM Parity Error";
+
+		printk("\t    %s Register: 0x%x\n", reg_desc,
+		    bridge->b_ram_perr_or_map_fault);
+		break;
+
+	    case BRIDGE_ISR_UNEXP_RESP:		/* UNEXPECTED_RESP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
+		break;
+
+	    case BRIDGE_ISR_BAD_XRESP_PKT:		/* BAD_RESP_PACKET */
+	    case BRIDGE_ISR_RESP_XTLK_ERR:		/* RESP_XTALK_ERROR */
+	    case BRIDGE_ISR_XREAD_REQ_TIMEOUT:		/* XREAD_REQ_TOUT */
+
+		addr = (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32)
+			| bridge->b_wid_resp_lower);
+		printk(
+		    "\t    Bridge Response Buffer Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Response Buffer Error Lower Address Register: 0x%x\n"
+		    "\t    dev-num %d buff-num %d addr 0x%x\n",
+		    bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
+		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
+		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
+		    addr);
+		if (bit == BRIDGE_ISR_RESP_XTLK_ERR) {
+			/* display memory directory associated with cacheline */
+			pcibr_show_dir_state(addr, "\t    ");
+		}
+		break;
+
+	    case BRIDGE_ISR_BAD_XREQ_PKT:		/* BAD_XREQ_PACKET */
+	    case BRIDGE_ISR_REQ_XTLK_ERR:		/* REQ_XTALK_ERROR */
+	    case BRIDGE_ISR_INVLD_ADDR:			/* INVALID_ADDRESS */
+	    case BRIDGE_ISR_UNSUPPORTED_XOP:		/* UNSUPPORTED_XOP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "");
+		printk("\t    Bridge Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Error Lower Address Register: 0x%x\n"
+		    "\t    Bridge Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_wid_err_upper,
+		    (uint64_t) bridge->b_wid_err_lower,
+		    (((uint64_t) bridge->b_wid_err_upper << 32) |
+		    bridge->b_wid_err_lower));
+		break;
+
+	    case BRIDGE_ISR_SSRAM_PERR:			/* SSRAM_PERR */
+		if (!is_xbridge(bridge)) {	/* only defined on Bridge */
+		    printk(
+			"\t    Bridge SSRAM Parity Error Register: 0x%x\n",
+			bridge->b_ram_perr);
+		}
+		break;
+
+	    case BRIDGE_ISR_PCI_ABORT:			/* PCI_ABORT */
+	    case BRIDGE_ISR_PCI_PARITY:			/* PCI_PARITY */
+	    case BRIDGE_ISR_PCI_SERR:			/* PCI_SERR */
+	    case BRIDGE_ISR_PCI_PERR:			/* PCI_PERR */
+	    case BRIDGE_ISR_PCI_MST_TIMEOUT:		/* PCI_MASTER_TOUT */
+	    case BRIDGE_ISR_PCI_RETRY_CNT:		/* PCI_RETRY_CNT */
+	    case BRIDGE_ISR_GIO_B_ENBL_ERR:		/* GIO BENABLE_ERR */
+		printk("\t    PCI Error Upper Address Register: 0x%x\n"
+		    "\t    PCI Error Lower Address Register: 0x%x\n"
+		    "\t    PCI Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_pci_err_upper,
+		    (uint64_t) bridge->b_pci_err_lower,
+		    (((uint64_t) bridge->b_pci_err_upper << 32) |
+		    bridge->b_pci_err_lower));
+		break;
+	    }
+	}
+    }
+
+    if (is_xbridge(bridge) && (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK)) {
+	mult_int = bridge->b_mult_int;
+	printk("    XBridge Multiple Interrupt Register is 0x%x\n",
+		mult_int);
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	    if (mult_int & (1 << i))
+		printk("\t%s\n", pcibr_isr_errs[i]);
+	    }
+	}
+}
+
+#define PCIBR_ERRINTR_GROUP(error)	\
+		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
+
+uint32_t
+pcibr_errintr_group(uint32_t error)
+{
+    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
+
+    if (error & BRIDGE_IRR_PCI_GRP)
+	group |= BRIDGE_IRR_PCI_GRP_CLR;
+    if (error & BRIDGE_IRR_SSRAM_GRP)
+	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
+    if (error & BRIDGE_IRR_LLP_GRP)
+	group |= BRIDGE_IRR_LLP_GRP_CLR;
+    if (error & BRIDGE_IRR_REQ_DSP_GRP)
+	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
+    if (error & BRIDGE_IRR_RESP_BUF_GRP)
+	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
+    if (error & BRIDGE_IRR_CRP_GRP)
+	group |= BRIDGE_IRR_CRP_GRP_CLR;
+
+    return group;
+
+}
+
+
+/* pcibr_pioerr_check():
+ *	Check to see if this pcibr has a PCI PIO
+ *	TIMEOUT error; if so, bump the timeout-count
+ *	on any piomaps that could cover the address.
+ */
+static void
+pcibr_pioerr_check(pcibr_soft_t soft)
+{
+    bridge_t		   *bridge;
+    bridgereg_t		    b_int_status;
+    bridgereg_t		    b_pci_err_lower;
+    bridgereg_t		    b_pci_err_upper;
+    iopaddr_t		    pci_addr;
+    pciio_slot_t	    slot;
+    pcibr_piomap_t	    map;
+    iopaddr_t		    base;
+    size_t		    size;
+    unsigned		    win;
+    int			    func;
+
+    bridge = soft->bs_base;
+    b_int_status = bridge->b_int_status;
+    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	b_pci_err_lower = bridge->b_pci_err_lower;
+	b_pci_err_upper = bridge->b_pci_err_upper;
+	b_int_status = bridge->b_int_status;
+	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+
+	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
+	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
+
+	    slot = 8;
+	    while (slot-- > 0) {
+		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
+		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
+
+		for (func = 0; func < nfunc; func++) {
+		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
+
+		    if (!pcibr_info)
+			continue;
+
+		    for (map = pcibr_info->f_piomap;
+			 map != NULL; map = map->bp_next) {
+			base = map->bp_pciaddr;
+			size = map->bp_mapsz;
+			win = map->bp_space - PCIIO_SPACE_WIN(0);
+			if (win < 6)
+			    base += 
+				soft->bs_slot[slot].bss_window[win].bssw_base;
+			else if (map->bp_space == PCIIO_SPACE_ROM)
+			    base += pcibr_info->f_rbase;
+			if ((pci_addr >= base) && (pci_addr < (base + size)))
+			    atomicAddInt(map->bp_toc, 1);
+		    }
+		}
+	    }
+	}
+    }
+}
+
+/*
+ * PCI Bridge Error interrupt handler.
+ *      This gets invoked, whenever a PCI bridge sends an error interrupt.
+ *      Primarily this servers two purposes.
+ *              - If an error can be handled (typically a PIO read/write
+ *                error, we try to do it silently.
+ *              - If an error cannot be handled, we die violently.
+ *      Interrupt due to PIO errors:
+ *              - Bridge sends an interrupt, whenever a PCI operation
+ *                done by the bridge as the master fails. Operations could
+ *                be either a PIO read or a PIO write.
+ *                PIO Read operation also triggers a bus error, and it's
+ *                We primarily ignore this interrupt in that context..
+ *                For PIO write errors, this is the only indication.
+ *                and we have to handle with the info from here.
+ *
+ *                So, there is no way to distinguish if an interrupt is
+ *                due to read or write error!.
+ */
+
+
+void
+pcibr_error_intr_handler(intr_arg_t arg)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    bridgereg_t             int_status;
+    bridgereg_t             err_status;
+    int                     i;
+
+    /* REFERENCED */
+    bridgereg_t             disable_errintr_mask = 0;
+    int 		    rv;
+    int 		    error_code = IOECODE_DMA | IOECODE_READ;
+    ioerror_mode_t 	    mode = MODE_DEVERROR;
+    ioerror_t 	            ioe;
+    nasid_t		    nasid;
+
+#if PCIBR_SOFT_LIST
+    {
+	extern pcibr_list_p	pcibr_list;
+	pcibr_list_p            entry;
+
+	entry = pcibr_list;
+	while (1) {
+	    if (entry == NULL) {
+		PRINT_PANIC(
+			"pcibr_error_intr_handler:\n"
+			"\tmy parameter (0x%x) is not a pcibr_soft!",
+			arg);
+	    }
+	    if ((intr_arg_t) entry->bl_soft == arg)
+		break;
+	    entry = entry->bl_next;
+	}
+    }
+#endif
+    pcibr_soft = (pcibr_soft_t) arg;
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * pcibr_error_intr_handler gets invoked whenever bridge encounters
+     * an error situation, and the interrupt for that error is enabled.
+     * This routine decides if the error is fatal or not, and takes
+     * action accordingly.
+     *
+     * In the case of PIO read/write timeouts, there is no way
+     * to know if it was a read or write request that timed out.
+     * If the error was due to a "read", a bus error will also occur
+     * and the bus error handling code takes care of it. 
+     * If the error is due to a "write", the error is currently logged 
+     * by this routine. For SN1 and SN0, if fire-and-forget mode is 
+     * disabled, a write error response xtalk packet will be sent to 
+     * the II, which will cause an II error interrupt. No write error 
+     * recovery actions of any kind currently take place at the pcibr 
+     * layer! (e.g., no panic on unrecovered write error)
+     *
+     * Prior to reading the Bridge int_status register we need to ensure
+     * that there are no error bits set in the lower layers (hubii)
+     * that have disabled PIO access to the widget. If so, there is nothing
+     * we can do until the bits clear, so we setup a timeout and try again
+     * later.
+     */
+
+    nasid = NASID_GET(bridge);
+    if (hubii_check_widget_disabled(nasid, pcibr_soft->bs_xid)) {
+	timeout(pcibr_error_intr_handler, pcibr_soft, BRIDGE_PIOERR_TIMEOUT);
+	pcibr_soft->bs_errinfo.bserr_toutcnt++;
+	return;
+    }
+
+    /* int_status is which bits we have to clear;
+     * err_status is the bits we haven't handled yet.
+     */
+
+    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
+    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
+
+    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
+	/*
+	 * No error bit set!!.
+	 */
+	return;
+    }
+    /*
+     * If we have a PCIBUS_PIOERR, hand it to the logger.
+     */
+    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	pcibr_pioerr_check(pcibr_soft);
+    }
+
+    if (err_status) {
+	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
+
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
+	    if (err_status & (1 << i)) {
+		uint32_t              errrate = 0;
+		uint32_t              errcount = 0;
+		uint32_t              errinterval = 0, current_tick = 0;
+		int                     llp_tx_retry_errors = 0;
+		int                     is_llp_tx_retry_intr = 0;
+
+		bs_estat->bs_errcount_total++;
+
+		current_tick = lbolt;
+		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
+		errcount = (bs_estat->bs_errcount_total -
+			    bs_estat->bs_lasterr_snapshot);
+
+		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
+
+		/* Check for the divide by zero condition while
+		 * calculating the error rates.
+		 */
+
+		if (errinterval) {
+		    errrate = errcount / errinterval;
+		    /* If able to calculate error rate
+		     * on a LLP transmitter retry interrupt, check
+		     * if the error rate is nonzero and we have seen
+		     * a certain minimum number of errors.
+		     *
+		     * NOTE : errcount is being compared to
+		     * PCIBR_ERRTIME_THRESHOLD to make sure that we are not
+		     * seeing cases like x error interrupts per y ticks for
+		     * very low x ,y (x > y ) which could result in a
+		     * rate > 100/tick.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			errrate &&
+			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
+			llp_tx_retry_errors = 1;
+		    }
+		} else {
+		    errrate = 0;
+		    /* Since we are not able to calculate the
+		     * error rate check if we exceeded a certain
+		     * minimum number of errors for LLP transmitter
+		     * retries. Note that this can only happen
+		     * within the first tick after the last snapshot.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
+			llp_tx_retry_errors = 1;
+		    }
+		}
+
+		/*
+		 * If a non-zero error rate (which is equivalent to
+		 * to 100 errors/tick at least) for the LLP transmitter
+		 * retry interrupt was seen, check if we should print
+		 * a warning message.
+		 */
+
+		if (llp_tx_retry_errors) {
+		    static uint32_t       last_printed_rate;
+
+		    if (errrate > last_printed_rate) {
+			last_printed_rate = errrate;
+			/* Print the warning only if the error rate
+			 * for the transmitter retry interrupt
+			 * exceeded the previously printed rate.
+			 */
+			printk(KERN_WARNING
+				"%s: %s, Excessive error interrupts : %d/tick\n",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+
+		    }
+		    /*
+		     * Update snapshot, and time
+		     */
+		    bs_estat->bs_lasterr_timestamp = current_tick;
+		    bs_estat->bs_lasterr_snapshot =
+			bs_estat->bs_errcount_total;
+
+		}
+		/*
+		 * If the error rate is high enough, print the error rate.
+		 */
+		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
+
+		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
+			printk(KERN_NOTICE "%s: %s, Error rate %d/tick",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+			/*
+			 * Update snapshot, and time
+			 */
+			bs_estat->bs_lasterr_timestamp = current_tick;
+			bs_estat->bs_lasterr_snapshot =
+			    bs_estat->bs_errcount_total;
+		    }
+		}
+		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
+		    /*
+		     * We have seen a fairly large number of errors of
+		     * this type. Let's disable the interrupt. But flash
+		     * a message about the interrupt being disabled.
+		     */
+		    printk(KERN_NOTICE
+			    "%s Disabling error interrupt type %s. Error count %d",
+			    pcibr_soft->bs_name,
+			    pcibr_isr_errs[i],
+			    bs_estat->bs_errcount_total);
+		    disable_errintr_mask |= (1 << i);
+		}
+	    }
+	}
+    }
+
+    if (disable_errintr_mask) {
+	/*
+	 * Disable some high frequency errors as they
+	 * could eat up too much cpu time.
+	 */
+	bridge->b_int_enable &= ~disable_errintr_mask;
+    }
+    /*
+     * If we leave the PROM cacheable, T5 might
+     * try to do a cache line sized writeback to it,
+     * which will cause a BRIDGE_ISR_INVLD_ADDR.
+     */
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	(0x00000000 == bridge->b_wid_err_upper) &&
+	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
+	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#if defined (PCIBR_LLP_CONTROL_WAR)
+    /*
+     * The bridge bug, where the llp_config or control registers
+     * need to be read back after being written, affects an MP
+     * system since there could be small windows between writing
+     * the register and reading it back on one cpu while another
+     * cpu is fielding an interrupt. If we run into this scenario,
+     * workaround the problem by ignoring the error. (bug 454474)
+     * pcibr_llp_control_war_cnt keeps an approximate number of
+     * times we saw this problem on a system.
+     */
+
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
+	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
+#if 0
+	if (kdebug)
+	    printk(KERN_NOTICE "%s bridge: ignoring llp/control address interrupt",
+		    pcibr_soft->bs_name);
+#endif
+	pcibr_llp_control_war_cnt++;
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+#ifdef EHE_ENABLE
+    /* Check if this is the RESP_XTALK_ERROR interrupt. 
+     * This can happen due to a failed DMA READ operation.
+     */
+    if (err_status & BRIDGE_ISR_RESP_XTLK_ERR) {
+	/* Phase 1 : Look at the error state in the bridge and further
+	 * down in the device layers.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_LOOKUP);
+	IOERROR_SETVALUE(&ioe, widgetnum, pcibr_soft->bs_xid);
+	(void)pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				  error_code,
+				  mode,
+				  &ioe);
+	/* Phase 2 : Perform the action agreed upon in phase 1.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_ACTION);
+	rv = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				 error_code,
+				 mode,
+				 &ioe);
+    }
+    if (rv != IOERROR_HANDLED) {
+#endif /* EHE_ENABLE */
+
+    /* Dump/Log Bridge error interrupt info */
+    if (err_status & bridge_errors_to_dump) {
+	printk("BRIDGE ERR_STATUS 0x%x\n", err_status);
+	pcibr_error_dump(pcibr_soft);
+    }
+
+    if (err_status & BRIDGE_ISR_ERROR_FATAL) {
+	machine_error_dump("");
+	cmn_err_tag(14, CE_PANIC, "PCI Bridge Error interrupt killed the system");
+	    /*NOTREACHED */
+    }
+
+#ifdef EHE_ENABLE
+    }
+#endif
+
+    /*
+     * We can't return without re-enabling the interrupt, since
+     * it would cause problems for devices like IOC3 (Lost
+     * interrupts ?.). So, just cleanup the interrupt, and
+     * use saved values later..
+     */
+    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
+
+    /* Zero out bserr_intstat field */
+    test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat, 0);
+}
+
+/*
+ * pcibr_addr_toslot
+ *      Given the 'pciaddr' find out which slot this address is
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      function number, space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ */
+int
+pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
+		  iopaddr_t pciaddr,
+		  pciio_space_t *spacep,
+		  iopaddr_t *offsetp,
+		  pciio_function_t *funcp)
+{
+    int                     s, f, w;
+    iopaddr_t               base;
+    size_t                  size;
+    pciio_piospace_t        piosp;
+
+    /*
+     * Check if the address is in config space
+     */
+
+    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
+
+	if (pciaddr >= BRIDGE_CONFIG1_BASE)
+	    pciaddr -= BRIDGE_CONFIG1_BASE;
+	else
+	    pciaddr -= BRIDGE_CONFIG_BASE;
+
+	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
+	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
+
+	if (funcp) {
+	    f = pciaddr / 0x100;
+	    pciaddr %= 0x100;
+	}
+	if (spacep)
+	    *spacep = PCIIO_SPACE_CFG;
+	if (offsetp)
+	    *offsetp = pciaddr;
+	if (funcp)
+	    *funcp = f;
+
+	return s;
+    }
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    for (w = 0; w < 6; w++) {
+		if (pcibr_info->f_window[w].w_space
+		    == PCIIO_SPACE_NONE) {
+		    continue;
+		}
+		base = pcibr_info->f_window[w].w_base;
+		size = pcibr_info->f_window[w].w_size;
+
+		if ((pciaddr >= base) && (pciaddr < (base + size))) {
+		    if (spacep)
+			*spacep = PCIIO_SPACE_WIN(w);
+		    if (offsetp)
+			*offsetp = pciaddr - base;
+		    if (funcp)
+			*funcp = f;
+		    return s;
+		}			/* endif match */
+	    }				/* next window */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Check if the address was allocated as part of the
+     * pcibr_piospace_alloc calls.
+     */
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    piosp = pcibr_info->f_piospace;
+	    while (piosp) {
+		if ((piosp->start <= pciaddr) &&
+		    ((piosp->count + piosp->start) > pciaddr)) {
+		    if (spacep)
+			*spacep = piosp->space;
+		    if (offsetp)
+			*offsetp = pciaddr - piosp->start;
+		    return s;
+		}			/* endif match */
+		piosp = piosp->next;
+	    }				/* next piosp */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Some other random address on the PCI bus ...
+     * we have no way of knowing whether this was
+     * a MEM or I/O access; so, for now, we just
+     * assume that the low 1G is MEM, the next
+     * 3G is I/O, and anything above the 4G limit
+     * is obviously MEM.
+     */
+
+    if (spacep)
+	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
+		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
+		   PCIIO_SPACE_MEM);
+    if (offsetp)
+	*offsetp = pciaddr;
+
+    return PCIIO_SLOT_NONE;
+
+}
+
+void
+pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    ASSERT(error_code & IOECODE_PIO);
+    error_code = error_code;
+
+    bridge->b_int_rst_stat =
+	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
+    (void) bridge->b_wid_tflush;	/* flushbus */
+}
+
+/*
+ * pcibr_error_extract
+ *      Given the 'pcibr vertex handle' find out which slot
+ *      the bridge status error address (from pcibr_soft info
+ *      hanging off the vertex)
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ *
+ * XXX- this interface has no way to return the function
+ * number on a multifunction card, even though that data
+ * is available.
+ */
+
+pciio_slot_t
+pcibr_error_extract(devfs_handle_t pcibr_vhdl,
+		    pciio_space_t *spacep,
+		    iopaddr_t *offsetp)
+{
+    pcibr_soft_t            pcibr_soft = 0;
+    iopaddr_t               bserr_addr;
+    bridge_t               *bridge;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+    arbitrary_info_t	    rev;
+
+    /* Do a sanity check as to whether we really got a 
+     * bridge vertex handle.
+     */
+    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
+	GRAPH_SUCCESS) 
+	return(slot);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (pcibr_soft) {
+	bridge = pcibr_soft->bs_base;
+	bserr_addr =
+	    bridge->b_pci_err_lower |
+	    ((uint64_t) (bridge->b_pci_err_upper &
+			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
+
+	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
+				 spacep, offsetp, NULL);
+    }
+    return slot;
+}
+
+/*ARGSUSED */
+void
+pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
+{
+    /*
+     * XXX
+     * Device failed to handle error. Take steps to
+     * disable this device ? HOW TO DO IT ?
+     *
+     * If there are any Read response buffers associated
+     * with this device, it's time to get them back!!
+     *
+     * We can disassociate any interrupt level associated
+     * with this device, and disable that interrupt level
+     *
+     * For now it's just a place holder
+     */
+}
+
+/*
+ * pcibr_pioerror
+ *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
+ *
+ *      Queries the Bus interface attached to see if the device driver
+ *      mapping the device-number that caused error can handle the
+ *      situation. If so, it will clean up any error, and return
+ *      indicating the error was handled. If the device driver is unable
+ *      to handle the error, it expects the bus-interface to disable that
+ *      device, and takes any steps needed here to take away any resources
+ *      associated with this device.
+ */
+
+#define BEM_ADD_STR(s)	printk("%s", (s))
+#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
+
+#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
+
+/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
+ * decodes the PCI specific portions -- we count on our
+ * callers to dump the raw IOE data.
+ */
+#define BEM_ADD_IOE(ioe)						\
+	do {								\
+	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
+		unsigned		spc;				\
+		unsigned		win;				\
+									\
+		spc = IOERROR_GETVALUE(ioe, busspace);			\
+		win = spc - PCIIO_SPACE_WIN(0);				\
+									\
+		switch (spc) {						\
+		case PCIIO_SPACE_CFG:					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_IO:					\
+		    printk(					\
+			    "\tPCI I/O space  Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_MEM:					\
+		case PCIIO_SPACE_MEM32:					\
+		case PCIIO_SPACE_MEM64:					\
+		    printk(					\
+			    "\tPCI MEM space Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		default:						\
+		    if (win < 6) {					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    win,					\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    }							\
+		    break;						\
+		}							\
+	    }								\
+	} while (0)
+
+/*ARGSUSED */
+int
+pcibr_pioerror(
+		  pcibr_soft_t pcibr_soft,
+		  int error_code,
+		  ioerror_mode_t mode,
+		  ioerror_t *ioe)
+{
+    int                     retval = IOERROR_HANDLED;
+
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    iopaddr_t               bad_xaddr;
+
+    pciio_space_t           raw_space;	/* raw PCI space */
+    iopaddr_t               raw_paddr;	/* raw PCI address */
+
+    pciio_space_t           space;	/* final PCI space */
+    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
+    pciio_function_t        func;	/* final PCI func, if appropriate */
+    iopaddr_t               offset;	/* final PCI offset */
+    
+    int                     cs, cw, cf;
+    pciio_space_t           wx;
+    iopaddr_t               wb;
+    size_t                  ws;
+    iopaddr_t               wl;
+
+
+    /*
+     * We expect to have an "xtalkaddr" coming in,
+     * and need to construct the slot/space/offset.
+     */
+
+    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
+
+    slot = PCIIO_SLOT_NONE;
+    func = PCIIO_FUNC_NONE;
+    raw_space = PCIIO_SPACE_NONE;
+    raw_paddr = 0;
+
+    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
+	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
+	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
+	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
+	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
+	/* Type 1 config space:
+	 * slot and function numbers not known.
+	 * Perhaps we can read them back?
+	 */
+	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
+	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
+	int                     x;
+
+	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
+	x = raw_paddr / BRIDGE_DEVIO_OFF;
+	raw_paddr %= BRIDGE_DEVIO_OFF;
+	/* first two devio windows are double-sized */
+	if ((x == 1) || (x == 3))
+	    raw_paddr += BRIDGE_DEVIO_OFF;
+	if (x > 0)
+	    x--;
+	if (x > 1)
+	    x--;
+	/* x is which devio reg; no guarantee
+	 * PCI slot x will be responding.
+	 * still need to figure out who decodes
+	 * space/offset on the bus.
+	 */
+	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
+	if (raw_space == PCIIO_SPACE_NONE) {
+	    /* Someone got an error because they
+	     * accessed the PCI bus via a DevIO(x)
+	     * window that pcibr has not yet assigned
+	     * to any specific PCI address. It is
+	     * quite possible that the Device(x)
+	     * register has been changed since they
+	     * made their access, but we will give it
+	     * our best decode shot.
+	     */
+	    raw_space = pcibr_soft->bs_slot[x].bss_device
+		& BRIDGE_DEV_DEV_IO_MEM
+		? PCIIO_SPACE_MEM
+		: PCIIO_SPACE_IO;
+	    raw_paddr +=
+		(pcibr_soft->bs_slot[x].bss_device &
+		 BRIDGE_DEV_OFF_MASK) <<
+		BRIDGE_DEV_OFF_ADDR_SHFT;
+	} else
+	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM32;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM64;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
+	raw_space = PCIIO_SPACE_IO;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
+    }
+    space = raw_space;
+    offset = raw_paddr;
+
+    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
+	/* we've got a space/offset but not which
+	 * PCI slot decodes it. Check through our
+	 * notions of which devices decode where.
+	 *
+	 * Yes, this "duplicates" some logic in
+	 * pcibr_addr_toslot; the difference is,
+	 * this code knows which space we are in,
+	 * and can really really tell what is
+	 * going on (no guessing).
+	 */
+
+	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
+	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
+		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
+
+		if (!pcibr_info)
+		    continue;
+		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
+		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
+			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
+			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
+			((wl = wb + ws) > wb) &&
+			((wb <= offset) && (wl > offset))) {
+			/* MEM, MEM32 and MEM64 need to
+			 * compare as equal ...
+			 */
+			if ((wx == space) ||
+			    (((wx == PCIIO_SPACE_MEM) ||
+			      (wx == PCIIO_SPACE_MEM32) ||
+			      (wx == PCIIO_SPACE_MEM64)) &&
+			     ((space == PCIIO_SPACE_MEM) ||
+			      (space == PCIIO_SPACE_MEM32) ||
+			      (space == PCIIO_SPACE_MEM64)))) {
+			    slot = cs;
+			    func = cf;
+			    space = PCIIO_SPACE_WIN(cw);
+			    offset -= wb;
+			}		/* endif window space match */
+		    }			/* endif window valid and addr match */
+		}			/* next window unless slot set */
+	    }				/* next func unless slot set */
+	}				/* next slot unless slot set */
+	/* XXX- if slot is still -1, no PCI devices are
+	 * decoding here using their standard PCI BASE
+	 * registers. This would be a really good place
+	 * to cross-coordinate with the pciio PCI
+	 * address space allocation routines, to find
+	 * out if this address is "allocated" by any of
+	 * our subsidiary devices.
+	 */
+    }
+    /* Scan all piomap records on this PCI bus to update
+     * the TimeOut Counters on all matching maps. If we
+     * don't already know the slot number, take it from
+     * the first matching piomap. Note that we have to
+     * compare maps against raw_space and raw_paddr
+     * since space and offset could already be
+     * window-relative.
+     *
+     * There is a chance that one CPU could update
+     * through this path, and another CPU could also
+     * update due to an interrupt. Closing this hole
+     * would only result in the possibility of some
+     * errors never getting logged at all, and since the
+     * use for bp_toc is as a logical test rather than a
+     * strict count, the excess counts are not a
+     * problem.
+     */
+    for (cs = 0; cs < 8; ++cs) {
+	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	for (cf = 0; cf < nf; cf++) {
+	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
+	    pcibr_piomap_t	map;    
+
+	    if (!pcibr_info)
+		continue;
+
+	    for (map = pcibr_info->f_piomap;
+	     map != NULL; map = map->bp_next) {
+	    wx = map->bp_space;
+	    wb = map->bp_pciaddr;
+	    ws = map->bp_mapsz;
+	    cw = wx - PCIIO_SPACE_WIN(0);
+	    if (cw < 6) {
+		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
+	    }
+	    if (wx == PCIIO_SPACE_ROM) {
+		wb += pcibr_info->f_rbase;
+		wx = PCIIO_SPACE_MEM;
+	    }
+	    if ((wx == PCIIO_SPACE_MEM32) ||
+		(wx == PCIIO_SPACE_MEM64))
+		wx = PCIIO_SPACE_MEM;
+	    wl = wb + ws;
+	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
+		atomicAddInt(map->bp_toc, 1);
+		if (slot == PCIIO_SLOT_NONE) {
+		    slot = cs;
+		    space = map->bp_space;
+		    if (cw < 6)
+			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		}
+	    }
+	    }
+	}
+    }
+
+    if (space != PCIIO_SPACE_NONE) {
+	if (slot != PCIIO_SLOT_NONE) 
+	    if (func != PCIIO_FUNC_NONE)
+		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,func));
+	    else
+    		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,0));
+
+	IOERROR_SETVALUE(ioe, busspace, space);
+	IOERROR_SETVALUE(ioe, busaddr, offset);
+    }
+    if (mode == MODE_DEVPROBE) {
+	/*
+	 * During probing, we don't really care what the
+	 * error is. Clean up the error in Bridge, notify
+	 * subsidiary devices, and return success.
+	 */
+	pcibr_error_cleanup(pcibr_soft, error_code);
+
+	/* if appropriate, give the error handler for this slot
+	 * a shot at this probe access as well.
+	 */
+	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
+	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    }
+    /*
+     * If we don't know what "PCI SPACE" the access
+     * was targeting, we may have problems at the
+     * Bridge itself. Don't touch any bridge registers,
+     * and do complain loudly.
+     */
+
+    if (space == PCIIO_SPACE_NONE) {
+	printk("XIO Bus Error at %s\n"
+		"\taccess to XIO bus offset 0x%x\n"
+		"\tdoes not correspond to any PCI address\n",
+		pcibr_soft->bs_name, bad_xaddr);
+
+	/* caller will dump contents of ioe struct */
+	return IOERROR_XTALKLEVEL;
+    }
+
+    /*
+     * Actual PCI Error handling situation.
+     * Typically happens when a user level process accesses
+     * PCI space, and it causes some error.
+     *
+     * Due to PCI Bridge implementation, we get two indication
+     * for a read error: an interrupt and a Bus error.
+     * We like to handle read error in the bus error context.
+     * But the interrupt comes and goes before bus error
+     * could make much progress. (NOTE: interrupd does
+     * come in _after_ bus error processing starts. But it's
+     * completed by the time bus error code reaches PCI PIO
+     * error handling.
+     * Similarly write error results in just an interrupt,
+     * and error handling has to be done at interrupt level.
+     * There is no way to distinguish at interrupt time, if an
+     * error interrupt is due to read/write error..
+     */
+
+    /* We know the xtalk addr, the raw PCI bus space,
+     * the raw PCI bus address, the decoded PCI bus
+     * space, the offset within that space, and the
+     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
+     * is known to be involved).
+     */
+
+    /*
+     * Hand the error off to the handler registered
+     * for the slot that should have decoded the error,
+     * or to generic PCI handling (if pciio decides that
+     * such is appropriate).
+     */
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+
+	/* Generate a generic message for IOERROR_UNHANDLED
+	 * since the subsidiary handlers were silent, and
+	 * did no recovery.
+	 */
+	if (retval == IOERROR_UNHANDLED) {
+	    retval = IOERROR_PANIC;
+
+	    /* we may or may not want to print some of this,
+	     * depending on debug level and which error code.
+	     */
+
+	    printk(KERN_ALERT
+		    "PIO Error on PCI Bus %s",
+		    pcibr_soft->bs_name);
+	    /* this decodes part of the ioe; our caller
+	     * will dump the raw details in DEBUG and
+	     * kdebug kernels.
+	     */
+	    BEM_ADD_IOE(ioe);
+	}
+#if defined(FORCE_ERRORS)
+	if (0) {
+#elif !DEBUG
+	if (kdebug) {
+#endif
+	    /*
+	     * Dump raw data from Bridge/PCI layer.
+	     */
+
+	    BEM_ADD_STR("Raw info from Bridge/PCI layer:\n");
+	    if (bridge->b_int_status & BRIDGE_ISR_PCIBUS_PIOERR)
+		pcibr_error_dump(pcibr_soft);
+	    BEM_ADD_SPC(raw_space);
+	    BEM_ADD_VAR(raw_paddr);
+	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
+
+		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		if (slot < 8) {
+		    bridgereg_t             device = bridge->b_device[slot].reg;
+
+		    BEM_ADD_VAR(slot);
+		    BEM_ADD_VAR(func);
+		    BEM_ADD_REG(device);
+		}
+	    }
+#if !DEBUG || defined(FORCE_ERRORS)
+	}
+#endif
+
+	/*
+	 * Since error could not be handled at lower level,
+	 * error data logged has not  been cleared.
+	 * Clean up errors, and
+	 * re-enable bridge to interrupt on error conditions.
+	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
+	 * dependent on INT_ENABLE register. This write just makes sure
+	 * that if the interrupt was enabled, we do get the interrupt.
+	 *
+	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
+	 *      a group of interrupts. If while handling this error,
+	 *      some other error has occured, that would be
+	 *      implicitly cleared by this write.
+	 *      Need a way to ensure we don't inadvertently clear some
+	 *      other errors.
+	 */
+	if (IOERROR_FIELDVALID(ioe, widgetdev))
+	    pcibr_device_disable(pcibr_soft, 
+				 pciio_widgetdev_slot_get(
+					  IOERROR_GETVALUE(ioe, widgetdev)));
+
+	if (mode == MODE_DEVUSERERROR)
+	    pcibr_error_cleanup(pcibr_soft, error_code);
+    }
+    return retval;
+}
+
+/*
+ * bridge_dmaerror
+ *      Some error was identified in a DMA transaction.
+ *      This routine will identify the <device, address> that caused the error,
+ *      and try to invoke the appropriate bus service to handle this.
+ */
+
+#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+
+int
+pcibr_dmard_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             bus_lowaddr, bus_uppraddr;
+    int                     retval = 0;
+    int                     bufnum;
+
+    /*
+     * In case of DMA errors, bridge should have logged the
+     * address that caused the error.
+     * Look up the address, in the bridge error registers, and
+     * take appropriate action
+     */
+    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
+    ASSERT(bridge);
+
+    /*
+     * read error log registers
+     */
+    bus_lowaddr = bridge->b_wid_resp_lower;
+    bus_uppraddr = bridge->b_wid_resp_upper;
+
+    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
+    IOERROR_SETVALUE(ioe, widgetdev, 
+		     pciio_widgetdev_create(
+				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
+				    0));
+    IOERROR_SETVALUE(ioe, busaddr,
+		     (bus_lowaddr |
+		      ((iopaddr_t)
+		       (bus_uppraddr &
+			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
+
+    /*
+     * need to ensure that the xtalk adress in ioe
+     * maps to PCI error address read from bridge.
+     * How to convert PCI address back to Xtalk address ?
+     * (better idea: convert XTalk address to PCI address
+     * and then do the compare!)
+     */
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    if (retval != IOERROR_HANDLED)
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe,widgetdev)));
+
+    /*
+     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
+     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
+     * not is dependent on INT_ENABLE register. This write just makes sure
+     * that if the interrupt was enabled, we do get the interrupt.
+     */
+    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
+
+    /*
+     * Also, release the "bufnum" back to buffer pool that could be re-used.
+     * This is done by "disabling" the buffer for a moment, then restoring
+     * the original assignment.
+     */
+
+    {
+	reg_p                   regp;
+	bridgereg_t             regv;
+	bridgereg_t             mask;
+
+	regp = (bufnum & 1)
+	    ? &bridge->b_odd_resp
+	    : &bridge->b_even_resp;
+
+	mask = 0xF << ((bufnum >> 1) * 4);
+
+	regv = *regp;
+	*regp = regv & ~mask;
+	*regp = regv;
+    }
+
+    return retval;
+}
+
+/*
+ * pcibr_dmawr_error:
+ *      Handle a dma write error caused by a device attached to this bridge.
+ *
+ *      ioe has the widgetnum, widgetdev, and memaddr fields updated
+ *      But we don't know the PCI address that corresponds to "memaddr"
+ *      nor do we know which device driver is generating this address.
+ *
+ *      There is no easy way to find out the PCI address(es) that map
+ *      to a specific system memory address. Bus handling code is also
+ *      of not much help, since they don't keep track of the DMA mapping
+ *      that have been handed out.
+ *      So it's a dead-end at this time.
+ *
+ *      If translation is available, we could invoke the error handling
+ *      interface of the device driver.
+ */
+/*ARGSUSED */
+int
+pcibr_dmawr_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    int                     retval;
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe, widgetdev)));
+
+    }
+    return retval;
+}
+
+/*
+ * Bridge error handler.
+ *      Interface to handle all errors that involve bridge in some way.
+ *
+ *      This normally gets called from xtalk error handler.
+ *      ioe has different set of fields set depending on the error that
+ *      was encountered. So, we have a bit field indicating which of the
+ *      fields are valid.
+ *
+ * NOTE: This routine could be operating in interrupt context. So,
+ *      don't try to sleep here (till interrupt threads work!!)
+ */
+int
+pcibr_error_handler(
+		       error_handler_arg_t einfo,
+		       int error_code,
+		       ioerror_mode_t mode,
+		       ioerror_t *ioe)
+{
+    pcibr_soft_t            pcibr_soft;
+    int                     retval = IOERROR_BADERRORCODE;
+
+#ifdef EHE_ENABLE
+    devfs_handle_t	    xconn_vhdl,pcibr_vhdl;
+    error_state_t	    e_state;
+#endif /* EHE_ENABLE */
+
+    pcibr_soft = (pcibr_soft_t) einfo;
+
+#ifdef EHE_ENABLE
+    xconn_vhdl = pcibr_soft->bs_conn;
+    pcibr_vhdl = pcibr_soft->bs_vhdl;
+
+    e_state = error_state_get(xconn_vhdl);
+    
+    if (error_state_set(pcibr_vhdl, e_state) == 
+	ERROR_RETURN_CODE_CANNOT_SET_STATE)
+	return(IOERROR_UNHANDLED);
+
+    /* If we are in the action handling phase clean out the error state
+     * on the xswitch.
+     */
+    if (e_state == ERROR_STATE_ACTION)
+	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
+#endif /* EHE_ENABLE */
+
+#if DEBUG && ERROR_DEBUG
+    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
+#endif
+
+    ASSERT(pcibr_soft != NULL);
+
+    if (error_code & IOECODE_PIO)
+	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
+
+    if (error_code & IOECODE_DMA) {
+	if (error_code & IOECODE_READ) {
+	    /*
+	     * DMA read error occurs when a device attached to the bridge
+	     * tries to read some data from system memory, and this
+	     * either results in a timeout or access error.
+	     * First case is indicated by the bit "XREAD_REQ_TOUT"
+	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
+	     * interrupt status register.
+	     *
+	     * pcibr_error_intr_handler would get invoked first, and it has
+	     * the responsibility of calling pcibr_error_handler with
+	     * suitable parameters.
+	     */
+
+	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+	if (error_code & IOECODE_WRITE) {
+	    /*
+	     * A device attached to this bridge has been generating
+	     * bad DMA writes. Find out the device attached, and
+	     * slap on it's wrist.
+	     */
+
+	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+    }
+    return retval;
+
+}
+
+/*
+ * Reenable a device after handling the error.
+ * This is called by the lower layers when they wish to be reenabled
+ * after an error.
+ * Note that each layer would be calling the previous layer to reenable
+ * first, before going ahead with their own re-enabling.
+ */
+
+int
+pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    ASSERT(error_code & IOECODE_PIO);
+
+    /* If the error is not known to be a write,
+     * we have to call devenable.
+     * write errors are isolated to the bridge.
+     */
+    if (!(error_code & IOECODE_WRITE)) {
+	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+	int                     rc;
+
+	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
+	if (rc != IOERROR_HANDLED)
+	    return rc;
+    }
+    pcibr_error_cleanup(pcibr_soft, error_code);
+    return IOERROR_HANDLED;
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,205 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+pcibr_hints_t           pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,148 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef LATER
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+    sprintf(name, "%v", pcibr_info->f_vertex);
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+    sprintf(name, "%v", pcibr_info->f_master);
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    pss->bss_ext_ates_active ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+#endif	/* LATER */
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,907 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*
+ *	Get the next wrapper pointer queued in the interrupt circular buffer.
+ */
+pcibr_intr_wrap_t
+pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
+{
+    pcibr_intr_wrap_t	wrap;
+
+	if (cbuf->ib_in == cbuf->ib_out)
+	    PRINT_PANIC( "pcibr intr circular buffer empty, cbuf=0x%p, ib_in=ib_out=%d\n",
+		(void *)cbuf, cbuf->ib_out);
+
+	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
+	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
+	return(wrap);
+}
+
+/* 
+ *	Queue a wrapper pointer in the interrupt circular buffer.
+ */
+void
+pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
+{
+	int	in;
+	int	s;
+
+	/*
+	 * Multiple CPUs could be executing this code simultaneously
+	 * if a handler has registered multiple interrupt lines and
+	 * the interrupts are directed to different CPUs.
+	 */
+	s = mutex_spinlock(&cbuf->ib_lock);
+	in = (cbuf->ib_in + 1) % IBUFSIZE;
+	if (in == cbuf->ib_out) 
+	    PRINT_PANIC( "pcibr intr circular buffer full, cbuf=0x%p, ib_in=%d\n",
+		(void *)cbuf, cbuf->ib_in);
+
+	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
+	cbuf->ib_in = in;
+	mutex_spinunlock(&cbuf->ib_lock, s);
+	return;
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    pcibr_intr->bi_ibuf.ib_in = 0;
+    pcibr_intr->bi_ibuf.ib_out = 0;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+
+void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c	Mon Nov 19 23:22:52 2001
@@ -0,0 +1,897 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+void              do_pcibr_rrb_clear(bridge_t *, int);
+void              do_pcibr_rrb_flush(bridge_t *, int);
+int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int		  pcibr_wrb_flush(devfs_handle_t);
+int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void              pcibr_rrb_flush(devfs_handle_t);
+int		  pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+
+/* 
+ *    RRB Management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk("do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    int                     res_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* Save the boot-time RRB configuration for this slot */
+    if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] < 0) {
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_valid[pciio_slot]; 
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] =
+                pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+        pcibr_soft->bs_rrb_res_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_res[pciio_slot];
+                  
+    }
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+        /*
+         * Reserve enough RRBs so this slot's RRB configuration can be
+         * reset to its boot-time default following a hot-plug shut-down
+         */
+        res_rrbs =   (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot]) 
+                   + (pcibr_soft->bs_rrb_valid_dflt[pciio_slot +
+                                                    PCIBR_RRB_SLOT_VIRTUAL] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot +
+                                               PCIBR_RRB_SLOT_VIRTUAL])
+                   + (pcibr_soft->bs_rrb_res_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_res[pciio_slot]);
+
+         if (res_rrbs > 0) {
+             pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs;
+             pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+                 pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+                 - res_rrbs;
+         }
+ 
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devices.  The evn_odd argument indicates whether
+ * allocation is for the odd or even rrbs. The next group of four argument
+ * pairs indicate the amount of rrbs to be assigned to each device. The first
+ * argument of each pair indicate the total number of rrbs to allocate for that
+ * device. The second argument of each pair indicates how many rrb's from the
+ * first argument should be assigned to the virtual channel. The total of all
+ * of the first arguments should be <= 8. The second argument should be <= the
+ * first argument.
+ * if even_odd = 0 the devices in order are 0, 2, 4, 6 
+ * if even_odd = 1 the devices in order are 1, 3, 5, 7
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t          pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t)0;
+    bridge_t               *bridge = NULL;
+
+    uint32_t                rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t                cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+		for( j = 0; j < virt[i]; j++) {
+			cur_rrb = i | 0xc;
+			cur_rrb = cur_rrb << (rrb_shift * 4);
+			rrb_shift--;
+			rrb_setting = rrb_setting | cur_rrb;
+			dev_rrbs[i] = dev_rrbs[i] - 1;
+		}
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    pcibr_info_h	 pcibr_infoh;
+    pcibr_info_t	 pcibr_info;
+    bridge_t		*bridge;
+    int                  c0, c1, r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk(
+	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n",
+            slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_initial_rrb
+ *      Assign an equal total number of RRBs to all candidate slots, 
+ *      where the total is the sum of the number of RRBs assigned to
+ *      the normal channel, the number of RRBs assigned to the virtual
+ *      channel, and the number of RRBs assigned as reserved. 
+ *
+ *      A candidate slot is a populated slot on a non-SN1 system or 
+ *      any existing (populated or empty) slot on an SN1 system.
+ *      Empty SN1 slots need RRBs to support hot-plug operations.
+ */
+
+int
+pcibr_initial_rrb(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t first, pciio_slot_t last)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    pciio_slot_t            slot;
+    int                     c0, c1;
+    int                     have[2][3];
+    int                     res[2];
+    int                     eo;
+
+    have[0][0] = have[0][1] = have[0][2] = 0;
+    have[1][0] = have[1][1] = have[1][2] = 0;
+    res[0] = res[1] = 0;
+
+    for (slot = 0; slot < 8; ++slot) {
+        /* Initial RRB management; give back RRBs in all non-existent slots */
+        (void) pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+
+        /* Base calculations only on existing slots */
+        if ((slot >= first) && (slot <= last)) {
+            c0 = pcibr_soft->bs_rrb_valid[slot];
+            c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+            if ((c0 + c1) < 3)
+                have[slot & 1][c0 + c1]++;
+        }
+    }
+
+    /* Initialize even/odd slot available RRB counts */
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    /*
+     * Calculate reserved RRBs for slots based on current RRB usage
+     */
+    for (eo = 0; eo < 2; eo++) {
+        if ((3 * have[eo][0] + 2 * have[eo][1] + have[eo][2]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 3;
+        else if ((2 * have[eo][0] + have[eo][1]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 2;
+        else if (have[eo][0] <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 1;
+        else
+            res[eo] = 0;
+
+    }
+
+    /* Assign reserved RRBs to existing slots */
+    for (slot = first; slot <= last; ++slot) {
+        int                     r;
+
+        c0 = pcibr_soft->bs_rrb_valid[slot];
+        c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+        r = res[slot & 1] - (c0 + c1);
+
+        if (r > 0) {
+            pcibr_soft->bs_rrb_res[slot] = r;
+            pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+            }
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("%v RRB MANAGEMENT: %d+%d free\n",
+            pcibr_vhdl,
+            pcibr_soft->bs_rrb_avail[0],
+            pcibr_soft->bs_rrb_avail[1]);
+    for (slot = first; slot <= last; ++slot)
+        printk("\tslot %d: %d+%d+%d", slot,
+                0xFFF & pcibr_soft->bs_rrb_valid[slot],
+                0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+                pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return 0;
+
+}
+
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,1693 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t     pcibr_info_get(devfs_handle_t);
+extern int              pcibr_widget_to_bus(int);
+extern pcibr_info_t     pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+extern void             pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+#if 0
+int pcibr_slot_reset(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+#endif
+
+int pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags);
+int pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *);
+void		 pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+extern uint64_t  do_pcibr_config_get(cfg_p, unsigned, unsigned);
+
+#ifdef LATER
+int pcibr_slot_attach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot,
+                int drv_flags, char *l1_msg, int *sub_errorp);
+int pcibr_slot_pwr(devfs_handle_t, pciio_slot_t, int, char *);
+int pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+int pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+void pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh, int func,
+                 pcibr_slot_func_info_resp_t funcp);
+int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot,
+                 pcibr_slot_info_resp_t respp);
+int pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif	/* LATER */
+
+extern devfs_handle_t baseio_pci_vhdl;
+int scsi_ctlr_nums_add(devfs_handle_t, devfs_handle_t);
+
+/* For now .... */
+/*
+ * PCI Hot-Plug Capability Flags
+ */
+#define D_PCI_HOT_PLUG_ATTACH  0x200  /* Driver supports PCI hot-plug attach */
+#define D_PCI_HOT_PLUG_DETACH  0x400  /* Driver supports PCI hot-plug detach */
+
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_startup
+ *	Software start-up the PCI slot.
+ */
+int
+pcibr_slot_startup(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_up_resp_s    tmp_up_resp;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Do not allow start-up of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+ 
+    /* Check for the valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) {
+        error = PCI_SLOT_ALREADY_UP;
+        goto startup_unlock;
+    }
+
+    error = pcibr_slot_attach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_ATTACH,
+                              l1_msg, &tmp_up_resp.resp_sub_errno);
+
+    strncpy(tmp_up_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_up_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_up_resp, reqp->req_respp.up, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    startup_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+/*
+ * pcibr_slot_shutdown
+ *	Software shut-down the PCI slot
+ */
+int
+pcibr_slot_shutdown(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t                      *bridge;
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_down_resp_s  tmp_down_resp;
+    pciio_slot_t                   tmp_slot;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Check for valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Do not allow shut-down of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) ||
+        ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) {
+        error = PCI_SLOT_ALREADY_DOWN;
+        /*
+         * RJR - Should we invoke an L1 slot power-down command just in case
+         *       a previous shut-down failed to power-down the slot?
+         */
+        goto shutdown_unlock;
+    }
+
+    /* Do not allow the last 33 MHz card to be removed */
+    if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) ==
+         BRIDGE_CTRL_BUS_SPEED_33) {
+        for (tmp_slot = pcibr_soft->bs_first_slot;
+             tmp_slot <= pcibr_soft->bs_last_slot; tmp_slot++)
+            if (tmp_slot != slot)
+                if (pcibr_soft->bs_slot[tmp_slot].slot_status & SLOT_POWER_UP) {
+                    error++;
+                    break;
+                }
+        if (!error) {
+            error = PCI_EMPTY_33MHZ;
+            goto shutdown_unlock;
+        }
+    }
+
+    error = pcibr_slot_detach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_DETACH,
+                              l1_msg, &tmp_down_resp.resp_sub_errno);
+
+    strncpy(tmp_down_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_down_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_down_resp, reqp->req_respp.down, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    shutdown_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+    slotp->resp_slot_status = pss->slot_status;
+
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = pss->bss_ext_ates_active;
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_wid_control = bridge->b_wid_control;
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = reqp->req_respp.query;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(PCI_NOT_A_SLOT);
+    }
+
+    /* Do not allow a query of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+/* FIXME: there should be a better way to do this.
+ * pcibr_attach() needs PCI_ADDR_SPACE_LIMITS_STORE
+ */
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_attach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific initialization that needs to be done.
+ *	This is usually called when we want to initialize a new
+ * 	PCI card on the bus.
+ */
+int
+pcibr_slot_attach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags,
+		  char        *l1_msg,
+                  int         *sub_errorp)
+{
+    pcibr_soft_t  pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    timespec_t    ts;
+    int		  error;
+
+    if (!(pcibr_soft->bs_slot[slot].slot_status & SLOT_POWER_UP)) { 
+        /* Power-up the slot */
+        error = pcibr_slot_pwr(pcibr_vhdl, slot, L1_REQ_PCI_UP, l1_msg);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_L1_ERR);
+        } else {
+            pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_POWER_MASK;
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_POWER_UP;
+        }
+
+#ifdef LATER
+        /*
+         * Allow cards like the Alteon Gigabit Ethernet Adapter to complete
+         * on-card initialization following the slot reset
+         */
+         ts.tv_sec = 0;                      /* 0 secs */
+         ts.tv_nsec = 500 * (1000 * 1000);   /* 500 msecs */
+         nano_delay(&ts);
+#else
+#endif
+#if 0
+        /* Reset the slot */
+        error = pcibr_slot_reset(pcibr_vhdl, slot)
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RESET_ERR);
+        }
+#endif
+
+        /* Find out what is out there */
+        error = pcibr_slot_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_INFO_INIT_ERR);
+        }
+
+        /* Set up the address space for this slot in the PCI land */
+        error = pcibr_slot_addr_space_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_ADDR_INIT_ERR);
+        }
+
+        /* Setup the device register */
+        error = pcibr_slot_device_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_DEV_INIT_ERR);
+        }
+
+        /* Setup host/guest relations */
+        error = pcibr_slot_guest_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_GUEST_INIT_ERR);
+        }
+
+        /* Initial RRB management */
+        error = pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RRB_ALLOC_ERR);
+        }
+
+    }
+
+    /* Call the device attach */
+    error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags);
+    if (error) {
+        if (sub_errorp)
+            *sub_errorp = error;
+        if (error == EUNATCH)
+            return(PCI_NO_DRIVER);
+        else
+            return(PCI_SLOT_DRV_ATTACH_ERR);
+    }
+
+    return(0);
+}
+#endif	/* LATER */
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+    boolean_t		is_sys_critical_vertex(devfs_handle_t);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+    int                 bar;
+    int                 devio_index;
+    int                 s;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+        s = pcibr_lock(pcibr_soft);
+
+        for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) {
+            if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE)
+                continue;
+
+            /* Get index of the DevIO(x) register used to access this BAR */
+            devio_index = pcibr_info->f_window[bar].w_devio_index;
+
+ 
+            /* On last use, clear the DevIO(x) used to access this BAR */
+            if (! --pcibr_soft->bs_slot[devio_index].bss_devio.bssd_ref_cnt) {
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_space =
+                                                       PCIIO_SPACE_NONE; 
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_base =
+                                                       PCIBR_D32_BASE_UNSET;
+               pcibr_soft->bs_slot[devio_index].bss_device = 0;
+            }
+        }
+
+        pcibr_unlock(pcibr_soft, s);
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+
+	DEL(pcibr_info);
+    }
+
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/sn2/shub_intr.c lia64-2.4/arch/ia64/sn/io/sn2/shub_intr.c
--- linux-2.4.16/arch/ia64/sn/io/sn2/shub_intr.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/io/sn2/shub_intr.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,218 @@
+/* $Id: shub_intr.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 2001 by Alan Mayer
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern void hub_device_desc_update(device_desc_t, ilvl_t, cpuid_t);
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+	extern void sn_cpei_handler(int, void *, struct pt_regs *);
+	extern void sn_init_cpei_timer(void);
+
+	if (request_irq(SGI_SHUB_ERROR_VECTOR, sn_cpei_handler, 0, NULL, NULL) ) {
+		printk("hub_intr_init: Couldn't register SGI_SHUB_ERROR_VECTOR = %x\n",SGI_SHUB_ERROR_VECTOR);
+	}
+	sn_init_cpei_timer();
+}
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+        hubii_wcr_t     ii_wcr; /* the control status register */
+        
+        ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+        
+        return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev,
+		int uncond_nothread)
+{
+	cpuid_t		cpu = 0;
+	int		vector;
+	hub_intr_t	intr_hdl;
+	cnodeid_t	cnode;
+	int		cpuphys, slice;
+	int		nasid;
+	iopaddr_t	xtalk_addr;
+	struct xtalk_intr_s	*xtalk_info;
+	xwidget_info_t	xwidget_info;
+	ilvl_t		intr_swlevel = 0;
+
+	cpu = intr_heuristic(dev, dev_desc, -1, 0, owner_dev, NULL, &vector);
+
+	if (cpu == CPU_NONE) {
+		printk("Unable to allocate interrupt for 0x%p\n", (void *)owner_dev);
+		return(0);
+	}
+
+	cpuphys = cpu_physical_id(cpu);
+	slice = cpu_physical_id_to_slice(cpuphys);
+	nasid = cpu_physical_id_to_nasid(cpuphys);
+	cnode = cpuid_to_cnodeid(cpu);
+
+	if (slice) {
+		xtalk_addr = SH_II_INT1 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	} else {
+		xtalk_addr = SH_II_INT0 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	}
+
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, cnode);
+	ASSERT_ALWAYS(intr_hdl);
+
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = vector;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info) {
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+	}
+
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = vector;
+	intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED;
+
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	return(intr_hdl);
+}
+
+hub_intr_t
+hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int		vector = intr_hdl->i_bit;
+	xtalk_intr_t	xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED) {
+		kfree(intr_hdl);
+	}
+	intr_unreserve_level(cpu, vector);
+}
+
+int
+hub_intr_connect(hub_intr_t intr_hdl,
+		xtalk_intr_setfunc_t setfunc,
+		void *setfunc_arg)
+{
+	int		rv;
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int 		vector = intr_hdl->i_bit;
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, vector, intr_hdl->i_swlevel, NULL);
+
+	if (rv < 0) {
+		return rv;
+	}
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) {
+		(*setfunc)((xtalk_intr_t)intr_hdl);
+	}
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+
+	return 0;
+}
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -urN linux-2.4.16/arch/ia64/sn/io/stubs.c lia64-2.4/arch/ia64/sn/io/stubs.c
--- linux-2.4.16/arch/ia64/sn/io/stubs.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/stubs.c	Mon Nov 19 23:22:53 2001
@@ -4,10 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/ctype.h>
 #include <linux/mm.h>
@@ -61,45 +61,45 @@
 }
 
 void *
-kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
 {
         /* Allocates on node 'node' */
-	FIXME("kmem_alloc_node : use kmalloc");
+	FIXME("snia_kmem_alloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void *
-kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
 {
-	FIXME("kmem_zalloc_node : use kmalloc");
+	FIXME("snia_kmem_zalloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void
-kmem_free(void *where, int size)
+snia_kmem_free(void *where, int size)
 {
-	FIXME("kmem_free : use kfree");
+	FIXME("snia_kmem_free : use kfree");
 	return(kfree(where));
 }
 
 
 void *
-kmem_zone_alloc(register zone_t *zone, int flags)
+snia_kmem_zone_alloc(register zone_t *zone, int flags)
 {
-	FIXME("kmem_zone_alloc : return null");
+	FIXME("snia_kmem_zone_alloc : return null");
 	return((void *)0);
 }
 
 void
-kmem_zone_free(register zone_t *zone, void *ptr)
+snia_kmem_zone_free(register zone_t *zone, void *ptr)
 {
-	FIXME("kmem_zone_free : no-op");
+	FIXME("snia_kmem_zone_free : no-op");
 }
 
 zone_t *
-kmem_zone_init(register int size, char *zone_name)
+snia_kmem_zone_init(register int size, char *zone_name)
 {
-	FIXME("kmem_zone_free : returns NULL");
+	FIXME("snia_kmem_zone_free : returns NULL");
 	return((zone_t *)0);
 }
 
diff -urN linux-2.4.16/arch/ia64/sn/io/xbow.c lia64-2.4/arch/ia64/sn/io/xbow.c
--- linux-2.4.16/arch/ia64/sn/io/xbow.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/xbow.c	Mon Nov 19 23:22:53 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -19,6 +18,7 @@
 #include <asm/sn/hack.h>
 #include <asm/sn/pci/bridge.h>
 #include <asm/sn/xtalk/xtalk_private.h>
+#include <asm/sn/simulator.h>
 
 /* #define DEBUG		1 */
 /* #define XBOW_DEBUG	1 */
@@ -102,7 +102,6 @@
 #ifdef LATER
 static void             xbow_setwidint(xtalk_intr_t);
 static void             xbow_errintr_handler(intr_arg_t);
-static error_handler_f  xbow_error_handler;
 #endif
 void                    xbow_intr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
 
@@ -281,7 +280,7 @@
                         /* &hcl_fops */ (void *)&vhdl, NULL);
     if (!vhdl) {
         printk(KERN_WARNING "xbow_attach: Unable to create char device for xbow conn %p\n",
-                conn);
+                (void *)conn);
     }
 
     /*
@@ -306,7 +305,7 @@
 
     /*
      * get the name of this xbow vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(vhdl, devnm, MAXDEVNAME);
@@ -371,36 +370,9 @@
     }
 
     /*
-     * attach the crossbow error interrupt.
-     */
-#ifdef LATER
-    dev_desc = device_desc_dup(vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Crossbow error");
-
-    intr_hdl = xtalk_intr_alloc(conn, dev_desc, vhdl);
-    ASSERT(intr_hdl != NULL);
-
-    xtalk_intr_connect(intr_hdl,
-		       (intr_func_t) xbow_errintr_handler,
-		       (intr_arg_t) soft,
-		       (xtalk_intr_setfunc_t) xbow_setwidint,
-		       (void *) xbow,
-		       (void *) 0);
-    device_desc_free(dev_desc);
-
-    xwidget_error_register(conn, xbow_error_handler, soft);
-
-#else
-    FIXME("xbow_attach: Fixme: we bypassed attaching xbow error interrupt.\n");
-#endif /* LATER */
-
-    /*
      * Enable xbow error interrupts
      */
-    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE |
-			    XB_WID_CTRL_XTALK_IE);
+    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE | XB_WID_CTRL_XTALK_IE);
 
     /*
      * take a census of the widgets present,
@@ -918,460 +890,6 @@
     return 1;
 }
 
-/*
- * xbow_errintr_handler will be called if the xbow
- * sends an interrupt request to report an error.
- */
-
-#ifdef LATER
-static void
-xbow_errintr_handler(intr_arg_t arg)
-{
-    ioerror_t               ioe[1];
-    xbow_soft_t             soft = (xbow_soft_t) arg;
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_control;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    w_err_cmd_word_u        wid_err;
-    uint64_t                 wid_err_addr;
-
-    int                     fatal = 0;
-    int                     dump_ioe = 0;
-
-    wid_control = xbow->xb_wid_control;
-    wid_stat = xbow->xb_wid_stat_clr;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-    xbow->xb_wid_err_cmdword = 0;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if (wid_stat & XB_WID_STAT_LINK_INTR_MASK) {
-	int                     port;
-
-	wid_err.r = wid_err_cmdword;
-
-	for (port = MAX_PORT_NUM - MAX_XBOW_PORTS;
-	     port < MAX_PORT_NUM; port++) {
-	    if (wid_stat & XB_WID_STAT_LINK_INTR(port)) {
-		xb_linkregs_t          *link = &(xbow->xb_link(port));
-		xbowreg_t               link_control = link->link_control;
-		xbowreg_t               link_status = link->link_status_clr;
-		xbowreg_t               link_aux_status = link->link_aux_status;
-		xbowreg_t               link_pend;
-
-		link_pend = link_status & link_control &
-		    (XB_STAT_ILLEGAL_DST_ERR
-		     | XB_STAT_OALLOC_IBUF_ERR
-		     | XB_STAT_RCV_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_MAX_RTRY_ERR
-		     | XB_STAT_RCV_ERR
-		     | XB_STAT_XMT_RTRY_ERR
-		     | XB_STAT_MAXREQ_TOUT_ERR
-		     | XB_STAT_SRC_TOUT_ERR
-		    );
-
-		if (link_pend & XB_STAT_ILLEGAL_DST_ERR) {
-		    if (wid_err.f.sidn == port) {
-			IOERROR_INIT(ioe);
-			IOERROR_SETVALUE(ioe, widgetnum, port);
-			IOERROR_SETVALUE(ioe, xtalkaddr, wid_err_addr);
-			if (IOERROR_HANDLED ==
-			    xbow_error_handler(soft,
-					       IOECODE_DMA,
-					       MODE_DEVERROR,
-					       ioe)) {
-			    link_pend &= ~XB_STAT_ILLEGAL_DST_ERR;
-			} else {
-			    dump_ioe++;
-			}
-		    }
-		}
-		/* Xbow/Bridge WAR:
-		 * if the bridge signals an LLP Transmitter Retry,
-		 * rewrite its control register.
-		 * If someone else triggers this interrupt,
-		 * ignore (and disable) the interrupt.
-		 */
-		if (link_pend & XB_STAT_XMT_RTRY_ERR) {
-		    if (!xbow_xmit_retry_error(soft, port)) {
-			link_control &= ~XB_CTRL_XMT_RTRY_IE;
-			link->link_control = link_control;
-			link->link_control;	/* stall until written */
-		    }
-		    link_pend &= ~XB_STAT_XMT_RTRY_ERR;
-		}
-		if (link_pend) {
-		    devfs_handle_t	xwidget_vhdl;
-		    char		*xwidget_name;
-		    
-		    /* Get the widget name corresponding to the current
-		     * xbow link.
-		     */
-		    xwidget_vhdl = xbow_widget_lookup(soft->busv,port);
-		    xwidget_name = xwidget_name_get(xwidget_vhdl);
-
-#ifdef	LATER
-		    printk("%s port %X[%s] XIO Bus Error",
-			    soft->name, port, xwidget_name);
-		    if (link_status & XB_STAT_MULTI_ERR)
-			XEM_ADD_STR("\tMultiple Errors\n");
-		    if (link_status & XB_STAT_ILLEGAL_DST_ERR)
-			XEM_ADD_STR("\tInvalid Packet Destination\n");
-		    if (link_status & XB_STAT_OALLOC_IBUF_ERR)
-			XEM_ADD_STR("\tInput Overallocation Error\n");
-		    if (link_status & XB_STAT_RCV_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP receive error counter overflow\n");
-		    if (link_status & XB_STAT_XMT_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP transmit retry counter overflow\n");
-		    if (link_status & XB_STAT_XMT_MAX_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Max Transmitter Retry\n");
-		    if (link_status & XB_STAT_RCV_ERR)
-			XEM_ADD_STR("\tLLP Receiver error\n");
-		    if (link_status & XB_STAT_XMT_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Transmitter Retry\n");
-		    if (link_status & XB_STAT_MAXREQ_TOUT_ERR)
-			XEM_ADD_STR("\tMaximum Request Timeout\n");
-		    if (link_status & XB_STAT_SRC_TOUT_ERR)
-			XEM_ADD_STR("\tSource Timeout Error\n");
-#endif	/* LATER */
-		    {
-			int                     other_port;
-
-			for (other_port = 8; other_port < 16; ++other_port) {
-			    if (link_aux_status & (1 << other_port)) {
-				/* XXX- need to go to "other_port"
-				 * and clean up after the timeout?
-				 */
-				XEM_ADD_VAR(other_port);
-			    }
-			}
-		    }
-
-#if !DEBUG
-		    if (kdebug) {
-#endif
-			XEM_ADD_VAR(link_control);
-			XEM_ADD_VAR(link_status);
-			XEM_ADD_VAR(link_aux_status);
-
-			if (dump_ioe) {
-			    XEM_ADD_IOE();
-			    dump_ioe = 0;
-			}
-#if !DEBUG
-		    }
-#endif
-		    fatal++;
-		}
-	    }
-	}
-    }
-    if (wid_stat & wid_control & XB_WID_STAT_WIDGET0_INTR) {
-	/* we have a "widget zero" problem */
-
-	if (wid_stat & (XB_WID_STAT_MULTI_ERR
-			| XB_WID_STAT_XTALK_ERR
-			| XB_WID_STAT_REG_ACC_ERR)) {
-
-	    printk("%s Port 0 XIO Bus Error",
-		    soft->name);
-	    if (wid_stat & XB_WID_STAT_MULTI_ERR)
-		XEM_ADD_STR("\tMultiple Error\n");
-	    if (wid_stat & XB_WID_STAT_XTALK_ERR)
-		XEM_ADD_STR("\tXIO Error\n");
-	    if (wid_stat & XB_WID_STAT_REG_ACC_ERR)
-		XEM_ADD_STR("\tRegister Access Error\n");
-
-	    fatal++;
-	}
-    }
-    if (fatal) {
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_control);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	PRINT_PANIC("XIO Bus Error");
-    }
-}
-#endif	/* LATER */
-
-/*
- * XBOW ERROR Handling routines.
- * These get invoked as part of walking down the error handling path
- * from hub/heart towards the I/O device that caused the error.
- */
-
-/*
- * xbow_error_handler
- *      XBow error handling dispatch routine.
- *      This is the primary interface used by external world to invoke
- *      in case of an error related to a xbow.
- *      Only functionality in this layer is to identify the widget handle
- *      given the widgetnum. Otherwise, xbow does not gathers any error
- *      data.
- */
-
-#ifdef LATER
-static int
-xbow_error_handler(
-		      void *einfo,
-		      int error_code,
-		      ioerror_mode_t mode,
-		      ioerror_t *ioerror)
-{
-    int                     retval = IOERROR_WIDGETLEVEL;
-
-    xbow_soft_t             soft = (xbow_soft_t) einfo;
-    int                     port;
-    devfs_handle_t            conn;
-    devfs_handle_t            busv;
-
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    uint64_t                 wid_err_addr;
-
-    xb_linkregs_t          *link;
-    xbowreg_t               link_control;
-    xbowreg_t               link_status;
-    xbowreg_t               link_aux_status;
-
-    ASSERT(soft != 0);
-    busv = soft->busv;
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: xbow_error_handler\n", soft->name, busv);
-#endif
-
-    port = IOERROR_GETVALUE(ioerror, widgetnum);
-
-    if (port == 0) {
-	/* error during access to xbow:
-	 * do NOT attempt to access xbow regs.
-	 */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on Crossbow at %s\n"
-		    "\tbut Crosbow never initiates DMA!",
-		    soft->name);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERt("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO controller\n"
-		    "\twith offset 0x%X",
-		    soft->name,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /*
-     * error not on port zero:
-     * safe to read xbow registers.
-     */
-    wid_stat = xbow->xb_wid_stat;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if ((port < BASE_XBOW_PORT) ||
-	(port >= MAX_PORT_NUM)) {
-
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut Crossbow does not support that port",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which Crossbow does not support)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-#if !DEBUG
-	}
-#endif
-
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /* access to valid port:
-     * ok to check port status.
-     */
-
-    link = &(xbow->xb_link(port));
-    link_control = link->link_control;
-    link_status = link->link_status;
-    link_aux_status = link->link_aux_status;
-
-    /* Check that there is something present
-     * in that XIO port.
-     */
-    if (!(link_aux_status & XB_AUX_STAT_PRESENT)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut there is no device connected there.",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which has no device connected)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-	    XEM_ADD_VAR(port);
-	    XEM_ADD_VAR(link_control);
-	    XEM_ADD_VAR(link_status);
-	    XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-	}
-#endif
-	return retval;
-
-    }
-    /* Check that the link is alive.
-     */
-    if (!(link_status & XB_STAT_LINKALIVE)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	if (link_aux_status & XB_AUX_LINKFAIL_RST_BAD)
-	    XEM_ADD_STR("\tLink never came out of reset\n");
-	else
-	    XEM_ADD_STR("\tLink failed while transferring data\n");
-
-    }
-    /* get the connection point for the widget
-     * involved in this error; if it exists and
-     * is not our connectpoint, cycle back through
-     * xtalk_error_handler to deliver control to
-     * the proper handler (or to report a generic
-     * crosstalk error).
-     *
-     * If the downstream handler won't handle
-     * the problem, we let our upstream caller
-     * deal with it, after (in DEBUG and kdebug
-     * kernels) dumping the xbow state for this
-     * port.
-     */
-    conn = xbow_widget_lookup(busv, port);
-    if ((conn != GRAPH_VERTEX_NONE) &&
-	(conn != soft->conn)) {
-	retval = xtalk_error_handler(conn, error_code, mode, ioerror);
-	if (retval == IOERROR_HANDLED)
-	    return IOERROR_HANDLED;
-    }
-    if (mode == MODE_DEVPROBE)
-	return IOERROR_HANDLED;
-
-    if (retval == IOERROR_UNHANDLED) {
-	retval = IOERROR_PANIC;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-    }
-
-#if !DEBUG
-    if (kdebug) {
-#endif
-	XEM_ADD_STR("Raw status values for Crossbow:\n");
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	XEM_ADD_VAR(port);
-	XEM_ADD_VAR(link_control);
-	XEM_ADD_VAR(link_status);
-	XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-    }
-#endif
-    /* caller will dump raw ioerror data
-     * in DEBUG and kdebug kernels.
-     */
-
-    return retval;
-}
-
-#endif	/* LATER */
-
 void
 xbow_update_perf_counters(devfs_handle_t vhdl)
 {
@@ -1520,7 +1038,7 @@
 
 	if (lnk_sts.linkstatus & ~(XB_STAT_RCV_ERR | XB_STAT_XMT_RTRY_ERR | XB_STAT_LINKALIVE)) {
 #ifdef	LATER
-	    PRINT_WARNING("link %d[%s]: bad status 0x%x\n",
+	    printk(KERN_WARNING  "link %d[%s]: bad status 0x%x\n",
 		    link, xwidget_name, lnk_sts.linkstatus);
 #endif
 	}
diff -urN linux-2.4.16/arch/ia64/sn/io/xswitch.c lia64-2.4/arch/ia64/sn/io/xswitch.c
--- linux-2.4.16/arch/ia64/sn/io/xswitch.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/io/xswitch.c	Mon Nov 19 23:22:53 2001
@@ -4,14 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -urN linux-2.4.16/arch/ia64/sn/io/xtalk.c lia64-2.4/arch/ia64/sn/io/xtalk.c
--- linux-2.4.16/arch/ia64/sn/io/xtalk.c	Thu Apr 12 12:16:35 2001
+++ lia64-2.4/arch/ia64/sn/io/xtalk.c	Mon Nov 19 23:22:53 2001
@@ -4,24 +4,22 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/hcl_util.h>
-
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/xtalk/xswitch.h>
 #include <asm/sn/xtalk/xwidget.h>
-
 #include <asm/sn/xtalk/xtalk_private.h>
 
 /*
@@ -41,7 +39,6 @@
 
 cdl_p                   xtalk_registry = NULL;
 
-#include <asm/sn/agent.h>
 #define	DEV_FUNC(dev,func)	hub_##func
 #define	CAST_PIOMAP(x)		((hub_piomap_t)(x))
 #define	CAST_DMAMAP(x)		((hub_dmamap_t)(x))
@@ -72,7 +69,7 @@
 xtalk_intr_t            xtalk_intr_alloc(devfs_handle_t, device_desc_t, devfs_handle_t);
 xtalk_intr_t            xtalk_intr_alloc_nothd(devfs_handle_t, device_desc_t, devfs_handle_t);
 void                    xtalk_intr_free(xtalk_intr_t);
-int                     xtalk_intr_connect(xtalk_intr_t, intr_func_t, intr_arg_t, xtalk_intr_setfunc_t, void *, void *);
+int                     xtalk_intr_connect(xtalk_intr_t, xtalk_intr_setfunc_t, void *);
 void                    xtalk_intr_disconnect(xtalk_intr_t);
 devfs_handle_t            xtalk_intr_cpu_get(xtalk_intr_t);
 int                     xtalk_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
@@ -113,8 +110,6 @@
 					 xwidgetnum_t, devfs_handle_t, 
 					 xwidgetnum_t, async_attach_t);
 int			xwidget_unregister(devfs_handle_t);
-void                    xwidget_error_register(devfs_handle_t, error_handler_f *,
-					       error_handler_arg_t);
 void                    xwidget_reset(devfs_handle_t);
 char			*xwidget_name_get(devfs_handle_t);
 #if !defined(DEV_FUNC)
@@ -472,14 +467,11 @@
  */
 int
 xtalk_intr_connect(xtalk_intr_t intr_hdl,	/* xtalk intr resource handle */
-		   intr_func_t intr_func,	/* xtalk intr handler */
-		   intr_arg_t intr_arg,		/* arg to intr handler */
 		   xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-		   void *setfunc_arg,	/* arg to setfunc */
-		   void *thread)
-{				/* intr thread to use */
+		   void *setfunc_arg)	/* arg to setfunc */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, setfunc, setfunc_arg, thread);
+	(CAST_INTR(intr_hdl), setfunc, setfunc_arg);
 }
 
 
@@ -506,85 +498,6 @@
 }
 
 
-/*
- * =====================================================================
- *                      ERROR MANAGEMENT
- */
-
-/*
- * xtalk_error_handler:
- * pass this error on to the handler registered
- * at the specified xtalk connecdtion point,
- * or complain about it here if there is no handler.
- *
- * This routine plays two roles during error delivery
- * to most widgets: first, the external agent (heart,
- * hub, or whatever) calls in with the error and the
- * connect point representing the crosstalk switch,
- * or whatever crosstalk device is directly connected
- * to the agent.
- *
- * If there is a switch, it will generally look at the
- * widget number stashed in the ioerror structure; and,
- * if the error came from some widget other than the
- * switch, it will call back into xtalk_error_handler
- * with the connection point of the offending port.
- */
-int
-xtalk_error_handler(
-		       devfs_handle_t xconn,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    xwidget_info_t          xwidget_info;
-
-#if DEBUG && ERROR_DEBUG
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    printk("%v: xtalk_error_handler\n", xconn);
-#else
-    printk("%x: xtalk_error_handler\n", xconn);
-#endif
-#endif
-
-    xwidget_info = xwidget_info_get(xconn);
-    /* Make sure that xwidget_info is a valid pointer before derefencing it.
-     * We could come in here during very early initialization. 
-     */
-    if (xwidget_info && xwidget_info->w_efunc)
-	return xwidget_info->w_efunc
-	    (xwidget_info->w_einfo,
-	     error_code, mode, ioerror);
-    /*
-     * no error handler registered for
-     * the offending port. it's not clear
-     * what needs to be done, but reporting
-     * it would be a good thing, unless it
-     * is a mode that requires nothing.
-     */
-    if ((mode == MODE_DEVPROBE) || (mode == MODE_DEVUSERERROR) ||
-	(mode == MODE_DEVREENABLE))
-	return IOERROR_HANDLED;
-
-#ifdef	LATER
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING("Xbow at %v encountered Fatal error", xconn);
-#else
-    PRINT_WARNING("Xbow at %x encountered Fatal error", xconn);
-#endif
-#endif	/* LATER */
-    ioerror_dump("xtalk", error_code, mode, ioerror);
-
-    return IOERROR_UNHANDLED;
-}
-
-int
-xtalk_error_devenable(devfs_handle_t xconn_vhdl, int devnum, int error_code)
-{
-    return DEV_FUNC(xconn_vhdl, error_devenable) (xconn_vhdl, devnum, error_code);
-}
-
-
 /* =====================================================================
  *                    CONFIGURATION MANAGEMENT
  */
@@ -977,7 +890,7 @@
     widget_info->w_einfo = 0;
     /*
      * get the name of this xwidget vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(widget,devnm,MAXDEVNAME);
@@ -1038,19 +951,6 @@
     return(0);
 }
 
-void
-xwidget_error_register(devfs_handle_t xwidget,
-		       error_handler_f *efunc,
-		       error_handler_arg_t einfo)
-{
-    xwidget_info_t          xwidget_info;
-
-    xwidget_info = xwidget_info_get(xwidget);
-    ASSERT(xwidget_info != NULL);
-    xwidget_info->w_efunc = efunc;
-    xwidget_info->w_einfo = einfo;
-}
-
 /*
  * Issue a link reset to a widget.
  */
@@ -1120,17 +1020,5 @@
 
 	xwidget_unregister(widget_vhdl);
 	
-	return(0);
-}
-/*
- * xtalk_device_inquiry
- *	Find out hardware information about the xtalk widget.
- */
-int
-xtalk_device_inquiry(devfs_handle_t xbus_vhdl, xwidgetnum_t widget)
-{
-
-	extern void hub_device_inquiry(devfs_handle_t, xwidgetnum_t);
-	hub_device_inquiry(xbus_vhdl, widget);
 	return(0);
 }
diff -urN linux-2.4.16/arch/ia64/sn/kernel/Makefile lia64-2.4/arch/ia64/sn/kernel/Makefile
--- linux-2.4.16/arch/ia64/sn/kernel/Makefile	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/Makefile	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,37 @@
+#
+# arch/ia64/sn/Makefile
+#
+# Copyright (C) 1999,2001 Silicon Graphics, Inc. All rights reserved.
+#
+
+EXTRA_CFLAGS	:= -DSN -I. -DBRINGUP \
+		   -DNUMA_BASE -DSIMULATED_KLGRAPH \
+		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+O_TARGET        = sn.o
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = sn_ksyms.o
+endif
+
+subdir-$(CONFIG_IA64_SGI_SN1)	= sn1
+subdir-$(CONFIG_IA64_SGI_SN2)	= sn2
+
+obj-y		= probe.o setup.o sn_asm.o sv.o
+obj-$(CONFIG_IA64_SGI_SN1)      += irq.o mca.o
+obj-$(CONFIG_IA64_SGI_SN2)      += irq.o mca.o
+
+obj-$(CONFIG_IA64_SGI_SN1)      += sn1/sn1.a  
+obj-$(CONFIG_IA64_SGI_SN2)      += sn2/sn2.a  
+
+obj-$(CONFIG_IA64_SGI_AUTOTEST) += llsc4.o misctest.o
+obj-$(CONFIG_IA64_GENERIC)      += machvec.o
+obj-$(CONFIG_MODULES)           += sn_ksyms.o
+
+
+include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/kernel/irq.c lia64-2.4/arch/ia64/sn/kernel/irq.c
--- linux-2.4.16/arch/ia64/sn/kernel/irq.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/irq.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,276 @@
+/*
+ * Platform dependent support for SGI SN1
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics
+ * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000   Alan Mayer (ajm@sgi.com)
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <asm/current.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/types.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pciio_private.h>
+#ifdef ajmtestintr
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#endif /* ajmtestintr */
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/io.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/arch.h>
+
+int irq_to_bit_pos(int irq);
+
+
+
+static unsigned int
+sn1_startup_irq(unsigned int irq)
+{
+        return(0);
+}
+
+static void
+sn1_shutdown_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_disable_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_enable_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_ack_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	int bit = -1;
+	unsigned long long intpend_val;
+#endif
+	int subnode, nasid;
+
+	irq = irq & 0xff;
+	nasid = smp_physical_node_id();
+	subnode = cpuid_to_subnode(smp_processor_id());
+#ifdef CONFIG_IA64_SGI_SN1
+	if (irq == SGI_UART_IRQ) {
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & (1L<<GFX_INTR_A) ) {
+			bit = GFX_INTR_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if ( intpend_val & (1L<<GFX_INTR_B) ) {
+			bit = GFX_INTR_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<PG_MIG_INTR) ) {
+			bit = PG_MIG_INTR;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_A)) {
+			bit = CC_PEND_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_B)) {
+			bit = CC_PEND_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		return;
+	}
+	bit = irq_to_bit_pos(irq);
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+#endif
+}
+
+static void
+sn1_end_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	unsigned long long intpend_val, mask = 0x70L;
+	int nasid, subnode;
+#endif
+
+	irq = irq & 0xff;
+#ifdef CONFIG_IA64_SGI_SN1
+	if (irq == SGI_UART_IRQ) {
+		nasid = smp_physical_node_id();
+		subnode = cpuid_to_subnode(smp_processor_id());
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & mask) {
+			platform_send_ipi(smp_processor_id(), SGI_UART_IRQ, IA64_IPI_DM_INT, 0);
+		}
+	}
+#endif
+}
+
+static void
+sn1_set_affinity_irq(unsigned int irq, unsigned long mask)
+{
+}
+
+struct hw_interrupt_type irq_type_sn1 = {
+        "sn1_irq",
+        sn1_startup_irq,
+        sn1_shutdown_irq,
+        sn1_enable_irq,
+        sn1_disable_irq,
+        sn1_ack_irq,
+        sn1_end_irq,
+        sn1_set_affinity_irq
+};
+
+struct irq_desc *_sn1_irq_desc[NR_CPUS];
+
+struct irq_desc *
+sn1_irq_desc(unsigned int irq) {
+	int cpu = irq >> 8;
+
+	irq = irq & 0xff;
+
+	return(_sn1_irq_desc[cpu] + irq);
+}
+
+u8
+sn1_irq_to_vector(u8 irq) {
+	return(irq & 0xff);
+}
+
+unsigned int
+sn1_local_vector_to_irq(u8 vector) {
+	return ( (smp_processor_id() << 8) + vector);
+}
+
+int
+sn1_valid_irq(u8 irq) {
+
+	return( ((irq & 0xff) < NR_IRQS) && ((irq >> 8) < NR_CPUS) );
+}
+
+void *kmalloc(size_t, int);
+
+void
+sn1_irq_init (void)
+{
+	int i;
+	irq_desc_t *base_desc = _irq_desc;
+
+	for (i=IA64_FIRST_DEVICE_VECTOR; i<NR_IRQS; i++) {
+		if (base_desc[i].handler == &no_irq_type) {
+			base_desc[i].handler = &irq_type_sn1;
+		}
+	}
+}
+
+void
+sn1_init_irq_desc(void) {
+	int i;
+	irq_desc_t *base_desc = _irq_desc, *p;
+
+	for (i=0; i < NR_CPUS; i++) {
+		p =  page_address(alloc_pages_node(numa_node_id(), GFP_KERNEL,
+			get_order(sizeof(struct irq_desc) * NR_IRQS) ) );
+		ASSERT(p);
+		memcpy(p, base_desc, sizeof(struct irq_desc) * NR_IRQS);
+		_sn1_irq_desc[i] = p;
+	}
+}
+
+
+#if !defined(CONFIG_IA64_SGI_SN)
+void
+sn1_pci_fixup(void)
+{
+}
+#endif
+
+int
+bit_pos_to_irq(int bit) {
+#define BIT_TO_IRQ 64
+	if (bit > 118) bit = 118;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		return SGI_UART_IRQ;
+	}
+#endif
+
+        return bit + BIT_TO_IRQ;
+}
+
+int
+irq_to_bit_pos(int irq) {
+#define IRQ_TO_BIT 64
+	int bit = irq - IRQ_TO_BIT;
+
+        return bit;
+}
+
+#ifdef ajmtestintr
+
+#include <linux/timer.h>
+struct timer_list intr_test_timer;
+int intr_test_icount[NR_IRQS];
+struct intr_test_reg_struct {
+	pcibr_soft_t pcibr_soft;
+	int slot;
+};
+struct intr_test_reg_struct intr_test_registered[NR_IRQS];
+
+void
+intr_test_handle_timer(unsigned long data) {
+	int i;
+	bridge_t	*bridge;
+
+	for (i=0;i<NR_IRQS;i++) {
+		if (intr_test_registered[i].pcibr_soft) {
+			pcibr_soft_t pcibr_soft = intr_test_registered[i].pcibr_soft;
+			xtalk_intr_t intr = pcibr_soft->bs_intr[intr_test_registered[i].slot].bsi_xtalk_intr;
+			/* send interrupt */
+			bridge = pcibr_soft->bs_base;
+			bridge->b_force_always[intr_test_registered[i].slot].intr = 1;
+		}
+	}
+	del_timer(&intr_test_timer);
+	intr_test_timer.expires = jiffies + HZ/100;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_set_timer(void) {
+	intr_test_timer.expires = jiffies + HZ/100;
+	intr_test_timer.function = intr_test_handle_timer;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_register_irq(int irq, pcibr_soft_t pcibr_soft, int slot) {
+	irq = irq & 0xff;
+	intr_test_registered[irq].pcibr_soft = pcibr_soft;
+	intr_test_registered[irq].slot = slot;
+}
+
+void
+intr_test_handle_intr(int irq, void *junk, struct pt_regs *morejunk) {
+	intr_test_icount[irq]++;
+	printk("RECEIVED %d INTERRUPTS ON IRQ %d\n",intr_test_icount[irq], irq);
+}
+#endif /* ajmtestintr */
diff -urN linux-2.4.16/arch/ia64/sn/kernel/llsc4.c lia64-2.4/arch/ia64/sn/kernel/llsc4.c
--- linux-2.4.16/arch/ia64/sn/kernel/llsc4.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/llsc4.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,1037 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel_stat.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <asm/efi.h>
+#include <asm/page.h>
+#include <linux/threads.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+
+#include "llsc4.h"
+
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+#ifdef INTTEST
+static int	inttest=0;
+#endif
+
+#ifdef IA64_SEMFIX_INSN
+#undef IA64_SEMFIX_INSN
+#endif
+#ifdef IA64_SEMFIX
+#undef IA64_SEMFIX
+#endif
+# define IA64_SEMFIX_INSN
+# define IA64_SEMFIX    ""
+
+#define NOLOCK		0xdead
+#define BGUARD(linei)	(0xbbbb0000 | (linei));
+#define EGUARD(linei)	(0xeeee0000 | (linei));
+#define GUARDLINE(v)	((v)&0xffff)
+
+/*
+ * Test parameter table for AUTOTEST
+ */
+typedef struct {
+	int	passes;
+	int	linecount;
+	int	linepad;
+} autotest_table_t;
+
+autotest_table_t autotest_table[] = {
+	{50000000,	2,	0x2b4		},
+	{50000000,	16,	0,		},
+	{50000000,	16,	4,		},
+	{50000000,	128,	0x44		},
+	{50000000,	128,	0x84		},
+	{50000000,	128,	0x200		},
+	{50000000,	128,	0x204		},
+	{50000000,	128,	0x2b4		},
+	{50000000,	2,	8*MB+0x2b4	},
+	{50000000,	16,	8*MB+0		},
+	{50000000,	16,	8*MB+4		},
+	{50000000,	128,	8*MB+0x44	},
+	{50000000,	128,	8*MB+0x84	},
+	{50000000,	128,	8*MB+0x200	},
+	{50000000,	128,	8*MB+0x204	},
+	{50000000,	128,	8*MB+0x2b4	},
+	{0}};
+
+/*
+ * Array of virtual addresses available for test purposes.
+ */
+
+typedef struct {
+	long	vstart;
+	long	vend;
+	long	nextaddr;
+	long	nextinit;
+	int	wrapcount;
+} memmap_t;
+
+#define MAPCHUNKS		128
+memmap_t 	memmap[MAPCHUNKS];
+int		memmapx=0;
+
+typedef struct {
+	void	*addr;
+	long	data[16];
+	long	data_fc[16];
+} capture_line_t;
+
+typedef struct {
+	int	size;
+	void	*blockaddr;
+	void	*shadaddr;
+	long	blockdata[48];
+	long	shaddata[48];
+	long	blockdata_fc[48];
+	long	shaddata_fc[48];
+	long	synerr;
+} capture_t;
+
+/*
+ * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
+ * the rest of the tables have to start at 1MB to skip PROM tables.
+ */
+#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512)))
+
+#define k_capture		mbase->sk_capture
+#define k_go			mbase->sk_go
+#define k_linecount		mbase->sk_linecount
+#define k_passes		mbase->sk_passes
+#define k_napticks		mbase->sk_napticks
+#define k_stop_on_error		mbase->sk_stop_on_error
+#define k_verbose		mbase->sk_verbose
+#define k_threadprivate		mbase->sk_threadprivate
+#define k_blocks		mbase->sk_blocks
+#define k_iter_msg		mbase->sk_iter_msg
+#define k_vv			mbase->sk_vv
+#define k_linepad		mbase->sk_linepad
+#define k_options		mbase->sk_options
+#define k_testnumber		mbase->sk_testnumber
+#define k_currentpass		mbase->sk_currentpass
+
+static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
+static control_t	*mbase;
+static vint		initialized=0;
+
+static unsigned int ran_conf_llsc(int);
+static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
+static void dumpline(void *, char *, char *, void *, void *, int);
+static int  checkstop(int, int, uint);
+static void spin(int);
+static void capturedata(capture_t *, uint, void *, void *, int);
+static int  randn(uint max, uint *seed);
+static uint zrandom (uint *zranseed);
+static int  set_lock(uint *, uint);
+static int  clr_lock(uint *, uint);
+static void Speedo(void);
+
+int autotest_enabled=0;
+static int llsctest_number=-1;
+static int errstop_enabled=0;
+static int fail_enabled=0;
+static int l4_opt=0;
+static int selective_trigger=0;
+static int dump_block_addrs_opt=0;
+static lock_t errlock=NOLOCK;
+static private_t init_private[LLSC_MAXCPUS];
+
+static int __init autotest_enable(char *str)
+{
+        autotest_enabled = 1;
+	return 1;
+}
+static int __init set_llscblkadr(char *str)
+{
+	dump_block_addrs_opt = 1;
+	return 1;
+}
+static int __init set_llscselt(char *str)
+{
+	selective_trigger = 1;
+	return 1;
+}
+static int __init set_llsctest(char *str)
+{
+        llsctest_number = simple_strtol(str, &str, 10);
+	if (llsctest_number < 0 || llsctest_number > 15)
+		llsctest_number = -1;
+	return 1;
+}
+static int __init set_llscerrstop(char *str)
+{
+        errstop_enabled = 1;
+	return 1;
+}
+static int __init set_llscfail(char *str)
+{
+        fail_enabled = 8;
+	return 1;
+}
+static int __init set_llscl4(char *str)
+{
+        l4_opt = 1;
+	return 1;
+}
+
+static void print_params(void)
+{
+	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
+	printk ("  Test options:\n");
+	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
+	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
+	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
+	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
+	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
+	printk ("     llscl4      \t%s\tRun only tests that evict from L4\n", l4_opt ? "on" : "off");
+	printk ("  SEMFIX: %s\n", IA64_SEMFIX);
+	printk ("\n");
+}
+__setup("autotest", autotest_enable);
+__setup("llsctest=", set_llsctest);
+__setup("llscerrstop", set_llscerrstop);
+__setup("llscfail", set_llscfail);
+__setup("llscselt", set_llscselt);
+__setup("llscblkadr", set_llscblkadr);
+__setup("llscl4", set_llscl4);
+
+
+
+static inline int
+set_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_acq(lock, NOLOCK, id);
+	return (old == NOLOCK);
+}
+
+static inline int
+clr_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_rel(lock, id, NOLOCK);
+	return (old == id);
+}
+
+static inline void
+init_lock(uint *lock)
+{
+	*lock = NOLOCK;
+}
+
+/*------------------------------------------------------------------------+
+| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
+| Description: This test checks the coherency of shared data              |
++------------------------------------------------------------------------*/
+static unsigned int
+ran_conf_llsc(int thread)
+{
+	private_t	pval;
+	share_t		sval, sval2;
+	uint		vv, linei, slinei, sharei, pass;
+	long		t;
+	lock_t		lockpat;
+	share_t		*sharecopy;
+	long		verbose, napticks, passes, linecount, lcount;
+	dataline_t	*linep, *slinep;
+	int		s, seed;
+	threadprivate_t	*tp;
+	uint		iter_msg, iter_msg_i=0;
+	int		vv_mask;
+	int		correct_errors;
+	int		errs=0;
+	int		stillbad;
+	capture_t	capdata;
+	private_t	*privp;
+	share_t		*sharep;
+
+
+	linecount = k_linecount;
+	napticks = k_napticks;
+	verbose = k_verbose;
+	passes = k_passes;
+	iter_msg = k_iter_msg;
+	seed = (thread + 1) * 647;
+	tp = THREADPRIVATE(thread);
+	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
+	correct_errors = k_options&0xff;
+
+	memset (&capdata, 0, sizeof(capdata));
+	for (linei=0; linei<linecount; linei++)
+		tp->private[linei] = thread;	
+
+	for (pass = 1; passes == 0 || pass < passes; pass++) {
+		lockpat = (pass & 0x0fffffff) + (thread <<28);
+		if (lockpat == NOLOCK)
+			continue;
+		tp->threadpasses = pass;
+		if (checkstop(thread, pass, lockpat))
+			return 0;
+		iter_msg_i++;
+		if (iter_msg && iter_msg_i > iter_msg) {
+			printk("Thread %d, Pass %d\n", thread, pass);
+			iter_msg_i = 0;
+		}
+		lcount = 0;
+
+		/*
+		 * Select line to perform operations on.
+		 */
+		linei = randn(linecount, &seed);
+		sharei = randn(2, &seed);
+		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
+
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+		if (sharei == 0)
+			sharecopy = &slinep->share0;
+		else
+			sharecopy = &slinep->share1;
+
+
+		vv = randn(4, &seed);
+		if ((vv_mask & (1<<vv)) == 0)
+			continue;
+
+		if (napticks) {
+			t = randn(napticks, &seed);
+			udelay(t);
+		}
+		privp = &linep->private[thread];
+		sharep = &linep->share[sharei];
+		
+		switch(vv) {
+		case 0:
+			/* Read and verify private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors) {
+					tp->private[linei] = *privp;
+				}
+				errs++;
+			}
+			break;
+
+		case 1:
+			/* Read, verify, and increment private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+			pval = (pval==255) ? 0 : pval+1;
+			*privp = pval;
+			tp->private[linei] = pval;
+			break;
+
+		case 2:
+			/* Lock line, read and verify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (pass > 12 && thread == 0 && fail_enabled == 1)
+				sval++;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors)
+					*sharep = *sharecopy;
+				errs++;
+			}
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+
+		case 3:
+			/* Lock line, read and verify shared data, modify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+
+			*sharep = lockpat;
+			*sharecopy = lockpat;
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+		}
+	}
+
+	return (errs > 0);
+}
+
+static void
+trigger_la(long val)
+{
+	long	*p;
+
+	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
+	*p = val;
+}
+
+static long
+getsynerr(void)
+{
+	long	err, *errp;
+
+	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
+	err = *errp;
+	if (err)
+		*errp = -1L;
+	return (err & ~0x60);
+}
+
+static int
+rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int badlinei, int exp, int found, int stillbad)
+{
+	int		cpu, i, linei;
+	long 		synerr;
+	int		selt;
+
+
+	selt = selective_trigger && stillbad > 1 && 
+			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
+			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
+	if (selt) {
+		trigger_la(pass);
+	} else if (selective_trigger) {
+		k_go = ST_STOP;
+		return k_stop_on_error;;
+	}
+
+	spin(1);
+	i = 100;
+	while (i && set_lock(&errlock, 1) != 1) {
+		spin(1);
+		i--;
+	}
+	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
+	    msg, k_testnumber, thread, badlinei, pass, pass, jiffies, exp, found);
+
+	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
+#ifdef ZZZ
+	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
+		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
+#endif
+
+	if (cap->shadaddr) {
+		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
+#ifdef ZZZ
+		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
+			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
+#endif
+	}
+	
+	printk("Threadpasses: ");
+	for (cpu=0,i=0; cpu<LLSC_MAXCPUS; cpu++)
+		if (k_threadprivate[cpu]->threadpasses) {
+			if (i && (i%8) == 0)
+				printk("\n            : ");
+			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
+			i++;
+		}
+	printk("\n");
+	
+	for (linei=0; linei<k_linecount; linei++) {
+		int		slinei, g1linei, g2linei, g1err, g2err, sh0err, sh1err;
+		dataline_t	*linep, *slinep;
+
+		slinei = (linei + (k_linecount/2))%k_linecount;
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+
+		g1linei = GUARDLINE(linep->guard1);
+		g2linei = GUARDLINE(linep->guard2);
+		g1err = (g1linei != linei);
+		g2err = (g2linei != linei);
+		sh0err = (linep->share[0] != slinep->share0);
+		sh1err = (linep->share[1] != slinep->share1);
+
+		if (g1err || g2err || sh0err || sh1err) {
+			printk("Line 0x%lx (%03d), %sG1 0x%lx (%03d), %sG2 0x%lx (%03d), %sSH0 %08x (%08x), %sSH1 %08x (%08x)\n",
+				blocks[linei], linei, 
+				g1err ? "*" : " ", blocks[g1linei], g1linei,
+				g2err ? "*" : " ", blocks[g2linei], g2linei,
+				sh0err ? "*" : " ", linep->share[0], slinep->share0,
+				sh1err ? "*" : " ", linep->share[1], slinep->share1);
+
+
+		}
+	}
+
+	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
+	synerr = getsynerr();
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	spin(2);
+	printk("\n\n");
+	clr_lock(&errlock, 1);
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	return k_stop_on_error;
+}
+
+
+static void
+dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
+{
+	long *p;
+	int i, off;
+
+	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
+	p = (long*) data;
+	for (i=0; i<48; i++, p++) {
+		if (i%8 == 0) printk("%2s", i==16 ? str2 : "  ");
+		printk(" %016lx", *p);
+		if ((i&7)==7) printk("\n");
+	}
+	printk("   ");
+	off = (((long)addr) ^ size) & 63L;
+	for (i=0; i<off+size; i++) {
+		printk("%s", (i>=off) ? "--" : "  ");
+		if ((i%8) == 7)
+			printk(" ");
+	}
+
+	off = ((long)addr) & 127;
+	printk(" (line %d)\n", 2+off/64+1);
+}
+
+
+static int
+randn(uint max, uint *seedp)
+{
+	if (max == 1)
+		return(0);
+	else
+		return((int)(zrandom(seedp)>>10) % max);
+}
+
+
+static int
+checkstop(int thread, int pass, uint lockpat)
+{
+	long	synerr;
+
+	if (k_go == ST_RUN)
+		return 0;
+	if (k_go == ST_STOP)
+		return 1;
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	synerr = getsynerr();
+	spin(2);
+	if (k_go == ST_STOP)
+		return 1;
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	return 1;
+}
+
+
+static void
+spin(int j)
+{
+	udelay(j * 500000);
+}
+
+static void
+capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
+{
+
+	if (!selective_trigger)
+		trigger_la (pass);
+
+	memcpy (cap->blockdata, CACHEALIGN(blockaddr)-128, 3*128);
+	if (shadaddr) 
+		memcpy (cap->shaddata, CACHEALIGN(shadaddr)-128, 3*128);
+
+	if (k_stop_on_error) {
+		k_go = ST_ERRSTOP;
+	}
+
+ 	cap->size = size;
+	cap->blockaddr = blockaddr;
+	cap->shadaddr = shadaddr;
+
+	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
+	ia64_sync_i();
+	ia64_srlz_d();
+	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr)-128, 3*128);
+
+	if (shadaddr) {
+		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
+		ia64_sync_i();
+		ia64_srlz_d();
+		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr)-128, 3*128);
+	}
+}
+
+int             zranmult = 0x48c27395;
+
+static uint  
+zrandom (uint *seedp)
+{
+        *seedp = (*seedp * zranmult) & 0x7fffffff;
+        return (*seedp);
+}
+
+
+void
+set_autotest_params(void)
+{
+	static int	testnumber=-1;
+
+	if (llsctest_number >= 0) {
+		testnumber = llsctest_number;
+	} else {
+		testnumber++;
+		if (autotest_table[testnumber].passes == 0) {
+			testnumber = 0;
+			dump_block_addrs_opt = 0;
+		}
+	}
+	if (testnumber == 0 && l4_opt) testnumber = 9;
+
+	k_passes = autotest_table[testnumber].passes;
+	k_linepad = autotest_table[testnumber].linepad;
+	k_linecount = autotest_table[testnumber].linecount;
+	k_testnumber = testnumber;
+
+	if (IS_RUNNING_ON_SIMULATOR()) {
+		printk ("llsc start test %ld\n", k_testnumber);
+		k_passes = 1000;
+	}
+}
+
+
+static void
+set_leds(int errs)
+{
+	unsigned char	leds=0;
+
+	/*
+	 * Leds are:
+	 * 	ppppeee-  
+	 *   where
+	 *      pppp = test number
+	 *       eee = error count but top bit is stick
+	 */
+
+	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
+	set_led_bits(leds, LED_MASK_AUTOTEST);
+}
+
+static void
+setup_block_addresses(void)
+{
+	int			i, stride, memmapi;
+	dataline_t		*dp;
+	long			*ip, *ipe;
+
+
+	stride = k_linepad + sizeof(dataline_t);
+	memmapi = 0;
+	for (i=0; i<memmapx; i++) {
+		memmap[i].nextaddr = memmap[i].vstart;
+		memmap[i].nextinit = memmap[i].vstart;
+		memmap[i].wrapcount = 0;
+	}
+
+	for (i=0; i<k_linecount; i++) {
+		blocks[i] = memmap[memmapi].nextaddr;
+		dp = (dataline_t*)blocks[i];
+		memmap[memmapi].nextaddr += (stride & 0xffff);
+		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
+			memmap[memmapi].wrapcount++;
+			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
+					memmap[memmapi].wrapcount * sizeof(dataline_t);
+		}
+
+		ip = (long*)((memmap[memmapi].nextinit+7)&~7);
+		ipe = (long*)(memmap[memmapi].nextaddr+2*sizeof(dataline_t)+8);
+		while(ip <= ipe && ip < ((long*)memmap[memmapi].vend-8))
+			*ip++ = (long)ip;
+		memmap[memmapi].nextinit = (long) ipe;
+		dp->guard1 = BGUARD(i);
+		dp->guard2 = EGUARD(i);
+		dp->lock[0] = dp->lock[1] = NOLOCK;
+		dp->share[0] = dp->share0 = 0x1111;
+		dp->share[1] = dp->share1 = 0x2222;
+		memcpy(dp->private, init_private, LLSC_MAXCPUS*sizeof(private_t));
+
+
+		if (stride > 16384) {
+			memmapi++;
+			if (memmapi == memmapx)
+				memmapi = 0;
+		}
+	}
+
+}
+
+static void
+dump_block_addrs(void)
+{
+	int	i;
+
+	printk("LLSC TestNumber %ld\n", k_testnumber);
+
+	for (i=0; i<k_linecount; i++) {
+		printk("  %lx", blocks[i]);
+		if (i%4 == 3)
+			printk("\n");
+	}
+	printk("\n");
+}
+
+
+static void
+set_thread_state(int cpuid, int state)
+{
+	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
+		set_led_bits(LED_MASK_AUTOTEST, LED_MASK_AUTOTEST);
+		while(1);
+	}
+	k_threadprivate[cpuid]->threadstate = state;
+}
+
+static int
+build_mem_map(unsigned long start, unsigned long end, void *arg)
+{
+	long	lstart;
+	long	align = 8*MB;
+
+	/*
+	 * HACK - skip the kernel on the first node 
+	 */
+
+	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
+		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
+
+	if (memmapx >= MAPCHUNKS)
+		return 0;
+	while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0))
+		end -= PAGE_SIZE;
+
+	lstart = end;
+	while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0))
+		lstart -= PAGE_SIZE;
+
+	lstart = (lstart + align -1) /align * align;
+	end = end / align * align;
+	if (lstart >= end)
+		return 0;
+	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
+
+	memmap[memmapx].vstart = lstart;
+	memmap[memmapx].vend = end;
+	memmapx++;
+	return 0;
+}
+
+void int_test(void);
+
+int
+llsc_main (int cpuid, long mbasex)
+{
+	int		i, cpu, is_master, repeatcnt=0;
+	unsigned int	preverr=0, errs=0, pass=0;
+	int		automode=0;
+
+#ifdef INTTEST
+	if (inttest)
+		int_test();
+#endif
+
+	if (!autotest_enabled)
+		return 0;
+
+#ifdef CONFIG_SMP
+	is_master = !smp_processor_id();
+#else
+	is_master = 1;
+#endif
+
+
+	if (is_master) {
+		print_params();
+		if(!IS_RUNNING_ON_SIMULATOR())
+			spin(10);
+		mbase = (control_t*)mbasex;
+		k_currentpass = 0;
+		k_go = ST_IDLE;
+		k_passes = DEF_PASSES;
+		k_napticks = DEF_NAPTICKS;
+		k_stop_on_error = DEF_STOP_ON_ERROR;
+		k_verbose = DEF_VERBOSE;
+		k_linecount = DEF_LINECOUNT;
+		k_iter_msg = DEF_ITER_MSG;
+		k_vv = DEF_VV;
+		k_linepad = DEF_LINEPAD;
+		k_blocks = (void*)blocks;
+		efi_memmap_walk(build_mem_map, 0);
+	
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+		automode = 1;
+#endif
+
+		for (i=0; i<LLSC_MAXCPUS; i++) {
+			k_threadprivate[i] = THREADPRIVATE(i);
+			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
+			init_private[i] = i;
+		}
+		initialized = 1;
+	} else {
+		while (initialized == 0)
+			udelay(100);
+	}
+
+loop:
+	if (is_master) {
+		if (automode) {
+			if (!preverr || repeatcnt++ > 5) {
+				set_autotest_params();
+				repeatcnt = 0;
+			}
+		} else {
+			while (k_go == ST_IDLE);
+		}
+
+		k_go = ST_INIT;
+		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
+		k_linecount = k_linecount & ~1;
+		setup_block_addresses();
+		if (!preverr && dump_block_addrs_opt)
+			dump_block_addrs();
+
+		k_currentpass = pass++;
+		k_go = ST_RUN;
+		if (fail_enabled)
+			fail_enabled--;
+
+	} else {
+		while (k_go != ST_RUN || k_currentpass != pass);
+		pass++;
+	}
+
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_RUNNING);
+
+	errs += ran_conf_llsc(cpuid);
+	preverr = (k_go == ST_ERRSTOP);
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_STOPPED);
+
+	if (is_master) {
+		Speedo();
+		for (i=0, cpu=0; cpu<LLSC_MAXCPUS; cpu++) {
+			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
+				i++;
+				if (i == 10000) { 
+					k_go = ST_STOP;
+					printk ("  llsc master stopping test number %ld\n", k_testnumber);
+				}
+				if (i > 100000) {
+					k_threadprivate[cpu]->threadstate = TS_KILLED;
+					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
+							cpu, k_testnumber);
+				}
+				udelay(1000);
+			}
+		}
+	}
+
+	goto loop;
+}
+
+
+static void
+Speedo(void)
+{
+	static int i = 0;
+
+	switch (++i%4) {
+	case 0:
+		printk("|\b");
+		break;
+	case 1:
+		printk("\\\b");
+		break;
+	case 2:
+		printk("-\b");
+		break;
+	case 3:
+		printk("/\b");
+		break;
+	}
+}
+
+#ifdef INTTEST
+
+/* ======================================================================================================== 
+ *
+ * Some test code to verify that interrupts work
+ *
+ * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
+ * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
+ *
+ * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
+ *
+ */
+
+static int __init set_inttest(char *str)
+{
+        inttest = 1;
+	autotest_enabled = 1;
+
+	return 1;
+}	
+
+__setup("inttest=", set_inttest);
+
+int	zzzprint_resched=0;
+
+void
+int_test() {
+	int			mycpu, cpu;
+	static volatile int	control_cpu=0;
+
+	mycpu = smp_processor_id();
+	zzzprint_resched = 2;
+
+	printk("Testing cross interrupts\n");
+	
+	while (control_cpu != smp_num_cpus) {
+		if (mycpu == cpu_logical_map(control_cpu)) {
+			for (cpu=0; cpu<smp_num_cpus; cpu++) {
+				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+			}
+			control_cpu++;
+		}
+	}
+
+	zzzprint_resched = 1;
+
+	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
+		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
+		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
+		__cli();
+		while (1) {
+			smp_send_reschedule(0);
+			udelay(100);
+		}
+
+	}
+
+	while(1);
+}
+#endif
diff -urN linux-2.4.16/arch/ia64/sn/kernel/llsc4.h lia64-2.4/arch/ia64/sn/kernel/llsc4.h
--- linux-2.4.16/arch/ia64/sn/kernel/llsc4.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/llsc4.h	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,107 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+
+#define DEF_NAPTICKS		0
+#define DEF_PASSES		0
+#define DEF_AUTO_PASSES		1000000
+#define DEF_STOP_ON_ERROR	1
+#define DEF_VERBOSE		0
+#define DEF_LINECOUNT		2
+#define DEF_ITER_MSG		0
+#define DEF_VV			0xffffffff
+#define DEF_LINEPAD		0x234
+
+
+
+#define LLSC_MAXCPUS		64
+#define CACHELINE		64
+#define MAX_LINECOUNT		1024
+#define K			1024
+#define	MB			(K*K)
+
+
+#define	uint 		unsigned int
+#define	ushort		unsigned short
+#define	uchar		unsigned char
+#define vint		volatile int
+#define vlong		volatile long
+
+#define LOCKADDR(i)	&linep->lock[(i)]
+#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
+#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
+#define GETLOCK(i)	*LOCKADDR(i)
+#define ZEROLOCK(i)	init_lock(LOCKADDR(i))
+
+#define CACHEALIGN(a)	((char*)((long)(a) & ~127L))
+
+typedef uint		guard_t;
+typedef uint		lock_t;
+typedef uint		share_t;
+typedef uchar		private_t;
+
+typedef struct {
+	guard_t		guard1;
+	lock_t		lock[2];
+	share_t		share[2];
+	private_t	private[LLSC_MAXCPUS];
+	share_t		share0;
+	share_t		share1;
+	guard_t		guard2;
+} dataline_t ;
+
+
+#define LINEPAD			k_linepad
+#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
+
+
+typedef struct {
+	vint		threadstate;
+	uint		threadpasses;
+	private_t	private[MAX_LINECOUNT];
+} threadprivate_t;
+
+typedef struct {
+	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
+	long		sk_linecount;
+	long		sk_passes;
+	long		sk_napticks;
+	long		sk_stop_on_error;
+	long		sk_verbose;
+	long		sk_iter_msg;
+	long		sk_vv;
+	long		sk_linepad;
+	long		sk_options;
+	long		sk_testnumber;
+	vlong		sk_currentpass;
+	void 		*sk_blocks;
+	threadprivate_t	*sk_threadprivate[LLSC_MAXCPUS];
+} control_t;
+
+/* Run state (k_go) constants */
+#define ST_IDLE		0
+#define ST_INIT		1
+#define ST_RUN		2
+#define ST_STOP		3
+#define ST_ERRSTOP	4
+
+
+/* Threadstate constants */
+#define TS_STOPPED	0
+#define	TS_RUNNING	1
+#define TS_KILLED	2
+
+
+
+int llsc_main (int cpuid, long mbasex);
+
diff -urN linux-2.4.16/arch/ia64/sn/kernel/machvec.c lia64-2.4/arch/ia64/sn/kernel/machvec.c
--- linux-2.4.16/arch/ia64/sn/kernel/machvec.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/machvec.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,18 @@
+#define MACHVEC_PLATFORM_NAME	sn1
+#include <asm/machvec_init.h>
+#include <asm/io.h>
+#include <linux/pci.h>
+void*
+sn1_mk_io_addr_MACRO
+
+dma_addr_t
+sn1_pci_map_single_MACRO
+
+int
+sn1_pci_map_sg_MACRO
+
+unsigned long
+sn1_virt_to_phys_MACRO
+
+void *
+sn1_phys_to_virt_MACRO
diff -urN linux-2.4.16/arch/ia64/sn/kernel/mca.c lia64-2.4/arch/ia64/sn/kernel/mca.c
--- linux-2.4.16/arch/ia64/sn/kernel/mca.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/mca.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,254 @@
+/*
+ * File:	mca.c
+ * Purpose:	SN specific MCA code.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc.
+ * Copyright (C) Alan Mayer (ajm@sgi.com)
+ *
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp_lock.h>
+
+#include <asm/machvec.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/mca.h>
+#include <asm/sn/mca.h>
+
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/acpi-ext.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+
+
+// This is a dummy so that ia64/kernel/mca.c will compile.
+// This struct is never actually used in SN code.
+struct hw_interrupt_type irq_type_iosapic_level;
+
+static char *shub_mmr_names[] = {
+	"sh_event_occurred",
+	"sh_first_error",
+	"sh_event_overflow",
+
+/* PI */
+	"sh_pi_first_error",
+	"sh_pi_error_summary",
+	"sh_pi_error_overflow",
+
+/* PI HW */
+	"sh_pi_error_detail_1",
+	"sh_pi_error_detail_2",
+	"sh_pi_hw_time_stamp",
+
+/* PI UCE */
+	"sh_pi_uncorrected_detail_1",
+	"sh_pi_uncorrected_detail_2",
+	"sh_pi_uncorrected_detail_3",
+	"sh_pi_uncorrected_detail_4",
+	"sh_pi_uncor_time_stamp",
+
+/* PI CE */
+	"sh_pi_corrected_detail_1",
+	"sh_pi_corrected_detail_2",
+	"sh_pi_corrected_detail_3",
+	"sh_pi_corrected_detail_4",
+	"sh_pi_cor_time_stamp",
+
+/* MD */
+	"sh_mem_error_summary",
+	"sh_mem_error_overflow",
+/* MD HW */
+	"sh_misc_err_hdr_upper",
+	"sh_misc_err_hdr_lower",
+	"sh_md_dqlp_mmr_xperr_val",
+	"sh_md_dqlp_mmr_yperr_val",
+	"sh_md_dqrp_mmr_xperr_val",
+	"sh_md_dqrp_mmr_yperr_val",
+	"sh_md_hw_time_stamp",
+
+/* MD UCE */
+	"sh_dir_uc_err_hdr_lower",
+	"sh_dir_uc_err_hdr_upper",
+	"sh_md_dqlp_mmr_xuerr1",
+	"sh_md_dqlp_mmr_xuerr2",
+	"sh_md_dqlp_mmr_yuerr1",
+	"sh_md_dqlp_mmr_yuerr2",
+	"sh_md_dqrp_mmr_xuerr1",
+	"sh_md_dqrp_mmr_xuerr2",
+	"sh_md_dqrp_mmr_yuerr1",
+	"sh_md_dqrp_mmr_yuerr2",
+	"sh_md_uncor_time_stamp",
+
+/* MD CE */
+	"sh_dir_cor_err_hdr_lower",
+	"sh_dir_cor_err_hdr_upper",
+	"sh_md_dqlp_mmr_xcerr1",
+	"sh_md_dqlp_mmr_xcerr2",
+	"sh_md_dqlp_mmr_ycerr1",
+	"sh_md_dqlp_mmr_ycerr2",
+	"sh_md_dqrp_mmr_xcerr1",
+	"sh_md_dqrp_mmr_xcerr2",
+	"sh_md_dqrp_mmr_ycerr1",
+	"sh_md_dqrp_mmr_ycerr2",
+	"sh_md_cor_time_stamp",
+
+/* MD CE, UCE */
+	"sh_md_dqls_mmr_xamopw_err",
+	"sh_md_dqrs_mmr_yamopw_err",
+
+/* XN */
+	"sh_xn_error_summary",
+	"sh_xn_first_error",
+	"sh_xn_error_overflow",
+
+/* XN HW */
+	"sh_xniilb_error_summary",
+	"sh_xniilb_first_error",
+	"sh_xniilb_error_overflow",
+	"sh_xniilb_error_detail_1",
+	"sh_xniilb_error_detail_2",
+	"sh_xniilb_error_detail_3",
+
+	"sh_ni0_error_summary_1",
+	"sh_ni0_first_error_1",
+	"sh_ni0_error_overflow_1",
+
+	"sh_ni0_error_summary_2",
+	"sh_ni0_first_error_2",
+	"sh_ni0_error_overflow_2",
+	"sh_ni0_error_detail_1",
+	"sh_ni0_error_detail_2",
+	"sh_ni0_error_detail_3",
+
+	"sh_ni1_error_summary_1",
+	"sh_ni1_first_error_1",
+	"sh_ni1_error_overflow_1",
+
+	"sh_ni1_error_summary_2",
+	"sh_ni1_first_error_2",
+	"sh_ni1_error_overflow_2",
+
+	"sh_ni1_error_detail_1",
+	"sh_ni1_error_detail_2",
+	"sh_ni1_error_detail_3",
+
+	"sh_xn_hw_time_stamp",
+
+/* XN HW & UCE & SBE */
+	"sh_xnpi_error_summary",
+	"sh_xnpi_first_error",
+	"sh_xnpi_error_overflow",
+	"sh_xnpi_error_detail_1",
+
+	"sh_xnmd_error_summary",
+	"sh_xnmd_first_error",
+	"sh_xnmd_error_overflow",
+	"sh_xnmd_ecc_err_report",
+	"sh_xnmd_error_detail_1",
+
+/* XN UCE */
+	"sh_xn_uncorrected_detail_1",
+	"sh_xn_uncorrected_detail_2",
+	"sh_xn_uncorrected_detail_3",
+	"sh_xn_uncorrected_detail_4",
+	"sh_xn_uncor_time_stamp",
+
+/* XN CE */
+	"sh_xn_corrected_detail_1",
+	"sh_xn_corrected_detail_2",
+	"sh_xn_corrected_detail_3",
+	"sh_xn_corrected_detail_4",
+	"sh_xn_cor_time_stamp",
+
+/* LB HW */
+	"sh_lb_error_summary",
+	"sh_lb_first_error",
+	"sh_lb_error_overflow",
+	"sh_lb_error_detail_1",
+	"sh_lb_error_detail_2",
+	"sh_lb_error_detail_3",
+	"sh_lb_error_detail_4",
+	"sh_lb_error_detail_5",
+	"sh_junk_error_status",
+};
+
+void sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc) {
+	sal_log_plat_info_t *sh_info = (sal_log_plat_info_t *) p_data;
+	u64 *mmr_val = (u64 *)&(sh_info->shub_state);
+	char **mmr_name = shub_mmr_names;
+	int mmr_count = sizeof(sal_log_shub_state_t)>>3;
+
+	while(mmr_count) {
+		if(*mmr_val) {
+			prfunc("%-40s: %#016lx\n",*mmr_name, *mmr_val);
+		}
+		mmr_name++;
+		mmr_val++;
+		mmr_count--;
+	}
+
+}
+
+void
+sn_cpei_handler(int irq, void *devid, struct pt_regs *regs) {
+
+	struct ia64_sal_retval isrv;
+// this function's sole purpose is to call SAL when we receive
+// a CE interrupt from SHUB or when the timer routine decides
+// we need to call SAL to check for CEs.
+
+	// CALL SAL_LOG_CE
+	SAL_CALL(isrv, SN_SAL_LOG_CE, irq, 0, 0, 0, 0, 0, 0);
+}
+
+#include <linux/timer.h>
+
+#define CPEI_INTERVAL	(HZ/100)
+struct timer_list sn_cpei_timer;
+void sn_init_cpei_timer(void);
+
+void
+sn_cpei_timer_handler(unsigned long dummy) {
+	sn_cpei_handler(-1, NULL, NULL);
+	del_timer(&sn_cpei_timer);
+	sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_cpei_timer);
+}
+
+void
+sn_init_cpei_timer() {
+	sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_cpei_timer.function = sn_cpei_timer_handler;
+        add_timer(&sn_cpei_timer);
+}
+
+#ifdef ajmtestceintr
+
+struct timer_list sn_ce_timer;
+
+void
+sn_ce_timer_handler(long dummy) {
+	unsigned long *pi_ce_error_inject_reg = 0xc00000092fffff00;
+
+	*pi_ce_error_inject_reg = 0x0000000000000100;
+	del_timer(&sn_ce_timer);
+	sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_ce_timer);
+}
+
+sn_init_ce_timer() {
+	sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_ce_timer.function = sn_ce_timer_handler;
+        add_timer(&sn_ce_timer);
+}
+#endif // ajmtestceintr
diff -urN linux-2.4.16/arch/ia64/sn/kernel/misctest.c lia64-2.4/arch/ia64/sn/kernel/misctest.c
--- linux-2.4.16/arch/ia64/sn/kernel/misctest.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/misctest.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,122 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/processor.h>
+#include <asm/pgtable.h>
+
+
+extern	int autotest_enabled;
+int	mcatest=0;
+
+
+
+/* 
+ * mcatest
+ *	1 = expected MCA
+ *	2 = unexpected MCA
+ *	3 = expected MCA + unexpected MCA
+ *	4 = INIT
+ *	5 = speculative load to garbage memory address
+ *	6 = speculative load with ld8.s (needs poison hack in PROM)
+ *	7 = speculative load from mis-predicted branch (needs poison hack in PROM)
+ */
+static int __init set_mcatest(char *str)
+{
+	get_option(&str, &mcatest);
+	return 1;
+}
+
+__setup("mcatest=", set_mcatest);
+
+void
+sgi_mcatest(void)
+{
+	if (mcatest == 1 || mcatest == 3) {
+		long	*p, result, adrs[] = {0xc0000a000f021004UL, 0xc0000a000f026004UL, 0x800000000, 0x500000, 0};
+		long	size[] = {1,2,4,8};
+		int	r, i, j;
+		p = (long*)0xc000000000000000UL;
+		ia64_fc(p);
+		*p = 0x0123456789abcdefL;
+		for (i=0; i<5; i++) {
+			for (j=0; j<4; j++) {
+				printk("Probing 0x%lx, size %ld\n", adrs[i], size[j]);
+				result = -1;
+				r = ia64_sn_probe_io_slot (adrs[i], size[j], &result);
+				printk("    status %d, val 0x%lx\n", r, result); 
+			}
+		}
+	}
+	if (mcatest == 2 || mcatest == 3) {
+		void zzzmca(int, int, int);
+		printk("About to cause unexpected MCA\n");
+		zzzmca(mcatest, 0x32dead, 0x33dead);
+	}
+	if (mcatest == 4) {
+		long	*p;
+		int	delivery_mode = 5;
+		printk("About to try to cause an INIT on cpu 0\n");
+		p = (long*)((0xc0000a0000000000LL | ((long)get_nasid())<<33) | 0x1800080);
+		*p = (delivery_mode << 8);
+		udelay(10000);
+		printk("Returned from INIT\n");
+	}
+	if (mcatest == 5) {
+		int zzzspec(long);
+		int	i;
+		long	flags, dcr, res, val, addr=0xff00000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("Default DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+			printk("New     DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(dcr);
+			res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val);
+			printk("zzzspec: probe %ld, 0x%lx\n", res, val);
+			ia64_clear_ic(flags);
+			ia64_itc(0x2, 0xe00000ff00000000UL,
+			          pte_val(mk_pte_phys(0xff00000000UL,
+				  __pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M);
+			local_irq_restore(flags);
+			ia64_srlz_i ();
+		}
+
+	}
+	if (mcatest == 6) {
+		int zzzspec(long);
+		int	i;
+		long	dcr, addr=0xe000000008000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+		}
+		ia64_set_dcr(dcr);
+	}
+	if (mcatest == 7) {
+		int zzzspec2(long, long);
+		int	i;
+		long	addr=0xe000000008000000UL;
+		long	addr2=0xe000000007000000UL;
+
+		for (i=0; i<5; i++) {
+			printk("zzzspec2\n");
+			zzzspec2(addr, addr2);
+		}
+	}
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/probe.c lia64-2.4/arch/ia64/sn/kernel/probe.c
--- linux-2.4.16/arch/ia64/sn/kernel/probe.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/probe.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,61 @@
+/*
+ * Platform dependent support for IO probing.
+ *
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <asm/sn/sn_sal.h>
+
+/*
+ * ia64_sn_probe_io_slot
+ *	This function will probe a physical address to determine if
+ *	the address can be read. If reading the address causes a BUS
+ *	error, an error is returned. If the probe succeeds, the contents 
+ *	of the memory location is returned.
+ *
+ *   Calling sequence:
+ *		ia64_probe_io_slot(paddr, size, data_ptr)
+ *
+ *   Input:
+ *	paddr		Physical address to probe
+ *	size		Number bytes to read (1,2,4,8)
+ *	data_ptr	Address to store value read by probe
+ *		          (-1 returned if probe fails)
+ *
+ *   Output:
+ *	Status
+ *		 0 - probe successful
+ *		 1 - probe failed (generated MCA)
+ *		 2 - Bad arg
+ *		<0 - PAL error
+ */
+
+
+u64
+ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
+{
+	struct ia64_sal_retval isrv;
+
+	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
+
+	if (data_ptr) {
+		switch (size) {
+			case 1:
+				*((u8*)data_ptr) = (u8)isrv.v0;
+				break;
+			case 2:
+				*((u16*)data_ptr) = (u16)isrv.v0;
+				break;
+			case 4:
+				*((u32*)data_ptr) = (u32)isrv.v0;
+				break;
+			case 8:
+				*((u64*)data_ptr) = (u64)isrv.v0;
+				break;
+			default:
+				isrv.status = 2;	
+		}
+	}
+
+	return isrv.status;
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/setup.c lia64-2.4/arch/ia64/sn/kernel/setup.c
--- linux-2.4.16/arch/ia64/sn/kernel/setup.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/setup.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,342 @@
+/*
+ *
+ * Copyright (C) 1999,2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/console.h>
+#include <linux/timex.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/serial.h>
+#include <linux/irq.h>
+#include <linux/bootmem.h>
+#include <linux/mmzone.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/sal.h>
+#include <asm/machvec.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/shub.h>
+#endif
+
+void platform_smp_callin(int);
+long sn_rtc_cycles_per_second;   
+
+/*
+ * This is the address of the RRegs in the HSpace of the global
+ * master.  It is used by a hack in serial.c (serial_[in|out],
+ * printk.c (early_printk), and kdb_io.c to put console output on that
+ * node's Bedrock UART.  It is initialized here to 0, so that
+ * early_printk won't try to access the UART before
+ * master_node_bedrock_address is properly calculated.
+ */
+#ifdef BRINGUP
+u64 master_node_bedrock_address = 0UL;
+#endif
+
+static void sn_init_pdas(void);
+
+extern struct irq_desc *_sn1_irq_desc[];
+
+#if defined(CONFIG_IA64_SGI_SN1)
+extern synergy_da_t	*Synergy_da_indr[];
+#endif
+
+static nodepda_t	*nodepdaindr[MAX_COMPACT_NODES];
+
+#ifdef CONFIG_IA64_SGI_SN2
+irqpda_t		*irqpdaindr[NR_CPUS];
+#endif /* CONFIG_IA64_SGI_SN2 */
+
+
+/*
+ * The format of "screen_info" is strange, and due to early i386-setup
+ * code. This is just enough to make the console code think we're on a
+ * VGA color display.
+ */
+struct screen_info sn1_screen_info = {
+	orig_x:			 0,
+	orig_y:			 0,
+	orig_video_mode:	 3,
+	orig_video_cols:	80,
+	orig_video_ega_bx:	 3,
+	orig_video_lines:	25,
+	orig_video_isVGA:	 1,
+	orig_video_points:	16
+};
+
+/*
+ * This is here so we can use the CMOS detection in ide-probe.c to
+ * determine what drives are present.  In theory, we don't need this
+ * as the auto-detection could be done via ide-probe.c:do_probe() but
+ * in practice that would be much slower, which is painful when
+ * running in the simulator.  Note that passing zeroes in DRIVE_INFO
+ * is sufficient (the IDE driver will autodetect the drive geometry).
+ */
+char drive_info[4*16];
+
+unsigned long
+sn1_map_nr (unsigned long addr)
+{
+	return MAP_NR_DISCONTIG(addr);
+}
+
+#if defined(BRINGUP) && defined(CONFIG_IA64_EARLY_PRINTK)
+void __init
+early_sn1_setup(void)
+{
+#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	if ( IS_RUNNING_ON_SIMULATOR() )
+#endif
+	{
+#ifdef CONFIG_IA64_SGI_SN2
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#endif
+		printk("early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
+	}
+}
+#endif /* BRINGUP && CONFIG_IA64_EARLY_PRINTK */
+
+extern void ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs);
+static struct irqaction mca_cpe_irqaction = {
+        handler:    ia64_mca_cpe_int_handler,
+        flags:      SA_INTERRUPT,
+        name:       "cpe_hndlr"
+};
+
+extern nasid_t master_nasid;
+
+void __init
+sn1_setup(char **cmdline_p)
+{
+	long	status, ticks_per_sec, drift;
+	int i;
+
+#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	struct serial_struct req;
+#endif
+
+	master_nasid = get_nasid();
+
+	status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift);
+	if (status != 0 || ticks_per_sec < 100000)
+		printk("WARNING: unable to determine platform RTC clock frequency\n");
+	else
+		sn_rtc_cycles_per_second = ticks_per_sec;
+		
+	for (i=0;i<NR_CPUS;i++)
+		_sn1_irq_desc[i] = _irq_desc;
+
+	register_percpu_irq(IA64_PCE_VECTOR, &mca_cpe_irqaction);
+	if (ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, IA64_PCE_VECTOR, 0, 0)) {
+                printk("sn1_setup : failed to register Corrected "
+                       "Platform Error interrupt vector with SAL.\n");
+        }
+
+
+#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	if ( IS_RUNNING_ON_SIMULATOR() )
+#endif
+	{
+#ifdef CONFIG_IA64_SGI_SN2
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#endif
+		printk("sn1_setup: setting master_node_bedrock_address to 0x%lx\n",
+		   	master_node_bedrock_address);
+	}
+
+#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	/*
+	 * We do early_serial_setup() to clean out the rs-table[] from the
+	 * statically compiled in version.
+	 */
+	memset(&req, 0, sizeof(struct serial_struct));
+	req.line = 0;
+	req.baud_base = 124800;
+	req.port = 0;
+	req.port_high = 0;
+	req.irq = 0;
+	req.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
+	req.io_type = SERIAL_IO_MEM;
+	req.hub6 = 0;
+#ifdef CONFIG_IA64_SGI_SN2
+	req.iomem_base = (u8 *)(master_node_bedrock_address);
+#else
+	req.iomem_base = (u8 *)(master_node_bedrock_address + 0x80);
+#endif
+	req.iomem_reg_shift = 3;
+	req.type = 0;
+	req.xmit_fifo_size = 0;
+	req.custom_divisor = 0;
+	req.closing_wait = 0;
+	early_serial_setup(&req);
+#endif /* CONFIG_SERIAL && !CONFIG_SERIAL_SGI_L1_PROTOCOL */
+
+	ROOT_DEV = to_kdev_t(0x0301);		/* default to first IDE drive */
+
+	/*
+	 * Create the PDAs and NODEPDAs for all the cpus.
+	 */
+	sn_init_pdas();
+
+#ifdef CONFIG_SMP
+	init_smp_config();
+#endif
+	screen_info = sn1_screen_info;
+}
+
+
+
+
+
+/*
+ * One-time setup for Node Data Area.
+ */
+void
+sn_init_pdas(void)
+{
+	cnodeid_t	cnode;
+
+	/*
+	 * Make sure that the PDA fits entirely in the same page as the 
+	 * cpu_data area.
+	 */
+	if ((PDAADDR&~PAGE_MASK)+sizeof(pda_t) > PAGE_SIZE)
+		panic("overflow of cpu_data page");
+
+        /*
+         * Allocate & initalize the nodepda for each node.
+         */
+        for (cnode=0; cnode<num_compact_nodes; cnode++) {
+	    nodepdaindr[cnode] = alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
+	    memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    Synergy_da_indr[cnode * 2] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+	    Synergy_da_indr[cnode * 2 + 1] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+	    memset(Synergy_da_indr[cnode * 2], 0, sizeof(synergy_da_t));
+	    memset(Synergy_da_indr[cnode * 2 + 1], 0, sizeof(synergy_da_t));
+#endif
+        }
+
+	/*
+	 * Now copy the array of nodepda pointers to each nodepda.
+	 */
+        for (cnode=0; cnode<num_compact_nodes; cnode++)
+		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, sizeof(nodepdaindr));
+
+
+	/* 
+	 * For the bootcpu, we do this here. All other cpus will make the
+	 * call as part of smp_callin initialization.
+	 */
+	platform_smp_callin(smp_processor_id());
+
+	/*
+	 * Set up IO related platform-dependent nodepda fields.
+	 * The following routine actually sets up the hubinfo struct
+	 * in nodepda.
+	 */
+	for (cnode = 0; cnode < num_compact_nodes; cnode++) 
+		init_platform_nodepda(nodepdaindr[cnode], cnode);
+}
+
+/*
+ * platform_smp_callin
+ *
+ * Called during cpu initialization on each cpu as it starts.
+ * Currently, initializes the per-cpu data area for SNIA.
+ * Also setup up a few fields in the nodepda.
+ */
+void __init
+platform_smp_callin(int cpuid)
+{
+	int	cpuphyid;
+	int	nasid;
+	int	slice;
+	int	cnode;
+
+	cpuphyid = ((ia64_get_lid() >> 16) & 0xffff);
+	nasid = cpu_physical_id_to_nasid(cpuphyid);
+	cnode = nasid_to_cnodeid(nasid);
+	slice = cpu_physical_id_to_slice(cpuphyid);
+
+	pda.p_nodepda = nodepdaindr[cnode];
+	pda.led_address = (long*) (LED0 + (slice<<LED_CPU_SHIFT));
+	pda.led_state = 0;
+	pda.hb_count = HZ/2;
+	pda.hb_state = 0;
+	pda.idle_flag = 0;
+	
+	if (nodepda->node_num_cpus == 0)
+		nodepda->node_first_cpu = cpuid;
+	nodepda->node_num_cpus++;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	{
+		int	synergy;
+		synergy = cpu_physical_id_to_synergy(cpuphyid);
+		pda.p_subnodepda = &nodepdaindr[cnode]->snpda[synergy];
+	}
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+	/*
+	 * We must use different memory allocators for first cpu (bootmem allocator)
+	 * than for the other cpus (regular allocator).
+	 */
+	if (cpuid == 0)
+		irqpdaindr[cpuid] = alloc_bootmem_node(NODE_DATA(cpuid_to_cnodeid(cpuid)),sizeof(irqpda_t));
+	else
+		irqpdaindr[cpuid] = page_address(alloc_pages_node(numa_node_id(), GFP_KERNEL, get_order(sizeof(irqpda_t))));
+	memset(irqpdaindr[cpuid], 0, sizeof(irqpda_t));
+	pda.p_irqpda = irqpdaindr[cpuid];
+#endif
+}
+
+
+/*
+ * cnodeid_to_cpuid - convert a cnode  to a cpuid of a cpu on the node.
+ *      returns -1 if no cpus exist on the node
+ *	
+ *	NOTE: BRINGUP ZZZ this is NOT a good way to find cpus on the node. Need a 
+ *	      better way!!
+ */
+
+int
+cnodeid_to_cpuid(int cnode) {
+	int cpu;
+
+	for (cpu = 0; cpu < smp_num_cpus; cpu++)
+		if (cpuid_to_cnodeid(cpu) == cnode)
+			break;
+
+	if (cpu == smp_num_cpus) 
+		cpu = -1;
+
+	return cpu;
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/Makefile lia64-2.4/arch/ia64/sn/kernel/sn1/Makefile
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/Makefile	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/Makefile	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,26 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001 Silicon Graphics, Inc. All rights reserved.
+#
+
+EXTRA_CFLAGS	:= -DSN -I. -DBRINGUP \
+		   -DNUMA_BASE -DSIMULATED_KLGRAPH \
+		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN
+# -DSN1_IOPORTS
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn1.a
+
+O_TARGET        = sn1.a
+export-objs	:= sn1_ksyms.o
+
+obj-y          = cache.o error.o iomv.o synergy.o sn1_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/cache.c lia64-2.4/arch/ia64/sn/kernel/sn1/cache.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/cache.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/cache.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,84 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <asm/pgalloc.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/delay.h>
+
+#ifndef MB
+#define	MB	(1024*1024)
+#endif
+
+/*
+ * Lock for protecting SYN_TAG_DISABLE_WAY.
+ * Consider making this a per-FSB lock. 
+ */
+static spinlock_t flush_lock = SPIN_LOCK_UNLOCKED;
+
+/*
+ * sn_flush_all_caches
+ *
+ * Flush a range of addresses from all caches including L4. 
+ * All addresses fully or partially contained within 
+ * <flush_addr> to <flush_addr>+<bytes> are flushed
+ * from the all caches.
+ *
+ *	flush_addr:	identity mapped region 7 address to start flushing
+ *	bytes:		number of bytes to flush
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+	ulong 	addr, baddr, eaddr, bitbucket;
+	int	way, alias;
+
+	/*
+	 * Because of the way synergy implements "fc", this flushes the
+	 * data from all caches on all cpus & L4's on OTHER FSBs. It also
+	 * flushes both cpus on the local FSB. It does NOT flush it from 
+	 * the local FSB.
+	 */
+	flush_icache_range(flush_addr, flush_addr+bytes);
+
+	/*
+	 * Memory DIMMs are a minimum of 256MB and start on 256MB
+	 * boundaries. Convert the start address to an address
+	 * that is between +0MB & +128 of the same DIMM. 
+	 * Then add 8MB to skip the uncached MinState areas if the address
+	 * is on the master node.
+	 */
+	if (bytes > SYNERGY_L4_BYTES_PER_WAY)
+		bytes = SYNERGY_L4_BYTES_PER_WAY;
+	baddr = TO_NODE(smp_physical_node_id(), PAGE_OFFSET + (flush_addr & (128*MB-1)) + 8*MB); 
+	eaddr = (baddr+bytes+SYNERGY_BLOCK_SIZE-1) & ~(SYNERGY_BLOCK_SIZE-1);
+	baddr = baddr & ~(SYNERGY_BLOCK_SIZE-1);
+
+	/*
+	 * Now flush the local synergy.
+	 */
+	spin_lock(&flush_lock);
+	for(way=0; way<SYNERGY_L4_WAYS; way++) {
+		WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0xffL ^ (1L<<way));
+		mb();
+		for(alias=0; alias < 9; alias++)
+			for(addr=baddr; addr<eaddr; addr+=SYNERGY_BLOCK_SIZE)
+				bitbucket = *(volatile ulong *)(addr+alias*8*MB);
+		mb();
+	}
+	WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0);
+	spin_unlock(&flush_lock);
+
+}
+
+
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/error.c lia64-2.4/arch/ia64/sn/kernel/sn1/error.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/error.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/error.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,148 @@
+
+
+/*
+ * SN1 Platform specific error Support
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+
+void
+snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs) {
+	unsigned long long intpend_val;
+	unsigned long long bit;
+
+	switch (irq) {
+	case SGI_UART_IRQ:
+		// This isn't really an error interrupt.  We're just
+		// here because we have to do something with them.
+		// This is probably wrong, and this code will be
+		// removed.
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
+		if ( (bit = ~(1L<<GFX_INTR_A)) ==
+			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<GFX_INTR_B)) ==
+			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
+			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<UART_INTR)) ==
+			(intpend_val & ~(1L<<UART_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_A)) ==
+			(intpend_val & ~(1L<<CC_PEND_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_B)) ==
+			(intpend_val & ~(1L<<CC_PEND_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
+		return;
+	case SGI_HUB_ERROR_IRQ:
+		// These are mostly error interrupts of various
+		// sorts.  We need to do more than panic here, but
+		// what the heck, this is bring up.
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
+		
+		if ( (bit = ~(1L<<XB_ERROR)) ==
+			(intpend_val & ~(1L<<XB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<LB_ERROR)) ==
+			(intpend_val & ~(1L<<LB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_A)) ==
+			(intpend_val & ~(1L<<NACK_INT_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_B)) ==
+			(intpend_val & ~(1L<<NACK_INT_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
+			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
+			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
+			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
+			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
+		return;
+	default:
+		printk("Received invalid irq in snia_error_intr_handler()/n");
+	}
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/iomv.c lia64-2.4/arch/ia64/sn/kernel/sn1/iomv.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/iomv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/iomv.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,136 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <linux/pci.h>
+#include <asm/sn/simulator.h>
+
+static inline void *
+sn1_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+#ifdef SN1_IOPORTS
+unsigned int
+sn1_inb (unsigned long port)
+{
+return __ia64_inb ( port );
+}
+
+unsigned int
+sn1_inw (unsigned long port)
+{
+return __ia64_inw ( port );
+}
+
+unsigned int
+sn1_inl (unsigned long port)
+{
+return __ia64_inl ( port );
+}
+
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+return __ia64_outb ( val, port );
+}
+
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+return __ia64_outw ( val, port );
+}
+
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+return __ia64_outl ( val, port );
+}
+
+#else
+
+unsigned int
+sn1_inb (unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+	unsigned char ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+unsigned int
+sn1_inw (unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+	unsigned short ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+unsigned int
+sn1_inl (unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+	unsigned int ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+#endif /* SN1_IOPORTS */
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/sn1_smp.c lia64-2.4/arch/ia64/sn/kernel/sn1/sn1_smp.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/sn1_smp.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/sn1_smp.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,372 @@
+/*
+ * SN1 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * The following structure is used to pass params thru smp_call_function
+ * to other cpus for flushing TLB ranges.
+ */
+typedef struct {
+	unsigned long	start;
+	unsigned long	end;
+	unsigned long	nbits;
+	unsigned int	rid;
+	atomic_t	unfinished_count;
+} ptc_params_t;
+
+#define NUMPTC	256
+
+static ptc_params_t	ptcParamArray[NUMPTC] __attribute__((__aligned__(128)));
+
+/* use separate cache lines on ptcParamsNextByCpu to avoid false sharing */
+static ptc_params_t	*ptcParamsNextByCpu[NR_CPUS*16] __attribute__((__aligned__(128)));
+static volatile ptc_params_t	*ptcParamsEmpty;
+static spinlock_t	ptcParamsLock = SPIN_LOCK_UNLOCKED;
+
+static int ptcInit = 0;
+static int ptcParamsAllBusy = 0;		/* debugging/statistics */
+#ifdef PTCDEBUG
+static int ptcCountBacklog = 0;
+static int ptcBacklog[NUMPTC+1];
+static char ptcParamsCounts[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+static char ptcParamsResults[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+#endif
+
+
+/*
+ * The following table/struct is for remembering PTC coherency domains. It
+ * is also used to translate sapicid into cpuids. We dont want to start 
+ * cpus unless we know their cache domain.
+ */
+#ifdef PTC_NOTYET
+sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
+#endif
+
+
+
+/*
+ * NOTE: This is probably not good enough, but I dont want to try to make
+ * it better until I get some statistics on a running system. 
+ * At a minimum, we should only send IPIs to 1 processor in each TLB domain
+ * & have it issue a ptc.g on it's own FSB. Also, serialize per FSB, not 
+ * globally.
+ *
+ * More likely, we will have to do some work to reduce the frequency of calls to
+ * this routine.
+ */
+
+static inline void
+sn1_ptc_l_range(unsigned long start, unsigned long end, unsigned long nbits)
+{
+	do {
+		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
+		start += (1UL << nbits);
+	} while (start < end);
+	ia64_srlz_d();
+}
+
+void
+sn1_received_flush_tlb(void)
+{
+	unsigned long	start, end, nbits;
+	unsigned int	rid, saved_rid;
+	int		cpu = smp_processor_id();
+	int		result;
+	ptc_params_t	*ptcParams;
+
+	ptcParams = ptcParamsNextByCpu[cpu*16];
+	if (ptcParams == ptcParamsEmpty)
+		return;
+
+	do {
+		start = ptcParams->start;
+		saved_rid = (unsigned int) ia64_get_rr(start);
+		end = ptcParams->end;
+		nbits = ptcParams->nbits;
+		rid = ptcParams->rid;
+
+		if (saved_rid != rid) {
+			ia64_set_rr(start, (unsigned long)rid);
+			ia64_srlz_d();
+		}
+
+		sn1_ptc_l_range(start, end, nbits);
+
+		if (saved_rid != rid) 
+			ia64_set_rr(start, (unsigned long)saved_rid);
+
+		ia64_srlz_i();
+
+		result = atomic_dec(&ptcParams->unfinished_count);
+#ifdef PTCDEBUG
+		{
+		    int i = ptcParams-&ptcParamArray[0];
+		    ptcParamsResults[cpu][i] = (char) result;
+		    ptcParamsCounts[cpu][i]++;
+		}
+#endif /* PTCDEBUG */
+
+		if (++ptcParams == &ptcParamArray[NUMPTC])
+			ptcParams = &ptcParamArray[0];
+
+	} while (ptcParams != ptcParamsEmpty);
+
+	ptcParamsNextByCpu[cpu*16] = ptcParams;
+}
+
+
+void
+sn1_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	extern void smp_send_flush_tlb (void);
+	ptc_params_t	*params;
+	ptc_params_t	*next;
+	unsigned long	irqflags;
+#ifdef PTCDEBUG
+	ptc_params_t	*nextnext;
+	int		backlog = 0;
+#endif
+
+	if (smp_num_cpus == 1) {
+		sn1_ptc_l_range(start, end, nbits);
+		return;
+	}
+
+	while (!spin_trylock(&ptcParamsLock)) {
+		local_irq_save(irqflags);
+		sn1_received_flush_tlb();
+		local_irq_restore(irqflags);
+	}
+
+	if (!ptcInit) {
+		int cpu;
+		ptcInit = 1;
+		memset(ptcParamArray, 0, sizeof(ptcParamArray));
+		ptcParamsEmpty = &ptcParamArray[0];
+		for (cpu=0; cpu<NR_CPUS; cpu++)
+			ptcParamsNextByCpu[cpu*16] = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+		memset(ptcBacklog, 0, sizeof(ptcBacklog));
+		memset(ptcParamsCounts, 0, sizeof(ptcParamsCounts));
+		memset(ptcParamsResults, 0, sizeof(ptcParamsResults));
+#endif	/* PTCDEBUG */
+	}
+
+	params = (ptc_params_t *) ptcParamsEmpty;
+	next = (ptc_params_t *) ptcParamsEmpty + 1;
+	if (next == &ptcParamArray[NUMPTC])
+		next = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+	nextnext = next + 1;
+	if (nextnext == &ptcParamArray[NUMPTC])
+		nextnext = &ptcParamArray[0];
+
+	if (ptcCountBacklog) {
+		/* quick count of backlog */
+		ptc_params_t *ptr;
+
+		/* check the current pointer to the beginning */
+		ptr = params;
+		while(--ptr >= &ptcParamArray[0]) {
+			if (atomic_read(&ptr->unfinished_count) == 0)
+				break;
+			++backlog;
+		}
+
+		if (backlog) {
+			/* check the end of the array */
+			ptr = &ptcParamArray[NUMPTC];
+			while (--ptr > params) {
+				if (atomic_read(&ptr->unfinished_count) == 0)
+					break;
+				++backlog;
+			}
+		}
+		ptcBacklog[backlog]++;
+	}
+#endif	/* PTCDEBUG */
+
+	/* wait for the next entry to clear...should be rare */
+	if (atomic_read(&next->unfinished_count) > 0) {
+		ptcParamsAllBusy++;
+
+#ifdef PTCDEBUG
+		if (atomic_read(&nextnext->unfinished_count) == 0) {
+		    if (atomic_read(&next->unfinished_count) > 0) {
+			panic("\nnonzero next zero nextnext %lx %lx\n",
+			    (long)next, (long)nextnext);
+		    }
+		}
+#endif
+
+		/* it could be this cpu that is behind */
+		local_irq_save(irqflags);
+		sn1_received_flush_tlb();
+		local_irq_restore(irqflags);
+
+		/* now we know it's not this cpu, so just wait */
+		while (atomic_read(&next->unfinished_count) > 0) {
+			barrier();
+		}
+	}
+
+	params->start = start;
+	params->end = end;
+	params->nbits = nbits;
+	params->rid = (unsigned int) ia64_get_rr(start);
+	atomic_set(&params->unfinished_count, smp_num_cpus);
+
+	/* The atomic_set above can hit memory *after* the update
+	 * to ptcParamsEmpty below, which opens a timing window
+	 * that other cpus can squeeze into!
+	 */
+	mb();
+
+	/* everything is ready to process:
+	 *	-- global lock is held
+	 *	-- new entry + 1 is free
+	 *	-- new entry is set up
+	 * so now:
+	 *	-- update the global next pointer
+	 *	-- unlock the global lock
+	 *	-- send IPI to notify other cpus
+	 *	-- process the data ourselves
+	 */
+	ptcParamsEmpty = next;
+	spin_unlock(&ptcParamsLock);
+	smp_send_flush_tlb();
+
+	local_irq_save(irqflags);
+	sn1_received_flush_tlb();
+	local_irq_restore(irqflags);
+
+	/* Currently we don't think global TLB purges need to be atomic.
+	 * All CPUs get sent IPIs, so if they haven't done the purge,
+	 * they're busy with interrupts that are at the IPI level, which is
+	 * priority 15.  We're asserting that any code at that level
+	 * shouldn't be using user TLB entries.  To change this to wait
+	 * for all the flushes to complete, enable the following code.
+	 */
+#ifdef SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE
+	/* this code is not tested */
+	/* wait for the flush to complete */
+	while (atomic_read(&params.unfinished_count) > 1)
+		barrier();
+
+	atomic_set(&params->unfinished_count, 0);
+#endif
+}
+
+
+
+void
+sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		*p, nasid, slice;
+	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
+
+	/*
+	 * ZZZ - Replace with standard macros when available.
+	 */
+	nasid = cpuid_to_nasid(cpuid);
+	slice = cpuid_to_slice(cpuid);
+	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
+
+#if defined(ZZZBRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
+		smp_processor_id(), cpuid, vector, nasid, slice, (long)p);
+	}
+#endif
+	mb();
+	*p = (delivery_mode << 8) | (vector & 0xff);
+	
+}
+
+
+#ifdef CONFIG_SMP
+
+#ifdef PTC_NOTYET
+static void __init
+process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
+{
+	ia64_sal_ptc_domain_proc_entry_t	*pe;
+	int 					i, sapicid, cpuid;
+
+	pe = __va(di->proc_list);
+	for (i=0; i<di->proc_count; i++, pe++) {
+		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
+		cpuid = cpu_logical_id(sapicid);
+		sn_sapicid_info[cpuid].domain = domain;
+		sn_sapicid_info[cpuid].sapicid = sapicid;
+	}
+}
+
+
+static void __init
+process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
+{
+	ia64_sal_ptc_domain_info_t	*di;
+	int i;
+
+	di = __va(ptc->domain_info);
+	for (i=0; i<ptc->num_domains; i++, di++) {
+		process_sal_ptc_domain_info(di, i);	
+	}
+}
+#endif
+
+
+void __init
+init_sn1_smp_config(void)
+{
+	if (!ia64_ptc_domain_info)  {
+		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
+		smp_num_cpus = 1;
+		return;
+	}
+
+#ifdef PTC_NOTYET
+	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
+	process_sal_desc_ptc(ia64_ptc_domain_info);
+#endif
+}
+
+#else /* CONFIG_SMP */
+
+void __init
+init_sn1_smp_config(void)
+{
+
+#ifdef PTC_NOTYET
+	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
+#endif
+}
+
+#endif /* CONFIG_SMP */
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn1/synergy.c lia64-2.4/arch/ia64/sn/kernel/sn1/synergy.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn1/synergy.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn1/synergy.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,508 @@
+
+/*
+ * SN1 Platform specific synergy Support
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/proc_fs.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/sn/sndrv.h>
+
+int bit_pos_to_irq(int bit);
+void setclear_mask_b(int irq, int cpuid, int set);
+void setclear_mask_a(int irq, int cpuid, int set);
+void * kmalloc(size_t size, int flags);
+
+static int synergy_perf_initialized = 0;
+
+void
+synergy_intr_alloc(int bit, int cpuid) {
+	return;
+}
+
+int
+synergy_intr_connect(int bit, 
+		int cpuid)
+{
+	int irq;
+	unsigned is_b;
+
+	irq = bit_pos_to_irq(bit);
+
+	is_b = (cpuid_to_slice(cpuid)) & 1;
+	if (is_b) {
+		setclear_mask_b(irq,cpuid,1);
+		setclear_mask_a(irq,cpuid, 0);
+	} else {
+		setclear_mask_a(irq, cpuid, 1);
+		setclear_mask_b(irq, cpuid, 0);
+	}
+	return 0;
+}
+void
+setclear_mask_a(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+        /*
+         * Perform some idiot checks ..
+         */
+        if ( (irq < 0) || (irq > 255) ||
+                (cpuid < 0) || (cpuid > 512) ) {
+                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0A;
+			addr = VEC_MASK0A_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1A;
+			addr = VEC_MASK1A_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2A;
+			addr = VEC_MASK2A_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3A;
+			addr = VEC_MASK3A_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+void
+setclear_mask_b(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+	/*
+	 * Perform some idiot checks ..
+	 */
+	if ( (irq < 0) || (irq > 255) ||
+		(cpuid < 0) || (cpuid > 512) ) {
+		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0B;
+			addr = VEC_MASK0B_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1B;
+			addr = VEC_MASK1B_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2B;
+			addr = VEC_MASK2B_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3B;
+			addr = VEC_MASK3B_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+/*
+ * Synergy perf stats. Multiplexed via timer_interrupt.
+ */
+
+static int
+synergy_perf_append(uint64_t modesel)
+{
+	int		cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		checked = 0;
+	int		err = 0;
+
+	/* bit 45 is enable */
+	modesel |= (1UL << 45);
+
+	for (cnode=0; cnode < num_compact_nodes; cnode++) {
+		/* for each node, insert a new synergy_perf entry */
+		if ((npdap = NODEPDA(cnode)) == NULL) {
+			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, (void *)nodepda);
+			continue;
+		}
+
+		if (npdap->synergy_perf_enabled) {
+			/* user must disable counting to append new events */
+			err = -EBUSY;
+			break;
+		}
+
+		if (!checked && npdap->synergy_perf_data != NULL) {
+			checked = 1;
+			for (p = npdap->synergy_perf_first; ;) {
+				if (p->modesel == modesel)
+					return 0; /* event already registered */
+				if ((p = p->next) == npdap->synergy_perf_first)
+					break;
+			}
+		}
+
+		/* XX use kmem_alloc_node() when it is implemented */
+		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
+		if ((((uint64_t)p) & 7UL) != 0)
+			BUG(); /* bad alignment */
+		if (p == NULL) {
+			err = -ENOMEM;
+			break;
+		}
+		else {
+			memset(p, 0, sizeof(synergy_perf_t));
+			p->modesel = modesel;
+
+			spin_lock_irq(&npdap->synergy_perf_lock);
+			if (npdap->synergy_perf_data == NULL) {
+				/* circular list */
+				p->next = p;
+				npdap->synergy_perf_first = p;
+				npdap->synergy_perf_data = p;
+			}
+			else {
+				p->next = npdap->synergy_perf_data->next;
+				npdap->synergy_perf_data->next = p;
+			}
+			spin_unlock_irq(&npdap->synergy_perf_lock);
+		}
+	}
+
+	return err;
+}
+
+static void
+synergy_perf_set_freq(int freq)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < num_compact_nodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_freq = freq;
+	}
+}
+
+static void
+synergy_perf_set_enable(int enable)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < num_compact_nodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_enabled = enable;
+	}
+	printk("NOTICE: synergy perf counting %sabled on all nodes\n", enable ? "en" : "dis");
+}
+
+static int
+synergy_perf_size(nodepda_t *npdap)
+{
+	synergy_perf_t	*p;
+	int		n;
+
+	if (npdap->synergy_perf_enabled == 0) {
+		/* no stats to return */
+		return 0;
+	}
+
+	spin_lock_irq(&npdap->synergy_perf_lock);
+	for (n=0, p = npdap->synergy_perf_first; p;) {
+		n++;
+		p = p->next;
+		if (p == npdap->synergy_perf_first)
+			break;
+	}
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* bytes == n pairs of {event,counter} */
+	return n * 2 * sizeof(uint64_t);
+}
+
+static int
+synergy_perf_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+	int             cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		intarg;
+	int		fsb;
+	uint64_t	longarg;
+	uint64_t	*stats;
+	int		n;
+	devfs_handle_t	d;
+	arbitrary_info_t info;
+	
+	if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+		return -ENODEV;
+	info = hwgraph_fastinfo_get(d);
+
+	cnode = SYNERGY_PERF_INFO_CNODE(info);
+	fsb = SYNERGY_PERF_INFO_FSB(info);
+	npdap = NODEPDA(cnode);
+
+	switch (cmd) {
+	case SNDRV_GET_SYNERGY_VERSION:
+		/* return int, version of data structure for SNDRV_GET_SYNERGYINFO */
+		intarg = 1; /* version 1 */
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_INFOSIZE:
+		/* return int, sizeof buf needed for SYNERGY_PERF_GET_STATS */
+		intarg = synergy_perf_size(npdap);
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_SYNERGYINFO:
+		/* return array of event/value pairs, this node only */
+		if ((intarg = synergy_perf_size(npdap)) <= 0)
+			return -ENODATA;
+		if ((stats = (uint64_t *)kmalloc(intarg, GFP_KERNEL)) == NULL)
+			return -ENOMEM;
+		spin_lock_irq(&npdap->synergy_perf_lock);
+		for (n=0, p = npdap->synergy_perf_first; p;) {
+			stats[n++] = p->modesel;
+			if (p->intervals > 0)
+			    stats[n++] = p->counts[fsb] * p->total_intervals / p->intervals;
+			else
+			    stats[n++] = 0;
+			p = p->next;
+			if (p == npdap->synergy_perf_first)
+				break;
+		}
+		spin_unlock_irq(&npdap->synergy_perf_lock);
+
+		if (copy_to_user((void *)arg, stats, intarg)) {
+		    kfree(stats);
+		    return -EFAULT;
+		}
+
+		kfree(stats);
+		break;
+
+	case SNDRV_SYNERGY_APPEND:
+		/* reads 64bit event, append synergy perf event to all nodes  */
+		if (copy_from_user(&longarg, (void *)arg, sizeof(longarg)))
+		    return -EFAULT;
+		return synergy_perf_append(longarg);
+		break;
+
+	case SNDRV_GET_SYNERGY_STATUS:
+		/* return int, 1 if enabled else 0 */
+		intarg = npdap->synergy_perf_enabled;
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_SYNERGY_ENABLE:
+		/* read int, if true enable counting else disable */
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		synergy_perf_set_enable(intarg);
+		break;
+
+	case SNDRV_SYNERGY_FREQ:
+		/* read int, set jiffies per update */ 
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		if (intarg < 0 || intarg >= HZ)
+			return -EINVAL;
+		synergy_perf_set_freq(intarg);
+		break;
+
+	default:
+		printk("Warning: invalid ioctl %d on synergy mon for cnode=%d fsb=%d\n", cmd, cnode, fsb);
+		return -EINVAL;
+	}
+	return(0);
+}
+
+struct file_operations synergy_mon_fops = {
+        ioctl:		synergy_perf_ioctl,
+};
+
+void
+synergy_perf_update(int cpu)
+{
+	nasid_t		nasid;
+	cnodeid_t       cnode;
+	struct nodepda_s *npdap;
+
+	/*
+	 * synergy_perf_initialized is set by synergy_perf_init()
+	 * which is called last thing by sn_mp_setup(), i.e. well
+	 * after nodepda has been initialized.
+	 */
+	if (!synergy_perf_initialized)
+		return;
+
+	cnode = cpuid_to_cnodeid(cpu);
+	npdap = NODEPDA(cnode);
+
+	if (npdap == NULL || cnode < 0 || cnode >= num_compact_nodes)
+		/* this should not happen: still in early io init */
+		return;
+
+#if 0
+	/* use this to check nodepda initialization */
+	if (((uint64_t)npdap) & 0x7) {
+		printk("\nERROR on cpu %d : cnode=%d, npdap == %p, not aligned\n", cpu, cnode, npdap);
+		BUG();
+	}
+#endif
+
+	if (npdap->synergy_perf_enabled == 0 || npdap->synergy_perf_data == NULL) {
+		/* Not enabled, or no events to monitor */
+		return;
+	}
+
+	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
+		/* don't multiplex on every timer interrupt */
+		return;
+	}
+
+	/*
+	 * Read registers for last interval and increment counters.
+	 * Hold the per-node synergy_perf_lock so concurrent readers get
+	 * consistent values.
+	 */
+	spin_lock_irq(&npdap->synergy_perf_lock);
+
+	nasid = cpuid_to_nasid(cpu);
+	npdap->synergy_active_intervals++;
+	npdap->synergy_perf_data->intervals++;
+	npdap->synergy_perf_data->total_intervals = npdap->synergy_active_intervals;
+
+	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
+
+	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
+
+	/* skip to next in circular list */
+	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
+
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* set the counter 0 selection modes for both A and B */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
+
+	/* and reset the counter registers to zero */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
+}
+
+void
+synergy_perf_init(void)
+{
+	printk("synergy_perf_init(), counting is initially disabled\n");
+	synergy_perf_initialized++;
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn2/Makefile lia64-2.4/arch/ia64/sn/kernel/sn2/Makefile
--- linux-2.4.16/arch/ia64/sn/kernel/sn2/Makefile	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn2/Makefile	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,26 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001 Silicon Graphics, Inc. All rights reserved.
+#
+
+EXTRA_CFLAGS	:= -DSN -I. -DBRINGUP \
+		   -DNUMA_BASE -DSIMULATED_KLGRAPH \
+		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN
+# -DSN1_IOPORTS
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn2.a
+
+O_TARGET        = sn2.a
+export-objs	:= sn2_ksyms.o
+
+obj-y          = cache.o iomv.o sn2_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn2/cache.c lia64-2.4/arch/ia64/sn/kernel/sn2/cache.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn2/cache.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn2/cache.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,34 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+
+#include <asm/pgalloc.h>
+
+
+/*
+ * sn_flush_all_caches
+ *
+ * Flush a range of addresses from all caches including L4. 
+ * All addresses fully or partially contained within 
+ * <flush_addr> to <flush_addr>+<bytes> are flushed
+ * from the all caches.
+ *
+ *	flush_addr:	identity mapped region 7 address to start flushing
+ *	bytes:		number of bytes to flush
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+
+	flush_icache_range(flush_addr, flush_addr+bytes);
+
+}
+
+
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn2/iomv.c lia64-2.4/arch/ia64/sn/kernel/sn2/iomv.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn2/iomv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn2/iomv.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,137 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <linux/pci.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
+
+static inline void *
+sn1_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = (0xc000000fcc000000 | ((unsigned long)get_nasid() << 38));
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+#ifdef SN1_IOPORTS
+unsigned int
+sn1_inb (unsigned long port)
+{
+return __ia64_inb ( port );
+}
+
+unsigned int
+sn1_inw (unsigned long port)
+{
+return __ia64_inw ( port );
+}
+
+unsigned int
+sn1_inl (unsigned long port)
+{
+return __ia64_inl ( port );
+}
+
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+return __ia64_outb ( val, port );
+}
+
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+return __ia64_outw ( val, port );
+}
+
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+return __ia64_outl ( val, port );
+}
+
+#else
+
+unsigned int
+sn1_inb (unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+	unsigned char ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+unsigned int
+sn1_inw (unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+	unsigned short ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+unsigned int
+sn1_inl (unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+	unsigned int ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+#endif /* SN1_IOPORTS */
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn2/sn2_smp.c lia64-2.4/arch/ia64/sn/kernel/sn2/sn2_smp.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn2/sn2_smp.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn2/sn2_smp.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,109 @@
+/*
+ * SN2 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+
+void
+sn2_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	int		cnode, nasid;
+	volatile long	*ptc0, *ptc1, *piows;
+	unsigned long	ws, next, data0, data1;
+
+	piows = (long*)LOCAL_MMR_ADDR(get_slice() ? SH_PIO_WRITE_STATUS_1 : SH_PIO_WRITE_STATUS_0);
+	data0 = (1UL<<SH_PTC_0_A_SHFT) |
+		(nbits<<SH_PTC_0_PS_SHFT) |
+		((ia64_get_rr(start)>>8)<<SH_PTC_0_RID_SHFT) |
+		(1UL<<SH_PTC_0_START_SHFT);
+
+	ptc0 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_0);
+	ptc1 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_1);
+	do {
+		*(piows+1) = -1;	/* use alias address to clear bits*/
+		next = start;
+		do {
+			for (cnode = 0; cnode < num_compact_nodes; cnode++) {
+				nasid = cnodeid_to_nasid(cnode);
+				ptc0 = CHANGE_NASID(nasid, ptc0);
+				ptc1 = CHANGE_NASID(nasid, ptc1);
+				data1 = next | (1UL<<SH_PTC_1_START_SHFT);
+				*ptc0 = data0;
+				*ptc1 = data1;
+			}
+			next += (1UL << nbits);
+		} while (next < end);
+
+		while ((ws = *piows) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK)
+			;
+
+	} while (ws & SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK);
+
+	
+}
+
+
+
+
+void
+sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		*p, val;
+	long		physid;
+	long		nasid, slice;
+
+	physid = cpu_physical_id(cpuid);
+	nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+	p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+	val =   (1UL<<SH_IPI_INT_SEND_SHFT) | 
+		(physid<<SH_IPI_INT_PID_SHFT) | 
+	        ((long)delivery_mode<<SH_IPI_INT_TYPE_SHFT) | 
+		((long)vector<<SH_IPI_INT_IDX_SHFT) |
+		(0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+
+#if defined(BRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx, val 0x%lx\n",
+		smp_processor_id(), cpuid, vector, nasid, slice, (long)p, val);
+	}
+#endif
+	mb();
+	*p = val;
+	
+}
+
+
+void __init
+init_sn2_smp_config(void)
+{
+
+}
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn_asm.S lia64-2.4/arch/ia64/sn/kernel/sn_asm.S
--- linux-2.4.16/arch/ia64/sn/kernel/sn_asm.S	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn_asm.S	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,148 @@
+
+/*
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+
+// Testing only.
+// Routine will cause MCAs
+//   zzzmsa(n)
+//      n=0 MCA via duplicate TLB dropin
+//      n=0 MCA via read of garbage address
+//
+
+#define ITIR(key, ps)           ((key<<8) | (ps<<2))
+#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
+
+                        .global zzzmca
+                        .proc   zzzmca
+zzzmca:
+                        alloc   loc4       = ar.pfs,2,8,1,0;;
+                        cmp.ne  p6,p0=r32,r0;;
+                        movl    r2=0x2dead
+                        movl    r3=0x3dead
+                        movl    r15=0x15dead
+                        movl    r16=0x16dead
+                        movl    r31=0x31dead
+                        movl    loc0=0x34beef
+                        movl    loc1=0x35beef
+                        movl    loc2=0x36beef
+                        movl    loc3=0x37beef
+                        movl    out0=0x42beef
+
+                        movl    r20=0x32feed;;
+                        mov     ar32=r20
+                        movl    r20=0x36feed;;
+                        mov     ar36=r20
+                        movl    r20=0x65feed;;
+                        mov     ar65=r20
+                        movl    r20=0x66feed;;
+                        mov     ar66=r20
+
+(p6)                    br.cond.sptk    1f
+
+                        rsm      0x2000;;
+                        srlz.d;
+                        mov      r11      = 1
+                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
+                        mov      cr.itir  = r3
+                        mov      r10      = 0;;
+                        itr.d    dtr[r11] = r10;;
+                        mov      r11      = 2
+
+                        itr.d    dtr[r11] = r10;;
+                        br      9f
+
+1:                      movl    r8=0xfe00000048;;
+                        ld8     r9=[r8];;
+                        mf
+                        mf.a
+                        srlz.d
+
+9:                      mov     ar.pfs=loc4
+                        br.ret.sptk     rp
+
+                        .endp   zzzmca
+
+                        .global zzzspec
+                        .proc   zzzspec
+zzzspec:
+			mov	r8=r32
+			movl	r9=0xe000000000000000
+			movl	r10=0x4000;;
+			ld8.s	r16=[r8];;
+			ld8.s	r17=[r9];;
+			add	r8=r8,r10;;
+			ld8.s	r18=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r19=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r20=[r8];;
+			mov	r8=r0
+			tnat.nz	p6,p0=r16
+			tnat.nz	p7,p0=r17
+			tnat.nz	p8,p0=r18
+			tnat.nz	p9,p0=r19
+			tnat.nz	p10,p0=r20;;
+		(p6)	dep	r8=-1,r8,0,1;;
+		(p7)	dep	r8=-1,r8,1,1;;
+		(p8)	dep	r8=-1,r8,2,1;;
+		(p9)	dep	r8=-1,r8,3,1;;
+		(p10)	dep	r8=-1,r8,4,1;;
+                        br.ret.sptk     rp
+                        .endp   zzzspec
+
+                        .global zzzspec2
+                        .proc   zzzspec2
+zzzspec2:
+			cmp.eq	p6,p7=r2,r2
+			movl	r16=0xc0000a0001000020
+			;;
+			mf
+			;;
+			ld8	r9=[r16]
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r16];;
+			cmp.ne	p6,p7=r9,r16
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r33];;
+			cmp.ne	p6,p7=r9,r33
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			tpa	r23=r32
+			add	r20=512,r33
+			add	r21=1024,r33;;
+			ld8	r9=[r20]
+			ld8	r10=[r21];;
+			nop.i	0
+			{ .mib
+			nop.m 0
+			cmp.ne	p6,p7=r10,r33
+		(p6)	br.spnt	1f
+			}
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+			br.ret.sptk     rp
+
+                        .endp   zzzspec
+
+#endif
+
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sn_ksyms.c lia64-2.4/arch/ia64/sn/kernel/sn_ksyms.c
--- linux-2.4.16/arch/ia64/sn/kernel/sn_ksyms.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sn_ksyms.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,74 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+/*
+ * Architecture-specific kernel symbols
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <asm/machvec.h>
+
+/*
+ * I/O routines
+ */
+EXPORT_SYMBOL(sn1_outb);
+EXPORT_SYMBOL(sn1_outl);
+EXPORT_SYMBOL(sn1_outw);
+EXPORT_SYMBOL(sn1_inw);
+EXPORT_SYMBOL(sn1_inb);
+EXPORT_SYMBOL(sn1_inl);
+
+/*
+ * other stuff (more to be added later, cleanup then)
+ */
+EXPORT_SYMBOL(sn1_pci_map_sg);
+EXPORT_SYMBOL(sn1_pci_unmap_sg);
+EXPORT_SYMBOL(sn1_pci_alloc_consistent);
+EXPORT_SYMBOL(sn1_pci_free_consistent);
+EXPORT_SYMBOL(sn1_dma_address);
+
+#include <linux/mm.h>
+#include <linux/devfs_fs_kernel.h>
+extern devfs_handle_t          base_io_scsi_ctlr_vhdl[];
+#include <asm/sn/types.h>
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+#include <asm/sn/arch.h>
+EXPORT_SYMBOL(base_io_scsi_ctlr_vhdl);
+EXPORT_SYMBOL(master_node_get);
+
+
+/*
+ * symbols referenced by the PCIBA module
+ */
+#include <asm/sn/invent.h>
+#include <asm/sn/hack.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/pci/pciio.h>
+
+devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
+EXPORT_SYMBOL(devfn_to_vertex);
+EXPORT_SYMBOL(hwgraph_vertex_unref);
+EXPORT_SYMBOL(pciio_config_get);
+EXPORT_SYMBOL(pciio_info_slot_get);
+EXPORT_SYMBOL(hwgraph_edge_add);
+EXPORT_SYMBOL(pciio_info_master_get);
+EXPORT_SYMBOL(pciio_info_get);
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+EXPORT_SYMBOL(__pa_debug);
+EXPORT_SYMBOL(__va_debug);
+#endif
+
+/* added by tduffy 04.08.01 to fix depmod issues */
+#include <linux/mmzone.h>
+EXPORT_SYMBOL(sn1_pci_unmap_single);
+EXPORT_SYMBOL(sn1_pci_map_single);
+EXPORT_SYMBOL(sn1_pci_dma_sync_single);
diff -urN linux-2.4.16/arch/ia64/sn/kernel/sv.c lia64-2.4/arch/ia64/sn/kernel/sv.c
--- linux-2.4.16/arch/ia64/sn/kernel/sv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/arch/ia64/sn/kernel/sv.c	Mon Nov 19 23:22:53 2001
@@ -0,0 +1,552 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved
+ *
+ * This implemenation of synchronization variables is heavily based on
+ * one done by Steve Lord <lord@sgi.com>
+ *
+ * Paul Cassella <pwc@sgi.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/semaphore.h>
+#include <asm/hardirq.h>
+#include <asm/softirq.h>
+#include <asm/current.h>
+
+#include <asm/sn/sv.h>
+
+/* Define this to have sv_test() run some simple tests.
+   kernel_thread() must behave as expected when this is called.  */
+#undef RUN_SV_TEST
+
+#define DEBUG
+
+/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
+   can sanity check interrupt state on architectures where we know
+   how. */
+#ifdef DEBUG
+ #define SV_DEBUG_INTERRUPT_STATE
+ #ifdef __mips64
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 31
+ #elif defined(__ia64)
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
+ #else
+  #undef  SV_DEBUG_INTERRUPT_STATE
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
+ #endif /* __mips64 */
+#endif /* DEBUG */
+
+
+/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
+   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
+#ifdef TASK_EXCLUSIVE
+  #undef EXCLUSIVE_IN_QUEUE
+#else
+  #define EXCLUSIVE_IN_QUEUE
+  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
+#endif
+
+
+static inline void sv_lock(sv_t *sv) {
+	spin_lock(&sv->sv_lock);
+}
+
+static inline void sv_unlock(sv_t *sv) {
+	spin_unlock(&sv->sv_lock);
+}
+
+/* up() is "extern inline", so we can't pass its address to sv_wait.
+   Use this function's address instead. */
+static void up_wrapper(struct semaphore *sem) {
+	up(sem);
+}
+
+/* spin_unlock() is sometimes a macro. */
+static void spin_unlock_wrapper(spinlock_t *s) {
+	spin_unlock(s);
+}
+
+/* XXX Perhaps sv_wait() should do the switch() each time and avoid
+   the extra indirection and the need for the _wrapper functions? */
+
+static inline void sv_set_mon_type(sv_t *sv, int type) {
+	switch (type) {
+	case SV_MON_SPIN:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
+		break;
+	case SV_MON_SEMA:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)up_wrapper;
+		if(sv->sv_flags & SV_INTS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with interrupts if it is a "
+			       "semaphore!\n");
+			BUG();
+		}
+		if(sv->sv_flags & SV_BHS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with bottom-halves if it is "
+			       "a semaphore!\n");
+			BUG();
+		}
+		break;
+#if 0 
+	/*
+	 * If needed, and will need to think about interrupts.  This
+	 * may be needed, for example, if someone wants to use sv's
+	 * with something like dev_base; writers need to hold two
+	 * locks. 
+	 */
+	case SV_MON_CUSTOM: 
+		{
+		struct sv_mon_custom *c = lock;
+		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
+		sv->sv_mon_lock        = c->sv_mon_lock;
+		break;
+		}
+#endif
+		
+	default:
+		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
+		       "(flags 0x%x)\n", type, type, sv->sv_flags);
+		BUG();
+		break;
+	}
+	sv->sv_flags |= type;
+}
+
+static inline void sv_set_ord(sv_t *sv, int ord) {
+	if (!ord)
+		ord = SV_ORDER_DEFAULT;
+
+	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
+		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
+		       ord, ord);
+		BUG();
+	}
+
+	sv->sv_flags |= ord;
+}
+
+void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
+{
+	int ord = flags & SV_ORDER_MASK;
+	int type = flags & SV_MON_MASK;
+
+	/* Copy all non-order, non-type flags */
+	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
+
+	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
+	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
+	  BUG();
+	}
+
+	sv_set_ord(sv, ord);
+	sv_set_mon_type(sv, type);
+
+	/* If lock is NULL, we'll get it from sv_wait_compat() (and
+           ignore it in sv_signal() and sv_broadcast()). */
+	sv->sv_mon_lock = lock;
+
+	spin_lock_init(&sv->sv_lock);
+	init_waitqueue_head(&sv->sv_waiters);
+}
+
+/*
+ * The associated lock must be locked on entry.  It is unlocked on return.
+ *
+ * Return values:
+ *
+ * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
+ * n = 0 : timeout expired
+ * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
+ */
+signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
+{
+	DECLARE_WAITQUEUE( wait, current );
+	unsigned long flags;
+	signed long ret = 0;
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	{
+	unsigned long flags;
+	__save_flags(flags);
+
+	if(sv->sv_flags & SV_INTS) {
+		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
+			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
+			       "enabled (flags: 0x%lx)\n", flags);
+			BUG();
+		}
+	} else {
+		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
+			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
+			       "disabled! (flags: 0x%lx)\n", flags);
+		}
+	}
+	}
+#endif  /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+
+	sv->sv_mon_unlock_func(sv->sv_mon_lock);
+
+	/* Add ourselves to the wait queue and set the state before
+	 * releasing the sv_lock so as to avoid racing with the
+	 * wake_up() in sv_signal() and sv_broadcast(). 
+	 */
+
+	/* don't need the _irqsave part, but there is no wq_write_lock() */
+	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
+
+#ifdef EXCLUSIVE_IN_QUEUE
+	wait.flags |= WQ_FLAG_EXCLUSIVE;
+#endif
+
+	switch(sv->sv_flags & SV_ORDER_MASK) {
+	case SV_ORDER_FIFO:
+		__add_wait_queue_tail(&sv->sv_waiters, &wait);
+		break;
+	case SV_ORDER_FILO:
+		__add_wait_queue(&sv->sv_waiters, &wait);
+		break;
+	default:
+		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
+					(void *)sv, sv->sv_flags);
+		BUG();
+	}
+	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
+
+	if(sv_wait_flags & SV_WAIT_SIG)
+		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
+	else
+		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
+
+	spin_unlock(&sv->sv_lock);
+
+	if(sv->sv_flags & SV_INTS)
+		local_irq_enable();
+	else if(sv->sv_flags & SV_BHS)
+		local_bh_enable();
+
+	if (timeout)
+		ret = schedule_timeout(timeout);
+	else
+		schedule();
+
+	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
+		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
+		       "schedule().\n");
+		set_current_state(TASK_RUNNING);
+	}
+
+	remove_wait_queue(&sv->sv_waiters, &wait);
+
+	/* Return cases:
+	   - woken by a sv_signal/sv_broadcast
+	   - woken by a signal
+	   - woken by timeout expiring
+	*/
+
+	/* XXX This isn't really accurate; we may have been woken
+           before the signal anyway.... */
+	if(signal_pending(current))
+		return timeout ? -ret : -1;
+	return timeout ? ret : 1;
+}
+
+
+void sv_signal(sv_t *sv) 
+{
+	/* If interrupts can acquire this lock, they can also acquire the
+	   sv_mon_lock, which we must already have to have called this, so
+	   interrupts must be disabled already.  If interrupts cannot
+	   contend for this lock, we don't have to worry about it. */
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_signal: SV_INTS and "
+			"interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_broadcast(sv_t *sv) 
+{
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_broadcast: SV_INTS and "
+			       "interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up_all(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_destroy(sv_t *sv) 
+{
+	if(!spin_trylock(&sv->sv_lock)) {
+		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", (void *)sv);
+		BUG();
+	}
+
+	/* XXX Check that the waitqueue is empty? 
+	       Mark the sv destroyed?
+	*/
+}
+
+
+#ifdef RUN_SV_TEST
+
+static DECLARE_MUTEX_LOCKED(talkback);
+static DECLARE_MUTEX_LOCKED(sem);
+sv_t sv;
+sv_t sv_filo;
+
+static int sv_test_1_w(void *arg) 
+{
+	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
+
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
+
+	up(&sem);
+
+	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
+
+	sv_spin_wait(&sv, arg);
+
+	printk("sv_test_1_w: talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_1_w: exiting.\n");
+	return 0;
+}
+
+static int sv_test_1_s(void *arg) 
+{
+	printk("sv_test_1_s: waiting for semaphore.\n");
+	down(&sem);
+	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
+	sv_signal(&sv);
+	printk("sv_test_1_s: talkback.\n");
+	up(&talkback);
+	printk("sv_test_1_s: exiting.\n");
+	return 0;
+
+}
+
+static int count;
+static DECLARE_MUTEX(monitor);
+
+static int sv_test_2_w(void *arg) 
+{
+	int dummy = count++;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	up(&talkback);
+	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
+	sv_sema_wait(sv, &monitor);
+	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
+	up(&sem);
+	return 0;
+}
+
+static int sv_test_2_s_1(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s_1: waking one thread.\n");
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
+	sv_signal(sv);
+	sv_broadcast(sv);
+	sv_signal(sv);
+	sv_broadcast(sv);
+
+	printk("sv_test_2_s_1: talkbacking.\n");
+	up(&talkback);
+	up(&monitor);
+	return 0;
+}
+
+static int sv_test_2_s(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
+	sv_broadcast(sv);
+	for(; i < 10; i++)
+		down(&sem);
+
+	printk("sv_test_3_s: sending talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_3_s: exiting.\n");
+	up(&monitor);
+	return 0;
+}
+
+
+static void big_test(sv_t *sv) 
+{
+	int i;
+
+	count = 0;
+
+	for(i = 0; i < 3; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning first wake-up thread.\n");
+	kernel_thread(sv_test_2_s_1, sv, 0);
+
+	down(&talkback);
+	printk("big_test: talkback happened.\n");
+
+
+	for(i = 3; i < 13; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning wake-up thread.\n");
+	kernel_thread(sv_test_2_s, sv, 0);
+
+	down(&talkback);
+}
+
+sv_t int_test_sv;
+spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
+int int_test_ready;
+static int irqtestcount;
+
+static int interrupt_test_worker(void *unused) 
+{
+	int id = ++irqtestcount;
+	int it = 0;
+			unsigned long flags, flags2;
+
+	printk("ITW: thread %d started.\n", id);
+
+	while(1) {
+		__save_flags(flags2);
+		if(jiffies % 3) {
+			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
+			spin_lock_irqsave(&int_test_spin, flags);
+		} else {
+			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
+			spin_lock_irq(&int_test_spin);
+		}
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
+		sv_wait(&int_test_sv, 0, 0);
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(jiffies & 0xf);
+		if(current->state != TASK_RUNNING)
+		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
+		it++;
+	}
+}
+
+static void interrupt_test(void) 
+{
+	int i;
+
+	printk("interrupt_test: initing sv.\n");
+	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
+
+	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
+		printk("interrupt_test: starting test thread %d.\n", i);
+		kernel_thread(interrupt_test_worker, 0, 0);
+	}
+	printk("interrupt_test: done with init part.\n");
+	int_test_ready = 1;
+}
+
+int sv_test(void) 
+{
+	spinlock_t s = SPIN_LOCK_UNLOCKED;
+
+	sv_init(&sv, &s, SV_MON_SPIN);
+	printk("sv_test: starting sv_test_1_w.\n");
+	kernel_thread(sv_test_1_w, &s, 0);
+	printk("sv_test: starting sv_test_1_s.\n");
+	kernel_thread(sv_test_1_s, &s, 0);
+
+	printk("sv_test: waiting for talkback.\n");
+	down(&talkback); down(&talkback);
+	printk("sv_test: talkback happened, sv_destroying.\n");
+	sv_destroy(&sv);
+
+	count = 0;
+
+	printk("sv_test: beginning big_test on sv.\n");
+
+	sv_init(&sv, &monitor, SV_MON_SEMA);
+	big_test(&sv);
+	sv_destroy(&sv);
+
+	printk("sv_test: beginning big_test on sv_filo.\n");
+	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
+	big_test(&sv_filo);
+	sv_destroy(&sv_filo);
+
+	interrupt_test();
+
+	printk("sv_test: done.\n");
+	return 0;
+}
+
+__initcall(sv_test);
+
+#endif /* RUN_SV_TEST */
diff -urN linux-2.4.16/arch/ia64/sn/sn1/Makefile lia64-2.4/arch/ia64/sn/sn1/Makefile
--- linux-2.4.16/arch/ia64/sn/sn1/Makefile	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/Makefile	Wed Dec 31 16:00:00 1969
@@ -1,31 +0,0 @@
-#
-# ia64/platform/sn/sn1/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-
-.S.s:
-	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
-.S.o:
-	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-
-all: sn1.a
-
-O_TARGET        = sn1.a
-
-obj-y          = irq.o setup.o iomv.o mm.o smp.o synergy.o sn1_asm.o \
-		discontig.o probe.o error.o sv.o
-
-obj-$(CONFIG_IA64_SGI_AUTOTEST)	+= llsc4.o
-obj-$(CONFIG_IA64_GENERIC)	+= machvec.o
-obj-$(CONFIG_MODULES)		+= sn1_ksyms.o
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -urN linux-2.4.16/arch/ia64/sn/sn1/discontig.c lia64-2.4/arch/ia64/sn/sn1/discontig.c
--- linux-2.4.16/arch/ia64/sn/sn1/discontig.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/discontig.c	Wed Dec 31 16:00:00 1969
@@ -1,159 +0,0 @@
-/*
- * Copyright 2000, Silicon Graphics, sprasad@engr.sgi.com
- * Copyright 2000, Kanoj Sarcar, kanoj@sgi.com
- */
-
-/*
- * Contains common definitions and globals for NUMA platform
- * support. For now, SN-IA64 and SN-MIPS are the NUMA platforms.
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/sn/mmzone.h>
-#include <asm/efi.h>
-
-extern int numnodes ;
-
-plat_pg_data_t plat_node_data[MAXNODES];
-bootmem_data_t bdata[MAXNODES];
-int chunktonid[MAXCHUNKS];
-int nasid_map[MAXNASIDS];
-
-void __init
-init_chunktonid(void)
-{
-	memset(chunktonid, -1, sizeof(chunktonid)) ;
-}
-
-void __init
-init_nodeidmap(void)
-{
-	memset(nasid_map, -1, sizeof(nasid_map)) ;
-}
-
-int		cnodeid_map[MAXNODES] ;
-void __init
-init_cnodeidmap(void)
-{
-	memset(cnodeid_map, -1, sizeof(cnodeid_map)) ;
-}
-
-int
-numa_debug(void)
-{
-       panic("NUMA debug\n");
-       return(0);
-}
-
-int __init
-build_cnodeid_map(void)
-{
-	int	i,j ;
-
-	for (i=0,j=0;i<MAXNASIDS;i++) {
-		if (nasid_map[i] >= 0)
-			cnodeid_map[j++] = i ;
-	}
-	return j ;
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasids covered by the input memory descriptor.
- */
-static int __init
-build_nasid_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	int nasid = GetNasId(__pa(vaddr));
-
-	while (vaddr < end) {
-		if (nasid < MAXNASIDS)
-			nasid_map[nasid] = 0;
-		else
-			panic("build_nasid_map");
-		vaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-	}
-	return 0;
-}
-
-void __init
-fix_nasid_map(void)
-{
-	int	i ;
-	int		j ;
-
-	/* For every nasid */
-	for (j=0;j<MAXNASIDS;j++) {
-		for (i=0;i<MAXNODES;i++) {
-			if (CNODEID_TO_NASID(i) == j)
-				break ;
-		}
-		if (i<MAXNODES)
-			nasid_map[j] = i ;
-	}
-}
-
-static void __init
-dump_bootmem_info(void)
-{
-        int     i;
-        struct bootmem_data *bdata ;
-
-	printk("CNODE INFO ....\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d ", CNODEID_TO_NASID(i)) ;
-	}
-	printk("\n") ;
-
-	printk("BOOT MEM INFO ....\n") ;
-        printk("Node   Start                LowPfn               BootmemMap\n") ;
-        for (i=0;i<numnodes;i++) {
-                bdata = NODE_DATA(i)->bdata ;
-                printk("%d      0x%016lx   0x%016lx   0x%016lx\n", i,
-                        bdata->node_boot_start, bdata->node_low_pfn,
-                        (unsigned long)bdata->node_bootmem_map) ;
-        }
-}
-
-void __init
-discontig_mem_init(void)
-{
-	extern void setup_sn1_bootmem(int);
-	int		maxnodes ;
-
-        init_chunktonid() ;
-	init_nodeidmap() ;
-	init_cnodeidmap() ;
-	efi_memmap_walk(build_nasid_map, 0) ;
-	maxnodes = build_cnodeid_map() ;
-	fix_nasid_map() ;
-#ifdef CONFIG_DISCONTIGMEM
-	setup_sn1_bootmem(maxnodes) ;
-#endif
-	numnodes = maxnodes;
-	dump_bootmem_info() ;
-}
-
-void
-dump_node_data(void)
-{
-        int     i;
-
-	printk("NODE DATA ....\n") ;
-	printk("Node, Start, Size, MemMap, BitMap, StartP, Mapnr, Size, Id\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %d\n", 
-			CNODEID_TO_NASID(i), NODE_START(i), NODE_SIZE(i), 
-			(long)NODE_MEM_MAP(i), (long)NODE_DATA(i)->valid_addr_bitmap, 
-			NODE_DATA(i)->node_start_paddr, 
-			NODE_DATA(i)->node_start_mapnr,
-			NODE_DATA(i)->node_size,
-			NODE_DATA(i)->node_id)  ;
-	}
-}
-
diff -urN linux-2.4.16/arch/ia64/sn/sn1/error.c lia64-2.4/arch/ia64/sn/sn1/error.c
--- linux-2.4.16/arch/ia64/sn/sn1/error.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/error.c	Wed Dec 31 16:00:00 1969
@@ -1,149 +0,0 @@
-
-
-/*
- * SN1 Platform specific error Support
- *
- * Copyright (C) 2001 Silicon Graphics, Inc.
- * Copyright (C) 2001 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-
-void
-snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs) {
-	unsigned long long intpend_val;
-	unsigned long long bit;
-
-	switch (irq) {
-	case SGI_UART_IRQ:
-		// This isn't really an error interrupt.  We're just
-		// here because we have to do something with them.
-		// This is probably wrong, and this code will be
-		// removed.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
-		if ( (bit = ~(1L<<GFX_INTR_A)) ==
-			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<GFX_INTR_B)) ==
-			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
-			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<UART_INTR)) ==
-			(intpend_val & ~(1L<<UART_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_A)) ==
-			(intpend_val & ~(1L<<CC_PEND_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_B)) ==
-			(intpend_val & ~(1L<<CC_PEND_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
-		return;
-	case SGI_HUB_ERROR_IRQ:
-		// These are mostly error interrupts of various
-		// sorts.  We need to do more than panic here, but
-		// what the heck, this is bring up.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
-		
-		if ( (bit = ~(1L<<XB_ERROR)) ==
-			(intpend_val & ~(1L<<XB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<LB_ERROR)) ==
-			(intpend_val & ~(1L<<LB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_A)) ==
-			(intpend_val & ~(1L<<NACK_INT_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_B)) ==
-			(intpend_val & ~(1L<<NACK_INT_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
-			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
-			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
-			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
-			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
-		return;
-	default:
-		printk("Received invalid irq in snia_error_intr_handler()/n");
-	}
-}
diff -urN linux-2.4.16/arch/ia64/sn/sn1/iomv.c lia64-2.4/arch/ia64/sn/sn1/iomv.c
--- linux-2.4.16/arch/ia64/sn/sn1/iomv.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/iomv.c	Wed Dec 31 16:00:00 1969
@@ -1,97 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <asm/io.h>
-#include <linux/pci.h>
-
-static inline void *
-sn1_io_addr(unsigned long port)
-{
-	if (!IS_RUNNING_ON_SIMULATOR()) {
-		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
-	} else {
-		unsigned long io_base;
-		unsigned long addr;
- 
-		/*
- 		 * word align port, but need more than 10 bits
- 		 * for accessing registers in bedrock local block
- 		 * (so we don't do port&0xfff)
- 		 */
-		if (port >= 0x1f0 && port <= 0x1f7 ||
-			port == 0x3f6 || port == 0x3f7) {
-			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
-			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
-		} else {
-			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
-		}
-		return(void *) addr;
-	}
-}
-
-unsigned int
-sn1_inb (unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-	unsigned char ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inw (unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-	unsigned short ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inl (unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-	unsigned int ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-void
-sn1_outb (unsigned char val, unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outw (unsigned short val, unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outl (unsigned int val, unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
diff -urN linux-2.4.16/arch/ia64/sn/sn1/irq.c lia64-2.4/arch/ia64/sn/sn1/irq.c
--- linux-2.4.16/arch/ia64/sn/sn1/irq.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/irq.c	Wed Dec 31 16:00:00 1969
@@ -1,183 +0,0 @@
-/*
- * Platform dependent support for SGI SN1
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000   Alan Mayer (ajm@sgi.com)
- * Copyright (C) 2000   Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <asm/current.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/types.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pciio_private.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn1/addrs.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/sn1/arch.h>
-#include <asm/sn/synergy.h>
-
-#define IRQ_BIT_OFFSET 64
-
-int bit_pos_to_irq(int bit)
-{
-	if (bit > 118)
-		bit = 118;
-	return (bit + IRQ_BIT_OFFSET);
-}
-
-static inline int irq_to_bit_pos(int irq)
-{
-	int bit = irq - IRQ_BIT_OFFSET;
-
-	if (bit > 63)
-		bit -= 64;
-	return bit;
-}
-
-static unsigned int
-sn1_startup_irq(unsigned int irq)
-{
-        return(0);
-}
-
-static void
-sn1_shutdown_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_disable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_enable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_ack_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_end_irq(unsigned int irq)
-{
-	int bit;
-
-	bit = irq_to_bit_pos(irq);
-	LOCAL_HUB_CLR_INTR(bit);
-}
-
-static void
-sn1_set_affinity_irq(unsigned int irq, unsigned long mask)
-{
-}
-
-struct hw_interrupt_type irq_type_sn1 = {
-        "sn1_irq",
-        sn1_startup_irq,
-        sn1_shutdown_irq,
-        sn1_enable_irq,
-        sn1_disable_irq,
-        sn1_ack_irq,
-        sn1_end_irq,
-        sn1_set_affinity_irq
-};
-
-
-void
-sn1_irq_init (void)
-{
-	int i;
-
-	for (i = 0; i <= NR_IRQS; ++i) {
-		if (idesc_from_vector(i)->handler == &no_irq_type) {
-			idesc_from_vector(i)->handler = &irq_type_sn1;
-		}
-	}
-}
-
-
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-void
-sn1_pci_fixup(int arg)
-{
-}
-#endif
-
-#ifdef CONFIG_PERCPU_IRQ
-
-extern irq_desc_t irq_descX[NR_IRQS];
-irq_desc_t *irq_desc_ptr[NR_CPUS] = { irq_descX };
-
-/*
- * Each slave AP allocates its own irq table.
- */
-int __init cpu_irq_init(void)
-{
-	irq_desc_ptr[smp_processor_id()] = (irq_desc_t *)kmalloc(sizeof(irq_descX), GFP_KERNEL);
-	if (irq_desc_ptr[smp_processor_id()] == 0)
-		return(-1);
-	memcpy(irq_desc_ptr[smp_processor_id()], irq_desc_ptr[0], 
-							sizeof(irq_descX));
-	return(0);
-}
-
-/*
- * This can also allocate the irq tables for the other cpus, specifically
- * on their nodes.
- */
-int __init master_irq_init(void)
-{
-	return(0);
-}
-
-/*
- * The input is an ivt level.
- */
-irq_desc_t *idesc_from_vector(unsigned int ivnum)
-{
-	return(irq_desc_ptr[smp_processor_id()] + ivnum);
-}
-
-/*
- * The input is a "soft" level, that we encoded in.
- */
-irq_desc_t *idesc_from_irq(unsigned int irq)
-{
-	return(irq_desc_ptr[irq >> 8] + (irq & 0xff));
-}
-
-unsigned int ivector_from_irq(unsigned int irq)
-{
-	return(irq & 0xff);
-}
-
-/*
- * This should return the Linux irq # for the i/p vector on the
- * i/p cpu. We currently do not track this.
- */
-unsigned int irq_from_cpuvector(int cpunum, unsigned int vector)
-{
-	return (vector);
-}
-
-#endif /* CONFIG_PERCPU_IRQ */
diff -urN linux-2.4.16/arch/ia64/sn/sn1/llsc4.c lia64-2.4/arch/ia64/sn/sn1/llsc4.c
--- linux-2.4.16/arch/ia64/sn/sn1/llsc4.c	Mon Nov 26 11:18:25 2001
+++ lia64-2.4/arch/ia64/sn/sn1/llsc4.c	Wed Dec 31 16:00:00 1969
@@ -1,952 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <linux/kernel_stat.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <asm/efi.h>
-#include <asm/page.h>
-#include <linux/threads.h>
-
-extern void bringup_set_led_bits(u8 bits, u8 mask);
-
-#include "llsc4.h"
-
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-#ifdef INTTEST
-static int	inttest=0;
-#endif
-
-/*
- * Test parameter table for AUTOTEST
- */
-typedef struct {
-	int	passes;
-	int	linecount;
-	int	linepad;
-} autotest_table_t;
-
-autotest_table_t autotest_table[] = {
-	{5000000,	2,	0x2b4		},
-	{5000000,	16,	0,		},
-	{5000000,	16,	4,		},
-	{5000000,	128,	0x44		},
-	{5000000,	128,	0x84		},
-	{5000000,	128,	0x200		},
-	{5000000,	128,	0x204		},
-	{5000000,	128,	0x2b4		},
-	{5000000,	2,	8*MB+0x2b4	},
-	{5000000,	16,	8*MB+0		},
-	{5000000,	16,	8*MB+4		},
-	{5000000,	128,	8*MB+0x44	},
-	{5000000,	128,	8*MB+0x84	},
-	{5000000,	128,	8*MB+0x200	},
-	{5000000,	128,	8*MB+0x204	},
-	{5000000,	128,	8*MB+0x2b4	},
-	{0}};
-
-/*
- * Array of virtual addresses available for test purposes.
- */
-
-typedef struct {
-	long	vstart;
-	long	vend;
-	long	nextaddr;
-	int	wrapcount;
-} memmap_t;
-
-memmap_t 	memmap[MAXCHUNKS];
-int		memmapx=0;
-
-typedef struct {
-	void	*addr;
-	long	data[16];
-	long	data_fc[16];
-} capture_line_t;
-
-typedef struct {
-	int	size;
-	void	*blockaddr;
-	void	*shadaddr;
-	long	blockdata[16];
-	long	shaddata[16];
-	long	blockdata_fc[16];
-	long	shaddata_fc[16];
-	long	synerr;
-} capture_t;
-
-/*
- * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
- * the rest of the tables have to start at 1MB to skip PROM tables.
- */
-#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512)))
-
-#define k_capture		mbase->sk_capture
-#define k_go			mbase->sk_go
-#define k_linecount		mbase->sk_linecount
-#define k_passes		mbase->sk_passes
-#define k_napticks		mbase->sk_napticks
-#define k_stop_on_error		mbase->sk_stop_on_error
-#define k_verbose		mbase->sk_verbose
-#define k_threadprivate		mbase->sk_threadprivate
-#define k_blocks		mbase->sk_blocks
-#define k_iter_msg		mbase->sk_iter_msg
-#define k_vv			mbase->sk_vv
-#define k_linepad		mbase->sk_linepad
-#define k_options		mbase->sk_options
-#define k_testnumber		mbase->sk_testnumber
-#define k_currentpass		mbase->sk_currentpass
-
-static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
-static control_t	*mbase;
-static vint		initialized=0;
-
-static unsigned int ran_conf_llsc(int);
-static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
-static void dumpline(void *, char *, char *, void *, void *, int);
-static int  checkstop(int, int, uint);
-static void spin(int);
-static void capturedata(capture_t *, uint, void *, void *, int);
-static int  randn(uint max, uint *seed);
-static uint zrandom (uint *zranseed);
-static int  set_lock(uint *, uint);
-static int  clr_lock(uint *, uint);
-static void Speedo(void);
-
-int autotest_enabled=0;
-static int llsctest_number=-1;
-static int errstop_enabled=0;
-static int fail_enabled=0;
-static int selective_trigger=0;
-static int dump_block_addrs_opt=0;
-static uint errlock=0;
-
-static int __init autotest_enable(char *str)
-{
-        autotest_enabled = 1;
-	return 1;
-}
-static int __init set_llscblkadr(char *str)
-{
-	dump_block_addrs_opt = 1;
-	return 1;
-}
-static int __init set_llscselt(char *str)
-{
-	selective_trigger = 1;
-	return 1;
-}
-static int __init set_llsctest(char *str)
-{
-        llsctest_number = simple_strtol(str, &str, 10);
-	if (llsctest_number < 0 || llsctest_number > 15)
-		llsctest_number = -1;
-	return 1;
-}
-static int __init set_llscerrstop(char *str)
-{
-        errstop_enabled = 1;
-	return 1;
-}
-static int __init set_llscfail(char *str)
-{
-        fail_enabled = 8;
-	return 1;
-}
-
-static void print_params(void)
-{
-	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
-	printk ("  Test options:\n");
-	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
-	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
-	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
-	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
-	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
-	printk ("\n");
-}
-__setup("autotest", autotest_enable);
-__setup("llsctest=", set_llsctest);
-__setup("llscerrstop", set_llscerrstop);
-__setup("llscfail", set_llscfail);
-__setup("llscselt", set_llscselt);
-__setup("llscblkadr", set_llscblkadr);
-
-
-extern inline int
-set_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_acq(lock, 0, id);
-	return (old == 0);
-}
-
-extern inline int
-clr_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_rel(lock, id, 0);
-	return (old == id);
-}
-
-extern inline void
-zero_lock(uint *lock)
-{
-	*lock = 0;
-}
-
-/*------------------------------------------------------------------------+
-| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
-| Description: This test checks the coherency of shared data              |
-+------------------------------------------------------------------------*/
-static unsigned int
-ran_conf_llsc(int thread)
-{
-	private_t	pval;
-	share_t		sval, sval2;
-	uint		vv, linei, slinei, sharei, pass;
-	long		t;
-	lock_t		lockpat;
-	share_t		*sharecopy;
-	long		verbose, napticks, passes, linecount, lcount;
-	dataline_t	*linep, *slinep;
-	int		s, seed;
-	threadprivate_t	*tp;
-	uint		iter_msg, iter_msg_i=0;
-	int		vv_mask;
-	int		correct_errors;
-	int		errs=0;
-	int		stillbad;
-	capture_t	capdata;
-	private_t	*privp;
-	share_t		*sharep;
-
-
-	linecount = k_linecount;
-	napticks = k_napticks;
-	verbose = k_verbose;
-	passes = k_passes;
-	iter_msg = k_iter_msg;
-	seed = (thread + 1) * 647;
-	tp = THREADPRIVATE(thread);
-	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
-	correct_errors = k_options&0xff;
-
-	memset (&tp->private, 0, sizeof(tp->private));
-	memset (&capdata, 0, sizeof(capdata));
-
-	for (pass = 1; passes == 0 || pass < passes; pass++) {
-		lockpat = (pass & 0x0fffffff) + (thread <<28);
-		tp->threadpasses = pass;
-		if (checkstop(thread, pass, lockpat))
-			return 0;
-		iter_msg_i++;
-		if (iter_msg && iter_msg_i > iter_msg) {
-			printk("Thread %d, Pass %d\n", thread, pass);
-			iter_msg_i = 0;
-		}
-		lcount = 0;
-
-		/*
-		 * Select line to perform operations on.
-		 */
-		linei = randn(linecount, &seed);
-		sharei = randn(2, &seed);
-		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
-
-		linep = (dataline_t *)blocks[linei];
-		slinep = (dataline_t *)blocks[slinei];
-		if (sharei == 0)
-			sharecopy = &slinep->share0;
-		else
-			sharecopy = &slinep->share1;
-
-
-		vv = randn(4, &seed);
-		if ((vv_mask & (1<<vv)) == 0)
-			continue;
-
-		if (napticks) {
-			t = randn(napticks, &seed);
-			udelay(t);
-		}
-		privp = &linep->private[thread];
-		sharep = &linep->share[sharei];
-		
-		switch(vv) {
-		case 0:
-			/* Read and verify private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors) {
-					tp->private[linei] = *privp;
-				}
-				errs++;
-			}
-			break;
-
-		case 1:
-			/* Read, verify, and increment private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-			pval++;
-			*privp = pval;
-			tp->private[linei] = pval;
-			break;
-
-		case 2:
-			/* Lock line, read and verify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (pass > 12 && thread == 0 && fail_enabled == 1)
-				sval++;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors)
-					*sharep = *sharecopy;
-				errs++;
-			}
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-
-		case 3:
-			/* Lock line, read and verify shared data, modify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-
-			*sharep = lockpat;
-			*sharecopy = lockpat;
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-		}
-	}
-
-	return (errs > 0);
-}
-
-static void
-trigger_la(long val)
-{
-	long	*p;
-
-	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
-	*p = val;
-}
-
-static long
-getsynerr(void)
-{
-	long	err, *errp;
-
-	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
-	err = *errp;
-	if (err)
-		*errp = -1L;
-	return (err & ~0x60);
-}
-
-static int
-rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int linei, int exp, int found, int stillbad)
-{
-	int		cpu, i;
-	long 		synerr;
-	int		selt;
-
-
-	selt = selective_trigger && stillbad > 1 && 
-			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
-			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
-	if (selt) {
-		trigger_la(pass);
-	} else if (selective_trigger) {
-		k_go = ST_STOP;
-		return k_stop_on_error;;
-	}
-
-	spin(1);
-	i = 100;
-	while (i && set_lock(&errlock, 1) != 1) {
-		spin(1);
-		i--;
-	}
-	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
-	    msg, k_testnumber, thread, linei, pass, pass, jiffies, exp, found);
-
-	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
-	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
-		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
-
-	if (cap->shadaddr) {
-		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
-		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
-			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
-	}
-	
-	printk("Threadpasses: ");
-	for (cpu=0; cpu<MAXCPUS; cpu++)
-		if (k_threadprivate[cpu]->threadpasses)
-			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
-
-
-	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
-	synerr = getsynerr();
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	spin(2);
-	printk("\n\n");
-	clr_lock(&errlock, 1);
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	return k_stop_on_error;
-}
-
-
-static void
-dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
-{
-	long *p;
-	int i, off;
-
-	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
-	p = (long*) data;
-	for (i=0; i<16; i++, p++) {
-		if (i==0) printk("%2s", str2);
-		if (i==8) printk("  ");
-		printk(" %016lx", *p);
-		if ((i&7)==7) printk("\n");
-	}
-	printk("   ");
-	off = (((long)addr) ^ size) & 63L;
-	for (i=0; i<off+size; i++) {
-		printk("%s", (i>=off) ? "--" : "  ");
-		if ((i%8) == 7)
-			printk(" ");
-	}
-
-	off = ((long)addr) & 127;
-	printk(" (line %d)\n", off/64+1);
-}
-
-
-static int
-randn(uint max, uint *seedp)
-{
-	if (max == 1)
-		return(0);
-	else
-		return((int)(zrandom(seedp)>>10) % max);
-}
-
-
-static int
-checkstop(int thread, int pass, uint lockpat)
-{
-	long	synerr;
-
-	if (k_go == ST_RUN)
-		return 0;
-	if (k_go == ST_STOP)
-		return 1;
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	synerr = getsynerr();
-	spin(2);
-	if (k_go == ST_STOP)
-		return 1;
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	return 1;
-}
-
-
-static void
-spin(int j)
-{
-	udelay(j * 500000);
-}
-
-static void
-capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
-{
-
-	if (!selective_trigger)
-		trigger_la (pass);
-
-	memcpy (cap->blockdata, CACHEALIGN(blockaddr), 128);
-	if (shadaddr) 
-		memcpy (cap->shaddata, CACHEALIGN(shadaddr), 128);
-
-	if (k_stop_on_error) {
-		k_go = ST_ERRSTOP;
-	}
-
- 	cap->size = size;
-	cap->blockaddr = blockaddr;
-	cap->shadaddr = shadaddr;
-
-	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
-	ia64_sync_i();
-	ia64_srlz_d();
-	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr), 128);
-
-	if (shadaddr) {
-		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
-		ia64_sync_i();
-		ia64_srlz_d();
-		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr), 128);
-	}
-}
-
-int             zranmult = 0x48c27395;
-
-static uint  
-zrandom (uint *seedp)
-{
-        *seedp = (*seedp * zranmult) & 0x7fffffff;
-        return (*seedp);
-}
-
-
-void
-set_autotest_params(void)
-{
-	static int	testnumber=-1;
-
-	if (llsctest_number >= 0) {
-		testnumber = llsctest_number;
-	} else {
-		testnumber++;
-		if (autotest_table[testnumber].passes == 0) {
-			testnumber = 0;
-			dump_block_addrs_opt = 0;
-		}
-	}
-	k_passes = autotest_table[testnumber].passes;
-	k_linepad = autotest_table[testnumber].linepad;
-	k_linecount = autotest_table[testnumber].linecount;
-	k_testnumber = testnumber;
-
-	if (IS_RUNNING_ON_SIMULATOR()) {
-		printk ("llsc start test %ld\n", k_testnumber);
-		k_passes = 1000;
-	}
-}
-
-
-static void
-set_leds(int errs)
-{
-	unsigned char	leds=0;
-
-	/*
-	 * Leds are:
-	 * 	ppppeee-  
-	 *   where
-	 *      pppp = test number
-	 *       eee = error count but top bit is stick
-	 */
-
-	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
-	bringup_set_led_bits(leds, 0xfe);
-}
-
-static void
-setup_block_addresses(void)
-{
-	int		i, stride, memmapi;
-
-	stride = LINESTRIDE;
-	memmapi = 0;
-	for (i=0; i<memmapx; i++) {
-		memmap[i].nextaddr = memmap[i].vstart;
-		memmap[i].wrapcount = 0;
-	}
-
-	for (i=0; i<k_linecount; i++) {
-		blocks[i] = memmap[memmapi].nextaddr;
-		memmap[memmapi].nextaddr += stride;
-		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
-			memmap[memmapi].wrapcount++;
-			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
-					memmap[memmapi].wrapcount * sizeof(dataline_t);
-		}
-
-		memset((void*)blocks[i], 0, sizeof(dataline_t));
-
-		if (stride > 16384) {
-			memmapi++;
-			if (memmapi == memmapx)
-				memmapi = 0;
-		}
-	}
-
-}
-
-static void
-dump_block_addrs(void)
-{
-	int	i;
-
-	printk("LLSC TestNumber %ld\n", k_testnumber);
-
-	for (i=0; i<k_linecount; i++) {
-		printk("  %lx", blocks[i]);
-		if (i%4 == 3)
-			printk("\n");
-	}
-	printk("\n");
-}
-
-
-static void
-set_thread_state(int cpuid, int state)
-{
-	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
-		bringup_set_led_bits(0xfe, 0xfe);
-		while(1);
-	}
-	k_threadprivate[cpuid]->threadstate = state;
-}
-
-static int
-build_mem_map(unsigned long start, unsigned long end, void *arg)
-{
-	long	lstart;
-	long	align = 8*MB;
-	/*
-	 * HACK - skip the kernel on the first node 
-	 */
-
-	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
-		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
-
-	while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0))
-		end -= PAGE_SIZE;
-
-	lstart = end;
-	while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0))
-		lstart -= PAGE_SIZE;
-
-	lstart = (lstart + align -1) /align * align;
-	end = end / align * align;
-	if (lstart >= end)
-		return 0;
-	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
-
-	memmap[memmapx].vstart = lstart;
-	memmap[memmapx].vend = end;
-	memmapx++;
-	return 0;
-}
-
-void int_test(void);
-
-int
-llsc_main (int cpuid, long mbasex)
-{
-	int		i, cpu, is_master, repeatcnt=0;
-	unsigned int	preverr=0, errs=0, pass=0;
-	int		automode=0;
-
-#ifdef INTTEST
-	if (inttest)
-		int_test();
-#endif
-
-	if (!autotest_enabled)
-		return 0;
-
-#ifdef CONFIG_SMP
-	is_master = !smp_processor_id();
-#else
-	is_master = 1;
-#endif
-
-
-	if (is_master) {
-		print_params();
-		if(!IS_RUNNING_ON_SIMULATOR())
-			spin(10);
-		mbase = (control_t*)mbasex;
-		k_currentpass = 0;
-		k_go = ST_IDLE;
-		k_passes = DEF_PASSES;
-		k_napticks = DEF_NAPTICKS;
-		k_stop_on_error = DEF_STOP_ON_ERROR;
-		k_verbose = DEF_VERBOSE;
-		k_linecount = DEF_LINECOUNT;
-		k_iter_msg = DEF_ITER_MSG;
-		k_vv = DEF_VV;
-		k_linepad = DEF_LINEPAD;
-		k_blocks = (void*)blocks;
-		efi_memmap_walk(build_mem_map, 0);
-	
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-		automode = 1;
-#endif
-
-		for (i=0; i<MAXCPUS; i++) {
-			k_threadprivate[i] = THREADPRIVATE(i);
-			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
-		}
-		initialized = 1;
-	} else {
-		while (initialized == 0)
-			udelay(100);
-	}
-
-loop:
-	if (is_master) {
-		if (automode) {
-			if (!preverr || repeatcnt++ > 5) {
-				set_autotest_params();
-				repeatcnt = 0;
-			}
-		} else {
-			while (k_go == ST_IDLE);
-		}
-
-		k_go = ST_INIT;
-		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
-		k_linecount = k_linecount & ~1;
-		setup_block_addresses();
-		if (dump_block_addrs_opt)
-			dump_block_addrs();
-
-		k_currentpass = pass++;
-		k_go = ST_RUN;
-		if (fail_enabled)
-			fail_enabled--;
-
-	} else {
-		while (k_go != ST_RUN || k_currentpass != pass);
-		pass++;
-	}
-
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_RUNNING);
-
-	errs += ran_conf_llsc(cpuid);
-	preverr = (k_go == ST_ERRSTOP);
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_STOPPED);
-
-	if (is_master) {
-		Speedo();
-		for (i=0, cpu=0; cpu<MAXCPUS; cpu++) {
-			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
-				i++;
-				if (i == 10000) { 
-					k_go = ST_STOP;
-					printk ("  llsc master stopping test number %ld\n", k_testnumber);
-				}
-				if (i > 100000) {
-					k_threadprivate[cpu]->threadstate = TS_KILLED;
-					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
-							cpu, k_testnumber);
-				}
-				udelay(1000);
-			}
-		}
-	}
-
-	goto loop;
-}
-
-
-static void
-Speedo(void)
-{
-	static int i = 0;
-
-	switch (++i%4) {
-	case 0:
-		printk("|\b");
-		break;
-	case 1:
-		printk("\\\b");
-		break;
-	case 2:
-		printk("-\b");
-		break;
-	case 3:
-		printk("/\b");
-		break;
-	}
-}
-
-#ifdef INTTEST
-
-/* ======================================================================================================== 
- *
- * Some test code to verify that interrupts work
- *
- * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
- * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
- *
- * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
- *
- */
-
-static int __init set_inttest(char *str)
-{
-        inttest = 1;
-	autotest_enabled = 1;
-
-	return 1;
-}	
-
-__setup("inttest=", set_inttest);
-
-int	zzzprint_resched=0;
-
-void
-int_test() {
-	int			mycpu, cpu;
-	static volatile int	control_cpu=0;
-
-	mycpu = smp_processor_id();
-	zzzprint_resched = 2;
-
-	printk("Testing cross interrupts\n");
-	
-	while (control_cpu != smp_num_cpus) {
-		if (mycpu == cpu_logical_map(control_cpu)) {
-			for (cpu=0; cpu<smp_num_cpus; cpu++) {
-				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-			}
-			control_cpu++;
-		}
-	}
-
-	zzzprint_resched = 1;
-
-	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
-		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
-		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
-		__cli();
-		while (1) {
-			smp_send_reschedule(0);
-			udelay(100);
-		}
-
-	}
-
-	while(1);
-}
-#endif
diff -urN linux-2.4.16/arch/ia64/sn/sn1/llsc4.h lia64-2.4/arch/ia64/sn/sn1/llsc4.h
--- linux-2.4.16/arch/ia64/sn/sn1/llsc4.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/sn1/llsc4.h	Wed Dec 31 16:00:00 1969
@@ -1,104 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-
-#define DEF_NAPTICKS		0
-#define DEF_PASSES		0
-#define DEF_AUTO_PASSES		1000000
-#define DEF_STOP_ON_ERROR	1
-#define DEF_VERBOSE		0
-#define DEF_LINECOUNT		2
-#define DEF_ITER_MSG		0
-#define DEF_VV			0xffffffff
-#define DEF_LINEPAD		0x234
-
-
-
-#define MAXCPUS			16
-#define CACHELINE		64
-#define MAX_LINECOUNT		1024
-#define K			1024
-#define	MB			(K*K)
-
-
-#define	uint 		unsigned int
-#define	ushort		unsigned short
-#define vint		volatile int
-#define vlong		volatile long
-
-#define LOCKADDR(i)	&linep->lock[(i)]
-#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
-#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
-#define GETLOCK(i)	*LOCKADDR(i)
-#define ZEROLOCK(i)	zero_lock(LOCKADDR(i))
-
-#define CACHEALIGN(a)	((void*)((long)(a) & ~127L))
-
-typedef uint		lock_t;
-typedef uint		share_t;
-typedef uint		private_t;
-
-typedef struct {
-	lock_t		lock[2];
-	share_t		share[2];
-	private_t	private[MAXCPUS];
-	share_t		share0;
-	share_t		share1;
-} dataline_t ;
-
-
-#define LINEPAD			k_linepad
-#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
-
-
-typedef struct {
-	vint		threadstate;
-	uint		threadpasses;
-	private_t	private[MAX_LINECOUNT];
-} threadprivate_t;
-
-typedef struct {
-	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
-	long		sk_linecount;
-	long		sk_passes;
-	long		sk_napticks;
-	long		sk_stop_on_error;
-	long		sk_verbose;
-	long		sk_iter_msg;
-	long		sk_vv;
-	long		sk_linepad;
-	long		sk_options;
-	long		sk_testnumber;
-	vlong		sk_currentpass;
-	void 		*sk_blocks;
-	threadprivate_t	*sk_threadprivate[MAXCPUS];
-} control_t;
-
-/* Run state (k_go) constants */
-#define ST_IDLE		0
-#define ST_INIT		1
-#define ST_RUN		2
-#define ST_STOP		3
-#define ST_ERRSTOP	4
-
-
-/* Threadstate constants */
-#define TS_STOPPED	0
-#define	TS_RUNNING	1
-#define TS_KILLED	2
-
-
-
-int llsc_main (int cpuid, long mbasex);
-
diff -urN linux-2.4.16/arch/ia64/sn/sn1/machvec.c lia64-2.4/arch/ia64/sn/sn1/machvec.c
--- linux-2.4.16/arch/ia64/sn/sn1/machvec.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/machvec.c	Wed Dec 31 16:00:00 1969
@@ -1,18 +0,0 @@
-#define MACHVEC_PLATFORM_NAME	sn1
-#include <asm/machvec_init.h>
-#include <asm/io.h>
-#include <linux/pci.h>
-void*
-sn1_mk_io_addr_MACRO
-
-dma_addr_t
-sn1_pci_map_single_MACRO
-
-int
-sn1_pci_map_sg_MACRO
-
-unsigned long
-sn1_virt_to_phys_MACRO
-
-void *
-sn1_phys_to_virt_MACRO
diff -urN linux-2.4.16/arch/ia64/sn/sn1/mm.c lia64-2.4/arch/ia64/sn/sn1/mm.c
--- linux-2.4.16/arch/ia64/sn/sn1/mm.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/mm.c	Wed Dec 31 16:00:00 1969
@@ -1,394 +0,0 @@
-/*
- * Copyright, 2000-2001, Silicon Graphics.
- * Copyright Srinivasa Thirumalachar (sprasad@engr.sgi.com)
- * Copyright 2000-2001 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/page.h>
-#include <asm/efi.h>
-#include <asm/sn/mmzone_sn1.h>
-
-#define MIN(a,b)	((a) < (b) ? (a) : (b))
-#define MAX(a,b)	((a) > (b) ? (a) : (b))
-
-#define DONE_NOTHING	0
-#define DONE_FINDING	1
-#define DONE_BUILDING	2
-
-struct nodemem_s {
-        u64     start;	/* start of kernel usable memory */
-        u64     end;	/* end of kernel usable memory */
-	u64	mtot;	/* total kernel usable memory */
-	u64	done;	/* state of bootmem initialization */
-	u64	bstart;	/* where should the bootmem area be */
-	u64	bsize;	/* bootmap size */
-        u64 	hole[SN1_MAX_BANK_PER_NODE];
-} nodemem[MAXNODES];
-
-static int nodemem_valid = 0;
-
-static int __init
-free_unused_memmap_hole(int nid, unsigned long start, unsigned long end)
-{
-        struct page * page, *pageend;
-        unsigned long count = 0;
-
-	if (start >= end)
-		return 0;
-
-	/*
-	 * Get the memmap ptrs to the start and end of the holes.
-	 * virt_to_page(start) will panic, if start is in hole.
-	 * Can we do virt_to_page(end), if end is on the next node?
-	 */
-
-	page = virt_to_page(start - 1);
-	page++;
-	pageend = virt_to_page(end);
-
-	printk("hpage=0x%lx, hpageend=0x%lx\n", (u64)page, (u64)pageend) ;
-	free_bootmem_node(NODE_DATA(nid), __pa(page), (u64)pageend - (u64)page);
-
-	return count;
-}
-
-static void __init
-free_unused_memmap_node(int nid)
-{
-	u64	i = 0;
-	u64	holestart = -1;
-	u64	start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	do {
-		holestart = nodemem[nid].hole[i];
-		i++;
-		while ((i < SN1_MAX_BANK_PER_NODE) && 
-					(nodemem[nid].hole[i] == (u64)-1))
-			i++;
-		if (i < SN1_MAX_BANK_PER_NODE)
-			free_unused_memmap_hole(nid, holestart, 
-				start + (i<<SN1_BANK_ADDR_SHIFT));
-	} while (i<SN1_MAX_BANK_PER_NODE);
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasid/banks covered by the input memory descriptor.
- */
-static int __init
-build_nodemem_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	unsigned long nvaddr;
-	int nasid = GetNasId(__pa(vaddr));
-	int cnodeid, bankid;
-
-	while (vaddr < end) {
-		cnodeid = NASID_TO_CNODEID(nasid);
-		bankid = GetBankId(__pa(vaddr));
-		nodemem[cnodeid].start = MIN(nodemem[cnodeid].start, vaddr);
-		nvaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-		nodemem[cnodeid].end = MAX(nodemem[cnodeid].end, MIN(end, nvaddr));
-		while ((bankid < SN1_MAX_BANK_PER_NODE) && 
-					(vaddr < nodemem[cnodeid].end)) {
-			nvaddr = nodemem[cnodeid].start + 
-			  ((unsigned long)(bankid + 1) << SN1_BANK_ADDR_SHIFT);
-			nodemem[cnodeid].hole[bankid++] = MIN(nvaddr, end);
-			vaddr = nvaddr;
-		}
-	}
-
-	return 0;
-}
-
-static int __init
-pgtbl_size_ok(int nid)
-{
-	unsigned long numpfn, bank0size, nodesize ;
-	unsigned long start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	
-	nodesize 	= nodemem[nid].end - start ;
-	numpfn 		= nodesize >> PAGE_SHIFT;
-
-	bank0size 	= nodemem[nid].hole[0] - start ;
-	/* If nid == master node && no kernel text replication */
-	bank0size      -= 0xA00000 ;	/* Kernel text + stuff */
-	bank0size      -= ((numpfn + 7) >> 3);
-
-	if ((numpfn * sizeof(mem_map_t)) > bank0size) {
-		printk("nid = %d, ns=0x%lx, npfn=0x%lx, bank0size=0x%lx\n", 
-			nid, nodesize, numpfn, bank0size) ;
-		return 0 ;
-	}
-
-	return 1 ;
-}
-
-static void __init
-check_pgtbl_size(int nid)
-{
-	int	bank = SN1_MAX_BANK_PER_NODE - 1 ;
-
-	/* Find highest bank with valid memory */
-        while ((nodemem[nid].hole[bank] == -1) && (bank))
-               bank-- ;
-
-	while (!pgtbl_size_ok(nid)) {
-		/* Remove that bank of memory */
-		/* Collect some numbers later */
-		printk("Ignoring node %d bank %d\n", nid, bank) ;
-		nodemem[nid].hole[bank--] = -1 ;
-		/* Get to the next populated bank */
-		while ((nodemem[nid].hole[bank] == -1) && (bank))
-			bank-- ;
-		printk("Using only upto bank %d on node %d\n", bank,nid) ;
-		nodemem[nid].end = nodemem[nid].hole[bank] ; 
-		if (!bank) break ;
-	}
-}
-
-void dump_nodemem_map(int) ;
-
-#ifdef CONFIG_DISCONTIGMEM
-
-extern bootmem_data_t bdata[];
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order. It tries to identify first suitable free area to 
- * put the bootmem for the node in. When presented with the md holding
- * the kernel, it only searches at the end of the kernel area.
- */
-static int __init
-find_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int cnodeid = NASID_TO_CNODEID(nasid);
-	unsigned long nodesize;
-	extern char _end;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	/*
-	 * Track memory available to kernel.
-	 */
-	nodemem[cnodeid].mtot += ((end - start) >> PAGE_SHIFT);
-	if (nodemem[cnodeid].done != DONE_NOTHING)
-		return(0);
-	nodesize = nodemem[cnodeid].end - ((nodemem[cnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	nodesize >>= PAGE_SHIFT;
-
-	/*
-	 * Adjust limits for the md holding the kernel.
-	 */
-	if ((start < kaddr) && (end > kaddr))
-		start = PAGE_ALIGN(kaddr);
-
-	/*
-	 * We need space for mem_map, bootmem map plus a few more pages
-	 * to satisfy alloc_bootmems out of node 0.
-	 */
-	if ((end - start) > ((nodesize * sizeof(struct page)) + (nodesize/8)
-						+ (10 * PAGE_SIZE))) {
-		nodemem[cnodeid].bstart = start;
-		nodemem[cnodeid].done = DONE_FINDING;
-	}
-	return(0);
-}
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order.
- */
-static int __init
-build_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int curnodeid = NASID_TO_CNODEID(nasid);
-	int i;
-	unsigned long pstart, pend;
-	extern char _end, _stext;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	if (nodemem[curnodeid].done == DONE_FINDING) {
-		/*
-		 * This is where we come to know the node is present.
-		 * Do node wide tasks.
-		 */
-		nodemem[curnodeid].done = DONE_BUILDING;
-		NODE_DATA(curnodeid)->bdata = &(bdata[curnodeid]);
-
-		/*
-	 	 * Update the chunktonid array as a node wide task. There
-		 * are too many smalls mds on first node to do this per md.
-	 	 */
-		pstart = __pa(nodemem[curnodeid].start);
-		pend = __pa(nodemem[curnodeid].end);
-		pstart &= CHUNKMASK;
-		pend = (pend + CHUNKSZ - 1) & CHUNKMASK;
-		/* Possible check point to enforce minimum node size */
-		if (nodemem[curnodeid].bstart == -1) {
-			printk("No valid bootmem area on node %d\n", curnodeid);
-			while(1);
-		}
-		for (i = PCHUNKNUM(pstart); i <= PCHUNKNUM(pend - 1); i++)
-			chunktonid[i] = curnodeid;
-		if ((CHUNKTONID(PCHUNKNUM(pend)) > MAXCHUNKS) || 
-				(PCHUNKNUM(pstart) >= PCHUNKNUM(pend))) {
-			printk("Ign 0x%lx-0x%lx, ", __pa(start), __pa(end));
-			return(0);
-		}
-
-		/*
-		 * NODE_START and NODE_SIZE determine the physical range
-		 * on the node that mem_map array needs to be set up for.
-		 */
-		NODE_START(curnodeid) = ((nodemem[curnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-		NODE_SIZE(curnodeid) = (nodemem[curnodeid].end - 
-							NODE_START(curnodeid));
-
-        	nodemem[curnodeid].bsize = 
-			init_bootmem_node(NODE_DATA(curnodeid),
-			(__pa(nodemem[curnodeid].bstart) >> PAGE_SHIFT),
-			(__pa((nodemem[curnodeid].start >> SN1_NODE_ADDR_SHIFT)
-			<< SN1_NODE_ADDR_SHIFT) >> PAGE_SHIFT),
-			(__pa(nodemem[curnodeid].end) >> PAGE_SHIFT));
-
-	} else if (nodemem[curnodeid].done == DONE_NOTHING) {
-		printk("build_node_bootmem: node %d weirdness\n", curnodeid);
-		while(1);		/* Paranoia */
-	}
-
-	/*
-	 * Free the entire md.
-	 */
-	free_bootmem_node(NODE_DATA(curnodeid), __pa(start), (end - start));
-
-	/*
-	 * Reclaim back the bootmap and kernel areas.
-	 */
-	if ((start <= nodemem[curnodeid].bstart) && (end >
-						nodemem[curnodeid].bstart))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(nodemem[curnodeid].bstart), nodemem[curnodeid].bsize);
-	if ((start <= kaddr) && (end > kaddr))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(&_stext), (&_end - &_stext));
-
-	return(0);
-}
-
-void __init
-setup_sn1_bootmem(int maxnodes)
-{
-        int     i;
-
-        for (i = 0; i < MAXNODES; i++) {
-                nodemem[i].start = nodemem[i].bstart = -1;
-                nodemem[i].end = nodemem[i].bsize = nodemem[i].mtot = 0;
-		nodemem[i].done = DONE_NOTHING;
-		memset(&nodemem[i].hole, -1, sizeof(nodemem[i].hole));
-        }
-        efi_memmap_walk(build_nodemem_map, 0);
-
-	nodemem_valid = 1;
-
-	/* 
-	 * After building the nodemem map, check if the node memmap
-	 * will fit in the first bank of each node. If not change
-	 * the node end addr till it fits.
- 	 */
-
-        for (i = 0; i < maxnodes; i++)
-		check_pgtbl_size(i);
-
-	dump_nodemem_map(maxnodes);
-
-	efi_memmap_walk(find_node_bootmem, 0);
-	efi_memmap_walk(build_node_bootmem, 0);
-}
-#endif
-
-void __init
-discontig_paging_init(void)
-{
-	int i;
-	unsigned long max_dma, zones_size[MAX_NR_ZONES], holes_size[MAX_NR_ZONES];
-	extern void dump_node_data(void);
-
-	max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-	for (i = 0; i < numnodes; i++) {
-		unsigned long startpfn = __pa((void *)NODE_START(i)) >> PAGE_SHIFT;
-		unsigned long numpfn = NODE_SIZE(i) >> PAGE_SHIFT;
-		memset(zones_size, 0, sizeof(zones_size));
-		memset(holes_size, 0, sizeof(holes_size));
-		holes_size[ZONE_DMA] = numpfn - nodemem[i].mtot;
-
-		if ((startpfn + numpfn) < max_dma) {
-			zones_size[ZONE_DMA] = numpfn;
-		} else if (startpfn > max_dma) {
-			zones_size[ZONE_NORMAL] = numpfn;
-			panic("discontig_paging_init: %d\n", i);
-		} else {
-			zones_size[ZONE_DMA] = (max_dma - startpfn);
-			zones_size[ZONE_NORMAL] = numpfn - zones_size[ZONE_DMA];
-			panic("discontig_paging_init: %d\n", i);
-		}
-		free_area_init_node(i, NODE_DATA(i), NULL, zones_size, startpfn<<PAGE_SHIFT, holes_size);
-		free_unused_memmap_node(i);
-	}
-	dump_node_data();
-}
-
-/*
- * This used to be invoked from an SN1 specific hack in efi_memmap_walk.
- * It tries to ignore banks which the kernel is ignoring because bank 0 
- * is too small to hold the memmap entries for this bank.
- * The current SN1 efi_memmap_walk callbacks do not need this. That 
- * leaves the generic ia64 callbacks find_max_pfn, count_pages and
- * count_reserved_pages, of which the first can probably get by without
- * this, the last two probably need this, although they also can probably
- * get by. 
- */
-int
-sn1_bank_ignore(u64 start, u64 end)
-{
-	int 	nid = NASID_TO_CNODEID(GetNasId(__pa(end))) ;
-	int	bank = GetBankId(__pa(end)) ;
-
-	if (!nodemem_valid)
-		return 0 ;
-
-	if (nodemem[nid].hole[bank] == -1)
-		return 1 ;
-	else
-		return 0 ;
-}
-
-void
-dump_nodemem_map(int maxnodes)
-{
-	int	i,j;
-
-        printk("NODEMEM_S info ....\n") ;
-        printk("Node         start                end\n");
-        for (i=0;i<maxnodes;i++) {
-                printk("%d      0x%lx   0x%lx\n",
-                       i, nodemem[i].start, nodemem[i].end);
-                printk("Holes -> ") ;
-                for (j=0;j<SN1_MAX_BANK_PER_NODE;j++)
-                        printk("0x%lx ", nodemem[i].hole[j]) ;
-		printk("\n");
-        }
-}
-
diff -urN linux-2.4.16/arch/ia64/sn/sn1/probe.c lia64-2.4/arch/ia64/sn/sn1/probe.c
--- linux-2.4.16/arch/ia64/sn/sn1/probe.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/probe.c	Wed Dec 31 16:00:00 1969
@@ -1,62 +0,0 @@
-/*
- * Platform dependent support for IO probing.
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- */
-
-#include <asm/sn/sn_sal.h>
-
-/*
- * ia64_sn_probe_io_slot
- *	This function will probe a physical address to determine if
- *	the address can be read. If reading the address causes a BUS
- *	error, an error is returned. If the probe succeeds, the contents 
- *	of the memory location is returned.
- *
- *   Calling sequence:
- *		ia64_probe_io_slot(paddr, size, data_ptr)
- *
- *   Input:
- *	paddr		Physical address to probe
- *	size		Number bytes to read (1,2,4,8)
- *	data_ptr	Address to store value read by probe
- *		          (-1 returned if probe fails)
- *
- *   Output:
- *	Status
- *		 0 - probe successful
- *		 1 - probe failed (generated MCA)
- *		 2 - Bad arg
- *		<0 - PAL error
- */
-
-
-u64
-ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
-{
-	struct ia64_sal_retval isrv;
-
-	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
-
-	if (data_ptr) {
-		switch (size) {
-			case 1:
-				*((u8*)data_ptr) = (u8)isrv.v0;
-				break;
-			case 2:
-				*((u16*)data_ptr) = (u16)isrv.v0;
-				break;
-			case 4:
-				*((u32*)data_ptr) = (u32)isrv.v0;
-				break;
-			case 8:
-				*((u64*)data_ptr) = (u64)isrv.v0;
-				break;
-			default:
-				isrv.status = 2;	
-		}
-	}
-
-	return isrv.status;
-}
diff -urN linux-2.4.16/arch/ia64/sn/sn1/setup.c lia64-2.4/arch/ia64/sn/sn1/setup.c
--- linux-2.4.16/arch/ia64/sn/sn1/setup.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/setup.c	Wed Dec 31 16:00:00 1969
@@ -1,254 +0,0 @@
-/*
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/serial.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-#include <asm/machvec.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm-ia64/sn/arch.h>
-#include <asm-ia64/sn/addrs.h>
-
-
-/*
- * This is the address of the RRegs in the HSpace of the global
- * master.  It is used by a hack in serial.c (serial_[in|out],
- * printk.c (early_printk), and kdb_io.c to put console output on that
- * node's Bedrock UART.  It is initialized here to 0, so that
- * early_printk won't try to access the UART before
- * master_node_bedrock_address is properly calculated.
- */
-u64 master_node_bedrock_address = 0UL;
-
-static void sn_fix_ivt_for_partitioned_system(void);
-
-
-/*
- * The format of "screen_info" is strange, and due to early i386-setup
- * code. This is just enough to make the console code think we're on a
- * VGA color display.
- */
-struct screen_info sn1_screen_info = {
-	orig_x:			 0,
-	orig_y:			 0,
-	orig_video_mode:	 3,
-	orig_video_cols:	80,
-	orig_video_ega_bx:	 3,
-	orig_video_lines:	25,
-	orig_video_isVGA:	 1,
-	orig_video_points:	16
-};
-
-/*
- * This is here so we can use the CMOS detection in ide-probe.c to
- * determine what drives are present.  In theory, we don't need this
- * as the auto-detection could be done via ide-probe.c:do_probe() but
- * in practice that would be much slower, which is painful when
- * running in the simulator.  Note that passing zeroes in DRIVE_INFO
- * is sufficient (the IDE driver will autodetect the drive geometry).
- */
-char drive_info[4*16];
-
-unsigned long
-sn1_map_nr (unsigned long addr)
-{
-#ifdef CONFIG_DISCONTIGMEM
-	return MAP_NR_SN1(addr);
-#else
-	return MAP_NR_DENSE(addr);
-#endif
-}
-
-#if defined(BRINGUP) && defined(CONFIG_IA64_EARLY_PRINTK)
-void __init
-early_sn1_setup(void)
-{
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
-}
-#endif /* BRINGUP && CONFIG_IA64_EARLY_PRINTK */
-
-void __init
-sn1_setup(char **cmdline_p)
-{
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	struct serial_struct req;
-#endif
-
-	MAX_DMA_ADDRESS = PAGE_OFFSET + 0x10000000000UL;
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("sn1_setup: setting master_node_bedrock_address to 0x%lx\n",
-		   master_node_bedrock_address);
-
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	/*
-	 * We do early_serial_setup() to clean out the rs-table[] from the
-	 * statically compiled in version.
-	 */
-	memset(&req, 0, sizeof(struct serial_struct));
-	req.line = 0;
-	req.baud_base = 124800;
-	req.port = 0;
-	req.port_high = 0;
-	req.irq = 0;
-	req.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
-	req.io_type = SERIAL_IO_MEM;
-	req.hub6 = 0;
-	req.iomem_base = (u8 *)(master_node_bedrock_address + 0x80);
-	req.iomem_reg_shift = 3;
-	req.type = 0;
-	req.xmit_fifo_size = 0;
-	req.custom_divisor = 0;
-	req.closing_wait = 0;
-	early_serial_setup(&req);
-#endif /* CONFIG_SERIAL && !CONFIG_SERIAL_SGI_L1_PROTOCOL */
-
-	ROOT_DEV = to_kdev_t(0x0301);		/* default to first IDE drive */
-	sn_fix_ivt_for_partitioned_system();
-
-#ifdef CONFIG_SMP
-	init_smp_config();
-#endif
-	screen_info = sn1_screen_info;
-}
-
-
-/* 
- * sn_fix_ivt_for_partitioned_system
- *
- * This is an ugly hack that is needed for partitioned systems.
- *
- * On a partitioned system, most partitions do NOT have a physical address 0.
- * Unfortunately, the exception handling code in ivt.S has a couple of physical
- * addresses of kernel structures hardcoded into "movl" instructions.
- * These addresses are correct on partition 0 only. On all other partitions,
- * the addresses must be changed to reference the correct address.
- *
- * This routine scans the ivt code and replaces the hardcoded addresses with 
- * the correct address.
- *
- * Note that we could have made the ivt.S code dynamically determine the correct
- * address but this would add code to performance critical pathes. This option
- * was rejected.
- */
-
-#define TEMP_mlx	4		/* template type that contains movl instruction */
-#define TEMP_mlX	5		/* template type that contains movl instruction */
-
-typedef union {				/* Instruction encoding for movl instruction */
-	struct {
-		unsigned long	qp:6;
-		unsigned long	r1:7;
-		unsigned long	imm7b:7;
-		unsigned long	vc:1;
-		unsigned long	ic:1;
-		unsigned long	imm5c:5;
-		unsigned long	imm9d:9;
-		unsigned long	i:1;
-		unsigned long	op:4;
-		unsigned long	fill:23;
-	} b;
-	unsigned long	l;
-} movl_instruction_t;
-
-#define MOVL_OPCODE	6
-#define MOVL_ARG(a,b)	(((long)a.i<<63) | ((long)b<<22) | ((long)a.ic<<21) | \
-			((long)a.imm5c<<16) | ((long)a.imm9d<<7) | ((long)a.imm7b))
-
-typedef struct {				/* Instruction bundle */
-	unsigned long template:5;
-	unsigned long ins2:41;
-	unsigned long ins1l:18;
-	unsigned long ins1u:23;
-	unsigned long ins0:41;
-} instruction_bundle_t;
-
-
-static void __init
-sn_fix_ivt_for_partitioned_system(void)
-{
-	extern int		ia64_ivt;
-	instruction_bundle_t	*p, *pend;
-	movl_instruction_t	ins0, ins1, ins2;
-	long			new_ins1, phys_offset;
-	unsigned long		val;
-
-	/*
-	 * Setup to scan the ivt code.
-	 */
-	p = (instruction_bundle_t*)&ia64_ivt;
-	pend = p + 0x8000/sizeof(instruction_bundle_t);
-	phys_offset = __pa(p) & ~0x1ffffffffUL;
-
-	/*
-	 * Hunt for movl instructions that contain the node 0 physical address 
-	 * of "SWAPPER_PGD_ADDR".  These addresses must be relocated to reference the 
-	 * actual node that the kernel is loaded on.
-	 */
-	for (; p < pend; p++) {
-		if (p->template != TEMP_mlx && p->template != TEMP_mlX)
-			continue;
-		ins0.l =  p->ins0;
-		if (ins0.b.op != MOVL_OPCODE)
-			continue;
-		ins1.l =  ((long)p->ins1u<<18) | p->ins1l;
-		ins2.l =  p->ins2;
-		val = MOVL_ARG(ins0.b, ins1.l);
-
-		/*
-		 * Test for correct address. SWAPPER_PGD_ADDR will
-		 * always be a node 0 virtual address. Note that we cant
-		 * use the __pa or __va macros here since they may contain
-		 * debug code that gets fooled here.
-		 */
-		if ((PAGE_OFFSET | val)  != SWAPPER_PGD_ADDR)
-			continue;
-
-		/*
-		 * We found an instruction that needs to be fixed. The following
-		 * inserts the NASID of the ivt into the movl instruction.
-		 */
-		new_ins1 = ins1.l | (phys_offset>>22);
-		p->ins1l = new_ins1 & 0x3ffff;
-		p->ins1u = (new_ins1>>18) & 0x7fffff;
-		ia64_fc(p);
-	}
-
-	/*
-	 * Do necessary serialization.
-	 */
-	ia64_sync_i();
-	ia64_srlz_i();
-
-}
-
-int
-IS_RUNNING_ON_SIMULATOR(void)
-{
-#ifdef CONFIG_IA64_SGI_SN1_SIM
-	long sn;
-	asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2));
-	return(sn == SNMAGIC);
-#else
-	return(0);
-#endif
-}
diff -urN linux-2.4.16/arch/ia64/sn/sn1/smp.c lia64-2.4/arch/ia64/sn/sn1/smp.c
--- linux-2.4.16/arch/ia64/sn/sn1/smp.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/smp.c	Wed Dec 31 16:00:00 1969
@@ -1,186 +0,0 @@
-/*
- * SN1 Platform specific SMP Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jack Steiner <steiner@sgi.com>
- */
-
-
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/sal.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/current.h>
-#include <asm/sn/sn_cpuid.h>
-
-
-
-
-/*
- * The following structure is used to pass params thru smp_call_function
- * to other cpus for flushing TLB ranges.
- */
-typedef struct {
-	unsigned long	start;
-	unsigned long	end;
-	unsigned long	nbits;
-} ptc_params_t;
-
-
-/*
- * The following table/struct is for remembering PTC coherency domains. It
- * is also used to translate sapicid into cpuids. We dont want to start 
- * cpus unless we know their cache domain.
- */
-#ifdef PTC_NOTYET
-sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
-#endif
-
-
-
-#ifdef PTC_NOTYET
-/*
- * NOTE: This is probably not good enough, but I dont want to try to make
- * it better until I get some statistics on a running system. 
- * At a minimum, we should only send IPIs to 1 processor in each TLB domain
- * & have it issue a ptc.g on it's own FSB. Also, serialize per FSB, not 
- * globally.
- *
- * More likely, we will have to do some work to reduce the frequency of calls to
- * this routine.
- */
-
-static void
-sn1_ptc_local(void *arg)
-{
-	ptc_params_t	*params = arg;
-	unsigned long	start, end, nbits;
-
-	start = params->start;
-	end = params->end;
-	nbits = params->nbits;
-
-	do {
-		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
-		start += (1UL << nbits);
-	} while (start < end);
-}
-
-
-void
-sn1_ptc_global (unsigned long start, unsigned long end, unsigned long nbits)
-{
-	ptc_params_t	params;
-
-	params.start = start;
-	params.end = end;
-	params.nbits = nbits;
-
-	if (smp_call_function(sn1_ptc_local, &params, 1, 0) != 0)
-		panic("Unable to do ptc_global - timed out");
-
-	sn1_ptc_local(&params);
-}
-#endif
-
-
-
-
-void
-sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
-{
-	long		*p, nasid, slice;
-	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
-
-	/*
-	 * ZZZ - Replace with standard macros when available.
-	 */
-	nasid = cpuid_to_nasid(cpuid);
-	slice = cpuid_to_slice(cpuid);
-	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
-
-#if defined(ZZZBRINGUP)
-	{
-	static int count=0;
-	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
-		smp_processor_id(), cpuid, vector, nasid, slice, (long)p);
-	}
-#endif
-	mb();
-	*p = (delivery_mode << 8) | (vector & 0xff);
-	
-}
-
-
-#ifdef CONFIG_SMP
-
-#ifdef PTC_NOTYET
-static void __init
-process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
-{
-	ia64_sal_ptc_domain_proc_entry_t	*pe;
-	int 					i, sapicid, cpuid;
-
-	pe = __va(di->proc_list);
-	for (i=0; i<di->proc_count; i++, pe++) {
-		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
-		cpuid = cpu_logical_id(sapicid);
-		sn_sapicid_info[cpuid].domain = domain;
-		sn_sapicid_info[cpuid].sapicid = sapicid;
-	}
-}
-
-
-static void __init
-process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
-{
-	ia64_sal_ptc_domain_info_t	*di;
-	int i;
-
-	di = __va(ptc->domain_info);
-	for (i=0; i<ptc->num_domains; i++, di++) {
-		process_sal_ptc_domain_info(di, i);	
-	}
-}
-#endif
-
-
-void __init
-init_sn1_smp_config(void)
-{
-
-	if (!ia64_ptc_domain_info)  {
-		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
-		smp_num_cpus = 1;
-		return;
-	}
-
-#ifdef PTC_NOTYET
-	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
-	process_sal_desc_ptc(ia64_ptc_domain_info);
-#endif
-
-}
-
-#else /* CONFIG_SMP */
-
-void __init
-init_sn1_smp_config(void)
-{
-
-#ifdef PTC_NOTYET
-	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
-#endif
-}
-
-#endif /* CONFIG_SMP */
diff -urN linux-2.4.16/arch/ia64/sn/sn1/sn1_asm.S lia64-2.4/arch/ia64/sn/sn1/sn1_asm.S
--- linux-2.4.16/arch/ia64/sn/sn1/sn1_asm.S	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/sn1_asm.S	Wed Dec 31 16:00:00 1969
@@ -1,149 +0,0 @@
-
-/*
- * Copyright (C) 2000 Silicon Graphics
- * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-
-// Testing only.
-// Routine will cause MCAs
-//   zzzmsa(n)
-//      n=0 MCA via duplicate TLB dropin
-//      n=0 MCA via read of garbage address
-//
-
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
-
-                        .global zzzmca
-                        .proc   zzzmca
-zzzmca:
-                        alloc   loc4       = ar.pfs,2,8,1,0;;
-                        cmp.ne  p6,p0=r32,r0;;
-                        movl    r2=0x2dead
-                        movl    r3=0x3dead
-                        movl    r15=0x15dead
-                        movl    r16=0x16dead
-                        movl    r31=0x31dead
-                        movl    loc0=0x34beef
-                        movl    loc1=0x35beef
-                        movl    loc2=0x36beef
-                        movl    loc3=0x37beef
-                        movl    out0=0x42beef
-
-                        movl    r20=0x32feed;;
-                        mov     ar32=r20
-                        movl    r20=0x36feed;;
-                        mov     ar36=r20
-                        movl    r20=0x65feed;;
-                        mov     ar65=r20
-                        movl    r20=0x66feed;;
-                        mov     ar66=r20
-
-(p6)                    br.cond.sptk    1f
-
-                        rsm      0x2000;;
-                        srlz.d;
-                        mov      r11      = 1
-                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
-                        mov      cr.itir  = r3
-                        mov      r10      = 0;;
-                        itr.d    dtr[r11] = r10;;
-                        mov      r11      = 2
-
-                        itr.d    dtr[r11] = r10;;
-                        br      9f
-
-1:                      movl    r8=0xfe00000048;;
-                        ld8     r9=[r8];;
-                        mf
-                        mf.a
-                        srlz.d
-
-9:                      mov     ar.pfs=loc4
-                        br.ret.sptk     rp
-
-                        .endp   zzzmca
-
-                        .global zzzspec
-                        .proc   zzzspec
-zzzspec:
-			mov	r8=r32
-			movl	r9=0xe000000000000000
-			movl	r10=0x4000;;
-			ld8.s	r16=[r8];;
-			ld8.s	r17=[r9];;
-			add	r8=r8,r10;;
-			ld8.s	r18=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r19=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r20=[r8];;
-			mov	r8=r0
-			tnat.nz	p6,p0=r16
-			tnat.nz	p7,p0=r17
-			tnat.nz	p8,p0=r18
-			tnat.nz	p9,p0=r19
-			tnat.nz	p10,p0=r20;;
-		(p6)	dep	r8=-1,r8,0,1;;
-		(p7)	dep	r8=-1,r8,1,1;;
-		(p8)	dep	r8=-1,r8,2,1;;
-		(p9)	dep	r8=-1,r8,3,1;;
-		(p10)	dep	r8=-1,r8,4,1;;
-                        br.ret.sptk     rp
-                        .endp   zzzspec
-
-                        .global zzzspec2
-                        .proc   zzzspec2
-zzzspec2:
-			cmp.eq	p6,p7=r2,r2
-			movl	r16=0xc0000a0001000020
-			;;
-			mf
-			;;
-			ld8	r9=[r16]
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r16];;
-			cmp.ne	p6,p7=r9,r16
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r33];;
-			cmp.ne	p6,p7=r9,r33
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			tpa	r23=r32
-			add	r20=512,r33
-			add	r21=1024,r33;;
-			ld8	r9=[r20]
-			ld8	r10=[r21];;
-			nop.i	0
-			{ .mib
-			nop.m 0
-			cmp.ne	p6,p7=r10,r33
-		(p6)	br.spnt	1f
-			}
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-			br.ret.sptk     rp
-
-                        .endp   zzzspec
-
-#endif
-
diff -urN linux-2.4.16/arch/ia64/sn/sn1/sn1_ksyms.c lia64-2.4/arch/ia64/sn/sn1/sn1_ksyms.c
--- linux-2.4.16/arch/ia64/sn/sn1/sn1_ksyms.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/sn1_ksyms.c	Wed Dec 31 16:00:00 1969
@@ -1,39 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jesse Barnes (jbarnes@sgi.com)
- */
-
-
-/*
- * Architecture-specific kernel symbols
- */
-
-#include <linux/module.h>
-
-#include <asm/machvec.h>
-
-/*
- * I/O routines
- */
-EXPORT_SYMBOL(sn1_outb);
-EXPORT_SYMBOL(sn1_outl);
-EXPORT_SYMBOL(sn1_outw);
-EXPORT_SYMBOL(sn1_inw);
-EXPORT_SYMBOL(sn1_inb);
-EXPORT_SYMBOL(sn1_inl);
-
-/*
- * other stuff (more to be added later, cleanup then)
- */
-EXPORT_SYMBOL(sn1_pci_map_sg);
-EXPORT_SYMBOL(sn1_pci_unmap_sg);
-EXPORT_SYMBOL(sn1_pci_alloc_consistent);
-EXPORT_SYMBOL(sn1_pci_free_consistent);
-EXPORT_SYMBOL(sn1_dma_address);
-
-#include <linux/mm.h>
-EXPORT_SYMBOL(alloc_pages);
diff -urN linux-2.4.16/arch/ia64/sn/sn1/sv.c lia64-2.4/arch/ia64/sn/sn1/sv.c
--- linux-2.4.16/arch/ia64/sn/sn1/sv.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/sv.c	Wed Dec 31 16:00:00 1969
@@ -1,551 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.  All rights reserved
- *
- * This implemenation of synchronization variables is heavily based on
- * one done by Steve Lord <lord@sgi.com>
- *
- * Paul Cassella <pwc@sgi.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-
-#include <asm/semaphore.h>
-#include <asm/hardirq.h>
-#include <asm/softirq.h>
-#include <asm/current.h>
-
-#include <asm/sn/sv.h>
-
-/* Define this to have sv_test() run some simple tests.
-   kernel_thread() must behave as expected when this is called.  */
-#undef RUN_SV_TEST
-
-#define DEBUG
-
-/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
-   can sanity check interrupt state on architectures where we know
-   how. */
-#ifdef DEBUG
- #define SV_DEBUG_INTERRUPT_STATE
- #ifdef __mips64
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 31
- #elif defined(__ia64)
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
- #else
-  #undef  SV_DEBUG_INTERRUPT_STATE
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
- #endif /* __mips64 */
-#endif /* DEBUG */
-
-
-/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
-   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
-#ifdef TASK_EXCLUSIVE
-  #undef EXCLUSIVE_IN_QUEUE
-#else
-  #define EXCLUSIVE_IN_QUEUE
-  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
-#endif
-
-
-static inline void sv_lock(sv_t *sv) {
-	spin_lock(&sv->sv_lock);
-}
-
-static inline void sv_unlock(sv_t *sv) {
-	spin_unlock(&sv->sv_lock);
-}
-
-/* up() is "extern inline", so we can't pass its address to sv_wait.
-   Use this function's address instead. */
-static void up_wrapper(struct semaphore *sem) {
-	up(sem);
-}
-
-/* spin_unlock() is sometimes a macro. */
-static void spin_unlock_wrapper(spinlock_t *s) {
-	spin_unlock(s);
-}
-
-/* XXX Perhaps sv_wait() should do the switch() each time and avoid
-   the extra indirection and the need for the _wrapper functions? */
-
-static inline void sv_set_mon_type(sv_t *sv, int type) {
-	switch (type) {
-	case SV_MON_SPIN:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
-		break;
-	case SV_MON_SEMA:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)up_wrapper;
-		if(sv->sv_flags & SV_INTS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with interrupts if it is a "
-			       "semaphore!\n");
-			BUG();
-		}
-		if(sv->sv_flags & SV_BHS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with bottom-halves if it is "
-			       "a semaphore!\n");
-			BUG();
-		}
-		break;
-#if 0 
-	/*
-	 * If needed, and will need to think about interrupts.  This
-	 * may be needed, for example, if someone wants to use sv's
-	 * with something like dev_base; writers need to hold two
-	 * locks. 
-	 */
-	case SV_MON_CUSTOM: 
-		{
-		struct sv_mon_custom *c = lock;
-		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
-		sv->sv_mon_lock        = c->sv_mon_lock;
-		break;
-		}
-#endif
-		
-	default:
-		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
-		       "(flags 0x%x)\n", type, type, sv->sv_flags);
-		BUG();
-		break;
-	}
-	sv->sv_flags |= type;
-}
-
-static inline void sv_set_ord(sv_t *sv, int ord) {
-	if (!ord)
-		ord = SV_ORDER_DEFAULT;
-
-	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
-		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
-		       ord, ord);
-		BUG();
-	}
-
-	sv->sv_flags |= ord;
-}
-
-void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
-{
-	int ord = flags & SV_ORDER_MASK;
-	int type = flags & SV_MON_MASK;
-
-	/* Copy all non-order, non-type flags */
-	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
-
-	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
-	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
-	  BUG();
-	}
-
-	sv_set_ord(sv, ord);
-	sv_set_mon_type(sv, type);
-
-	/* If lock is NULL, we'll get it from sv_wait_compat() (and
-           ignore it in sv_signal() and sv_broadcast()). */
-	sv->sv_mon_lock = lock;
-
-	spin_lock_init(&sv->sv_lock);
-	init_waitqueue_head(&sv->sv_waiters);
-}
-
-/*
- * The associated lock must be locked on entry.  It is unlocked on return.
- *
- * Return values:
- *
- * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
- * n = 0 : timeout expired
- * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
- */
-signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
-{
-	DECLARE_WAITQUEUE( wait, current );
-	unsigned long flags;
-	signed long ret = 0;
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	{
-	unsigned long flags;
-	__save_flags(flags);
-
-	if(sv->sv_flags & SV_INTS) {
-		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
-			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
-			       "enabled (flags: 0x%lx)\n", flags);
-			BUG();
-		}
-	} else {
-		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
-			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
-			       "disabled! (flags: 0x%lx)\n", flags);
-		}
-	}
-	}
-#endif  /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-
-	sv->sv_mon_unlock_func(sv->sv_mon_lock);
-
-	/* Add ourselves to the wait queue and set the state before
-	 * releasing the sv_lock so as to avoid racing with the
-	 * wake_up() in sv_signal() and sv_broadcast(). 
-	 */
-
-	/* don't need the _irqsave part, but there is no wq_write_lock() */
-	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
-
-#ifdef EXCLUSIVE_IN_QUEUE
-	wait.flags |= WQ_FLAG_EXCLUSIVE;
-#endif
-
-	switch(sv->sv_flags & SV_ORDER_MASK) {
-	case SV_ORDER_FIFO:
-		__add_wait_queue_tail(&sv->sv_waiters, &wait);
-		break;
-	case SV_ORDER_FILO:
-		__add_wait_queue(&sv->sv_waiters, &wait);
-		break;
-	default:
-		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
-					sv, sv->sv_flags);
-		BUG();
-	}
-	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
-
-	if(sv_wait_flags & SV_WAIT_SIG)
-		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
-	else
-		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
-
-	spin_unlock(&sv->sv_lock);
-
-	if(sv->sv_flags & SV_INTS)
-		local_irq_enable();
-	else if(sv->sv_flags & SV_BHS)
-		local_bh_enable();
-
-	if (timeout)
-		ret = schedule_timeout(timeout);
-	else
-		schedule();
-
-	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
-		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
-		       "schedule().\n");
-		set_current_state(TASK_RUNNING);
-	}
-
-	remove_wait_queue(&sv->sv_waiters, &wait);
-
-	/* Return cases:
-	   - woken by a sv_signal/sv_broadcast
-	   - woken by a signal
-	   - woken by timeout expiring
-	*/
-
-	/* XXX This isn't really accurate; we may have been woken
-           before the signal anyway.... */
-	if(signal_pending(current))
-		return timeout ? -ret : -1;
-	return timeout ? ret : 1;
-}
-
-
-void sv_signal(sv_t *sv) 
-{
-	/* If interrupts can acquire this lock, they can also acquire the
-	   sv_mon_lock, which we must already have to have called this, so
-	   interrupts must be disabled already.  If interrupts cannot
-	   contend for this lock, we don't have to worry about it. */
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_signal: SV_INTS and "
-			"interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_broadcast(sv_t *sv) 
-{
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_broadcast: SV_INTS and "
-			       "interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up_all(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_destroy(sv_t *sv) 
-{
-	if(!spin_trylock(&sv->sv_lock)) {
-		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", sv);
-		BUG();
-	}
-
-	/* XXX Check that the waitqueue is empty? 
-	       Mark the sv destroyed?
-	*/
-}
-
-
-#ifdef RUN_SV_TEST
-
-static DECLARE_MUTEX_LOCKED(talkback);
-static DECLARE_MUTEX_LOCKED(sem);
-sv_t sv;
-sv_t sv_filo;
-
-static int sv_test_1_w(void *arg) 
-{
-	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
-
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
-
-	up(&sem);
-
-	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
-
-	sv_spin_wait(&sv, arg);
-
-	printk("sv_test_1_w: talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_1_w: exiting.\n");
-	return 0;
-}
-
-static int sv_test_1_s(void *arg) 
-{
-	printk("sv_test_1_s: waiting for semaphore.\n");
-	down(&sem);
-	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
-	sv_signal(&sv);
-	printk("sv_test_1_s: talkback.\n");
-	up(&talkback);
-	printk("sv_test_1_s: exiting.\n");
-	return 0;
-
-}
-
-static int count;
-static DECLARE_MUTEX(monitor);
-
-static int sv_test_2_w(void *arg) 
-{
-	int dummy = count++;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	up(&talkback);
-	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
-	sv_sema_wait(sv, &monitor);
-	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
-	up(&sem);
-	return 0;
-}
-
-static int sv_test_2_s_1(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s_1: waking one thread.\n");
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
-	sv_signal(sv);
-	sv_broadcast(sv);
-	sv_signal(sv);
-	sv_broadcast(sv);
-
-	printk("sv_test_2_s_1: talkbacking.\n");
-	up(&talkback);
-	up(&monitor);
-	return 0;
-}
-
-static int sv_test_2_s(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
-	sv_broadcast(sv);
-	for(; i < 10; i++)
-		down(&sem);
-
-	printk("sv_test_3_s: sending talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_3_s: exiting.\n");
-	up(&monitor);
-	return 0;
-}
-
-
-static void big_test(sv_t *sv) 
-{
-	int i;
-
-	count = 0;
-
-	for(i = 0; i < 3; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning first wake-up thread.\n");
-	kernel_thread(sv_test_2_s_1, sv, 0);
-
-	down(&talkback);
-	printk("big_test: talkback happened.\n");
-
-
-	for(i = 3; i < 13; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning wake-up thread.\n");
-	kernel_thread(sv_test_2_s, sv, 0);
-
-	down(&talkback);
-}
-
-sv_t int_test_sv;
-spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
-int int_test_ready;
-static int irqtestcount;
-
-static int interrupt_test_worker(void *unused) 
-{
-	int id = ++irqtestcount;
-	int it = 0;
-			unsigned long flags, flags2;
-
-	printk("ITW: thread %d started.\n", id);
-
-	while(1) {
-		__save_flags(flags2);
-		if(jiffies % 3) {
-			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
-			spin_lock_irqsave(&int_test_spin, flags);
-		} else {
-			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
-			spin_lock_irq(&int_test_spin);
-		}
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
-		sv_wait(&int_test_sv, 0, 0);
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
-		set_current_state(TASK_INTERRUPTIBLE);
-		schedule_timeout(jiffies & 0xf);
-		if(current->state != TASK_RUNNING)
-		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
-		it++;
-	}
-}
-
-static void interrupt_test(void) 
-{
-	int i;
-
-	printk("interrupt_test: initing sv.\n");
-	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
-
-	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
-		printk("interrupt_test: starting test thread %d.\n", i);
-		kernel_thread(interrupt_test_worker, 0, 0);
-	}
-	printk("interrupt_test: done with init part.\n");
-	int_test_ready = 1;
-}
-
-int sv_test(void) 
-{
-	spinlock_t s = SPIN_LOCK_UNLOCKED;
-
-	sv_init(&sv, &s, SV_MON_SPIN);
-	printk("sv_test: starting sv_test_1_w.\n");
-	kernel_thread(sv_test_1_w, &s, 0);
-	printk("sv_test: starting sv_test_1_s.\n");
-	kernel_thread(sv_test_1_s, &s, 0);
-
-	printk("sv_test: waiting for talkback.\n");
-	down(&talkback); down(&talkback);
-	printk("sv_test: talkback happened, sv_destroying.\n");
-	sv_destroy(&sv);
-
-	count = 0;
-
-	printk("sv_test: beginning big_test on sv.\n");
-
-	sv_init(&sv, &monitor, SV_MON_SEMA);
-	big_test(&sv);
-	sv_destroy(&sv);
-
-	printk("sv_test: beginning big_test on sv_filo.\n");
-	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
-	big_test(&sv_filo);
-	sv_destroy(&sv_filo);
-
-	interrupt_test();
-
-	printk("sv_test: done.\n");
-	return 0;
-}
-
-__initcall(sv_test);
-
-#endif /* RUN_SV_TEST */
diff -urN linux-2.4.16/arch/ia64/sn/sn1/synergy.c lia64-2.4/arch/ia64/sn/sn1/synergy.c
--- linux-2.4.16/arch/ia64/sn/sn1/synergy.c	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/arch/ia64/sn/sn1/synergy.c	Wed Dec 31 16:00:00 1969
@@ -1,429 +0,0 @@
-
-/*
- * SN1 Platform specific synergy Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/proc_fs.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/synergy.h>
-
-int bit_pos_to_irq(int bit);
-void setclear_mask_b(int irq, int cpuid, int set);
-void setclear_mask_a(int irq, int cpuid, int set);
-void * kmalloc(size_t size, int flags);
-
-
-void
-synergy_intr_alloc(int bit, int cpuid) {
-	return;
-}
-
-int
-synergy_intr_connect(int bit, 
-		int cpuid)
-{
-	int irq;
-	unsigned is_b;
-
-	irq = bit_pos_to_irq(bit);
-
-	is_b = (cpuid_to_slice(cpuid)) & 1;
-	if (is_b) {
-		setclear_mask_b(irq,cpuid,1);
-		setclear_mask_a(irq,cpuid, 0);
-	} else {
-		setclear_mask_a(irq, cpuid, 1);
-		setclear_mask_b(irq, cpuid, 0);
-	}
-	return 0;
-}
-void
-setclear_mask_a(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-        /*
-         * Perform some idiot checks ..
-         */
-        if ( (irq < 0) || (irq > 255) ||
-                (cpuid < 0) || (cpuid > 512) ) {
-                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0A;
-			addr = VEC_MASK0A_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1A;
-			addr = VEC_MASK1A_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2A;
-			addr = VEC_MASK2A_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3A;
-			addr = VEC_MASK3A_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-void
-setclear_mask_b(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-	/*
-	 * Perform some idiot checks ..
-	 */
-	if ( (irq < 0) || (irq > 255) ||
-		(cpuid < 0) || (cpuid > 512) ) {
-		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0B;
-			addr = VEC_MASK0B_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1B;
-			addr = VEC_MASK1B_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2B;
-			addr = VEC_MASK2B_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3B;
-			addr = VEC_MASK3B_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-
-/*
- * Synergy perf registers. Multiplexed via timer_interrupt
- */
-static struct proc_dir_entry *synergy_perf_proc = NULL;
-
-/*
- * read handler for /proc/synergy
- */
-static int
-synergy_perf_read_proc (char *page, char **start, off_t off,
-                                 int count, int *eof, void *data)
-{
-	cnodeid_t       cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		len = 0;
-
-	len += sprintf(page+len, "# cnode module slot event synergy-A synergy-B\n");
-
-	/* walk the event list for each node */
-	for (cnode=0; cnode < numnodes; cnode++) {
-		npdap = NODEPDA(cnode);
-		if (npdap->synergy_perf_enabled == 0) {
-			len += sprintf(page+len, "# DISABLED\n");
-			break;
-		}
-
-		spin_lock_irq(&npdap->synergy_perf_lock);
-		for (p = npdap->synergy_perf_first; p;) {
-			uint64_t cnt_a=0, cnt_b=0;
-
-			if (p->intervals > 0) {
-				cnt_a = p->counts[0] * npdap->synergy_active_intervals / p->intervals;
-				cnt_b = p->counts[1] * npdap->synergy_active_intervals / p->intervals;
-			}
-
-			len += sprintf(page+len, "%d %d %d %12lx %lu %lu\n",
-				(int)cnode, (int)npdap->module_id, (int)npdap->slotdesc,
-				p->modesel, cnt_a, cnt_b);
-
-			p = p->next;
-			if (p == npdap->synergy_perf_first)
-				break;
-		}
-		spin_unlock_irq(&npdap->synergy_perf_lock);
-	}
-
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return len;
-}
-
-static int
-synergy_perf_append(uint64_t modesel)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		err = 0;
-
-	/* bit 45 is enable */
-	modesel |= (1UL << 45);
-
-	for (cnode=0; cnode < numnodes; cnode++) {
-		/* for each node, insert a new synergy_perf entry */
-		if ((npdap = NODEPDA(cnode)) == NULL) {
-			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, nodepda);
-			continue;
-		}
-
-		/* XX use kmem_alloc_node() when it is implemented */
-		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
-		if (p == NULL)
-			err = -ENOMEM;
-		else {
-			memset(p, 0, sizeof(synergy_perf_t));
-			p->modesel = modesel;
-			if (npdap->synergy_perf_data == NULL) {
-				/* circular list */
-				p->next = p;
-				npdap->synergy_perf_data = p;
-				npdap->synergy_perf_first = p;
-			}
-			else {
-				/*
-				 * Jumble up the insertion order so we get better sampling.
-				 * Once the list is complete, "first" stays the same so the
-				 * reporting order is consistent.
-				 */
-				p->next = npdap->synergy_perf_first->next;
-				npdap->synergy_perf_first->next = p;
-				npdap->synergy_perf_first = p->next;
-			}
-		}
-	}
-
-	return err;
-}
-
-static int
-synergy_perf_write_proc (struct file *file, const char *buffer,
-                                unsigned long count, void *data)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	uint64_t	modesel;
-	char		cmd[64];
-	extern long	atoi(char *);
-    
-	if (count == sizeof(uint64_t)) {
-	    if (copy_from_user(&modesel, buffer, sizeof(uint64_t)))
-		    return -EFAULT;
-	    synergy_perf_append(modesel);
-	}
-	else {
-	    if (copy_from_user(cmd, buffer, count < sizeof(cmd) ? count : sizeof(cmd)))
-		    return -EFAULT;
-	    if (strncmp(cmd, "enable", 6) == 0) {
-		/* enable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 1;
-		}
-		printk("NOTICE: synergy perf counting enabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "disable", 7) == 0) {
-		/* disable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 0;
-		}
-		printk("NOTICE: synergy perf counting disabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "frequency", 9) == 0) {
-		/* set the update frequency (timer-interrupts per update) */
-		int freq;
-
-		if (count < 12)
-			return -EINVAL;
-		freq = atoi(cmd + 10);
-		if (freq <= 0 || freq > 100)
-			return -EINVAL;
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_freq = (uint64_t)freq;
-		}
-		printk("NOTICE: synergy perf freq set to %d\n", freq);
-	    }
-	    else
-		return -EINVAL;
-	}
-	
-	return count;
-}
-
-void
-synergy_perf_update(int cpu)
-{
-	nasid_t		nasid;
-	cnodeid_t       cnode = cpuid_to_cnodeid(cpu);
-	struct nodepda_s *npdap;
-	extern struct nodepda_s *nodepda;
-
-	if (nodepda == NULL || (npdap=NODEPDA(cnode)) == NULL || npdap->synergy_perf_enabled == 0 ||
-		npdap->synergy_perf_data == NULL) {
-		/* I/O not initialized, or not enabled, or no events to monitor */
-		return;
-	}
-
-	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
-		/* don't multiplex on every timer interrupt */
-		return;
-	}
-
-	/*
-	 * Read registers for last interval and increment counters.
-	 * Hold the per-node synergy_perf_lock so concurrent readers get
-	 * consistent values.
-	 */
-	spin_lock_irq(&npdap->synergy_perf_lock);
-
-	nasid = cpuid_to_nasid(cpu);
-	npdap->synergy_active_intervals++;
-	npdap->synergy_perf_data->intervals++;
-
-	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
-
-	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
-
-	/* skip to next in circular list */
-	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
-
-	spin_unlock_irq(&npdap->synergy_perf_lock);
-
-	/* set the counter 0 selection modes for both A and B */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
-
-	/* and reset the counter registers to zero */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
-}
-
-void
-synergy_perf_init(void)
-{
-        if ((synergy_perf_proc = create_proc_entry("synergy", 0644, NULL)) != NULL) {
-                synergy_perf_proc->read_proc = synergy_perf_read_proc;
-                synergy_perf_proc->write_proc = synergy_perf_write_proc;
-                printk("markgw: synergy_perf_init()\n");
-        }
-}
-
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
diff -urN linux-2.4.16/arch/ia64/sn/tools/make_textsym lia64-2.4/arch/ia64/sn/tools/make_textsym
--- linux-2.4.16/arch/ia64/sn/tools/make_textsym	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/arch/ia64/sn/tools/make_textsym	Mon Nov 19 23:22:53 2001
@@ -30,107 +30,131 @@
 
 LINUX=${1:-vmlinux}
 TEXTSYM=${2:-${LINUX}.sym}
+TMPSYM=${2:-${LINUX}.sym.tmp}
+trap "/bin/rm -f $TMPSYM" 0
 
 [ -f $VMLINUX ] || help
 
+$OBJDUMP -t $LINUX | sort > $TMPSYM
+SN1=`egrep "dig_setup|Synergy_da_indr" $TMPSYM|wc -l`
+
+# Dataprefix and textprefix correspond to the VGLOBAL_BASE and VPERNODE_BASE.
+# Eventually, these values should be:
+#	dataprefix	ffffffff
+#	textprefix	fffffffe
+# but right now they're still changing, so make them dynamic.
+dataprefix=`awk ' / \.data	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
+textprefix=`awk ' / \.text	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
 
 # pipe everything thru sort
 echo "TEXTSYM V1.0"
 (cat <<END 
-GLOBAL | e000000000500000 | CODE | VEC_VHPT_Translation_0000
-GLOBAL | e000000000500400 | CODE | VEC_ITLB_0400
-GLOBAL | e000000000500800 | CODE | VEC_DTLB_0800
-GLOBAL | e000000000500c00 | CODE | VEC_Alt_ITLB_0c00
-GLOBAL | e000000000501000 | CODE | VEC_Alt_DTLB_1000
-GLOBAL | e000000000501400 | CODE | VEC_Data_nested_TLB_1400
-GLOBAL | e000000000501800 | CODE | VEC_Instruction_Key_Miss_1800
-GLOBAL | e000000000501c00 | CODE | VEC_Data_Key_Miss_1c00
-GLOBAL | e000000000502000 | CODE | VEC_Dirty-bit_2000
-GLOBAL | e000000000502400 | CODE | VEC_Instruction_Access-bit_2400
-GLOBAL | e000000000502800 | CODE | VEC_Data_Access-bit_2800
-GLOBAL | e000000000502c00 | CODE | VEC_Break_instruction_2c00
-GLOBAL | e000000000503000 | CODE | VEC_External_Interrupt_3000
-GLOBAL | e000000000503400 | CODE | VEC_Reserved_3400
-GLOBAL | e000000000503800 | CODE | VEC_Reserved_3800
-GLOBAL | e000000000503c00 | CODE | VEC_Reserved_3c00
-GLOBAL | e000000000504000 | CODE | VEC_Reserved_4000
-GLOBAL | e000000000504400 | CODE | VEC_Reserved_4400
-GLOBAL | e000000000504800 | CODE | VEC_Reserved_4800
-GLOBAL | e000000000504c00 | CODE | VEC_Reserved_4c00
-GLOBAL | e000000000505000 | CODE | VEC_Page_Not_Present_5000
-GLOBAL | e000000000505100 | CODE | VEC_Key_Permission_5100
-GLOBAL | e000000000505200 | CODE | VEC_Instruction_Access_Rights_5200
-GLOBAL | e000000000505300 | CODE | VEC_Data_Access_Rights_5300
-GLOBAL | e000000000505400 | CODE | VEC_General_Exception_5400
-GLOBAL | e000000000505500 | CODE | VEC_Disabled_FP-Register_5500
-GLOBAL | e000000000505600 | CODE | VEC_Nat_Consumption_5600
-GLOBAL | e000000000505700 | CODE | VEC_Speculation_5700
-GLOBAL | e000000000505800 | CODE | VEC_Reserved_5800
-GLOBAL | e000000000505900 | CODE | VEC_Debug_5900
-GLOBAL | e000000000505a00 | CODE | VEC_Unaligned_Reference_5a00
-GLOBAL | e000000000505b00 | CODE | VEC_Unsupported_Data_Reference_5b00
-GLOBAL | e000000000505c00 | CODE | VEC_Floating-Point_Fault_5c00
-GLOBAL | e000000000505d00 | CODE | VEC_Floating_Point_Trap_5d00
-GLOBAL | e000000000505e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
-GLOBAL | e000000000505f00 | CODE | VEC_Taken_Branch_Trap_5f00
-GLOBAL | e000000000506000 | CODE | VEC_Single_Step_Trap_6000
-GLOBAL | e000000000506100 | CODE | VEC_Reserved_6100
-GLOBAL | e000000000506200 | CODE | VEC_Reserved_6200
-GLOBAL | e000000000506300 | CODE | VEC_Reserved_6300
-GLOBAL | e000000000506400 | CODE | VEC_Reserved_6400
-GLOBAL | e000000000506500 | CODE | VEC_Reserved_6500
-GLOBAL | e000000000506600 | CODE | VEC_Reserved_6600
-GLOBAL | e000000000506700 | CODE | VEC_Reserved_6700
-GLOBAL | e000000000506800 | CODE | VEC_Reserved_6800
-GLOBAL | e000000000506900 | CODE | VEC_IA-32_Exeception_6900
-GLOBAL | e000000000506a00 | CODE | VEC_IA-32_Intercept_6a00
-GLOBAL | e000000000506b00 | CODE | VEC_IA-32_Interrupt_6b00
-GLOBAL | e000000000506c00 | CODE | VEC_Reserved_6c00
-GLOBAL | e000000000506d00 | CODE | VEC_Reserved_6d00
-GLOBAL | e000000000506e00 | CODE | VEC_Reserved_6e00
-GLOBAL | e000000000506f00 | CODE | VEC_Reserved_6f00
-GLOBAL | e000000000507000 | CODE | VEC_Reserved_7000
-GLOBAL | e000000000507100 | CODE | VEC_Reserved_7100
-GLOBAL | e000000000507200 | CODE | VEC_Reserved_7200
-GLOBAL | e000000000507300 | CODE | VEC_Reserved_7300
-GLOBAL | e000000000507400 | CODE | VEC_Reserved_7400
-GLOBAL | e000000000507500 | CODE | VEC_Reserved_7500
-GLOBAL | e000000000507600 | CODE | VEC_Reserved_7600
-GLOBAL | e000000000507700 | CODE | VEC_Reserved_7700
-GLOBAL | e000000000507800 | CODE | VEC_Reserved_7800
-GLOBAL | e000000000507900 | CODE | VEC_Reserved_7900
-GLOBAL | e000000000507a00 | CODE | VEC_Reserved_7a00
-GLOBAL | e000000000507b00 | CODE | VEC_Reserved_7b00
-GLOBAL | e000000000507c00 | CODE | VEC_Reserved_7c00
-GLOBAL | e000000000507d00 | CODE | VEC_Reserved_7d00
-GLOBAL | e000000000507e00 | CODE | VEC_Reserved_7e00
-GLOBAL | e000000000507f00 | CODE | VEC_Reserved_7f00
+GLOBAL | ${textprefix}00400000 | CODE | VEC_VHPT_Translation_0000
+GLOBAL | ${textprefix}00400400 | CODE | VEC_ITLB_0400
+GLOBAL | ${textprefix}00400800 | CODE | VEC_DTLB_0800
+GLOBAL | ${textprefix}00400c00 | CODE | VEC_Alt_ITLB_0c00
+GLOBAL | ${textprefix}00401000 | CODE | VEC_Alt_DTLB_1000
+GLOBAL | ${textprefix}00401400 | CODE | VEC_Data_nested_TLB_1400
+GLOBAL | ${textprefix}00401800 | CODE | VEC_Instruction_Key_Miss_1800
+GLOBAL | ${textprefix}00401c00 | CODE | VEC_Data_Key_Miss_1c00
+GLOBAL | ${textprefix}00402000 | CODE | VEC_Dirty-bit_2000
+GLOBAL | ${textprefix}00402400 | CODE | VEC_Instruction_Access-bit_2400
+GLOBAL | ${textprefix}00402800 | CODE | VEC_Data_Access-bit_2800
+GLOBAL | ${textprefix}00402c00 | CODE | VEC_Break_instruction_2c00
+GLOBAL | ${textprefix}00403000 | CODE | VEC_External_Interrupt_3000
+GLOBAL | ${textprefix}00403400 | CODE | VEC_Reserved_3400
+GLOBAL | ${textprefix}00403800 | CODE | VEC_Reserved_3800
+GLOBAL | ${textprefix}00403c00 | CODE | VEC_Reserved_3c00
+GLOBAL | ${textprefix}00404000 | CODE | VEC_Reserved_4000
+GLOBAL | ${textprefix}00404400 | CODE | VEC_Reserved_4400
+GLOBAL | ${textprefix}00404800 | CODE | VEC_Reserved_4800
+GLOBAL | ${textprefix}00404c00 | CODE | VEC_Reserved_4c00
+GLOBAL | ${textprefix}00405000 | CODE | VEC_Page_Not_Present_5000
+GLOBAL | ${textprefix}00405100 | CODE | VEC_Key_Permission_5100
+GLOBAL | ${textprefix}00405200 | CODE | VEC_Instruction_Access_Rights_5200
+GLOBAL | ${textprefix}00405300 | CODE | VEC_Data_Access_Rights_5300
+GLOBAL | ${textprefix}00405400 | CODE | VEC_General_Exception_5400
+GLOBAL | ${textprefix}00405500 | CODE | VEC_Disabled_FP-Register_5500
+GLOBAL | ${textprefix}00405600 | CODE | VEC_Nat_Consumption_5600
+GLOBAL | ${textprefix}00405700 | CODE | VEC_Speculation_5700
+GLOBAL | ${textprefix}00405800 | CODE | VEC_Reserved_5800
+GLOBAL | ${textprefix}00405900 | CODE | VEC_Debug_5900
+GLOBAL | ${textprefix}00405a00 | CODE | VEC_Unaligned_Reference_5a00
+GLOBAL | ${textprefix}00405b00 | CODE | VEC_Unsupported_Data_Reference_5b00
+GLOBAL | ${textprefix}00405c00 | CODE | VEC_Floating-Point_Fault_5c00
+GLOBAL | ${textprefix}00405d00 | CODE | VEC_Floating_Point_Trap_5d00
+GLOBAL | ${textprefix}00405e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
+GLOBAL | ${textprefix}00405f00 | CODE | VEC_Taken_Branch_Trap_5f00
+GLOBAL | ${textprefix}00406000 | CODE | VEC_Single_Step_Trap_6000
+GLOBAL | ${textprefix}00406100 | CODE | VEC_Reserved_6100
+GLOBAL | ${textprefix}00406200 | CODE | VEC_Reserved_6200
+GLOBAL | ${textprefix}00406300 | CODE | VEC_Reserved_6300
+GLOBAL | ${textprefix}00406400 | CODE | VEC_Reserved_6400
+GLOBAL | ${textprefix}00406500 | CODE | VEC_Reserved_6500
+GLOBAL | ${textprefix}00406600 | CODE | VEC_Reserved_6600
+GLOBAL | ${textprefix}00406700 | CODE | VEC_Reserved_6700
+GLOBAL | ${textprefix}00406800 | CODE | VEC_Reserved_6800
+GLOBAL | ${textprefix}00406900 | CODE | VEC_IA-32_Exeception_6900
+GLOBAL | ${textprefix}00406a00 | CODE | VEC_IA-32_Intercept_6a00
+GLOBAL | ${textprefix}00406b00 | CODE | VEC_IA-32_Interrupt_6b00
+GLOBAL | ${textprefix}00406c00 | CODE | VEC_Reserved_6c00
+GLOBAL | ${textprefix}00406d00 | CODE | VEC_Reserved_6d00
+GLOBAL | ${textprefix}00406e00 | CODE | VEC_Reserved_6e00
+GLOBAL | ${textprefix}00406f00 | CODE | VEC_Reserved_6f00
+GLOBAL | ${textprefix}00407000 | CODE | VEC_Reserved_7000
+GLOBAL | ${textprefix}00407100 | CODE | VEC_Reserved_7100
+GLOBAL | ${textprefix}00407200 | CODE | VEC_Reserved_7200
+GLOBAL | ${textprefix}00407300 | CODE | VEC_Reserved_7300
+GLOBAL | ${textprefix}00407400 | CODE | VEC_Reserved_7400
+GLOBAL | ${textprefix}00407500 | CODE | VEC_Reserved_7500
+GLOBAL | ${textprefix}00407600 | CODE | VEC_Reserved_7600
+GLOBAL | ${textprefix}00407700 | CODE | VEC_Reserved_7700
+GLOBAL | ${textprefix}00407800 | CODE | VEC_Reserved_7800
+GLOBAL | ${textprefix}00407900 | CODE | VEC_Reserved_7900
+GLOBAL | ${textprefix}00407a00 | CODE | VEC_Reserved_7a00
+GLOBAL | ${textprefix}00407b00 | CODE | VEC_Reserved_7b00
+GLOBAL | ${textprefix}00407c00 | CODE | VEC_Reserved_7c00
+GLOBAL | ${textprefix}00407d00 | CODE | VEC_Reserved_7d00
+GLOBAL | ${textprefix}00407e00 | CODE | VEC_Reserved_7e00
+GLOBAL | ${textprefix}00407f00 | CODE | VEC_Reserved_7f00
 END
 
-$OBJDUMP -t $LINUX | sort | awk '
-/empty_zero_page/ {start=1}
-/e0000000/ {
+
+awk '
+/__start_gate_section/ {start=1}
+/^'${dataprefix}\|${textprefix}'/ {
 	if ($4 == ".kdb")
 		next
 	if (start && substr($NF,1,1) != "0") {
 		type = substr($0,26,5)
 		if (type == ".text")
 			printf "GLOBAL | %s | CODE | %s\n", $1, $NF
-		else
-			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, $(NF-1)
+		else {
+			n = 0
+			s = $(NF-1)
+			while (length(s) > 0) {
+				n = n*16 + substr(s,1,1)
+				s = substr(s,2)
+			}
+			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, n
+		}
 	}
 	if($NF == "_end") 
 		exit
 
 }
-' ) | egrep -v " __device| __vendor" | awk '
+' $TMPSYM ) | egrep -v " __device| __vendor" | awk -v sn1="$SN1" '
 /GLOBAL/ {
 	print $0
-	print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	if (sn1 != 0) {
+		/* 32 bits of sn1 physical addrs, */
+		print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	} else {
+		/* 38 bits of sn2 physical addrs, need addr space bits */
+		print substr($0,1,9) "30" substr($0,18,18) "Phy_" substr($0,36)
+	}
 
 } ' | sort -k3
-
-
 
 N=`wc -l $TEXTSYM|awk '{print $1}'`
 echo "Generated TEXTSYM file" >&2
diff -urN linux-2.4.16/arch/parisc/kernel/traps.c lia64-2.4/arch/parisc/kernel/traps.c
--- linux-2.4.16/arch/parisc/kernel/traps.c	Wed Oct 10 16:31:44 2001
+++ lia64-2.4/arch/parisc/kernel/traps.c	Wed Oct 24 11:43:30 2001
@@ -43,7 +43,6 @@
 
 static inline void console_verbose(void)
 {
-	extern int console_loglevel;
 	console_loglevel = 15;
 }
 
diff -urN linux-2.4.16/drivers/acpi/acpiconf.c lia64-2.4/drivers/acpi/acpiconf.c
--- linux-2.4.16/drivers/acpi/acpiconf.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/acpi/acpiconf.c	Mon Oct  8 23:28:50 2001
@@ -0,0 +1,593 @@
+/*
+ *  acpiconf.c - ACPI based kernel configuration
+ *
+ *  Copyright (C) 2000-2001 Intel Corp.
+ *  Copyright (C) 2000-2001 J.I. Lee <Jung-Ik.Lee@intel.com>
+ *
+ *  Revision History:
+ *	 9/15/2000 J.I.
+ *		Major revision:	for new ACPI initialization requirements
+ *	11/15/2000 J.I.
+ *		Major revision:	ACPI 2.0 tables support
+ *	04/23/2001 J.I.
+ *		Rewrote functions to support multiple _PRTs of child P2Ps
+ *		under root pci bus
+ */
+
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <asm/system.h>
+#include <asm/iosapic.h>
+#include <asm/efi.h>
+#include <asm/acpikcfg.h>
+#include "acpi.h"
+#include "osconf.h"
+#include "acpiconf.h"
+
+
+static	int	acpi_cf_initialized __initdata = 0;
+
+acpi_status	__init
+acpi_cf_init (
+	void * rsdp
+	)
+{
+	acpi_status	status;
+
+	acpi_os_bind_osd(ACPI_CF_PHASE_BOOTTIME);
+
+	status = acpi_initialize_subsystem ();
+	if (ACPI_FAILURE(status)) {
+		printk ("Acpi cfg:initialize_subsystem error=0x%x\n", status);
+		return status;
+	}
+	dprintk(("Acpi cfg:initialize_subsystem pass\n"));
+
+	status = acpi_load_tables ();
+	if (ACPI_FAILURE(status)) {
+		printk ("Acpi cfg:load firmware tables error=0x%x\n", status);
+		acpi_terminate();
+		return status;
+	}
+	dprintk(("Acpi cfg:load firmware tables pass\n"));
+
+	status = acpi_enable_subsystem (ACPI_FULL_INITIALIZATION);
+	if (ACPI_FAILURE(status)) {
+		printk ("Acpi cfg:enable_subsystem error=0x%x\n", status);
+		acpi_terminate();
+		return status;
+	}
+	dprintk(("Acpi cfg:enable_subsystem pass\n"));
+
+	acpi_cf_initialized++;
+
+	return AE_OK;
+}
+
+
+acpi_status	__init
+acpi_cf_terminate ( void )
+{
+	acpi_status	status;
+
+	if (! ACPI_CF_INITIALIZED()) {
+		acpi_os_bind_osd(ACPI_CF_PHASE_RUNTIME);
+		return AE_ERROR;
+	}
+
+	status = acpi_disable ();
+	if (ACPI_FAILURE(status)) {
+		printk ("Acpi cfg:disable fail=0x%x\n", status);
+		/* fall thru...*/
+	}
+
+	status = acpi_terminate ();
+	if (ACPI_FAILURE(status)) {
+		printk ("Acpi cfg:acpi terminate error=0x%x\n", status);
+		/* fall thru...*/
+	}
+
+	acpi_cf_cleanup();
+	acpi_os_bind_osd(ACPI_CF_PHASE_RUNTIME);
+
+	acpi_cf_initialized--;
+
+	return status;
+}
+
+
+acpi_status	__init
+acpi_cf_get_pci_vectors (
+	struct pci_vector_struct	**vectors,
+	int				*num_pci_vectors
+	)
+{
+	acpi_status	status;
+	void		*prts;
+
+	if (! ACPI_CF_INITIALIZED()) {
+		status = acpi_cf_init((void *)efi.acpi);
+		if (ACPI_FAILURE (status))
+			return status;
+	}
+
+	*vectors = NULL;
+	*num_pci_vectors = 0;
+
+	status = acpi_cf_get_prt (&prts);
+	if (ACPI_FAILURE (status)) {
+		printk("Acpi cfg: get prt fail\n");
+		return status;
+	}
+
+	status = acpi_cf_convert_prt_to_vectors (prts, vectors, num_pci_vectors);
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+	if (ACPI_SUCCESS(status)) {
+		acpi_cf_print_pci_vectors (*vectors, *num_pci_vectors);
+	}
+#endif
+	printk("Acpi cfg: get PCI interrupt vectors %s\n",
+		(ACPI_SUCCESS(status))?"pass":"fail");
+
+	return status;
+}
+
+
+static	pci_routing_table	*pci_routing_tables[PCI_MAX_BUS] __initdata = {NULL};
+
+
+typedef struct _acpi_rpb {
+	NATIVE_UINT	rpb_busnum;
+	NATIVE_UINT	lastbusnum;
+	acpi_handle	rpb_handle;
+} acpi_rpb_t;
+
+
+static acpi_status	__init
+acpi_cf_evaluate_method (
+	acpi_handle	handle,
+	UINT8		*method_name,
+	NATIVE_UINT	*nuint
+	)
+{
+	UINT32			tnuint = 0;
+	acpi_status		status;
+
+	acpi_buffer		ret_buf;
+	acpi_object		*ext_obj;
+	UINT8			buf[PATHNAME_MAX];
+
+
+	ret_buf.length  = PATHNAME_MAX;
+	ret_buf.pointer = (void *) buf;
+
+	status = acpi_evaluate_object(handle, method_name, NULL, &ret_buf);
+	if (ACPI_FAILURE(status)) {
+		if (status == AE_NOT_FOUND) {
+			printk("Acpi cfg: no %s found\n", method_name);
+		} else {
+			printk("Acpi cfg: %s fail=0x%x\n", method_name, status);
+		}
+	} else {
+		ext_obj = (acpi_object *) ret_buf.pointer;
+
+		switch (ext_obj->type) {
+		case ACPI_TYPE_INTEGER:
+			tnuint = (NATIVE_UINT) ext_obj->integer.value;
+			break;
+		default:
+			printk("Acpi cfg: %s obj type incorrect\n", method_name);
+			status = AE_TYPE;
+			break;
+		}
+	}
+
+	*nuint = tnuint;
+	return (status);
+}
+
+
+static acpi_status	__init
+acpi_cf_evaluate_PRT (
+	acpi_handle		handle,
+	pci_routing_table	**prt
+	)
+{
+	acpi_buffer		acpi_buffer;
+	acpi_status		status;
+
+	acpi_buffer.length  = 0;
+	acpi_buffer.pointer = NULL;
+
+	status = acpi_get_irq_routing_table (handle, &acpi_buffer);
+
+	switch (status) {
+	case AE_BUFFER_OVERFLOW:
+		dprintk(("Acpi cfg: _PRT found. need %d bytes\n",
+			acpi_buffer.length));
+		break;		/* found */
+	default:
+		printk("Acpi cfg: _PRT fail=0x%x\n", status);
+	case AE_NOT_FOUND:
+		return status;
+	}
+
+	*prt = (pci_routing_table *) acpi_os_callocate (acpi_buffer.length);
+	if (!*prt) {
+		printk("Acpi cfg: callocate %d bytes for _PRT fail\n",
+			acpi_buffer.length);
+		return AE_NO_MEMORY;
+	}
+	acpi_buffer.pointer = (void *) *prt;
+
+	status = acpi_get_irq_routing_table (handle, &acpi_buffer);
+	if (ACPI_FAILURE(status)) {
+		printk("Acpi cfg: _PRT fail=0x%x.\n", status);
+		acpi_os_free(prt);
+	}
+
+	return status;
+}
+
+static acpi_status	__init
+acpi_cf_get_root_pci_callback (
+	acpi_handle		handle,
+	UINT32			Level,
+	void			*context,
+	void			**retval
+	)
+{
+	NATIVE_UINT		busnum = 0;
+	acpi_status		status;
+	acpi_rpb_t		rpb;
+	pci_routing_table	*prt;
+
+	UINT8			path_name[PATHNAME_MAX];
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+	acpi_buffer		ret_buf;
+
+	ret_buf.length  = PATHNAME_MAX;
+	ret_buf.pointer = (void *) path_name;
+
+	status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf);
+#else
+	memset(path_name, 0, sizeof (path_name));
+#endif
+
+	/*
+	 * get bus number of this pci root bridge
+	 */
+	status = acpi_cf_evaluate_method(handle, METHOD_NAME__BBN, &busnum);
+	if (ACPI_FAILURE(status)) {
+		printk("Acpi cfg:%s evaluate _BBN fail=0x%x\n",
+			path_name, status);
+		return (status);
+	}
+	printk("Acpi cfg:%s ROOT PCI bus %ld\n", path_name, busnum);
+
+	/*
+	 * evaluate root pci bridge's _CRS for Bus number range for child P2P
+	 * (bus min/max/len) - not yet.
+	 */
+
+	/*
+	 * get immediate _PRT of this root pci bridge if any
+	 */
+	status = acpi_cf_evaluate_PRT (handle, &prt);
+	switch(status) {
+	case AE_NOT_FOUND:
+		break;
+	default:
+		if (ACPI_FAILURE(status)) {
+			printk("Acpi cfg:%s _PRT fail=0x%x\n",
+				path_name, status);
+			return status;
+		}
+		dprintk(("Acpi cfg:%s bus %ld got _PRT\n", path_name, busnum));
+		acpi_cf_add_to_pci_routing_tables (busnum, prt);
+		break;
+	}
+
+
+	/*
+	 * walk down this root pci bridge to get _PRTs if any
+	 */
+	rpb.rpb_busnum = rpb.lastbusnum = busnum;
+	rpb.rpb_handle = handle;
+	status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
+					handle,
+					ACPI_UINT32_MAX,
+					acpi_cf_get_prt_callback,
+					&rpb,
+					NULL );
+	if (ACPI_FAILURE(status))
+		printk("Acpi cfg:%s walk namespace for _PRT error=0x%x\n",
+			path_name, status);
+
+	return (status);
+}
+
+
+/*
+ * handle _PRTs of immediate P2Ps of root pci. 
+ */
+static acpi_status	__init
+acpi_cf_associate_prt_to_bus (
+	acpi_handle		handle,
+	acpi_rpb_t		*rpb,
+	NATIVE_UINT		*retbusnum,
+	NATIVE_UINT		depth
+	)
+{
+	acpi_status		status;
+	UINT32			segbus;
+	NATIVE_UINT		devfn;
+	UINT8			bn;
+
+	UINT8			path_name[PATHNAME_MAX];
+	acpi_pci_id		pci_id;
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+	acpi_buffer		ret_buf;
+
+	ret_buf.length  = PATHNAME_MAX;
+	ret_buf.pointer = (void *) path_name;
+
+	status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf);
+#else
+	memset(path_name, 0, sizeof (path_name));
+#endif
+
+	/*
+	 * get devfn from _ADR
+	 */
+	status = acpi_cf_evaluate_method(handle, METHOD_NAME__ADR, &devfn);
+	if (ACPI_FAILURE(status)) {
+		*retbusnum = rpb->rpb_busnum + 1;
+		printk("Acpi cfg:%s _ADR fail=0x%x. Set busnum to %ld\n",
+			path_name, status, *retbusnum);
+		return AE_OK;
+	}
+	dprintk(("Acpi cfg:%s _ADR =0x%x\n", path_name, (UINT32)devfn));
+
+
+	/*
+	 * access pci config space for bus number
+	 *	segbus = from rpb, devfn = from _ADR
+	 */
+	pci_id.segment = 0;
+	pci_id.bus = (u16)(rpb->rpb_busnum & 0xffffffff);
+	pci_id.device = (u16)((devfn >> 16) & 0xffff);
+	pci_id.function = (u16)(devfn & 0xffff);
+
+	status = acpi_os_read_pci_configuration(&pci_id, PCI_PRIMARY_BUS,
+						&bn, 8);
+	if (ACPI_FAILURE(status)) {
+		*retbusnum = rpb->rpb_busnum + 1;
+		printk("Acpi cfg:%s pci read fail=0x%x. b:df:a=%x:%x:%x\n",
+			path_name, status, segbus, (UINT32)devfn,
+			PCI_PRIMARY_BUS);
+		printk("Acpi cfg:%s Set busnum to %ld\n",
+			path_name, *retbusnum);
+		return AE_OK;
+	}
+	dprintk(("Acpi cfg:%s pribus %d\n", path_name, bn));
+
+
+	status = acpi_os_read_pci_configuration(&pci_id, PCI_SECONDARY_BUS,
+						&bn, 8);
+	if (ACPI_FAILURE(status)) {
+		*retbusnum = rpb->rpb_busnum + 1;
+		printk("Acpi cfg:%s pci read fail=0x%x. b:df:a=%x:%x:%x\n",
+			path_name, status, segbus, (UINT32)devfn,
+			PCI_SECONDARY_BUS);
+		printk("Acpi cfg:%s Set busnum to %ld\n",
+			path_name, *retbusnum);
+		return AE_OK;
+	}
+	dprintk(("Acpi cfg:%s busnum %d\n", path_name, bn));
+
+	*retbusnum = (NATIVE_UINT)bn;
+	return AE_OK;
+}
+
+
+static acpi_status	__init
+acpi_cf_get_prt (
+	void		**prts
+	)
+{
+	acpi_status	status;
+
+	status = acpi_get_devices ( PCI_ROOT_HID_STRING,
+				acpi_cf_get_root_pci_callback,
+				NULL,
+				NULL );
+
+	if (ACPI_FAILURE(status)) {
+		printk("Acpi cfg:get_device PCI ROOT HID error=0x%x\n", status);
+	}
+
+	*prts = (void *)pci_routing_tables;
+
+	return status;
+}
+
+static acpi_status	__init
+acpi_cf_get_prt_callback (
+	acpi_handle		handle,
+	UINT32			Level,
+	void			*context,
+	void			**retval
+	)
+{
+	pci_routing_table	*prt;
+	NATIVE_UINT		busnum = 0;
+	NATIVE_UINT		temp = 0x0F;
+	acpi_status		status;
+
+	UINT8			path_name[PATHNAME_MAX];
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+	acpi_buffer		ret_buf;
+
+	ret_buf.length  = PATHNAME_MAX;
+	ret_buf.pointer = (void *) path_name;
+
+	status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &ret_buf);
+#else
+	memset(path_name, 0, sizeof (path_name));
+#endif
+
+	status = acpi_cf_evaluate_PRT (handle, &prt);
+	switch(status) {
+	case AE_NOT_FOUND:
+		return AE_OK;
+	default:
+		if (ACPI_FAILURE(status)) {
+			printk("Acpi cfg:%s _PRT fail=0x%x\n",
+				path_name, status);
+			return status;
+		}
+	}
+
+	/*
+	 * evaluate _STA in case this device does not exist
+	 */
+	status = acpi_cf_evaluate_method(handle, METHOD_NAME__STA, &temp);
+	switch(status) {
+	case AE_NOT_FOUND:
+		break;
+	default:
+		if (ACPI_FAILURE(status)) {
+			printk("Acpi cfg:%s _STA fail=0x%x\n",
+				path_name, status);
+			return status;
+		}
+		if (!(temp & ACPI_STA_DEVICE_PRESENT)) {
+			dprintk(("Acpi cfg:%s not exist. _PRT discarded\n",
+				path_name));
+			acpi_os_free(prt);
+			return AE_OK;
+		}
+		break;
+	}
+
+	/*
+	 * associate a bus number to this _PRT since 
+	 * this _PRT is not on root pci bridge 
+	 */
+	acpi_cf_associate_prt_to_bus(handle, context, &busnum, 0);
+
+	printk("Acpi cfg:%s busnum %ld got _PRT\n", path_name, busnum);
+	acpi_cf_add_to_pci_routing_tables (busnum, prt);
+
+	return AE_OK;
+}
+
+
+static void	__init
+acpi_cf_add_to_pci_routing_tables (
+	NATIVE_UINT		busnum,
+	pci_routing_table	*prt
+	)
+{
+	if ( busnum >= PCI_MAX_BUS ) {
+		printk("Acpi cfg:invalid pci bus number %ld\n", busnum);
+		acpi_os_free(prt);
+		return;
+	}
+
+	if (pci_routing_tables[busnum]) {
+		printk("Acpi cfg:duplicate PRT for pci bus %ld. overiding...\n", busnum);
+		acpi_os_free(pci_routing_tables[busnum]);
+	}
+
+	pci_routing_tables[busnum] = prt;
+}
+
+
+#define	DUMPVECTOR(pv)	printk("PCI bus=0x%x id=0x%x pin=0x%x irq=0x%x\n", pv->bus, pv->pci_id, pv->pin, pv->irq);
+
+static acpi_status	__init
+acpi_cf_convert_prt_to_vectors (
+	void				*prts,
+	struct pci_vector_struct	**vectors,
+	int				*num_pci_vectors
+	)
+{
+	struct pci_vector_struct	*pvec;
+	pci_routing_table		**pprts, *prt, *prtf;
+	int				nvec = 0;
+	int				i;
+
+
+	pprts = (pci_routing_table **)prts;
+
+	for ( i = 0; i < PCI_MAX_BUS; i++) {
+		prt = *pprts++;
+		if (prt) {
+			for ( ; prt->length > 0; nvec++) {
+				prt = (pci_routing_table *) ((NATIVE_UINT)prt + (NATIVE_UINT)prt->length);
+			}
+		}
+	}
+
+	*num_pci_vectors = nvec;
+	*vectors = acpi_os_callocate (sizeof(struct pci_vector_struct) * nvec);
+	if (!*vectors) {
+		printk("Acpi cfg: callocate for pci_vector error\n");
+		return AE_NO_MEMORY;
+	}
+
+	pvec = *vectors;
+	pprts = (pci_routing_table **)prts;
+
+	for ( i = 0; i < PCI_MAX_BUS; i++) {
+		prt = prtf = *pprts++;
+		if (prt) {
+			for ( ; prt->length > 0; pvec++) {
+				pvec->bus	= (UINT16)i;
+				pvec->pci_id	= prt->address;
+				pvec->pin	= (UINT8)prt->pin;
+				pvec->irq	= (UINT8)prt->source_index;
+
+				prt = (pci_routing_table *) ((NATIVE_UINT)prt + (NATIVE_UINT)prt->length);
+			}
+			acpi_os_free((void *)prtf);
+		}
+	}
+
+	return AE_OK;
+}
+
+
+void	__init
+acpi_cf_cleanup ( void )
+{
+	/* nothing to free, pci_vectors are used by the kernel */
+}
+
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+void	__init
+acpi_cf_print_pci_vectors (
+	struct pci_vector_struct	*vectors,
+	int				num_pci_vectors
+	)
+{
+	struct pci_vector_struct	*pvec;
+	int				i;
+
+	printk("number of PCI interrupt vectors = %d\n", num_pci_vectors);
+
+	pvec = vectors;
+	for (i = 0; i < num_pci_vectors; i++) {
+		DUMPVECTOR(pvec);
+		pvec++;
+	}
+}
+#endif
diff -urN linux-2.4.16/drivers/acpi/acpiconf.h lia64-2.4/drivers/acpi/acpiconf.h
--- linux-2.4.16/drivers/acpi/acpiconf.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/acpi/acpiconf.h	Mon Nov 26 18:09:00 2001
@@ -0,0 +1,63 @@
+/*
+ *  acpiconf.h - ACPI based kernel configuration 
+ *
+ *  Copyright (C) 2000 Intel Corp.
+ *  Copyright (C) 2000 J.I. Lee <Jung-Ik.Lee@intel.com>
+ */
+
+#include <linux/init.h>
+
+#define	PCI_MAX_BUS		0x100
+#define	ACPI_STA_DEVICE_PRESENT	0x01
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_DEBUG
+#define	ACPI_CF_INITIALIZED()	(acpi_cf_initialized > 0)
+#undef	dprintk
+#define	dprintk(a)	printk a
+#else
+#define	ACPI_CF_INITIALIZED()	1
+#undef	dprintk
+#define	dprintk(a)
+#endif
+
+
+extern
+void	__init
+acpi_os_bind_osd(int acpi_phase);
+
+
+static
+acpi_status	__init
+acpi_cf_get_prt (void **prts);
+
+
+static
+acpi_status	__init
+acpi_cf_get_prt_callback (
+	acpi_handle		handle,
+	UINT32			level,
+	void			*context,
+	void			**retval
+	);
+
+
+static
+void	__init
+acpi_cf_add_to_pci_routing_tables (
+	NATIVE_UINT		busnum,
+	pci_routing_table	*prt
+	);
+
+
+static
+acpi_status	__init
+acpi_cf_convert_prt_to_vectors (
+	void				*prts,
+	struct pci_vector_struct	**vectors,
+	int				*num_pci_vectors
+	);
+
+
+void	__init
+acpi_cf_cleanup ( void );
+
diff -urN linux-2.4.16/drivers/acpi/driver.c lia64-2.4/drivers/acpi/driver.c
--- linux-2.4.16/drivers/acpi/driver.c	Mon Nov  5 18:28:43 2001
+++ lia64-2.4/drivers/acpi/driver.c	Mon Nov 19 23:22:53 2001
@@ -180,7 +180,9 @@
 
 	printk(KERN_INFO "ACPI: Subsystem enabled\n");
 
+#ifdef CONFIG_PM
 	pm_active = 1;
+#endif
 
 	return 0;
 }
@@ -193,7 +195,9 @@
 {
 	acpi_terminate();
 
+#ifdef CONFIG_PM
 	pm_active = 0;
+#endif
 
 	printk(KERN_ERR "ACPI: Subsystem disabled\n");
 }
diff -urN linux-2.4.16/drivers/acpi/hardware/hwacpi.c lia64-2.4/drivers/acpi/hardware/hwacpi.c
--- linux-2.4.16/drivers/acpi/hardware/hwacpi.c	Mon Nov  5 18:28:43 2001
+++ lia64-2.4/drivers/acpi/hardware/hwacpi.c	Mon Nov  5 18:42:03 2001
@@ -196,6 +196,7 @@
 {
 
 	acpi_status             status = AE_NO_HARDWARE_RESPONSE;
+	u32			retries = 20;
 
 
 	FUNCTION_TRACE ("Hw_set_mode");
@@ -220,11 +221,14 @@
 
 	/* Give the platform some time to react */
 
-	acpi_os_stall (20000);
+	while (retries-- > 0) {
+		acpi_os_stall (20000);
 
-	if (acpi_hw_get_mode () == mode) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Mode %X successfully enabled\n", mode));
-		status = AE_OK;
+		if (acpi_hw_get_mode () == mode) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Mode %X successfully enabled\n", mode));
+			status = AE_OK;
+			break;
+		}
 	}
 
 	return_ACPI_STATUS (status);
diff -urN linux-2.4.16/drivers/acpi/include/actypes.h lia64-2.4/drivers/acpi/include/actypes.h
--- linux-2.4.16/drivers/acpi/include/actypes.h	Mon Nov  5 18:28:43 2001
+++ lia64-2.4/drivers/acpi/include/actypes.h	Mon Nov  5 18:34:13 2001
@@ -60,6 +60,7 @@
 typedef int                             INT32;
 typedef unsigned int                    UINT32;
 typedef COMPILER_DEPENDENT_UINT64       UINT64;
+typedef	long				INT64;
 
 typedef UINT64                          NATIVE_UINT;
 typedef INT64                           NATIVE_INT;
diff -urN linux-2.4.16/drivers/acpi/include/acutils.h lia64-2.4/drivers/acpi/include/acutils.h
--- linux-2.4.16/drivers/acpi/include/acutils.h	Mon Nov  5 18:28:43 2001
+++ lia64-2.4/drivers/acpi/include/acutils.h	Mon Nov  5 18:48:04 2001
@@ -383,6 +383,7 @@
 /* Method name strings */
 
 #define METHOD_NAME__HID        "_HID"
+#define METHOD_NAME__CID        "_CID"
 #define METHOD_NAME__UID        "_UID"
 #define METHOD_NAME__ADR        "_ADR"
 #define METHOD_NAME__STA        "_STA"
@@ -397,6 +398,11 @@
 	NATIVE_CHAR             *object_name,
 	acpi_namespace_node     *device_node,
 	acpi_integer            *address);
+
+acpi_status
+acpi_ut_execute_CID (
+	acpi_namespace_node     *device_node,
+	acpi_device_id          *cid);
 
 acpi_status
 acpi_ut_execute_HID (
diff -urN linux-2.4.16/drivers/acpi/include/platform/acgcc.h lia64-2.4/drivers/acpi/include/platform/acgcc.h
--- linux-2.4.16/drivers/acpi/include/platform/acgcc.h	Mon Nov  5 18:28:44 2001
+++ lia64-2.4/drivers/acpi/include/platform/acgcc.h	Mon Nov  5 18:34:13 2001
@@ -42,11 +42,32 @@
 
 /*! [Begin] no source code translation */
 
+#include <linux/interrupt.h>
+
+#include <asm/processor.h>
 #include <asm/pal.h>
 
 #define halt()              ia64_pal_halt_light()           /* PAL_HALT[_LIGHT] */
 #define safe_halt()         ia64_pal_halt(1)                /* PAL_HALT */
 
+static inline void
+wbinvd (void)
+{
+	unsigned long flags, vector, position = 0;
+	long status;
+
+	do {
+		ia64_clear_ic(flags);
+		status = ia64_pal_cache_flush(0x3, (PAL_CACHE_FLUSH_INVALIDATE
+						    | PAL_CACHE_FLUSH_CHK_INTRS),
+					      &position, &vector);
+		local_irq_restore(flags);
+		if (status == 1) {
+			ia64_eoi();
+			hw_resend_irq(NULL, vector);
+		}
+	} while (status == 1);
+}
 
 #define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \
 	do { \
diff -urN linux-2.4.16/drivers/acpi/namespace/nsxfobj.c lia64-2.4/drivers/acpi/namespace/nsxfobj.c
--- linux-2.4.16/drivers/acpi/namespace/nsxfobj.c	Mon Nov  5 18:28:44 2001
+++ lia64-2.4/drivers/acpi/namespace/nsxfobj.c	Mon Nov  5 18:41:25 2001
@@ -548,6 +548,7 @@
 	acpi_namespace_node     *node;
 	u32                     flags;
 	acpi_device_id          device_id;
+	acpi_device_id          compatible_id;
 	acpi_get_devices_info   *info;
 
 
@@ -588,7 +589,17 @@
 		}
 
 		if (STRNCMP (device_id.buffer, info->hid, sizeof (device_id.buffer)) != 0) {
-			return (AE_OK);
+			status = acpi_ut_execute_CID (node, &compatible_id);
+			if (status == AE_NOT_FOUND) {
+				return (AE_OK);
+			}
+			else if (ACPI_FAILURE (status)) {
+				return (AE_CTRL_DEPTH);
+			}
+
+			if (STRNCMP (compatible_id.buffer, info->hid, sizeof (compatible_id.buffer)) != 0) {
+				return (AE_OK);
+			}
 		}
 	}
 
diff -urN linux-2.4.16/drivers/acpi/os.c lia64-2.4/drivers/acpi/os.c
--- linux-2.4.16/drivers/acpi/os.c	Mon Nov 26 11:18:30 2001
+++ lia64-2.4/drivers/acpi/os.c	Mon Nov 26 11:20:28 2001
@@ -31,6 +31,8 @@
  * - Fixed improper kernel_thread parameters 
  */
 
+#include <linux/config.h>
+
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/mm.h>
@@ -47,7 +49,8 @@
 
 #ifdef _IA64
 #include <asm/hw_irq.h>
-#endif 
+#include <asm/delay.h>
+#endif
 
 #define _COMPONENT	ACPI_OS_SERVICES
 	MODULE_NAME	("os")
@@ -60,6 +63,33 @@
 
 
 /*****************************************************************************
+ *			       Function Binding
+ *****************************************************************************/
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG
+#include "osconf.h"
+
+struct acpi_osd acpi_osd_rt = {
+	/* these are runtime osd entries that differ from boottime entries */
+	acpi_os_allocate_rt,
+	acpi_os_callocate_rt,
+	acpi_os_free_rt,
+	acpi_os_queue_for_execution_rt,
+	acpi_os_read_pci_configuration_rt,
+	acpi_os_write_pci_configuration_rt,
+	acpi_os_stall_rt
+};
+#else
+#define	acpi_os_allocate_rt		acpi_os_allocate
+#define	acpi_os_callocate_rt		acpi_os_callocate
+#define	acpi_os_free_rt			acpi_os_free
+#define acpi_os_queue_for_execution_rt	acpi_os_queue_for_execution
+#define acpi_os_read_pci_configuration_rt	acpi_os_read_pci_configuration
+#define acpi_os_write_pci_configuration_rt	acpi_os_write_pci_configuration
+#define acpi_os_stall_rt acpi_os_stall
+#endif
+
+/*****************************************************************************
  *			       Debugger Stuff
  *****************************************************************************/
 
@@ -136,13 +166,13 @@
 }
 
 void *
-acpi_os_allocate(u32 size)
+acpi_os_allocate_rt(u32 size)
 {
 	return kmalloc(size, GFP_KERNEL);
 }
 
 void *
-acpi_os_callocate(u32 size)
+acpi_os_callocate_rt(u32 size)
 {
 	void *ptr = acpi_os_allocate(size);
 	if (ptr)
@@ -152,7 +182,7 @@
 }
 
 void
-acpi_os_free(void *ptr)
+acpi_os_free_rt(void *ptr)
 {
 	kfree(ptr);
 }
@@ -219,12 +249,105 @@
 	(*acpi_irq_handler)(acpi_irq_context);
 }
 
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG
+struct irqaction	acpiirqaction;
+/*
+ * codes from request_irq and free_irq.
+ */
 acpi_status
 acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context)
 {
-#ifdef _IA64
+	struct irqaction	*act;
+	int	retval;
+
+	if (irq >= NR_IRQS) {
+		printk("ACPI: install SCI handler fail: invalid irq%d\n", irq);
+		return AE_ERROR;
+	}
+
+	if (!handler) {
+		printk("ACPI: install SCI handler fail: invalid handler\n");
+		return AE_ERROR;
+	}
+
+	act = & acpiirqaction;
+
 	irq = isa_irq_to_vector(irq);
-#endif /*_IA64*/
+	acpi_irq_irq = irq;
+	acpi_irq_handler = handler;
+	acpi_irq_context = context;
+
+	act->handler = acpi_irq;
+	act->flags = SA_INTERRUPT | SA_SHIRQ;
+	act->mask = 0;
+	act->name = "acpi";
+	act->next = NULL;
+	act->dev_id = acpi_irq;
+
+	retval = setup_irq(irq, act);
+	if (retval) {
+		printk("ACPI: install SCI handler fail: setup_irq\n");
+		acpi_irq_handler = NULL;
+		return AE_ERROR;
+	}
+	printk("ACPI: install SCI %d handler pass\n", irq);
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_remove_interrupt_handler(u32 irq, OSD_HANDLER handler)
+{
+	irq_desc_t *desc;
+	struct irqaction **p;
+	unsigned long flags;
+
+	if (!acpi_irq_handler)
+		return AE_OK;
+
+	irq = isa_irq_to_vector(irq);
+	if (irq != acpi_irq_irq) return AE_ERROR;
+
+	acpi_irq_handler = NULL;
+
+	desc = irq_desc(irq);
+	spin_lock_irqsave(&desc->lock,flags);
+	p = &desc->action;
+	for (;;) {
+		struct irqaction * action = *p;
+		if (action) {
+			struct irqaction **pp = p;
+			p = &action->next;
+			if (action->dev_id != acpi_irq)
+				continue;
+
+			/* Found it - now remove it from the list of entries */
+			*pp = action->next;
+			if (!desc->action) {
+				desc->status |= IRQ_DISABLED;
+				desc->handler->shutdown(irq);
+			}
+			spin_unlock_irqrestore(&desc->lock,flags);
+
+#ifdef CONFIG_SMP
+			/* Wait to make sure it's not being used on another CPU */
+			while (desc->status & IRQ_INPROGRESS)
+				barrier();
+#endif
+			return AE_OK;
+		}
+		printk("ACPI: Trying to free free IRQ%d\n",irq);
+		spin_unlock_irqrestore(&desc->lock,flags);
+		return AE_OK;
+	}
+
+	return AE_OK;
+}
+
+#else
+acpi_status
+acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context)
+{
 	acpi_irq_irq = irq;
 	acpi_irq_handler = handler;
 	acpi_irq_context = context;
@@ -253,6 +376,7 @@
 
 	return AE_OK;
 }
+#endif
 
 /*
  * Running in interpreter thread context, safe to sleep
@@ -266,7 +390,7 @@
 }
 
 void
-acpi_os_stall(u32 us)
+acpi_os_stall_rt(u32 us)
 {
 	if (us > 10000) {
 		mdelay(us / 1000);
@@ -361,7 +485,7 @@
 acpi_status
 acpi_os_write_memory(
 	ACPI_PHYSICAL_ADDRESS	phys_addr,
-	u32			value,
+	NATIVE_UINT		value,
 	u32			width)
 {
 	switch (width)
@@ -454,7 +578,7 @@
 #else /*CONFIG_ACPI_PCI*/
 
 acpi_status
-acpi_os_read_pci_configuration (
+acpi_os_read_pci_configuration_rt (
 	acpi_pci_id	*pci_id,
 	u32		reg,
 	void		*value,
@@ -488,10 +612,10 @@
 }
 
 acpi_status
-acpi_os_write_pci_configuration (
+acpi_os_write_pci_configuration_rt (
 	acpi_pci_id	*pci_id,
 	u32		reg,
-	u32		value,
+	NATIVE_UINT	value,
 	u32		width)
 {
 	int devfn = PCI_DEVFN(pci_id->device, pci_id->function);
@@ -606,6 +730,22 @@
 		acpi_os_free(dpc);
 	}
 }
+
+#ifdef CONFIG_ACPI_KERNEL_CONFIG
+/*
+ * Queue for interpreter thread
+ */
+
+acpi_status
+acpi_os_queue_for_execution_rt(
+	u32 priority,
+	OSD_EXECUTION_CALLBACK callback,
+	void *context)
+{
+	(*callback)(context);
+	return AE_OK;
+}
+#endif
 
 acpi_status
 acpi_os_queue_for_execution(
diff -urN linux-2.4.16/drivers/acpi/osconf.c lia64-2.4/drivers/acpi/osconf.c
--- linux-2.4.16/drivers/acpi/osconf.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/acpi/osconf.c	Mon Sep 24 22:00:48 2001
@@ -0,0 +1,286 @@
+/*
+ *  osconf.c - ACPI OS-dependent functions for Kernel Boot/Configuration time
+ *
+ *  Copyright (C) 2000 Intel Corp.
+ *  Copyright (C) 2000 J.I. Lee <Jung-Ik.Lee@intel.com>
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/pci.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/sal.h>
+#include <asm/delay.h>
+
+#include "acpi.h"
+#include "osconf.h"
+
+
+static void * __init acpi_os_allocate_bt(u32 size);
+static void * __init acpi_os_callocate_bt(u32 size);
+static void __init acpi_os_free_bt(void *ptr);
+static void __init acpi_os_stall_bt(u32 us);
+
+static acpi_status __init
+acpi_os_queue_for_execution_bt(
+	u32			priority,
+	OSD_EXECUTION_CALLBACK	callback,
+	void			*context
+	);
+
+static acpi_status __init
+acpi_os_read_pci_configuration_bt( acpi_pci_id *pci_id, u32 reg, void *value, u32 width);
+
+static acpi_status __init
+acpi_os_write_pci_configuration_bt( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width);
+
+
+extern struct acpi_osd acpi_osd_rt;
+static struct acpi_osd acpi_osd_bt __initdata = {
+	/* these are boottime osd entries that differ from runtime entries */
+	acpi_os_allocate_bt,
+	acpi_os_callocate_bt,
+	acpi_os_free_bt,
+	acpi_os_queue_for_execution_bt,
+	acpi_os_read_pci_configuration_bt,
+	acpi_os_write_pci_configuration_bt,
+	acpi_os_stall_bt
+};
+static struct acpi_osd *acpi_osd = &acpi_osd_rt;
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE
+static void	__init
+acpi_cf_bm_statistics( void );
+#endif
+
+void __init
+acpi_os_bind_osd(int	acpi_phase)
+{
+	switch (acpi_phase) {
+	case	ACPI_CF_PHASE_BOOTTIME:
+		acpi_osd = &acpi_osd_bt;
+		printk("Acpi cfg:bind to Boot time Acpi OSD\n");
+		break;
+	case	ACPI_CF_PHASE_RUNTIME:
+	default:
+		acpi_osd = &acpi_osd_rt;
+		printk("Acpi cfg:bind to Run time Acpi OSD\n");
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE
+		acpi_cf_bm_statistics();
+#endif
+		break;
+	}
+}
+
+void *
+acpi_os_allocate(u32 size)
+{
+	return acpi_osd->allocate(size);
+}
+
+void *
+acpi_os_callocate(u32 size)
+{
+	return acpi_osd->callocate(size);
+}
+
+void
+acpi_os_free(void *ptr)
+{
+	acpi_osd->free(ptr);
+	return;
+}
+
+void
+acpi_os_stall(u32 us)
+{
+	acpi_osd->stall(us);
+	return;
+}
+
+acpi_status
+acpi_os_read_pci_configuration( acpi_pci_id *pci_id, u32 reg, void *value, u32 width)
+{
+	return acpi_osd->read_pci_configuration(pci_id, reg, value, width);
+}
+
+
+acpi_status
+acpi_os_write_pci_configuration( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width)
+{
+	return acpi_osd->write_pci_configuration(pci_id, reg, value, width);
+}
+
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE
+/*
+ * Let's profile bootmem usage to see how much we consume. J.I.
+ */
+static	unsigned long	bm_alloc_size __initdata = 0;
+static	unsigned long	bm_alloc_size_max __initdata = 0;
+static	unsigned long	bm_alloc_count_max __initdata = 0;
+static	unsigned long	bm_free_count_max __initdata = 0;
+
+static void	__init
+acpi_cf_bm_checkin(void *ptr, u32 size)
+{
+	bm_alloc_count_max++;
+	bm_alloc_size += size;
+	if (bm_alloc_size > bm_alloc_size_max)
+		bm_alloc_size_max = bm_alloc_size;
+};
+
+static void	__init
+acpi_cf_bm_checkout(void *ptr, u32 size)
+{
+	bm_free_count_max++;
+	bm_alloc_size -= size;
+};
+
+static void	__init
+acpi_cf_bm_statistics( void )
+{
+	printk("Acpi cfg:bm_alloc_size_max =%ld bytes\n", bm_alloc_size_max);
+	printk("Acpi cfg:bm_alloc_count_max=%ld\n", bm_alloc_count_max);
+	printk("Acpi cfg:bm_free_count_max =%ld\n", bm_free_count_max);
+}
+#endif
+
+
+static void * __init
+acpi_os_allocate_bt(u32 size)
+{
+	void *ptr;
+
+	size += sizeof(unsigned long);
+	ptr = alloc_bootmem(size);
+
+	if (ptr) {
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE
+		acpi_cf_bm_checkin(ptr, size);
+#endif
+		*((unsigned long *)ptr) = (unsigned long)size;
+		ptr += sizeof(unsigned long);
+	}
+
+	return ptr;
+}
+
+static void * __init
+acpi_os_callocate_bt(u32 size)
+{
+	void *ptr = acpi_os_allocate_bt(size);
+
+	return ptr;
+}
+
+static void __init
+acpi_os_free_bt(void *ptr)
+{
+	unsigned long	size;
+
+	ptr -= sizeof(size);
+	size = *((unsigned long *)ptr);
+
+#ifdef	CONFIG_ACPI_KERNEL_CONFIG_BM_PROFILE
+	acpi_cf_bm_checkout(ptr, (unsigned long)size);
+#endif
+	//if (size)
+		free_bootmem (__pa((unsigned long)ptr), (u32)size);
+}
+
+
+static void __init
+acpi_os_stall_bt(u32 us)
+{
+	unsigned long start = ia64_get_itc();
+	unsigned long cycles = us*733;	/* XXX: 733 or 800 */
+	while (ia64_get_itc() - start < cycles)
+		/* skip */;
+}
+
+
+static acpi_status __init
+acpi_os_queue_for_execution_bt(
+	u32			priority,
+	OSD_EXECUTION_CALLBACK	callback,
+	void			*context)
+{
+	/*
+	 * run callback immediately
+	 */
+	(*callback)(context);
+	return AE_OK;
+}
+
+
+static acpi_status __init
+acpi_os_read_pci_configuration_bt (
+	acpi_pci_id	*pci_id,
+	u32		reg,
+	void		*value,
+	u32		width)
+{
+	unsigned int	devfn;
+	s64		status;
+	u64		lval;
+
+	devfn = PCI_DEVFN(pci_id->device, pci_id->function);
+
+	switch (width)
+	{
+	case 8:
+		status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 1, &lval);
+		*(u8*)value = (u8)lval;
+		break;
+	case 16:
+		status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 2, &lval);
+		*(u16*)value = (u16)lval;
+		break;
+	case 32:
+		status = ia64_sal_pci_config_read(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 4, &lval);
+		*(u32*)value = (u32)lval;
+		break;
+	default:
+		BUG();
+	}
+
+	return status;
+}
+
+
+static acpi_status __init
+acpi_os_write_pci_configuration_bt (
+	acpi_pci_id	*pci_id,
+	u32		reg,
+	NATIVE_UINT	value,
+	u32		width)
+{
+	unsigned int	devfn;
+	s64		status;
+
+	devfn = PCI_DEVFN(pci_id->device, pci_id->function);
+
+	switch (width)
+	{
+	case 8:
+		status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 1, value);
+		break;
+	case 16:
+		status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 2, value);
+		break;
+	case 32:
+		status = ia64_sal_pci_config_write(PCI_CONFIG_ADDRESS((pci_id->bus), devfn, reg), 4, value);
+		break;
+	default:
+		BUG();
+	}
+
+	return status;
+}
diff -urN linux-2.4.16/drivers/acpi/osconf.h lia64-2.4/drivers/acpi/osconf.h
--- linux-2.4.16/drivers/acpi/osconf.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/acpi/osconf.h	Mon Sep 24 22:01:49 2001
@@ -0,0 +1,57 @@
+/*
+ *  osconf.h - ACPI OS-dependent headers for Kernel Boot/Configuration time
+ *
+ *  Copyright (C) 2000 Intel Corp.
+ *  Copyright (C) 2000 J.I. Lee <Jung-Ik.Lee@intel.com>
+ */
+
+
+struct acpi_osd {
+	void * (*allocate)(u32 size);
+	void * (*callocate)(u32 size);
+	void  (*free)(void *ptr);
+	acpi_status (*queue_for_exec)(u32 pri, OSD_EXECUTION_CALLBACK cb, void *context);
+	acpi_status (*read_pci_configuration)(acpi_pci_id *pci_id, u32 reg, void *value, u32 width);
+	acpi_status (*write_pci_configuration)(acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width);
+	void (*stall)(u32 us);
+};
+
+
+#define	PCI_CONFIG_ADDRESS(bus, devfn, where) \
+	(((u64) bus << 16) | ((u64) (devfn & 0xff) << 8) | (where & 0xff))
+
+#define	ACPI_CF_PHASE_BOOTTIME	0x00
+#define	ACPI_CF_PHASE_RUNTIME	0x01
+
+
+/* acpi_osd functions */
+void * acpi_os_allocate(u32 size);
+void * acpi_os_callocate(u32 size);
+void acpi_os_free(void *ptr);
+void acpi_os_stall(u32 us);
+
+acpi_status
+acpi_os_read_pci_configuration( acpi_pci_id *pci_id, u32 reg, void *value, u32 width );
+
+acpi_status
+acpi_os_write_pci_configuration( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width );
+
+
+/* acpi_osd_rt functions */
+extern void * acpi_os_allocate_rt(u32 size);
+extern void * acpi_os_callocate_rt(u32 size);
+extern void acpi_os_free_rt(void *ptr);
+extern void acpi_os_stall_rt(u32 us);
+
+extern acpi_status
+acpi_os_queue_for_execution_rt(
+	u32			priority,
+	OSD_EXECUTION_CALLBACK	callback,
+	void			*context
+	);
+
+extern acpi_status
+acpi_os_read_pci_configuration_rt( acpi_pci_id *pci_id, u32 reg, void *value, u32 width );
+
+extern acpi_status
+acpi_os_write_pci_configuration_rt( acpi_pci_id *pci_id, u32 reg, NATIVE_UINT value, u32 width );
diff -urN linux-2.4.16/drivers/acpi/ospm/include/ec.h lia64-2.4/drivers/acpi/ospm/include/ec.h
--- linux-2.4.16/drivers/acpi/ospm/include/ec.h	Mon Sep 24 15:06:44 2001
+++ lia64-2.4/drivers/acpi/ospm/include/ec.h	Mon Sep 24 22:03:30 2001
@@ -167,14 +167,14 @@
 acpi_status
 ec_io_read (
 	EC_CONTEXT              *ec,
-	u32         		io_port,
+	ACPI_IO_ADDRESS		io_port,
 	u8                      *data,
 	EC_EVENT                wait_event);
 
 acpi_status
 ec_io_write (
 	EC_CONTEXT              *ec,
-	u32         		io_port,
+	ACPI_IO_ADDRESS		io_port,
 	u8                      data,
 	EC_EVENT                wait_event);
 
diff -urN linux-2.4.16/drivers/acpi/ospm/system/sm_osl.c lia64-2.4/drivers/acpi/ospm/system/sm_osl.c
--- linux-2.4.16/drivers/acpi/ospm/system/sm_osl.c	Mon Nov  5 18:28:44 2001
+++ lia64-2.4/drivers/acpi/ospm/system/sm_osl.c	Mon Nov  5 18:34:13 2001
@@ -33,7 +33,9 @@
 #include <asm/uaccess.h>
 #include <linux/acpi.h>
 #include <asm/io.h>
+#ifndef __ia64__
 #include <linux/mc146818rtc.h>
+#endif
 #include <linux/delay.h>
 
 #include <acpi.h>
@@ -277,6 +279,7 @@
 	int                     *eof,
 	void                    *context)
 {
+#ifndef _IA64
 	char *str = page;
 	int len;
 	u32 sec,min,hr;
@@ -350,6 +353,9 @@
 	*start = page;
 
 	return len;
+#else
+	return 0;
+#endif
 }
 
 static int get_date_field(char **str, u32 *value)
@@ -380,6 +386,7 @@
 	unsigned long count,
 	void *data)
 {
+#ifndef _IA64
 	char buf[30];
 	char *str = buf;
 	u32 sec,min,hr;
@@ -519,6 +526,9 @@
 	error = 0;
  out:
 	return error ? error : count;
+#else
+	return 0;
+#endif
 }
 
 static int 
diff -urN linux-2.4.16/drivers/acpi/utilities/uteval.c lia64-2.4/drivers/acpi/utilities/uteval.c
--- linux-2.4.16/drivers/acpi/utilities/uteval.c	Mon Nov  5 18:28:44 2001
+++ lia64-2.4/drivers/acpi/utilities/uteval.c	Mon Nov  5 18:57:21 2001
@@ -115,6 +115,93 @@
 
 /*******************************************************************************
  *
+ * FUNCTION:    Acpi_ut_execute_CID
+ *
+ * PARAMETERS:  Device_node         - Node for the device
+ *              *Cid                - Where the CID is returned
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Executes the _CID control method that returns the compatible
+ *              ID of the device.
+ *
+ *              NOTE: Internal function, no parameter validation
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_execute_CID (
+	acpi_namespace_node     *device_node,
+	acpi_device_id          *cid)
+{
+	acpi_operand_object     *obj_desc;
+	acpi_status             status;
+
+
+	FUNCTION_TRACE ("Ut_execute_CID");
+
+
+	/* Execute the method */
+
+	status = acpi_ns_evaluate_relative (device_node,
+			 METHOD_NAME__CID, NULL, &obj_desc);
+	if (ACPI_FAILURE (status)) {
+		if (status == AE_NOT_FOUND) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "_CID on %4.4s was not found\n",
+				&device_node->name));
+		}
+
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_CID on %4.4s failed %s\n",
+				&device_node->name, acpi_format_exception (status)));
+		}
+
+		return_ACPI_STATUS (status);
+	}
+
+	/* Did we get a return object? */
+
+	if (!obj_desc) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "No object was returned from _CID\n"));
+		return_ACPI_STATUS (AE_TYPE);
+	}
+
+	/*
+	 *  A _CID can return either a Number (32 bit compressed EISA ID) or
+	 *  a string
+	 */
+	if ((obj_desc->common.type != ACPI_TYPE_INTEGER) &&
+		(obj_desc->common.type != ACPI_TYPE_STRING)) {
+		status = AE_TYPE;
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+			"Type returned from _CID not a number or string: %s(%X) \n",
+			acpi_ut_get_type_name (obj_desc->common.type), obj_desc->common.type));
+	}
+
+	else {
+		if (obj_desc->common.type == ACPI_TYPE_INTEGER) {
+			/* Convert the Numeric CID to string */
+
+			acpi_ex_eisa_id_to_string ((u32) obj_desc->integer.value, cid->buffer);
+		}
+
+		else {
+			/* Copy the String CID from the returned object */
+
+			STRNCPY(cid->buffer, obj_desc->string.pointer, sizeof(cid->buffer));
+		}
+	}
+
+
+	/* On exit, we must delete the return object */
+
+	acpi_ut_remove_reference (obj_desc);
+
+	return_ACPI_STATUS (status);
+}
+
+/*******************************************************************************
+ *
  * FUNCTION:    Acpi_ut_execute_HID
  *
  * PARAMETERS:  Device_node         - Node for the device
diff -urN linux-2.4.16/drivers/char/Config.in lia64-2.4/drivers/char/Config.in
--- linux-2.4.16/drivers/char/Config.in	Mon Nov 26 11:18:31 2001
+++ lia64-2.4/drivers/char/Config.in	Mon Nov 26 11:36:09 2001
@@ -211,6 +211,9 @@
 dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
 if [ "$CONFIG_AGP" != "n" ]; then
    bool '  Intel 440LX/BX/GX and I815/I830M/I840/I850 support' CONFIG_AGP_INTEL
+   if [ "$CONFIG_IA64" != "n" ]; then
+   	bool '  Intel 460GX support' CONFIG_AGP_I460
+   fi
    bool '  Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
    bool '  VIA chipset support' CONFIG_AGP_VIA
    bool '  AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
@@ -219,7 +222,17 @@
    bool '  Serverworks LE/HE support' CONFIG_AGP_SWORKS
 fi
 
-source drivers/char/drm/Config.in
+bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
+
+if [ "$CONFIG_DRM" = "y" ]; then
+   bool '  Build drivers for new (XFree 4.1) DRM' CONFIG_DRM_NEW
+   if [ "$CONFIG_DRM_NEW" = "y" ]; then
+      source drivers/char/drm/Config.in
+   else
+      define_bool CONFIG_DRM_OLD y
+      source drivers/char/drm-4.0/Config.in
+   fi
+fi
 
 if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
    source drivers/char/pcmcia/Config.in
diff -urN linux-2.4.16/drivers/char/Makefile lia64-2.4/drivers/char/Makefile
--- linux-2.4.16/drivers/char/Makefile	Mon Nov 26 11:18:31 2001
+++ lia64-2.4/drivers/char/Makefile	Mon Nov 26 11:37:06 2001
@@ -25,7 +25,7 @@
 			misc.o pty.o random.o selection.o serial.o \
 			sonypi.o tty_io.o tty_ioctl.o generic_serial.o
 
-mod-subdirs	:=	joystick ftape drm pcmcia
+mod-subdirs	:=	joystick ftape drm pcmcia drm-4.0
 
 list-multi	:=	
 
@@ -139,6 +139,7 @@
 
 obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
 obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
+obj-$(CONFIG_SIM_SERIAL) += simserial.o
 obj-$(CONFIG_ROCKETPORT) += rocket.o
 obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
 obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
@@ -200,7 +201,8 @@
 obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
 
 subdir-$(CONFIG_FTAPE) += ftape
-subdir-$(CONFIG_DRM) += drm
+subdir-$(CONFIG_DRM_NEW) += drm
+subdir-$(CONFIG_DRM_OLD) += drm-4.0
 subdir-$(CONFIG_PCMCIA) += pcmcia
 subdir-$(CONFIG_AGP) += agp
 
diff -urN linux-2.4.16/drivers/char/agp/agp.h lia64-2.4/drivers/char/agp/agp.h
--- linux-2.4.16/drivers/char/agp/agp.h	Mon Nov 26 11:18:31 2001
+++ lia64-2.4/drivers/char/agp/agp.h	Mon Nov 26 11:21:27 2001
@@ -84,8 +84,8 @@
 	void *dev_private_data;
 	struct pci_dev *dev;
 	gatt_mask *masks;
-	unsigned long *gatt_table;
-	unsigned long *gatt_table_real;
+	u32 *gatt_table;
+	u32 *gatt_table_real;
 	unsigned long scratch_page;
 	unsigned long gart_bus_addr;
 	unsigned long gatt_bus_addr;
@@ -111,6 +111,7 @@
 	void (*cleanup) (void);
 	void (*tlb_flush) (agp_memory *);
 	unsigned long (*mask_memory) (unsigned long, int);
+	unsigned long (*unmask_memory) (unsigned long);
 	void (*cache_flush) (void);
 	int (*create_gatt_table) (void);
 	int (*free_gatt_table) (void);
@@ -150,6 +151,10 @@
 #define A_IDXFIX()	(A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
 #define MAXKEY		(4096 * 32)
 
+#ifndef max
+#define max(a,b)	(((a)>(b))?(a):(b))
+#endif
+
 #define AGPGART_MODULE_NAME	"agpgart"
 #define PFX			AGPGART_MODULE_NAME ": "
 
@@ -218,6 +223,9 @@
 #ifndef PCI_DEVICE_ID_INTEL_82443GX_1
 #define PCI_DEVICE_ID_INTEL_82443GX_1   0x71a1
 #endif
+#ifndef PCI_DEVICE_ID_INTEL_460GX
+#define PCI_DEVICE_ID_INTEL_460GX	 0x84ea
+#endif
 #ifndef PCI_DEVICE_ID_AMD_IRONGATE_0
 #define PCI_DEVICE_ID_AMD_IRONGATE_0    0x7006
 #endif
@@ -259,6 +267,15 @@
 #define INTEL_AGPCTRL   0xb0
 #define INTEL_NBXCFG    0x50
 #define INTEL_ERRSTS    0x91
+
+/* Intel 460GX Registers */
+#define INTEL_I460_APBASE		0x10
+#define INTEL_I460_BAPBASE		0x98
+#define INTEL_I460_GXBCTL		0xa0
+#define INTEL_I460_AGPSIZ		0xa2
+#define INTEL_I460_ATTBASE		0xfe200000
+#define INTEL_I460_GATT_VALID		(1UL << 24)
+#define INTEL_I460_GATT_COHERENT	(1UL << 25)
 
 /* intel i830 registers */
 #define I830_GMCH_CTRL             0x52
diff -urN linux-2.4.16/drivers/char/agp/agpgart_be.c lia64-2.4/drivers/char/agp/agpgart_be.c
--- linux-2.4.16/drivers/char/agp/agpgart_be.c	Mon Nov 26 11:18:32 2001
+++ lia64-2.4/drivers/char/agp/agpgart_be.c	Mon Nov 26 11:34:29 2001
@@ -22,6 +22,7 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
+ * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
  */
 #include <linux/config.h>
 #include <linux/version.h>
@@ -43,6 +44,9 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
+#include <asm/smplock.h>
 
 #include <linux/agp_backend.h>
 #include "agp.h"
@@ -60,7 +64,7 @@
 EXPORT_SYMBOL(agp_backend_release);
 
 static void flush_cache(void);
-
+ 
 static struct agp_bridge_data agp_bridge;
 static int agp_try_unsupported __initdata = 0;
 
@@ -205,19 +209,56 @@
 		agp_bridge.free_by_type(curr);
 		return;
 	}
-	if (curr->page_count != 0) {
-		for (i = 0; i < curr->page_count; i++) {
-			curr->memory[i] &= ~(0x00000fff);
-			agp_bridge.agp_destroy_page((unsigned long)
-					 phys_to_virt(curr->memory[i]));
+	if(agp_bridge.cant_use_aperture == 0) {
+		if (curr->page_count != 0) {
+			for (i = 0; i < curr->page_count; i++) {
+				curr->memory[i] = agp_bridge.unmask_memory(
+					                     curr->memory[i]);
+				agp_bridge.agp_destroy_page((unsigned long)
+						 phys_to_virt(curr->memory[i]));
+			}
 		}
+	} else {
+		vfree(curr->vmptr);
 	}
+
 	agp_free_key(curr->key);
 	vfree(curr->memory);
 	kfree(curr);
 	MOD_DEC_USE_COUNT;
 }
 
+#define IN_VMALLOC(_x)	  (((_x) >= VMALLOC_START) && ((_x) < VMALLOC_END))
+
+/*
+ * Look up and return the pte corresponding to addr.  We only do this for
+ * agp_ioremap'ed addresses. 
+ */
+static pte_t * agp_lookup_pte(unsigned long addr) { 
+
+	pgd_t			*dir;
+	pmd_t			*pmd;
+	pte_t			*pte;
+
+	if(!IN_VMALLOC(addr))
+		return NULL;
+
+	dir = pgd_offset_k(addr);
+	pmd = pmd_offset(dir, addr);
+
+	if(pmd) {
+		pte = pte_offset(pmd, addr);
+
+		if(pte) {
+			return pte;
+		} else {
+			return NULL;
+		}
+	} else {
+		return NULL;
+	}
+}
+
 #define ENTRIES_PER_PAGE		(PAGE_SIZE / sizeof(unsigned long))
 
 agp_memory *agp_allocate_memory(size_t page_count, u32 type)
@@ -247,24 +288,60 @@
 	scratch_pages = (page_count + ENTRIES_PER_PAGE - 1) / ENTRIES_PER_PAGE;
 
 	new = agp_create_memory(scratch_pages);
-
 	if (new == NULL) {
 	      	MOD_DEC_USE_COUNT;
 		return NULL;
 	}
-	for (i = 0; i < page_count; i++) {
-		new->memory[i] = agp_bridge.agp_alloc_page();
 
-		if (new->memory[i] == 0) {
-			/* Free this structure */
-			agp_free_memory(new);
+	if(agp_bridge.cant_use_aperture == 0) {
+		for (i = 0; i < page_count; i++) {
+			new->memory[i] = agp_bridge.agp_alloc_page();
+
+			if (new->memory[i] == 0) {
+				/* Free this structure */
+				agp_free_memory(new);
+				return NULL;
+			}
+			new->memory[i] =
+			    agp_bridge.mask_memory(
+					  virt_to_phys((void *) new->memory[i]),
+							  type);
+			new->page_count++;
+		}
+	} else {
+		void *vmblock;
+		unsigned long vaddr, paddr;
+		pte_t *pte;
+
+		vmblock = __vmalloc(page_count << PAGE_SHIFT, GFP_KERNEL,
+#ifdef __ia64__
+					pgprot_writecombine(PAGE_KERNEL));
+#else
+					PAGE_KERNEL);
+#endif
+		if(vmblock == NULL) {
+			MOD_DEC_USE_COUNT;
 			return NULL;
 		}
-		new->memory[i] =
-		    agp_bridge.mask_memory(
-				   virt_to_phys((void *) new->memory[i]),
-						  type);
-		new->page_count++;
+
+		new->vmptr = vmblock;
+		vaddr = (unsigned long) vmblock;
+
+		for(i = 0; i < page_count; i++, vaddr += PAGE_SIZE) {
+			pte = agp_lookup_pte(vaddr);
+			if(pte == NULL) {
+				MOD_DEC_USE_COUNT;
+				return NULL;
+			}
+#ifdef __ia64__
+			paddr = pte_val(*pte) & _PFN_MASK;
+#else
+			paddr = pte_val(*pte) & PAGE_MASK;
+#endif
+			new->memory[i] = agp_bridge.mask_memory(paddr, type);
+		}
+
+		new->page_count = page_count;
 	}
 
 	return new;
@@ -353,12 +430,13 @@
 		curr->is_flushed = TRUE;
 	}
 	ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type);
-
+		
 	if (ret_val != 0) {
 		return ret_val;
 	}
 	curr->is_bound = TRUE;
 	curr->pg_start = pg_start;
+
 	return 0;
 }
 
@@ -377,6 +455,7 @@
 	if (ret_val != 0) {
 		return ret_val;
 	}
+
 	curr->is_bound = FALSE;
 	curr->pg_start = 0;
 	return 0;
@@ -387,9 +466,9 @@
 /* 
  * Driver routines - start
  * Currently this module supports the following chipsets:
- * i810, i815, 440lx, 440bx, 440gx, i830, i840, i845, i850, i860, via vp3,
+ * i810, i815, 440lx, 440bx, 440gx, 460gx, i830, i840, i845, i850, i860, via vp3,
  * via mvp3, via kx133, via kt133, amd irongate, amd 761, amd 762, ALi M1541,
- * and generic support for the SiS chipsets.
+ * chipsets.
  */
 
 /* Generic Agp routines - Start */
@@ -614,7 +693,7 @@
 	for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
 		set_bit(PG_reserved, &page->flags);
 
-	agp_bridge.gatt_table_real = (unsigned long *) table;
+	agp_bridge.gatt_table_real = (u32 *) table;
 	CACHE_FLUSH();
 	agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
 					(PAGE_SIZE * (1 << page_order)));
@@ -833,6 +912,11 @@
 	agp_bridge.agp_enable(mode);
 }
 
+static unsigned long agp_generic_unmask_memory(unsigned long addr)
+{
+	return addr & ~(0x00000fff);
+}
+
 /* End - Generic Agp routines */
 
 #ifdef CONFIG_AGP_I810
@@ -1097,6 +1181,7 @@
 	agp_bridge.cleanup = intel_i810_cleanup;
 	agp_bridge.tlb_flush = intel_i810_tlbflush;
 	agp_bridge.mask_memory = intel_i810_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = intel_i810_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -1404,6 +1489,633 @@
 
 #endif /* CONFIG_AGP_I810 */
 
+#ifdef CONFIG_AGP_I460
+
+/* BIOS configures the chipset so that one of two apbase registers are used */
+static u8 intel_i460_dynamic_apbase = 0x10;
+
+/* 460 supports multiple GART page sizes, so GART pageshift is dynamic */ 
+static u8 intel_i460_pageshift = 12;
+
+/* Keep track of which is larger, chipset or kernel page size. */
+static u32 intel_i460_cpk = 1;
+
+/* Structure for tracking partial use of 4MB GART pages */
+static u32 **i460_pg_detail = NULL;
+static u32 *i460_pg_count = NULL;
+
+#define I460_CPAGES_PER_KPAGE (PAGE_SIZE >> intel_i460_pageshift)
+#define I460_KPAGES_PER_CPAGE ((1 << intel_i460_pageshift) >> PAGE_SHIFT)
+
+#define I460_SRAM_IO_DISABLE		(1 << 4)
+#define I460_BAPBASE_ENABLE		(1 << 3)
+#define I460_AGPSIZ_MASK		0x7
+#define I460_4M_PS			(1 << 1)
+
+#define log2(x)				ffz(~(x))
+
+static int intel_i460_fetch_size(void)
+{
+	int i;
+	u8 temp;
+	aper_size_info_8 *values;
+
+	/* Determine the GART page size */
+	pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp);
+	intel_i460_pageshift = (temp & I460_4M_PS) ? 22 : 12;
+
+	values = A_SIZE_8(agp_bridge.aperture_sizes);
+
+	pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
+
+	/* Exit now if the IO drivers for the GART SRAMS are turned off */
+	if(temp & I460_SRAM_IO_DISABLE) {
+		printk("[agpgart] GART SRAMS disabled on 460GX chipset\n");
+		printk("[agpgart] AGPGART operation not possible\n");
+		return 0;
+	}
+
+	/* Make sure we don't try to create an 2 ^ 23 entry GATT */
+	if((intel_i460_pageshift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
+		printk("[agpgart] We can't have a 32GB aperture with 4KB"
+			" GART pages\n");
+		return 0;
+	}
+
+	/* Determine the proper APBASE register */
+	if(temp & I460_BAPBASE_ENABLE)
+		intel_i460_dynamic_apbase = INTEL_I460_BAPBASE;
+	else intel_i460_dynamic_apbase = INTEL_I460_APBASE;
+
+	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+
+		/*
+		 * Dynamically calculate the proper num_entries and page_order 
+		 * values for the define aperture sizes. Take care not to
+		 * shift off the end of values[i].size.
+		 */	
+		values[i].num_entries = (values[i].size << 8) >>
+						(intel_i460_pageshift - 12);
+		values[i].page_order = log2((sizeof(u32)*values[i].num_entries)
+						>> PAGE_SHIFT);
+	}
+
+	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+		/* Neglect control bits when matching up size_value */
+		if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
+			agp_bridge.previous_size =
+			    agp_bridge.current_size = (void *) (values + i);
+			agp_bridge.aperture_size_idx = i;
+			return values[i].size;
+		}
+	}
+
+	return 0;
+}
+
+/* There isn't anything to do here since 460 has no GART TLB. */ 
+static void intel_i460_tlb_flush(agp_memory * mem)
+{
+	return;
+}
+
+/*
+ * This utility function is needed to prevent corruption of the control bits
+ * which are stored along with the aperture size in 460's AGPSIZ register
+ */
+static void intel_i460_write_agpsiz(u8 size_value)
+{
+	u8 temp;
+
+	pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
+	pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ,
+		((temp & ~I460_AGPSIZ_MASK) | size_value));
+}
+
+static void intel_i460_cleanup(void)
+{
+	aper_size_info_8 *previous_size;
+
+	previous_size = A_SIZE_8(agp_bridge.previous_size);
+	intel_i460_write_agpsiz(previous_size->size_value);
+
+	if(intel_i460_cpk == 0)
+	{
+		vfree(i460_pg_detail);
+		vfree(i460_pg_count);
+	}
+}
+
+
+/* Control bits for Out-Of-GART coherency and Burst Write Combining */
+#define I460_GXBCTL_OOG		(1UL << 0)
+#define I460_GXBCTL_BWC		(1UL << 2)
+
+static int intel_i460_configure(void)
+{
+	union {
+		u32 small[2];
+		u64 large;
+	} temp;
+	u8 scratch;
+	int i;
+
+	aper_size_info_8 *current_size;
+
+	temp.large = 0;
+
+	current_size = A_SIZE_8(agp_bridge.current_size);
+	intel_i460_write_agpsiz(current_size->size_value);	
+
+	/*
+	 * Do the necessary rigmarole to read all eight bytes of APBASE.
+	 * This has to be done since the AGP aperture can be above 4GB on
+	 * 460 based systems.
+	 */
+	pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase, 
+		&(temp.small[0]));
+	pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase + 4,
+		&(temp.small[1]));
+
+	/* Clear BAR control bits */
+	agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1); 
+
+	pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch);
+	pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL,
+			  (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
+
+	/* 
+	 * Initialize partial allocation trackers if a GART page is bigger than
+	 * a kernel page.
+	 */
+	if(I460_CPAGES_PER_KPAGE >= 1) {
+		intel_i460_cpk = 1;
+	} else {
+		intel_i460_cpk = 0;
+
+		i460_pg_detail = (void *) vmalloc(sizeof(*i460_pg_detail) *
+					current_size->num_entries);
+		i460_pg_count = (void *) vmalloc(sizeof(*i460_pg_count) *
+					current_size->num_entries);
+	
+		for (i = 0; i < current_size->num_entries; i++) {
+			i460_pg_count[i] = 0;
+			i460_pg_detail[i] = NULL;
+		}
+	}
+
+	return 0;
+}
+
+static int intel_i460_create_gatt_table(void) {
+
+	char *table;
+	int i;
+	int page_order;
+	int num_entries;
+	void *temp;
+	unsigned int read_back;
+
+	/*
+	 * Load up the fixed address of the GART SRAMS which hold our
+	 * GATT table.
+	 */
+	table = (char *) __va(INTEL_I460_ATTBASE);
+
+	temp = agp_bridge.current_size;
+	page_order = A_SIZE_8(temp)->page_order;
+	num_entries = A_SIZE_8(temp)->num_entries;
+
+	agp_bridge.gatt_table_real = (u32 *) table;
+	agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
+		 			     (PAGE_SIZE * (1 << page_order)));
+	agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real);
+
+	for (i = 0; i < num_entries; i++) {
+		agp_bridge.gatt_table[i] = 0;
+	}
+
+	/* 
+	 * The 460 spec says we have to read the last location written to 
+	 * make sure that all writes have taken effect
+	 */
+	read_back = agp_bridge.gatt_table[i - 1];
+
+	return 0;
+}
+
+static int intel_i460_free_gatt_table(void)
+{
+	int num_entries;
+	int i;
+	void *temp;
+	unsigned int read_back;
+
+	temp = agp_bridge.current_size;
+
+	num_entries = A_SIZE_8(temp)->num_entries;
+
+	for (i = 0; i < num_entries; i++) {
+		agp_bridge.gatt_table[i] = 0;
+	}
+	
+	/* 
+	 * The 460 spec says we have to read the last location written to 
+	 * make sure that all writes have taken effect
+	 */
+	read_back = agp_bridge.gatt_table[i - 1];
+
+	iounmap(agp_bridge.gatt_table);
+
+	return 0;
+}
+
+/* These functions are called when PAGE_SIZE exceeds the GART page size */	
+
+static int intel_i460_insert_memory_cpk(agp_memory * mem,
+				     off_t pg_start, int type)
+{
+	int i, j, k, num_entries;
+	void *temp;
+	unsigned int hold;
+	unsigned int read_back;
+
+	/* 
+	 * The rest of the kernel will compute page offsets in terms of
+	 * PAGE_SIZE.
+	 */
+	pg_start = I460_CPAGES_PER_KPAGE * pg_start;
+
+	temp = agp_bridge.current_size;
+	num_entries = A_SIZE_8(temp)->num_entries;
+
+	if((pg_start + I460_CPAGES_PER_KPAGE * mem->page_count) > num_entries) {
+		printk("[agpgart] Looks like we're out of AGP memory\n");
+		return -EINVAL;
+	}
+
+	j = pg_start;
+	while (j < (pg_start + I460_CPAGES_PER_KPAGE * mem->page_count)) {
+		if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
+			return -EBUSY;
+		}
+		j++;
+	}
+
+	if (mem->is_flushed == FALSE) {
+		CACHE_FLUSH();
+		mem->is_flushed = TRUE;
+	}
+
+	for (i = 0, j = pg_start; i < mem->page_count; i++) {
+
+		hold = (unsigned int) (mem->memory[i]);
+
+		for (k = 0; k < I460_CPAGES_PER_KPAGE; k++, j++, hold++)
+			agp_bridge.gatt_table[j] = hold;
+	}
+
+	/* 
+	 * The 460 spec says we have to read the last location written to 
+	 * make sure that all writes have taken effect
+	 */
+	read_back = agp_bridge.gatt_table[j - 1];
+
+	return 0;
+}
+
+static int intel_i460_remove_memory_cpk(agp_memory * mem, off_t pg_start,
+				     int type)
+{
+	int i;
+	unsigned int read_back;
+
+	pg_start = I460_CPAGES_PER_KPAGE * pg_start;
+
+	for (i = pg_start; i < (pg_start + I460_CPAGES_PER_KPAGE * 
+							mem->page_count); i++) 
+		agp_bridge.gatt_table[i] = 0;
+
+	/* 
+	 * The 460 spec says we have to read the last location written to 
+	 * make sure that all writes have taken effect
+	 */
+	read_back = agp_bridge.gatt_table[i - 1];
+
+	return 0;
+}
+
+/*
+ * These functions are called when the GART page size exceeds PAGE_SIZE.
+ *
+ * This situation is interesting since AGP memory allocations that are
+ * smaller than a single GART page are possible.  The structures i460_pg_count
+ * and i460_pg_detail track partial allocation of the large GART pages to
+ * work around this issue.
+ *
+ * i460_pg_count[pg_num] tracks the number of kernel pages in use within
+ * GART page pg_num.  i460_pg_detail[pg_num] is an array containing a
+ * psuedo-GART entry for each of the aforementioned kernel pages.  The whole
+ * of i460_pg_detail is equivalent to a giant GATT with page size equal to
+ * that of the kernel.
+ */	
+
+static void *intel_i460_alloc_large_page(int pg_num)
+{
+	int i;
+	void *bp, *bp_end;
+	struct page *page;
+
+	i460_pg_detail[pg_num] = (void *) vmalloc(sizeof(u32) * 
+							I460_KPAGES_PER_CPAGE);
+	if(i460_pg_detail[pg_num] == NULL) {
+		printk("[agpgart] Out of memory, we're in trouble...\n");
+		return NULL;
+	}
+
+	for(i = 0; i < I460_KPAGES_PER_CPAGE; i++)
+		i460_pg_detail[pg_num][i] = 0;
+
+	bp = (void *) __get_free_pages(GFP_KERNEL, 
+					intel_i460_pageshift - PAGE_SHIFT);
+	if(bp == NULL) {
+		printk("[agpgart] Couldn't alloc 4M GART page...\n");
+		return NULL;
+	}
+
+	bp_end = bp + ((PAGE_SIZE * 
+			    (1 << (intel_i460_pageshift - PAGE_SHIFT))) - 1);
+
+	for (page = virt_to_page(bp); page <= virt_to_page(bp_end); page++)
+	{
+		atomic_inc(&page->count);
+		set_bit(PG_locked, &page->flags);
+		atomic_inc(&agp_bridge.current_memory_agp);
+	}
+
+	return bp;		
+}
+
+static void intel_i460_free_large_page(int pg_num, unsigned long addr)
+{
+	struct page *page;
+	void *bp, *bp_end;
+
+	bp = (void *) __va(addr);
+	bp_end = bp + (PAGE_SIZE * 
+			(1 << (intel_i460_pageshift - PAGE_SHIFT)));
+
+	vfree(i460_pg_detail[pg_num]);
+	i460_pg_detail[pg_num] = NULL;
+
+	for (page = virt_to_page(bp); page < virt_to_page(bp_end); page++)
+	{
+		atomic_dec(&page->count);
+		clear_bit(PG_locked, &page->flags);
+		wake_up(&page->wait);
+		atomic_dec(&agp_bridge.current_memory_agp);
+	}
+
+	free_pages((unsigned long) bp, intel_i460_pageshift - PAGE_SHIFT);
+}
+	
+static int intel_i460_insert_memory_kpc(agp_memory * mem,
+				     off_t pg_start, int type)
+{
+	int i, pg, start_pg, end_pg, start_offset, end_offset, idx;
+	int num_entries;	
+	void *temp;
+	unsigned int read_back;
+
+	temp = agp_bridge.current_size;
+	num_entries = A_SIZE_8(temp)->num_entries;
+
+	/* Figure out what pg_start means in terms of our large GART pages */
+	start_pg 	= pg_start / I460_KPAGES_PER_CPAGE;
+	start_offset 	= pg_start % I460_KPAGES_PER_CPAGE;
+	end_pg 		= (pg_start + mem->page_count - 1) / 
+							I460_KPAGES_PER_CPAGE;
+	end_offset 	= (pg_start + mem->page_count - 1) % 
+							I460_KPAGES_PER_CPAGE;
+
+	if(end_pg > num_entries)
+	{
+		printk("[agpgart] Looks like we're out of AGP memory\n");
+		return -EINVAL;
+	}
+
+	/* Check if the requested region of the aperture is free */
+	for(pg = start_pg; pg <= end_pg; pg++)
+	{
+		/* Allocate new GART pages if necessary */
+		if(i460_pg_detail[pg] == NULL) {
+			temp = intel_i460_alloc_large_page(pg);
+			if(temp == NULL)
+				return -ENOMEM;
+			agp_bridge.gatt_table[pg] = agp_bridge.mask_memory(
+			    			       (unsigned long) temp, 0);
+			read_back = agp_bridge.gatt_table[pg];
+		}
+
+		for(idx = ((pg == start_pg) ? start_offset : 0);
+		    idx < ((pg == end_pg) ? (end_offset + 1) 
+				       : I460_KPAGES_PER_CPAGE);
+		    idx++) 
+		{
+			if(i460_pg_detail[pg][idx] != 0)
+				return -EBUSY;
+		}
+	}
+		
+	if (mem->is_flushed == FALSE) {
+		CACHE_FLUSH();
+		mem->is_flushed = TRUE;
+	}
+
+	for(pg = start_pg, i = 0; pg <= end_pg; pg++)
+	{
+		for(idx = ((pg == start_pg) ? start_offset : 0);
+		    idx < ((pg == end_pg) ? (end_offset + 1)
+				       : I460_KPAGES_PER_CPAGE);
+		    idx++, i++)
+		{
+			i460_pg_detail[pg][idx] = agp_bridge.gatt_table[pg] + 
+						      ((idx * PAGE_SIZE) >> 12);
+			i460_pg_count[pg]++;
+
+			/* Finally we fill in mem->memory... */
+			mem->memory[i] = ((unsigned long) (0xffffff & 
+						i460_pg_detail[pg][idx])) << 12;
+		}
+	}
+
+	return 0;
+}
+	
+static int intel_i460_remove_memory_kpc(agp_memory * mem,
+				     off_t pg_start, int type)
+{
+	int i, pg, start_pg, end_pg, start_offset, end_offset, idx;
+	int num_entries;
+	void *temp;
+	unsigned int read_back;
+	unsigned long addr;
+
+	temp = agp_bridge.current_size;
+	num_entries = A_SIZE_8(temp)->num_entries;
+
+	/* Figure out what pg_start means in terms of our large GART pages */
+	start_pg 	= pg_start / I460_KPAGES_PER_CPAGE;
+	start_offset 	= pg_start % I460_KPAGES_PER_CPAGE;
+	end_pg 		= (pg_start + mem->page_count - 1) / 
+						I460_KPAGES_PER_CPAGE;
+	end_offset 	= (pg_start + mem->page_count - 1) % 
+						I460_KPAGES_PER_CPAGE;
+
+	for(i = 0, pg = start_pg; pg <= end_pg; pg++)
+	{
+		for(idx = ((pg == start_pg) ? start_offset : 0);
+		    idx < ((pg == end_pg) ? (end_offset + 1)
+				       : I460_KPAGES_PER_CPAGE);
+		    idx++, i++) 
+		{
+			mem->memory[i] = 0;
+			i460_pg_detail[pg][idx] = 0;
+			i460_pg_count[pg]--;
+		}
+
+		/* Free GART pages if they are unused */
+		if(i460_pg_count[pg] == 0) {
+			addr = (0xffffffUL & (unsigned long) 
+					     (agp_bridge.gatt_table[pg])) << 12;
+
+			agp_bridge.gatt_table[pg] = 0;
+			read_back = agp_bridge.gatt_table[pg];
+
+			intel_i460_free_large_page(pg, addr);
+		}
+	}
+		
+	return 0;
+}
+
+/* Dummy routines to call the approriate {cpk,kpc} function */
+
+static int intel_i460_insert_memory(agp_memory * mem,
+				     off_t pg_start, int type)
+{
+	if(intel_i460_cpk)
+		return intel_i460_insert_memory_cpk(mem, pg_start, type);
+	else
+		return intel_i460_insert_memory_kpc(mem, pg_start, type);
+}
+
+static int intel_i460_remove_memory(agp_memory * mem,
+				     off_t pg_start, int type)
+{
+	if(intel_i460_cpk)
+		return intel_i460_remove_memory_cpk(mem, pg_start, type);
+	else
+		return intel_i460_remove_memory_kpc(mem, pg_start, type);
+}
+
+/*
+ * If the kernel page size is smaller that the chipset page size, we don't
+ * want to allocate memory until we know where it is to be bound in the
+ * aperture (a multi-kernel-page alloc might fit inside of an already
+ * allocated GART page).  Consequently, don't allocate or free anything
+ * if i460_cpk (meaning chipset pages per kernel page) isn't set.
+ *
+ * Let's just hope nobody counts on the allocated AGP memory being there
+ * before bind time (I don't think current drivers do)...
+ */ 
+static unsigned long intel_i460_alloc_page(void)
+{
+	if(intel_i460_cpk)
+		return agp_generic_alloc_page();
+
+	/* Returning NULL would cause problems */
+	return ((unsigned long) ~0UL);
+}
+
+static void intel_i460_destroy_page(unsigned long page)
+{
+	if(intel_i460_cpk)
+		agp_generic_destroy_page(page);
+}
+
+static gatt_mask intel_i460_masks[] =
+{
+	{ 
+	  INTEL_I460_GATT_VALID, 
+	  0
+	}
+};
+
+static unsigned long intel_i460_mask_memory(unsigned long addr, int type) 
+{
+	/* Make sure the returned address is a valid GATT entry */
+	return (agp_bridge.masks[0].mask | (((addr & 
+		     ~((1 << intel_i460_pageshift) - 1)) & 0xffffff000) >> 12));
+}
+
+static unsigned long intel_i460_unmask_memory(unsigned long addr)
+{
+	/* Turn a GATT entry into a physical address */
+	return ((addr & 0xffffff) << 12);
+}
+
+static aper_size_info_8 intel_i460_sizes[3] =
+{
+	/* 
+	 * The 32GB aperture is only available with a 4M GART page size.
+	 * Due to the dynamic GART page size, we can't figure out page_order
+	 * or num_entries until runtime.
+	 */
+	{32768, 0, 0, 4},
+	{1024, 0, 0, 2},
+	{256, 0, 0, 1}
+};
+
+static int __init intel_i460_setup (struct pci_dev *pdev)
+{
+
+        agp_bridge.masks = intel_i460_masks;
+        agp_bridge.num_of_masks = 1;
+        agp_bridge.aperture_sizes = (void *) intel_i460_sizes;
+        agp_bridge.size_type = U8_APER_SIZE;
+        agp_bridge.num_aperture_sizes = 3;
+        agp_bridge.dev_private_data = NULL;
+        agp_bridge.needs_scratch_page = FALSE;
+        agp_bridge.configure = intel_i460_configure;
+        agp_bridge.fetch_size = intel_i460_fetch_size;
+        agp_bridge.cleanup = intel_i460_cleanup;
+        agp_bridge.tlb_flush = intel_i460_tlb_flush;
+        agp_bridge.mask_memory = intel_i460_mask_memory;
+        agp_bridge.unmask_memory = intel_i460_unmask_memory;
+        agp_bridge.agp_enable = agp_generic_agp_enable;
+        agp_bridge.cache_flush = global_cache_flush;
+        agp_bridge.create_gatt_table = intel_i460_create_gatt_table;
+        agp_bridge.free_gatt_table = intel_i460_free_gatt_table;
+        agp_bridge.insert_memory = intel_i460_insert_memory;
+        agp_bridge.remove_memory = intel_i460_remove_memory;
+        agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
+        agp_bridge.free_by_type = agp_generic_free_by_type;
+        agp_bridge.agp_alloc_page = intel_i460_alloc_page;
+        agp_bridge.agp_destroy_page = intel_i460_destroy_page;
+#if 0
+	agp_bridge.suspend = ??;
+	agp_bridge.resume = ??;
+#endif
+	agp_bridge.cant_use_aperture = 1;
+
+        return 0;
+
+        (void) pdev; /* unused */
+}
+
+#endif		/* CONFIG_AGP_I460 */
+
 #ifdef CONFIG_AGP_INTEL
 
 static int intel_fetch_size(void)
@@ -1759,6 +2471,7 @@
 	agp_bridge.cleanup = intel_cleanup;
 	agp_bridge.tlb_flush = intel_tlbflush;
 	agp_bridge.mask_memory = intel_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -1857,6 +2570,7 @@
 	agp_bridge.cleanup = intel_8xx_cleanup;
 	agp_bridge.tlb_flush = intel_8xx_tlbflush;
 	agp_bridge.mask_memory = intel_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -1890,6 +2604,7 @@
 	agp_bridge.cleanup = intel_8xx_cleanup;
 	agp_bridge.tlb_flush = intel_8xx_tlbflush;
 	agp_bridge.mask_memory = intel_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -2043,6 +2758,7 @@
 	agp_bridge.cleanup = via_cleanup;
 	agp_bridge.tlb_flush = via_tlbflush;
 	agp_bridge.mask_memory = via_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -2157,6 +2873,7 @@
 	agp_bridge.cleanup = sis_cleanup;
 	agp_bridge.tlb_flush = sis_tlbflush;
 	agp_bridge.mask_memory = sis_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -2179,8 +2896,8 @@
 #ifdef CONFIG_AGP_AMD
 
 typedef struct _amd_page_map {
-	unsigned long *real;
-	unsigned long *remapped;
+	u32 *real;
+	u32 *remapped;
 } amd_page_map;
 
 static struct _amd_irongate_private {
@@ -2193,7 +2910,7 @@
 {
 	int i;
 
-	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
+	page_map->real = (u32 *) __get_free_page(GFP_KERNEL);
 	if (page_map->real == NULL) {
 		return -ENOMEM;
 	}
@@ -2448,7 +3165,7 @@
 			     off_t pg_start, int type)
 {
 	int i, j, num_entries;
-	unsigned long *cur_gatt;
+	u32 *cur_gatt;
 	unsigned long addr;
 
 	num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
@@ -2488,7 +3205,7 @@
 			     int type)
 {
 	int i;
-	unsigned long *cur_gatt;
+	u32 *cur_gatt;
 	unsigned long addr;
 
 	if (type != 0 || mem->type != 0) {
@@ -2535,6 +3252,7 @@
 	agp_bridge.cleanup = amd_irongate_cleanup;
 	agp_bridge.tlb_flush = amd_irongate_tlbflush;
 	agp_bridge.mask_memory = amd_irongate_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = amd_create_gatt_table;
@@ -2783,6 +3501,7 @@
 	agp_bridge.cleanup = ali_cleanup;
 	agp_bridge.tlb_flush = ali_tlbflush;
 	agp_bridge.mask_memory = ali_mask_memory;
+	agp_bridge.unmask_memory = agp_generic_unmask_memory;
 	agp_bridge.agp_enable = agp_generic_agp_enable;
 	agp_bridge.cache_flush = ali_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
@@ -3591,6 +4310,15 @@
 
 #endif /* CONFIG_AGP_INTEL */
 
+#ifdef CONFIG_AGP_I460
+	{ PCI_DEVICE_ID_INTEL_460GX,
+		PCI_VENDOR_ID_INTEL,
+		INTEL_460GX,
+		"Intel",
+		"460GX",
+		intel_i460_setup },
+#endif
+
 #ifdef CONFIG_AGP_SIS
 	{ PCI_DEVICE_ID_SI_740,
 		PCI_VENDOR_ID_SI,
@@ -3789,6 +4517,18 @@
 	return -ENODEV;
 }
 
+static int agp_check_supported_device(struct pci_dev *dev) {
+
+	int i;
+
+	for(i = 0; i < ARRAY_SIZE (agp_bridge_info); i++) {
+		if(dev->vendor == agp_bridge_info[i].vendor_id &&
+		   dev->device == agp_bridge_info[i].device_id)
+			return 1;
+	}
+
+	return 0;
+}
 
 /* Supported Device Scanning routine */
 
@@ -3798,8 +4538,14 @@
 	u8 cap_ptr = 0x00;
 	u32 cap_id, scratch;
 
-	if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) == NULL)
-		return -ENODEV;
+	/* 
+	 * Some systems have multiple host bridges (i.e. BigSur), so
+	 * we can't just use the first one we find.
+	 */
+	do {
+		if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, dev)) == NULL)
+			return -ENODEV;
+	} while(!agp_check_supported_device(dev));
 
 	agp_bridge.dev = dev;
 
diff -urN linux-2.4.16/drivers/char/drm/Config.in lia64-2.4/drivers/char/drm/Config.in
--- linux-2.4.16/drivers/char/drm/Config.in	Wed Aug  8 09:42:10 2001
+++ lia64-2.4/drivers/char/drm/Config.in	Wed Aug 15 20:52:09 2001
@@ -5,12 +5,9 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 #
 
-bool 'Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)' CONFIG_DRM
-if [ "$CONFIG_DRM" != "n" ]; then
-    tristate '  3dfx Banshee/Voodoo3+' CONFIG_DRM_TDFX
-    tristate '  3dlabs GMX 2000' CONFIG_DRM_GAMMA
-    tristate '  ATI Rage 128' CONFIG_DRM_R128
-    dep_tristate '  ATI Radeon' CONFIG_DRM_RADEON $CONFIG_AGP
-    dep_tristate '  Intel I810' CONFIG_DRM_I810 $CONFIG_AGP
-    dep_tristate '  Matrox g200/g400' CONFIG_DRM_MGA $CONFIG_AGP
-fi
+tristate '  3dfx Banshee/Voodoo3+' CONFIG_DRM_TDFX
+tristate '  3dlabs GMX 2000' CONFIG_DRM_GAMMA
+tristate '  ATI Rage 128' CONFIG_DRM_R128
+dep_tristate '  ATI Radeon' CONFIG_DRM_RADEON $CONFIG_AGP
+dep_tristate '  Intel I810' CONFIG_DRM_I810 $CONFIG_AGP
+dep_tristate '  Matrox g200/g400' CONFIG_DRM_MGA $CONFIG_AGP
diff -urN linux-2.4.16/drivers/char/drm/ati_pcigart.h lia64-2.4/drivers/char/drm/ati_pcigart.h
--- linux-2.4.16/drivers/char/drm/ati_pcigart.h	Mon Nov 26 11:18:32 2001
+++ lia64-2.4/drivers/char/drm/ati_pcigart.h	Mon Nov 26 11:21:28 2001
@@ -30,7 +30,10 @@
 #define __NO_VERSION__
 #include "drmP.h"
 
-#if PAGE_SIZE == 8192
+#if PAGE_SIZE == 16384
+# define ATI_PCIGART_TABLE_ORDER 	1
+# define ATI_PCIGART_TABLE_PAGES 	(1 << 1)
+#elif PAGE_SIZE == 8192
 # define ATI_PCIGART_TABLE_ORDER 	2
 # define ATI_PCIGART_TABLE_PAGES 	(1 << 2)
 #elif PAGE_SIZE == 4096
@@ -103,6 +106,7 @@
 		goto done;
 	}
 
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 	if ( !dev->pdev ) {
 		DRM_ERROR( "PCI device unknown!\n" );
 		goto done;
@@ -117,6 +121,9 @@
 		address = 0;
 		goto done;
 	}
+#else
+	bus_address = virt_to_bus( (void *)address );
+#endif
 
 	pci_gart = (u32 *)address;
 
@@ -126,6 +133,7 @@
 	memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) );
 
 	for ( i = 0 ; i < pages ; i++ ) {
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 		/* we need to support large memory configurations */
 		entry->busaddr[i] = pci_map_single(dev->pdev,
 					   page_address( entry->pagelist[i] ),
@@ -139,7 +147,9 @@
 			goto done;
 		}
 		page_base = (u32) entry->busaddr[i];
-
+#else
+		page_base = page_to_bus( entry->pagelist[i] );
+#endif
 		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 			*pci_gart++ = cpu_to_le32( page_base );
 			page_base += ATI_PCIGART_PAGE_SIZE;
@@ -164,6 +174,7 @@
 			      unsigned long addr,
 			      dma_addr_t bus_addr)
 {
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 	drm_sg_mem_t *entry = dev->sg;
 	unsigned long pages;
 	int i;
@@ -188,6 +199,8 @@
 					 PAGE_SIZE, PCI_DMA_TODEVICE);
 		}
 	}
+
+#endif
 
 	if ( addr ) {
 		DRM(ati_free_pcigart_table)( addr );
diff -urN linux-2.4.16/drivers/char/drm/drmP.h lia64-2.4/drivers/char/drm/drmP.h
--- linux-2.4.16/drivers/char/drm/drmP.h	Mon Nov  5 18:28:46 2001
+++ lia64-2.4/drivers/char/drm/drmP.h	Mon Nov  5 18:34:14 2001
@@ -366,13 +366,13 @@
    if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; }
 
 				/* Mapping helper macros */
-#define DRM_IOREMAP(map)						\
-	(map)->handle = DRM(ioremap)( (map)->offset, (map)->size )
+#define DRM_IOREMAP(map, dev)						\
+	(map)->handle = DRM(ioremap)( (map)->offset, (map)->size, (dev) )
 
-#define DRM_IOREMAPFREE(map)						\
+#define DRM_IOREMAPFREE(map, dev)						\
 	do {								\
 		if ( (map)->handle && (map)->size )			\
-			DRM(ioremapfree)( (map)->handle, (map)->size );	\
+			DRM(ioremapfree)( (map)->handle, (map)->size, (dev) );	\
 	} while (0)
 
 #define DRM_FIND_MAP(_map, _o)						\
@@ -826,8 +826,8 @@
 extern unsigned long DRM(alloc_pages)(int order, int area);
 extern void	     DRM(free_pages)(unsigned long address, int order,
 				     int area);
-extern void	     *DRM(ioremap)(unsigned long offset, unsigned long size);
-extern void	     DRM(ioremapfree)(void *pt, unsigned long size);
+extern void	     *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev);
+extern void	     DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev);
 
 #if __REALLY_HAVE_AGP
 extern agp_memory    *DRM(alloc_agp)(int pages, u32 type);
diff -urN linux-2.4.16/drivers/char/drm/drm_agpsupport.h lia64-2.4/drivers/char/drm/drm_agpsupport.h
--- linux-2.4.16/drivers/char/drm/drm_agpsupport.h	Mon Nov 26 11:18:32 2001
+++ lia64-2.4/drivers/char/drm/drm_agpsupport.h	Mon Nov 26 11:21:28 2001
@@ -277,6 +277,7 @@
 		case INTEL_I840:	head->chipset = "Intel i840";    break;
 		case INTEL_I845:	head->chipset = "Intel i845";    break;
 		case INTEL_I850:	head->chipset = "Intel i850";	 break;
+		case INTEL_460GX:	head->chipset = "Intel 460GX";	 break;
 #endif
 
 		case VIA_GENERIC:	head->chipset = "VIA";           break;
diff -urN linux-2.4.16/drivers/char/drm/drm_bufs.h lia64-2.4/drivers/char/drm/drm_bufs.h
--- linux-2.4.16/drivers/char/drm/drm_bufs.h	Fri Aug 10 18:14:41 2001
+++ lia64-2.4/drivers/char/drm/drm_bufs.h	Mon Aug 20 18:09:30 2001
@@ -107,7 +107,7 @@
 	switch ( map->type ) {
 	case _DRM_REGISTERS:
 	case _DRM_FRAME_BUFFER:
-#if !defined(__sparc__) && !defined(__alpha__)
+#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__)
 		if ( map->offset + map->size < map->offset ||
 		     map->offset < virt_to_phys(high_memory) ) {
 			DRM(free)( map, sizeof(*map), DRM_MEM_MAPS );
@@ -124,7 +124,7 @@
 					      MTRR_TYPE_WRCOMB, 1 );
 		}
 #endif
-		map->handle = DRM(ioremap)( map->offset, map->size );
+		map->handle = DRM(ioremap)( map->offset, map->size, dev );
 		break;
 
 	case _DRM_SHM:
@@ -249,7 +249,7 @@
 				DRM_DEBUG("mtrr_del = %d\n", retcode);
 			}
 #endif
-			DRM(ioremapfree)(map->handle, map->size);
+			DRM(ioremapfree)(map->handle, map->size, dev);
 			break;
 		case _DRM_SHM:
 			vfree(map->handle);
diff -urN linux-2.4.16/drivers/char/drm/drm_drv.h lia64-2.4/drivers/char/drm/drm_drv.h
--- linux-2.4.16/drivers/char/drm/drm_drv.h	Wed Oct 24 10:17:46 2001
+++ lia64-2.4/drivers/char/drm/drm_drv.h	Wed Oct 24 10:24:23 2001
@@ -439,7 +439,7 @@
 					DRM_DEBUG( "mtrr_del=%d\n", retcode );
 				}
 #endif
-				DRM(ioremapfree)( map->handle, map->size );
+				DRM(ioremapfree)( map->handle, map->size, dev );
 				break;
 			case _DRM_SHM:
 				vfree(map->handle);
diff -urN linux-2.4.16/drivers/char/drm/drm_memory.h lia64-2.4/drivers/char/drm/drm_memory.h
--- linux-2.4.16/drivers/char/drm/drm_memory.h	Fri Aug 10 18:14:41 2001
+++ lia64-2.4/drivers/char/drm/drm_memory.h	Wed Aug 22 11:05:01 2001
@@ -306,9 +306,14 @@
 	}
 }
 
-void *DRM(ioremap)(unsigned long offset, unsigned long size)
+void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev)
 {
 	void *pt;
+#if __REALLY_HAVE_AGP
+	drm_map_t *map = NULL;
+	drm_map_list_t *r_list;
+	struct list_head *list;
+#endif
 
 	if (!size) {
 		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
@@ -316,12 +321,51 @@
 		return NULL;
 	}
 
+#if __REALLY_HAVE_AGP
+	if(dev->agp->cant_use_aperture == 0)
+		goto standard_ioremap;
+
+	list_for_each(list, &dev->maplist->head) {
+		r_list = (drm_map_list_t *)list;
+		map = r_list->map;
+		if (!map) continue;
+		if (map->offset <= offset &&
+			(map->offset + map->size) >= (offset + size))
+			break;
+	}
+	
+	if(map && map->type == _DRM_AGP) {
+		struct drm_agp_mem *agpmem;
+
+		for(agpmem = dev->agp->memory; agpmem;
+					agpmem = agpmem->next) {
+			if(agpmem->bound <= offset &&
+			   (agpmem->bound + (agpmem->pages
+				<< PAGE_SHIFT)) >= (offset + size))
+				break;
+		}
+
+		if(agpmem == NULL)
+			goto ioremap_failure;
+
+		pt = agpmem->memory->vmptr + (offset - agpmem->bound);
+		goto ioremap_success;
+	}
+
+standard_ioremap:
+#endif
 	if (!(pt = ioremap(offset, size))) {
+#if __REALLY_HAVE_AGP
+ioremap_failure:
+#endif
 		spin_lock(&DRM(mem_lock));
 		++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count;
 		spin_unlock(&DRM(mem_lock));
 		return NULL;
 	}
+#if __REALLY_HAVE_AGP
+ioremap_success:
+#endif
 	spin_lock(&DRM(mem_lock));
 	++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
 	DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size;
@@ -329,7 +373,7 @@
 	return pt;
 }
 
-void DRM(ioremapfree)(void *pt, unsigned long size)
+void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev)
 {
 	int alloc_count;
 	int free_count;
@@ -337,7 +381,11 @@
 	if (!pt)
 		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
 			      "Attempt to free NULL pointer\n");
+#if __REALLY_HAVE_AGP
+	else if(dev->agp->cant_use_aperture == 0)
+#else
 	else
+#endif
 		iounmap(pt);
 
 	spin_lock(&DRM(mem_lock));
diff -urN linux-2.4.16/drivers/char/drm/drm_scatter.h lia64-2.4/drivers/char/drm/drm_scatter.h
--- linux-2.4.16/drivers/char/drm/drm_scatter.h	Mon Sep 24 15:06:58 2001
+++ lia64-2.4/drivers/char/drm/drm_scatter.h	Mon Sep 24 15:25:55 2001
@@ -47,9 +47,11 @@
 
 	vfree( entry->virtual );
 
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 	DRM(free)( entry->busaddr,
 		   entry->pages * sizeof(*entry->busaddr),
 		   DRM_MEM_PAGES );
+#endif
 	DRM(free)( entry->pagelist,
 		   entry->pages * sizeof(*entry->pagelist),
 		   DRM_MEM_PAGES );
@@ -97,6 +99,7 @@
 		return -ENOMEM;
 	}
 
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 	entry->busaddr = DRM(alloc)( pages * sizeof(*entry->busaddr),
 				     DRM_MEM_PAGES );
 	if ( !entry->busaddr ) {
@@ -109,12 +112,15 @@
 		return -ENOMEM;
 	}
 	memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) );
+#endif
 
 	entry->virtual = vmalloc_32( pages << PAGE_SHIFT );
 	if ( !entry->virtual ) {
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 		DRM(free)( entry->busaddr,
 			   entry->pages * sizeof(*entry->busaddr),
 			   DRM_MEM_PAGES );
+#endif
 		DRM(free)( entry->pagelist,
 			   entry->pages * sizeof(*entry->pagelist),
 			   DRM_MEM_PAGES );
diff -urN linux-2.4.16/drivers/char/drm/drm_vm.h lia64-2.4/drivers/char/drm/drm_vm.h
--- linux-2.4.16/drivers/char/drm/drm_vm.h	Mon Nov 26 11:18:32 2001
+++ lia64-2.4/drivers/char/drm/drm_vm.h	Mon Nov 26 11:33:07 2001
@@ -89,7 +89,7 @@
 
 	if (map && map->type == _DRM_AGP) {
 		unsigned long offset = address - vma->vm_start;
-		unsigned long baddr = VM_OFFSET(vma) + offset;
+		unsigned long baddr = VM_OFFSET(vma) + offset, paddr;
 		struct drm_agp_mem *agpmem;
 		struct page *page;
 
@@ -115,8 +115,19 @@
                  * Get the page, inc the use count, and return it
                  */
 		offset = (baddr - agpmem->bound) >> PAGE_SHIFT;
-		agpmem->memory->memory[offset] &= dev->agp->page_mask;
-		page = virt_to_page(__va(agpmem->memory->memory[offset]));
+
+		/*
+		 * This is bad.  What we really want to do here is unmask
+		 * the GART table entry held in the agp_memory structure.
+		 * There isn't a convenient way to call agp_bridge.unmask_
+		 * memory from here, so hard code it for now.
+		 */
+#if defined(__ia64__)
+		paddr = (agpmem->memory->memory[offset] & 0xffffff) << 12;
+#else
+		paddr = agpmem->memory->memory[offset] & dev->agp->page_mask;
+#endif
+		page = virt_to_page(__va(paddr));
 		get_page(page);
 
 		DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx\n",
@@ -255,7 +266,7 @@
 					DRM_DEBUG("mtrr_del = %d\n", retcode);
 				}
 #endif
-				DRM(ioremapfree)(map->handle, map->size);
+				DRM(ioremapfree)(map->handle, map->size, dev);
 				break;
 			case _DRM_SHM:
 				vfree(map->handle);
@@ -502,15 +513,21 @@
 
 	switch (map->type) {
         case _DRM_AGP:
-#if defined(__alpha__)
-                /*
-                 * On Alpha we can't talk to bus dma address from the
-                 * CPU, so for memory of type DRM_AGP, we'll deal with
-                 * sorting out the real physical pages and mappings
-                 * in nopage()
-                 */
-                vma->vm_ops = &DRM(vm_ops);
-                break;
+#if __REALLY_HAVE_AGP
+		if(dev->agp->cant_use_aperture == 1) {
+                	/*
+                	 * On some systems we can't talk to bus dma address from
+                	 * the CPU, so for memory of type DRM_AGP, we'll deal
+                	 * with sorting out the real physical pages and mappings
+                	 * in nopage()
+                	 */
+                	vma->vm_ops = &DRM(vm_ops);
+#if defined(__ia64__)
+			vma->vm_page_prot =
+			                pgprot_writecombine(vma->vm_page_prot);
+#endif
+			goto mapswitch_out;
+		}
 #endif
                 /* fall through to _DRM_FRAME_BUFFER... */        
 	case _DRM_FRAME_BUFFER:
@@ -522,8 +539,7 @@
 				pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT;
 			}
 #elif defined(__ia64__)
-			if (map->type != _DRM_AGP)
-				vma->vm_page_prot =
+			vma->vm_page_prot =
 					pgprot_writecombine(vma->vm_page_prot);
 #elif defined(__powerpc__)
 			pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE | _PAGE_GUARDED;
@@ -567,11 +583,14 @@
 #else
 		vma->vm_pte = (unsigned long)map;
 #endif
-                vma->vm_flags |= VM_RESERVED;
+		vma->vm_flags |= VM_RESERVED;
                 break;
 	default:
 		return -EINVAL;	/* This should never happen. */
 	}
+#if __REALLY_HAVE_AGP
+mapswitch_out:
+#endif
 	vma->vm_flags |= VM_RESERVED; /* Don't swap */
 
 #if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */
diff -urN linux-2.4.16/drivers/char/drm/i810_dma.c lia64-2.4/drivers/char/drm/i810_dma.c
--- linux-2.4.16/drivers/char/drm/i810_dma.c	Wed Aug  8 09:42:15 2001
+++ lia64-2.4/drivers/char/drm/i810_dma.c	Mon Aug 20 18:09:34 2001
@@ -315,7 +315,7 @@
 
 	   	if(dev_priv->ring.virtual_start) {
 		   	DRM(ioremapfree)((void *) dev_priv->ring.virtual_start,
-					 dev_priv->ring.Size);
+					 dev_priv->ring.Size, dev);
 		}
 	   	if(dev_priv->hw_status_page != 0UL) {
 		   	i810_free_page(dev, dev_priv->hw_status_page);
@@ -329,7 +329,8 @@
 		for (i = 0; i < dma->buf_count; i++) {
 			drm_buf_t *buf = dma->buflist[ i ];
 			drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-			DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total);
+			DRM(ioremapfree)(buf_priv->kernel_virtual,
+							buf->total, dev);
 		}
 	}
    	return 0;
@@ -402,7 +403,7 @@
 	   	*buf_priv->in_use = I810_BUF_FREE;
 
 		buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address,
-							buf->total);
+							buf->total, dev);
 	}
 	return 0;
 }
@@ -458,7 +459,7 @@
 
    	dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base +
 						    init->ring_start,
-						    init->ring_size);
+						    init->ring_size, dev);
 
    	if (dev_priv->ring.virtual_start == NULL) {
 		dev->dev_private = (void *) dev_priv;
diff -urN linux-2.4.16/drivers/char/drm/mga_dma.c lia64-2.4/drivers/char/drm/mga_dma.c
--- linux-2.4.16/drivers/char/drm/mga_dma.c	Wed Aug  8 09:42:15 2001
+++ lia64-2.4/drivers/char/drm/mga_dma.c	Mon Aug 20 18:09:34 2001
@@ -557,9 +557,9 @@
 		(drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
 				    init->sarea_priv_offset);
 
-	DRM_IOREMAP( dev_priv->warp );
-	DRM_IOREMAP( dev_priv->primary );
-	DRM_IOREMAP( dev_priv->buffers );
+	DRM_IOREMAP( dev_priv->warp, dev );
+	DRM_IOREMAP( dev_priv->primary, dev );
+	DRM_IOREMAP( dev_priv->buffers, dev );
 
 	if(!dev_priv->warp->handle ||
 	   !dev_priv->primary->handle ||
@@ -647,9 +647,9 @@
 	if ( dev->dev_private ) {
 		drm_mga_private_t *dev_priv = dev->dev_private;
 
-		DRM_IOREMAPFREE( dev_priv->warp );
-		DRM_IOREMAPFREE( dev_priv->primary );
-		DRM_IOREMAPFREE( dev_priv->buffers );
+		DRM_IOREMAPFREE( dev_priv->warp, dev );
+		DRM_IOREMAPFREE( dev_priv->primary, dev );
+		DRM_IOREMAPFREE( dev_priv->buffers, dev );
 
 		if ( dev_priv->head != NULL ) {
 			mga_freelist_cleanup( dev );
diff -urN linux-2.4.16/drivers/char/drm/r128_cce.c lia64-2.4/drivers/char/drm/r128_cce.c
--- linux-2.4.16/drivers/char/drm/r128_cce.c	Mon Sep 24 15:06:58 2001
+++ lia64-2.4/drivers/char/drm/r128_cce.c	Wed Nov 21 13:42:25 2001
@@ -216,7 +216,22 @@
 	int i;
 
 	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+#ifndef CONFIG_AGP_I460
 		if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
+#else
+		/*
+		 * XXX - this is (I think) a 460GX specific hack
+		 *
+		 * When doing texturing, ring.tail sometimes gets ahead of
+		 * PM4_BUFFER_DL_WPTR by 2; consequently, the card processes
+		 * its whole quota of instructions and *ring.head is still 2
+		 * short of ring.tail.  Work around this for now in lieu of
+		 * a better solution.
+		 */
+ 		if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ||
+			( dev_priv->ring.tail -
+				GET_RING_HEAD( &dev_priv->ring ) ) == 2 ) {
+#endif
 			int pm4stat = R128_READ( R128_PM4_STAT );
 			if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
 			       dev_priv->cce_fifo_size ) &&
@@ -317,7 +332,7 @@
 static void r128_cce_init_ring_buffer( drm_device_t *dev,
 				       drm_r128_private_t *dev_priv )
 {
-	u32 ring_start;
+	u32 ring_start, rptr_addr;
 	u32 tmp;
 
 	DRM_DEBUG( "%s\n", __FUNCTION__ );
@@ -341,8 +356,28 @@
 	SET_RING_HEAD( &dev_priv->ring, 0 );
 
 	if ( !dev_priv->is_pci ) {
-		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
-			    dev_priv->ring_rptr->offset );
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * XXX - This is a 460GX specific hack
+		 *
+		 * We have to hack this right now.  460GX isn't claiming PCI
+		 * writes from the card into the AGP aperture.  Because of this,
+		 * we have to get space outside of the aperture for RPTR_ADDR.
+		 */
+		if( dev->agp->agp_info.chipset == INTEL_460GX ) {
+			unsigned long alt_rh_off;
+
+			alt_rh_off = __get_free_page(GFP_KERNEL | GFP_DMA);
+			atomic_inc(&virt_to_page(alt_rh_off)->count);
+			set_bit(PG_locked, &virt_to_page(alt_rh_off)->flags);
+
+			dev_priv->ring.head = (__volatile__ u32 *) alt_rh_off;
+			SET_RING_HEAD( &dev_priv->ring, 0 );
+			rptr_addr = __pa( dev_priv->ring.head );
+		} else
+#endif
+			rptr_addr = dev_priv->ring_rptr->offset;
+		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, rptr_addr );
 	} else {
 		drm_sg_mem_t *entry = dev->sg;
 		unsigned long tmp_ofs, page_ofs;
@@ -350,11 +385,20 @@
 		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 		page_ofs = tmp_ofs >> PAGE_SHIFT;
 
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
      			    entry->busaddr[page_ofs]);
 		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 			   entry->busaddr[page_ofs],
      			   entry->handle + tmp_ofs );
+#else
+		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
+			    page_to_bus(entry->pagelist[page_ofs]));
+
+		DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
+			   page_to_bus(entry->pagelist[page_ofs]),
+			   entry->handle + tmp_ofs );
+#endif
 	}
 
 	/* Set watermark control */
@@ -550,9 +594,9 @@
 				     init->sarea_priv_offset);
 
 	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cce_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
+		DRM_IOREMAP( dev_priv->cce_ring, dev );
+		DRM_IOREMAP( dev_priv->ring_rptr, dev );
+		DRM_IOREMAP( dev_priv->buffers, dev );
 		if(!dev_priv->cce_ring->handle ||
 		   !dev_priv->ring_rptr->handle ||
 		   !dev_priv->buffers->handle) {
@@ -624,9 +668,9 @@
 		drm_r128_private_t *dev_priv = dev->dev_private;
 
 		if ( !dev_priv->is_pci ) {
-			DRM_IOREMAPFREE( dev_priv->cce_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
+			DRM_IOREMAPFREE( dev_priv->cce_ring, dev );
+			DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
+			DRM_IOREMAPFREE( dev_priv->buffers, dev );
 		} else {
 			if (!DRM(ati_pcigart_cleanup)( dev,
 						dev_priv->phys_pci_gart,
@@ -634,6 +678,21 @@
 				DRM_ERROR( "failed to cleanup PCI GART!\n" );
 		}
 
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * Free the page we grabbed for RPTR_ADDR
+		 */
+		if( !dev_priv->is_pci && dev->agp->agp_info.chipset == INTEL_460GX ) {
+			unsigned long alt_rh_off =
+				(unsigned long) dev_priv->ring.head;
+
+			atomic_dec(&virt_to_page(alt_rh_off)->count);
+			clear_bit(PG_locked, &virt_to_page(alt_rh_off)->flags);
+			wake_up(&virt_to_page(alt_rh_off)->wait);
+			free_page(alt_rh_off);
+		}
+#endif
+	
 		DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
 			   DRM_MEM_DRIVER );
 		dev->dev_private = NULL;
diff -urN linux-2.4.16/drivers/char/drm/radeon_cp.c lia64-2.4/drivers/char/drm/radeon_cp.c
--- linux-2.4.16/drivers/char/drm/radeon_cp.c	Mon Sep 24 15:06:58 2001
+++ lia64-2.4/drivers/char/drm/radeon_cp.c	Wed Nov 21 13:54:26 2001
@@ -575,7 +575,7 @@
 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 				        drm_radeon_private_t *dev_priv )
 {
-	u32 ring_start, cur_read_ptr;
+	u32 ring_start, cur_read_ptr, rptr_addr;
 	u32 tmp;
 
 	/* Initialize the memory controller */
@@ -612,8 +612,28 @@
 	dev_priv->ring.tail = cur_read_ptr;
 
 	if ( !dev_priv->is_pci ) {
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			      dev_priv->ring_rptr->offset );
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * XXX - This is a 460GX specific hack
+		 *
+		 * We have to hack this right now.  460GX isn't claiming PCI
+		 * writes from the card into the AGP aperture.  Because of this,
+		 * we have to get space outside of the aperture for RPTR_ADDR.
+		 */
+		if( dev->agp->agp_info.chipset == INTEL_460GX ) {
+			unsigned long alt_rh_off;
+
+			alt_rh_off = __get_free_page(GFP_KERNEL | GFP_DMA);
+			atomic_inc(&virt_to_page(alt_rh_off)->count);
+			set_bit(PG_locked, &virt_to_page(alt_rh_off)->flags);
+
+			dev_priv->ring.head = (__volatile__ u32 *) alt_rh_off;
+			*dev_priv->ring.head = cur_read_ptr;
+			rptr_addr = __pa( dev_priv->ring.head );
+		} else
+#endif
+			rptr_addr = dev_priv->ring_rptr->offset;
+		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, rptr_addr );
 	} else {
 		drm_sg_mem_t *entry = dev->sg;
 		unsigned long tmp_ofs, page_ofs;
@@ -621,11 +641,19 @@
 		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 		page_ofs = tmp_ofs >> PAGE_SHIFT;
 
+#if defined(__alpha__) && (LINUX_VERSION_CODE >= 0x020400)
 		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 			     entry->busaddr[page_ofs]);
 		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 			   entry->busaddr[page_ofs],
 			   entry->handle + tmp_ofs );
+#else
+		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
+			     entry->busaddr[page_ofs]);
+		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
+			   entry->busaddr[page_ofs],
+			   entry->handle + tmp_ofs );
+#endif
 	}
 
 	/* Set ring buffer size */
@@ -836,9 +864,9 @@
 				       init->sarea_priv_offset);
 
 	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cp_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
+		DRM_IOREMAP( dev_priv->cp_ring, dev );
+		DRM_IOREMAP( dev_priv->ring_rptr, dev );
+		DRM_IOREMAP( dev_priv->buffers, dev );
 		if(!dev_priv->cp_ring->handle ||
 		   !dev_priv->ring_rptr->handle ||
 		   !dev_priv->buffers->handle) {
@@ -983,9 +1011,9 @@
 		drm_radeon_private_t *dev_priv = dev->dev_private;
 
 		if ( !dev_priv->is_pci ) {
-			DRM_IOREMAPFREE( dev_priv->cp_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
+			DRM_IOREMAPFREE( dev_priv->cp_ring, dev );
+			DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
+			DRM_IOREMAPFREE( dev_priv->buffers, dev );
 		} else {
 			if (!DRM(ati_pcigart_cleanup)( dev,
 						dev_priv->phys_pci_gart,
@@ -993,6 +1021,21 @@
 				DRM_ERROR( "failed to cleanup PCI GART!\n" );
 		}
 
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * Free the page we grabbed for RPTR_ADDR
+		 */
+		if( !dev_priv->is_pci && dev->agp->agp_info.chipset == INTEL_460GX ) {
+			unsigned long alt_rh_off =
+				(unsigned long) dev_priv->ring.head;
+
+			atomic_dec(&virt_to_page(alt_rh_off)->count);
+			clear_bit(PG_locked, &virt_to_page(alt_rh_off)->flags);
+			wake_up(&virt_to_page(alt_rh_off)->wait);
+			free_page(alt_rh_off);
+		}
+#endif
+	
 		DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
 			   DRM_MEM_DRIVER );
 		dev->dev_private = NULL;
diff -urN linux-2.4.16/drivers/char/drm-4.0/Config.in lia64-2.4/drivers/char/drm-4.0/Config.in
--- linux-2.4.16/drivers/char/drm-4.0/Config.in	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/Config.in	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,13 @@
+#
+# drm device configuration
+#
+# This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.x.
+#
+
+tristate '  3dfx Banshee/Voodoo3+' CONFIG_DRM40_TDFX
+tristate '  3dlabs GMX 2000' CONFIG_DRM40_GAMMA
+dep_tristate '  ATI Rage 128' CONFIG_DRM40_R128 $CONFIG_AGP
+dep_tristate '  ATI Radeon' CONFIG_DRM40_RADEON $CONFIG_AGP
+dep_tristate '  Intel I810' CONFIG_DRM40_I810 $CONFIG_AGP
+dep_tristate '  Matrox g200/g400' CONFIG_DRM40_MGA $CONFIG_AGP
diff -urN linux-2.4.16/drivers/char/drm-4.0/Makefile lia64-2.4/drivers/char/drm-4.0/Makefile
--- linux-2.4.16/drivers/char/drm-4.0/Makefile	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/Makefile	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,104 @@
+#
+# Makefile for the drm device driver.  This driver provides support for
+# the Direct Rendering Infrastructure (DRI) in XFree86 4.x.
+#
+
+O_TARGET	:= drm.o
+
+export-objs     := gamma_drv.o tdfx_drv.o r128_drv.o ffb_drv.o mga_drv.o \
+		   i810_drv.o
+
+# lib-objs are included in every module so that radical changes to the
+# architecture of the DRM support library can be made at a later time.
+#
+# The downside is that each module is larger, and a system that uses
+# more than one module (i.e., a dual-head system) will use more memory
+# (but a system that uses exactly one module will use the same amount of
+# memory).
+#
+# The upside is that if the DRM support library ever becomes insufficient
+# for new families of cards, a new library can be implemented for those new
+# cards without impacting the drivers for the old cards.  This is significant,
+# because testing architectural changes to old cards may be impossible, and
+# may delay the implementation of a better architecture.  We've traded slight
+# memory waste (in the dual-head case) for greatly improved long-term
+# maintainability.
+#
+# NOTE: lib-objs will be eliminated in future versions, thereby
+# eliminating the need to compile the .o files into every module, but
+# for now we still need them.
+#
+
+lib-objs   := init.o memory.o proc.o auth.o context.o drawable.o bufs.o
+lib-objs   += lists.o lock.o ioctl.o fops.o vm.o dma.o ctxbitmap.o
+
+ifeq ($(CONFIG_AGP),y)
+ lib-objs  += agpsupport.o
+else
+ ifeq ($(CONFIG_AGP),m)
+  lib-objs  += agpsupport.o
+ endif
+endif
+
+list-multi  := gamma.o tdfx.o r128.o ffb.o mga.o i810.o
+gamma-objs  := gamma_drv.o  gamma_dma.o
+tdfx-objs   := tdfx_drv.o                 tdfx_context.o
+r128-objs   := r128_drv.o   r128_cce.o    r128_context.o r128_bufs.o r128_state.o
+ffb-objs    := ffb_drv.o                  ffb_context.o
+mga-objs    := mga_drv.o    mga_dma.o     mga_context.o  mga_bufs.o  mga_state.o
+i810-objs   := i810_drv.o   i810_dma.o    i810_context.o i810_bufs.o
+radeon-objs := radeon_drv.o radeon_cp.o   radeon_context.o radeon_bufs.o radeon_state.o
+
+obj-$(CONFIG_DRM40_GAMMA) += gamma.o
+obj-$(CONFIG_DRM40_TDFX)  += tdfx.o
+obj-$(CONFIG_DRM40_R128)  += r128.o
+obj-$(CONFIG_DRM40_RADEON)+= radeon.o
+obj-$(CONFIG_DRM40_FFB)   += ffb.o
+obj-$(CONFIG_DRM40_MGA)   += mga.o
+obj-$(CONFIG_DRM40_I810)  += i810.o
+
+
+# When linking into the kernel, link the library just once. 
+# If making modules, we include the library into each module
+
+lib-objs-mod := $(patsubst %.o,%-mod.o,$(lib-objs))
+
+ifdef MAKING_MODULES
+  lib = drmlib-mod.a
+else
+  obj-y += drmlib.a
+endif
+
+include $(TOPDIR)/Rules.make
+
+$(patsubst %.o,%.c,$(lib-objs-mod)): 
+	@ln -sf $(subst -mod,,$@) $@
+
+drmlib-mod.a: $(lib-objs-mod)
+	rm -f $@
+	$(AR) $(EXTRA_ARFLAGS) rcs $@ $(lib-objs-mod)
+
+drmlib.a: $(lib-objs)
+	rm -f $@
+	$(AR) $(EXTRA_ARFLAGS) rcs $@ $(lib-objs)
+
+gamma.o: $(gamma-objs) $(lib)
+	$(LD) -r -o $@ $(gamma-objs) $(lib)
+
+tdfx.o: $(tdfx-objs) $(lib)
+	$(LD) -r -o $@ $(tdfx-objs) $(lib)
+
+mga.o: $(mga-objs) $(lib)
+	$(LD) -r -o $@ $(mga-objs) $(lib)
+
+i810.o: $(i810-objs) $(lib)
+	$(LD) -r -o $@ $(i810-objs) $(lib)
+
+r128.o: $(r128-objs) $(lib)
+	$(LD) -r -o $@ $(r128-objs) $(lib)
+
+radeon.o: $(radeon-objs) $(lib)
+	$(LD) -r -o $@ $(radeon-objs) $(lib)
+
+ffb.o: $(ffb-objs) $(lib)
+	$(LD) -r -o $@ $(ffb-objs) $(lib)
diff -urN linux-2.4.16/drivers/char/drm-4.0/README.drm lia64-2.4/drivers/char/drm-4.0/README.drm
--- linux-2.4.16/drivers/char/drm-4.0/README.drm	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/README.drm	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,46 @@
+************************************************************
+* For the very latest on DRI development, please see:      *
+*     http://dri.sourceforge.net/                          *
+************************************************************
+
+The Direct Rendering Manager (drm) is a device-independent kernel-level
+device driver that provides support for the XFree86 Direct Rendering
+Infrastructure (DRI).
+
+The DRM supports the Direct Rendering Infrastructure (DRI) in four major
+ways:
+
+    1. The DRM provides synchronized access to the graphics hardware via
+       the use of an optimized two-tiered lock.
+
+    2. The DRM enforces the DRI security policy for access to the graphics
+       hardware by only allowing authenticated X11 clients access to
+       restricted regions of memory.
+
+    3. The DRM provides a generic DMA engine, complete with multiple
+       queues and the ability to detect the need for an OpenGL context
+       switch.
+
+    4. The DRM is extensible via the use of small device-specific modules
+       that rely extensively on the API exported by the DRM module.
+
+
+Documentation on the DRI is available from:
+    http://precisioninsight.com/piinsights.html
+
+For specific information about kernel-level support, see:
+
+    The Direct Rendering Manager, Kernel Support for the Direct Rendering
+    Infrastructure
+    http://precisioninsight.com/dr/drm.html
+
+    Hardware Locking for the Direct Rendering Infrastructure
+    http://precisioninsight.com/dr/locking.html
+
+    A Security Analysis of the Direct Rendering Infrastructure
+    http://precisioninsight.com/dr/security.html
+
+************************************************************
+* For the very latest on DRI development, please see:      *
+*     http://dri.sourceforge.net/                          *
+************************************************************
diff -urN linux-2.4.16/drivers/char/drm-4.0/agpsupport.c lia64-2.4/drivers/char/drm-4.0/agpsupport.c
--- linux-2.4.16/drivers/char/drm-4.0/agpsupport.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/agpsupport.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,349 @@
+/* agpsupport.c -- DRM support for AGP/GART backend -*- linux-c -*-
+ * Created: Mon Dec 13 09:56:45 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include <linux/config.h>
+#include <linux/module.h>
+#if LINUX_VERSION_CODE < 0x020400
+#include "agpsupport-pre24.h"
+#else
+#define DRM_AGP_GET (drm_agp_t *)inter_module_get("drm_agp")
+#define DRM_AGP_PUT inter_module_put("drm_agp")
+#endif
+
+static const drm_agp_t *drm_agp = NULL;
+
+int drm_agp_info(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	agp_kern_info    *kern;
+	drm_agp_info_t   info;
+
+	if (!dev->agp->acquired || !drm_agp->copy_info) return -EINVAL;
+
+	kern                   = &dev->agp->agp_info;
+	info.agp_version_major = kern->version.major;
+	info.agp_version_minor = kern->version.minor;
+	info.mode              = kern->mode;
+	info.aperture_base     = kern->aper_base;
+	info.aperture_size     = kern->aper_size * 1024 * 1024;
+	info.memory_allowed    = kern->max_memory << PAGE_SHIFT;
+	info.memory_used       = kern->current_memory << PAGE_SHIFT;
+	info.id_vendor         = kern->device->vendor;
+	info.id_device         = kern->device->device;
+
+	if (copy_to_user((drm_agp_info_t *)arg, &info, sizeof(info)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_agp_acquire(struct inode *inode, struct file *filp, unsigned int cmd,
+		    unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int              retcode;
+
+	if (dev->agp->acquired || !drm_agp->acquire) return -EINVAL;
+	if ((retcode = drm_agp->acquire())) return retcode;
+	dev->agp->acquired = 1;
+	return 0;
+}
+
+int drm_agp_release(struct inode *inode, struct file *filp, unsigned int cmd,
+		    unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+
+	if (!dev->agp->acquired || !drm_agp->release) return -EINVAL;
+	drm_agp->release();
+	dev->agp->acquired = 0;
+	return 0;
+	
+}
+
+void _drm_agp_release(void)
+{
+	if (drm_agp->release) drm_agp->release();
+}
+
+int drm_agp_enable(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_agp_mode_t   mode;
+
+	if (!dev->agp->acquired || !drm_agp->enable) return -EINVAL;
+
+	if (copy_from_user(&mode, (drm_agp_mode_t *)arg, sizeof(mode)))
+		return -EFAULT;
+	
+	dev->agp->mode    = mode.mode;
+	drm_agp->enable(mode.mode);
+	dev->agp->base    = dev->agp->agp_info.aper_base;
+	dev->agp->enabled = 1;
+	return 0;
+}
+
+int drm_agp_alloc(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_agp_buffer_t request;
+	drm_agp_mem_t    *entry;
+	agp_memory       *memory;
+	unsigned long    pages;
+	u32 		 type;
+	if (!dev->agp->acquired) return -EINVAL;
+	if (copy_from_user(&request, (drm_agp_buffer_t *)arg, sizeof(request)))
+		return -EFAULT;
+	if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS)))
+		return -ENOMEM;
+   
+   	memset(entry, 0, sizeof(*entry));
+
+	pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE;
+	type = (u32) request.type;
+
+	if (!(memory = drm_alloc_agp(pages, type))) {
+		drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		return -ENOMEM;
+	}
+	
+	entry->handle    = (unsigned long)memory->memory;
+	entry->memory    = memory;
+	entry->bound     = 0;
+	entry->pages     = pages;
+	entry->prev      = NULL;
+	entry->next      = dev->agp->memory;
+	if (dev->agp->memory) dev->agp->memory->prev = entry;
+	dev->agp->memory = entry;
+
+	request.handle   = entry->handle;
+        request.physical = memory->physical;
+
+	if (copy_to_user((drm_agp_buffer_t *)arg, &request, sizeof(request))) {
+		dev->agp->memory       = entry->next;
+		dev->agp->memory->prev = NULL;
+		drm_free_agp(memory, pages);
+		drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		return -EFAULT;
+	}
+	return 0;
+}
+
+static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev,
+					   unsigned long handle)
+{
+	drm_agp_mem_t *entry;
+
+	for (entry = dev->agp->memory; entry; entry = entry->next) {
+		if (entry->handle == handle) return entry;
+	}
+	return NULL;
+}
+
+int drm_agp_unbind(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	  *priv	 = filp->private_data;
+	drm_device_t	  *dev	 = priv->dev;
+	drm_agp_binding_t request;
+	drm_agp_mem_t     *entry;
+
+	if (!dev->agp->acquired) return -EINVAL;
+	if (copy_from_user(&request, (drm_agp_binding_t *)arg, sizeof(request)))
+		return -EFAULT;
+	if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
+		return -EINVAL;
+	if (!entry->bound) return -EINVAL;
+	return drm_unbind_agp(entry->memory);
+}
+
+int drm_agp_bind(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	  *priv	 = filp->private_data;
+	drm_device_t	  *dev	 = priv->dev;
+	drm_agp_binding_t request;
+	drm_agp_mem_t     *entry;
+	int               retcode;
+	int               page;
+	
+	if (!dev->agp->acquired || !drm_agp->bind_memory) return -EINVAL;
+	if (copy_from_user(&request, (drm_agp_binding_t *)arg, sizeof(request)))
+		return -EFAULT;
+	if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
+		return -EINVAL;
+	if (entry->bound) return -EINVAL;
+	page = (request.offset + PAGE_SIZE - 1) / PAGE_SIZE;
+	if ((retcode = drm_bind_agp(entry->memory, page))) return retcode;
+	entry->bound = dev->agp->base + (page << PAGE_SHIFT);
+	DRM_DEBUG("base = 0x%lx entry->bound = 0x%lx\n", 
+		  dev->agp->base, entry->bound);
+	return 0;
+}
+
+int drm_agp_free(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_agp_buffer_t request;
+	drm_agp_mem_t    *entry;
+	
+	if (!dev->agp->acquired) return -EINVAL;
+	if (copy_from_user(&request, (drm_agp_buffer_t *)arg, sizeof(request)))
+		return -EFAULT;
+	if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
+		return -EINVAL;
+	if (entry->bound) drm_unbind_agp(entry->memory);
+   
+	if (entry->prev) entry->prev->next = entry->next;
+	else             dev->agp->memory  = entry->next;
+	if (entry->next) entry->next->prev = entry->prev;
+	drm_free_agp(entry->memory, entry->pages);
+	drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+	return 0;
+}
+
+drm_agp_head_t *drm_agp_init(void)
+{
+	drm_agp_head_t *head         = NULL;
+
+	drm_agp = DRM_AGP_GET;
+	if (drm_agp) {
+		if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS)))
+			return NULL;
+		memset((void *)head, 0, sizeof(*head));
+		drm_agp->copy_info(&head->agp_info);
+		if (head->agp_info.chipset == NOT_SUPPORTED) {
+			drm_free(head, sizeof(*head), DRM_MEM_AGPLISTS);
+			return NULL;
+		}
+		head->memory = NULL;
+		switch (head->agp_info.chipset) {
+		case INTEL_GENERIC:	head->chipset = "Intel";         break;
+		case INTEL_LX:		head->chipset = "Intel 440LX";   break;
+		case INTEL_BX:		head->chipset = "Intel 440BX";   break;
+		case INTEL_GX:		head->chipset = "Intel 440GX";   break;
+		case INTEL_I810:	head->chipset = "Intel i810";    break;
+
+#if LINUX_VERSION_CODE >= 0x020400
+		case INTEL_I840:	head->chipset = "Intel i840";    break;
+#endif
+		case INTEL_460GX:	head->chipset = "Intel 460GX";	 break;
+
+		case VIA_GENERIC:	head->chipset = "VIA";           break;
+		case VIA_VP3:		head->chipset = "VIA VP3";       break;
+		case VIA_MVP3:		head->chipset = "VIA MVP3";      break;
+
+#if LINUX_VERSION_CODE >= 0x020400
+		case VIA_MVP4:		head->chipset = "VIA MVP4";      break;
+		case VIA_APOLLO_KX133:	head->chipset = "VIA Apollo KX133"; 
+			break;
+		case VIA_APOLLO_KT133:	head->chipset = "VIA Apollo KT133"; 
+			break;
+#endif
+
+		case VIA_APOLLO_PRO: 	head->chipset = "VIA Apollo Pro";
+			break;
+		case SIS_GENERIC:	head->chipset = "SiS";           break;
+		case AMD_GENERIC:	head->chipset = "AMD";           break;
+		case AMD_IRONGATE:	head->chipset = "AMD Irongate";  break;
+		case ALI_GENERIC:	head->chipset = "ALi";           break;
+		case ALI_M1541: 	head->chipset = "ALi M1541";     break;
+		case ALI_M1621: 	head->chipset = "ALi M1621";	 break;
+		case ALI_M1631: 	head->chipset = "ALi M1631";	 break;
+		case ALI_M1632: 	head->chipset = "ALi M1632";	 break;
+		case ALI_M1641: 	head->chipset = "ALi M1641";	 break;
+		case ALI_M1647: 	head->chipset = "ALi M1647";	 break;
+		case ALI_M1651: 	head->chipset = "ALi M1651";	 break;
+		case SVWRKS_GENERIC:	head->chipset = "Serverworks Generic";
+			break;
+		case SVWRKS_HE: 	head->chipset = "Serverworks HE"; break;
+		case SVWRKS_LE: 	head->chipset = "Serverworks LE"; break;
+
+		default:		head->chipset = "Unknown";       break;
+		}
+#if LINUX_VERSION_CODE <= 0x020408
+		head->cant_use_aperture = 0;
+		head->page_mask = ~(0xfff);
+#else
+		head->cant_use_aperture = head->agp_info.cant_use_aperture;
+		head->page_mask = head->agp_info.page_mask;
+#endif
+
+		DRM_INFO("AGP %d.%d on %s @ 0x%08lx %ZuMB\n",
+			 head->agp_info.version.major,
+			 head->agp_info.version.minor,
+			 head->chipset,
+			 head->agp_info.aper_base,
+			 head->agp_info.aper_size);
+	}
+	return head;
+}
+
+void drm_agp_uninit(void)
+{
+	DRM_AGP_PUT;
+	drm_agp = NULL;
+}
+
+agp_memory *drm_agp_allocate_memory(size_t pages, u32 type)
+{
+	if (!drm_agp->allocate_memory) return NULL;
+	return drm_agp->allocate_memory(pages, type);
+}
+
+int drm_agp_free_memory(agp_memory *handle)
+{
+	if (!handle || !drm_agp->free_memory) return 0;
+	drm_agp->free_memory(handle);
+	return 1;
+}
+
+int drm_agp_bind_memory(agp_memory *handle, off_t start)
+{
+	if (!handle || !drm_agp->bind_memory) return -EINVAL;
+	return drm_agp->bind_memory(handle, start);
+}
+
+int drm_agp_unbind_memory(agp_memory *handle)
+{
+	if (!handle || !drm_agp->unbind_memory) return -EINVAL;
+	return drm_agp->unbind_memory(handle);
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/auth.c lia64-2.4/drivers/char/drm-4.0/auth.c
--- linux-2.4.16/drivers/char/drm-4.0/auth.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/auth.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,162 @@
+/* auth.c -- IOCTLs for authentication -*- linux-c -*-
+ * Created: Tue Feb  2 08:37:54 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+static int drm_hash_magic(drm_magic_t magic)
+{
+	return magic & (DRM_HASH_SIZE-1);
+}
+
+static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
+{
+	drm_file_t	  *retval = NULL;
+	drm_magic_entry_t *pt;
+	int		  hash	  = drm_hash_magic(magic);
+
+	down(&dev->struct_sem);
+	for (pt = dev->magiclist[hash].head; pt; pt = pt->next) {
+		if (pt->magic == magic) {
+			retval = pt->priv;
+			break;
+		}
+	}
+	up(&dev->struct_sem);
+	return retval;
+}
+
+int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
+{
+	int		  hash;
+	drm_magic_entry_t *entry;
+	
+	DRM_DEBUG("%d\n", magic);
+	
+	hash	     = drm_hash_magic(magic);
+	entry	     = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC);
+	if (!entry) return -ENOMEM;
+	entry->magic = magic;
+	entry->priv  = priv;
+	entry->next  = NULL;
+
+	down(&dev->struct_sem);
+	if (dev->magiclist[hash].tail) {
+		dev->magiclist[hash].tail->next = entry;
+		dev->magiclist[hash].tail	= entry;
+	} else {
+		dev->magiclist[hash].head	= entry;
+		dev->magiclist[hash].tail	= entry;
+	}
+	up(&dev->struct_sem);
+	
+	return 0;
+}
+
+int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
+{
+	drm_magic_entry_t *prev = NULL;
+	drm_magic_entry_t *pt;
+	int		  hash;
+	
+	DRM_DEBUG("%d\n", magic);
+	hash = drm_hash_magic(magic);
+	
+	down(&dev->struct_sem);
+	for (pt = dev->magiclist[hash].head; pt; prev = pt, pt = pt->next) {
+		if (pt->magic == magic) {
+			if (dev->magiclist[hash].head == pt) {
+				dev->magiclist[hash].head = pt->next;
+			}
+			if (dev->magiclist[hash].tail == pt) {
+				dev->magiclist[hash].tail = prev;
+			}
+			if (prev) {
+				prev->next = pt->next;
+			}
+			up(&dev->struct_sem);
+			return 0;
+		}
+	}
+	up(&dev->struct_sem);
+
+	drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+	
+	return -EINVAL;
+}
+
+int drm_getmagic(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	static drm_magic_t sequence = 0;
+	static spinlock_t  lock	    = SPIN_LOCK_UNLOCKED;
+	drm_file_t	   *priv    = filp->private_data;
+	drm_device_t	   *dev	    = priv->dev;
+	drm_auth_t	   auth;
+
+				/* Find unique magic */
+	if (priv->magic) {
+		auth.magic = priv->magic;
+	} else {
+		do {
+			spin_lock(&lock);
+			if (!sequence) ++sequence; /* reserve 0 */
+			auth.magic = sequence++;
+			spin_unlock(&lock);
+		} while (drm_find_file(dev, auth.magic));
+		priv->magic = auth.magic;
+		drm_add_magic(dev, priv, auth.magic);
+	}
+	
+	DRM_DEBUG("%u\n", auth.magic);
+	if (copy_to_user((drm_auth_t *)arg, &auth, sizeof(auth)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_authmagic(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	   *priv    = filp->private_data;
+	drm_device_t	   *dev	    = priv->dev;
+	drm_auth_t	   auth;
+	drm_file_t	   *file;
+
+	if (copy_from_user(&auth, (drm_auth_t *)arg, sizeof(auth)))
+		return -EFAULT;
+	DRM_DEBUG("%u\n", auth.magic);
+	if ((file = drm_find_file(dev, auth.magic))) {
+		file->authenticated = 1;
+		drm_remove_magic(dev, auth.magic);
+		return 0;
+	}
+	return -EINVAL;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/bufs.c lia64-2.4/drivers/char/drm-4.0/bufs.c
--- linux-2.4.16/drivers/char/drm-4.0/bufs.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/bufs.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,543 @@
+/* bufs.c -- IOCTLs to manage buffers -*- linux-c -*-
+ * Created: Tue Feb  2 08:37:54 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include <linux/config.h>
+#include "drmP.h"
+#include "linux/un.h"
+
+				/* Compute order.  Can be made faster. */
+int drm_order(unsigned long size)
+{
+	int	      order;
+	unsigned long tmp;
+
+	for (order = 0, tmp = size; tmp >>= 1; ++order);
+	if (size & ~(1 << order)) ++order;
+	return order;
+}
+
+int drm_addmap(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_map_t	*map;
+	
+	if (!(filp->f_mode & 3)) return -EACCES; /* Require read/write */
+
+	map	     = drm_alloc(sizeof(*map), DRM_MEM_MAPS);
+	if (!map) return -ENOMEM;
+	if (copy_from_user(map, (drm_map_t *)arg, sizeof(*map))) {
+		drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		return -EFAULT;
+	}
+
+	DRM_DEBUG("offset = 0x%08lx, size = 0x%08lx, type = %d\n",
+		  map->offset, map->size, map->type);
+	if ((map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK))) {
+		drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		return -EINVAL;
+	}
+	map->mtrr   = -1;
+	map->handle = 0;
+
+	switch (map->type) {
+	case _DRM_REGISTERS:
+	case _DRM_FRAME_BUFFER:
+#if !defined(__sparc__) && !defined(__ia64__)
+		if (map->offset + map->size < map->offset
+		    || map->offset < virt_to_phys(high_memory)) {
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+			return -EINVAL;
+		}
+#endif
+#ifdef CONFIG_MTRR
+		if (map->type == _DRM_FRAME_BUFFER
+		    || (map->flags & _DRM_WRITE_COMBINING)) {
+			map->mtrr = mtrr_add(map->offset, map->size,
+					     MTRR_TYPE_WRCOMB, 1);
+		}
+#endif
+		map->handle = drm_ioremap(map->offset, map->size, dev);
+		break;
+			
+
+	case _DRM_SHM:
+		map->handle = (void *)drm_alloc_pages(drm_order(map->size)
+						      - PAGE_SHIFT,
+						      DRM_MEM_SAREA);
+		DRM_DEBUG("%ld %d %p\n", map->size, drm_order(map->size),
+			  map->handle);
+		if (!map->handle) {
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+			return -ENOMEM;
+		}
+		map->offset = (unsigned long)map->handle;
+		if (map->flags & _DRM_CONTAINS_LOCK) {
+			dev->lock.hw_lock = map->handle; /* Pointer to lock */
+		}
+		break;
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	case _DRM_AGP:
+		map->offset = map->offset + dev->agp->base;
+		break;
+#endif
+	default:
+		drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		return -EINVAL;
+	}
+
+	down(&dev->struct_sem);
+	if (dev->maplist) {
+		++dev->map_count;
+		dev->maplist = drm_realloc(dev->maplist,
+					   (dev->map_count-1)
+					   * sizeof(*dev->maplist),
+					   dev->map_count
+					   * sizeof(*dev->maplist),
+					   DRM_MEM_MAPS);
+	} else {
+		dev->map_count = 1;
+		dev->maplist = drm_alloc(dev->map_count*sizeof(*dev->maplist),
+					 DRM_MEM_MAPS);
+	}
+	dev->maplist[dev->map_count-1] = map;
+	up(&dev->struct_sem);
+
+	if (copy_to_user((drm_map_t *)arg, map, sizeof(*map)))
+		return -EFAULT;
+	if (map->type != _DRM_SHM) {
+		if (copy_to_user(&((drm_map_t *)arg)->handle,
+				 &map->offset,
+				 sizeof(map->offset)))
+			return -EFAULT;
+	}		
+	return 0;
+}
+
+int drm_addbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_desc_t	 request;
+	int		 count;
+	int		 order;
+	int		 size;
+	int		 total;
+	int		 page_order;
+	drm_buf_entry_t	 *entry;
+	unsigned long	 page;
+	drm_buf_t	 *buf;
+	int		 alignment;
+	unsigned long	 offset;
+	int		 i;
+	int		 byte_count;
+	int		 page_count;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	count	   = request.count;
+	order	   = drm_order(request.size);
+	size	   = 1 << order;
+	
+	DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n",
+		  request.count, request.size, size, order, dev->queue_count);
+
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total	   = PAGE_SIZE << page_order;
+
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+	
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;	/* May only call once for each order */
+	}
+	
+	if(count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		return -EINVAL;
+	}
+	
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+
+	entry->seglist = drm_alloc(count * sizeof(*entry->seglist),
+				   DRM_MEM_SEGS);
+	if (!entry->seglist) {
+		drm_free(entry->buflist,
+			 count * sizeof(*entry->buflist),
+			 DRM_MEM_BUFS);
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->seglist, 0, count * sizeof(*entry->seglist));
+
+	dma->pagelist = drm_realloc(dma->pagelist,
+				    dma->page_count * sizeof(*dma->pagelist),
+				    (dma->page_count + (count << page_order))
+				    * sizeof(*dma->pagelist),
+				    DRM_MEM_PAGES);
+	DRM_DEBUG("pagelist: %d entries\n",
+		  dma->page_count + (count << page_order));
+
+
+	entry->buf_size	  = size;
+	entry->page_order = page_order;
+	byte_count	  = 0;
+	page_count	  = 0;
+	while (entry->buf_count < count) {
+		if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break;
+		entry->seglist[entry->seg_count++] = page;
+		for (i = 0; i < (1 << page_order); i++) {
+			DRM_DEBUG("page %d @ 0x%08lx\n",
+				  dma->page_count + page_count,
+				  page + PAGE_SIZE * i);
+			dma->pagelist[dma->page_count + page_count++]
+				= page + PAGE_SIZE * i;
+		}
+		for (offset = 0;
+		     offset + size <= total && entry->buf_count < count;
+		     offset += alignment, ++entry->buf_count) {
+			buf	     = &entry->buflist[entry->buf_count];
+			buf->idx     = dma->buf_count + entry->buf_count;
+			buf->total   = alignment;
+			buf->order   = order;
+			buf->used    = 0;
+			buf->offset  = (dma->byte_count + byte_count + offset);
+			buf->address = (void *)(page + offset);
+			buf->next    = NULL;
+			buf->waiting = 0;
+			buf->pending = 0;
+			init_waitqueue_head(&buf->dma_wait);
+			buf->pid     = 0;
+#if DRM_DMA_HISTOGRAM
+			buf->time_queued     = 0;
+			buf->time_dispatched = 0;
+			buf->time_completed  = 0;
+			buf->time_freed	     = 0;
+#endif
+			DRM_DEBUG("buffer %d @ %p\n",
+				  entry->buf_count, buf->address);
+		}
+		byte_count += PAGE_SIZE << page_order;
+	}
+
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+
+	dma->buf_count	+= entry->buf_count;
+	dma->seg_count	+= entry->seg_count;
+	dma->page_count += entry->seg_count << page_order;
+	dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order);
+	
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+	
+	up(&dev->struct_sem);
+
+	request.count = entry->buf_count;
+	request.size  = size;
+
+	if (copy_to_user((drm_buf_desc_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+	
+	atomic_dec(&dev->buf_alloc);
+	return 0;
+}
+
+int drm_infobufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_info_t	 request;
+	int		 i;
+	int		 count;
+
+	if (!dma) return -EINVAL;
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_info_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+		if (dma->bufs[i].buf_count) ++count;
+	}
+	
+	DRM_DEBUG("count = %d\n", count);
+	
+	if (request.count >= count) {
+		for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+			if (dma->bufs[i].buf_count) {
+				if (copy_to_user(&request.list[count].count,
+						 &dma->bufs[i].buf_count,
+						 sizeof(dma->bufs[0]
+							.buf_count)) ||
+				    copy_to_user(&request.list[count].size,
+						 &dma->bufs[i].buf_size,
+						 sizeof(dma->bufs[0].buf_size)) ||
+				    copy_to_user(&request.list[count].low_mark,
+						 &dma->bufs[i]
+						 .freelist.low_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.low_mark)) ||
+				    copy_to_user(&request.list[count]
+						 .high_mark,
+						 &dma->bufs[i]
+						 .freelist.high_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.high_mark)))
+					return -EFAULT;
+
+				DRM_DEBUG("%d %d %d %d %d\n",
+					  i,
+					  dma->bufs[i].buf_count,
+					  dma->bufs[i].buf_size,
+					  dma->bufs[i].freelist.low_mark,
+					  dma->bufs[i].freelist.high_mark);
+				++count;
+			}
+		}
+	}
+	request.count = count;
+
+	if (copy_to_user((drm_buf_info_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+	
+	return 0;
+}
+
+int drm_markbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_desc_t	 request;
+	int		 order;
+	drm_buf_entry_t	 *entry;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	DRM_DEBUG("%d, %d, %d\n",
+		  request.size, request.low_mark, request.high_mark);
+	order = drm_order(request.size);
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	entry = &dma->bufs[order];
+
+	if (request.low_mark < 0 || request.low_mark > entry->buf_count)
+		return -EINVAL;
+	if (request.high_mark < 0 || request.high_mark > entry->buf_count)
+		return -EINVAL;
+
+	entry->freelist.low_mark  = request.low_mark;
+	entry->freelist.high_mark = request.high_mark;
+	
+	return 0;
+}
+
+int drm_freebufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_free_t	 request;
+	int		 i;
+	int		 idx;
+	drm_buf_t	 *buf;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_free_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	DRM_DEBUG("%d\n", request.count);
+	for (i = 0; i < request.count; i++) {
+		if (copy_from_user(&idx,
+				   &request.list[i],
+				   sizeof(idx)))
+			return -EFAULT;
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+				  idx, dma->buf_count - 1);
+			return -EINVAL;
+		}
+		buf = dma->buflist[idx];
+		if (buf->pid != current->pid) {
+			DRM_ERROR("Process %d freeing buffer owned by %d\n",
+				  current->pid, buf->pid);
+			return -EINVAL;
+		}
+		drm_free_buffer(dev, buf);
+	}
+	
+	return 0;
+}
+
+int drm_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	int		 retcode = 0;
+	const int	 zero	 = 0;
+	unsigned long	 virtual;
+	unsigned long	 address;
+	drm_buf_map_t	 request;
+	int		 i;
+
+	if (!dma) return -EINVAL;
+	
+	DRM_DEBUG("\n");
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_map_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	if (request.count >= dma->buf_count) {
+		down_write(&current->mm->mmap_sem);
+		virtual = do_mmap(filp, 0, dma->byte_count,
+				  PROT_READ|PROT_WRITE, MAP_SHARED, 0);
+		up_write(&current->mm->mmap_sem);
+		if (virtual > -1024UL) {
+				/* Real error */
+			retcode = (signed long)virtual;
+			goto done;
+		}
+		request.virtual = (void *)virtual;
+
+		for (i = 0; i < dma->buf_count; i++) {
+			if (copy_to_user(&request.list[i].idx,
+					 &dma->buflist[i]->idx,
+					 sizeof(request.list[0].idx))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].total,
+					 &dma->buflist[i]->total,
+					 sizeof(request.list[0].total))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].used,
+					 &zero,
+					 sizeof(zero))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			address = virtual + dma->buflist[i]->offset;
+			if (copy_to_user(&request.list[i].address,
+					 &address,
+					 sizeof(address))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+		}
+	}
+done:
+	request.count = dma->buf_count;
+	DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode);
+
+	if (copy_to_user((drm_buf_map_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+
+	return retcode;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/context.c lia64-2.4/drivers/char/drm-4.0/context.c
--- linux-2.4.16/drivers/char/drm-4.0/context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/context.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,321 @@
+/* context.c -- IOCTLs for contexts and DMA queues -*- linux-c -*-
+ * Created: Tue Feb  2 08:37:54 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+static int drm_init_queue(drm_device_t *dev, drm_queue_t *q, drm_ctx_t *ctx)
+{
+	DRM_DEBUG("\n");
+	
+	if (atomic_read(&q->use_count) != 1
+	    || atomic_read(&q->finalization)
+	    || atomic_read(&q->block_count)) {
+		DRM_ERROR("New queue is already in use: u%d f%d b%d\n",
+			  atomic_read(&q->use_count),
+			  atomic_read(&q->finalization),
+			  atomic_read(&q->block_count));
+	}
+		  
+	atomic_set(&q->finalization,  0);
+	atomic_set(&q->block_count,   0);
+	atomic_set(&q->block_read,    0);
+	atomic_set(&q->block_write,   0);
+	atomic_set(&q->total_queued,  0);
+	atomic_set(&q->total_flushed, 0);
+	atomic_set(&q->total_locks,   0);
+
+	init_waitqueue_head(&q->write_queue);
+	init_waitqueue_head(&q->read_queue);
+	init_waitqueue_head(&q->flush_queue);
+
+	q->flags = ctx->flags;
+
+	drm_waitlist_create(&q->waitlist, dev->dma->buf_count);
+
+	return 0;
+}
+
+
+/* drm_alloc_queue:
+PRE: 1) dev->queuelist[0..dev->queue_count] is allocated and will not
+	disappear (so all deallocation must be done after IOCTLs are off)
+     2) dev->queue_count < dev->queue_slots
+     3) dev->queuelist[i].use_count == 0 and
+	dev->queuelist[i].finalization == 0 if i not in use 
+POST: 1) dev->queuelist[i].use_count == 1
+      2) dev->queue_count < dev->queue_slots */
+		
+static int drm_alloc_queue(drm_device_t *dev)
+{
+	int	    i;
+	drm_queue_t *queue;
+	int	    oldslots;
+	int	    newslots;
+				/* Check for a free queue */
+	for (i = 0; i < dev->queue_count; i++) {
+		atomic_inc(&dev->queuelist[i]->use_count);
+		if (atomic_read(&dev->queuelist[i]->use_count) == 1
+		    && !atomic_read(&dev->queuelist[i]->finalization)) {
+			DRM_DEBUG("%d (free)\n", i);
+			return i;
+		}
+		atomic_dec(&dev->queuelist[i]->use_count);
+	}
+				/* Allocate a new queue */
+	
+	queue = drm_alloc(sizeof(*queue), DRM_MEM_QUEUES);
+	if(queue == NULL)
+		return -ENOMEM;	
+
+	memset(queue, 0, sizeof(*queue));
+	down(&dev->struct_sem);
+	atomic_set(&queue->use_count, 1);
+	
+	++dev->queue_count;
+	if (dev->queue_count >= dev->queue_slots) {
+		oldslots = dev->queue_slots * sizeof(*dev->queuelist);
+		if (!dev->queue_slots) dev->queue_slots = 1;
+		dev->queue_slots *= 2;
+		newslots = dev->queue_slots * sizeof(*dev->queuelist);
+
+		dev->queuelist = drm_realloc(dev->queuelist,
+					     oldslots,
+					     newslots,
+					     DRM_MEM_QUEUES);
+		if (!dev->queuelist) {
+			up(&dev->struct_sem);
+			DRM_DEBUG("out of memory\n");
+			return -ENOMEM;
+		}
+	}
+	dev->queuelist[dev->queue_count-1] = queue;
+	
+	up(&dev->struct_sem);
+	DRM_DEBUG("%d (new)\n", dev->queue_count - 1);
+	return dev->queue_count - 1;
+}
+
+int drm_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+
+int drm_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = drm_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Init kernel's context and get a new one. */
+		drm_init_queue(dev, dev->queuelist[ctx.handle], &ctx);
+		ctx.handle = drm_alloc_queue(dev);
+	}
+	drm_init_queue(dev, dev->queuelist[ctx.handle], &ctx);
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+	drm_queue_t	*q;
+		
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	
+	DRM_DEBUG("%d\n", ctx.handle);
+	
+	if (ctx.handle < 0 || ctx.handle >= dev->queue_count) return -EINVAL;
+	q = dev->queuelist[ctx.handle];
+	
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) == 1) {
+				/* No longer in use */
+		atomic_dec(&q->use_count);
+		return -EINVAL;
+	}
+
+	if (DRM_BUFCOUNT(&q->waitlist)) {
+		atomic_dec(&q->use_count);
+		return -EBUSY;
+	}
+	
+	q->flags = ctx.flags;
+	
+	atomic_dec(&q->use_count);
+	return 0;
+}
+
+int drm_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+	drm_queue_t	*q;
+		
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	
+	DRM_DEBUG("%d\n", ctx.handle);
+	
+	if (ctx.handle >= dev->queue_count) return -EINVAL;
+	q = dev->queuelist[ctx.handle];
+	
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) == 1) {
+				/* No longer in use */
+		atomic_dec(&q->use_count);
+		return -EINVAL;
+	}
+	
+	ctx.flags = q->flags;
+	atomic_dec(&q->use_count);
+	
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	
+	return 0;
+}
+
+int drm_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return drm_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int drm_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	drm_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int drm_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+	drm_queue_t	*q;
+	drm_buf_t	*buf;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	
+	if (ctx.handle >= dev->queue_count) return -EINVAL;
+	q = dev->queuelist[ctx.handle];
+	
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) == 1) {
+				/* No longer in use */
+		atomic_dec(&q->use_count);
+		return -EINVAL;
+	}
+	
+	atomic_inc(&q->finalization); /* Mark queue in finalization state */
+	atomic_sub(2, &q->use_count); /* Mark queue as unused (pending
+					 finalization) */
+
+	while (test_and_set_bit(0, &dev->interrupt_flag)) {
+		schedule();
+		if (signal_pending(current)) {
+			clear_bit(0, &dev->interrupt_flag);
+			return -EINTR;
+		}
+	}
+				/* Remove queued buffers */
+	while ((buf = drm_waitlist_get(&q->waitlist))) {
+		drm_free_buffer(dev, buf);
+	}
+	clear_bit(0, &dev->interrupt_flag);
+	
+				/* Wakeup blocked processes */
+	wake_up_interruptible(&q->read_queue);
+	wake_up_interruptible(&q->write_queue);
+	wake_up_interruptible(&q->flush_queue);
+	
+				/* Finalization over.  Queue is made
+				   available when both use_count and
+				   finalization become 0, which won't
+				   happen until all the waiting processes
+				   stop waiting. */
+	atomic_dec(&q->finalization);
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/ctxbitmap.c lia64-2.4/drivers/char/drm-4.0/ctxbitmap.c
--- linux-2.4.16/drivers/char/drm-4.0/ctxbitmap.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/ctxbitmap.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,85 @@
+/* ctxbitmap.c -- Context bitmap management -*- linux-c -*-
+ * Created: Thu Jan 6 03:56:42 2000 by jhartmann@precisioninsight.com
+ * 
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle)
+{
+	if (ctx_handle < 0) goto failed;
+
+	if (ctx_handle < DRM_MAX_CTXBITMAP) {
+		clear_bit(ctx_handle, dev->ctx_bitmap);
+		return;
+	}
+failed:
+       	DRM_ERROR("Attempt to free invalid context handle: %d\n",
+		  ctx_handle);
+       	return;
+}
+
+int drm_ctxbitmap_next(drm_device_t *dev)
+{
+	int bit;
+
+	bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP);
+	if (bit < DRM_MAX_CTXBITMAP) {
+		set_bit(bit, dev->ctx_bitmap);
+	   	DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit);
+		return bit;
+	}
+	return -1;
+}
+
+int drm_ctxbitmap_init(drm_device_t *dev)
+{
+	int i;
+   	int temp;
+
+	dev->ctx_bitmap = (unsigned long *) drm_alloc(PAGE_SIZE, 
+						      DRM_MEM_CTXBITMAP);
+	if(dev->ctx_bitmap == NULL) {
+		return -ENOMEM;
+	}
+	memset((void *) dev->ctx_bitmap, 0, PAGE_SIZE);
+	for(i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+		temp = drm_ctxbitmap_next(dev);
+	   	DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp);
+	}
+
+	return 0;
+}
+
+void drm_ctxbitmap_cleanup(drm_device_t *dev)
+{
+	drm_free((void *)dev->ctx_bitmap, PAGE_SIZE,
+		 DRM_MEM_CTXBITMAP);
+}
+
diff -urN linux-2.4.16/drivers/char/drm-4.0/dma.c lia64-2.4/drivers/char/drm-4.0/dma.c
--- linux-2.4.16/drivers/char/drm-4.0/dma.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/dma.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,546 @@
+/* dma.c -- DMA IOCTL and function support -*- linux-c -*-
+ * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinuxa.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+#include <linux/interrupt.h>	/* For task queue support */
+
+void drm_dma_setup(drm_device_t *dev)
+{
+	int i;
+	
+	if (!(dev->dma = drm_alloc(sizeof(*dev->dma), DRM_MEM_DRIVER))) {
+                printk(KERN_ERR "drm_dma_setup: can't drm_alloc dev->dma");
+                return;
+        }       
+	memset(dev->dma, 0, sizeof(*dev->dma));
+	for (i = 0; i <= DRM_MAX_ORDER; i++)
+		memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0]));
+}
+
+void drm_dma_takedown(drm_device_t *dev)
+{
+	drm_device_dma_t  *dma = dev->dma;
+	int		  i, j;
+
+	if (!dma) return;
+	
+				/* Clear dma buffers */
+	for (i = 0; i <= DRM_MAX_ORDER; i++) {
+		if (dma->bufs[i].seg_count) {
+			DRM_DEBUG("order %d: buf_count = %d,"
+				  " seg_count = %d\n",
+				  i,
+				  dma->bufs[i].buf_count,
+				  dma->bufs[i].seg_count);
+			for (j = 0; j < dma->bufs[i].seg_count; j++) {
+				drm_free_pages(dma->bufs[i].seglist[j],
+					       dma->bufs[i].page_order,
+					       DRM_MEM_DMA);
+			}
+			drm_free(dma->bufs[i].seglist,
+				 dma->bufs[i].seg_count
+				 * sizeof(*dma->bufs[0].seglist),
+				 DRM_MEM_SEGS);
+		}
+	   	if(dma->bufs[i].buf_count) {
+		   	for(j = 0; j < dma->bufs[i].buf_count; j++) {
+			   if(dma->bufs[i].buflist[j].dev_private) {
+			      drm_free(dma->bufs[i].buflist[j].dev_private,
+				       dma->bufs[i].buflist[j].dev_priv_size,
+				       DRM_MEM_BUFS);
+			   }
+			}
+		   	drm_free(dma->bufs[i].buflist,
+				 dma->bufs[i].buf_count *
+				 sizeof(*dma->bufs[0].buflist),
+				 DRM_MEM_BUFS);
+		   	drm_freelist_destroy(&dma->bufs[i].freelist);
+		}
+	}
+	
+	if (dma->buflist) {
+		drm_free(dma->buflist,
+			 dma->buf_count * sizeof(*dma->buflist),
+			 DRM_MEM_BUFS);
+	}
+
+	if (dma->pagelist) {
+		drm_free(dma->pagelist,
+			 dma->page_count * sizeof(*dma->pagelist),
+			 DRM_MEM_PAGES);
+	}
+	drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER);
+	dev->dma = NULL;
+}
+
+#if DRM_DMA_HISTOGRAM
+/* This is slow, but is useful for debugging. */
+int drm_histogram_slot(unsigned long count)
+{
+	int value = DRM_DMA_HISTOGRAM_INITIAL;
+	int slot;
+
+	for (slot = 0;
+	     slot < DRM_DMA_HISTOGRAM_SLOTS;
+	     ++slot, value = DRM_DMA_HISTOGRAM_NEXT(value)) {
+		if (count < value) return slot;
+	}
+	return DRM_DMA_HISTOGRAM_SLOTS - 1;
+}
+
+void drm_histogram_compute(drm_device_t *dev, drm_buf_t *buf)
+{
+	cycles_t queued_to_dispatched;
+	cycles_t dispatched_to_completed;
+	cycles_t completed_to_freed;
+	int	 q2d, d2c, c2f, q2c, q2f;
+	
+	if (buf->time_queued) {
+		queued_to_dispatched	= (buf->time_dispatched
+					   - buf->time_queued);
+		dispatched_to_completed = (buf->time_completed
+					   - buf->time_dispatched);
+		completed_to_freed	= (buf->time_freed
+					   - buf->time_completed);
+
+		q2d = drm_histogram_slot(queued_to_dispatched);
+		d2c = drm_histogram_slot(dispatched_to_completed);
+		c2f = drm_histogram_slot(completed_to_freed);
+
+		q2c = drm_histogram_slot(queued_to_dispatched
+					 + dispatched_to_completed);
+		q2f = drm_histogram_slot(queued_to_dispatched
+					 + dispatched_to_completed
+					 + completed_to_freed);
+		
+		atomic_inc(&dev->histo.total);
+		atomic_inc(&dev->histo.queued_to_dispatched[q2d]);
+		atomic_inc(&dev->histo.dispatched_to_completed[d2c]);
+		atomic_inc(&dev->histo.completed_to_freed[c2f]);
+		
+		atomic_inc(&dev->histo.queued_to_completed[q2c]);
+		atomic_inc(&dev->histo.queued_to_freed[q2f]);
+
+	}
+	buf->time_queued     = 0;
+	buf->time_dispatched = 0;
+	buf->time_completed  = 0;
+	buf->time_freed	     = 0;
+}
+#endif
+
+void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf)
+{
+	drm_device_dma_t *dma = dev->dma;
+
+	if (!buf) return;
+	
+	buf->waiting  = 0;
+	buf->pending  = 0;
+	buf->pid      = 0;
+	buf->used     = 0;
+#if DRM_DMA_HISTOGRAM
+	buf->time_completed = get_cycles();
+#endif
+	if (waitqueue_active(&buf->dma_wait)) {
+		wake_up_interruptible(&buf->dma_wait);
+	} else {
+				/* If processes are waiting, the last one
+				   to wake will put the buffer on the free
+				   list.  If no processes are waiting, we
+				   put the buffer on the freelist here. */
+		drm_freelist_put(dev, &dma->bufs[buf->order].freelist, buf);
+	}
+}
+
+void drm_reclaim_buffers(drm_device_t *dev, pid_t pid)
+{
+	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+
+	if (!dma) return;
+	for (i = 0; i < dma->buf_count; i++) {
+		if (dma->buflist[i]->pid == pid) {
+			switch (dma->buflist[i]->list) {
+			case DRM_LIST_NONE:
+				drm_free_buffer(dev, dma->buflist[i]);
+				break;
+			case DRM_LIST_WAIT:
+				dma->buflist[i]->list = DRM_LIST_RECLAIM;
+				break;
+			default:
+				/* Buffer already on hardware. */
+				break;
+			}
+		}
+	}
+}
+
+int drm_context_switch(drm_device_t *dev, int old, int new)
+{
+	char	    buf[64];
+	drm_queue_t *q;
+
+	atomic_inc(&dev->total_ctx);
+
+	if (test_and_set_bit(0, &dev->context_flag)) {
+		DRM_ERROR("Reentering -- FIXME\n");
+		return -EBUSY;
+	}
+
+#if DRM_DMA_HISTOGRAM
+	dev->ctx_start = get_cycles();
+#endif
+	
+	DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+	if (new >= dev->queue_count) {
+		clear_bit(0, &dev->context_flag);
+		return -EINVAL;
+	}
+
+	if (new == dev->last_context) {
+		clear_bit(0, &dev->context_flag);
+		return 0;
+	}
+	
+	q = dev->queuelist[new];
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) == 1) {
+		atomic_dec(&q->use_count);
+		clear_bit(0, &dev->context_flag);
+		return -EINVAL;
+	}
+
+	if (drm_flags & DRM_FLAG_NOCTX) {
+		drm_context_switch_complete(dev, new);
+	} else {
+		sprintf(buf, "C %d %d\n", old, new);
+		drm_write_string(dev, buf);
+	}
+	
+	atomic_dec(&q->use_count);
+	
+	return 0;
+}
+
+int drm_context_switch_complete(drm_device_t *dev, int new)
+{
+	drm_device_dma_t *dma = dev->dma;
+	
+	dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+	dev->last_switch  = jiffies;
+	
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("Lock isn't held after context switch\n");
+	}
+
+	if (!dma || !(dma->next_buffer && dma->next_buffer->while_locked)) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("Cannot free lock\n");
+		}
+	}
+	
+#if DRM_DMA_HISTOGRAM
+	atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+						      - dev->ctx_start)]);
+		   
+#endif
+	clear_bit(0, &dev->context_flag);
+	wake_up_interruptible(&dev->context_wait);
+	
+	return 0;
+}
+
+void drm_clear_next_buffer(drm_device_t *dev)
+{
+	drm_device_dma_t *dma = dev->dma;
+	
+	dma->next_buffer = NULL;
+	if (dma->next_queue && !DRM_BUFCOUNT(&dma->next_queue->waitlist)) {
+		wake_up_interruptible(&dma->next_queue->flush_queue);
+	}
+	dma->next_queue	 = NULL;
+}
+
+
+int drm_select_queue(drm_device_t *dev, void (*wrapper)(unsigned long))
+{
+	int	   i;
+	int	   candidate = -1;
+	int	   j	     = jiffies;
+
+	if (!dev) {
+		DRM_ERROR("No device\n");
+		return -1;
+	}
+	if (!dev->queuelist || !dev->queuelist[DRM_KERNEL_CONTEXT]) {
+				/* This only happens between the time the
+				   interrupt is initialized and the time
+				   the queues are initialized. */
+		return -1;
+	}
+
+				/* Doing "while locked" DMA? */
+	if (DRM_WAITCOUNT(dev, DRM_KERNEL_CONTEXT)) {
+		return DRM_KERNEL_CONTEXT;
+	}
+
+				/* If there are buffers on the last_context
+				   queue, and we have not been executing
+				   this context very long, continue to
+				   execute this context. */
+	if (dev->last_switch <= j
+	    && dev->last_switch + DRM_TIME_SLICE > j
+	    && DRM_WAITCOUNT(dev, dev->last_context)) {
+		return dev->last_context;
+	}
+
+				/* Otherwise, find a candidate */
+	for (i = dev->last_checked + 1; i < dev->queue_count; i++) {
+		if (DRM_WAITCOUNT(dev, i)) {
+			candidate = dev->last_checked = i;
+			break;
+		}
+	}
+
+	if (candidate < 0) {
+		for (i = 0; i < dev->queue_count; i++) {
+			if (DRM_WAITCOUNT(dev, i)) {
+				candidate = dev->last_checked = i;
+				break;
+			}
+		}
+	}
+
+	if (wrapper
+	    && candidate >= 0
+	    && candidate != dev->last_context
+	    && dev->last_switch <= j
+	    && dev->last_switch + DRM_TIME_SLICE > j) {
+		if (dev->timer.expires != dev->last_switch + DRM_TIME_SLICE) {
+			del_timer(&dev->timer);
+			dev->timer.function = wrapper;
+			dev->timer.data	    = (unsigned long)dev;
+			dev->timer.expires  = dev->last_switch+DRM_TIME_SLICE;
+			add_timer(&dev->timer);
+		}
+		return -1;
+	}
+
+	return candidate;
+}
+
+
+int drm_dma_enqueue(drm_device_t *dev, drm_dma_t *d)
+{
+	int		  i;
+	drm_queue_t	  *q;
+	drm_buf_t	  *buf;
+	int		  idx;
+	int		  while_locked = 0;
+	drm_device_dma_t  *dma = dev->dma;
+	DECLARE_WAITQUEUE(entry, current);
+
+	DRM_DEBUG("%d\n", d->send_count);
+
+	if (d->flags & _DRM_DMA_WHILE_LOCKED) {
+		int context = dev->lock.hw_lock->lock;
+		
+		if (!_DRM_LOCK_IS_HELD(context)) {
+			DRM_ERROR("No lock held during \"while locked\""
+				  " request\n");
+			return -EINVAL;
+		}
+		if (d->context != _DRM_LOCKING_CONTEXT(context)
+		    && _DRM_LOCKING_CONTEXT(context) != DRM_KERNEL_CONTEXT) {
+			DRM_ERROR("Lock held by %d while %d makes"
+				  " \"while locked\" request\n",
+				  _DRM_LOCKING_CONTEXT(context),
+				  d->context);
+			return -EINVAL;
+		}
+		q = dev->queuelist[DRM_KERNEL_CONTEXT];
+		while_locked = 1;
+	} else {
+		q = dev->queuelist[d->context];
+	}
+
+
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->block_write)) {
+		add_wait_queue(&q->write_queue, &entry);
+		atomic_inc(&q->block_count);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!atomic_read(&q->block_write)) break;
+			schedule();
+			if (signal_pending(current)) {
+				atomic_dec(&q->use_count);
+				remove_wait_queue(&q->write_queue, &entry);
+				return -EINTR;
+			}
+		}
+		atomic_dec(&q->block_count);
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&q->write_queue, &entry);
+	}
+	
+	for (i = 0; i < d->send_count; i++) {
+		idx = d->send_indices[i];
+		if (idx < 0 || idx >= dma->buf_count) {
+			atomic_dec(&q->use_count);
+			DRM_ERROR("Index %d (of %d max)\n",
+				  d->send_indices[i], dma->buf_count - 1);
+			return -EINVAL;
+		}
+		buf = dma->buflist[ idx ];
+		if (buf->pid != current->pid) {
+			atomic_dec(&q->use_count);
+			DRM_ERROR("Process %d using buffer owned by %d\n",
+				  current->pid, buf->pid);
+			return -EINVAL;
+		}
+		if (buf->list != DRM_LIST_NONE) {
+			atomic_dec(&q->use_count);
+			DRM_ERROR("Process %d using buffer %d on list %d\n",
+				  current->pid, buf->idx, buf->list);
+		}
+		buf->used	  = d->send_sizes[i];
+		buf->while_locked = while_locked;
+		buf->context	  = d->context;
+		if (!buf->used) {
+			DRM_ERROR("Queueing 0 length buffer\n");
+		}
+		if (buf->pending) {
+			atomic_dec(&q->use_count);
+			DRM_ERROR("Queueing pending buffer:"
+				  " buffer %d, offset %d\n",
+				  d->send_indices[i], i);
+			return -EINVAL;
+		}
+		if (buf->waiting) {
+			atomic_dec(&q->use_count);
+			DRM_ERROR("Queueing waiting buffer:"
+				  " buffer %d, offset %d\n",
+				  d->send_indices[i], i);
+			return -EINVAL;
+		}
+		buf->waiting = 1;
+		if (atomic_read(&q->use_count) == 1
+		    || atomic_read(&q->finalization)) {
+			drm_free_buffer(dev, buf);
+		} else {
+			drm_waitlist_put(&q->waitlist, buf);
+			atomic_inc(&q->total_queued);
+		}
+	}
+	atomic_dec(&q->use_count);
+	
+	return 0;
+}
+
+static int drm_dma_get_buffers_of_order(drm_device_t *dev, drm_dma_t *d,
+					int order)
+{
+	int		  i;
+	drm_buf_t	  *buf;
+	drm_device_dma_t  *dma = dev->dma;
+	
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = drm_freelist_get(&dma->bufs[order].freelist,
+				       d->flags & _DRM_DMA_WAIT);
+		if (!buf) break;
+		if (buf->pending || buf->waiting) {
+			DRM_ERROR("Free buffer %d in use by %d (w%d, p%d)\n",
+				  buf->idx,
+				  buf->pid,
+				  buf->waiting,
+				  buf->pending);
+		}
+		buf->pid     = current->pid;
+		if (copy_to_user(&d->request_indices[i],
+				 &buf->idx,
+				 sizeof(buf->idx)))
+			return -EFAULT;
+
+		if (copy_to_user(&d->request_sizes[i],
+				 &buf->total,
+				 sizeof(buf->total)))
+			return -EFAULT;
+
+		++d->granted_count;
+	}
+	return 0;
+}
+
+
+int drm_dma_get_buffers(drm_device_t *dev, drm_dma_t *dma)
+{
+	int		  order;
+	int		  retcode = 0;
+	int		  tmp_order;
+	
+	order = drm_order(dma->request_size);
+
+	dma->granted_count = 0;
+	retcode		   = drm_dma_get_buffers_of_order(dev, dma, order);
+
+	if (dma->granted_count < dma->request_count
+	    && (dma->flags & _DRM_DMA_SMALLER_OK)) {
+		for (tmp_order = order - 1;
+		     !retcode
+			     && dma->granted_count < dma->request_count
+			     && tmp_order >= DRM_MIN_ORDER;
+		     --tmp_order) {
+			
+			retcode = drm_dma_get_buffers_of_order(dev, dma,
+							       tmp_order);
+		}
+	}
+
+	if (dma->granted_count < dma->request_count
+	    && (dma->flags & _DRM_DMA_LARGER_OK)) {
+		for (tmp_order = order + 1;
+		     !retcode
+			     && dma->granted_count < dma->request_count
+			     && tmp_order <= DRM_MAX_ORDER;
+		     ++tmp_order) {
+			
+			retcode = drm_dma_get_buffers_of_order(dev, dma,
+							       tmp_order);
+		}
+	}
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/drawable.c lia64-2.4/drivers/char/drm-4.0/drawable.c
--- linux-2.4.16/drivers/char/drm-4.0/drawable.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/drawable.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,51 @@
+/* drawable.c -- IOCTLs for drawables -*- linux-c -*-
+ * Created: Tue Feb  2 08:37:54 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+int drm_adddraw(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_draw_t draw;
+
+	draw.handle = 0;	/* NOOP */
+	DRM_DEBUG("%d\n", draw.handle);
+	if (copy_to_user((drm_draw_t *)arg, &draw, sizeof(draw)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_rmdraw(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	return 0;		/* NOOP */
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/drm.h lia64-2.4/drivers/char/drm-4.0/drm.h
--- linux-2.4.16/drivers/char/drm-4.0/drm.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/drm.h	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,414 @@
+/* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
+ * Created: Mon Jan  4 10:05:05 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ * Acknowledgements:
+ * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
+ *
+ */
+
+#ifndef _DRM_H_
+#define _DRM_H_
+
+#include <linux/config.h>
+#if defined(__linux__)
+#include <asm/ioctl.h>		/* For _IO* macros */
+#define DRM_IOCTL_NR(n)	     _IOC_NR(n)
+#elif defined(__FreeBSD__)
+#include <sys/ioccom.h>
+#define DRM_IOCTL_NR(n)	     ((n) & 0xff)
+#endif
+
+#define DRM_PROC_DEVICES "/proc/devices"
+#define DRM_PROC_MISC	 "/proc/misc"
+#define DRM_PROC_DRM	 "/proc/drm"
+#define DRM_DEV_DRM	 "/dev/drm"
+#define DRM_DEV_MODE	 (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
+#define DRM_DEV_UID	 0
+#define DRM_DEV_GID	 0
+
+
+#define DRM_NAME	"drm"	  /* Name in kernel, /dev, and /proc	    */
+#define DRM_MIN_ORDER	5	  /* At least 2^5 bytes = 32 bytes	    */
+#define DRM_MAX_ORDER	22	  /* Up to 2^22 bytes = 4MB		    */
+#define DRM_RAM_PERCENT 10	  /* How much system ram can we lock?	    */
+
+#define _DRM_LOCK_HELD	0x80000000 /* Hardware lock is held		    */
+#define _DRM_LOCK_CONT	0x40000000 /* Hardware lock is contended	    */
+#define _DRM_LOCK_IS_HELD(lock)	   ((lock) & _DRM_LOCK_HELD)
+#define _DRM_LOCK_IS_CONT(lock)	   ((lock) & _DRM_LOCK_CONT)
+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
+
+typedef unsigned long drm_handle_t;
+typedef unsigned int  drm_context_t;
+typedef unsigned int  drm_drawable_t;
+typedef unsigned int  drm_magic_t;
+
+/* Warning: If you change this structure, make sure you change
+ * XF86DRIClipRectRec in the server as well */
+
+typedef struct drm_clip_rect {
+           unsigned short x1;
+           unsigned short y1;
+           unsigned short x2;
+           unsigned short y2;
+} drm_clip_rect_t;
+
+/* Seperate include files for the i810/mga/r128 specific structures */
+#include "mga_drm.h"
+#include "i810_drm.h"
+#include "r128_drm.h"
+#include "radeon_drm.h"
+#ifdef CONFIG_DRM40_SIS
+#include "sis_drm.h"
+#endif
+
+typedef struct drm_version {
+	int    version_major;	  /* Major version			    */
+	int    version_minor;	  /* Minor version			    */
+	int    version_patchlevel;/* Patch level			    */
+	size_t name_len;	  /* Length of name buffer		    */
+	char   *name;		  /* Name of driver			    */
+	size_t date_len;	  /* Length of date buffer		    */
+	char   *date;		  /* User-space buffer to hold date	    */
+	size_t desc_len;	  /* Length of desc buffer		    */
+	char   *desc;		  /* User-space buffer to hold desc	    */
+} drm_version_t;
+
+typedef struct drm_unique {
+	size_t unique_len;	  /* Length of unique			    */
+	char   *unique;		  /* Unique name for driver instantiation   */
+} drm_unique_t;
+
+typedef struct drm_list {
+	int		 count;	  /* Length of user-space structures	    */
+	drm_version_t	 *version;
+} drm_list_t;
+
+typedef struct drm_block {
+	int		 unused;
+} drm_block_t;
+
+typedef struct drm_control {
+	enum {
+		DRM_ADD_COMMAND,
+		DRM_RM_COMMAND,
+		DRM_INST_HANDLER,
+		DRM_UNINST_HANDLER
+	}		 func;
+	int		 irq;
+} drm_control_t;
+
+typedef enum drm_map_type {
+	_DRM_FRAME_BUFFER = 0,	  /* WC (no caching), no core dump	    */
+	_DRM_REGISTERS	  = 1,	  /* no caching, no core dump		    */
+	_DRM_SHM	  = 2,	  /* shared, cached			    */
+	_DRM_AGP          = 3	  /* AGP/GART                               */
+} drm_map_type_t;
+
+typedef enum drm_map_flags {
+	_DRM_RESTRICTED	     = 0x01, /* Cannot be mapped to user-virtual    */
+	_DRM_READ_ONLY	     = 0x02,
+	_DRM_LOCKED	     = 0x04, /* shared, cached, locked		    */
+	_DRM_KERNEL	     = 0x08, /* kernel requires access		    */
+	_DRM_WRITE_COMBINING = 0x10, /* use write-combining if available    */
+	_DRM_CONTAINS_LOCK   = 0x20  /* SHM page that contains lock	    */
+} drm_map_flags_t;
+
+typedef struct drm_map {
+	unsigned long	offset;	 /* Requested physical address (0 for SAREA)*/
+	unsigned long	size;	 /* Requested physical size (bytes)	    */
+	drm_map_type_t	type;	 /* Type of memory to map		    */
+	drm_map_flags_t flags;	 /* Flags				    */
+	void		*handle; /* User-space: "Handle" to pass to mmap    */
+				 /* Kernel-space: kernel-virtual address    */
+	int		mtrr;	 /* MTRR slot used			    */
+				 /* Private data			    */
+} drm_map_t;
+
+typedef enum drm_lock_flags {
+	_DRM_LOCK_READY	     = 0x01, /* Wait until hardware is ready for DMA */
+	_DRM_LOCK_QUIESCENT  = 0x02, /* Wait until hardware quiescent	     */
+	_DRM_LOCK_FLUSH	     = 0x04, /* Flush this context's DMA queue first */
+	_DRM_LOCK_FLUSH_ALL  = 0x08, /* Flush all DMA queues first	     */
+				/* These *HALT* flags aren't supported yet
+				   -- they will be used to support the
+				   full-screen DGA-like mode. */
+	_DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues   */
+	_DRM_HALT_CUR_QUEUES = 0x20  /* Halt all current queues		     */
+} drm_lock_flags_t;
+
+typedef struct drm_lock {
+	int		 context;
+	drm_lock_flags_t flags;
+} drm_lock_t;
+
+typedef enum drm_dma_flags {	      /* These values *MUST* match xf86drm.h */
+				      /* Flags for DMA buffer dispatch	     */
+	_DRM_DMA_BLOCK	      = 0x01, /* Block until buffer dispatched.
+					 Note, the buffer may not yet have
+					 been processed by the hardware --
+					 getting a hardware lock with the
+					 hardware quiescent will ensure
+					 that the buffer has been
+					 processed.			     */
+	_DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held	     */
+	_DRM_DMA_PRIORITY     = 0x04, /* High priority dispatch		     */
+
+				      /* Flags for DMA buffer request	     */
+	_DRM_DMA_WAIT	      = 0x10, /* Wait for free buffers		     */
+	_DRM_DMA_SMALLER_OK   = 0x20, /* Smaller-than-requested buffers ok   */
+	_DRM_DMA_LARGER_OK    = 0x40  /* Larger-than-requested buffers ok    */
+} drm_dma_flags_t;
+
+typedef struct drm_buf_desc {
+	int	      count;	 /* Number of buffers of this size	     */
+	int	      size;	 /* Size in bytes			     */
+	int	      low_mark;	 /* Low water mark			     */
+	int	      high_mark; /* High water mark			     */
+	enum {
+		_DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA  */
+		_DRM_AGP_BUFFER = 0x02  /* Buffer is in agp space            */
+	}	      flags;
+	unsigned long agp_start; /* Start address of where the agp buffers
+				  * are in the agp aperture */
+} drm_buf_desc_t;
+
+typedef struct drm_buf_info {
+	int	       count;	/* Entries in list			     */
+	drm_buf_desc_t *list;
+} drm_buf_info_t;
+
+typedef struct drm_buf_free {
+	int	       count;
+	int	       *list;
+} drm_buf_free_t;
+
+typedef struct drm_buf_pub {
+	int		  idx;	       /* Index into master buflist	     */
+	int		  total;       /* Buffer size			     */
+	int		  used;	       /* Amount of buffer in use (for DMA)  */
+	void		  *address;    /* Address of buffer		     */
+} drm_buf_pub_t;
+
+typedef struct drm_buf_map {
+	int	      count;	/* Length of buflist			    */
+	void	      *virtual;	/* Mmaped area in user-virtual		    */
+	drm_buf_pub_t *list;	/* Buffer information			    */
+} drm_buf_map_t;
+
+typedef struct drm_dma {
+				/* Indices here refer to the offset into
+				   buflist in drm_buf_get_t.  */
+	int		context;	  /* Context handle		    */
+	int		send_count;	  /* Number of buffers to send	    */
+	int		*send_indices;	  /* List of handles to buffers	    */
+	int		*send_sizes;	  /* Lengths of data to send	    */
+	drm_dma_flags_t flags;		  /* Flags			    */
+	int		request_count;	  /* Number of buffers requested    */
+	int		request_size;	  /* Desired size for buffers	    */
+	int		*request_indices; /* Buffer information		    */
+	int		*request_sizes;
+	int		granted_count;	  /* Number of buffers granted	    */
+} drm_dma_t;
+
+typedef enum {
+	_DRM_CONTEXT_PRESERVED = 0x01,
+	_DRM_CONTEXT_2DONLY    = 0x02
+} drm_ctx_flags_t;
+
+typedef struct drm_ctx {
+	drm_context_t	handle;
+	drm_ctx_flags_t flags;
+} drm_ctx_t;
+
+typedef struct drm_ctx_res {
+	int		count;
+	drm_ctx_t	*contexts;
+} drm_ctx_res_t;
+
+typedef struct drm_draw {
+	drm_drawable_t	handle;
+} drm_draw_t;
+
+typedef struct drm_auth {
+	drm_magic_t	magic;
+} drm_auth_t;
+
+typedef struct drm_irq_busid {
+	int irq;
+	int busnum;
+	int devnum;
+	int funcnum;
+} drm_irq_busid_t;
+
+typedef struct drm_agp_mode {
+	unsigned long mode;
+} drm_agp_mode_t;
+
+				/* For drm_agp_alloc -- allocated a buffer */
+typedef struct drm_agp_buffer {
+	unsigned long size;	/* In bytes -- will round to page boundary */
+	unsigned long handle;	/* Used for BIND/UNBIND ioctls */
+	unsigned long type;     /* Type of memory to allocate  */
+        unsigned long physical; /* Physical used by i810       */
+} drm_agp_buffer_t;
+
+				/* For drm_agp_bind */
+typedef struct drm_agp_binding {
+	unsigned long handle;   /* From drm_agp_buffer */
+	unsigned long offset;	/* In bytes -- will round to page boundary */
+} drm_agp_binding_t;
+
+typedef struct drm_agp_info {
+	int            agp_version_major;
+	int            agp_version_minor;
+	unsigned long  mode;
+	unsigned long  aperture_base;  /* physical address */
+	unsigned long  aperture_size;  /* bytes */
+	unsigned long  memory_allowed; /* bytes */
+	unsigned long  memory_used;
+
+				/* PCI information */
+	unsigned short id_vendor;
+	unsigned short id_device;
+} drm_agp_info_t;
+
+#define DRM_IOCTL_BASE			'd'
+#define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
+#define DRM_IOR(nr,size)		_IOR(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOW(nr,size)		_IOW(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOWR(nr,size)		_IOWR(DRM_IOCTL_BASE,nr,size)
+
+
+#define DRM_IOCTL_VERSION		DRM_IOWR(0x00, drm_version_t)
+#define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, drm_unique_t)
+#define DRM_IOCTL_GET_MAGIC		DRM_IOR( 0x02, drm_auth_t)
+#define DRM_IOCTL_IRQ_BUSID		DRM_IOWR(0x03, drm_irq_busid_t)
+
+#define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, drm_unique_t)
+#define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, drm_auth_t)
+#define DRM_IOCTL_BLOCK			DRM_IOWR(0x12, drm_block_t)
+#define DRM_IOCTL_UNBLOCK		DRM_IOWR(0x13, drm_block_t)
+#define DRM_IOCTL_CONTROL		DRM_IOW( 0x14, drm_control_t)
+#define DRM_IOCTL_ADD_MAP		DRM_IOWR(0x15, drm_map_t)
+#define DRM_IOCTL_ADD_BUFS		DRM_IOWR(0x16, drm_buf_desc_t)
+#define DRM_IOCTL_MARK_BUFS		DRM_IOW( 0x17, drm_buf_desc_t)
+#define DRM_IOCTL_INFO_BUFS		DRM_IOWR(0x18, drm_buf_info_t)
+#define DRM_IOCTL_MAP_BUFS		DRM_IOWR(0x19, drm_buf_map_t)
+#define DRM_IOCTL_FREE_BUFS		DRM_IOW( 0x1a, drm_buf_free_t)
+
+#define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, drm_ctx_t)
+#define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, drm_ctx_t)
+#define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, drm_ctx_t)
+#define DRM_IOCTL_GET_CTX		DRM_IOWR(0x23, drm_ctx_t)
+#define DRM_IOCTL_SWITCH_CTX		DRM_IOW( 0x24, drm_ctx_t)
+#define DRM_IOCTL_NEW_CTX		DRM_IOW( 0x25, drm_ctx_t)
+#define DRM_IOCTL_RES_CTX		DRM_IOWR(0x26, drm_ctx_res_t)
+#define DRM_IOCTL_ADD_DRAW		DRM_IOWR(0x27, drm_draw_t)
+#define DRM_IOCTL_RM_DRAW		DRM_IOWR(0x28, drm_draw_t)
+#define DRM_IOCTL_DMA			DRM_IOWR(0x29, drm_dma_t)
+#define DRM_IOCTL_LOCK			DRM_IOW( 0x2a, drm_lock_t)
+#define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, drm_lock_t)
+#define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, drm_lock_t)
+
+#define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)
+#define DRM_IOCTL_AGP_RELEASE		DRM_IO(  0x31)
+#define DRM_IOCTL_AGP_ENABLE		DRM_IOW( 0x32, drm_agp_mode_t)
+#define DRM_IOCTL_AGP_INFO		DRM_IOR( 0x33, drm_agp_info_t)
+#define DRM_IOCTL_AGP_ALLOC		DRM_IOWR(0x34, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_FREE		DRM_IOW( 0x35, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, drm_agp_binding_t)
+#define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, drm_agp_binding_t)
+
+/* Mga specific ioctls */
+#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_SWAP		DRM_IOW( 0x41, drm_mga_swap_t)
+#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x42, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x43, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x44, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x45, drm_lock_t )
+#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x47, drm_mga_blit_t)
+
+/* I810 specific ioctls */
+#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
+#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
+#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
+#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
+
+/* Rage 128 specific ioctls */
+#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
+#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
+#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
+#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_PACKET		DRM_IOWR(0x4e, drm_r128_packet_t)
+
+/* Radeon specific ioctls */
+#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)
+#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)
+#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)
+#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_BLIT		DRM_IOW( 0x4b, drm_radeon_blit_t)
+#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)
+
+#ifdef CONFIG_DRM40_SIS
+/* SiS specific ioctls */
+#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
+#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
+#endif
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/drmP.h lia64-2.4/drivers/char/drm-4.0/drmP.h
--- linux-2.4.16/drivers/char/drm-4.0/drmP.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/drmP.h	Mon Nov 26 18:08:41 2001
@@ -0,0 +1,839 @@
+/* drmP.h -- Private header for Direct Rendering Manager -*- linux-c -*-
+ * Created: Mon Jan  4 10:05:05 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#ifndef _DRM_P_H_
+#define _DRM_P_H_
+
+#ifdef __KERNEL__
+#ifdef __alpha__
+/* add include of current.h so that "current" is defined
+ * before static inline funcs in wait.h. Doing this so we
+ * can build the DRM (part of PI DRI). 4/21/2000 S + B */
+#include <asm/current.h>
+#endif /* __alpha__ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/miscdevice.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/file.h>
+#include <linux/pci.h>
+#include <linux/wrapper.h>
+#include <linux/version.h>
+#include <linux/sched.h>
+#include <linux/smp_lock.h>	/* For (un)lock_kernel */
+#include <linux/mm.h>
+#ifdef __alpha__
+#include <asm/pgtable.h> /* For pte_wrprotect */
+#endif
+#include <asm/io.h>
+#include <asm/mman.h>
+#include <asm/uaccess.h>
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+#include <linux/types.h>
+#include <linux/agp_backend.h>
+#endif
+#if LINUX_VERSION_CODE >= 0x020100 /* KERNEL_VERSION(2,1,0) */
+#include <linux/tqueue.h>
+#include <linux/poll.h>
+#endif
+#if LINUX_VERSION_CODE < 0x020400
+#include "compat-pre24.h"
+#endif
+#include "drm.h"
+
+#define DRM_DEBUG_CODE 2	  /* Include debugging code (if > 1, then
+				     also include looping detection. */
+#define DRM_DMA_HISTOGRAM 1	  /* Make histogram of DMA latency. */
+
+#define DRM_HASH_SIZE	      16 /* Size of key hash table		  */
+#define DRM_KERNEL_CONTEXT    0	 /* Change drm_resctx if changed	  */
+#define DRM_RESERVED_CONTEXTS 1	 /* Change drm_resctx if changed	  */
+#define DRM_LOOPING_LIMIT     5000000
+#define DRM_BSZ		      1024 /* Buffer size for /dev/drm? output	  */
+#define DRM_TIME_SLICE	      (HZ/20)  /* Time slice for GLXContexts	  */
+#define DRM_LOCK_SLICE	      1	/* Time slice for lock, in jiffies	  */
+
+#define DRM_FLAG_DEBUG	  0x01
+#define DRM_FLAG_NOCTX	  0x02
+
+#define DRM_MEM_DMA	   0
+#define DRM_MEM_SAREA	   1
+#define DRM_MEM_DRIVER	   2
+#define DRM_MEM_MAGIC	   3
+#define DRM_MEM_IOCTLS	   4
+#define DRM_MEM_MAPS	   5
+#define DRM_MEM_VMAS	   6
+#define DRM_MEM_BUFS	   7
+#define DRM_MEM_SEGS	   8
+#define DRM_MEM_PAGES	   9
+#define DRM_MEM_FILES	  10
+#define DRM_MEM_QUEUES	  11
+#define DRM_MEM_CMDS	  12
+#define DRM_MEM_MAPPINGS  13
+#define DRM_MEM_BUFLISTS  14
+#define DRM_MEM_AGPLISTS  15
+#define DRM_MEM_TOTALAGP  16
+#define DRM_MEM_BOUNDAGP  17
+#define DRM_MEM_CTXBITMAP 18
+
+#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
+
+				/* Backward compatibility section */
+				/* _PAGE_WT changed to _PAGE_PWT in 2.2.6 */
+#ifndef _PAGE_PWT
+#define _PAGE_PWT _PAGE_WT
+#endif
+				/* Wait queue declarations changed in 2.3.1 */
+#ifndef DECLARE_WAITQUEUE
+#define DECLARE_WAITQUEUE(w,c) struct wait_queue w = { c, NULL }
+typedef struct wait_queue *wait_queue_head_t;
+#define init_waitqueue_head(q) *q = NULL;
+#endif
+
+				/* _PAGE_4M changed to _PAGE_PSE in 2.3.23 */
+#ifndef _PAGE_PSE
+#define _PAGE_PSE _PAGE_4M
+#endif
+
+				/* vm_offset changed to vm_pgoff in 2.3.25 */
+#if LINUX_VERSION_CODE < 0x020319
+#define VM_OFFSET(vma) ((vma)->vm_offset)
+#else
+#define VM_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT)
+#endif
+
+				/* *_nopage return values defined in 2.3.26 */
+#ifndef NOPAGE_SIGBUS
+#define NOPAGE_SIGBUS 0
+#endif
+#ifndef NOPAGE_OOM
+#define NOPAGE_OOM 0
+#endif
+
+				/* module_init/module_exit added in 2.3.13 */
+#ifndef module_init
+#define module_init(x)  int init_module(void) { return x(); }
+#endif
+#ifndef module_exit
+#define module_exit(x)  void cleanup_module(void) { x(); }
+#endif
+
+				/* Generic cmpxchg added in 2.3.x */
+#ifndef __HAVE_ARCH_CMPXCHG
+				/* Include this here so that driver can be
+                                   used with older kernels. */
+#if defined(__alpha__)
+static __inline__ unsigned long
+__cmpxchg_u32(volatile int *m, int old, int new)
+{
+	unsigned long prev, cmp;
+
+	__asm__ __volatile__(
+	"1:	ldl_l %0,%2\n"
+	"	cmpeq %0,%3,%1\n"
+	"	beq %1,2f\n"
+	"	mov %4,%1\n"
+	"	stl_c %1,%2\n"
+	"	beq %1,3f\n"
+	"2:	mb\n"
+	".subsection 2\n"
+	"3:	br 1b\n"
+	".previous"
+	: "=&r"(prev), "=&r"(cmp), "=m"(*m)
+	: "r"((long) old), "r"(new), "m"(*m));
+
+	return prev;
+}
+
+static __inline__ unsigned long
+__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
+{
+	unsigned long prev, cmp;
+
+	__asm__ __volatile__(
+	"1:	ldq_l %0,%2\n"
+	"	cmpeq %0,%3,%1\n"
+	"	beq %1,2f\n"
+	"	mov %4,%1\n"
+	"	stq_c %1,%2\n"
+	"	beq %1,3f\n"
+	"2:	mb\n"
+	".subsection 2\n"
+	"3:	br 1b\n"
+	".previous"
+	: "=&r"(prev), "=&r"(cmp), "=m"(*m)
+	: "r"((long) old), "r"(new), "m"(*m));
+
+	return prev;
+}
+
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+	switch (size) {
+		case 4:
+			return __cmpxchg_u32(ptr, old, new);
+		case 8:
+			return __cmpxchg_u64(ptr, old, new);
+	}
+	return old;
+}
+#define cmpxchg(ptr,o,n)						 \
+  ({									 \
+     __typeof__(*(ptr)) _o_ = (o);					 \
+     __typeof__(*(ptr)) _n_ = (n);					 \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
+				    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+#elif __i386__
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+				      unsigned long new, int size)
+{
+	unsigned long prev;
+	switch (size) {
+	case 1:
+		__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
+				     : "=a"(prev)
+				     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+				     : "memory");
+		return prev;
+	case 2:
+		__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
+				     : "=a"(prev)
+				     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+				     : "memory");
+		return prev;
+	case 4:
+		__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
+				     : "=a"(prev)
+				     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+				     : "memory");
+		return prev;
+	}
+	return old;
+}
+
+#define cmpxchg(ptr,o,n)						\
+  ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),		\
+				 (unsigned long)(n),sizeof(*(ptr))))
+#endif /* i386 & alpha */
+#endif
+
+				/* Macros to make printk easier */
+#define DRM_ERROR(fmt, arg...) \
+	printk(KERN_ERR "[" DRM_NAME ":" __FUNCTION__ "] *ERROR* " fmt , ##arg)
+#define DRM_MEM_ERROR(area, fmt, arg...) \
+	printk(KERN_ERR "[" DRM_NAME ":" __FUNCTION__ ":%s] *ERROR* " fmt , \
+	       drm_mem_stats[area].name , ##arg)
+#define DRM_INFO(fmt, arg...)  printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg)
+
+#if DRM_DEBUG_CODE
+#define DRM_DEBUG(fmt, arg...)						  \
+	do {								  \
+		if (drm_flags&DRM_FLAG_DEBUG)				  \
+			printk(KERN_DEBUG				  \
+			       "[" DRM_NAME ":" __FUNCTION__ "] " fmt ,	  \
+			       ##arg);					  \
+	} while (0)
+#else
+#define DRM_DEBUG(fmt, arg...)		 do { } while (0)
+#endif
+
+#define DRM_PROC_LIMIT (PAGE_SIZE-80)
+
+#define DRM_PROC_PRINT(fmt, arg...)	   \
+   len += sprintf(&buf[len], fmt , ##arg); \
+   if (len > DRM_PROC_LIMIT) return len;
+
+#define DRM_PROC_PRINT_RET(ret, fmt, arg...)	    \
+   len += sprintf(&buf[len], fmt , ##arg);	    \
+   if (len > DRM_PROC_LIMIT) { ret; return len; }
+
+				/* Internal types and structures */
+#define DRM_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
+#define DRM_MIN(a,b) ((a)<(b)?(a):(b))
+#define DRM_MAX(a,b) ((a)>(b)?(a):(b))
+
+#define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1))
+#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x))
+#define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist)
+
+typedef int drm_ioctl_t(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+
+typedef struct drm_ioctl_desc {
+	drm_ioctl_t	     *func;
+	int		     auth_needed;
+	int		     root_only;
+} drm_ioctl_desc_t;
+
+typedef struct drm_devstate {
+	pid_t		  owner;	/* X server pid holding x_lock */
+	
+} drm_devstate_t;
+
+typedef struct drm_magic_entry {
+	drm_magic_t	       magic;
+	struct drm_file	       *priv;
+	struct drm_magic_entry *next;
+} drm_magic_entry_t;
+
+typedef struct drm_magic_head {
+	struct drm_magic_entry *head;
+	struct drm_magic_entry *tail;
+} drm_magic_head_t;
+
+typedef struct drm_vma_entry {
+	struct vm_area_struct *vma;
+	struct drm_vma_entry  *next;
+	pid_t		      pid;
+} drm_vma_entry_t;
+
+typedef struct drm_buf {
+	int		  idx;	       /* Index into master buflist	     */
+	int		  total;       /* Buffer size			     */
+	int		  order;       /* log-base-2(total)		     */
+	int		  used;	       /* Amount of buffer in use (for DMA)  */
+	unsigned long	  offset;      /* Byte offset (used internally)	     */
+	void		  *address;    /* Address of buffer		     */
+	unsigned long	  bus_address; /* Bus address of buffer		     */
+	struct drm_buf	  *next;       /* Kernel-only: used for free list    */
+	__volatile__ int  waiting;     /* On kernel DMA queue		     */
+	__volatile__ int  pending;     /* On hardware DMA queue		     */
+	wait_queue_head_t dma_wait;    /* Processes waiting		     */
+	pid_t		  pid;	       /* PID of holding process	     */
+	int		  context;     /* Kernel queue for this buffer	     */
+	int		  while_locked;/* Dispatch this buffer while locked  */
+	enum {
+		DRM_LIST_NONE	 = 0,
+		DRM_LIST_FREE	 = 1,
+		DRM_LIST_WAIT	 = 2,
+		DRM_LIST_PEND	 = 3,
+		DRM_LIST_PRIO	 = 4,
+		DRM_LIST_RECLAIM = 5
+	}		  list;	       /* Which list we're on		     */
+
+#if DRM_DMA_HISTOGRAM
+	cycles_t	  time_queued;	   /* Queued to kernel DMA queue     */
+	cycles_t	  time_dispatched; /* Dispatched to hardware	     */
+	cycles_t	  time_completed;  /* Completed by hardware	     */
+	cycles_t	  time_freed;	   /* Back on freelist		     */
+#endif
+
+	int		  dev_priv_size; /* Size of buffer private stoarge   */
+	void		  *dev_private;  /* Per-buffer private storage       */
+} drm_buf_t;
+
+#if DRM_DMA_HISTOGRAM
+#define DRM_DMA_HISTOGRAM_SLOTS		  9
+#define DRM_DMA_HISTOGRAM_INITIAL	 10
+#define DRM_DMA_HISTOGRAM_NEXT(current)	 ((current)*10)
+typedef struct drm_histogram {
+	atomic_t	  total;
+
+	atomic_t	  queued_to_dispatched[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  dispatched_to_completed[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  completed_to_freed[DRM_DMA_HISTOGRAM_SLOTS];
+
+	atomic_t	  queued_to_completed[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  queued_to_freed[DRM_DMA_HISTOGRAM_SLOTS];
+
+	atomic_t	  dma[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  schedule[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  ctx[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  lacq[DRM_DMA_HISTOGRAM_SLOTS];
+	atomic_t	  lhld[DRM_DMA_HISTOGRAM_SLOTS];
+} drm_histogram_t;
+#endif
+
+				/* bufs is one longer than it has to be */
+typedef struct drm_waitlist {
+	int		  count;	/* Number of possible buffers	   */
+	drm_buf_t	  **bufs;	/* List of pointers to buffers	   */
+	drm_buf_t	  **rp;		/* Read pointer			   */
+	drm_buf_t	  **wp;		/* Write pointer		   */
+	drm_buf_t	  **end;	/* End pointer			   */
+	spinlock_t	  read_lock;
+	spinlock_t	  write_lock;
+} drm_waitlist_t;
+
+typedef struct drm_freelist {
+	int		  initialized; /* Freelist in use		   */
+	atomic_t	  count;       /* Number of free buffers	   */
+	drm_buf_t	  *next;       /* End pointer			   */
+
+	wait_queue_head_t waiting;     /* Processes waiting on free bufs   */
+	int		  low_mark;    /* Low water mark		   */
+	int		  high_mark;   /* High water mark		   */
+	atomic_t	  wfh;	       /* If waiting for high mark	   */
+	spinlock_t        lock;
+} drm_freelist_t;
+
+typedef struct drm_buf_entry {
+	int		  buf_size;
+	int		  buf_count;
+	drm_buf_t	  *buflist;
+	int		  seg_count;
+	int		  page_order;
+	unsigned long	  *seglist;
+
+	drm_freelist_t	  freelist;
+} drm_buf_entry_t;
+
+typedef struct drm_hw_lock {
+	__volatile__ unsigned int lock;
+	char			  padding[60]; /* Pad to cache line */
+} drm_hw_lock_t;
+
+typedef struct drm_file {
+	int		  authenticated;
+	int		  minor;
+	pid_t		  pid;
+	uid_t		  uid;
+	drm_magic_t	  magic;
+	unsigned long	  ioctl_count;
+	struct drm_file	  *next;
+	struct drm_file	  *prev;
+	struct drm_device *dev;
+	int 		  remove_auth_on_close;
+} drm_file_t;
+
+
+typedef struct drm_queue {
+	atomic_t	  use_count;	/* Outstanding uses (+1)	    */
+	atomic_t	  finalization;	/* Finalization in progress	    */
+	atomic_t	  block_count;	/* Count of processes waiting	    */
+	atomic_t	  block_read;	/* Queue blocked for reads	    */
+	wait_queue_head_t read_queue;	/* Processes waiting on block_read  */
+	atomic_t	  block_write;	/* Queue blocked for writes	    */
+	wait_queue_head_t write_queue;	/* Processes waiting on block_write */
+	atomic_t	  total_queued;	/* Total queued statistic	    */
+	atomic_t	  total_flushed;/* Total flushes statistic	    */
+	atomic_t	  total_locks;	/* Total locks statistics	    */
+	drm_ctx_flags_t	  flags;	/* Context preserving and 2D-only   */
+	drm_waitlist_t	  waitlist;	/* Pending buffers		    */
+	wait_queue_head_t flush_queue;	/* Processes waiting until flush    */
+} drm_queue_t;
+
+typedef struct drm_lock_data {
+	drm_hw_lock_t	  *hw_lock;	/* Hardware lock		   */
+	pid_t		  pid;		/* PID of lock holder (0=kernel)   */
+	wait_queue_head_t lock_queue;	/* Queue of blocked processes	   */
+	unsigned long	  lock_time;	/* Time of last lock in jiffies	   */
+} drm_lock_data_t;
+
+typedef struct drm_device_dma {
+				/* Performance Counters */
+	atomic_t	  total_prio;	/* Total DRM_DMA_PRIORITY	   */
+	atomic_t	  total_bytes;	/* Total bytes DMA'd		   */
+	atomic_t	  total_dmas;	/* Total DMA buffers dispatched	   */
+
+	atomic_t	  total_missed_dma;  /* Missed drm_do_dma	    */
+	atomic_t	  total_missed_lock; /* Missed lock in drm_do_dma   */
+	atomic_t	  total_missed_free; /* Missed drm_free_this_buffer */
+	atomic_t	  total_missed_sched;/* Missed drm_dma_schedule	    */
+
+	atomic_t	  total_tried;	/* Tried next_buffer		    */
+	atomic_t	  total_hit;	/* Sent next_buffer		    */
+	atomic_t	  total_lost;	/* Lost interrupt		    */
+
+	drm_buf_entry_t	  bufs[DRM_MAX_ORDER+1];
+	int		  buf_count;
+	drm_buf_t	  **buflist;	/* Vector of pointers info bufs	   */
+	int		  seg_count;
+	int		  page_count;
+	unsigned long	  *pagelist;
+	unsigned long	  byte_count;
+	enum {
+	   _DRM_DMA_USE_AGP = 0x01
+	} flags;
+
+				/* DMA support */
+	drm_buf_t	  *this_buffer;	/* Buffer being sent		   */
+	drm_buf_t	  *next_buffer; /* Selected buffer to send	   */
+	drm_queue_t	  *next_queue;	/* Queue from which buffer selected*/
+	wait_queue_head_t waiting;	/* Processes waiting on free bufs  */
+} drm_device_dma_t;
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+typedef struct drm_agp_mem {
+	unsigned long      handle;
+	agp_memory         *memory;
+	unsigned long      bound; /* address */
+	int                pages;
+	struct drm_agp_mem *prev;
+	struct drm_agp_mem *next;
+} drm_agp_mem_t;
+
+typedef struct drm_agp_head {
+	agp_kern_info      agp_info;
+	const char         *chipset;
+	drm_agp_mem_t      *memory;
+	unsigned long      mode;
+	int                enabled;
+	int                acquired;
+	unsigned long      base;
+   	int 		   agp_mtrr;
+	int		   cant_use_aperture;
+	unsigned long	   page_mask;
+} drm_agp_head_t;
+#endif
+
+typedef struct drm_sigdata {
+	int           context;
+	drm_hw_lock_t *lock;
+} drm_sigdata_t;
+
+typedef struct drm_device {
+	const char	  *name;	/* Simple driver name		   */
+	char		  *unique;	/* Unique identifier: e.g., busid  */
+	int		  unique_len;	/* Length of unique field	   */
+	dev_t		  device;	/* Device number for mknod	   */
+	char		  *devname;	/* For /proc/interrupts		   */
+
+	int		  blocked;	/* Blocked due to VC switch?	   */
+	struct proc_dir_entry *root;	/* Root for this device's entries  */
+
+				/* Locks */
+	spinlock_t	  count_lock;	/* For inuse, open_count, buf_use  */
+	struct semaphore  struct_sem;	/* For others			   */
+
+				/* Usage Counters */
+	int		  open_count;	/* Outstanding files open	   */
+	atomic_t	  ioctl_count;	/* Outstanding IOCTLs pending	   */
+	atomic_t	  vma_count;	/* Outstanding vma areas open	   */
+	int		  buf_use;	/* Buffers in use -- cannot alloc  */
+	atomic_t	  buf_alloc;	/* Buffer allocation in progress   */
+
+				/* Performance Counters */
+	atomic_t	  total_open;
+	atomic_t	  total_close;
+	atomic_t	  total_ioctl;
+	atomic_t	  total_irq;	/* Total interruptions		   */
+	atomic_t	  total_ctx;	/* Total context switches	   */
+
+	atomic_t	  total_locks;
+	atomic_t	  total_unlocks;
+	atomic_t	  total_contends;
+	atomic_t	  total_sleeps;
+
+				/* Authentication */
+	drm_file_t	  *file_first;
+	drm_file_t	  *file_last;
+	drm_magic_head_t  magiclist[DRM_HASH_SIZE];
+
+				/* Memory management */
+	drm_map_t	  **maplist;	/* Vector of pointers to regions   */
+	int		  map_count;	/* Number of mappable regions	   */
+
+	drm_vma_entry_t	  *vmalist;	/* List of vmas (for debugging)	   */
+	drm_lock_data_t	  lock;		/* Information on hardware lock	   */
+
+				/* DMA queues (contexts) */
+	int		  queue_count;	/* Number of active DMA queues	   */
+	int		  queue_reserved; /* Number of reserved DMA queues */
+	int		  queue_slots;	/* Actual length of queuelist	   */
+	drm_queue_t	  **queuelist;	/* Vector of pointers to DMA queues */
+	drm_device_dma_t  *dma;		/* Optional pointer for DMA support */
+
+				/* Context support */
+	int		  irq;		/* Interrupt used by board	   */
+	__volatile__ long context_flag;	/* Context swapping flag	   */
+	__volatile__ long interrupt_flag; /* Interruption handler flag	   */
+	__volatile__ long dma_flag;	/* DMA dispatch flag		   */
+	struct timer_list timer;	/* Timer for delaying ctx switch   */
+	wait_queue_head_t context_wait; /* Processes waiting on ctx switch */
+	int		  last_checked;	/* Last context checked for DMA	   */
+	int		  last_context;	/* Last current context		   */
+	unsigned long	  last_switch;	/* jiffies at last context switch  */
+	struct tq_struct  tq;
+	cycles_t	  ctx_start;
+	cycles_t	  lck_start;
+#if DRM_DMA_HISTOGRAM
+	drm_histogram_t	  histo;
+#endif
+
+				/* Callback to X server for context switch
+				   and for heavy-handed reset. */
+	char		  buf[DRM_BSZ]; /* Output buffer		   */
+	char		  *buf_rp;	/* Read pointer			   */
+	char		  *buf_wp;	/* Write pointer		   */
+	char		  *buf_end;	/* End pointer			   */
+	struct fasync_struct *buf_async;/* Processes waiting for SIGIO	   */
+	wait_queue_head_t buf_readers;	/* Processes waiting to read	   */
+	wait_queue_head_t buf_writers;	/* Processes waiting to ctx switch */
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	drm_agp_head_t    *agp;
+#endif
+	unsigned long     *ctx_bitmap;
+	void		  *dev_private;
+	drm_sigdata_t     sigdata; /* For block_all_signals */
+	sigset_t          sigmask;
+} drm_device_t;
+
+				/* Internal function definitions */
+
+				/* Misc. support (init.c) */
+extern int	     drm_flags;
+extern void	     drm_parse_options(char *s);
+extern int           drm_cpu_valid(void);
+
+
+				/* Device support (fops.c) */
+extern int	     drm_open_helper(struct inode *inode, struct file *filp,
+				     drm_device_t *dev);
+extern int	     drm_flush(struct file *filp);
+extern int	     drm_release(struct inode *inode, struct file *filp);
+extern int	     drm_fasync(int fd, struct file *filp, int on);
+extern ssize_t	     drm_read(struct file *filp, char *buf, size_t count,
+			      loff_t *off);
+extern int	     drm_write_string(drm_device_t *dev, const char *s);
+extern unsigned int  drm_poll(struct file *filp, struct poll_table_struct *wait);
+
+				/* Mapping support (vm.c) */
+#if LINUX_VERSION_CODE < 0x020317
+extern unsigned long drm_vm_nopage(struct vm_area_struct *vma,
+				   unsigned long address,
+				   int write_access);
+extern unsigned long drm_vm_shm_nopage(struct vm_area_struct *vma,
+				       unsigned long address,
+				       int write_access);
+extern unsigned long drm_vm_shm_nopage_lock(struct vm_area_struct *vma,
+					    unsigned long address,
+					    int write_access);
+extern unsigned long drm_vm_dma_nopage(struct vm_area_struct *vma,
+				       unsigned long address,
+				       int write_access);
+#else
+				/* Return type changed in 2.3.23 */
+extern struct page *drm_vm_nopage(struct vm_area_struct *vma,
+				  unsigned long address,
+				  int write_access);
+extern struct page *drm_vm_shm_nopage(struct vm_area_struct *vma,
+				      unsigned long address,
+				      int write_access);
+extern struct page *drm_vm_shm_nopage_lock(struct vm_area_struct *vma,
+					   unsigned long address,
+					   int write_access);
+extern struct page *drm_vm_dma_nopage(struct vm_area_struct *vma,
+				      unsigned long address,
+				      int write_access);
+#endif
+extern void	     drm_vm_open(struct vm_area_struct *vma);
+extern void	     drm_vm_close(struct vm_area_struct *vma);
+extern int	     drm_mmap_dma(struct file *filp,
+				  struct vm_area_struct *vma);
+extern int	     drm_mmap(struct file *filp, struct vm_area_struct *vma);
+
+
+				/* Proc support (proc.c) */
+extern int	     drm_proc_init(drm_device_t *dev);
+extern int	     drm_proc_cleanup(void);
+
+				/* Memory management support (memory.c) */
+extern void	     drm_mem_init(void);
+extern int	     drm_mem_info(char *buf, char **start, off_t offset,
+				  int len, int *eof, void *data);
+extern void	     *drm_alloc(size_t size, int area);
+extern void	     *drm_realloc(void *oldpt, size_t oldsize, size_t size,
+				  int area);
+extern char	     *drm_strdup(const char *s, int area);
+extern void	     drm_strfree(const char *s, int area);
+extern void	     drm_free(void *pt, size_t size, int area);
+extern unsigned long drm_alloc_pages(int order, int area);
+extern void	     drm_free_pages(unsigned long address, int order,
+				    int area);
+extern void	     *drm_ioremap(unsigned long offset, unsigned long size,
+							drm_device_t *dev);
+extern void	     drm_ioremapfree(void *pt, unsigned long size,
+							drm_device_t *dev);
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+extern agp_memory    *drm_alloc_agp(int pages, u32 type);
+extern int           drm_free_agp(agp_memory *handle, int pages);
+extern int           drm_bind_agp(agp_memory *handle, unsigned int start);
+extern int           drm_unbind_agp(agp_memory *handle);
+#endif
+
+
+				/* Buffer management support (bufs.c) */
+extern int	     drm_order(unsigned long size);
+extern int	     drm_addmap(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_addbufs(struct inode *inode, struct file *filp,
+				 unsigned int cmd, unsigned long arg);
+extern int	     drm_infobufs(struct inode *inode, struct file *filp,
+				  unsigned int cmd, unsigned long arg);
+extern int	     drm_markbufs(struct inode *inode, struct file *filp,
+				  unsigned int cmd, unsigned long arg);
+extern int	     drm_freebufs(struct inode *inode, struct file *filp,
+				  unsigned int cmd, unsigned long arg);
+extern int	     drm_mapbufs(struct inode *inode, struct file *filp,
+				 unsigned int cmd, unsigned long arg);
+
+
+				/* Buffer list management support (lists.c) */
+extern int	     drm_waitlist_create(drm_waitlist_t *bl, int count);
+extern int	     drm_waitlist_destroy(drm_waitlist_t *bl);
+extern int	     drm_waitlist_put(drm_waitlist_t *bl, drm_buf_t *buf);
+extern drm_buf_t     *drm_waitlist_get(drm_waitlist_t *bl);
+
+extern int	     drm_freelist_create(drm_freelist_t *bl, int count);
+extern int	     drm_freelist_destroy(drm_freelist_t *bl);
+extern int	     drm_freelist_put(drm_device_t *dev, drm_freelist_t *bl,
+				      drm_buf_t *buf);
+extern drm_buf_t     *drm_freelist_get(drm_freelist_t *bl, int block);
+
+				/* DMA support (gen_dma.c) */
+extern void	     drm_dma_setup(drm_device_t *dev);
+extern void	     drm_dma_takedown(drm_device_t *dev);
+extern void	     drm_free_buffer(drm_device_t *dev, drm_buf_t *buf);
+extern void	     drm_reclaim_buffers(drm_device_t *dev, pid_t pid);
+extern int	     drm_context_switch(drm_device_t *dev, int old, int new);
+extern int	     drm_context_switch_complete(drm_device_t *dev, int new);
+extern void	     drm_clear_next_buffer(drm_device_t *dev);
+extern int	     drm_select_queue(drm_device_t *dev,
+				      void (*wrapper)(unsigned long));
+extern int	     drm_dma_enqueue(drm_device_t *dev, drm_dma_t *dma);
+extern int	     drm_dma_get_buffers(drm_device_t *dev, drm_dma_t *dma);
+#if DRM_DMA_HISTOGRAM
+extern int	     drm_histogram_slot(unsigned long count);
+extern void	     drm_histogram_compute(drm_device_t *dev, drm_buf_t *buf);
+#endif
+
+
+				/* Misc. IOCTL support (ioctl.c) */
+extern int	     drm_irq_busid(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern int	     drm_getunique(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern int	     drm_setunique(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+
+
+				/* Context IOCTL support (context.c) */
+extern int	     drm_resctx(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_addctx(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_modctx(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_getctx(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_switchctx(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern int	     drm_newctx(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_rmctx(struct inode *inode, struct file *filp,
+			       unsigned int cmd, unsigned long arg);
+
+
+				/* Drawable IOCTL support (drawable.c) */
+extern int	     drm_adddraw(struct inode *inode, struct file *filp,
+				 unsigned int cmd, unsigned long arg);
+extern int	     drm_rmdraw(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+
+
+				/* Authentication IOCTL support (auth.c) */
+extern int	     drm_add_magic(drm_device_t *dev, drm_file_t *priv,
+				   drm_magic_t magic);
+extern int	     drm_remove_magic(drm_device_t *dev, drm_magic_t magic);
+extern int	     drm_getmagic(struct inode *inode, struct file *filp,
+				  unsigned int cmd, unsigned long arg);
+extern int	     drm_authmagic(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+
+
+				/* Locking IOCTL support (lock.c) */
+extern int	     drm_block(struct inode *inode, struct file *filp,
+			       unsigned int cmd, unsigned long arg);
+extern int	     drm_unblock(struct inode *inode, struct file *filp,
+				 unsigned int cmd, unsigned long arg);
+extern int	     drm_lock_take(__volatile__ unsigned int *lock,
+				   unsigned int context);
+extern int	     drm_lock_transfer(drm_device_t *dev,
+				       __volatile__ unsigned int *lock,
+				       unsigned int context);
+extern int	     drm_lock_free(drm_device_t *dev,
+				   __volatile__ unsigned int *lock,
+				   unsigned int context);
+extern int	     drm_finish(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg);
+extern int	     drm_flush_unblock(drm_device_t *dev, int context,
+				       drm_lock_flags_t flags);
+extern int	     drm_flush_block_and_flush(drm_device_t *dev, int context,
+					       drm_lock_flags_t flags);
+extern int           drm_notifier(void *priv);
+
+				/* Context Bitmap support (ctxbitmap.c) */
+extern int	     drm_ctxbitmap_init(drm_device_t *dev);
+extern void	     drm_ctxbitmap_cleanup(drm_device_t *dev);
+extern int	     drm_ctxbitmap_next(drm_device_t *dev);
+extern void	     drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle);
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+				/* AGP/GART support (agpsupport.c) */
+extern drm_agp_head_t *drm_agp_init(void);
+extern void           drm_agp_uninit(void);
+extern int            drm_agp_acquire(struct inode *inode, struct file *filp,
+				      unsigned int cmd, unsigned long arg);
+extern void           _drm_agp_release(void);
+extern int            drm_agp_release(struct inode *inode, struct file *filp,
+				      unsigned int cmd, unsigned long arg);
+extern int            drm_agp_enable(struct inode *inode, struct file *filp,
+				     unsigned int cmd, unsigned long arg);
+extern int            drm_agp_info(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern int            drm_agp_alloc(struct inode *inode, struct file *filp,
+				    unsigned int cmd, unsigned long arg);
+extern int            drm_agp_free(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern int            drm_agp_unbind(struct inode *inode, struct file *filp,
+				     unsigned int cmd, unsigned long arg);
+extern int            drm_agp_bind(struct inode *inode, struct file *filp,
+				   unsigned int cmd, unsigned long arg);
+extern agp_memory     *drm_agp_allocate_memory(size_t pages, u32 type);
+extern int            drm_agp_free_memory(agp_memory *handle);
+extern int            drm_agp_bind_memory(agp_memory *handle, off_t start);
+extern int            drm_agp_unbind_memory(agp_memory *handle);
+#endif
+#endif
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/ffb_context.c lia64-2.4/drivers/char/drm-4.0/ffb_context.c
--- linux-2.4.16/drivers/char/drm-4.0/ffb_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/ffb_context.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,540 @@
+/* $Id: ffb_context.c,v 1.4 2000/08/29 07:01:55 davem Exp $
+ * ffb_context.c: Creator/Creator3D DRI/DRM context switching.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ *
+ * Almost entirely stolen from tdfx_context.c, see there
+ * for authors.
+ */
+
+#include <linux/sched.h>
+#include <asm/upa.h>
+
+#include "drmP.h"
+
+#include "ffb_drv.h"
+
+static int ffb_alloc_queue(drm_device_t *dev, int is_2d_only)
+{
+	ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1);
+	int i;
+
+	for (i = 0; i < FFB_MAX_CTXS; i++) {
+		if (fpriv->hw_state[i] == NULL)
+			break;
+	}
+	if (i == FFB_MAX_CTXS)
+		return -1;
+
+	fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL);
+	if (fpriv->hw_state[i] == NULL)
+		return -1;
+
+	fpriv->hw_state[i]->is_2d_only = is_2d_only;
+
+	/* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */
+	return i + 1;
+}
+
+static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
+{
+	ffb_fbcPtr ffb = fpriv->regs;
+	struct ffb_hw_context *ctx;
+	int i;
+
+	ctx = fpriv->hw_state[idx - 1];
+	if (idx == 0 || ctx == NULL)
+		return;
+
+	if (ctx->is_2d_only) {
+		/* 2D applications only care about certain pieces
+		 * of state.
+		 */
+		ctx->drawop = upa_readl(&ffb->drawop);
+		ctx->ppc = upa_readl(&ffb->ppc);
+		ctx->wid = upa_readl(&ffb->wid);
+		ctx->fg = upa_readl(&ffb->fg);
+		ctx->bg = upa_readl(&ffb->bg);
+		ctx->xclip = upa_readl(&ffb->xclip);
+		ctx->fbc = upa_readl(&ffb->fbc);
+		ctx->rop = upa_readl(&ffb->rop);
+		ctx->cmp = upa_readl(&ffb->cmp);
+		ctx->matchab = upa_readl(&ffb->matchab);
+		ctx->magnab = upa_readl(&ffb->magnab);
+		ctx->pmask = upa_readl(&ffb->pmask);
+		ctx->xpmask = upa_readl(&ffb->xpmask);
+		ctx->lpat = upa_readl(&ffb->lpat);
+		ctx->fontxy = upa_readl(&ffb->fontxy);
+		ctx->fontw = upa_readl(&ffb->fontw);
+		ctx->fontinc = upa_readl(&ffb->fontinc);
+
+		/* stencil/stencilctl only exists on FFB2+ and later
+		 * due to the introduction of 3DRAM-III.
+		 */
+		if (fpriv->ffb_type == ffb2_vertical_plus ||
+		    fpriv->ffb_type == ffb2_horizontal_plus) {
+			ctx->stencil = upa_readl(&ffb->stencil);
+			ctx->stencilctl = upa_readl(&ffb->stencilctl);
+		}
+
+		for (i = 0; i < 32; i++)
+			ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
+		ctx->ucsr = upa_readl(&ffb->ucsr);
+		return;
+	}
+
+	/* Fetch drawop. */
+	ctx->drawop = upa_readl(&ffb->drawop);
+
+	/* If we were saving the vertex registers, this is where
+	 * we would do it.  We would save 32 32-bit words starting
+	 * at ffb->suvtx.
+	 */
+
+	/* Capture rendering attributes. */
+
+	ctx->ppc = upa_readl(&ffb->ppc);		/* Pixel Processor Control */
+	ctx->wid = upa_readl(&ffb->wid);		/* Current WID */
+	ctx->fg = upa_readl(&ffb->fg);			/* Constant FG color */
+	ctx->bg = upa_readl(&ffb->bg);			/* Constant BG color */
+	ctx->consty = upa_readl(&ffb->consty);		/* Constant Y */
+	ctx->constz = upa_readl(&ffb->constz);		/* Constant Z */
+	ctx->xclip = upa_readl(&ffb->xclip);		/* X plane clip */
+	ctx->dcss = upa_readl(&ffb->dcss);		/* Depth Cue Scale Slope */
+	ctx->vclipmin = upa_readl(&ffb->vclipmin);	/* Primary XY clip, minimum */
+	ctx->vclipmax = upa_readl(&ffb->vclipmax);	/* Primary XY clip, maximum */
+	ctx->vclipzmin = upa_readl(&ffb->vclipzmin);	/* Primary Z clip, minimum */
+	ctx->vclipzmax = upa_readl(&ffb->vclipzmax);	/* Primary Z clip, maximum */
+	ctx->dcsf = upa_readl(&ffb->dcsf);		/* Depth Cue Scale Front Bound */
+	ctx->dcsb = upa_readl(&ffb->dcsb);		/* Depth Cue Scale Back Bound */
+	ctx->dczf = upa_readl(&ffb->dczf);		/* Depth Cue Scale Z Front */
+	ctx->dczb = upa_readl(&ffb->dczb);		/* Depth Cue Scale Z Back */
+	ctx->blendc = upa_readl(&ffb->blendc);		/* Alpha Blend Control */
+	ctx->blendc1 = upa_readl(&ffb->blendc1);	/* Alpha Blend Color 1 */
+	ctx->blendc2 = upa_readl(&ffb->blendc2);	/* Alpha Blend Color 2 */
+	ctx->fbc = upa_readl(&ffb->fbc);		/* Frame Buffer Control */
+	ctx->rop = upa_readl(&ffb->rop);		/* Raster Operation */
+	ctx->cmp = upa_readl(&ffb->cmp);		/* Compare Controls */
+	ctx->matchab = upa_readl(&ffb->matchab);	/* Buffer A/B Match Ops */
+	ctx->matchc = upa_readl(&ffb->matchc);		/* Buffer C Match Ops */
+	ctx->magnab = upa_readl(&ffb->magnab);		/* Buffer A/B Magnitude Ops */
+	ctx->magnc = upa_readl(&ffb->magnc);		/* Buffer C Magnitude Ops */
+	ctx->pmask = upa_readl(&ffb->pmask);		/* RGB Plane Mask */
+	ctx->xpmask = upa_readl(&ffb->xpmask);		/* X Plane Mask */
+	ctx->ypmask = upa_readl(&ffb->ypmask);		/* Y Plane Mask */
+	ctx->zpmask = upa_readl(&ffb->zpmask);		/* Z Plane Mask */
+
+	/* Auxiliary Clips. */
+	ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
+	ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max);
+	ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min);
+	ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max);
+	ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min);
+	ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max);
+	ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
+	ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);
+
+	ctx->lpat = upa_readl(&ffb->lpat);		/* Line Pattern */
+	ctx->fontxy = upa_readl(&ffb->fontxy);		/* XY Font Coordinate */
+	ctx->fontw = upa_readl(&ffb->fontw);		/* Font Width */
+	ctx->fontinc = upa_readl(&ffb->fontinc);	/* Font X/Y Increment */
+
+	/* These registers/features only exist on FFB2 and later chips. */
+	if (fpriv->ffb_type >= ffb2_prototype) {
+		ctx->dcss1 = upa_readl(&ffb->dcss1);	/* Depth Cue Scale Slope 1 */
+		ctx->dcss2 = upa_readl(&ffb->dcss2);	/* Depth Cue Scale Slope 2 */
+		ctx->dcss2 = upa_readl(&ffb->dcss3);	/* Depth Cue Scale Slope 3 */
+		ctx->dcs2  = upa_readl(&ffb->dcs2);	/* Depth Cue Scale 2 */
+		ctx->dcs3  = upa_readl(&ffb->dcs3);	/* Depth Cue Scale 3 */
+		ctx->dcs4  = upa_readl(&ffb->dcs4);	/* Depth Cue Scale 4 */
+		ctx->dcd2  = upa_readl(&ffb->dcd2);	/* Depth Cue Depth 2 */
+		ctx->dcd3  = upa_readl(&ffb->dcd3);	/* Depth Cue Depth 3 */
+		ctx->dcd4  = upa_readl(&ffb->dcd4);	/* Depth Cue Depth 4 */
+
+		/* And stencil/stencilctl only exists on FFB2+ and later
+		 * due to the introduction of 3DRAM-III.
+		 */
+		if (fpriv->ffb_type == ffb2_vertical_plus ||
+		    fpriv->ffb_type == ffb2_horizontal_plus) {
+			ctx->stencil = upa_readl(&ffb->stencil);
+			ctx->stencilctl = upa_readl(&ffb->stencilctl);
+		}
+	}
+
+	/* Save the 32x32 area pattern. */
+	for (i = 0; i < 32; i++)
+		ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
+
+	/* Finally, stash away the User Constol/Status Register. */
+	ctx->ucsr = upa_readl(&ffb->ucsr);
+}
+
+static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
+{
+	ffb_fbcPtr ffb = fpriv->regs;
+	struct ffb_hw_context *ctx;
+	int i;
+
+	ctx = fpriv->hw_state[idx - 1];
+	if (idx == 0 || ctx == NULL)
+		return;
+
+	if (ctx->is_2d_only) {
+		/* 2D applications only care about certain pieces
+		 * of state.
+		 */
+		upa_writel(ctx->drawop, &ffb->drawop);
+
+		/* If we were restoring the vertex registers, this is where
+		 * we would do it.  We would restore 32 32-bit words starting
+		 * at ffb->suvtx.
+		 */
+
+		upa_writel(ctx->ppc, &ffb->ppc);
+		upa_writel(ctx->wid, &ffb->wid);
+		upa_writel(ctx->fg,  &ffb->fg);
+		upa_writel(ctx->bg, &ffb->bg);
+		upa_writel(ctx->xclip, &ffb->xclip);
+		upa_writel(ctx->fbc, &ffb->fbc);
+		upa_writel(ctx->rop, &ffb->rop);
+		upa_writel(ctx->cmp, &ffb->cmp);
+		upa_writel(ctx->matchab, &ffb->matchab);
+		upa_writel(ctx->magnab, &ffb->magnab);
+		upa_writel(ctx->pmask, &ffb->pmask);
+		upa_writel(ctx->xpmask, &ffb->xpmask);
+		upa_writel(ctx->lpat, &ffb->lpat);
+		upa_writel(ctx->fontxy, &ffb->fontxy);
+		upa_writel(ctx->fontw, &ffb->fontw);
+		upa_writel(ctx->fontinc, &ffb->fontinc);
+
+		/* stencil/stencilctl only exists on FFB2+ and later
+		 * due to the introduction of 3DRAM-III.
+		 */
+		if (fpriv->ffb_type == ffb2_vertical_plus ||
+		    fpriv->ffb_type == ffb2_horizontal_plus) {
+			upa_writel(ctx->stencil, &ffb->stencil);
+			upa_writel(ctx->stencilctl, &ffb->stencilctl);
+			upa_writel(0x80000000, &ffb->fbc);
+			upa_writel((ctx->stencilctl | 0x80000),
+				   &ffb->rawstencilctl);
+			upa_writel(ctx->fbc, &ffb->fbc);
+		}
+
+		for (i = 0; i < 32; i++)
+			upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
+		upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
+		return;
+	}
+
+	/* Restore drawop. */
+	upa_writel(ctx->drawop, &ffb->drawop);
+
+	/* If we were restoring the vertex registers, this is where
+	 * we would do it.  We would restore 32 32-bit words starting
+	 * at ffb->suvtx.
+	 */
+
+	/* Restore rendering attributes. */
+
+	upa_writel(ctx->ppc, &ffb->ppc);		/* Pixel Processor Control */
+	upa_writel(ctx->wid, &ffb->wid);		/* Current WID */
+	upa_writel(ctx->fg, &ffb->fg);			/* Constant FG color */
+	upa_writel(ctx->bg, &ffb->bg);			/* Constant BG color */
+	upa_writel(ctx->consty, &ffb->consty);		/* Constant Y */
+	upa_writel(ctx->constz, &ffb->constz);		/* Constant Z */
+	upa_writel(ctx->xclip, &ffb->xclip);		/* X plane clip */
+	upa_writel(ctx->dcss, &ffb->dcss);		/* Depth Cue Scale Slope */
+	upa_writel(ctx->vclipmin, &ffb->vclipmin);	/* Primary XY clip, minimum */
+	upa_writel(ctx->vclipmax, &ffb->vclipmax);	/* Primary XY clip, maximum */
+	upa_writel(ctx->vclipzmin, &ffb->vclipzmin);	/* Primary Z clip, minimum */
+	upa_writel(ctx->vclipzmax, &ffb->vclipzmax);	/* Primary Z clip, maximum */
+	upa_writel(ctx->dcsf, &ffb->dcsf);		/* Depth Cue Scale Front Bound */
+	upa_writel(ctx->dcsb, &ffb->dcsb);		/* Depth Cue Scale Back Bound */
+	upa_writel(ctx->dczf, &ffb->dczf);		/* Depth Cue Scale Z Front */
+	upa_writel(ctx->dczb, &ffb->dczb);		/* Depth Cue Scale Z Back */
+	upa_writel(ctx->blendc, &ffb->blendc);		/* Alpha Blend Control */
+	upa_writel(ctx->blendc1, &ffb->blendc1);	/* Alpha Blend Color 1 */
+	upa_writel(ctx->blendc2, &ffb->blendc2);	/* Alpha Blend Color 2 */
+	upa_writel(ctx->fbc, &ffb->fbc);		/* Frame Buffer Control */
+	upa_writel(ctx->rop, &ffb->rop);		/* Raster Operation */
+	upa_writel(ctx->cmp, &ffb->cmp);		/* Compare Controls */
+	upa_writel(ctx->matchab, &ffb->matchab);	/* Buffer A/B Match Ops */
+	upa_writel(ctx->matchc, &ffb->matchc);		/* Buffer C Match Ops */
+	upa_writel(ctx->magnab, &ffb->magnab);		/* Buffer A/B Magnitude Ops */
+	upa_writel(ctx->magnc, &ffb->magnc);		/* Buffer C Magnitude Ops */
+	upa_writel(ctx->pmask, &ffb->pmask);		/* RGB Plane Mask */
+	upa_writel(ctx->xpmask, &ffb->xpmask);		/* X Plane Mask */
+	upa_writel(ctx->ypmask, &ffb->ypmask);		/* Y Plane Mask */
+	upa_writel(ctx->zpmask, &ffb->zpmask);		/* Z Plane Mask */
+
+	/* Auxiliary Clips. */
+	upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min);
+	upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max);
+	upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min);
+	upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max);
+	upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min);
+	upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max);
+	upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min);
+	upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max);
+
+	upa_writel(ctx->lpat, &ffb->lpat);		/* Line Pattern */
+	upa_writel(ctx->fontxy, &ffb->fontxy);		/* XY Font Coordinate */
+	upa_writel(ctx->fontw, &ffb->fontw);		/* Font Width */
+	upa_writel(ctx->fontinc, &ffb->fontinc);	/* Font X/Y Increment */
+
+	/* These registers/features only exist on FFB2 and later chips. */
+	if (fpriv->ffb_type >= ffb2_prototype) {
+		upa_writel(ctx->dcss1, &ffb->dcss1);	/* Depth Cue Scale Slope 1 */
+		upa_writel(ctx->dcss2, &ffb->dcss2);	/* Depth Cue Scale Slope 2 */
+		upa_writel(ctx->dcss3, &ffb->dcss2);	/* Depth Cue Scale Slope 3 */
+		upa_writel(ctx->dcs2, &ffb->dcs2);	/* Depth Cue Scale 2 */
+		upa_writel(ctx->dcs3, &ffb->dcs3);	/* Depth Cue Scale 3 */
+		upa_writel(ctx->dcs4, &ffb->dcs4);	/* Depth Cue Scale 4 */
+		upa_writel(ctx->dcd2, &ffb->dcd2);	/* Depth Cue Depth 2 */
+		upa_writel(ctx->dcd3, &ffb->dcd3);	/* Depth Cue Depth 3 */
+		upa_writel(ctx->dcd4, &ffb->dcd4);	/* Depth Cue Depth 4 */
+
+		/* And stencil/stencilctl only exists on FFB2+ and later
+		 * due to the introduction of 3DRAM-III.
+		 */
+		if (fpriv->ffb_type == ffb2_vertical_plus ||
+		    fpriv->ffb_type == ffb2_horizontal_plus) {
+			/* Unfortunately, there is a hardware bug on
+			 * the FFB2+ chips which prevents a normal write
+			 * to the stencil control register from working
+			 * as it should.
+			 *
+			 * The state controlled by the FFB stencilctl register
+			 * really gets transferred to the per-buffer instances
+			 * of the stencilctl register in the 3DRAM chips.
+			 *
+			 * The bug is that FFB does not update buffer C correctly,
+			 * so we have to do it by hand for them.
+			 */
+
+			/* This will update buffers A and B. */
+			upa_writel(ctx->stencil, &ffb->stencil);
+			upa_writel(ctx->stencilctl, &ffb->stencilctl);
+
+			/* Force FFB to use buffer C 3dram regs. */
+			upa_writel(0x80000000, &ffb->fbc);
+			upa_writel((ctx->stencilctl | 0x80000),
+				   &ffb->rawstencilctl);
+
+			/* Now restore the correct FBC controls. */
+			upa_writel(ctx->fbc, &ffb->fbc);
+		}
+	}
+
+	/* Restore the 32x32 area pattern. */
+	for (i = 0; i < 32; i++)
+		upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
+
+	/* Finally, stash away the User Constol/Status Register.
+	 * The only state we really preserve here is the picking
+	 * control.
+	 */
+	upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
+}
+
+#define FFB_UCSR_FB_BUSY       0x01000000
+#define FFB_UCSR_RP_BUSY       0x02000000
+#define FFB_UCSR_ALL_BUSY      (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
+
+static void FFBWait(ffb_fbcPtr ffb)
+{
+	int limit = 100000;
+
+	do {
+		u32 regval = upa_readl(&ffb->ucsr);
+
+		if ((regval & FFB_UCSR_ALL_BUSY) == 0)
+			break;
+	} while (--limit);
+}
+
+int ffb_context_switch(drm_device_t *dev, int old, int new)
+{
+	ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1);
+
+        atomic_inc(&dev->total_ctx);
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+        
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context ||
+	    dev->last_context == 0) {
+		dev->last_context = new;
+                return 0;
+	}
+        
+	FFBWait(fpriv->regs);
+	ffb_save_context(fpriv, old);
+	ffb_restore_context(fpriv, old, new);
+	FFBWait(fpriv->regs);
+        
+	dev->last_context = new;
+
+        return 0;
+}
+
+int ffb_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+
+int ffb_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+	int idx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	idx = ffb_alloc_queue(dev, (ctx.flags & _DRM_CONTEXT_2DONLY));
+	if (idx < 0)
+		return -ENFILE;
+
+	DRM_DEBUG("%d\n", ctx.handle);
+	ctx.handle = idx;
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int ffb_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	ffb_dev_priv_t	*fpriv	= (ffb_dev_priv_t *) (dev + 1);
+	struct ffb_hw_context *hwctx;
+	drm_ctx_t ctx;
+	int idx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+
+	idx = ctx.handle;
+	if (idx <= 0 || idx >= FFB_MAX_CTXS)
+		return -EINVAL;
+
+	hwctx = fpriv->hw_state[idx - 1];
+	if (hwctx == NULL)
+		return -EINVAL;
+
+	if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0)
+		hwctx->is_2d_only = 0;
+	else
+		hwctx->is_2d_only = 1;
+
+	return 0;
+}
+
+int ffb_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	ffb_dev_priv_t	*fpriv	= (ffb_dev_priv_t *) (dev + 1);
+	struct ffb_hw_context *hwctx;
+	drm_ctx_t ctx;
+	int idx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+
+	idx = ctx.handle;
+	if (idx <= 0 || idx >= FFB_MAX_CTXS)
+		return -EINVAL;
+
+	hwctx = fpriv->hw_state[idx - 1];
+	if (hwctx == NULL)
+		return -EINVAL;
+
+	if (hwctx->is_2d_only != 0)
+		ctx.flags = _DRM_CONTEXT_2DONLY;
+	else
+		ctx.flags = 0;
+
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+
+	return 0;
+}
+
+int ffb_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return ffb_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int ffb_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+
+	return 0;
+}
+
+int ffb_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_t	ctx;
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	ffb_dev_priv_t	*fpriv	= (ffb_dev_priv_t *) (dev + 1);
+	int idx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+
+	idx = ctx.handle - 1;
+	if (idx < 0 || idx >= FFB_MAX_CTXS)
+		return -EINVAL;
+
+	if (fpriv->hw_state[idx] != NULL) {
+		kfree(fpriv->hw_state[idx]);
+		fpriv->hw_state[idx] = NULL;
+	}
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/ffb_drv.c lia64-2.4/drivers/char/drm-4.0/ffb_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/ffb_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/ffb_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,951 @@
+/* $Id: ffb_drv.c,v 1.14 2001/05/24 12:01:47 davem Exp $
+ * ffb_drv.c: Creator/Creator3D direct rendering driver.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ */
+
+#include "drmP.h"
+
+#include <linux/sched.h>
+#include <linux/smp_lock.h>
+#include <asm/shmparam.h>
+#include <asm/oplib.h>
+#include <asm/upa.h>
+
+#include "ffb_drv.h"
+
+#define FFB_NAME	"ffb"
+#define FFB_DESC	"Creator/Creator3D"
+#define FFB_DATE	"20000517"
+#define FFB_MAJOR	0
+#define FFB_MINOR	0
+#define FFB_PATCHLEVEL	1
+
+/* Forward declarations. */
+int  ffb_init(void);
+void ffb_cleanup(void);
+static int  ffb_version(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+static int  ffb_open(struct inode *inode, struct file *filp);
+static int  ffb_release(struct inode *inode, struct file *filp);
+static int  ffb_ioctl(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+static int  ffb_lock(struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg);
+static int  ffb_unlock(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+static int ffb_mmap(struct file *filp, struct vm_area_struct *vma);
+static unsigned long ffb_get_unmapped_area(struct file *, unsigned long, unsigned long, unsigned long, unsigned long);
+
+/* From ffb_context.c */
+extern int ffb_resctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_addctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_modctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_getctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_switchctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_newctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_rmctx(struct inode *, struct file *, unsigned int, unsigned long);
+extern int ffb_context_switch(drm_device_t *, int, int);
+
+static struct file_operations ffb_fops = {
+	owner:			THIS_MODULE,
+	open:			ffb_open,
+	flush:			drm_flush,
+	release:		ffb_release,
+	ioctl:			ffb_ioctl,
+	mmap:			ffb_mmap,
+	read:			drm_read,
+	fasync:			drm_fasync,
+	poll:			drm_poll,
+	get_unmapped_area:	ffb_get_unmapped_area,
+};
+
+/* This is just a template, we make a new copy for each FFB
+ * we discover at init time so that each one gets a unique
+ * misc device minor number.
+ */
+static struct miscdevice ffb_misc = {
+	minor:	MISC_DYNAMIC_MINOR,
+	name:	FFB_NAME,
+	fops:	&ffb_fops,
+};
+
+static drm_ioctl_desc_t ffb_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]    = { ffb_version,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]  = { drm_getmagic,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]  = { drm_irq_busid,	  0, 1 }, /* XXX */
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	     = { drm_block,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]    = { drm_unblock,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]    = { drm_addmap,	  1, 1 },
+	
+	/* The implementation is currently a nop just like on tdfx.
+	 * Later we can do something more clever. -DaveM
+	 */
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]    = { ffb_addctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]     = { ffb_rmctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]    = { ffb_modctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]    = { ffb_getctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { ffb_switchctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]    = { ffb_newctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]    = { ffb_resctx,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]   = { drm_adddraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]    = { drm_rmdraw,	  1, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	     = { ffb_lock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]     = { ffb_unlock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]     = { drm_finish,	  1, 0 },
+};
+#define FFB_IOCTL_COUNT DRM_ARRAY_SIZE(ffb_ioctls)
+
+#ifdef MODULE
+static char *ffb = NULL;
+#endif
+
+MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
+MODULE_DESCRIPTION("Sun Creator/Creator3D DRI");
+
+static int ffb_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+	
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+	
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+
+	/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+	
+	/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+	
+	/* Clear map area information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+
+			default:
+				break;
+			};
+
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+	
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+	
+	return 0;
+}
+
+drm_device_t **ffb_dev_table;
+static int ffb_dev_table_size;
+
+static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance)
+{
+	volatile unsigned char *strap_bits;
+	unsigned char val;
+
+	strap_bits = (volatile unsigned char *)
+		(ffb_priv->card_phys_base + 0x00200000UL);
+
+	/* Don't ask, you have to read the value twice for whatever
+	 * reason to get correct contents.
+	 */
+	val = upa_readb(strap_bits);
+	val = upa_readb(strap_bits);
+	switch (val & 0x78) {
+	case (0x0 << 5) | (0x0 << 3):
+		ffb_priv->ffb_type = ffb1_prototype;
+		printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance);
+		break;
+	case (0x0 << 5) | (0x1 << 3):
+		ffb_priv->ffb_type = ffb1_standard;
+		printk("ffb%d: Detected FFB1\n", instance);
+		break;
+	case (0x0 << 5) | (0x3 << 3):
+		ffb_priv->ffb_type = ffb1_speedsort;
+		printk("ffb%d: Detected FFB1-SpeedSort\n", instance);
+		break;
+	case (0x1 << 5) | (0x0 << 3):
+		ffb_priv->ffb_type = ffb2_prototype;
+		printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance);
+		break;
+	case (0x1 << 5) | (0x1 << 3):
+		ffb_priv->ffb_type = ffb2_vertical;
+		printk("ffb%d: Detected FFB2/vertical\n", instance);
+		break;
+	case (0x1 << 5) | (0x2 << 3):
+		ffb_priv->ffb_type = ffb2_vertical_plus;
+		printk("ffb%d: Detected FFB2+/vertical\n", instance);
+		break;
+	case (0x2 << 5) | (0x0 << 3):
+		ffb_priv->ffb_type = ffb2_horizontal;
+		printk("ffb%d: Detected FFB2/horizontal\n", instance);
+		break;
+	case (0x2 << 5) | (0x2 << 3):
+		ffb_priv->ffb_type = ffb2_horizontal;
+		printk("ffb%d: Detected FFB2+/horizontal\n", instance);
+		break;
+	default:
+		ffb_priv->ffb_type = ffb2_vertical;
+		printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val);
+		break;
+	};
+}
+
+static void __init ffb_apply_upa_parent_ranges(int parent, struct linux_prom64_registers *regs)
+{
+	struct linux_prom64_ranges ranges[PROMREG_MAX];
+	char name[128];
+	int len, i;
+
+	prom_getproperty(parent, "name", name, sizeof(name));
+	if (strcmp(name, "upa") != 0)
+		return;
+
+	len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges));
+	if (len <= 0)
+		return;
+
+	len /= sizeof(struct linux_prom64_ranges);
+	for (i = 0; i < len; i++) {
+		struct linux_prom64_ranges *rng = &ranges[i];
+		u64 phys_addr = regs->phys_addr;
+
+		if (phys_addr >= rng->ot_child_base &&
+		    phys_addr < (rng->ot_child_base + rng->or_size)) {
+			regs->phys_addr -= rng->ot_child_base;
+			regs->phys_addr += rng->ot_parent_base;
+			return;
+		}
+	}
+
+	return;
+}
+
+static int __init ffb_init_one(int prom_node, int parent_node, int instance)
+{
+	struct linux_prom64_registers regs[2*PROMREG_MAX];
+	drm_device_t *dev;
+	ffb_dev_priv_t *ffb_priv;
+	int ret, i;
+
+	dev = kmalloc(sizeof(drm_device_t) + sizeof(ffb_dev_priv_t), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	memset(dev, 0, sizeof(*dev));
+	spin_lock_init(&dev->count_lock);
+	sema_init(&dev->struct_sem, 1);
+
+	ffb_priv = (ffb_dev_priv_t *) (dev + 1);
+	ffb_priv->prom_node = prom_node;
+	if (prom_getproperty(ffb_priv->prom_node, "reg",
+			     (void *)regs, sizeof(regs)) <= 0) {
+		kfree(dev);
+		return -EINVAL;
+	}
+	ffb_apply_upa_parent_ranges(parent_node, &regs[0]);
+	ffb_priv->card_phys_base = regs[0].phys_addr;
+	ffb_priv->regs = (ffb_fbcPtr)
+		(regs[0].phys_addr + 0x00600000UL);
+	get_ffb_type(ffb_priv, instance);
+	for (i = 0; i < FFB_MAX_CTXS; i++)
+		ffb_priv->hw_state[i] = NULL;
+
+	ffb_dev_table[instance] = dev;
+
+#ifdef MODULE
+	drm_parse_options(ffb);
+#endif
+
+	memcpy(&ffb_priv->miscdev, &ffb_misc, sizeof(ffb_misc));
+	ret = misc_register(&ffb_priv->miscdev);
+	if (ret) {
+		ffb_dev_table[instance] = NULL;
+		kfree(dev);
+		return ret;
+	}
+
+	dev->device = MKDEV(MISC_MAJOR, ffb_priv->miscdev.minor);
+	dev->name = FFB_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d at %016lx\n",
+		 FFB_NAME,
+		 FFB_MAJOR,
+		 FFB_MINOR,
+		 FFB_PATCHLEVEL,
+		 FFB_DATE,
+		 ffb_priv->miscdev.minor,
+		 ffb_priv->card_phys_base);
+	
+	return 0;
+}
+
+static int __init ffb_count_siblings(int root)
+{
+	int node, child, count = 0;
+
+	child = prom_getchild(root);
+	for (node = prom_searchsiblings(child, "SUNW,ffb"); node;
+	     node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb"))
+		count++;
+
+	return count;
+}
+
+static int __init ffb_init_dev_table(void)
+{
+	int root, total;
+
+	total = ffb_count_siblings(prom_root_node);
+	root = prom_getchild(prom_root_node);
+	for (root = prom_searchsiblings(root, "upa"); root;
+	     root = prom_searchsiblings(prom_getsibling(root), "upa"))
+		total += ffb_count_siblings(root);
+
+	if (!total)
+		return -ENODEV;
+
+	ffb_dev_table = kmalloc(sizeof(drm_device_t *) * total, GFP_KERNEL);
+	if (!ffb_dev_table)
+		return -ENOMEM;
+
+	ffb_dev_table_size = total;
+
+	return 0;
+}
+
+static int __init ffb_scan_siblings(int root, int instance)
+{
+	int node, child;
+
+	child = prom_getchild(root);
+	for (node = prom_searchsiblings(child, "SUNW,ffb"); node;
+	     node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) {
+		ffb_init_one(node, root, instance);
+		instance++;
+	}
+
+	return instance;
+}
+
+int __init ffb_init(void)
+{
+	int root, instance, ret;
+
+	ret = ffb_init_dev_table();
+	if (ret)
+		return ret;
+
+	instance = ffb_scan_siblings(prom_root_node, 0);
+
+	root = prom_getchild(prom_root_node);
+	for (root = prom_searchsiblings(root, "upa"); root;
+	     root = prom_searchsiblings(prom_getsibling(root), "upa"))
+		instance = ffb_scan_siblings(root, instance);
+
+	return 0;
+}
+
+void __exit ffb_cleanup(void)
+{
+	int instance;
+
+	DRM_DEBUG("\n");
+	
+	drm_proc_cleanup();
+	for (instance = 0; instance < ffb_dev_table_size; instance++) {
+		drm_device_t *dev = ffb_dev_table[instance];
+		ffb_dev_priv_t *ffb_priv;
+
+		if (!dev)
+			continue;
+
+		ffb_priv = (ffb_dev_priv_t *) (dev + 1);
+		if (misc_deregister(&ffb_priv->miscdev)) {
+			DRM_ERROR("Cannot unload module\n");
+		} else {
+			DRM_INFO("Module unloaded\n");
+		}
+		ffb_takedown(dev);
+		kfree(dev);
+		ffb_dev_table[instance] = NULL;
+	}
+	kfree(ffb_dev_table);
+	ffb_dev_table = NULL;
+	ffb_dev_table_size = 0;
+}
+
+static int ffb_version(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	drm_version_t version;
+	int len, ret;
+
+	ret = copy_from_user(&version, (drm_version_t *)arg, sizeof(version));
+	if (ret)
+		return -EFAULT;
+
+	version.version_major		= FFB_MAJOR;
+	version.version_minor		= FFB_MINOR;
+	version.version_patchlevel	= FFB_PATCHLEVEL;
+
+	len = strlen(FFB_NAME);
+	if (len > version.name_len)
+		len = version.name_len;
+	version.name_len = len;
+	if (len && version.name) {
+		ret = copy_to_user(version.name, FFB_NAME, len);
+		if (ret)
+			return -EFAULT;
+	}
+
+	len = strlen(FFB_DATE);
+	if (len > version.date_len)
+		len = version.date_len;
+	version.date_len = len;
+	if (len && version.date) {
+		ret = copy_to_user(version.date, FFB_DATE, len);
+		if (ret)
+			return -EFAULT;
+	}
+
+	len = strlen(FFB_DESC);
+	if (len > version.desc_len)
+		len = version.desc_len;
+	version.desc_len = len;
+	if (len && version.desc) {
+		ret = copy_to_user(version.desc, FFB_DESC, len);
+		if (ret)
+			return -EFAULT;
+	}
+
+	ret = copy_to_user((drm_version_t *) arg, &version, sizeof(version));
+	if (ret)
+		ret = -EFAULT;
+
+	return ret;
+}
+
+static int ffb_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma            = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+	
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	return 0;
+}
+
+static int ffb_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t *dev;
+	int minor, i;
+	int ret = 0;
+
+	minor = MINOR(inode->i_rdev);
+	for (i = 0; i < ffb_dev_table_size; i++) {
+		ffb_dev_priv_t *ffb_priv;
+
+		ffb_priv = (ffb_dev_priv_t *) (ffb_dev_table[i] + 1);
+
+		if (ffb_priv->miscdev.minor == minor)
+			break;
+	}
+
+	if (i >= ffb_dev_table_size)
+		return -EINVAL;
+
+	dev = ffb_dev_table[i];
+	if (!dev)
+		return -EINVAL;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	ret = drm_open_helper(inode, filp, dev);
+	if (!ret) {
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return ffb_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	return ret;
+}
+
+static int ffb_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev;
+	int ret = 0;
+
+	lock_kernel();
+	dev = priv->dev;
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (dev->lock.hw_lock != NULL
+	    && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
+	    && dev->lock.pid == current->pid) {
+		ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) (dev + 1);
+		int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock);
+		int idx;
+
+		/* We have to free up the rogue hw context state
+		 * holding error or else we will leak it.
+		 */
+		idx = context - 1;
+		if (fpriv->hw_state[idx] != NULL) {
+			kfree(fpriv->hw_state[idx]);
+			fpriv->hw_state[idx] = NULL;
+		}
+	}
+
+	ret = drm_release(inode, filp);
+
+	if (!ret) {
+		atomic_inc(&dev->total_close);
+		spin_lock(&dev->count_lock);
+		if (!--dev->open_count) {
+			if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+				DRM_ERROR("Device busy: %d %d\n",
+					  atomic_read(&dev->ioctl_count),
+					  dev->blocked);
+				spin_unlock(&dev->count_lock);
+				unlock_kernel();
+				return -EBUSY;
+			}
+			spin_unlock(&dev->count_lock);
+			ret = ffb_takedown(dev);
+			unlock_kernel();
+			return ret;
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	unlock_kernel();
+	return ret;
+}
+
+static int ffb_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+	int		 ret;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+	
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= FFB_IOCTL_COUNT) {
+		ret = -EINVAL;
+	} else {
+		ioctl	  = &ffb_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			ret = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			ret = -EACCES;
+		} else {
+			ret = (func)(inode, filp, cmd, arg);
+		}
+	}
+	
+	atomic_dec(&dev->ioctl_count);
+
+	return ret;
+}
+
+static int ffb_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+        drm_file_t        *priv	= filp->private_data;
+        drm_device_t      *dev	= priv->dev;
+        DECLARE_WAITQUEUE(entry, current);
+        int               ret	= 0;
+        drm_lock_t        lock;
+
+	ret = copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock));
+	if (ret)
+		return -EFAULT;
+
+        if (lock.context == DRM_KERNEL_CONTEXT) {
+                DRM_ERROR("Process %d using kernel context %d\n",
+                          current->pid, lock.context);
+                return -EINVAL;
+        }
+
+        DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+                  lock.context, current->pid, dev->lock.hw_lock->lock,
+                  lock.flags);
+
+	add_wait_queue(&dev->lock.lock_queue, &entry);
+	for (;;) {
+		if (!dev->lock.hw_lock) {
+			/* Device has been unregistered */
+			ret = -EINTR;
+			break;
+		}
+		if (drm_lock_take(&dev->lock.hw_lock->lock,
+				  lock.context)) {
+			dev->lock.pid       = current->pid;
+			dev->lock.lock_time = jiffies;
+			atomic_inc(&dev->total_locks);
+			break;  /* Got lock */
+		}
+                        
+		/* Contention */
+		atomic_inc(&dev->total_sleeps);
+		current->state = TASK_INTERRUPTIBLE;
+		current->policy |= SCHED_YIELD;
+		schedule();
+		if (signal_pending(current)) {
+			ret = -ERESTARTSYS;
+			break;
+		}
+	}
+	current->state = TASK_RUNNING;
+	remove_wait_queue(&dev->lock.lock_queue, &entry);
+
+        if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+
+		if (dev->last_context != lock.context)
+			ffb_context_switch(dev, dev->last_context, lock.context);
+	}
+
+        DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+
+        return ret;
+}
+
+int ffb_unlock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+	unsigned int old, new, prev, ctx;
+	int ret;
+
+	ret = copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock));
+	if (ret)
+		return -EFAULT;
+	
+	if ((ctx = lock.context) == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+
+	/* We no longer really hold it, but if we are the next
+	 * agent to request it then we should just be able to
+	 * take it immediately and not eat the ioctl.
+	 */
+	dev->lock.pid = 0;
+	{
+		__volatile__ unsigned int *plock = &dev->lock.hw_lock->lock;
+
+		do {
+			old  = *plock;
+			new  = ctx;
+			prev = cmpxchg(plock, old, new);
+		} while (prev != old);
+	}
+
+	wake_up_interruptible(&dev->lock.lock_queue);
+	
+	unblock_all_signals();
+	return 0;
+}
+
+extern struct vm_operations_struct drm_vm_ops;
+extern struct vm_operations_struct drm_vm_shm_ops;
+extern struct vm_operations_struct drm_vm_shm_lock_ops;
+
+static int ffb_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_map_t	*map	= NULL;
+	ffb_dev_priv_t	*ffb_priv;
+	int		i, minor;
+	
+	DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
+		  vma->vm_start, vma->vm_end, VM_OFFSET(vma));
+
+	minor = MINOR(filp->f_dentry->d_inode->i_rdev);
+	ffb_priv = NULL;
+	for (i = 0; i < ffb_dev_table_size; i++) {
+		ffb_priv = (ffb_dev_priv_t *) (ffb_dev_table[i] + 1);
+		if (ffb_priv->miscdev.minor == minor)
+			break;
+	}
+	if (i >= ffb_dev_table_size)
+		return -EINVAL;
+
+	/* We don't support/need dma mappings, so... */
+	if (!VM_OFFSET(vma))
+		return -EINVAL;
+
+	for (i = 0; i < dev->map_count; i++) {
+		unsigned long off;
+
+		map = dev->maplist[i];
+
+		/* Ok, a little hack to make 32-bit apps work. */
+		off = (map->offset & 0xffffffff);
+		if (off == VM_OFFSET(vma))
+			break;
+	}
+
+	if (i >= dev->map_count)
+		return -EINVAL;
+
+	if (!map ||
+	    ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN)))
+		return -EPERM;
+
+	if (map->size != (vma->vm_end - vma->vm_start))
+		return -EINVAL;
+
+	/* Set read-only attribute before mappings are created
+	 * so it works for fb/reg maps too.
+	 */
+	if (map->flags & _DRM_READ_ONLY)
+		vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect(
+			__pte(pgprot_val(vma->vm_page_prot)))));
+
+	switch (map->type) {
+	case _DRM_FRAME_BUFFER:
+		/* FALLTHROUGH */
+
+	case _DRM_REGISTERS:
+		/* In order to handle 32-bit drm apps/xserver we
+		 * play a trick.  The mappings only really specify
+		 * the 32-bit offset from the cards 64-bit base
+		 * address, and we just add in the base here.
+		 */
+		vma->vm_flags |= VM_IO;
+		if (io_remap_page_range(vma->vm_start,
+					ffb_priv->card_phys_base + VM_OFFSET(vma),
+					vma->vm_end - vma->vm_start,
+					vma->vm_page_prot, 0))
+			return -EAGAIN;
+
+		vma->vm_ops = &drm_vm_ops;
+		break;
+	case _DRM_SHM:
+		if (map->flags & _DRM_CONTAINS_LOCK)
+			vma->vm_ops = &drm_vm_shm_lock_ops;
+		else {
+			vma->vm_ops = &drm_vm_shm_ops;
+			vma->vm_private_data = (void *) map;
+		}
+
+		/* Don't let this area swap.  Change when
+		 * DRM_KERNEL advisory is supported.
+		 */
+		vma->vm_flags |= VM_LOCKED;
+		break;
+	default:
+		return -EINVAL;	/* This should never happen. */
+	};
+
+	vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */
+
+	vma->vm_file = filp; /* Needed for drm_vm_open() */
+	drm_vm_open(vma);
+	return 0;
+}
+
+static drm_map_t *ffb_find_map(struct file *filp, unsigned long off)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev;
+	drm_map_t	*map;
+	int		i;
+
+	if (!priv || (dev = priv->dev) == NULL)
+		return NULL;
+
+	for (i = 0; i < dev->map_count; i++) {
+		unsigned long uoff;
+
+		map = dev->maplist[i];
+
+		/* Ok, a little hack to make 32-bit apps work. */
+		uoff = (map->offset & 0xffffffff);
+		if (uoff == off)
+			return map;
+	}
+	return NULL;
+}
+
+static unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, unsigned long pgoff, unsigned long flags)
+{
+	drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT);
+	unsigned long addr = -ENOMEM;
+
+	if (!map)
+		return get_unmapped_area(NULL, hint, len, pgoff, flags);
+
+	if (map->type == _DRM_FRAME_BUFFER ||
+	    map->type == _DRM_REGISTERS) {
+#ifdef HAVE_ARCH_FB_UNMAPPED_AREA
+		addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags);
+#else
+		addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
+#endif
+	} else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) {
+		unsigned long slack = SHMLBA - PAGE_SIZE;
+
+		addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags);
+		if (!(addr & ~PAGE_MASK)) {
+			unsigned long kvirt = (unsigned long) map->handle;
+
+			if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
+				unsigned long koff, aoff;
+
+				koff = kvirt & (SHMLBA - 1);
+				aoff = addr & (SHMLBA - 1);
+				if (koff < aoff)
+					koff += SHMLBA;
+
+				addr += (koff - aoff);
+			}
+		}
+	} else {
+		addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
+	}
+
+	return addr;
+}
+
+module_init(ffb_init);
+module_exit(ffb_cleanup);
diff -urN linux-2.4.16/drivers/char/drm-4.0/ffb_drv.h lia64-2.4/drivers/char/drm-4.0/ffb_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/ffb_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/ffb_drv.h	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,276 @@
+/* $Id: ffb_drv.h,v 1.1 2000/06/01 04:24:39 davem Exp $
+ * ffb_drv.h: Creator/Creator3D direct rendering driver.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ */
+
+/* Auxilliary clips. */
+typedef struct  {
+	volatile unsigned int min;
+	volatile unsigned int max;
+} ffb_auxclip, *ffb_auxclipPtr;
+
+/* FFB register set. */
+typedef struct _ffb_fbc {
+	/* Next vertex registers, on the right we list which drawops
+	 * use said register and the logical name the register has in
+	 * that context.
+	 */					/* DESCRIPTION		DRAWOP(NAME)	*/
+/*0x00*/unsigned int		pad1[3];	/* Reserved				*/
+/*0x0c*/volatile unsigned int	alpha;		/* ALPHA Transparency			*/
+/*0x10*/volatile unsigned int	red;		/* RED					*/
+/*0x14*/volatile unsigned int	green;		/* GREEN				*/
+/*0x18*/volatile unsigned int	blue;		/* BLUE					*/
+/*0x1c*/volatile unsigned int	z;		/* DEPTH				*/
+/*0x20*/volatile unsigned int	y;		/* Y			triangle(DOYF)	*/
+						/*                      aadot(DYF)	*/
+						/*                      ddline(DYF)	*/
+						/*                      aaline(DYF)	*/
+/*0x24*/volatile unsigned int	x;		/* X			triangle(DOXF)	*/
+						/*                      aadot(DXF)	*/
+						/*                      ddline(DXF)	*/
+						/*                      aaline(DXF)	*/
+/*0x28*/unsigned int		pad2[2];	/* Reserved				*/
+/*0x30*/volatile unsigned int	ryf;		/* Y (alias to DOYF)	ddline(RYF)	*/
+						/*			aaline(RYF)	*/
+						/*			triangle(RYF)	*/
+/*0x34*/volatile unsigned int	rxf;		/* X			ddline(RXF)	*/
+						/*			aaline(RXF)	*/
+						/*			triangle(RXF)	*/
+/*0x38*/unsigned int		pad3[2];	/* Reserved				*/
+/*0x40*/volatile unsigned int	dmyf;		/* Y (alias to DOYF)	triangle(DMYF)	*/
+/*0x44*/volatile unsigned int	dmxf;		/* X			triangle(DMXF)	*/
+/*0x48*/unsigned int		pad4[2];	/* Reserved				*/
+/*0x50*/volatile unsigned int	ebyi;		/* Y (alias to RYI)	polygon(EBYI)	*/
+/*0x54*/volatile unsigned int	ebxi;		/* X			polygon(EBXI)	*/
+/*0x58*/unsigned int		pad5[2];	/* Reserved				*/
+/*0x60*/volatile unsigned int	by;		/* Y			brline(RYI)	*/
+						/*			fastfill(OP)	*/
+						/*			polygon(YI)	*/
+						/*			rectangle(YI)	*/
+						/*			bcopy(SRCY)	*/
+						/*			vscroll(SRCY)	*/
+/*0x64*/volatile unsigned int	bx;		/* X			brline(RXI)	*/
+						/*			polygon(XI)	*/
+						/*			rectangle(XI)	*/
+						/*			bcopy(SRCX)	*/
+						/*			vscroll(SRCX)	*/
+						/*			fastfill(GO)	*/
+/*0x68*/volatile unsigned int	dy;		/* destination Y	fastfill(DSTY)	*/
+						/*			bcopy(DSRY)	*/
+						/*			vscroll(DSRY)	*/
+/*0x6c*/volatile unsigned int	dx;		/* destination X	fastfill(DSTX)	*/
+						/*			bcopy(DSTX)	*/
+						/*			vscroll(DSTX)	*/
+/*0x70*/volatile unsigned int	bh;		/* Y (alias to RYI)	brline(DYI)	*/
+						/*			dot(DYI)	*/
+						/*			polygon(ETYI)	*/
+						/* Height		fastfill(H)	*/
+						/*			bcopy(H)	*/
+						/*			vscroll(H)	*/
+						/* Y count		fastfill(NY)	*/
+/*0x74*/volatile unsigned int	bw;		/* X			dot(DXI)	*/
+						/*			brline(DXI)	*/
+						/*			polygon(ETXI)	*/
+						/*			fastfill(W)	*/
+						/*			bcopy(W)	*/
+						/*			vscroll(W)	*/
+						/*			fastfill(NX)	*/
+/*0x78*/unsigned int		pad6[2];	/* Reserved				*/
+/*0x80*/unsigned int		pad7[32];	/* Reserved				*/
+	
+	/* Setup Unit's vertex state register */
+/*100*/	volatile unsigned int	suvtx;
+/*104*/	unsigned int		pad8[63];	/* Reserved				*/
+	
+	/* Frame Buffer Control Registers */
+/*200*/	volatile unsigned int	ppc;		/* Pixel Processor Control		*/
+/*204*/	volatile unsigned int	wid;		/* Current WID				*/
+/*208*/	volatile unsigned int	fg;		/* FG data				*/
+/*20c*/	volatile unsigned int	bg;		/* BG data				*/
+/*210*/	volatile unsigned int	consty;		/* Constant Y				*/
+/*214*/	volatile unsigned int	constz;		/* Constant Z				*/
+/*218*/	volatile unsigned int	xclip;		/* X Clip				*/
+/*21c*/	volatile unsigned int	dcss;		/* Depth Cue Scale Slope		*/
+/*220*/	volatile unsigned int	vclipmin;	/* Viewclip XY Min Bounds		*/
+/*224*/	volatile unsigned int	vclipmax;	/* Viewclip XY Max Bounds		*/
+/*228*/	volatile unsigned int	vclipzmin;	/* Viewclip Z Min Bounds		*/
+/*22c*/	volatile unsigned int	vclipzmax;	/* Viewclip Z Max Bounds		*/
+/*230*/	volatile unsigned int	dcsf;		/* Depth Cue Scale Front Bound		*/
+/*234*/	volatile unsigned int	dcsb;		/* Depth Cue Scale Back Bound		*/
+/*238*/	volatile unsigned int	dczf;		/* Depth Cue Z Front			*/
+/*23c*/	volatile unsigned int	dczb;		/* Depth Cue Z Back			*/
+/*240*/	unsigned int		pad9;		/* Reserved				*/
+/*244*/	volatile unsigned int	blendc;		/* Alpha Blend Control			*/
+/*248*/	volatile unsigned int	blendc1;	/* Alpha Blend Color 1			*/
+/*24c*/	volatile unsigned int	blendc2;	/* Alpha Blend Color 2			*/
+/*250*/	volatile unsigned int	fbramitc;	/* FB RAM Interleave Test Control	*/
+/*254*/	volatile unsigned int	fbc;		/* Frame Buffer Control			*/
+/*258*/	volatile unsigned int	rop;		/* Raster OPeration			*/
+/*25c*/	volatile unsigned int	cmp;		/* Frame Buffer Compare			*/
+/*260*/	volatile unsigned int	matchab;	/* Buffer AB Match Mask			*/
+/*264*/	volatile unsigned int	matchc;		/* Buffer C(YZ) Match Mask		*/
+/*268*/	volatile unsigned int	magnab;		/* Buffer AB Magnitude Mask		*/
+/*26c*/	volatile unsigned int	magnc;		/* Buffer C(YZ) Magnitude Mask		*/
+/*270*/	volatile unsigned int	fbcfg0;		/* Frame Buffer Config 0		*/
+/*274*/	volatile unsigned int	fbcfg1;		/* Frame Buffer Config 1		*/
+/*278*/	volatile unsigned int	fbcfg2;		/* Frame Buffer Config 2		*/
+/*27c*/	volatile unsigned int	fbcfg3;		/* Frame Buffer Config 3		*/
+/*280*/	volatile unsigned int	ppcfg;		/* Pixel Processor Config		*/
+/*284*/	volatile unsigned int	pick;		/* Picking Control			*/
+/*288*/	volatile unsigned int	fillmode;	/* FillMode				*/
+/*28c*/	volatile unsigned int	fbramwac;	/* FB RAM Write Address Control		*/
+/*290*/	volatile unsigned int	pmask;		/* RGB PlaneMask			*/
+/*294*/	volatile unsigned int	xpmask;		/* X PlaneMask				*/
+/*298*/	volatile unsigned int	ypmask;		/* Y PlaneMask				*/
+/*29c*/	volatile unsigned int	zpmask;		/* Z PlaneMask				*/
+/*2a0*/	ffb_auxclip		auxclip[4]; 	/* Auxilliary Viewport Clip		*/
+	
+	/* New 3dRAM III support regs */
+/*2c0*/	volatile unsigned int	rawblend2;
+/*2c4*/	volatile unsigned int	rawpreblend;
+/*2c8*/	volatile unsigned int	rawstencil;
+/*2cc*/	volatile unsigned int	rawstencilctl;
+/*2d0*/	volatile unsigned int	threedram1;
+/*2d4*/	volatile unsigned int	threedram2;
+/*2d8*/	volatile unsigned int	passin;
+/*2dc*/	volatile unsigned int	rawclrdepth;
+/*2e0*/	volatile unsigned int	rawpmask;
+/*2e4*/	volatile unsigned int	rawcsrc;
+/*2e8*/	volatile unsigned int	rawmatch;
+/*2ec*/	volatile unsigned int	rawmagn;
+/*2f0*/	volatile unsigned int	rawropblend;
+/*2f4*/	volatile unsigned int	rawcmp;
+/*2f8*/	volatile unsigned int	rawwac;
+/*2fc*/	volatile unsigned int	fbramid;
+	
+/*300*/	volatile unsigned int	drawop;		/* Draw OPeration			*/
+/*304*/	unsigned int		pad10[2];	/* Reserved				*/
+/*30c*/	volatile unsigned int	lpat;		/* Line Pattern control			*/
+/*310*/	unsigned int		pad11;		/* Reserved				*/
+/*314*/	volatile unsigned int	fontxy;		/* XY Font coordinate			*/
+/*318*/	volatile unsigned int	fontw;		/* Font Width				*/
+/*31c*/	volatile unsigned int	fontinc;	/* Font Increment			*/
+/*320*/	volatile unsigned int	font;		/* Font bits				*/
+/*324*/	unsigned int		pad12[3];	/* Reserved				*/
+/*330*/	volatile unsigned int	blend2;
+/*334*/	volatile unsigned int	preblend;
+/*338*/	volatile unsigned int	stencil;
+/*33c*/	volatile unsigned int	stencilctl;
+
+/*340*/	unsigned int		pad13[4];	/* Reserved				*/
+/*350*/	volatile unsigned int	dcss1;		/* Depth Cue Scale Slope 1		*/
+/*354*/	volatile unsigned int	dcss2;		/* Depth Cue Scale Slope 2		*/
+/*358*/	volatile unsigned int	dcss3;		/* Depth Cue Scale Slope 3		*/
+/*35c*/	volatile unsigned int	widpmask;
+/*360*/	volatile unsigned int	dcs2;
+/*364*/	volatile unsigned int	dcs3;
+/*368*/	volatile unsigned int	dcs4;
+/*36c*/	unsigned int		pad14;		/* Reserved				*/
+/*370*/	volatile unsigned int	dcd2;
+/*374*/	volatile unsigned int	dcd3;
+/*378*/	volatile unsigned int	dcd4;
+/*37c*/	unsigned int		pad15;		/* Reserved				*/
+/*380*/	volatile unsigned int	pattern[32];	/* area Pattern				*/
+/*400*/	unsigned int		pad16[8];	/* Reserved				*/
+/*420*/	volatile unsigned int	reset;		/* chip RESET				*/
+/*424*/	unsigned int		pad17[247];	/* Reserved				*/
+/*800*/	volatile unsigned int	devid;		/* Device ID				*/
+/*804*/	unsigned int		pad18[63];	/* Reserved				*/
+/*900*/	volatile unsigned int	ucsr;		/* User Control & Status Register	*/
+/*904*/	unsigned int		pad19[31];	/* Reserved				*/
+/*980*/	volatile unsigned int	mer;		/* Mode Enable Register			*/
+/*984*/	unsigned int		pad20[1439];	/* Reserved				*/
+} ffb_fbc, *ffb_fbcPtr;
+
+struct ffb_hw_context {
+	int is_2d_only;
+
+	unsigned int ppc;
+	unsigned int wid;
+	unsigned int fg;
+	unsigned int bg;
+	unsigned int consty;
+	unsigned int constz;
+	unsigned int xclip;
+	unsigned int dcss;
+	unsigned int vclipmin;
+	unsigned int vclipmax;
+	unsigned int vclipzmin;
+	unsigned int vclipzmax;
+	unsigned int dcsf;
+	unsigned int dcsb;
+	unsigned int dczf;
+	unsigned int dczb;
+	unsigned int blendc;
+	unsigned int blendc1;
+	unsigned int blendc2;
+	unsigned int fbc;
+	unsigned int rop;
+	unsigned int cmp;
+	unsigned int matchab;
+	unsigned int matchc;
+	unsigned int magnab;
+	unsigned int magnc;
+	unsigned int pmask;
+	unsigned int xpmask;
+	unsigned int ypmask;
+	unsigned int zpmask;
+	unsigned int auxclip0min;
+	unsigned int auxclip0max;
+	unsigned int auxclip1min;
+	unsigned int auxclip1max;
+	unsigned int auxclip2min;
+	unsigned int auxclip2max;
+	unsigned int auxclip3min;
+	unsigned int auxclip3max;
+	unsigned int drawop;
+	unsigned int lpat;
+	unsigned int fontxy;
+	unsigned int fontw;
+	unsigned int fontinc;
+	unsigned int area_pattern[32];
+	unsigned int ucsr;
+	unsigned int stencil;
+	unsigned int stencilctl;
+	unsigned int dcss1;
+	unsigned int dcss2;
+	unsigned int dcss3;
+	unsigned int dcs2;
+	unsigned int dcs3;
+	unsigned int dcs4;
+	unsigned int dcd2;
+	unsigned int dcd3;
+	unsigned int dcd4;
+	unsigned int mer;
+};
+
+#define FFB_MAX_CTXS	32
+
+enum ffb_chip_type {
+	ffb1_prototype = 0,	/* Early pre-FCS FFB */
+	ffb1_standard,		/* First FCS FFB, 100Mhz UPA, 66MHz gclk */
+	ffb1_speedsort,		/* Second FCS FFB, 100Mhz UPA, 75MHz gclk */
+	ffb2_prototype,		/* Early pre-FCS vertical FFB2 */
+	ffb2_vertical,		/* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk,
+				   75(SingleBuffer)/83(DoubleBuffer) MHz fclk */
+	ffb2_vertical_plus,	/* Second FCS FFB2/vertical, same timings */
+	ffb2_horizontal,	/* First FCS FFB2/horizontal, same timings as FFB2/vert */
+	ffb2_horizontal_plus,	/* Second FCS FFB2/horizontal, same timings */
+	afb_m3,			/* FCS Elite3D, 3 float chips */
+	afb_m6			/* FCS Elite3D, 6 float chips */
+};
+
+typedef struct ffb_dev_priv {
+	/* Misc software state. */
+	int			prom_node;
+	enum ffb_chip_type	ffb_type;
+	u64			card_phys_base;
+	struct miscdevice 	miscdev;
+
+	/* Controller registers. */
+	ffb_fbcPtr		regs;
+
+	/* Context table. */
+	struct ffb_hw_context	*hw_state[FFB_MAX_CTXS];
+} ffb_dev_priv_t;
diff -urN linux-2.4.16/drivers/char/drm-4.0/fops.c lia64-2.4/drivers/char/drm-4.0/fops.c
--- linux-2.4.16/drivers/char/drm-4.0/fops.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/fops.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,253 @@
+/* fops.c -- File operations for DRM -*- linux-c -*-
+ * Created: Mon Jan  4 08:58:31 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *    Daryll Strauss <daryll@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include <linux/poll.h>
+
+/* drm_open is called whenever a process opens /dev/drm. */
+
+int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev)
+{
+	kdev_t	     minor = MINOR(inode->i_rdev);
+	drm_file_t   *priv;
+
+	if (filp->f_flags & O_EXCL)   return -EBUSY; /* No exclusive opens */
+	if (!drm_cpu_valid())         return -EINVAL;
+
+	DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor);
+
+	priv		    = drm_alloc(sizeof(*priv), DRM_MEM_FILES);
+	if(priv == NULL)
+		return -ENOMEM;
+	memset(priv, 0, sizeof(*priv));
+
+	filp->private_data  = priv;
+	priv->uid	    = current->euid;
+	priv->pid	    = current->pid;
+	priv->minor	    = minor;
+	priv->dev	    = dev;
+	priv->ioctl_count   = 0;
+	priv->authenticated = capable(CAP_SYS_ADMIN);
+
+	down(&dev->struct_sem);
+	if (!dev->file_last) {
+		priv->next	= NULL;
+		priv->prev	= NULL;
+		dev->file_first = priv;
+		dev->file_last	= priv;
+	} else {
+		priv->next	     = NULL;
+		priv->prev	     = dev->file_last;
+		dev->file_last->next = priv;
+		dev->file_last	     = priv;
+	}
+	up(&dev->struct_sem);
+	
+	return 0;
+}
+
+int drm_flush(struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev    = priv->dev;
+
+	DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n",
+		  current->pid, dev->device, dev->open_count);
+	return 0;
+}
+
+/* drm_release is called whenever a process closes /dev/drm*.  Linux calls
+   this only if any mappings have been closed. */
+
+int drm_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev    = priv->dev;
+
+	DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n",
+		  current->pid, dev->device, dev->open_count);
+
+	if (dev->lock.hw_lock
+	    && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
+	    && dev->lock.pid == current->pid) {
+		DRM_ERROR("Process %d dead, freeing lock for context %d\n",
+			  current->pid,
+			  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+		drm_lock_free(dev,
+			      &dev->lock.hw_lock->lock,
+			      _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+		
+				/* FIXME: may require heavy-handed reset of
+                                   hardware at this point, possibly
+                                   processed via a callback to the X
+                                   server. */
+	}
+	drm_reclaim_buffers(dev, priv->pid);
+
+	drm_fasync(-1, filp, 0);
+
+	down(&dev->struct_sem);
+	if (priv->prev) priv->prev->next = priv->next;
+	else		dev->file_first	 = priv->next;
+	if (priv->next) priv->next->prev = priv->prev;
+	else		dev->file_last	 = priv->prev;
+	up(&dev->struct_sem);
+	
+	drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
+	
+	return 0;
+}
+
+int drm_fasync(int fd, struct file *filp, int on)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev    = priv->dev;
+	int	      retcode;
+	
+	DRM_DEBUG("fd = %d, device = 0x%x\n", fd, dev->device);
+	retcode = fasync_helper(fd, filp, on, &dev->buf_async);
+	if (retcode < 0) return retcode;
+	return 0;
+}
+
+
+/* The drm_read and drm_write_string code (especially that which manages
+   the circular buffer), is based on Alessandro Rubini's LINUX DEVICE
+   DRIVERS (Cambridge: O'Reilly, 1998), pages 111-113. */
+
+ssize_t drm_read(struct file *filp, char *buf, size_t count, loff_t *off)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev    = priv->dev;
+	int	      left;
+	int	      avail;
+	int	      send;
+	int	      cur;
+
+	DRM_DEBUG("%p, %p\n", dev->buf_rp, dev->buf_wp);
+	
+	while (dev->buf_rp == dev->buf_wp) {
+		DRM_DEBUG("  sleeping\n");
+		if (filp->f_flags & O_NONBLOCK) {
+			return -EAGAIN;
+		}
+		interruptible_sleep_on(&dev->buf_readers);
+		if (signal_pending(current)) {
+			DRM_DEBUG("  interrupted\n");
+			return -ERESTARTSYS;
+		}
+		DRM_DEBUG("  awake\n");
+	}
+
+	left  = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ;
+	avail = DRM_BSZ - left;
+	send  = DRM_MIN(avail, count);
+
+	while (send) {
+		if (dev->buf_wp > dev->buf_rp) {
+			cur = DRM_MIN(send, dev->buf_wp - dev->buf_rp);
+		} else {
+			cur = DRM_MIN(send, dev->buf_end - dev->buf_rp);
+		}
+		if (copy_to_user(buf, dev->buf_rp, cur))
+			return -EFAULT;
+		dev->buf_rp += cur;
+		if (dev->buf_rp == dev->buf_end) dev->buf_rp = dev->buf;
+		send -= cur;
+	}
+	
+	wake_up_interruptible(&dev->buf_writers);
+	return DRM_MIN(avail, count);;
+}
+
+int drm_write_string(drm_device_t *dev, const char *s)
+{
+	int left   = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ;
+	int send   = strlen(s);
+	int count;
+
+	DRM_DEBUG("%d left, %d to send (%p, %p)\n",
+		  left, send, dev->buf_rp, dev->buf_wp);
+	
+	if (left == 1 || dev->buf_wp != dev->buf_rp) {
+		DRM_ERROR("Buffer not empty (%d left, wp = %p, rp = %p)\n",
+			  left,
+			  dev->buf_wp,
+			  dev->buf_rp);
+	}
+
+	while (send) {
+		if (dev->buf_wp >= dev->buf_rp) {
+			count = DRM_MIN(send, dev->buf_end - dev->buf_wp);
+			if (count == left) --count; /* Leave a hole */
+		} else {
+			count = DRM_MIN(send, dev->buf_rp - dev->buf_wp - 1);
+		}
+		strncpy(dev->buf_wp, s, count);
+		dev->buf_wp += count;
+		if (dev->buf_wp == dev->buf_end) dev->buf_wp = dev->buf;
+		send -= count;
+	}
+
+#if LINUX_VERSION_CODE < 0x020315 && !defined(KILLFASYNCHASTHREEPARAMETERS)
+	/* The extra parameter to kill_fasync was added in 2.3.21, and is
+           _not_ present in _stock_ 2.2.14 and 2.2.15.  However, some
+           distributions patch 2.2.x kernels to add this parameter.  The
+           Makefile.linux attempts to detect this addition and defines
+           KILLFASYNCHASTHREEPARAMETERS if three parameters are found. */
+	if (dev->buf_async) kill_fasync(dev->buf_async, SIGIO);
+#else
+
+				/* Parameter added in 2.3.21. */
+#if LINUX_VERSION_CODE < 0x020400
+	if (dev->buf_async) kill_fasync(dev->buf_async, SIGIO, POLL_IN);
+#else
+				/* Type of first parameter changed in
+                                   Linux 2.4.0-test2... */
+	if (dev->buf_async) kill_fasync(&dev->buf_async, SIGIO, POLL_IN);
+#endif
+#endif
+	DRM_DEBUG("waking\n");
+	wake_up_interruptible(&dev->buf_readers);
+	return 0;
+}
+
+unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait)
+{
+	drm_file_t   *priv = filp->private_data;
+	drm_device_t *dev  = priv->dev;
+
+	poll_wait(filp, &dev->buf_readers, wait);
+	if (dev->buf_wp != dev->buf_rp) return POLLIN | POLLRDNORM;
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/gamma_dma.c lia64-2.4/drivers/char/drm-4.0/gamma_dma.c
--- linux-2.4.16/drivers/char/drm-4.0/gamma_dma.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/gamma_dma.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,836 @@
+/* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*-
+ * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "gamma_drv.h"
+
+#include <linux/interrupt.h>	/* For task queue support */
+
+
+/* WARNING!!! MAGIC NUMBER!!!  The number of regions already added to the
+   kernel must be specified here.  Currently, the number is 2.	This must
+   match the order the X server uses for instantiating register regions ,
+   or must be passed in a new ioctl. */
+#define GAMMA_REG(reg)						   \
+	(2							   \
+	 + ((reg < 0x1000)					   \
+	    ? 0							   \
+	    : ((reg < 0x10000) ? 1 : ((reg < 0x11000) ? 2 : 3))))
+
+#define GAMMA_OFF(reg)						   \
+	((reg < 0x1000)						   \
+	 ? reg							   \
+	 : ((reg < 0x10000)					   \
+	    ? (reg - 0x1000)					   \
+	    : ((reg < 0x11000)					   \
+	       ? (reg - 0x10000)				   \
+	       : (reg - 0x11000))))
+
+#define GAMMA_BASE(reg)	 ((unsigned long)dev->maplist[GAMMA_REG(reg)]->handle)
+#define GAMMA_ADDR(reg)	 (GAMMA_BASE(reg) + GAMMA_OFF(reg))
+#define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg)
+#define GAMMA_READ(reg)	 GAMMA_DEREF(reg)
+#define GAMMA_WRITE(reg,val) do { GAMMA_DEREF(reg) = val; } while (0)
+
+#define GAMMA_BROADCASTMASK    0x9378
+#define GAMMA_COMMANDINTENABLE 0x0c48
+#define GAMMA_DMAADDRESS       0x0028
+#define GAMMA_DMACOUNT	       0x0030
+#define GAMMA_FILTERMODE       0x8c00
+#define GAMMA_GCOMMANDINTFLAGS 0x0c50
+#define GAMMA_GCOMMANDMODE     0x0c40
+#define GAMMA_GCOMMANDSTATUS   0x0c60
+#define GAMMA_GDELAYTIMER      0x0c38
+#define GAMMA_GDMACONTROL      0x0060
+#define GAMMA_GINTENABLE       0x0808
+#define GAMMA_GINTFLAGS	       0x0810
+#define GAMMA_INFIFOSPACE      0x0018
+#define GAMMA_OUTFIFOWORDS     0x0020
+#define GAMMA_OUTPUTFIFO       0x2000
+#define GAMMA_SYNC	       0x8c40
+#define GAMMA_SYNC_TAG	       0x0188
+
+static inline void gamma_dma_dispatch(drm_device_t *dev, unsigned long address,
+				      unsigned long length)
+{
+	GAMMA_WRITE(GAMMA_DMAADDRESS, virt_to_phys((void *)address));
+	while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4)
+		;
+	GAMMA_WRITE(GAMMA_DMACOUNT, length / 4);
+}
+
+static inline void gamma_dma_quiescent_single(drm_device_t *dev)
+{
+	while (GAMMA_READ(GAMMA_DMACOUNT))
+		;
+	while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
+		;
+
+	GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
+	GAMMA_WRITE(GAMMA_SYNC, 0);
+	
+	do {
+		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
+			;
+	} while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
+}
+
+static inline void gamma_dma_quiescent_dual(drm_device_t *dev)
+{
+	while (GAMMA_READ(GAMMA_DMACOUNT))
+		;
+	while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
+		;
+
+	GAMMA_WRITE(GAMMA_BROADCASTMASK, 3);
+
+	GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
+	GAMMA_WRITE(GAMMA_SYNC, 0);
+	
+				/* Read from first MX */
+	do {
+		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
+			;
+	} while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
+	
+				/* Read from second MX */
+	do {
+		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000))
+			;
+	} while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG);
+}
+
+static inline void gamma_dma_ready(drm_device_t *dev)
+{
+	while (GAMMA_READ(GAMMA_DMACOUNT))
+		;
+}
+
+static inline int gamma_dma_is_ready(drm_device_t *dev)
+{
+	return !GAMMA_READ(GAMMA_DMACOUNT);
+}
+
+static void gamma_dma_service(int irq, void *device, struct pt_regs *regs)
+{
+	drm_device_t	 *dev = (drm_device_t *)device;
+	drm_device_dma_t *dma = dev->dma;
+	
+	atomic_inc(&dev->total_irq);
+	GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
+	GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
+	GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
+	if (gamma_dma_is_ready(dev)) {
+				/* Free previous buffer */
+		if (test_and_set_bit(0, &dev->dma_flag)) {
+			atomic_inc(&dma->total_missed_free);
+			return;
+		}
+		if (dma->this_buffer) {
+			drm_free_buffer(dev, dma->this_buffer);
+			dma->this_buffer = NULL;
+		}
+		clear_bit(0, &dev->dma_flag);
+
+				/* Dispatch new buffer */
+		queue_task(&dev->tq, &tq_immediate);
+		mark_bh(IMMEDIATE_BH);
+	}
+}
+
+/* Only called by gamma_dma_schedule. */
+static int gamma_do_dma(drm_device_t *dev, int locked)
+{
+	unsigned long	 address;
+	unsigned long	 length;
+	drm_buf_t	 *buf;
+	int		 retcode = 0;
+	drm_device_dma_t *dma = dev->dma;
+#if DRM_DMA_HISTOGRAM
+	cycles_t	 dma_start, dma_stop;
+#endif
+
+	if (test_and_set_bit(0, &dev->dma_flag)) {
+		atomic_inc(&dma->total_missed_dma);
+		return -EBUSY;
+	}
+	
+#if DRM_DMA_HISTOGRAM
+	dma_start = get_cycles();
+#endif
+
+	if (!dma->next_buffer) {
+		DRM_ERROR("No next_buffer\n");
+		clear_bit(0, &dev->dma_flag);
+		return -EINVAL;
+	}
+
+	buf	= dma->next_buffer;
+	address = (unsigned long)buf->address;
+	length	= buf->used;
+
+	DRM_DEBUG("context %d, buffer %d (%ld bytes)\n",
+		  buf->context, buf->idx, length);
+
+	if (buf->list == DRM_LIST_RECLAIM) {
+		drm_clear_next_buffer(dev);
+		drm_free_buffer(dev, buf);
+		clear_bit(0, &dev->dma_flag);
+		return -EINVAL;
+	}
+
+	if (!length) {
+		DRM_ERROR("0 length buffer\n");
+		drm_clear_next_buffer(dev);
+		drm_free_buffer(dev, buf);
+		clear_bit(0, &dev->dma_flag);
+		return 0;
+	}
+	
+	if (!gamma_dma_is_ready(dev)) {
+		clear_bit(0, &dev->dma_flag);
+		return -EBUSY;
+	}
+
+	if (buf->while_locked) {
+		if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+			DRM_ERROR("Dispatching buffer %d from pid %d"
+				  " \"while locked\", but no lock held\n",
+				  buf->idx, buf->pid);
+		}
+	} else {
+		if (!locked && !drm_lock_take(&dev->lock.hw_lock->lock,
+					      DRM_KERNEL_CONTEXT)) {
+			atomic_inc(&dma->total_missed_lock);
+			clear_bit(0, &dev->dma_flag);
+			return -EBUSY;
+		}
+	}
+
+	if (dev->last_context != buf->context
+	    && !(dev->queuelist[buf->context]->flags
+		 & _DRM_CONTEXT_PRESERVED)) {
+				/* PRE: dev->last_context != buf->context */
+		if (drm_context_switch(dev, dev->last_context, buf->context)) {
+			drm_clear_next_buffer(dev);
+			drm_free_buffer(dev, buf);
+		}
+		retcode = -EBUSY;
+		goto cleanup;
+			
+				/* POST: we will wait for the context
+				   switch and will dispatch on a later call
+				   when dev->last_context == buf->context.
+				   NOTE WE HOLD THE LOCK THROUGHOUT THIS
+				   TIME! */
+	}
+
+	drm_clear_next_buffer(dev);
+	buf->pending	 = 1;
+	buf->waiting	 = 0;
+	buf->list	 = DRM_LIST_PEND;
+#if DRM_DMA_HISTOGRAM
+	buf->time_dispatched = get_cycles();
+#endif
+
+	gamma_dma_dispatch(dev, address, length);
+	drm_free_buffer(dev, dma->this_buffer);
+	dma->this_buffer = buf;
+
+	atomic_add(length, &dma->total_bytes);
+	atomic_inc(&dma->total_dmas);
+
+	if (!buf->while_locked && !dev->context_flag && !locked) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+cleanup:
+
+	clear_bit(0, &dev->dma_flag);
+
+#if DRM_DMA_HISTOGRAM
+	dma_stop = get_cycles();
+	atomic_inc(&dev->histo.dma[drm_histogram_slot(dma_stop - dma_start)]);
+#endif
+
+	return retcode;
+}
+
+static void gamma_dma_schedule_timer_wrapper(unsigned long dev)
+{
+	gamma_dma_schedule((drm_device_t *)dev, 0);
+}
+
+static void gamma_dma_schedule_tq_wrapper(void *dev)
+{
+	gamma_dma_schedule(dev, 0);
+}
+
+int gamma_dma_schedule(drm_device_t *dev, int locked)
+{
+	int		 next;
+	drm_queue_t	 *q;
+	drm_buf_t	 *buf;
+	int		 retcode   = 0;
+	int		 processed = 0;
+	int		 missed;
+	int		 expire	   = 20;
+	drm_device_dma_t *dma	   = dev->dma;
+#if DRM_DMA_HISTOGRAM
+	cycles_t	 schedule_start;
+#endif
+
+	if (test_and_set_bit(0, &dev->interrupt_flag)) {
+				/* Not reentrant */
+		atomic_inc(&dma->total_missed_sched);
+		return -EBUSY;
+	}
+	missed = atomic_read(&dma->total_missed_sched);
+
+#if DRM_DMA_HISTOGRAM
+	schedule_start = get_cycles();
+#endif
+
+again:
+	if (dev->context_flag) {
+		clear_bit(0, &dev->interrupt_flag);
+		return -EBUSY;
+	}
+	if (dma->next_buffer) {
+				/* Unsent buffer that was previously
+				   selected, but that couldn't be sent
+				   because the lock could not be obtained
+				   or the DMA engine wasn't ready.  Try
+				   again. */
+		atomic_inc(&dma->total_tried);
+		if (!(retcode = gamma_do_dma(dev, locked))) {
+			atomic_inc(&dma->total_hit);
+			++processed;
+		}
+	} else {
+		do {
+			next = drm_select_queue(dev,
+					     gamma_dma_schedule_timer_wrapper);
+			if (next >= 0) {
+				q   = dev->queuelist[next];
+				buf = drm_waitlist_get(&q->waitlist);
+				dma->next_buffer = buf;
+				dma->next_queue	 = q;
+				if (buf && buf->list == DRM_LIST_RECLAIM) {
+					drm_clear_next_buffer(dev);
+					drm_free_buffer(dev, buf);
+				}
+			}
+		} while (next >= 0 && !dma->next_buffer);
+		if (dma->next_buffer) {
+			if (!(retcode = gamma_do_dma(dev, locked))) {
+				++processed;
+			}
+		}
+	}
+
+	if (--expire) {
+		if (missed != atomic_read(&dma->total_missed_sched)) {
+			atomic_inc(&dma->total_lost);
+			if (gamma_dma_is_ready(dev)) goto again;
+		}
+		if (processed && gamma_dma_is_ready(dev)) {
+			atomic_inc(&dma->total_lost);
+			processed = 0;
+			goto again;
+		}
+	}
+	
+	clear_bit(0, &dev->interrupt_flag);
+	
+#if DRM_DMA_HISTOGRAM
+	atomic_inc(&dev->histo.schedule[drm_histogram_slot(get_cycles()
+							   - schedule_start)]);
+#endif
+	return retcode;
+}
+
+static int gamma_dma_priority(drm_device_t *dev, drm_dma_t *d)
+{
+	unsigned long	  address;
+	unsigned long	  length;
+	int		  must_free = 0;
+	int		  retcode   = 0;
+	int		  i;
+	int		  idx;
+	drm_buf_t	  *buf;
+	drm_buf_t	  *last_buf = NULL;
+	drm_device_dma_t  *dma	    = dev->dma;
+	DECLARE_WAITQUEUE(entry, current);
+
+				/* Turn off interrupt handling */
+	while (test_and_set_bit(0, &dev->interrupt_flag)) {
+		schedule();
+		if (signal_pending(current)) return -EINTR;
+	}
+	if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) {
+		while (!drm_lock_take(&dev->lock.hw_lock->lock,
+				      DRM_KERNEL_CONTEXT)) {
+			schedule();
+			if (signal_pending(current)) {
+				clear_bit(0, &dev->interrupt_flag);
+				return -EINTR;
+			}
+		}
+		++must_free;
+	}
+	atomic_inc(&dma->total_prio);
+
+	for (i = 0; i < d->send_count; i++) {
+		idx = d->send_indices[i];
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+				  d->send_indices[i], dma->buf_count - 1);
+			continue;
+		}
+		buf = dma->buflist[ idx ];
+		if (buf->pid != current->pid) {
+			DRM_ERROR("Process %d using buffer owned by %d\n",
+				  current->pid, buf->pid);
+			retcode = -EINVAL;
+			goto cleanup;
+		}
+		if (buf->list != DRM_LIST_NONE) {
+			DRM_ERROR("Process %d using %d's buffer on list %d\n",
+				  current->pid, buf->pid, buf->list);
+			retcode = -EINVAL;
+			goto cleanup;
+		}
+				/* This isn't a race condition on
+				   buf->list, since our concern is the
+				   buffer reclaim during the time the
+				   process closes the /dev/drm? handle, so
+				   it can't also be doing DMA. */
+		buf->list	  = DRM_LIST_PRIO;
+		buf->used	  = d->send_sizes[i];
+		buf->context	  = d->context;
+		buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED;
+		address		  = (unsigned long)buf->address;
+		length		  = buf->used;
+		if (!length) {
+			DRM_ERROR("0 length buffer\n");
+		}
+		if (buf->pending) {
+			DRM_ERROR("Sending pending buffer:"
+				  " buffer %d, offset %d\n",
+				  d->send_indices[i], i);
+			retcode = -EINVAL;
+			goto cleanup;
+		}
+		if (buf->waiting) {
+			DRM_ERROR("Sending waiting buffer:"
+				  " buffer %d, offset %d\n",
+				  d->send_indices[i], i);
+			retcode = -EINVAL;
+			goto cleanup;
+		}
+		buf->pending = 1;
+		
+		if (dev->last_context != buf->context
+		    && !(dev->queuelist[buf->context]->flags
+			 & _DRM_CONTEXT_PRESERVED)) {
+			add_wait_queue(&dev->context_wait, &entry);
+			current->state = TASK_INTERRUPTIBLE;
+				/* PRE: dev->last_context != buf->context */
+			drm_context_switch(dev, dev->last_context,
+					   buf->context);
+				/* POST: we will wait for the context
+				   switch and will dispatch on a later call
+				   when dev->last_context == buf->context.
+				   NOTE WE HOLD THE LOCK THROUGHOUT THIS
+				   TIME! */
+			schedule();
+			current->state = TASK_RUNNING;
+			remove_wait_queue(&dev->context_wait, &entry);
+			if (signal_pending(current)) {
+				retcode = -EINTR;
+				goto cleanup;
+			}
+			if (dev->last_context != buf->context) {
+				DRM_ERROR("Context mismatch: %d %d\n",
+					  dev->last_context,
+					  buf->context);
+			}
+		}
+
+#if DRM_DMA_HISTOGRAM
+		buf->time_queued     = get_cycles();
+		buf->time_dispatched = buf->time_queued;
+#endif
+		gamma_dma_dispatch(dev, address, length);
+		atomic_add(length, &dma->total_bytes);
+		atomic_inc(&dma->total_dmas);
+		
+		if (last_buf) {
+			drm_free_buffer(dev, last_buf);
+		}
+		last_buf = buf;
+	}
+
+
+cleanup:
+	if (last_buf) {
+		gamma_dma_ready(dev);
+		drm_free_buffer(dev, last_buf);
+	}
+	
+	if (must_free && !dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+	clear_bit(0, &dev->interrupt_flag);
+	return retcode;
+}
+
+static int gamma_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
+{
+	DECLARE_WAITQUEUE(entry, current);
+	drm_buf_t	  *last_buf = NULL;
+	int		  retcode   = 0;
+	drm_device_dma_t  *dma	    = dev->dma;
+
+	if (d->flags & _DRM_DMA_BLOCK) {
+		last_buf = dma->buflist[d->send_indices[d->send_count-1]];
+		add_wait_queue(&last_buf->dma_wait, &entry);
+	}
+	
+	if ((retcode = drm_dma_enqueue(dev, d))) {
+		if (d->flags & _DRM_DMA_BLOCK)
+			remove_wait_queue(&last_buf->dma_wait, &entry);
+		return retcode;
+	}
+	
+	gamma_dma_schedule(dev, 0);
+	
+	if (d->flags & _DRM_DMA_BLOCK) {
+		DRM_DEBUG("%d waiting\n", current->pid);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!last_buf->waiting && !last_buf->pending)
+				break; /* finished */
+			schedule();
+			if (signal_pending(current)) {
+				retcode = -EINTR; /* Can't restart */
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		DRM_DEBUG("%d running\n", current->pid);
+		remove_wait_queue(&last_buf->dma_wait, &entry);
+		if (!retcode
+		    || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) {
+			if (!waitqueue_active(&last_buf->dma_wait)) {
+				drm_free_buffer(dev, last_buf);
+			}
+		}
+		if (retcode) {
+			DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n",
+				  d->context,
+				  last_buf->waiting,
+				  last_buf->pending,
+				  DRM_WAITCOUNT(dev, d->context),
+				  last_buf->idx,
+				  last_buf->list,
+				  last_buf->pid,
+				  current->pid);
+		}
+	}
+	return retcode;
+}
+
+int gamma_dma(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	drm_file_t	  *priv	    = filp->private_data;
+	drm_device_t	  *dev	    = priv->dev;
+	drm_device_dma_t  *dma	    = dev->dma;
+	int		  retcode   = 0;
+	drm_dma_t	  d;
+
+	if (copy_from_user(&d, (drm_dma_t *)arg, sizeof(d)))
+		return -EFAULT;
+	DRM_DEBUG("%d %d: %d send, %d req\n",
+		  current->pid, d.context, d.send_count, d.request_count);
+
+	if (d.context == DRM_KERNEL_CONTEXT || d.context >= dev->queue_slots) {
+		DRM_ERROR("Process %d using context %d\n",
+			  current->pid, d.context);
+		return -EINVAL;
+	}
+	if (d.send_count < 0 || d.send_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n",
+			  current->pid, d.send_count, dma->buf_count);
+		return -EINVAL;
+	}
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  current->pid, d.request_count, dma->buf_count);
+		return -EINVAL;
+	}
+
+	if (d.send_count) {
+		if (d.flags & _DRM_DMA_PRIORITY)
+			retcode = gamma_dma_priority(dev, &d);
+		else 
+			retcode = gamma_dma_send_buffers(dev, &d);
+	}
+
+	d.granted_count = 0;
+
+	if (!retcode && d.request_count) {
+		retcode = drm_dma_get_buffers(dev, &d);
+	}
+
+	DRM_DEBUG("%d returning, granted = %d\n",
+		  current->pid, d.granted_count);
+	if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d)))
+		return -EFAULT;
+
+	return retcode;
+}
+
+int gamma_irq_install(drm_device_t *dev, int irq)
+{
+	int retcode;
+
+	if (!irq)     return -EINVAL;
+	
+	down(&dev->struct_sem);
+	if (dev->irq) {
+		up(&dev->struct_sem);
+		return -EBUSY;
+	}
+	dev->irq = irq;
+	up(&dev->struct_sem);
+	
+	DRM_DEBUG("%d\n", irq);
+
+	dev->context_flag     = 0;
+	dev->interrupt_flag   = 0;
+	dev->dma_flag	      = 0;
+	
+	dev->dma->next_buffer = NULL;
+	dev->dma->next_queue  = NULL;
+	dev->dma->this_buffer = NULL;
+
+	INIT_LIST_HEAD(&dev->tq.list);
+	dev->tq.sync	      = 0;
+	dev->tq.routine	      = gamma_dma_schedule_tq_wrapper;
+	dev->tq.data	      = dev;
+
+
+				/* Before installing handler */
+	GAMMA_WRITE(GAMMA_GCOMMANDMODE, 0);
+	GAMMA_WRITE(GAMMA_GDMACONTROL, 0);
+	
+				/* Install handler */
+	if ((retcode = request_irq(dev->irq,
+				   gamma_dma_service,
+				   0,
+				   dev->devname,
+				   dev))) {
+		down(&dev->struct_sem);
+		dev->irq = 0;
+		up(&dev->struct_sem);
+		return retcode;
+	}
+
+				/* After installing handler */
+	GAMMA_WRITE(GAMMA_GINTENABLE,	    0x2001);
+	GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0x0008);
+	GAMMA_WRITE(GAMMA_GDELAYTIMER,	   0x39090);
+	
+	return 0;
+}
+
+int gamma_irq_uninstall(drm_device_t *dev)
+{
+	int irq;
+
+	down(&dev->struct_sem);
+	irq	 = dev->irq;
+	dev->irq = 0;
+	up(&dev->struct_sem);
+	
+	if (!irq) return -EINVAL;
+	
+	DRM_DEBUG("%d\n", irq);
+	
+	GAMMA_WRITE(GAMMA_GDELAYTIMER,	    0);
+	GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0);
+	GAMMA_WRITE(GAMMA_GINTENABLE,	    0);
+	free_irq(irq, dev);
+
+	return 0;
+}
+
+
+int gamma_control(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_control_t	ctl;
+	int		retcode;
+	
+	if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl)))
+		return -EFAULT;
+	
+	switch (ctl.func) {
+	case DRM_INST_HANDLER:
+		if ((retcode = gamma_irq_install(dev, ctl.irq)))
+			return retcode;
+		break;
+	case DRM_UNINST_HANDLER:
+		if ((retcode = gamma_irq_uninstall(dev)))
+			return retcode;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int gamma_lock(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	DECLARE_WAITQUEUE(entry, current);
+	int		  ret	= 0;
+	drm_lock_t	  lock;
+	drm_queue_t	  *q;
+#if DRM_DMA_HISTOGRAM
+	cycles_t	  start;
+
+	dev->lck_start = start = get_cycles();
+#endif
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+		  lock.context, current->pid, dev->lock.hw_lock->lock,
+		  lock.flags);
+
+	if (lock.context < 0 || lock.context >= dev->queue_count)
+		return -EINVAL;
+	q = dev->queuelist[lock.context];
+	
+	ret = drm_flush_block_and_flush(dev, lock.context, lock.flags);
+
+	if (!ret) {
+		if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)
+		    != lock.context) {
+			long j = jiffies - dev->lock.lock_time;
+
+			if (j > 0 && j <= DRM_LOCK_SLICE) {
+				/* Can't take lock if we just had it and
+				   there is contention. */
+				current->state = TASK_INTERRUPTIBLE;
+				schedule_timeout(j);
+			}
+		}
+		add_wait_queue(&dev->lock.lock_queue, &entry);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!dev->lock.hw_lock) {
+				/* Device has been unregistered */
+				ret = -EINTR;
+				break;
+			}
+			if (drm_lock_take(&dev->lock.hw_lock->lock,
+					  lock.context)) {
+				dev->lock.pid	    = current->pid;
+				dev->lock.lock_time = jiffies;
+				atomic_inc(&dev->total_locks);
+				atomic_inc(&q->total_locks);
+				break;	/* Got lock */
+			}
+			
+				/* Contention */
+			atomic_inc(&dev->total_sleeps);
+			schedule();
+			if (signal_pending(current)) {
+				ret = -ERESTARTSYS;
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&dev->lock.lock_queue, &entry);
+	}
+
+	drm_flush_unblock(dev, lock.context, lock.flags); /* cleanup phase */
+	
+	if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+
+		if (lock.flags & _DRM_LOCK_READY)
+			gamma_dma_ready(dev);
+		if (lock.flags & _DRM_LOCK_QUIESCENT) {
+			if (gamma_found() == 1) {
+				gamma_dma_quiescent_single(dev);
+			} else {
+				gamma_dma_quiescent_dual(dev);
+			}
+		}
+	}
+	DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+
+#if DRM_DMA_HISTOGRAM
+	atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]);
+#endif
+	
+	return ret;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/gamma_drv.c lia64-2.4/drivers/char/drm-4.0/gamma_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/gamma_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/gamma_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,571 @@
+/* gamma.c -- 3dlabs GMX 2000 driver -*- linux-c -*-
+ * Created: Mon Jan  4 08:58:31 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "gamma_drv.h"
+
+#ifndef PCI_DEVICE_ID_3DLABS_GAMMA
+#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008
+#endif
+#ifndef PCI_DEVICE_ID_3DLABS_MX
+#define PCI_DEVICE_ID_3DLABS_MX 0x0006
+#endif
+
+#define GAMMA_NAME	 "gamma"
+#define GAMMA_DESC	 "3dlabs GMX 2000"
+#define GAMMA_DATE	 "20000910"
+#define GAMMA_MAJOR	 1
+#define GAMMA_MINOR	 0
+#define GAMMA_PATCHLEVEL 0
+
+static drm_device_t	      gamma_device;
+
+static struct file_operations gamma_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 gamma_open,
+	flush:	 drm_flush,
+	release: gamma_release,
+	ioctl:	 gamma_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+	poll:	 drm_poll,
+};
+
+static struct miscdevice      gamma_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  GAMMA_NAME,
+	fops:  &gamma_fops,
+};
+
+static drm_ioctl_desc_t	      gamma_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]    = { gamma_version,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]  = { drm_getmagic,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]  = { drm_irq_busid,	  0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	     = { drm_block,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]    = { drm_unblock,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]    = { gamma_control,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]    = { drm_addmap,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]   = { drm_addbufs,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]  = { drm_markbufs,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]  = { drm_infobufs,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)]   = { drm_mapbufs,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]  = { drm_freebufs,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]    = { drm_addctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]     = { drm_rmctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]    = { drm_modctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]    = { drm_getctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]    = { drm_newctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]    = { drm_resctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]   = { drm_adddraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]    = { drm_rmdraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	     = { gamma_dma,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	     = { gamma_lock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]     = { gamma_unlock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]     = { drm_finish,	  1, 0 },
+};
+#define GAMMA_IOCTL_COUNT DRM_ARRAY_SIZE(gamma_ioctls)
+
+#ifdef MODULE
+static char		      *gamma = NULL;
+#endif
+static int 		      devices = 0;
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("3dlabs GMX 2000");
+MODULE_PARM(gamma, "s");
+MODULE_PARM(devices, "i");
+MODULE_PARM_DESC(devices,
+		 "devices=x, where x is the number of MX chips on card\n");
+#ifndef MODULE
+/* gamma_options is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_options.
+ */
+
+
+static int __init gamma_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("gamma=", gamma_options);
+#endif
+
+static int gamma_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	drm_dma_setup(dev);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+#if DRM_DMA_HISTO
+	memset(&dev->histo, 0, sizeof(dev->histo));
+#endif
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int gamma_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	if (dev->irq) gamma_irq_uninstall(dev);
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				/* Do nothing here, because this is all
+                                   handled in the AGP/GART driver. */
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	if (dev->queuelist) {
+		for (i = 0; i < dev->queue_count; i++) {
+			drm_waitlist_destroy(&dev->queuelist[i]->waitlist);
+			if (dev->queuelist[i]) {
+				drm_free(dev->queuelist[i],
+					 sizeof(*dev->queuelist[0]),
+					 DRM_MEM_QUEUES);
+				dev->queuelist[i] = NULL;
+			}
+		}
+		drm_free(dev->queuelist,
+			 dev->queue_slots * sizeof(*dev->queuelist),
+			 DRM_MEM_QUEUES);
+		dev->queuelist	 = NULL;
+	}
+
+	drm_dma_takedown(dev);
+
+	dev->queue_count     = 0;
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+int gamma_found(void)
+{
+	return devices;
+}
+
+int gamma_find_devices(void)
+{
+	struct pci_dev *d = NULL, *one = NULL, *two = NULL;
+
+	d = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_GAMMA,d);
+	if (!d) return 0;
+
+	one = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_MX,d);
+	if (!one) return 0;
+
+	/* Make sure it's on the same card, if not - no MX's found */
+	if (PCI_SLOT(d->devfn) != PCI_SLOT(one->devfn)) return 0;
+
+	two = pci_find_device(PCI_VENDOR_ID_3DLABS,PCI_DEVICE_ID_3DLABS_MX,one);
+	if (!two) return 1;
+
+	/* Make sure it's on the same card, if not - only 1 MX found */
+	if (PCI_SLOT(d->devfn) != PCI_SLOT(two->devfn)) return 1;
+
+	/* Two MX's found - we don't currently support more than 2 */
+	return 2;
+}
+
+/* gamma_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init gamma_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &gamma_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(gamma);
+#endif
+	devices = gamma_find_devices();
+	if (devices == 0) return -1;
+
+	if ((retcode = misc_register(&gamma_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", GAMMA_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, gamma_misc.minor);
+	dev->name   = GAMMA_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d with %d MX devices\n",
+		 GAMMA_NAME,
+		 GAMMA_MAJOR,
+		 GAMMA_MINOR,
+		 GAMMA_PATCHLEVEL,
+		 GAMMA_DATE,
+		 gamma_misc.minor,
+		 devices);
+
+	return 0;
+}
+
+/* gamma_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit gamma_cleanup(void)
+{
+	drm_device_t	      *dev = &gamma_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&gamma_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	gamma_takedown(dev);
+}
+
+module_init(gamma_init);
+module_exit(gamma_cleanup);
+
+
+int gamma_version(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)				     \
+	len = strlen(value);				     \
+	if (len > name##_len) len = name##_len;		     \
+	name##_len = strlen(value);			     \
+	if (len && name) {				     \
+		if (copy_to_user(name, value, len))	     \
+			return -EFAULT;			     \
+	}
+
+	version.version_major	   = GAMMA_MAJOR;
+	version.version_minor	   = GAMMA_MINOR;
+	version.version_patchlevel = GAMMA_PATCHLEVEL;
+
+	DRM_COPY(version.name, GAMMA_NAME);
+	DRM_COPY(version.date, GAMMA_DATE);
+	DRM_COPY(version.desc, GAMMA_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int gamma_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &gamma_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return gamma_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+	return retcode;
+}
+
+int gamma_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev = priv->dev;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_release(inode, filp))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_close);
+		spin_lock(&dev->count_lock);
+		if (!--dev->open_count) {
+			if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+				DRM_ERROR("Device busy: %d %d\n",
+					  atomic_read(&dev->ioctl_count),
+					  dev->blocked);
+				spin_unlock(&dev->count_lock);
+				unlock_kernel();
+				return -EBUSY;
+			}
+			spin_unlock(&dev->count_lock);
+			unlock_kernel();
+			return gamma_takedown(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+	unlock_kernel();
+	return retcode;
+}
+
+/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+
+int gamma_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= GAMMA_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &gamma_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+
+int gamma_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+	gamma_dma_schedule(dev, 1);
+	if (!dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+#if DRM_DMA_HISTOGRAM
+	atomic_inc(&dev->histo.lhld[drm_histogram_slot(get_cycles()
+						       - dev->lck_start)]);
+#endif
+
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/gamma_drv.h lia64-2.4/drivers/char/drm-4.0/gamma_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/gamma_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/gamma_drv.h	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,58 @@
+/* gamma_drv.h -- Private header for 3dlabs GMX 2000 driver -*- linux-c -*-
+ * Created: Mon Jan  4 10:05:05 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ * 
+ */
+
+#ifndef _GAMMA_DRV_H_
+#define _GAMMA_DRV_H_
+
+				/* gamma_drv.c */
+extern int  gamma_version(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  gamma_open(struct inode *inode, struct file *filp);
+extern int  gamma_release(struct inode *inode, struct file *filp);
+extern int  gamma_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  gamma_lock(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  gamma_unlock(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+
+				/* gamma_dma.c */
+extern int  gamma_dma_schedule(drm_device_t *dev, int locked);
+extern int  gamma_dma(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+extern int  gamma_irq_install(drm_device_t *dev, int irq);
+extern int  gamma_irq_uninstall(drm_device_t *dev);
+extern int  gamma_control(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  gamma_find_devices(void);
+extern int  gamma_found(void);
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_bufs.c lia64-2.4/drivers/char/drm-4.0/i810_bufs.c
--- linux-2.4.16/drivers/char/drm-4.0/i810_bufs.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_bufs.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,339 @@
+/* i810_bufs.c -- IOCTLs to manage buffers -*- linux-c -*-
+ * Created: Thu Jan 6 01:47:26 2000 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ * 
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "i810_drv.h"
+#include "linux/un.h"
+
+int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd,
+		    unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_desc_t request;
+	drm_buf_entry_t *entry;
+	drm_buf_t *buf;
+	unsigned long offset;
+	unsigned long agp_offset;
+	int count;
+	int order;
+	int size;
+	int alignment;
+	int page_order;
+	int total;
+	int byte_count;
+	int i;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	count = request.count;
+	order = drm_order(request.size);
+	size	= 1 << order;
+	agp_offset = request.agp_start;
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size) :size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total = PAGE_SIZE << page_order;
+	byte_count = 0;
+   
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+   
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM; /* May only call once for each order */
+	}
+
+	if(count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -EINVAL;
+	}
+	   
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+   
+	entry->buf_size   = size;
+	entry->page_order = page_order;
+	offset = 0;
+   
+	while(entry->buf_count < count) {
+		buf = &entry->buflist[entry->buf_count];
+		buf->idx = dma->buf_count + entry->buf_count;
+		buf->total = alignment;
+		buf->order = order;
+		buf->used = 0;
+		buf->offset = offset;
+		buf->bus_address = dev->agp->base + agp_offset + offset;
+		buf->address = (void *)(agp_offset + offset + dev->agp->base);
+		buf->next = NULL;
+		buf->waiting = 0;
+		buf->pending = 0;
+		init_waitqueue_head(&buf->dma_wait);
+		buf->pid = 0;
+
+		buf->dev_private = drm_alloc(sizeof(drm_i810_buf_priv_t), 
+					     DRM_MEM_BUFS);
+		buf->dev_priv_size = sizeof(drm_i810_buf_priv_t);
+	   	memset(buf->dev_private, 0, sizeof(drm_i810_buf_priv_t));
+
+#if DRM_DMA_HISTOGRAM
+		buf->time_queued = 0;
+		buf->time_dispatched = 0;
+		buf->time_completed = 0;
+		buf->time_freed = 0;
+#endif
+		offset = offset + alignment;
+		entry->buf_count++;
+		byte_count += PAGE_SIZE << page_order;
+      
+		DRM_DEBUG("buffer %d @ %p\n",
+			  entry->buf_count, buf->address);
+	}
+   
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+   
+	dma->buf_count  += entry->buf_count;
+	dma->byte_count += byte_count;
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+   
+	up(&dev->struct_sem);
+   
+	request.count = entry->buf_count;
+	request.size  = size;
+   
+	if (copy_to_user((drm_buf_desc_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+   
+	atomic_dec(&dev->buf_alloc);
+	dma->flags = _DRM_DMA_USE_AGP;
+	return 0;
+}
+
+int i810_addbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_buf_desc_t	 request;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	if(request.flags & _DRM_AGP_BUFFER)
+		return i810_addbufs_agp(inode, filp, cmd, arg);
+	else
+		return -EINVAL;
+}
+
+int i810_infobufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_info_t	 request;
+	int		 i;
+	int		 count;
+
+	if (!dma) return -EINVAL;
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_info_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+		if (dma->bufs[i].buf_count) ++count;
+	}
+	
+	DRM_DEBUG("count = %d\n", count);
+	
+	if (request.count >= count) {
+		for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+			if (dma->bufs[i].buf_count) {
+				if (copy_to_user(&request.list[count].count,
+						 &dma->bufs[i].buf_count,
+						 sizeof(dma->bufs[0]
+							.buf_count)) ||
+				    copy_to_user(&request.list[count].size,
+						 &dma->bufs[i].buf_size,
+						 sizeof(dma->bufs[0].buf_size)) ||
+				    copy_to_user(&request.list[count].low_mark,
+						 &dma->bufs[i]
+						 .freelist.low_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.low_mark)) ||
+				    copy_to_user(&request.list[count]
+						 .high_mark,
+						 &dma->bufs[i]
+						 .freelist.high_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.high_mark)))
+					return -EFAULT;
+
+				DRM_DEBUG("%d %d %d %d %d\n",
+					  i,
+					  dma->bufs[i].buf_count,
+					  dma->bufs[i].buf_size,
+					  dma->bufs[i].freelist.low_mark,
+					  dma->bufs[i].freelist.high_mark);
+				++count;
+			}
+		}
+	}
+	request.count = count;
+
+	if (copy_to_user((drm_buf_info_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+	
+	return 0;
+}
+
+int i810_markbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_desc_t	 request;
+	int		 order;
+	drm_buf_entry_t	 *entry;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	DRM_DEBUG("%d, %d, %d\n",
+		  request.size, request.low_mark, request.high_mark);
+	order = drm_order(request.size);
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	entry = &dma->bufs[order];
+
+	if (request.low_mark < 0 || request.low_mark > entry->buf_count)
+		return -EINVAL;
+	if (request.high_mark < 0 || request.high_mark > entry->buf_count)
+		return -EINVAL;
+
+	entry->freelist.low_mark  = request.low_mark;
+	entry->freelist.high_mark = request.high_mark;
+	
+	return 0;
+}
+
+int i810_freebufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_free_t	 request;
+	int		 i;
+	int		 idx;
+	drm_buf_t	 *buf;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_free_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	DRM_DEBUG("%d\n", request.count);
+	for (i = 0; i < request.count; i++) {
+		if (copy_from_user(&idx,
+				   &request.list[i],
+				   sizeof(idx)))
+			return -EFAULT;
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+				  idx, dma->buf_count - 1);
+			return -EINVAL;
+		}
+		buf = dma->buflist[idx];
+		if (buf->pid != current->pid) {
+			DRM_ERROR("Process %d freeing buffer owned by %d\n",
+				  current->pid, buf->pid);
+			return -EINVAL;
+		}
+		drm_free_buffer(dev, buf);
+	}
+	
+	return 0;
+}
+
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_context.c lia64-2.4/drivers/char/drm-4.0/i810_context.c
--- linux-2.4.16/drivers/char/drm-4.0/i810_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_context.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,212 @@
+/* i810_context.c -- IOCTLs for i810 contexts -*- linux-c -*-
+ * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "i810_drv.h"
+
+static int i810_alloc_queue(drm_device_t *dev)
+{
+   	int temp = drm_ctxbitmap_next(dev);
+   	DRM_DEBUG("i810_alloc_queue: %d\n", temp);
+	return temp;
+}
+
+int i810_context_switch(drm_device_t *dev, int old, int new)
+{
+        char        buf[64];
+
+        atomic_inc(&dev->total_ctx);
+
+        if (test_and_set_bit(0, &dev->context_flag)) {
+                DRM_ERROR("Reentering -- FIXME\n");
+                return -EBUSY;
+        }
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+        
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context) {
+                clear_bit(0, &dev->context_flag);
+                return 0;
+        }
+        
+        if (drm_flags & DRM_FLAG_NOCTX) {
+                i810_context_switch_complete(dev, new);
+        } else {
+                sprintf(buf, "C %d %d\n", old, new);
+                drm_write_string(dev, buf);
+        }
+        
+        return 0;
+}
+
+int i810_context_switch_complete(drm_device_t *dev, int new)
+{
+        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+        dev->last_switch  = jiffies;
+        
+        if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+                DRM_ERROR("Lock isn't held after context switch\n");
+        }
+
+				/* If a context switch is ever initiated
+                                   when the kernel holds the lock, release
+                                   that lock here. */
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+                                                      - dev->ctx_start)]);
+                   
+#endif
+        clear_bit(0, &dev->context_flag);
+        wake_up(&dev->context_wait);
+        
+        return 0;
+}
+
+int i810_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+int i810_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = i810_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Skip kernel's context and get a new one. */
+		ctx.handle = i810_alloc_queue(dev);
+	}
+        if (ctx.handle == -1) {
+		DRM_DEBUG("Not enough free contexts.\n");
+				/* Should this return -EBUSY instead? */
+		return -ENOMEM;
+	}
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int i810_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+   	/* This does nothing for the i810 */
+	return 0;
+}
+
+int i810_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	/* This is 0, because we don't hanlde any context flags */
+	ctx.flags = 0;
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int i810_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return i810_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int i810_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	i810_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int i810_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+   	if(ctx.handle != DRM_KERNEL_CONTEXT) {
+	   	drm_ctxbitmap_free(dev, ctx.handle);
+	}
+	
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_dma.c lia64-2.4/drivers/char/drm-4.0/i810_dma.c
--- linux-2.4.16/drivers/char/drm-4.0/i810_dma.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_dma.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,1438 @@
+/* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *          Keith Whitwell <keithw@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "i810_drv.h"
+#include <linux/interrupt.h>	/* For task queue support */
+
+/* in case we don't have a 2.3.99-pre6 kernel or later: */
+#ifndef VM_DONTCOPY
+#define VM_DONTCOPY 0
+#endif
+
+#define I810_BUF_FREE		2
+#define I810_BUF_CLIENT		1
+#define I810_BUF_HARDWARE      	0
+
+#define I810_BUF_UNMAPPED 0
+#define I810_BUF_MAPPED   1
+
+#define I810_REG(reg)		2
+#define I810_BASE(reg)		((unsigned long) \
+				dev->maplist[I810_REG(reg)]->handle)
+#define I810_ADDR(reg)		(I810_BASE(reg) + reg)
+#define I810_DEREF(reg)		*(__volatile__ int *)I810_ADDR(reg)
+#define I810_READ(reg)		I810_DEREF(reg)
+#define I810_WRITE(reg,val) 	do { I810_DEREF(reg) = val; } while (0)
+#define I810_DEREF16(reg)	*(__volatile__ u16 *)I810_ADDR(reg)
+#define I810_READ16(reg)	I810_DEREF16(reg)
+#define I810_WRITE16(reg,val)	do { I810_DEREF16(reg) = val; } while (0)
+
+#define RING_LOCALS	unsigned int outring, ringmask; volatile char *virt;
+
+#define BEGIN_LP_RING(n) do {				\
+	if (I810_VERBOSE)				\
+		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
+			  n, __FUNCTION__);		\
+	if (dev_priv->ring.space < n*4) 		\
+		i810_wait_ring(dev, n*4);		\
+	dev_priv->ring.space -= n*4;			\
+	outring = dev_priv->ring.tail;			\
+	ringmask = dev_priv->ring.tail_mask;		\
+	virt = dev_priv->ring.virtual_start;		\
+} while (0)
+
+#define ADVANCE_LP_RING() do {					\
+	if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n");	\
+	dev_priv->ring.tail = outring;				\
+	I810_WRITE(LP_RING + RING_TAIL, outring);		\
+} while(0)
+
+#define OUT_RING(n) do {						\
+	if (I810_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
+	*(volatile unsigned int *)(virt + outring) = n;			\
+	outring += 4;							\
+	outring &= ringmask;						\
+} while (0);
+
+static inline void i810_print_status_page(drm_device_t *dev)
+{
+   	drm_device_dma_t *dma = dev->dma;
+      	drm_i810_private_t *dev_priv = dev->dev_private;
+	u32 *temp = (u32 *)dev_priv->hw_status_page;
+   	int i;
+
+   	DRM_DEBUG(  "hw_status: Interrupt Status : %x\n", temp[0]);
+   	DRM_DEBUG(  "hw_status: LpRing Head ptr : %x\n", temp[1]);
+   	DRM_DEBUG(  "hw_status: IRing Head ptr : %x\n", temp[2]);
+      	DRM_DEBUG(  "hw_status: Reserved : %x\n", temp[3]);
+   	DRM_DEBUG(  "hw_status: Driver Counter : %d\n", temp[5]);
+   	for(i = 6; i < dma->buf_count + 6; i++) {
+	   	DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]);
+	}
+}
+
+static drm_buf_t *i810_freelist_get(drm_device_t *dev)
+{
+   	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+   	int 		 used;
+   
+	/* Linear search might not be the best solution */
+
+   	for (i = 0; i < dma->buf_count; i++) {
+	   	drm_buf_t *buf = dma->buflist[ i ];
+	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+		/* In use is already a pointer */
+	   	used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, 
+			       I810_BUF_CLIENT);
+	   	if(used == I810_BUF_FREE) {
+			return buf;
+		}
+	}
+   	return NULL;
+}
+
+/* This should only be called if the buffer is not sent to the hardware
+ * yet, the hardware updates in use for us once its on the ring buffer.
+ */
+
+static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
+{
+   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+   	int used;
+   
+   	/* In use is already a pointer */
+   	used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
+   	if(used != I810_BUF_CLIENT) {
+	   	DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
+	   	return -EINVAL;
+	}
+   
+   	return 0;
+}
+
+static struct file_operations i810_buffer_fops = {
+	open:	 i810_open,
+	flush:	 drm_flush,
+	release: i810_release,
+	ioctl:	 i810_ioctl,
+	mmap:	 i810_mmap_buffers,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+      	poll:	 drm_poll,
+};
+
+int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
+{
+	drm_file_t	    *priv	  = filp->private_data;
+	drm_device_t	    *dev;
+	drm_i810_private_t  *dev_priv;
+	drm_buf_t           *buf;
+	drm_i810_buf_priv_t *buf_priv;
+
+	lock_kernel();
+	dev	 = priv->dev;
+	dev_priv = dev->dev_private;
+	buf      = dev_priv->mmap_buffer;
+	buf_priv = buf->dev_private;
+   
+	vma->vm_flags |= (VM_IO | VM_DONTCOPY);
+	vma->vm_file = filp;
+   
+   	buf_priv->currently_mapped = I810_BUF_MAPPED;
+	unlock_kernel();
+
+	if (remap_page_range(vma->vm_start,
+			     VM_OFFSET(vma),
+			     vma->vm_end - vma->vm_start,
+			     vma->vm_page_prot)) return -EAGAIN;
+	return 0;
+}
+
+static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+      	drm_i810_private_t *dev_priv = dev->dev_private;
+   	struct file_operations *old_fops;
+	int retcode = 0;
+
+	if(buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL;
+
+	if(VM_DONTCOPY != 0) {
+		down_write(&current->mm->mmap_sem);
+		old_fops = filp->f_op;
+		filp->f_op = &i810_buffer_fops;
+		dev_priv->mmap_buffer = buf;
+		buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, 
+						    PROT_READ|PROT_WRITE,
+						    MAP_SHARED, 
+						    buf->bus_address);
+		dev_priv->mmap_buffer = NULL;
+   		filp->f_op = old_fops;
+		if ((unsigned long)buf_priv->virtual > -1024UL) {
+			/* Real error */
+			DRM_DEBUG("mmap error\n");
+			retcode = (signed int)buf_priv->virtual;
+			buf_priv->virtual = 0;
+		}
+   		up_write(&current->mm->mmap_sem);
+	} else {
+		buf_priv->virtual = buf_priv->kernel_virtual;
+   		buf_priv->currently_mapped = I810_BUF_MAPPED;
+	}
+	return retcode;
+}
+
+static int i810_unmap_buffer(drm_buf_t *buf)
+{
+	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+	int retcode = 0;
+
+	if(VM_DONTCOPY != 0) {
+		if(buf_priv->currently_mapped != I810_BUF_MAPPED) 
+			return -EINVAL;
+		down_write(&current->mm->mmap_sem);
+#if LINUX_VERSION_CODE < 0x020399
+        	retcode = do_munmap((unsigned long)buf_priv->virtual, 
+				    (size_t) buf->total);
+#else
+        	retcode = do_munmap(current->mm, 
+				    (unsigned long)buf_priv->virtual, 
+				    (size_t) buf->total);
+#endif
+   		up_write(&current->mm->mmap_sem);
+	}
+   	buf_priv->currently_mapped = I810_BUF_UNMAPPED;
+   	buf_priv->virtual = 0;
+
+	return retcode;
+}
+
+static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, 
+			       struct file *filp)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_buf_t	  *buf;
+	drm_i810_buf_priv_t *buf_priv;
+	int retcode = 0;
+
+	buf = i810_freelist_get(dev);
+	if (!buf) {
+		retcode = -ENOMEM;
+	   	DRM_DEBUG("retcode=%d\n", retcode);
+		return retcode;
+	}
+   
+	retcode = i810_map_buffer(buf, filp);
+	if(retcode) {
+		i810_freelist_put(dev, buf);
+	   	DRM_DEBUG("mapbuf failed, retcode %d\n", retcode);
+		return retcode;
+	}
+	buf->pid     = priv->pid;
+	buf_priv = buf->dev_private;	
+	d->granted = 1;
+   	d->request_idx = buf->idx;
+   	d->request_size = buf->total;
+   	d->virtual = buf_priv->virtual;
+
+	return retcode;
+}
+
+static unsigned long i810_alloc_page(drm_device_t *dev)
+{
+	unsigned long address;
+   
+	address = __get_free_page(GFP_KERNEL);
+	if(address == 0UL) 
+		return 0;
+	
+	atomic_inc(&virt_to_page(address)->count);
+	set_bit(PG_locked, &virt_to_page(address)->flags);
+   
+	return address;
+}
+
+static void i810_free_page(drm_device_t *dev, unsigned long page)
+{
+	if(page == 0UL) 
+		return;
+	
+	atomic_dec(&virt_to_page(page)->count);
+	clear_bit(PG_locked, &virt_to_page(page)->flags);
+	wake_up(&virt_to_page(page)->wait);
+	free_page(page);
+	return;
+}
+
+static int i810_dma_cleanup(drm_device_t *dev)
+{
+	drm_device_dma_t *dma = dev->dma;
+
+	if(dev->dev_private) {
+		int i;
+	   	drm_i810_private_t *dev_priv = 
+	     		(drm_i810_private_t *) dev->dev_private;
+	   
+	   	if(dev_priv->ring.virtual_start) {
+		   	drm_ioremapfree((void *) dev_priv->ring.virtual_start,
+					dev_priv->ring.Size, dev);
+		}
+	   	if(dev_priv->hw_status_page != 0UL) {
+		   	i810_free_page(dev, dev_priv->hw_status_page);
+		   	/* Need to rewrite hardware status page */
+		   	I810_WRITE(0x02080, 0x1ffff000);
+		}
+	   	drm_free(dev->dev_private, sizeof(drm_i810_private_t), 
+			 DRM_MEM_DRIVER);
+	   	dev->dev_private = NULL;
+
+		for (i = 0; i < dma->buf_count; i++) {
+			drm_buf_t *buf = dma->buflist[ i ];
+			drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+			drm_ioremapfree(buf_priv->kernel_virtual,
+							buf->total, dev);
+		}
+	}
+   	return 0;
+}
+
+static int i810_wait_ring(drm_device_t *dev, int n)
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+   	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
+   	int iters = 0;
+   	unsigned long end;
+	unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+
+	end = jiffies + (HZ*3);
+   	while (ring->space < n) {
+	   	int i;
+	
+	   	ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	   	ring->space = ring->head - (ring->tail+8);
+		if (ring->space < 0) ring->space += ring->Size;
+	   
+		if (ring->head != last_head)
+		   end = jiffies + (HZ*3);
+	  
+	   	iters++;
+		if((signed)(end - jiffies) <= 0) {
+		   	DRM_ERROR("space: %d wanted %d\n", ring->space, n);
+		   	DRM_ERROR("lockup\n");
+		   	goto out_wait_ring;
+		}
+
+	   	for (i = 0 ; i < 2000 ; i++) ;
+	}
+
+out_wait_ring:   
+   	return iters;
+}
+
+static void i810_kernel_lost_context(drm_device_t *dev)
+{
+      	drm_i810_private_t *dev_priv = dev->dev_private;
+   	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
+      
+   	ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+     	ring->tail = I810_READ(LP_RING + RING_TAIL);
+     	ring->space = ring->head - (ring->tail+8);
+     	if (ring->space < 0) ring->space += ring->Size;
+}
+
+static int i810_freelist_init(drm_device_t *dev)
+{
+      	drm_device_dma_t *dma = dev->dma;
+   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+   	int my_idx = 24;
+   	u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
+   	int i;
+   
+   	if(dma->buf_count > 1019) {
+	   	/* Not enough space in the status page for the freelist */
+	   	return -EINVAL;
+	}
+
+   	for (i = 0; i < dma->buf_count; i++) {
+	   	drm_buf_t *buf = dma->buflist[ i ];
+	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+	   
+	   	buf_priv->in_use = hw_status++;
+	   	buf_priv->my_use_idx = my_idx;
+	   	my_idx += 4;
+
+	   	*buf_priv->in_use = I810_BUF_FREE;
+
+		buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, 
+						       buf->total, dev);
+	}
+	return 0;
+}
+
+static int i810_dma_initialize(drm_device_t *dev, 
+			       drm_i810_private_t *dev_priv,
+			       drm_i810_init_t *init)
+{
+	drm_map_t *sarea_map;
+
+   	dev->dev_private = (void *) dev_priv;
+   	memset(dev_priv, 0, sizeof(drm_i810_private_t));
+
+   	if (init->ring_map_idx >= dev->map_count ||
+	    init->buffer_map_idx >= dev->map_count) {
+	   	i810_dma_cleanup(dev);
+	   	DRM_ERROR("ring_map or buffer_map are invalid\n");
+	   	return -EINVAL;
+	}
+   
+   	dev_priv->ring_map_idx = init->ring_map_idx;
+   	dev_priv->buffer_map_idx = init->buffer_map_idx;
+	sarea_map = dev->maplist[0];
+	dev_priv->sarea_priv = (drm_i810_sarea_t *) 
+		((u8 *)sarea_map->handle + 
+		 init->sarea_priv_offset);
+
+   	atomic_set(&dev_priv->flush_done, 0);
+	init_waitqueue_head(&dev_priv->flush_queue);
+   	
+   	dev_priv->ring.Start = init->ring_start;
+   	dev_priv->ring.End = init->ring_end;
+   	dev_priv->ring.Size = init->ring_size;
+
+   	dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + 
+						   init->ring_start, 
+						   init->ring_size, dev);
+
+   	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+   
+   	if (dev_priv->ring.virtual_start == NULL) {
+	   	i810_dma_cleanup(dev);
+	   	DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+	   	return -ENOMEM;
+	}
+
+	dev_priv->w = init->w;
+	dev_priv->h = init->h;
+	dev_priv->pitch = init->pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->depth_offset = init->depth_offset;
+
+	dev_priv->front_di1 = init->front_offset | init->pitch_bits;
+	dev_priv->back_di1 = init->back_offset | init->pitch_bits;
+	dev_priv->zi1 = init->depth_offset | init->pitch_bits;
+	
+   
+   	/* Program Hardware Status Page */
+   	dev_priv->hw_status_page = i810_alloc_page(dev);
+   	memset((void *) dev_priv->hw_status_page, 0, PAGE_SIZE);
+   	if(dev_priv->hw_status_page == 0UL) {
+		i810_dma_cleanup(dev);
+		DRM_ERROR("Can not allocate hardware status page\n");
+		return -ENOMEM;
+	}
+   	DRM_DEBUG("hw status page @ %lx\n", dev_priv->hw_status_page);
+   
+   	I810_WRITE(0x02080, virt_to_bus((void *)dev_priv->hw_status_page));
+   	DRM_DEBUG("Enabled hardware status page\n");
+   
+   	/* Now we need to init our freelist */
+   	if(i810_freelist_init(dev) != 0) {
+	   	i810_dma_cleanup(dev);
+	   	DRM_ERROR("Not enough space in the status page for"
+			  " the freelist\n");
+	   	return -ENOMEM;
+	}
+   	return 0;
+}
+
+int i810_dma_init(struct inode *inode, struct file *filp,
+		  unsigned int cmd, unsigned long arg)
+{
+   	drm_file_t *priv = filp->private_data;
+   	drm_device_t *dev = priv->dev;
+   	drm_i810_private_t *dev_priv;
+   	drm_i810_init_t init;
+   	int retcode = 0;
+	
+  	if (copy_from_user(&init, (drm_i810_init_t *)arg, sizeof(init)))
+		return -EFAULT;
+	
+   	switch(init.func) {
+	 	case I810_INIT_DMA:
+	   		dev_priv = drm_alloc(sizeof(drm_i810_private_t), 
+					     DRM_MEM_DRIVER);
+	   		if(dev_priv == NULL) return -ENOMEM;
+	   		retcode = i810_dma_initialize(dev, dev_priv, &init);
+	   	break;
+	 	case I810_CLEANUP_DMA:
+	   		retcode = i810_dma_cleanup(dev);
+	   	break;
+	 	default:
+	   		retcode = -EINVAL;
+	   	break;
+	}
+   
+   	return retcode;
+}
+
+
+
+/* Most efficient way to verify state for the i810 is as it is
+ * emitted.  Non-conformant state is silently dropped.
+ *
+ * Use 'volatile' & local var tmp to force the emitted values to be
+ * identical to the verified ones.
+ */
+static void i810EmitContextVerified( drm_device_t *dev, 
+				     volatile unsigned int *code ) 
+{	
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+	int i, j = 0;
+	unsigned int tmp;
+	RING_LOCALS;
+
+	BEGIN_LP_RING( I810_CTX_SETUP_SIZE );
+
+	OUT_RING( GFX_OP_COLOR_FACTOR );
+	OUT_RING( code[I810_CTXREG_CF1] );
+
+	OUT_RING( GFX_OP_STIPPLE );
+	OUT_RING( code[I810_CTXREG_ST1] );
+
+	for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) {
+		tmp = code[i];
+
+		if ((tmp & (7<<29)) == (3<<29) &&
+		    (tmp & (0x1f<<24)) < (0x1d<<24)) 
+		{
+			OUT_RING( tmp ); 
+			j++;
+		} 
+	}
+
+	if (j & 1) 
+		OUT_RING( 0 ); 
+
+	ADVANCE_LP_RING();
+}
+
+static void i810EmitTexVerified( drm_device_t *dev, 
+				 volatile unsigned int *code ) 
+{	
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+	int i, j = 0;
+	unsigned int tmp;
+	RING_LOCALS;
+
+	BEGIN_LP_RING( I810_TEX_SETUP_SIZE );
+
+	OUT_RING( GFX_OP_MAP_INFO );
+	OUT_RING( code[I810_TEXREG_MI1] );
+	OUT_RING( code[I810_TEXREG_MI2] );
+	OUT_RING( code[I810_TEXREG_MI3] );
+
+	for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) {
+		tmp = code[i];
+
+		if ((tmp & (7<<29)) == (3<<29) &&
+		    (tmp & (0x1f<<24)) < (0x1d<<24)) 
+		{
+			OUT_RING( tmp ); 
+			j++;
+		}
+	} 
+		
+	if (j & 1) 
+		OUT_RING( 0 ); 
+
+	ADVANCE_LP_RING();
+}
+
+
+/* Need to do some additional checking when setting the dest buffer.
+ */
+static void i810EmitDestVerified( drm_device_t *dev, 
+				  volatile unsigned int *code ) 
+{	
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+	unsigned int tmp;
+	RING_LOCALS;
+
+	BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
+
+	tmp = code[I810_DESTREG_DI1];
+	if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
+		OUT_RING( CMD_OP_DESTBUFFER_INFO );
+		OUT_RING( tmp );
+	} else
+	   DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
+		     tmp, dev_priv->front_di1, dev_priv->back_di1);
+
+	/* invarient:
+	 */
+	OUT_RING( CMD_OP_Z_BUFFER_INFO );
+	OUT_RING( dev_priv->zi1 );
+
+	OUT_RING( GFX_OP_DESTBUFFER_VARS );
+	OUT_RING( code[I810_DESTREG_DV1] );
+
+	OUT_RING( GFX_OP_DRAWRECT_INFO );
+	OUT_RING( code[I810_DESTREG_DR1] );
+	OUT_RING( code[I810_DESTREG_DR2] );
+	OUT_RING( code[I810_DESTREG_DR3] );
+	OUT_RING( code[I810_DESTREG_DR4] );
+	OUT_RING( 0 );
+
+	ADVANCE_LP_RING();
+}
+
+
+
+static void i810EmitState( drm_device_t *dev )
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int dirty = sarea_priv->dirty;
+
+	if (dirty & I810_UPLOAD_BUFFERS) {
+		i810EmitDestVerified( dev, sarea_priv->BufferState );
+		sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
+	}
+
+	if (dirty & I810_UPLOAD_CTX) {
+		i810EmitContextVerified( dev, sarea_priv->ContextState );
+		sarea_priv->dirty &= ~I810_UPLOAD_CTX;
+	}
+
+	if (dirty & I810_UPLOAD_TEX0) {
+		i810EmitTexVerified( dev, sarea_priv->TexState[0] );
+		sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
+	}
+
+	if (dirty & I810_UPLOAD_TEX1) {
+		i810EmitTexVerified( dev, sarea_priv->TexState[1] );
+		sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
+	}
+}
+
+
+
+/* need to verify 
+ */
+static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, 
+				     unsigned int clear_color,
+				     unsigned int clear_zval )
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	int pitch = dev_priv->pitch;
+	int cpp = 2;
+	int i;
+	RING_LOCALS;
+
+  	i810_kernel_lost_context(dev);
+
+      	if (nbox > I810_NR_SAREA_CLIPRECTS)
+     		nbox = I810_NR_SAREA_CLIPRECTS;
+
+	for (i = 0 ; i < nbox ; i++, pbox++) {
+		unsigned int x = pbox->x1;
+		unsigned int y = pbox->y1;
+		unsigned int width = (pbox->x2 - x) * cpp;
+		unsigned int height = pbox->y2 - y;
+		unsigned int start = y * pitch + x * cpp;
+
+		if (pbox->x1 > pbox->x2 ||
+		    pbox->y1 > pbox->y2 ||
+		    pbox->x2 > dev_priv->w ||
+		    pbox->y2 > dev_priv->h)
+			continue;
+
+	   	if ( flags & I810_FRONT ) {	    
+		   	DRM_DEBUG("clear front\n");
+			BEGIN_LP_RING( 6 );	    
+			OUT_RING( BR00_BITBLT_CLIENT | 
+				  BR00_OP_COLOR_BLT | 0x3 );
+			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
+			OUT_RING( (height << 16) | width );
+			OUT_RING( start );
+			OUT_RING( clear_color );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+		}
+
+		if ( flags & I810_BACK ) {
+			DRM_DEBUG("clear back\n");
+			BEGIN_LP_RING( 6 );	    
+			OUT_RING( BR00_BITBLT_CLIENT | 
+				  BR00_OP_COLOR_BLT | 0x3 );
+			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
+			OUT_RING( (height << 16) | width );
+			OUT_RING( dev_priv->back_offset + start );
+			OUT_RING( clear_color );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+		}
+
+		if ( flags & I810_DEPTH ) {
+			DRM_DEBUG("clear depth\n");
+			BEGIN_LP_RING( 6 );	    
+			OUT_RING( BR00_BITBLT_CLIENT | 
+				  BR00_OP_COLOR_BLT | 0x3 );
+			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
+			OUT_RING( (height << 16) | width );
+			OUT_RING( dev_priv->depth_offset + start );
+			OUT_RING( clear_zval );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+		}
+	}
+}
+
+static void i810_dma_dispatch_swap( drm_device_t *dev )
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	int pitch = dev_priv->pitch;
+	int cpp = 2;
+	int ofs = dev_priv->back_offset;
+	int i;
+	RING_LOCALS;
+
+	DRM_DEBUG("swapbuffers\n");
+
+  	i810_kernel_lost_context(dev);
+
+      	if (nbox > I810_NR_SAREA_CLIPRECTS)
+     		nbox = I810_NR_SAREA_CLIPRECTS;
+
+	for (i = 0 ; i < nbox; i++, pbox++) 
+	{
+		unsigned int w = pbox->x2 - pbox->x1;
+		unsigned int h = pbox->y2 - pbox->y1;
+		unsigned int dst = pbox->x1*cpp + pbox->y1*pitch;
+		unsigned int start = ofs + dst;
+
+		if (pbox->x1 > pbox->x2 ||
+		    pbox->y1 > pbox->y2 ||
+		    pbox->x2 > dev_priv->w ||
+		    pbox->y2 > dev_priv->h)
+			continue;
+ 
+	   	DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
+			  pbox[i].x1, pbox[i].y1,
+			  pbox[i].x2, pbox[i].y2);
+
+		BEGIN_LP_RING( 6 );
+		OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 );
+		OUT_RING( pitch | (0xCC << 16));
+		OUT_RING( (h << 16) | (w * cpp));
+		OUT_RING( dst );
+		OUT_RING( pitch );	
+		OUT_RING( start );
+		ADVANCE_LP_RING();
+	}
+}
+
+
+static void i810_dma_dispatch_vertex(drm_device_t *dev, 
+				     drm_buf_t *buf,
+				     int discard,
+				     int used)
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+   	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
+   	drm_clip_rect_t *box = sarea_priv->boxes;
+   	int nbox = sarea_priv->nbox;
+	unsigned long address = (unsigned long)buf->bus_address;
+	unsigned long start = address - dev->agp->base;     
+	int i = 0, u;
+   	RING_LOCALS;
+
+   	i810_kernel_lost_context(dev);
+
+   	if (nbox > I810_NR_SAREA_CLIPRECTS) 
+		nbox = I810_NR_SAREA_CLIPRECTS;
+
+	if (discard) {
+		u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, 
+			    I810_BUF_HARDWARE);
+		if(u != I810_BUF_CLIENT) {
+			DRM_DEBUG("xxxx 2\n");
+		}
+	}
+
+	if (used > 4*1024) 
+		used = 0;
+
+	if (sarea_priv->dirty)
+	   i810EmitState( dev );
+
+  	DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", 
+		  address, used, nbox);
+
+   	dev_priv->counter++;
+   	DRM_DEBUG(  "dispatch counter : %ld\n", dev_priv->counter);
+   	DRM_DEBUG(  "i810_dma_dispatch\n");
+   	DRM_DEBUG(  "start : %lx\n", start);
+	DRM_DEBUG(  "used : %d\n", used);
+   	DRM_DEBUG(  "start + used - 4 : %ld\n", start + used - 4);
+
+	if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
+		*(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE |
+					     sarea_priv->vertex_prim |
+					     ((used/4)-2));
+		
+		if (used & 4) {
+			*(u32 *)((u32)buf_priv->virtual + used) = 0;
+			used += 4;
+		}
+
+		i810_unmap_buffer(buf);
+	}
+		   
+	if (used) {
+		do {
+			if (i < nbox) {
+				BEGIN_LP_RING(4);
+				OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | 
+					  SC_ENABLE );
+				OUT_RING( GFX_OP_SCISSOR_INFO );
+				OUT_RING( box[i].x1 | (box[i].y1<<16) );
+				OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
+				ADVANCE_LP_RING();
+			}
+			
+			BEGIN_LP_RING(4);
+			OUT_RING( CMD_OP_BATCH_BUFFER );
+			OUT_RING( start | BB1_PROTECTED );
+			OUT_RING( start + used - 4 );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+			
+		} while (++i < nbox);
+	}
+
+	BEGIN_LP_RING(10);
+	OUT_RING( CMD_STORE_DWORD_IDX );
+	OUT_RING( 20 );
+	OUT_RING( dev_priv->counter );
+	OUT_RING( 0 );
+
+	if (discard) {
+		OUT_RING( CMD_STORE_DWORD_IDX );
+		OUT_RING( buf_priv->my_use_idx );
+		OUT_RING( I810_BUF_FREE );
+		OUT_RING( 0 );
+	}
+
+      	OUT_RING( CMD_REPORT_HEAD );
+	OUT_RING( 0 );
+   	ADVANCE_LP_RING();
+}
+
+
+/* Interrupts are only for flushing */
+static void i810_dma_service(int irq, void *device, struct pt_regs *regs)
+{
+	drm_device_t	 *dev = (drm_device_t *)device;
+   	u16 temp;
+   
+	atomic_inc(&dev->total_irq);
+      	temp = I810_READ16(I810REG_INT_IDENTITY_R);
+   	temp = temp & ~(0x6000);
+   	if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, 
+				   temp); /* Clear all interrupts */
+	else
+	   return;
+ 
+   	queue_task(&dev->tq, &tq_immediate);
+   	mark_bh(IMMEDIATE_BH);
+}
+
+static void i810_dma_task_queue(void *device)
+{
+	drm_device_t *dev = (drm_device_t *) device;
+      	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+
+   	atomic_set(&dev_priv->flush_done, 1);
+   	wake_up_interruptible(&dev_priv->flush_queue);
+}
+
+int i810_irq_install(drm_device_t *dev, int irq)
+{
+	int retcode;
+	u16 temp;
+   
+	if (!irq)     return -EINVAL;
+	
+	down(&dev->struct_sem);
+	if (dev->irq) {
+		up(&dev->struct_sem);
+		return -EBUSY;
+	}
+	dev->irq = irq;
+	up(&dev->struct_sem);
+	
+   	DRM_DEBUG(  "Interrupt Install : %d\n", irq);
+	DRM_DEBUG("%d\n", irq);
+
+	dev->context_flag     = 0;
+	dev->interrupt_flag   = 0;
+	dev->dma_flag	      = 0;
+	
+	dev->dma->next_buffer = NULL;
+	dev->dma->next_queue  = NULL;
+	dev->dma->this_buffer = NULL;
+
+	INIT_LIST_HEAD(&dev->tq.list);
+	dev->tq.sync	      = 0;
+	dev->tq.routine	      = i810_dma_task_queue;
+	dev->tq.data	      = dev;
+
+				/* Before installing handler */
+   	temp = I810_READ16(I810REG_HWSTAM);
+   	temp = temp & 0x6000;
+   	I810_WRITE16(I810REG_HWSTAM, temp);
+   	
+      	temp = I810_READ16(I810REG_INT_MASK_R);
+   	temp = temp & 0x6000;
+   	I810_WRITE16(I810REG_INT_MASK_R, temp); /* Unmask interrupts */
+   	temp = I810_READ16(I810REG_INT_ENABLE_R);
+   	temp = temp & 0x6000;
+      	I810_WRITE16(I810REG_INT_ENABLE_R, temp); /* Disable all interrupts */
+
+				/* Install handler */
+	if ((retcode = request_irq(dev->irq,
+				   i810_dma_service,
+				   SA_SHIRQ,
+				   dev->devname,
+				   dev))) {
+		down(&dev->struct_sem);
+		dev->irq = 0;
+		up(&dev->struct_sem);
+		return retcode;
+	}
+   	temp = I810_READ16(I810REG_INT_ENABLE_R);
+   	temp = temp & 0x6000;
+   	temp = temp | 0x0003;
+   	I810_WRITE16(I810REG_INT_ENABLE_R, 
+		     temp); /* Enable bp & user interrupts */
+	return 0;
+}
+
+int i810_irq_uninstall(drm_device_t *dev)
+{
+	int irq;
+   	u16 temp;
+
+
+/*  	return 0; */
+
+	down(&dev->struct_sem);
+	irq	 = dev->irq;
+	dev->irq = 0;
+	up(&dev->struct_sem);
+	
+	if (!irq) return -EINVAL;
+
+   	DRM_DEBUG(  "Interrupt UnInstall: %d\n", irq);	
+	DRM_DEBUG("%d\n", irq);
+   
+   	temp = I810_READ16(I810REG_INT_IDENTITY_R);
+   	temp = temp & ~(0x6000);
+   	if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, 
+				   temp); /* Clear all interrupts */
+   
+   	temp = I810_READ16(I810REG_INT_ENABLE_R);
+   	temp = temp & 0x6000;
+   	I810_WRITE16(I810REG_INT_ENABLE_R, 
+		     temp);                     /* Disable all interrupts */
+
+   	free_irq(irq, dev);
+
+	return 0;
+}
+
+int i810_control(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_control_t	ctl;
+	int		retcode;
+   
+   	DRM_DEBUG(  "i810_control\n");
+
+	if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl)))
+		return -EFAULT;
+	
+	switch (ctl.func) {
+	case DRM_INST_HANDLER:
+		if ((retcode = i810_irq_install(dev, ctl.irq)))
+			return retcode;
+		break;
+	case DRM_UNINST_HANDLER:
+		if ((retcode = i810_irq_uninstall(dev)))
+			return retcode;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline void i810_dma_emit_flush(drm_device_t *dev)
+{
+   	drm_i810_private_t *dev_priv = dev->dev_private;
+   	RING_LOCALS;
+
+   	i810_kernel_lost_context(dev);
+
+   	BEGIN_LP_RING(2);
+      	OUT_RING( CMD_REPORT_HEAD );
+      	OUT_RING( GFX_OP_USER_INTERRUPT );
+      	ADVANCE_LP_RING();
+
+/*  	i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */
+/*     	atomic_set(&dev_priv->flush_done, 1); */
+/*     	wake_up_interruptible(&dev_priv->flush_queue); */
+}
+
+static inline void i810_dma_quiescent_emit(drm_device_t *dev)
+{
+      	drm_i810_private_t *dev_priv = dev->dev_private;
+   	RING_LOCALS;
+
+  	i810_kernel_lost_context(dev);
+
+   	BEGIN_LP_RING(4);
+   	OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
+   	OUT_RING( CMD_REPORT_HEAD );
+      	OUT_RING( 0 );
+      	OUT_RING( GFX_OP_USER_INTERRUPT );
+   	ADVANCE_LP_RING();
+
+/*  	i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */
+/*     	atomic_set(&dev_priv->flush_done, 1); */
+/*     	wake_up_interruptible(&dev_priv->flush_queue); */
+}
+
+static void i810_dma_quiescent(drm_device_t *dev)
+{
+      	DECLARE_WAITQUEUE(entry, current);
+  	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+	unsigned long end;      
+
+   	if(dev_priv == NULL) {
+	   	return;
+	}
+      	atomic_set(&dev_priv->flush_done, 0);
+   	add_wait_queue(&dev_priv->flush_queue, &entry);
+   	end = jiffies + (HZ*3);
+   
+   	for (;;) {
+		current->state = TASK_INTERRUPTIBLE;
+	      	i810_dma_quiescent_emit(dev);
+	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
+		if((signed)(end - jiffies) <= 0) {
+		   	DRM_ERROR("lockup\n");
+		   	break;
+		}	   
+	      	schedule_timeout(HZ*3);
+	      	if (signal_pending(current)) {
+		   	break;
+		}
+	}
+   
+   	current->state = TASK_RUNNING;
+   	remove_wait_queue(&dev_priv->flush_queue, &entry);
+   
+   	return;
+}
+
+static int i810_flush_queue(drm_device_t *dev)
+{
+   	DECLARE_WAITQUEUE(entry, current);
+  	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	unsigned long end;
+   	int i, ret = 0;      
+
+   	if(dev_priv == NULL) {
+	   	return 0;
+	}
+      	atomic_set(&dev_priv->flush_done, 0);
+   	add_wait_queue(&dev_priv->flush_queue, &entry);
+   	end = jiffies + (HZ*3);
+   	for (;;) {
+		current->state = TASK_INTERRUPTIBLE;
+	      	i810_dma_emit_flush(dev);
+	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
+		if((signed)(end - jiffies) <= 0) {
+		   	DRM_ERROR("lockup\n");
+		   	break;
+		}	   
+	      	schedule_timeout(HZ*3);
+	      	if (signal_pending(current)) {
+		   	ret = -EINTR; /* Can't restart */
+		   	break;
+		}
+	}
+   
+   	current->state = TASK_RUNNING;
+   	remove_wait_queue(&dev_priv->flush_queue, &entry);
+
+
+   	for (i = 0; i < dma->buf_count; i++) {
+	   	drm_buf_t *buf = dma->buflist[ i ];
+	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+	   
+		int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, 
+				   I810_BUF_FREE);
+
+		if (used == I810_BUF_HARDWARE)
+			DRM_DEBUG("reclaimed from HARDWARE\n");
+		if (used == I810_BUF_CLIENT)
+			DRM_DEBUG("still on client HARDWARE\n");
+	}
+
+   	return ret;
+}
+
+/* Must be called with the lock held */
+void i810_reclaim_buffers(drm_device_t *dev, pid_t pid)
+{
+	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+
+	if (!dma) return;
+      	if (!dev->dev_private) return;
+	if (!dma->buflist) return;
+
+        i810_flush_queue(dev);
+
+	for (i = 0; i < dma->buf_count; i++) {
+	   	drm_buf_t *buf = dma->buflist[ i ];
+	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
+	   
+		if (buf->pid == pid && buf_priv) {
+			int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, 
+					   I810_BUF_FREE);
+
+			if (used == I810_BUF_CLIENT)
+				DRM_DEBUG("reclaimed from client\n");
+		   	if(buf_priv->currently_mapped == I810_BUF_MAPPED)
+		     		buf_priv->currently_mapped = I810_BUF_UNMAPPED;
+		}
+	}
+}
+
+int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+
+	DECLARE_WAITQUEUE(entry, current);
+	int		  ret	= 0;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+   
+   	DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+		  lock.context, current->pid, dev->lock.hw_lock->lock,
+		  lock.flags);
+
+	if (lock.context < 0) {
+		return -EINVAL;
+	}
+	/* Only one queue:
+	 */
+
+	if (!ret) {
+		add_wait_queue(&dev->lock.lock_queue, &entry);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!dev->lock.hw_lock) {
+				/* Device has been unregistered */
+				ret = -EINTR;
+				break;
+			}
+			if (drm_lock_take(&dev->lock.hw_lock->lock,
+					  lock.context)) {
+				dev->lock.pid	    = current->pid;
+				dev->lock.lock_time = jiffies;
+				atomic_inc(&dev->total_locks);
+				break;	/* Got lock */
+			}
+			
+				/* Contention */
+			atomic_inc(&dev->total_sleeps);
+		   	DRM_DEBUG("Calling lock schedule\n");
+			schedule();
+			if (signal_pending(current)) {
+				ret = -ERESTARTSYS;
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&dev->lock.lock_queue, &entry);
+	}
+	
+	if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+
+		if (lock.flags & _DRM_LOCK_QUIESCENT) {
+		   DRM_DEBUG("_DRM_LOCK_QUIESCENT\n");
+		   DRM_DEBUG("fred\n");
+		   i810_dma_quiescent(dev);
+		}
+	}
+	DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+	return ret;
+}
+
+int i810_flush_ioctl(struct inode *inode, struct file *filp, 
+		     unsigned int cmd, unsigned long arg)
+{
+   	drm_file_t	  *priv	  = filp->private_data;
+   	drm_device_t	  *dev	  = priv->dev;
+   
+   	DRM_DEBUG("i810_flush_ioctl\n");
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_flush_ioctl called without lock held\n");
+		return -EINVAL;
+	}
+
+   	i810_flush_queue(dev);
+   	return 0;
+}
+
+
+int i810_dma_vertex(struct inode *inode, struct file *filp,
+	       unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
+   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 
+     					dev_priv->sarea_priv; 
+	drm_i810_vertex_t vertex;
+
+	if (copy_from_user(&vertex, (drm_i810_vertex_t *)arg, sizeof(vertex)))
+		return -EFAULT;
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_dma_vertex called without lock held\n");
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
+		  vertex.idx, vertex.used, vertex.discard);
+
+	if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
+
+	i810_dma_dispatch_vertex( dev, 
+				  dma->buflist[ vertex.idx ], 
+				  vertex.discard, vertex.used );
+
+   	atomic_add(vertex.used, &dma->total_bytes);
+	atomic_inc(&dma->total_dmas);
+	sarea_priv->last_enqueue = dev_priv->counter-1;
+   	sarea_priv->last_dispatch = (int) hw_status[5];
+   
+	return 0;
+}
+
+
+
+int i810_clear_bufs(struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_i810_clear_t clear;
+
+   	if (copy_from_user(&clear, (drm_i810_clear_t *)arg, sizeof(clear)))
+		return -EFAULT;
+   
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_clear_bufs called without lock held\n");
+		return -EINVAL;
+	}
+
+	i810_dma_dispatch_clear( dev, clear.flags, 
+				 clear.clear_color, 
+				 clear.clear_depth );
+   	return 0;
+}
+
+int i810_swap_bufs(struct inode *inode, struct file *filp,
+		  unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+   
+	DRM_DEBUG("i810_swap_bufs\n");
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_swap_buf called without lock held\n");
+		return -EINVAL;
+	}
+
+	i810_dma_dispatch_swap( dev );
+   	return 0;
+}
+
+int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+   	drm_file_t	  *priv	    = filp->private_data;
+	drm_device_t	  *dev	    = priv->dev;
+   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
+   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 
+     					dev_priv->sarea_priv; 
+
+      	sarea_priv->last_dispatch = (int) hw_status[5];
+	return 0;
+}
+
+int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	  *priv	    = filp->private_data;
+	drm_device_t	  *dev	    = priv->dev;
+	int		  retcode   = 0;
+	drm_i810_dma_t	  d;
+   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
+   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 
+     					dev_priv->sarea_priv; 
+
+	DRM_DEBUG("getbuf\n");
+   	if (copy_from_user(&d, (drm_i810_dma_t *)arg, sizeof(d)))
+		return -EFAULT;
+   
+	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_dma called without lock held\n");
+		return -EINVAL;
+	}
+	
+	d.granted = 0;
+
+	retcode = i810_dma_get_buffer(dev, &d, filp);
+
+	DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
+		  current->pid, retcode, d.granted);
+
+	if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d)))
+		return -EFAULT;
+   	sarea_priv->last_dispatch = (int) hw_status[5];
+
+	return retcode;
+}
+
+int i810_copybuf(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	  *priv	    = filp->private_data;
+	drm_device_t	  *dev	    = priv->dev;
+	drm_i810_copy_t	  d;
+   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
+   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
+   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 
+     					dev_priv->sarea_priv; 
+	drm_buf_t *buf;
+	drm_i810_buf_priv_t *buf_priv;
+	drm_device_dma_t *dma = dev->dma;
+
+	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i810_dma called without lock held\n");
+		return -EINVAL;
+	}
+   
+   	if (copy_from_user(&d, (drm_i810_copy_t *)arg, sizeof(d)))
+		return -EFAULT;
+
+	if(d.idx < 0 || d.idx > dma->buf_count) return -EINVAL;
+	buf = dma->buflist[ d.idx ];
+   	buf_priv = buf->dev_private;
+	if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EPERM;
+
+	/* Stopping end users copying their data to the entire kernel
+	   is good.. */
+	if (d.used < 0 || d.used > buf->total)
+		return -EINVAL;
+		
+   	if (copy_from_user(buf_priv->virtual, d.address, d.used))
+		return -EFAULT;
+
+   	sarea_priv->last_dispatch = (int) hw_status[5];
+
+	return 0;
+}
+
+int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	if(VM_DONTCOPY == 0) return 1;
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_drm.h lia64-2.4/drivers/char/drm-4.0/i810_drm.h
--- linux-2.4.16/drivers/char/drm-4.0/i810_drm.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_drm.h	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,194 @@
+#ifndef _I810_DRM_H_
+#define _I810_DRM_H_
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ */
+
+#ifndef _I810_DEFINES_
+#define _I810_DEFINES_
+
+#define I810_DMA_BUF_ORDER		12
+#define I810_DMA_BUF_SZ 		(1<<I810_DMA_BUF_ORDER)
+#define I810_DMA_BUF_NR 		256
+#define I810_NR_SAREA_CLIPRECTS 	8
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define I810_NR_TEX_REGIONS 64
+#define I810_LOG_MIN_TEX_REGION_SIZE 16
+#endif
+
+#define I810_UPLOAD_TEX0IMAGE  0x1 /* handled clientside */
+#define I810_UPLOAD_TEX1IMAGE  0x2 /* handled clientside */
+#define I810_UPLOAD_CTX        0x4
+#define I810_UPLOAD_BUFFERS    0x8
+#define I810_UPLOAD_TEX0       0x10
+#define I810_UPLOAD_TEX1       0x20
+#define I810_UPLOAD_CLIPRECTS  0x40
+
+
+/* Indices into buf.Setup where various bits of state are mirrored per
+ * context and per buffer.  These can be fired at the card as a unit,
+ * or in a piecewise fashion as required.
+ */
+
+/* Destbuffer state 
+ *    - backbuffer linear offset and pitch -- invarient in the current dri
+ *    - zbuffer linear offset and pitch -- also invarient
+ *    - drawing origin in back and depth buffers.
+ *
+ * Keep the depth/back buffer state here to acommodate private buffers
+ * in the future.
+ */
+#define I810_DESTREG_DI0  0	/* CMD_OP_DESTBUFFER_INFO (2 dwords) */
+#define I810_DESTREG_DI1  1
+#define I810_DESTREG_DV0  2	/* GFX_OP_DESTBUFFER_VARS (2 dwords) */
+#define I810_DESTREG_DV1  3
+#define I810_DESTREG_DR0  4	/* GFX_OP_DRAWRECT_INFO (4 dwords) */
+#define I810_DESTREG_DR1  5
+#define I810_DESTREG_DR2  6
+#define I810_DESTREG_DR3  7
+#define I810_DESTREG_DR4  8
+#define I810_DEST_SETUP_SIZE 10
+
+/* Context state
+ */
+#define I810_CTXREG_CF0   0	/* GFX_OP_COLOR_FACTOR */
+#define I810_CTXREG_CF1   1	
+#define I810_CTXREG_ST0   2     /* GFX_OP_STIPPLE */
+#define I810_CTXREG_ST1   3
+#define I810_CTXREG_VF    4	/* GFX_OP_VERTEX_FMT */
+#define I810_CTXREG_MT    5	/* GFX_OP_MAP_TEXELS */
+#define I810_CTXREG_MC0   6	/* GFX_OP_MAP_COLOR_STAGES - stage 0 */
+#define I810_CTXREG_MC1   7     /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
+#define I810_CTXREG_MC2   8	/* GFX_OP_MAP_COLOR_STAGES - stage 2 */
+#define I810_CTXREG_MA0   9	/* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
+#define I810_CTXREG_MA1   10	/* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
+#define I810_CTXREG_MA2   11	/* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
+#define I810_CTXREG_SDM   12	/* GFX_OP_SRC_DEST_MONO */
+#define I810_CTXREG_FOG   13	/* GFX_OP_FOG_COLOR */
+#define I810_CTXREG_B1    14	/* GFX_OP_BOOL_1 */
+#define I810_CTXREG_B2    15	/* GFX_OP_BOOL_2 */
+#define I810_CTXREG_LCS   16	/* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
+#define I810_CTXREG_PV    17	/* GFX_OP_PV_RULE -- Invarient! */
+#define I810_CTXREG_ZA    18	/* GFX_OP_ZBIAS_ALPHAFUNC */
+#define I810_CTXREG_AA    19	/* GFX_OP_ANTIALIAS */
+#define I810_CTX_SETUP_SIZE 20 
+
+/* Texture state (per tex unit)
+ */
+#define I810_TEXREG_MI0  0	/* GFX_OP_MAP_INFO (4 dwords) */
+#define I810_TEXREG_MI1  1	
+#define I810_TEXREG_MI2  2	
+#define I810_TEXREG_MI3  3	
+#define I810_TEXREG_MF   4	/* GFX_OP_MAP_FILTER */
+#define I810_TEXREG_MLC  5	/* GFX_OP_MAP_LOD_CTL */
+#define I810_TEXREG_MLL  6	/* GFX_OP_MAP_LOD_LIMITS */
+#define I810_TEXREG_MCS  7	/* GFX_OP_MAP_COORD_SETS ??? */
+#define I810_TEX_SETUP_SIZE 8
+
+#define I810_FRONT   0x1
+#define I810_BACK    0x2
+#define I810_DEPTH   0x4
+
+
+typedef struct _drm_i810_init {
+	enum {
+		I810_INIT_DMA = 0x01,
+		I810_CLEANUP_DMA = 0x02
+	} func;
+	int ring_map_idx;
+	int buffer_map_idx;
+	int sarea_priv_offset;
+	unsigned int ring_start;
+	unsigned int ring_end;
+	unsigned int ring_size;
+	unsigned int front_offset;
+	unsigned int back_offset;
+	unsigned int depth_offset;
+	unsigned int w;
+	unsigned int h;
+	unsigned int pitch;
+	unsigned int pitch_bits; 
+} drm_i810_init_t;
+
+/* Warning: If you change the SAREA structure you must change the Xserver
+ * structure as well */
+
+typedef struct _drm_i810_tex_region {
+	unsigned char next, prev; /* indices to form a circular LRU  */
+	unsigned char in_use;	/* owned by a client, or free? */
+	int age;		/* tracked by clients to update local LRU's */
+} drm_i810_tex_region_t;
+
+typedef struct _drm_i810_sarea {
+   	unsigned int ContextState[I810_CTX_SETUP_SIZE];
+   	unsigned int BufferState[I810_DEST_SETUP_SIZE];
+   	unsigned int TexState[2][I810_TEX_SETUP_SIZE];
+   	unsigned int dirty;
+
+	unsigned int nbox;
+	drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
+
+	/* Maintain an LRU of contiguous regions of texture space.  If
+	 * you think you own a region of texture memory, and it has an
+	 * age different to the one you set, then you are mistaken and
+	 * it has been stolen by another client.  If global texAge
+	 * hasn't changed, there is no need to walk the list.
+	 *
+	 * These regions can be used as a proxy for the fine-grained
+	 * texture information of other clients - by maintaining them
+	 * in the same lru which is used to age their own textures,
+	 * clients have an approximate lru for the whole of global
+	 * texture space, and can make informed decisions as to which
+	 * areas to kick out.  There is no need to choose whether to
+	 * kick out your own texture or someone else's - simply eject
+	 * them all in LRU order.  
+	 */
+   
+	drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; 
+				/* Last elt is sentinal */
+        int texAge;		/* last time texture was uploaded */
+        int last_enqueue;	/* last time a buffer was enqueued */
+	int last_dispatch;	/* age of the most recently dispatched buffer */
+	int last_quiescent;     /*  */
+	int ctxOwner;		/* last context to upload state */
+
+	int vertex_prim;
+
+} drm_i810_sarea_t;
+
+typedef struct _drm_i810_clear {
+	int clear_color;
+	int clear_depth;
+	int flags;
+} drm_i810_clear_t;
+
+
+
+/* These may be placeholders if we have more cliprects than
+ * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
+ * false, indicating that the buffer will be dispatched again with a
+ * new set of cliprects.
+ */
+typedef struct _drm_i810_vertex {
+   	int idx;		/* buffer index */
+	int used;		/* nr bytes in use */
+	int discard;		/* client is finished with the buffer? */
+} drm_i810_vertex_t;
+
+typedef struct _drm_i810_copy_t {
+   	int idx;		/* buffer index */
+	int used;		/* nr bytes in use */
+	void *address;		/* Address to copy from */
+} drm_i810_copy_t;
+
+typedef struct drm_i810_dma {
+	void *virtual;
+	int request_idx;
+	int request_size;
+	int granted;
+} drm_i810_dma_t;
+
+#endif /* _I810_DRM_H_ */
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_drv.c lia64-2.4/drivers/char/drm-4.0/i810_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/i810_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,648 @@
+/* i810_drv.c -- I810 driver -*- linux-c -*-
+ * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "i810_drv.h"
+
+#define I810_NAME	 "i810"
+#define I810_DESC	 "Intel I810"
+#define I810_DATE	 "20000928"
+#define I810_MAJOR	 1
+#define I810_MINOR	 1
+#define I810_PATCHLEVEL	 0
+
+static drm_device_t	      i810_device;
+drm_ctx_t		      i810_res_ctx;
+
+static struct file_operations i810_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 i810_open,
+	flush:	 drm_flush,
+	release: i810_release,
+	ioctl:	 i810_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+      	poll:	 drm_poll,
+};
+
+static struct miscdevice      i810_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  I810_NAME,
+	fops:  &i810_fops,
+};
+
+static drm_ioctl_desc_t	      i810_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]     = { i810_version,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)]  = { drm_getunique,  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]   = { drm_getmagic,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]   = { drm_irq_busid,  0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)]  = { drm_setunique,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	      = { drm_block,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]     = { drm_unblock,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]     = { i810_control,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)]  = { drm_authmagic,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]     = { drm_addmap,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]    = { i810_addbufs,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]   = { i810_markbufs,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]   = { i810_infobufs,  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]   = { i810_freebufs,  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]     = { i810_addctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]      = { i810_rmctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]     = { i810_modctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]     = { i810_getctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)]  = { i810_switchctx,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]     = { i810_newctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]     = { i810_resctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]    = { drm_adddraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]     = { drm_rmdraw,	  1, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	      = { i810_lock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]      = { i810_unlock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]      = { drm_finish,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]  = { drm_agp_enable,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]    = { drm_agp_info,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]   = { drm_agp_alloc,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]    = { drm_agp_free,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]    = { drm_agp_bind,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]  = { drm_agp_unbind,  1, 1 },
+
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)]   = { i810_dma_init,   1, 1 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)]  = { i810_clear_bufs, 1, 0 },
+      	[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)]  = { i810_flush_ioctl,1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage,     1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf,     1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)]   = { i810_swap_bufs,  1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)]   = { i810_copybuf,    1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy,     1, 0 },
+};
+
+#define I810_IOCTL_COUNT DRM_ARRAY_SIZE(i810_ioctls)
+
+#ifdef MODULE
+static char		      *i810 = NULL;
+#endif
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("Intel I810");
+MODULE_PARM(i810, "s");
+
+#ifndef MODULE
+/* i810_options is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+
+static int __init i810_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("i810=", i810_options);
+#endif
+
+static int i810_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	drm_dma_setup(dev);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+#if DRM_DMA_HISTO
+	memset(&dev->histo, 0, sizeof(dev->histo));
+#endif
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int i810_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	if (dev->irq) i810_irq_uninstall(dev);
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+   				/* Clear AGP information */
+	if (dev->agp) {
+		drm_agp_mem_t *entry;
+		drm_agp_mem_t *nexte;
+
+				/* Remove AGP resources, but leave dev->agp
+                                   intact until r128_cleanup is called. */
+		for (entry = dev->agp->memory; entry; entry = nexte) {
+			nexte = entry->next;
+			if (entry->bound) drm_unbind_agp(entry->memory);
+			drm_free_agp(entry->memory, entry->pages);
+			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		}
+		dev->agp->memory = NULL;
+
+		if (dev->agp->acquired) _drm_agp_release();
+
+		dev->agp->acquired = 0;
+		dev->agp->enabled  = 0;
+	}
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	if (dev->queuelist) {
+		for (i = 0; i < dev->queue_count; i++) {
+			drm_waitlist_destroy(&dev->queuelist[i]->waitlist);
+			if (dev->queuelist[i]) {
+				drm_free(dev->queuelist[i],
+					 sizeof(*dev->queuelist[0]),
+					 DRM_MEM_QUEUES);
+				dev->queuelist[i] = NULL;
+			}
+		}
+		drm_free(dev->queuelist,
+			 dev->queue_slots * sizeof(*dev->queuelist),
+			 DRM_MEM_QUEUES);
+		dev->queuelist	 = NULL;
+	}
+
+	drm_dma_takedown(dev);
+
+	dev->queue_count     = 0;
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+/* i810_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init i810_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &i810_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(i810);
+#endif
+	DRM_DEBUG("doing misc_register\n");
+	if ((retcode = misc_register(&i810_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", I810_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, i810_misc.minor);
+	dev->name   = I810_NAME;
+
+   	DRM_DEBUG("doing mem init\n");
+	drm_mem_init();
+	DRM_DEBUG("doing proc init\n");
+	drm_proc_init(dev);
+	DRM_DEBUG("doing agp init\n");
+	dev->agp    = drm_agp_init();
+   	if(dev->agp == NULL) {
+	   	DRM_INFO("The i810 drm module requires the agpgart module"
+			 " to function correctly\nPlease load the agpgart"
+			 " module before you load the i810 module\n");
+	   	drm_proc_cleanup();
+	   	misc_deregister(&i810_misc);
+	   	i810_takedown(dev);
+	   	return -ENOMEM;
+	}
+	DRM_DEBUG("doing ctxbitmap init\n");
+	if((retcode = drm_ctxbitmap_init(dev))) {
+		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+		drm_proc_cleanup();
+		misc_deregister(&i810_misc);
+		i810_takedown(dev);
+		return retcode;
+	}
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+		 I810_NAME,
+		 I810_MAJOR,
+		 I810_MINOR,
+		 I810_PATCHLEVEL,
+		 I810_DATE,
+		 i810_misc.minor);
+
+	return 0;
+}
+
+/* i810_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit i810_cleanup(void)
+{
+	drm_device_t	      *dev = &i810_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&i810_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	drm_ctxbitmap_cleanup(dev);
+	i810_takedown(dev);
+	if (dev->agp) {
+		drm_agp_uninit();
+		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
+		dev->agp = NULL;
+	}
+}
+
+module_init(i810_init);
+module_exit(i810_cleanup);
+
+
+int i810_version(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)				     \
+	len = strlen(value);				     \
+	if (len > name##_len) len = name##_len;		     \
+	name##_len = strlen(value);			     \
+	if (len && name) {				     \
+		if (copy_to_user(name, value, len))          \
+			return -EFAULT;			     \
+	}
+
+	version.version_major	   = I810_MAJOR;
+	version.version_minor	   = I810_MINOR;
+	version.version_patchlevel = I810_PATCHLEVEL;
+
+	DRM_COPY(version.name, I810_NAME);
+	DRM_COPY(version.date, I810_DATE);
+	DRM_COPY(version.desc, I810_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int i810_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &i810_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return i810_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+	return retcode;
+}
+
+int i810_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev    = priv->dev;
+	DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n",
+		  current->pid, dev->device, dev->open_count);
+
+	if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
+	    && dev->lock.pid == current->pid) {
+	      	i810_reclaim_buffers(dev, priv->pid);
+		DRM_ERROR("Process %d dead, freeing lock for context %d\n",
+			  current->pid,
+			  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+		drm_lock_free(dev,
+			      &dev->lock.hw_lock->lock,
+			      _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+
+				/* FIXME: may require heavy-handed reset of
+                                   hardware at this point, possibly
+                                   processed via a callback to the X
+                                   server. */
+	} else if (dev->lock.hw_lock) {
+	   	/* The lock is required to reclaim buffers */
+	   	DECLARE_WAITQUEUE(entry, current);
+	   	add_wait_queue(&dev->lock.lock_queue, &entry);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!dev->lock.hw_lock) {
+				/* Device has been unregistered */
+				retcode = -EINTR;
+				break;
+			}
+			if (drm_lock_take(&dev->lock.hw_lock->lock,
+					  DRM_KERNEL_CONTEXT)) {
+				dev->lock.pid	    = priv->pid;
+				dev->lock.lock_time = jiffies;
+				atomic_inc(&dev->total_locks);
+				break;	/* Got lock */
+			}
+				/* Contention */
+			atomic_inc(&dev->total_sleeps);
+			schedule();
+			if (signal_pending(current)) {
+				retcode = -ERESTARTSYS;
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&dev->lock.lock_queue, &entry);
+	   	if(!retcode) {
+		   	i810_reclaim_buffers(dev, priv->pid);
+		   	drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				      DRM_KERNEL_CONTEXT);
+		}
+	}
+	drm_fasync(-1, filp, 0);
+
+	down(&dev->struct_sem);
+	if (priv->prev) priv->prev->next = priv->next;
+	else		dev->file_first	 = priv->next;
+	if (priv->next) priv->next->prev = priv->prev;
+	else		dev->file_last	 = priv->prev;
+	up(&dev->struct_sem);
+
+	drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
+#if LINUX_VERSION_CODE < 0x020333
+	MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+   	atomic_inc(&dev->total_close);
+   	spin_lock(&dev->count_lock);
+   	if (!--dev->open_count) {
+	   	if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+		   	DRM_ERROR("Device busy: %d %d\n",
+				  atomic_read(&dev->ioctl_count),
+				  dev->blocked);
+		   	spin_unlock(&dev->count_lock);
+			unlock_kernel();
+		   	return -EBUSY;
+		}
+	   	spin_unlock(&dev->count_lock);
+		unlock_kernel();
+		return i810_takedown(dev);
+	}
+	spin_unlock(&dev->count_lock);
+	unlock_kernel();
+	return retcode;
+}
+
+/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+
+int i810_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= I810_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &i810_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+int i810_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+   	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+	if (!dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+#if DRM_DMA_HISTOGRAM
+	atomic_inc(&dev->histo.lhld[drm_histogram_slot(get_cycles()
+						       - dev->lck_start)]);
+#endif
+
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/i810_drv.h lia64-2.4/drivers/char/drm-4.0/i810_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/i810_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/i810_drv.h	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,225 @@
+/* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ * 	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#ifndef _I810_DRV_H_
+#define _I810_DRV_H_
+
+typedef struct drm_i810_buf_priv {
+   	u32 *in_use;
+   	int my_use_idx;
+	int currently_mapped;
+	void *virtual;
+	void *kernel_virtual;
+	int map_count;
+   	struct vm_area_struct *vma;
+} drm_i810_buf_priv_t;
+
+typedef struct _drm_i810_ring_buffer{
+	int tail_mask;
+	unsigned long Start;
+	unsigned long End;
+	unsigned long Size;
+	u8 *virtual_start;
+	int head;
+	int tail;
+	int space;
+} drm_i810_ring_buffer_t;
+
+typedef struct drm_i810_private {
+   	int ring_map_idx;
+   	int buffer_map_idx;
+
+   	drm_i810_ring_buffer_t ring;
+	drm_i810_sarea_t *sarea_priv;
+
+      	unsigned long hw_status_page;
+   	unsigned long counter;
+
+   	atomic_t flush_done;
+   	wait_queue_head_t flush_queue;	/* Processes waiting until flush    */
+	drm_buf_t *mmap_buffer;
+
+	
+	u32 front_di1, back_di1, zi1;
+	
+	int back_offset;
+	int depth_offset;
+	int w, h;
+	int pitch;
+} drm_i810_private_t;
+
+				/* i810_drv.c */
+extern int  i810_version(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  i810_open(struct inode *inode, struct file *filp);
+extern int  i810_release(struct inode *inode, struct file *filp);
+extern int  i810_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  i810_unlock(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+
+				/* i810_dma.c */
+extern int  i810_dma_schedule(drm_device_t *dev, int locked);
+extern int  i810_getbuf(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  i810_irq_install(drm_device_t *dev, int irq);
+extern int  i810_irq_uninstall(drm_device_t *dev);
+extern int  i810_control(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  i810_lock(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_dma_init(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  i810_flush_ioctl(struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg);
+extern void i810_reclaim_buffers(drm_device_t *dev, pid_t pid);
+extern int  i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
+			unsigned long arg);
+extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
+extern int i810_copybuf(struct inode *inode, struct file *filp, 
+			unsigned int cmd, unsigned long arg);
+extern int i810_docopy(struct inode *inode, struct file *filp, 
+		       unsigned int cmd, unsigned long arg);
+
+				/* i810_bufs.c */
+extern int  i810_addbufs(struct inode *inode, struct file *filp, 
+			unsigned int cmd, unsigned long arg);
+extern int  i810_infobufs(struct inode *inode, struct file *filp, 
+			 unsigned int cmd, unsigned long arg);
+extern int  i810_markbufs(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+extern int  i810_freebufs(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+extern int  i810_addmap(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+
+				/* i810_context.c */
+extern int  i810_resctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_addctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_modctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_getctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_switchctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  i810_newctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  i810_rmctx(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+
+extern int  i810_context_switch(drm_device_t *dev, int old, int new);
+extern int  i810_context_switch_complete(drm_device_t *dev, int new);
+
+#define I810_VERBOSE 0
+
+
+int i810_dma_vertex(struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg);
+
+int i810_swap_bufs(struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg);
+
+int i810_clear_bufs(struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg);
+
+#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
+#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
+#define CMD_REPORT_HEAD			(7<<23)
+#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
+#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
+
+#define INST_PARSER_CLIENT   0x00000000
+#define INST_OP_FLUSH        0x02000000
+#define INST_FLUSH_MAP_CACHE 0x00000001
+
+
+#define BB1_START_ADDR_MASK   (~0x7)
+#define BB1_PROTECTED         (1<<0)
+#define BB1_UNPROTECTED       (0<<0)
+#define BB2_END_ADDR_MASK     (~0x7)
+
+#define I810REG_HWSTAM		0x02098
+#define I810REG_INT_IDENTITY_R	0x020a4
+#define I810REG_INT_MASK_R 	0x020a8
+#define I810REG_INT_ENABLE_R	0x020a0
+
+#define LP_RING     		0x2030
+#define HP_RING     		0x2040
+#define RING_TAIL      		0x00
+#define TAIL_ADDR		0x000FFFF8
+#define RING_HEAD      		0x04
+#define HEAD_WRAP_COUNT     	0xFFE00000
+#define HEAD_WRAP_ONE       	0x00200000
+#define HEAD_ADDR           	0x001FFFFC
+#define RING_START     		0x08
+#define START_ADDR          	0x00FFFFF8
+#define RING_LEN       		0x0C
+#define RING_NR_PAGES       	0x000FF000 
+#define RING_REPORT_MASK    	0x00000006
+#define RING_REPORT_64K     	0x00000002
+#define RING_REPORT_128K    	0x00000004
+#define RING_NO_REPORT      	0x00000000
+#define RING_VALID_MASK     	0x00000001
+#define RING_VALID          	0x00000001
+#define RING_INVALID        	0x00000000
+
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define SC_UPDATE_SCISSOR       (0x1<<1)
+#define SC_ENABLE_MASK          (0x1<<0)
+#define SC_ENABLE               (0x1<<0)
+
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define SCI_YMIN_MASK      (0xffff<<16)
+#define SCI_XMIN_MASK      (0xffff<<0)
+#define SCI_YMAX_MASK      (0xffff<<16)
+#define SCI_XMAX_MASK      (0xffff<<0)
+
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x2)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+#define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))
+
+#define CMD_OP_Z_BUFFER_INFO     ((0x0<<29)|(0x16<<23))
+#define CMD_OP_DESTBUFFER_INFO   ((0x0<<29)|(0x15<<23))
+
+#define BR00_BITBLT_CLIENT   0x40000000
+#define BR00_OP_COLOR_BLT    0x10000000
+#define BR00_OP_SRC_COPY_BLT 0x10C00000
+#define BR13_SOLID_PATTERN   0x80000000
+
+
+
+#endif
+
diff -urN linux-2.4.16/drivers/char/drm-4.0/init.c lia64-2.4/drivers/char/drm-4.0/init.c
--- linux-2.4.16/drivers/char/drm-4.0/init.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/init.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,113 @@
+/* init.c -- Setup/Cleanup for DRM -*- linux-c -*-
+ * Created: Mon Jan  4 08:58:31 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+int			      drm_flags		= 0;
+
+/* drm_parse_option parses a single option.  See description for
+   drm_parse_options for details. */
+
+static void drm_parse_option(char *s)
+{
+	char *c, *r;
+	
+	DRM_DEBUG("\"%s\"\n", s);
+	if (!s || !*s) return;
+	for (c = s; *c && *c != ':'; c++); /* find : or \0 */
+	if (*c) r = c + 1; else r = NULL;  /* remember remainder */
+	*c = '\0';			   /* terminate */
+	if (!strcmp(s, "noctx")) {
+		drm_flags |= DRM_FLAG_NOCTX;
+		DRM_INFO("Server-mediated context switching OFF\n");
+		return;
+	}
+	if (!strcmp(s, "debug")) {
+		drm_flags |= DRM_FLAG_DEBUG;
+		DRM_INFO("Debug messages ON\n");
+		return;
+	}
+	DRM_ERROR("\"%s\" is not a valid option\n", s);
+	return;
+}
+
+/* drm_parse_options parse the insmod "drm=" options, or the command-line
+ * options passed to the kernel via LILO.  The grammar of the format is as
+ * follows:
+ *
+ * drm		::= 'drm=' option_list
+ * option_list	::= option [ ';' option_list ]
+ * option	::= 'device:' major
+ *		|   'debug' 
+ *		|   'noctx'
+ * major	::= INTEGER
+ *
+ * Note that 's' contains option_list without the 'drm=' part.
+ *
+ * device=major,minor specifies the device number used for /dev/drm
+ *	  if major == 0 then the misc device is used
+ *	  if major == 0 and minor == 0 then dynamic misc allocation is used
+ * debug=on specifies that debugging messages will be printk'd
+ * debug=trace specifies that each function call will be logged via printk
+ * debug=off turns off all debugging options
+ *
+ */
+
+void drm_parse_options(char *s)
+{
+	char *h, *t, *n;
+	
+	DRM_DEBUG("\"%s\"\n", s ?: "");
+	if (!s || !*s) return;
+
+	for (h = t = n = s; h && *h; h = n) {
+		for (; *t && *t != ';'; t++);	       /* find ; or \0 */
+		if (*t) n = t + 1; else n = NULL;      /* remember next */
+		*t = '\0';			       /* terminate */
+		drm_parse_option(h);		       /* parse */
+	}
+}
+
+/* drm_cpu_valid returns non-zero if the DRI will run on this CPU, and 0
+ * otherwise. */
+
+int drm_cpu_valid(void)
+{
+#if defined(__i386__)
+	if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */
+#endif
+#if defined(__sparc__) && !defined(__sparc_v9__)
+	if (1)
+		return 0; /* No cmpxchg before v9 sparc. */
+#endif
+	return 1;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/ioctl.c lia64-2.4/drivers/char/drm-4.0/ioctl.c
--- linux-2.4.16/drivers/char/drm-4.0/ioctl.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/ioctl.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,99 @@
+/* ioctl.c -- IOCTL processing for DRM -*- linux-c -*-
+ * Created: Fri Jan  8 09:01:26 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+int drm_irq_busid(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_irq_busid_t p;
+	struct pci_dev	*dev;
+
+	if (copy_from_user(&p, (drm_irq_busid_t *)arg, sizeof(p)))
+		return -EFAULT;
+	dev = pci_find_slot(p.busnum, PCI_DEVFN(p.devnum, p.funcnum));
+	if (dev) p.irq = dev->irq;
+	else	 p.irq = 0;
+	DRM_DEBUG("%d:%d:%d => IRQ %d\n",
+		  p.busnum, p.devnum, p.funcnum, p.irq);
+	if (copy_to_user((drm_irq_busid_t *)arg, &p, sizeof(p)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_getunique(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_unique_t	 u;
+
+	if (copy_from_user(&u, (drm_unique_t *)arg, sizeof(u)))
+		return -EFAULT;
+	if (u.unique_len >= dev->unique_len) {
+		if (copy_to_user(u.unique, dev->unique, dev->unique_len))
+			return -EFAULT;
+	}
+	u.unique_len = dev->unique_len;
+	if (copy_to_user((drm_unique_t *)arg, &u, sizeof(u)))
+		return -EFAULT;
+	return 0;
+}
+
+int drm_setunique(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_unique_t	 u;
+
+	if (dev->unique_len || dev->unique)
+		return -EBUSY;
+
+	if (copy_from_user(&u, (drm_unique_t *)arg, sizeof(u)))
+		return -EFAULT;
+
+	if (!u.unique_len || u.unique_len > 1024)
+		return -EINVAL;
+	
+	dev->unique_len = u.unique_len;
+	dev->unique	= drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER);
+	if (copy_from_user(dev->unique, u.unique, dev->unique_len))
+		return -EFAULT;
+	dev->unique[dev->unique_len] = '\0';
+
+	dev->devname = drm_alloc(strlen(dev->name) + strlen(dev->unique) + 2,
+				 DRM_MEM_DRIVER);
+	sprintf(dev->devname, "%s@%s", dev->name, dev->unique);
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/lists.c lia64-2.4/drivers/char/drm-4.0/lists.c
--- linux-2.4.16/drivers/char/drm-4.0/lists.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/lists.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,218 @@
+/* lists.c -- Buffer list handling routines -*- linux-c -*-
+ * Created: Mon Apr 19 20:54:22 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+int drm_waitlist_create(drm_waitlist_t *bl, int count)
+{
+	if (bl->count) return -EINVAL;
+	
+	bl->count      = count;
+	bl->bufs       = drm_alloc((bl->count + 2) * sizeof(*bl->bufs),
+				   DRM_MEM_BUFLISTS);
+	bl->rp	       = bl->bufs;
+	bl->wp	       = bl->bufs;
+	bl->end	       = &bl->bufs[bl->count+1];
+	bl->write_lock = SPIN_LOCK_UNLOCKED;
+	bl->read_lock  = SPIN_LOCK_UNLOCKED;
+	return 0;
+}
+
+int drm_waitlist_destroy(drm_waitlist_t *bl)
+{
+	if (bl->rp != bl->wp) return -EINVAL;
+	if (bl->bufs) drm_free(bl->bufs,
+			       (bl->count + 2) * sizeof(*bl->bufs),
+			       DRM_MEM_BUFLISTS);
+	bl->count = 0;
+	bl->bufs  = NULL;
+	bl->rp	  = NULL;
+	bl->wp	  = NULL;
+	bl->end	  = NULL;
+	return 0;
+}
+
+int drm_waitlist_put(drm_waitlist_t *bl, drm_buf_t *buf)
+{							
+	int	      left;
+	unsigned long flags;
+
+	left = DRM_LEFTCOUNT(bl);
+	if (!left) {
+		DRM_ERROR("Overflow while adding buffer %d from pid %d\n",
+			  buf->idx, buf->pid);
+		return -EINVAL;
+	}
+#if DRM_DMA_HISTOGRAM
+	buf->time_queued = get_cycles();
+#endif
+	buf->list	 = DRM_LIST_WAIT;
+	
+	spin_lock_irqsave(&bl->write_lock, flags);
+	*bl->wp = buf;
+	if (++bl->wp >= bl->end) bl->wp = bl->bufs;
+	spin_unlock_irqrestore(&bl->write_lock, flags);
+	
+	return 0;
+}
+
+drm_buf_t *drm_waitlist_get(drm_waitlist_t *bl)
+{
+	drm_buf_t     *buf;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bl->read_lock, flags);
+	buf = *bl->rp;
+	if (bl->rp == bl->wp) {
+		spin_unlock_irqrestore(&bl->read_lock, flags);
+		return NULL;
+	}				     
+	if (++bl->rp >= bl->end) bl->rp = bl->bufs;
+	spin_unlock_irqrestore(&bl->read_lock, flags);
+	
+	return buf;
+}
+
+int drm_freelist_create(drm_freelist_t *bl, int count)
+{
+	atomic_set(&bl->count, 0);
+	bl->next      = NULL;
+	init_waitqueue_head(&bl->waiting);
+	bl->low_mark  = 0;
+	bl->high_mark = 0;
+	atomic_set(&bl->wfh,   0);
+	bl->lock      = SPIN_LOCK_UNLOCKED;
+	++bl->initialized;
+	return 0;
+}
+
+int drm_freelist_destroy(drm_freelist_t *bl)
+{
+	atomic_set(&bl->count, 0);
+	bl->next = NULL;
+	return 0;
+}
+
+int drm_freelist_put(drm_device_t *dev, drm_freelist_t *bl, drm_buf_t *buf)
+{
+	drm_device_dma_t *dma  = dev->dma;
+
+	if (!dma) {
+		DRM_ERROR("No DMA support\n");
+		return 1;
+	}
+
+	if (buf->waiting || buf->pending || buf->list == DRM_LIST_FREE) {
+		DRM_ERROR("Freed buffer %d: w%d, p%d, l%d\n",
+			  buf->idx, buf->waiting, buf->pending, buf->list);
+	}
+	if (!bl) return 1;
+#if DRM_DMA_HISTOGRAM
+	buf->time_freed = get_cycles();
+	drm_histogram_compute(dev, buf);
+#endif
+	buf->list	= DRM_LIST_FREE;
+	
+	spin_lock(&bl->lock);
+	buf->next	= bl->next;
+	bl->next	= buf;
+	spin_unlock(&bl->lock);
+	
+	atomic_inc(&bl->count);
+	if (atomic_read(&bl->count) > dma->buf_count) {
+		DRM_ERROR("%d of %d buffers free after addition of %d\n",
+			  atomic_read(&bl->count), dma->buf_count, buf->idx);
+		return 1;
+	}
+				/* Check for high water mark */
+	if (atomic_read(&bl->wfh) && atomic_read(&bl->count)>=bl->high_mark) {
+		atomic_set(&bl->wfh, 0);
+		wake_up_interruptible(&bl->waiting);
+	}
+	return 0;
+}
+
+static drm_buf_t *drm_freelist_try(drm_freelist_t *bl)
+{
+	drm_buf_t	  *buf;
+
+	if (!bl) return NULL;
+	
+				/* Get buffer */
+	spin_lock(&bl->lock);
+	if (!bl->next) {
+		spin_unlock(&bl->lock);
+		return NULL;
+	}
+	buf	  = bl->next;
+	bl->next  = bl->next->next;
+	spin_unlock(&bl->lock);
+	
+	atomic_dec(&bl->count);
+	buf->next = NULL;
+	buf->list = DRM_LIST_NONE;
+	if (buf->waiting || buf->pending) {
+		DRM_ERROR("Free buffer %d: w%d, p%d, l%d\n",
+			  buf->idx, buf->waiting, buf->pending, buf->list);
+	}
+	
+	return buf;
+}
+
+drm_buf_t *drm_freelist_get(drm_freelist_t *bl, int block)
+{
+	drm_buf_t	  *buf	= NULL;
+	DECLARE_WAITQUEUE(entry, current);
+
+	if (!bl || !bl->initialized) return NULL;
+	
+				/* Check for low water mark */
+	if (atomic_read(&bl->count) <= bl->low_mark) /* Became low */
+		atomic_set(&bl->wfh, 1);
+	if (atomic_read(&bl->wfh)) {
+		if (block) {
+			add_wait_queue(&bl->waiting, &entry);
+			for (;;) {
+				current->state = TASK_INTERRUPTIBLE;
+				if (!atomic_read(&bl->wfh)
+				    && (buf = drm_freelist_try(bl))) break;
+				schedule();
+				if (signal_pending(current)) break;
+			}
+			current->state = TASK_RUNNING;
+			remove_wait_queue(&bl->waiting, &entry);
+		}
+		return buf;
+	}
+		
+	return drm_freelist_try(bl);
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/lock.c lia64-2.4/drivers/char/drm-4.0/lock.c
--- linux-2.4.16/drivers/char/drm-4.0/lock.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/lock.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,252 @@
+/* lock.c -- IOCTLs for locking -*- linux-c -*-
+ * Created: Tue Feb  2 08:37:54 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+int drm_block(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	DRM_DEBUG("\n");
+	return 0;
+}
+
+int drm_unblock(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	DRM_DEBUG("\n");
+	return 0;
+}
+
+int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
+{
+	unsigned int old, new, prev;
+
+	do {
+		old = *lock;
+		if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT;
+		else			  new = context | _DRM_LOCK_HELD;
+		prev = cmpxchg(lock, old, new);
+	} while (prev != old);
+	if (_DRM_LOCKING_CONTEXT(old) == context) {
+		if (old & _DRM_LOCK_HELD) {
+			if (context != DRM_KERNEL_CONTEXT) {
+				DRM_ERROR("%d holds heavyweight lock\n",
+					  context);
+			}
+			return 0;
+		}
+	}
+	if (new == (context | _DRM_LOCK_HELD)) {
+				/* Have lock */
+		return 1;
+	}
+	return 0;
+}
+
+/* This takes a lock forcibly and hands it to context.	Should ONLY be used
+   inside *_unlock to give lock to kernel before calling *_dma_schedule. */
+int drm_lock_transfer(drm_device_t *dev,
+		      __volatile__ unsigned int *lock, unsigned int context)
+{
+	unsigned int old, new, prev;
+
+	dev->lock.pid = 0;
+	do {
+		old  = *lock;
+		new  = context | _DRM_LOCK_HELD;
+		prev = cmpxchg(lock, old, new);
+	} while (prev != old);
+	return 1;
+}
+
+int drm_lock_free(drm_device_t *dev,
+		  __volatile__ unsigned int *lock, unsigned int context)
+{
+	unsigned int old, new, prev;
+	pid_t        pid = dev->lock.pid;
+
+	dev->lock.pid = 0;
+	do {
+		old  = *lock;
+		new  = 0;
+		prev = cmpxchg(lock, old, new);
+	} while (prev != old);
+	if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
+		DRM_ERROR("%d freed heavyweight lock held by %d (pid %d)\n",
+			  context,
+			  _DRM_LOCKING_CONTEXT(old),
+			  pid);
+		return 1;
+	}
+	wake_up_interruptible(&dev->lock.lock_queue);
+	return 0;
+}
+
+static int drm_flush_queue(drm_device_t *dev, int context)
+{
+	DECLARE_WAITQUEUE(entry, current);
+	int		  ret	= 0;
+	drm_queue_t	  *q	= dev->queuelist[context];
+	
+	DRM_DEBUG("\n");
+	
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) > 1) {
+		atomic_inc(&q->block_write);
+		add_wait_queue(&q->flush_queue, &entry);
+		atomic_inc(&q->block_count);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!DRM_BUFCOUNT(&q->waitlist)) break;
+			schedule();
+			if (signal_pending(current)) {
+				ret = -EINTR; /* Can't restart */
+				break;
+			}
+		}
+		atomic_dec(&q->block_count);
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&q->flush_queue, &entry);
+	}
+	atomic_dec(&q->use_count);
+	atomic_inc(&q->total_flushed);
+		
+				/* NOTE: block_write is still incremented!
+				   Use drm_flush_unlock_queue to decrement. */
+	return ret;
+}
+
+static int drm_flush_unblock_queue(drm_device_t *dev, int context)
+{
+	drm_queue_t	  *q	= dev->queuelist[context];
+	
+	DRM_DEBUG("\n");
+	
+	atomic_inc(&q->use_count);
+	if (atomic_read(&q->use_count) > 1) {
+		if (atomic_read(&q->block_write)) {
+			atomic_dec(&q->block_write);
+			wake_up_interruptible(&q->write_queue);
+		}
+	}
+	atomic_dec(&q->use_count);
+	return 0;
+}
+
+int drm_flush_block_and_flush(drm_device_t *dev, int context,
+			      drm_lock_flags_t flags)
+{
+	int ret = 0;
+	int i;
+	
+	DRM_DEBUG("\n");
+	
+	if (flags & _DRM_LOCK_FLUSH) {
+		ret = drm_flush_queue(dev, DRM_KERNEL_CONTEXT);
+		if (!ret) ret = drm_flush_queue(dev, context);
+	}
+	if (flags & _DRM_LOCK_FLUSH_ALL) {
+		for (i = 0; !ret && i < dev->queue_count; i++) {
+			ret = drm_flush_queue(dev, i);
+		}
+	}
+	return ret;
+}
+
+int drm_flush_unblock(drm_device_t *dev, int context, drm_lock_flags_t flags)
+{
+	int ret = 0;
+	int i;
+	
+	DRM_DEBUG("\n");
+	
+	if (flags & _DRM_LOCK_FLUSH) {
+		ret = drm_flush_unblock_queue(dev, DRM_KERNEL_CONTEXT);
+		if (!ret) ret = drm_flush_unblock_queue(dev, context);
+	}
+	if (flags & _DRM_LOCK_FLUSH_ALL) {
+		for (i = 0; !ret && i < dev->queue_count; i++) {
+			ret = drm_flush_unblock_queue(dev, i);
+		}
+	}
+		
+	return ret;
+}
+
+int drm_finish(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	int		  ret	  = 0;
+	drm_lock_t	  lock;
+
+	DRM_DEBUG("\n");
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+	ret = drm_flush_block_and_flush(dev, lock.context, lock.flags);
+	drm_flush_unblock(dev, lock.context, lock.flags);
+	return ret;
+}
+
+/* If we get here, it means that the process has called DRM_IOCTL_LOCK
+   without calling DRM_IOCTL_UNLOCK.
+   
+   If the lock is not held, then let the signal proceed as usual.
+   
+   If the lock is held, then set the contended flag and keep the signal
+   blocked.
+   
+
+   Return 1 if the signal should be delivered normally.
+   Return 0 if the signal should be blocked.  */
+
+int drm_notifier(void *priv)
+{
+	drm_sigdata_t *s = (drm_sigdata_t *)priv;
+	unsigned int  old, new, prev;
+
+
+				/* Allow signal delivery if lock isn't held */
+	if (!_DRM_LOCK_IS_HELD(s->lock->lock)
+	    || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1;
+	
+				/* Otherwise, set flag to force call to
+                                   drmUnlock */
+	do {
+		old  = s->lock->lock;
+		new  = old | _DRM_LOCK_CONT;
+		prev = cmpxchg(&s->lock->lock, old, new);
+	} while (prev != old);
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/memory.c lia64-2.4/drivers/char/drm-4.0/memory.c
--- linux-2.4.16/drivers/char/drm-4.0/memory.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/memory.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,486 @@
+/* memory.c -- Memory management wrappers for DRM -*- linux-c -*-
+ * Created: Thu Feb  4 14:00:34 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include <linux/config.h>
+#include "drmP.h"
+#include <linux/wrapper.h>
+
+typedef struct drm_mem_stats {
+	const char	  *name;
+	int		  succeed_count;
+	int		  free_count;
+	int		  fail_count;
+	unsigned long	  bytes_allocated;
+	unsigned long	  bytes_freed;
+} drm_mem_stats_t;
+
+static spinlock_t	  drm_mem_lock	    = SPIN_LOCK_UNLOCKED;
+static unsigned long	  drm_ram_available = 0; /* In pages */
+static unsigned long	  drm_ram_used	    = 0;
+static drm_mem_stats_t	  drm_mem_stats[]   = {
+	[DRM_MEM_DMA]	    = { "dmabufs"  },
+	[DRM_MEM_SAREA]	    = { "sareas"   },
+	[DRM_MEM_DRIVER]    = { "driver"   },
+	[DRM_MEM_MAGIC]	    = { "magic"	   },
+	[DRM_MEM_IOCTLS]    = { "ioctltab" },
+	[DRM_MEM_MAPS]	    = { "maplist"  },
+	[DRM_MEM_VMAS]	    = { "vmalist"  },
+	[DRM_MEM_BUFS]	    = { "buflist"  },
+	[DRM_MEM_SEGS]	    = { "seglist"  },
+	[DRM_MEM_PAGES]	    = { "pagelist" },
+	[DRM_MEM_FILES]	    = { "files"	   },
+	[DRM_MEM_QUEUES]    = { "queues"   },
+	[DRM_MEM_CMDS]	    = { "commands" },
+	[DRM_MEM_MAPPINGS]  = { "mappings" },
+	[DRM_MEM_BUFLISTS]  = { "buflists" },
+	[DRM_MEM_AGPLISTS]  = { "agplist"  },
+	[DRM_MEM_TOTALAGP]  = { "totalagp" },
+	[DRM_MEM_BOUNDAGP]  = { "boundagp" },
+	[DRM_MEM_CTXBITMAP] = { "ctxbitmap"},
+	{ NULL, 0, }		/* Last entry must be null */
+};
+
+void drm_mem_init(void)
+{
+	drm_mem_stats_t *mem;
+	struct sysinfo	si;
+	
+	for (mem = drm_mem_stats; mem->name; ++mem) {
+		mem->succeed_count   = 0;
+		mem->free_count	     = 0;
+		mem->fail_count	     = 0;
+		mem->bytes_allocated = 0;
+		mem->bytes_freed     = 0;
+	}
+	
+	si_meminfo(&si);
+#if LINUX_VERSION_CODE < 0x020317
+				/* Changed to page count in 2.3.23 */
+	drm_ram_available = si.totalram >> PAGE_SHIFT;
+#else
+	drm_ram_available = si.totalram;
+#endif
+	drm_ram_used	  = 0;
+}
+
+/* drm_mem_info is called whenever a process reads /dev/drm/mem. */
+
+static int _drm_mem_info(char *buf, char **start, off_t offset, int len,
+			 int *eof, void *data)
+{
+	drm_mem_stats_t *pt;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT("		  total counts			"
+		       " |    outstanding  \n");
+	DRM_PROC_PRINT("type	   alloc freed fail	bytes	   freed"
+		       " | allocs      bytes\n\n");
+	DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB         |\n",
+		       "system", 0, 0, 0,
+		       drm_ram_available << (PAGE_SHIFT - 10));
+	DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB         |\n",
+		       "locked", 0, 0, 0, drm_ram_used >> 10);
+	DRM_PROC_PRINT("\n");
+	for (pt = drm_mem_stats; pt->name; pt++) {
+		DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n",
+			       pt->name,
+			       pt->succeed_count,
+			       pt->free_count,
+			       pt->fail_count,
+			       pt->bytes_allocated,
+			       pt->bytes_freed,
+			       pt->succeed_count - pt->free_count,
+			       (long)pt->bytes_allocated
+			       - (long)pt->bytes_freed);
+	}
+	
+	return len;
+}
+
+int drm_mem_info(char *buf, char **start, off_t offset, int len,
+		 int *eof, void *data)
+{
+	int ret;
+	
+	spin_lock(&drm_mem_lock);
+	ret = _drm_mem_info(buf, start, offset, len, eof, data);
+	spin_unlock(&drm_mem_lock);
+	return ret;
+}
+
+void *drm_alloc(size_t size, int area)
+{
+	void *pt;
+	
+	if (!size) {
+		DRM_MEM_ERROR(area, "Allocating 0 bytes\n");
+		return NULL;
+	}
+	
+	if (!(pt = kmalloc(size, GFP_KERNEL))) {
+		spin_lock(&drm_mem_lock);
+		++drm_mem_stats[area].fail_count;
+		spin_unlock(&drm_mem_lock);
+		return NULL;
+	}
+	spin_lock(&drm_mem_lock);
+	++drm_mem_stats[area].succeed_count;
+	drm_mem_stats[area].bytes_allocated += size;
+	spin_unlock(&drm_mem_lock);
+	return pt;
+}
+
+void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
+{
+	void *pt;
+	
+	if (!(pt = drm_alloc(size, area))) return NULL;
+	if (oldpt && oldsize) {
+		memcpy(pt, oldpt, oldsize);
+		drm_free(oldpt, oldsize, area);
+	}
+	return pt;
+}
+
+char *drm_strdup(const char *s, int area)
+{
+	char *pt;
+	int	 length = s ? strlen(s) : 0;
+	
+	if (!(pt = drm_alloc(length+1, area))) return NULL;
+	strcpy(pt, s);
+	return pt;
+}
+
+void drm_strfree(const char *s, int area)
+{
+	unsigned int size;
+	
+	if (!s) return;
+	
+	size = 1 + (s ? strlen(s) : 0);
+	drm_free((void *)s, size, area);
+}
+
+void drm_free(void *pt, size_t size, int area)
+{
+	int alloc_count;
+	int free_count;
+	
+	if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n");
+	else	 kfree(pt);
+	spin_lock(&drm_mem_lock);
+	drm_mem_stats[area].bytes_freed += size;
+	free_count  = ++drm_mem_stats[area].free_count;
+	alloc_count =	drm_mem_stats[area].succeed_count;
+	spin_unlock(&drm_mem_lock);
+	if (free_count > alloc_count) {
+		DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n",
+			      free_count, alloc_count);
+	}
+}
+
+unsigned long drm_alloc_pages(int order, int area)
+{
+	unsigned long address;
+	unsigned long bytes	  = PAGE_SIZE << order;
+	unsigned long addr;
+	unsigned int  sz;
+	
+	spin_lock(&drm_mem_lock);
+	if ((drm_ram_used >> PAGE_SHIFT)
+	    > (DRM_RAM_PERCENT * drm_ram_available) / 100) {
+		spin_unlock(&drm_mem_lock);
+		return 0;
+	}
+	spin_unlock(&drm_mem_lock);
+	
+	address = __get_free_pages(GFP_KERNEL, order);
+	if (!address) {
+		spin_lock(&drm_mem_lock);
+		++drm_mem_stats[area].fail_count;
+		spin_unlock(&drm_mem_lock);
+		return 0;
+	}
+	spin_lock(&drm_mem_lock);
+	++drm_mem_stats[area].succeed_count;
+	drm_mem_stats[area].bytes_allocated += bytes;
+	drm_ram_used		            += bytes;
+	spin_unlock(&drm_mem_lock);
+	
+	
+				/* Zero outside the lock */
+	memset((void *)address, 0, bytes);
+	
+				/* Reserve */
+	for (addr = address, sz = bytes;
+	     sz > 0;
+	     addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* Argument type changed in 2.4.0-test6/pre8 */
+		mem_map_reserve(virt_to_page(addr));
+#else
+		mem_map_reserve(MAP_NR(addr));
+#endif
+	}
+	
+	return address;
+}
+
+void drm_free_pages(unsigned long address, int order, int area)
+{
+	unsigned long bytes = PAGE_SIZE << order;
+	int		  alloc_count;
+	int		  free_count;
+	unsigned long addr;
+	unsigned int  sz;
+	
+	if (!address) {
+		DRM_MEM_ERROR(area, "Attempt to free address 0\n");
+	} else {
+				/* Unreserve */
+		for (addr = address, sz = bytes;
+		     sz > 0;
+		     addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* Argument type changed in 2.4.0-test6/pre8 */
+			mem_map_unreserve(virt_to_page(addr));
+#else
+			mem_map_unreserve(MAP_NR(addr));
+#endif
+		}
+		free_pages(address, order);
+	}
+	
+	spin_lock(&drm_mem_lock);
+	free_count  = ++drm_mem_stats[area].free_count;
+	alloc_count =	drm_mem_stats[area].succeed_count;
+	drm_mem_stats[area].bytes_freed += bytes;
+	drm_ram_used			-= bytes;
+	spin_unlock(&drm_mem_lock);
+	if (free_count > alloc_count) {
+		DRM_MEM_ERROR(area,
+			      "Excess frees: %d frees, %d allocs\n",
+			      free_count, alloc_count);
+	}
+}
+
+void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev)
+{
+	void *pt;
+	
+	if (!size) {
+		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
+			      "Mapping 0 bytes at 0x%08lx\n", offset);
+		return NULL;
+	}
+	
+	if(dev->agp->cant_use_aperture == 0) {
+		goto standard_ioremap;
+	} else {
+		drm_map_t *map    = NULL;
+		int i;
+
+		for(i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			if (!map) continue;
+			if (map->offset <= offset &&
+				(map->offset + map->size) >= (offset + size))
+				break;
+		}
+		
+		if(map && map->type == _DRM_AGP) {
+			struct drm_agp_mem *agpmem;
+
+			for(agpmem = dev->agp->memory; agpmem;
+						agpmem = agpmem->next) {
+				if(agpmem->bound <= offset &&
+				   (agpmem->bound + (agpmem->pages
+					<< PAGE_SHIFT)) >= (offset + size))
+					break;
+			}
+
+			if(agpmem == NULL)
+				goto standard_ioremap;
+
+			pt = agpmem->memory->vmptr + (offset - agpmem->bound);
+			goto ioremap_success;
+		} else {
+			goto standard_ioremap;
+		}
+	}
+
+standard_ioremap:
+	if (!(pt = ioremap(offset, size))) {
+		spin_lock(&drm_mem_lock);
+		++drm_mem_stats[DRM_MEM_MAPPINGS].fail_count;
+		spin_unlock(&drm_mem_lock);
+		return NULL;
+	}
+
+ioremap_success:
+	spin_lock(&drm_mem_lock);
+	++drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count;
+	drm_mem_stats[DRM_MEM_MAPPINGS].bytes_allocated += size;
+	spin_unlock(&drm_mem_lock);
+	return pt;
+}
+
+void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev)
+{
+	int alloc_count;
+	int free_count;
+	
+	if (!pt)
+		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
+			      "Attempt to free NULL pointer\n");
+	else if(dev->agp->cant_use_aperture == 0)
+		iounmap(pt);
+	
+	spin_lock(&drm_mem_lock);
+	drm_mem_stats[DRM_MEM_MAPPINGS].bytes_freed += size;
+	free_count  = ++drm_mem_stats[DRM_MEM_MAPPINGS].free_count;
+	alloc_count =	drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count;
+	spin_unlock(&drm_mem_lock);
+	if (free_count > alloc_count) {
+		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
+			      "Excess frees: %d frees, %d allocs\n",
+			      free_count, alloc_count);
+	}
+}
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+agp_memory *drm_alloc_agp(int pages, u32 type)
+{
+	agp_memory *handle;
+
+	if (!pages) {
+		DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n");
+		return NULL;
+	}
+	
+	if ((handle = drm_agp_allocate_memory(pages, type))) {
+		spin_lock(&drm_mem_lock);
+		++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
+		drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated
+			+= pages << PAGE_SHIFT;
+		spin_unlock(&drm_mem_lock);
+		return handle;
+	}
+	spin_lock(&drm_mem_lock);
+	++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count;
+	spin_unlock(&drm_mem_lock);
+	return NULL;
+}
+
+int drm_free_agp(agp_memory *handle, int pages)
+{
+	int           alloc_count;
+	int           free_count;
+	int           retval = -EINVAL;
+
+	if (!handle) {
+		DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
+			      "Attempt to free NULL AGP handle\n");
+		return retval;;
+	}
+	
+	if (drm_agp_free_memory(handle)) {
+		spin_lock(&drm_mem_lock);
+		free_count  = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count;
+		alloc_count =   drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
+		drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed
+			+= pages << PAGE_SHIFT;
+		spin_unlock(&drm_mem_lock);
+		if (free_count > alloc_count) {
+			DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
+				      "Excess frees: %d frees, %d allocs\n",
+				      free_count, alloc_count);
+		}
+		return 0;
+	}
+	return retval;
+}
+
+int drm_bind_agp(agp_memory *handle, unsigned int start)
+{
+	int retcode = -EINVAL;
+
+	if (!handle) {
+		DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+			      "Attempt to bind NULL AGP handle\n");
+		return retcode;
+	}
+
+	if (!(retcode = drm_agp_bind_memory(handle, start))) {
+		spin_lock(&drm_mem_lock);
+		++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
+		drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated
+			+= handle->page_count << PAGE_SHIFT;
+		spin_unlock(&drm_mem_lock);
+		return retcode;
+	}
+	spin_lock(&drm_mem_lock);
+	++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count;
+	spin_unlock(&drm_mem_lock);
+	return retcode;
+}
+
+int drm_unbind_agp(agp_memory *handle)
+{
+	int alloc_count;
+	int free_count;
+	int retcode = -EINVAL;
+	
+	if (!handle) {
+		DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+			      "Attempt to unbind NULL AGP handle\n");
+		return retcode;
+	}
+
+	if ((retcode = drm_agp_unbind_memory(handle))) return retcode;
+	spin_lock(&drm_mem_lock);
+	free_count  = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count;
+	alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
+	drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed
+		+= handle->page_count << PAGE_SHIFT;
+	spin_unlock(&drm_mem_lock);
+	if (free_count > alloc_count) {
+		DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
+			      "Excess frees: %d frees, %d allocs\n",
+			      free_count, alloc_count);
+	}
+	return retcode;
+}
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_bufs.c lia64-2.4/drivers/char/drm-4.0/mga_bufs.c
--- linux-2.4.16/drivers/char/drm-4.0/mga_bufs.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_bufs.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,629 @@
+/* mga_bufs.c -- IOCTLs to manage buffers -*- linux-c -*-
+ * Created: Thu Jan 6 01:47:26 2000 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "mga_drv.h"
+#include "linux/un.h"
+
+
+int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd,
+		    unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_desc_t request;
+	drm_buf_entry_t *entry;
+	drm_buf_t *buf;
+	unsigned long offset;
+	unsigned long agp_offset;
+	int count;
+	int order;
+	int size;
+	int alignment;
+	int page_order;
+	int total;
+	int byte_count;
+	int i;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	count = request.count;
+	order = drm_order(request.size);
+	size	= 1 << order;
+	agp_offset = request.agp_start;
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total = PAGE_SIZE << page_order;
+	byte_count = 0;
+
+	DRM_DEBUG("count: %d\n", count);
+	DRM_DEBUG("order: %d\n", order);
+	DRM_DEBUG("size: %d\n", size);
+	DRM_DEBUG("agp_offset: %ld\n", agp_offset);
+	DRM_DEBUG("alignment: %d\n", alignment);
+	DRM_DEBUG("page_order: %d\n", page_order);
+	DRM_DEBUG("total: %d\n", total);
+	DRM_DEBUG("byte_count: %d\n", byte_count);
+
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+   
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM; /* May only call once for each order */
+	}
+
+	/* This isnt neccessarily a good limit, but we have to stop a dumb
+	   32 bit overflow problem below */
+	   
+	if ( count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -EINVAL;
+	}
+		   
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+   
+	entry->buf_size   = size;
+	entry->page_order = page_order;
+	offset = 0;
+
+   
+	while(entry->buf_count < count) {
+		buf = &entry->buflist[entry->buf_count];
+		buf->idx = dma->buf_count + entry->buf_count;
+		buf->total = alignment;
+		buf->order = order;
+		buf->used = 0;
+
+		buf->offset = offset; /* Hrm */
+		buf->bus_address = dev->agp->base + agp_offset + offset;
+		buf->address = (void *)(agp_offset + offset + dev->agp->base);
+		buf->next = NULL;
+		buf->waiting = 0;
+		buf->pending = 0;
+		init_waitqueue_head(&buf->dma_wait);
+		buf->pid = 0;
+
+		buf->dev_private = drm_alloc(sizeof(drm_mga_buf_priv_t),
+					     DRM_MEM_BUFS);
+		buf->dev_priv_size = sizeof(drm_mga_buf_priv_t);
+
+#if DRM_DMA_HISTOGRAM
+		buf->time_queued = 0;
+		buf->time_dispatched = 0;
+		buf->time_completed = 0;
+		buf->time_freed = 0;
+#endif
+		offset = offset + alignment;
+		entry->buf_count++;
+		byte_count += PAGE_SIZE << page_order;
+	}
+   
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+   
+	dma->buf_count  += entry->buf_count;
+
+	DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
+
+	dma->byte_count += byte_count;
+
+	DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
+
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+   
+	up(&dev->struct_sem);
+   
+	request.count = entry->buf_count;
+	request.size  = size;
+   
+	if (copy_to_user((drm_buf_desc_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+   
+	atomic_dec(&dev->buf_alloc);
+
+	DRM_DEBUG("count: %d\n", count);
+	DRM_DEBUG("order: %d\n", order);
+	DRM_DEBUG("size: %d\n", size);
+	DRM_DEBUG("agp_offset: %ld\n", agp_offset);
+	DRM_DEBUG("alignment: %d\n", alignment);
+	DRM_DEBUG("page_order: %d\n", page_order);
+	DRM_DEBUG("total: %d\n", total);
+	DRM_DEBUG("byte_count: %d\n", byte_count);
+
+	dma->flags = _DRM_DMA_USE_AGP;
+
+	DRM_DEBUG("dma->flags : %x\n", dma->flags);
+
+	return 0;
+}
+
+int mga_addbufs_pci(struct inode *inode, struct file *filp, unsigned int cmd,
+		    unsigned long arg)
+{
+   	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_desc_t	 request;
+	int		 count;
+	int		 order;
+	int		 size;
+	int		 total;
+	int		 page_order;
+	drm_buf_entry_t	 *entry;
+	unsigned long	 page;
+	drm_buf_t	 *buf;
+	int		 alignment;
+	unsigned long	 offset;
+	int		 i;
+	int		 byte_count;
+	int		 page_count;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	count	   = request.count;
+	order	   = drm_order(request.size);
+	size	   = 1 << order;
+	
+	DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n",
+		  request.count, request.size, size, order, dev->queue_count);
+
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total	   = PAGE_SIZE << page_order;
+
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+	
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;	/* May only call once for each order */
+	}
+	
+	if(count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -EINVAL;
+	}
+	
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+
+	entry->seglist = drm_alloc(count * sizeof(*entry->seglist),
+				   DRM_MEM_SEGS);
+	if (!entry->seglist) {
+		drm_free(entry->buflist,
+			 count * sizeof(*entry->buflist),
+			 DRM_MEM_BUFS);
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->seglist, 0, count * sizeof(*entry->seglist));
+
+	dma->pagelist = drm_realloc(dma->pagelist,
+				    dma->page_count * sizeof(*dma->pagelist),
+				    (dma->page_count + (count << page_order))
+				    * sizeof(*dma->pagelist),
+				    DRM_MEM_PAGES);
+	DRM_DEBUG("pagelist: %d entries\n",
+		  dma->page_count + (count << page_order));
+
+
+	entry->buf_size	  = size;
+	entry->page_order = page_order;
+	byte_count	  = 0;
+	page_count	  = 0;
+	while (entry->buf_count < count) {
+		if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break;
+		entry->seglist[entry->seg_count++] = page;
+		for (i = 0; i < (1 << page_order); i++) {
+			DRM_DEBUG("page %d @ 0x%08lx\n",
+				  dma->page_count + page_count,
+				  page + PAGE_SIZE * i);
+			dma->pagelist[dma->page_count + page_count++]
+				= page + PAGE_SIZE * i;
+		}
+		for (offset = 0;
+		     offset + size <= total && entry->buf_count < count;
+		     offset += alignment, ++entry->buf_count) {
+			buf	     = &entry->buflist[entry->buf_count];
+			buf->idx     = dma->buf_count + entry->buf_count;
+			buf->total   = alignment;
+			buf->order   = order;
+			buf->used    = 0;
+			buf->offset  = (dma->byte_count + byte_count + offset);
+			buf->address = (void *)(page + offset);
+			buf->next    = NULL;
+			buf->waiting = 0;
+			buf->pending = 0;
+			init_waitqueue_head(&buf->dma_wait);
+			buf->pid     = 0;
+#if DRM_DMA_HISTOGRAM
+			buf->time_queued     = 0;
+			buf->time_dispatched = 0;
+			buf->time_completed  = 0;
+			buf->time_freed	     = 0;
+#endif
+			DRM_DEBUG("buffer %d @ %p\n",
+				  entry->buf_count, buf->address);
+		}
+		byte_count += PAGE_SIZE << page_order;
+	}
+
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+
+	dma->buf_count	+= entry->buf_count;
+	dma->seg_count	+= entry->seg_count;
+	dma->page_count += entry->seg_count << page_order;
+	dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order);
+	
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+	
+	up(&dev->struct_sem);
+
+	request.count = entry->buf_count;
+	request.size  = size;
+
+	if (copy_to_user((drm_buf_desc_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+	
+	atomic_dec(&dev->buf_alloc);
+	return 0;
+}
+
+int mga_addbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_buf_desc_t	 request;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	if(request.flags & _DRM_AGP_BUFFER)
+		return mga_addbufs_agp(inode, filp, cmd, arg);
+	else
+		return mga_addbufs_pci(inode, filp, cmd, arg);
+}
+
+int mga_infobufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_info_t	 request;
+	int		 i;
+	int		 count;
+
+	if (!dma) return -EINVAL;
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_info_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+		if (dma->bufs[i].buf_count) ++count;
+	}
+	
+	if (request.count >= count) {
+		for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) {
+			if (dma->bufs[i].buf_count) {
+				if (copy_to_user(&request.list[count].count,
+						 &dma->bufs[i].buf_count,
+						 sizeof(dma->bufs[0]
+							.buf_count)) ||
+				    copy_to_user(&request.list[count].size,
+						 &dma->bufs[i].buf_size,
+						 sizeof(dma->bufs[0].buf_size)) ||
+				    copy_to_user(&request.list[count].low_mark,
+						 &dma->bufs[i]
+						 .freelist.low_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.low_mark)) ||
+				    copy_to_user(&request.list[count]
+						 .high_mark,
+						 &dma->bufs[i]
+						 .freelist.high_mark,
+						 sizeof(dma->bufs[0]
+							.freelist.high_mark)))
+					return -EFAULT;
+				++count;
+			}
+		}
+	}
+	request.count = count;
+
+	if (copy_to_user((drm_buf_info_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+	
+	return 0;
+}
+
+int mga_markbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_desc_t	 request;
+	int		 order;
+	drm_buf_entry_t	 *entry;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request)))
+		return -EFAULT;
+
+	order = drm_order(request.size);
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	entry = &dma->bufs[order];
+
+	if (request.low_mark < 0 || request.low_mark > entry->buf_count)
+		return -EINVAL;
+	if (request.high_mark < 0 || request.high_mark > entry->buf_count)
+		return -EINVAL;
+
+	entry->freelist.low_mark  = request.low_mark;
+	entry->freelist.high_mark = request.high_mark;
+	
+	return 0;
+}
+
+int mga_freebufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	drm_buf_free_t	 request;
+	int		 i;
+	int		 idx;
+	drm_buf_t	 *buf;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_free_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	for (i = 0; i < request.count; i++) {
+		if (copy_from_user(&idx,
+				   &request.list[i],
+				   sizeof(idx)))
+			return -EFAULT;
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+				  idx, dma->buf_count - 1);
+			return -EINVAL;
+		}
+		buf = dma->buflist[idx];
+		if (buf->pid != current->pid) {
+			DRM_ERROR("Process %d freeing buffer owned by %d\n",
+				  current->pid, buf->pid);
+			return -EINVAL;
+		}
+		drm_free_buffer(dev, buf);
+	}
+	
+	return 0;
+}
+
+int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	int		 retcode = 0;
+	const int	 zero	 = 0;
+	unsigned long	 virtual;
+	unsigned long	 address;
+	drm_buf_map_t	 request;
+	int		 i;
+
+	if (!dma) return -EINVAL;
+	
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_map_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	if (request.count >= dma->buf_count) {
+		if(dma->flags & _DRM_DMA_USE_AGP) {
+			drm_mga_private_t *dev_priv = dev->dev_private;
+			drm_map_t *map = NULL;
+	 
+			map = dev->maplist[dev_priv->buffer_map_idx];
+			if (!map) {
+				retcode = -EINVAL;
+				goto done;
+			}
+
+			DRM_DEBUG("map->offset : %lx\n", map->offset);
+			DRM_DEBUG("map->size : %lx\n", map->size);
+			DRM_DEBUG("map->type : %d\n", map->type);
+			DRM_DEBUG("map->flags : %x\n", map->flags);
+			DRM_DEBUG("map->handle : %p\n", map->handle);
+			DRM_DEBUG("map->mtrr : %d\n", map->mtrr);
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, map->size, 
+					  PROT_READ|PROT_WRITE,
+					  MAP_SHARED, 
+					  (unsigned long)map->offset);
+			up_write(&current->mm->mmap_sem);
+		} else {
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, dma->byte_count,
+					  PROT_READ|PROT_WRITE, MAP_SHARED, 0);
+			up_write(&current->mm->mmap_sem);
+		}
+		if (virtual > -1024UL) {
+			/* Real error */
+			DRM_DEBUG("mmap error\n");
+			retcode = (signed long)virtual;
+			goto done;
+		}
+		request.virtual = (void *)virtual;
+      
+		for (i = 0; i < dma->buf_count; i++) {
+			if (copy_to_user(&request.list[i].idx,
+					 &dma->buflist[i]->idx,
+					 sizeof(request.list[0].idx))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].total,
+					 &dma->buflist[i]->total,
+					 sizeof(request.list[0].total))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].used,
+					 &zero,
+					 sizeof(zero))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			address = virtual + dma->buflist[i]->offset;
+			if (copy_to_user(&request.list[i].address,
+					 &address,
+					 sizeof(address))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+		}
+	}
+ done:
+	request.count = dma->buf_count;
+	DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode);
+   
+	if (copy_to_user((drm_buf_map_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+
+	DRM_DEBUG("retcode : %d\n", retcode);
+
+	return retcode;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_context.c lia64-2.4/drivers/char/drm-4.0/mga_context.c
--- linux-2.4.16/drivers/char/drm-4.0/mga_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_context.c	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,209 @@
+/* mga_context.c -- IOCTLs for mga contexts -*- linux-c -*-
+ * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	   Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "mga_drv.h"
+
+static int mga_alloc_queue(drm_device_t *dev)
+{
+   	return drm_ctxbitmap_next(dev);
+}
+
+int mga_context_switch(drm_device_t *dev, int old, int new)
+{
+        char        buf[64];
+
+        atomic_inc(&dev->total_ctx);
+
+        if (test_and_set_bit(0, &dev->context_flag)) {
+                DRM_ERROR("Reentering -- FIXME\n");
+                return -EBUSY;
+        }
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+        
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context) {
+                clear_bit(0, &dev->context_flag);
+                return 0;
+        }
+        
+        if (drm_flags & DRM_FLAG_NOCTX) {
+                mga_context_switch_complete(dev, new);
+        } else {
+                sprintf(buf, "C %d %d\n", old, new);
+                drm_write_string(dev, buf);
+        }
+        
+        return 0;
+}
+
+int mga_context_switch_complete(drm_device_t *dev, int new)
+{
+        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+        dev->last_switch  = jiffies;
+        
+        if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+                DRM_ERROR("Lock isn't held after context switch\n");
+        }
+
+				/* If a context switch is ever initiated
+                                   when the kernel holds the lock, release
+                                   that lock here. */
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+                                                      - dev->ctx_start)]);
+                   
+#endif
+        clear_bit(0, &dev->context_flag);
+        wake_up(&dev->context_wait);
+        
+        return 0;
+}
+
+int mga_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+int mga_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = mga_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Skip kernel's context and get a new one. */
+		ctx.handle = mga_alloc_queue(dev);
+	}
+        if (ctx.handle == -1) {
+		return -ENOMEM;
+	}
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int mga_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+   	/* This does nothing for the mga */
+	return 0;
+}
+
+int mga_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	/* This is 0, because we don't hanlde any context flags */
+	ctx.flags = 0;
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int mga_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return mga_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int mga_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	mga_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int mga_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	if(ctx.handle == DRM_KERNEL_CONTEXT+1) priv->remove_auth_on_close = 1;
+
+      	if(ctx.handle != DRM_KERNEL_CONTEXT) {
+	   	drm_ctxbitmap_free(dev, ctx.handle);
+	}
+	
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_dma.c lia64-2.4/drivers/char/drm-4.0/mga_dma.c
--- linux-2.4.16/drivers/char/drm-4.0/mga_dma.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_dma.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,1059 @@
+/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *	    Keith Whitwell <keithw@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "mga_drv.h"
+
+#include <linux/interrupt.h>	/* For task queue support */
+
+#define MGA_REG(reg)		2
+#define MGA_BASE(reg)		((unsigned long) \
+				((drm_device_t *)dev)->maplist[MGA_REG(reg)]->handle)
+#define MGA_ADDR(reg)		(MGA_BASE(reg) + reg)
+#define MGA_DEREF(reg)		*(__volatile__ int *)MGA_ADDR(reg)
+#define MGA_READ(reg)		MGA_DEREF(reg)
+#define MGA_WRITE(reg,val) 	do { MGA_DEREF(reg) = val; } while (0)
+
+#define PDEA_pagpxfer_enable 	     0x2
+
+static int mga_flush_queue(drm_device_t *dev);
+
+static unsigned long mga_alloc_page(drm_device_t *dev)
+{
+	unsigned long address;
+
+	address = __get_free_page(GFP_KERNEL);
+	if(address == 0UL) {
+		return 0;
+	}
+	atomic_inc(&virt_to_page(address)->count);
+	set_bit(PG_reserved, &virt_to_page(address)->flags);
+
+	return address;
+}
+
+static void mga_free_page(drm_device_t *dev, unsigned long page)
+{
+	if(!page) return;
+	atomic_dec(&virt_to_page(page)->count);
+	clear_bit(PG_reserved, &virt_to_page(page)->flags);
+	free_page(page);
+	return;
+}
+
+static void mga_delay(void)
+{
+	return;
+}
+
+/* These are two age tags that will never be sent to
+ * the hardware */
+#define MGA_BUF_USED 	0xffffffff
+#define MGA_BUF_FREE	0
+
+static int mga_freelist_init(drm_device_t *dev)
+{
+      	drm_device_dma_t *dma = dev->dma;
+   	drm_buf_t *buf;
+   	drm_mga_buf_priv_t *buf_priv;
+      	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+   	drm_mga_freelist_t *item;
+   	int i;
+
+   	dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
+	if(dev_priv->head == NULL) return -ENOMEM;
+   	memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
+   	dev_priv->head->age = MGA_BUF_USED;
+
+   	for (i = 0; i < dma->buf_count; i++) {
+	   	buf = dma->buflist[ i ];
+	        buf_priv = buf->dev_private;
+		item = drm_alloc(sizeof(drm_mga_freelist_t),
+				 DRM_MEM_DRIVER);
+	   	if(item == NULL) return -ENOMEM;
+	   	memset(item, 0, sizeof(drm_mga_freelist_t));
+	  	item->age = MGA_BUF_FREE;
+	   	item->prev = dev_priv->head;
+	   	item->next = dev_priv->head->next;
+	   	if(dev_priv->head->next != NULL)
+			dev_priv->head->next->prev = item;
+	   	if(item->next == NULL) dev_priv->tail = item;
+	   	item->buf = buf;
+	   	buf_priv->my_freelist = item;
+		buf_priv->discard = 0;
+		buf_priv->dispatched = 0;
+	   	dev_priv->head->next = item;
+	}
+
+   	return 0;
+}
+
+static void mga_freelist_cleanup(drm_device_t *dev)
+{
+      	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+   	drm_mga_freelist_t *item;
+   	drm_mga_freelist_t *prev;
+
+   	item = dev_priv->head;
+   	while(item) {
+	   	prev = item;
+	   	item = item->next;
+	   	drm_free(prev, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
+	}
+
+   	dev_priv->head = dev_priv->tail = NULL;
+}
+
+/* Frees dispatch lock */
+static inline void mga_dma_quiescent(drm_device_t *dev)
+{
+	drm_device_dma_t  *dma      = dev->dma;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+   	unsigned long end;
+	int i;
+
+	DRM_DEBUG("dispatch_status = 0x%02lx\n", dev_priv->dispatch_status);
+	end = jiffies + (HZ*3);
+    	while(1) {
+		if(!test_and_set_bit(MGA_IN_DISPATCH,
+				     &dev_priv->dispatch_status)) {
+			break;
+		}
+	   	if((signed)(end - jiffies) <= 0) {
+			DRM_ERROR("irqs: %d wanted %d\n",
+				  atomic_read(&dev->total_irq),
+				  atomic_read(&dma->total_lost));
+			DRM_ERROR("lockup: dispatch_status = 0x%02lx,"
+				  " jiffies = %lu, end = %lu\n",
+				  dev_priv->dispatch_status, jiffies, end);
+			return;
+		}
+		for (i = 0 ; i < 2000 ; i++) mga_delay();
+	}
+	end = jiffies + (HZ*3);
+    	DRM_DEBUG("quiescent status : %x\n", MGA_READ(MGAREG_STATUS));
+    	while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) {
+		if((signed)(end - jiffies) <= 0) {
+			DRM_ERROR("irqs: %d wanted %d\n",
+				  atomic_read(&dev->total_irq),
+				  atomic_read(&dma->total_lost));
+			DRM_ERROR("lockup\n");
+			clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status);
+			return;
+		}
+		for (i = 0 ; i < 2000 ; i++) mga_delay();
+	}
+    	sarea_priv->dirty |= MGA_DMA_FLUSH;
+
+    	clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status);
+	DRM_DEBUG("exit, dispatch_status = 0x%02lx\n",
+		  dev_priv->dispatch_status);
+}
+
+static void mga_reset_freelist(drm_device_t *dev)
+{
+   	drm_device_dma_t  *dma      = dev->dma;
+   	drm_buf_t *buf;
+   	drm_mga_buf_priv_t *buf_priv;
+	int i;
+
+   	for (i = 0; i < dma->buf_count; i++) {
+	   	buf = dma->buflist[ i ];
+	        buf_priv = buf->dev_private;
+		buf_priv->my_freelist->age = MGA_BUF_FREE;
+	}
+}
+
+/* Least recently used :
+ * These operations are not atomic b/c they are protected by the
+ * hardware lock */
+
+drm_buf_t *mga_freelist_get(drm_device_t *dev)
+{
+   	DECLARE_WAITQUEUE(entry, current);
+   	drm_mga_private_t *dev_priv =
+     		(drm_mga_private_t *) dev->dev_private;
+	drm_mga_freelist_t *prev;
+   	drm_mga_freelist_t *next;
+	static int failed = 0;
+	int return_null = 0;
+
+	if(failed >= 1000 && dev_priv->tail->age >= dev_priv->last_prim_age) {
+		DRM_DEBUG("Waiting on freelist,"
+			  " tail->age = %d, last_prim_age= %d\n",
+			  dev_priv->tail->age,
+			  dev_priv->last_prim_age);
+	   	add_wait_queue(&dev_priv->buf_queue, &entry);
+		set_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status);
+	   	for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+		   	mga_dma_schedule(dev, 0);
+			if(dev_priv->tail->age < dev_priv->last_prim_age)
+				break;
+		   	atomic_inc(&dev->total_sleeps);
+		   	schedule();
+		   	if (signal_pending(current)) {
+				++return_null;
+				break;
+			}
+		}
+		clear_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status);
+		current->state = TASK_RUNNING;
+	   	remove_wait_queue(&dev_priv->buf_queue, &entry);
+		if (return_null) return NULL;
+	}
+
+   	if(dev_priv->tail->age < dev_priv->last_prim_age) {
+		prev = dev_priv->tail->prev;
+	   	next = dev_priv->tail;
+	   	prev->next = NULL;
+	   	next->prev = next->next = NULL;
+	   	dev_priv->tail = prev;
+	   	next->age = MGA_BUF_USED;
+		failed = 0;
+	   	return next->buf;
+	}
+
+	failed++;
+   	return NULL;
+}
+
+int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf)
+{
+      	drm_mga_private_t *dev_priv =
+     		(drm_mga_private_t *) dev->dev_private;
+   	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
+	drm_mga_freelist_t *prev;
+   	drm_mga_freelist_t *head;
+   	drm_mga_freelist_t *next;
+
+   	if(buf_priv->my_freelist->age == MGA_BUF_USED) {
+		/* Discarded buffer, put it on the tail */
+		next = buf_priv->my_freelist;
+		next->age = MGA_BUF_FREE;
+		prev = dev_priv->tail;
+		prev->next = next;
+		next->prev = prev;
+		next->next = NULL;
+		dev_priv->tail = next;
+	} else {
+		/* Normally aged buffer, put it on the head + 1,
+		 * as the real head is a sentinal element
+		 */
+		next = buf_priv->my_freelist;
+		head = dev_priv->head;
+		prev = head->next;
+		head->next = next;
+		prev->prev = next;
+		next->prev = head;
+		next->next = prev;
+	}
+
+   	return 0;
+}
+
+static int mga_init_primary_bufs(drm_device_t *dev, drm_mga_init_t *init)
+{
+   	drm_mga_private_t *dev_priv = dev->dev_private;
+	drm_mga_prim_buf_t *prim_buffer;
+   	int i, temp, size_of_buf;
+   	int offset = init->reserved_map_agpstart;
+
+   	dev_priv->primary_size = ((init->primary_size + PAGE_SIZE - 1) /
+				  PAGE_SIZE) * PAGE_SIZE;
+   	size_of_buf = dev_priv->primary_size / MGA_NUM_PRIM_BUFS;
+	dev_priv->warp_ucode_size = init->warp_ucode_size;
+   	dev_priv->prim_bufs = drm_alloc(sizeof(drm_mga_prim_buf_t *) *
+					(MGA_NUM_PRIM_BUFS + 1),
+					DRM_MEM_DRIVER);
+   	if(dev_priv->prim_bufs == NULL) {
+		DRM_ERROR("Unable to allocate memory for prim_buf\n");
+		return -ENOMEM;
+	}
+   	memset(dev_priv->prim_bufs,
+	       0, sizeof(drm_mga_prim_buf_t *) * (MGA_NUM_PRIM_BUFS + 1));
+
+   	temp = init->warp_ucode_size + dev_priv->primary_size;
+	temp = ((temp + PAGE_SIZE - 1) / PAGE_SIZE) * PAGE_SIZE;
+
+	dev_priv->ioremap = drm_ioremap(dev->agp->base + offset,
+					temp, dev);
+	if(dev_priv->ioremap == NULL) {
+		DRM_ERROR("Ioremap failed\n");
+		return -ENOMEM;
+	}
+   	init_waitqueue_head(&dev_priv->wait_queue);
+
+   	for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) {
+	   	prim_buffer = drm_alloc(sizeof(drm_mga_prim_buf_t),
+					DRM_MEM_DRIVER);
+	   	if(prim_buffer == NULL) return -ENOMEM;
+	   	memset(prim_buffer, 0, sizeof(drm_mga_prim_buf_t));
+	   	prim_buffer->phys_head = offset + dev->agp->base;
+	   	prim_buffer->current_dma_ptr =
+			prim_buffer->head =
+			(u32 *) (dev_priv->ioremap +
+				 offset -
+				 init->reserved_map_agpstart);
+	   	prim_buffer->num_dwords = 0;
+	   	prim_buffer->max_dwords = size_of_buf / sizeof(u32);
+	   	prim_buffer->max_dwords -= 5; /* Leave room for the softrap */
+	   	prim_buffer->sec_used = 0;
+	   	prim_buffer->idx = i;
+		prim_buffer->prim_age = i + 1;
+	   	offset = offset + size_of_buf;
+	   	dev_priv->prim_bufs[i] = prim_buffer;
+	}
+	dev_priv->current_prim_idx = 0;
+        dev_priv->next_prim =
+		dev_priv->last_prim =
+		dev_priv->current_prim =
+        	dev_priv->prim_bufs[0];
+	dev_priv->next_prim_age = 2;
+	dev_priv->last_prim_age = 1;
+   	set_bit(MGA_BUF_IN_USE, &dev_priv->current_prim->buffer_status);
+   	return 0;
+}
+
+void mga_fire_primary(drm_device_t *dev, drm_mga_prim_buf_t *prim)
+{
+       	drm_mga_private_t *dev_priv = dev->dev_private;
+      	drm_device_dma_t  *dma	    = dev->dma;
+       	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ 	int use_agp = PDEA_pagpxfer_enable;
+	unsigned long end;
+   	int i;
+   	int next_idx;
+       	PRIMLOCALS;
+
+   	dev_priv->last_prim = prim;
+
+ 	/* We never check for overflow, b/c there is always room */
+    	PRIMPTR(prim);
+   	if(num_dwords <= 0) {
+		DRM_ERROR("num_dwords == 0 when dispatched\n");
+		goto out_prim_wait;
+	}
+ 	PRIMOUTREG( MGAREG_DMAPAD, 0);
+ 	PRIMOUTREG( MGAREG_DMAPAD, 0);
+       	PRIMOUTREG( MGAREG_DMAPAD, 0);
+   	PRIMOUTREG( MGAREG_SOFTRAP, 0);
+    	PRIMFINISH(prim);
+
+	end = jiffies + (HZ*3);
+    	if(sarea_priv->dirty & MGA_DMA_FLUSH) {
+		while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) {
+			if((signed)(end - jiffies) <= 0) {
+				DRM_ERROR("irqs: %d wanted %d\n",
+					  atomic_read(&dev->total_irq),
+					  atomic_read(&dma->total_lost));
+				DRM_ERROR("lockup (flush)\n");
+				goto out_prim_wait;
+			}
+
+			for (i = 0 ; i < 4096 ; i++) mga_delay();
+		}
+		sarea_priv->dirty &= ~(MGA_DMA_FLUSH);
+	} else {
+		while((MGA_READ(MGAREG_STATUS) & 0x00020001) != 0x00020000) {
+			if((signed)(end - jiffies) <= 0) {
+				DRM_ERROR("irqs: %d wanted %d\n",
+					  atomic_read(&dev->total_irq),
+					  atomic_read(&dma->total_lost));
+				DRM_ERROR("lockup (wait)\n");
+				goto out_prim_wait;
+			}
+
+			for (i = 0 ; i < 4096 ; i++) mga_delay();
+		}
+	}
+
+   	mga_flush_write_combine();
+    	atomic_inc(&dev_priv->pending_bufs);
+       	MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL);
+ 	MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp);
+   	prim->num_dwords = 0;
+	sarea_priv->last_enqueue = prim->prim_age;
+
+   	next_idx = prim->idx + 1;
+    	if(next_idx >= MGA_NUM_PRIM_BUFS)
+		next_idx = 0;
+
+    	dev_priv->next_prim = dev_priv->prim_bufs[next_idx];
+	return;
+
+ out_prim_wait:
+	prim->num_dwords = 0;
+	prim->sec_used = 0;
+	clear_bit(MGA_BUF_IN_USE, &prim->buffer_status);
+   	wake_up_interruptible(&dev_priv->wait_queue);
+	clear_bit(MGA_BUF_SWAP_PENDING, &prim->buffer_status);
+	clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status);
+}
+
+int mga_advance_primary(drm_device_t *dev)
+{
+   	DECLARE_WAITQUEUE(entry, current);
+   	drm_mga_private_t *dev_priv = dev->dev_private;
+   	drm_mga_prim_buf_t *prim_buffer;
+   	drm_device_dma_t  *dma      = dev->dma;
+   	int next_prim_idx;
+   	int ret = 0;
+
+   	/* This needs to reset the primary buffer if available,
+	 * we should collect stats on how many times it bites
+	 * it's tail */
+
+   	next_prim_idx = dev_priv->current_prim_idx + 1;
+   	if(next_prim_idx >= MGA_NUM_PRIM_BUFS)
+     		next_prim_idx = 0;
+   	prim_buffer = dev_priv->prim_bufs[next_prim_idx];
+	set_bit(MGA_IN_WAIT, &dev_priv->dispatch_status);
+
+      	/* In use is cleared in interrupt handler */
+
+   	if(test_and_set_bit(MGA_BUF_IN_USE, &prim_buffer->buffer_status)) {
+	   	add_wait_queue(&dev_priv->wait_queue, &entry);
+	   	for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+		   	mga_dma_schedule(dev, 0);
+		   	if(!test_and_set_bit(MGA_BUF_IN_USE,
+					     &prim_buffer->buffer_status))
+				break;
+		   	atomic_inc(&dev->total_sleeps);
+		   	atomic_inc(&dma->total_missed_sched);
+		   	schedule();
+		   	if (signal_pending(current)) {
+			   	ret = -ERESTARTSYS;
+			   	break;
+			}
+		}
+		current->state = TASK_RUNNING;
+	   	remove_wait_queue(&dev_priv->wait_queue, &entry);
+	   	if(ret) return ret;
+	}
+	clear_bit(MGA_IN_WAIT, &dev_priv->dispatch_status);
+
+   	/* This primary buffer is now free to use */
+   	prim_buffer->current_dma_ptr = prim_buffer->head;
+   	prim_buffer->num_dwords = 0;
+   	prim_buffer->sec_used = 0;
+	prim_buffer->prim_age = dev_priv->next_prim_age++;
+	if(prim_buffer->prim_age == 0 || prim_buffer->prim_age == 0xffffffff) {
+		mga_flush_queue(dev);
+		mga_dma_quiescent(dev);
+		mga_reset_freelist(dev);
+		prim_buffer->prim_age = (dev_priv->next_prim_age += 2);
+	}
+
+	/* Reset all buffer status stuff */
+	clear_bit(MGA_BUF_NEEDS_OVERFLOW, &prim_buffer->buffer_status);
+	clear_bit(MGA_BUF_FORCE_FIRE, &prim_buffer->buffer_status);
+	clear_bit(MGA_BUF_SWAP_PENDING, &prim_buffer->buffer_status);
+
+   	dev_priv->current_prim = prim_buffer;
+   	dev_priv->current_prim_idx = next_prim_idx;
+   	return 0;
+}
+
+/* More dynamic performance decisions */
+static inline int mga_decide_to_fire(drm_device_t *dev)
+{
+   	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+
+   	if(test_bit(MGA_BUF_FORCE_FIRE, &dev_priv->next_prim->buffer_status)) {
+	   	return 1;
+	}
+
+	if (test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status) &&
+	    dev_priv->next_prim->num_dwords) {
+	   	return 1;
+	}
+
+	if (test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) &&
+	    dev_priv->next_prim->num_dwords) {
+	   	return 1;
+	}
+
+   	if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS - 1) {
+		if(test_bit(MGA_BUF_SWAP_PENDING,
+			    &dev_priv->next_prim->buffer_status)) {
+			return 1;
+		}
+	}
+
+   	if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS / 2) {
+		if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 8) {
+			return 1;
+		}
+	}
+
+   	if(atomic_read(&dev_priv->pending_bufs) >= MGA_NUM_PRIM_BUFS / 2) {
+		if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 4) {
+			return 1;
+		}
+	}
+
+   	return 0;
+}
+
+int mga_dma_schedule(drm_device_t *dev, int locked)
+{
+      	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+	int               retval    = 0;
+
+   	if (!dev_priv) return -EBUSY;
+	
+	if (test_and_set_bit(0, &dev->dma_flag)) {
+		retval = -EBUSY;
+		goto sch_out_wakeup;
+	}
+
+   	if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) ||
+	   test_bit(MGA_IN_WAIT, &dev_priv->dispatch_status) ||
+	   test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status)) {
+		locked = 1;
+	}
+
+   	if (!locked &&
+	    !drm_lock_take(&dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) {
+	   	clear_bit(0, &dev->dma_flag);
+		retval = -EBUSY;
+		goto sch_out_wakeup;
+	}
+
+   	if(!test_and_set_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status)) {
+	   	/* Fire dma buffer */
+	   	if(mga_decide_to_fire(dev)) {
+			clear_bit(MGA_BUF_FORCE_FIRE,
+				  &dev_priv->next_prim->buffer_status);
+		   	if(dev_priv->current_prim == dev_priv->next_prim) {
+				/* Schedule overflow for a later time */
+				set_bit(MGA_BUF_NEEDS_OVERFLOW,
+					&dev_priv->next_prim->buffer_status);
+			}
+		   	mga_fire_primary(dev, dev_priv->next_prim);
+		} else {
+			clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status);
+		}
+	}
+
+	if (!locked) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+
+	clear_bit(0, &dev->dma_flag);
+
+sch_out_wakeup:
+      	if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) &&
+	   atomic_read(&dev_priv->pending_bufs) == 0) {
+		/* Everything has been processed by the hardware */
+		clear_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status);
+		wake_up_interruptible(&dev_priv->flush_queue);
+	}
+
+	if(test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status)
+	   && dev_priv->tail->age < dev_priv->last_prim_age)
+		wake_up_interruptible(&dev_priv->buf_queue);
+
+	return retval;
+}
+
+static void mga_dma_service(int irq, void *device, struct pt_regs *regs)
+{
+    	drm_device_t	 *dev = (drm_device_t *)device;
+    	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+    	drm_mga_prim_buf_t *last_prim_buffer;
+
+    	atomic_inc(&dev->total_irq);
+	if((MGA_READ(MGAREG_STATUS) & 0x00000001) != 0x00000001) return;
+      	MGA_WRITE(MGAREG_ICLEAR, 0x00000001);
+   	last_prim_buffer = dev_priv->last_prim;
+    	last_prim_buffer->num_dwords = 0;
+    	last_prim_buffer->sec_used = 0;
+	dev_priv->sarea_priv->last_dispatch =
+		dev_priv->last_prim_age = last_prim_buffer->prim_age;
+      	clear_bit(MGA_BUF_IN_USE, &last_prim_buffer->buffer_status);
+      	clear_bit(MGA_BUF_SWAP_PENDING, &last_prim_buffer->buffer_status);
+      	clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status);
+      	atomic_dec(&dev_priv->pending_bufs);
+   	queue_task(&dev->tq, &tq_immediate);
+   	mark_bh(IMMEDIATE_BH);
+   	wake_up_interruptible(&dev_priv->wait_queue);
+}
+
+static void mga_dma_task_queue(void *device)
+{
+	mga_dma_schedule((drm_device_t *)device, 0);
+}
+
+int mga_dma_cleanup(drm_device_t *dev)
+{
+	if(dev->dev_private) {
+		drm_mga_private_t *dev_priv =
+			(drm_mga_private_t *) dev->dev_private;
+
+		if (dev->irq) mga_flush_queue(dev);
+		mga_dma_quiescent(dev);
+
+		if(dev_priv->ioremap) {
+			int temp = (dev_priv->warp_ucode_size +
+				    dev_priv->primary_size +
+				    PAGE_SIZE - 1) / PAGE_SIZE * PAGE_SIZE;
+
+			drm_ioremapfree((void *) dev_priv->ioremap, temp, dev);
+		}
+	   	if(dev_priv->status_page != NULL) {
+		   	iounmap(dev_priv->status_page);
+		}
+	   	if(dev_priv->real_status_page != 0UL) {
+		   	mga_free_page(dev, dev_priv->real_status_page);
+		}
+	   	if(dev_priv->prim_bufs != NULL) {
+		   	int i;
+		   	for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) {
+			   	if(dev_priv->prim_bufs[i] != NULL) {
+			     		drm_free(dev_priv->prim_bufs[i],
+						 sizeof(drm_mga_prim_buf_t),
+						 DRM_MEM_DRIVER);
+				}
+			}
+		   	drm_free(dev_priv->prim_bufs, sizeof(void *) *
+				 (MGA_NUM_PRIM_BUFS + 1),
+				 DRM_MEM_DRIVER);
+		}
+		if(dev_priv->head != NULL) {
+		   	mga_freelist_cleanup(dev);
+		}
+
+
+		drm_free(dev->dev_private, sizeof(drm_mga_private_t),
+			 DRM_MEM_DRIVER);
+		dev->dev_private = NULL;
+	}
+
+	return 0;
+}
+
+static int mga_dma_initialize(drm_device_t *dev, drm_mga_init_t *init) {
+	drm_mga_private_t *dev_priv;
+	drm_map_t *sarea_map = NULL;
+
+	dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
+	if(dev_priv == NULL) return -ENOMEM;
+	dev->dev_private = (void *) dev_priv;
+
+	memset(dev_priv, 0, sizeof(drm_mga_private_t));
+
+	if((init->reserved_map_idx >= dev->map_count) ||
+	   (init->buffer_map_idx >= dev->map_count)) {
+		mga_dma_cleanup(dev);
+		return -EINVAL;
+	}
+
+	dev_priv->reserved_map_idx = init->reserved_map_idx;
+	dev_priv->buffer_map_idx = init->buffer_map_idx;
+	sarea_map = dev->maplist[0];
+	dev_priv->sarea_priv = (drm_mga_sarea_t *)
+		((u8 *)sarea_map->handle +
+		 init->sarea_priv_offset);
+
+	/* Scale primary size to the next page */
+	dev_priv->chipset = init->chipset;
+	dev_priv->frontOffset = init->frontOffset;
+	dev_priv->backOffset = init->backOffset;
+	dev_priv->depthOffset = init->depthOffset;
+	dev_priv->textureOffset = init->textureOffset;
+	dev_priv->textureSize = init->textureSize;
+	dev_priv->cpp = init->cpp;
+	dev_priv->sgram = init->sgram;
+	dev_priv->stride = init->stride;
+
+	dev_priv->mAccess = init->mAccess;
+   	init_waitqueue_head(&dev_priv->flush_queue);
+	init_waitqueue_head(&dev_priv->buf_queue);
+	dev_priv->WarpPipe = 0xff000000;
+	dev_priv->vertexsize = 0;
+
+   	DRM_DEBUG("chipset=%d ucode_size=%d backOffset=%x depthOffset=%x\n",
+		  dev_priv->chipset, dev_priv->warp_ucode_size,
+		  dev_priv->backOffset, dev_priv->depthOffset);
+   	DRM_DEBUG("cpp: %d sgram: %d stride: %d maccess: %x\n",
+		  dev_priv->cpp, dev_priv->sgram, dev_priv->stride,
+		  dev_priv->mAccess);
+
+	memcpy(&dev_priv->WarpIndex, &init->WarpIndex,
+	       sizeof(drm_mga_warp_index_t) * MGA_MAX_WARP_PIPES);
+
+   	if(mga_init_primary_bufs(dev, init) != 0) {
+		DRM_ERROR("Can not initialize primary buffers\n");
+		mga_dma_cleanup(dev);
+		return -ENOMEM;
+	}
+   	dev_priv->real_status_page = mga_alloc_page(dev);
+      	if(dev_priv->real_status_page == 0UL) {
+		mga_dma_cleanup(dev);
+		DRM_ERROR("Can not allocate status page\n");
+		return -ENOMEM;
+	}
+
+   	dev_priv->status_page =
+		ioremap_nocache(virt_to_bus((void *)dev_priv->real_status_page),
+				PAGE_SIZE);
+
+   	if(dev_priv->status_page == NULL) {
+		mga_dma_cleanup(dev);
+		DRM_ERROR("Can not remap status page\n");
+		return -ENOMEM;
+	}
+
+   	/* Write status page when secend or softrap occurs
+	 *
+	 * Disable this on ia64 on the off chance that real status page will be
+	 * above 4GB.
+	 */
+#if defined(__ia64__)
+   	MGA_WRITE(MGAREG_PRIMPTR,
+		  virt_to_bus((void *)dev_priv->real_status_page));
+#else
+   	MGA_WRITE(MGAREG_PRIMPTR,
+		  virt_to_bus((void *)dev_priv->real_status_page) | 0x00000003);
+#endif
+
+	/* Private is now filled in, initialize the hardware */
+	{
+		PRIMLOCALS;
+		PRIMGETPTR( dev_priv );
+
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DWGSYNC, 0x0100);
+		PRIMOUTREG(MGAREG_SOFTRAP, 0);
+		/* Poll for the first buffer to insure that
+		 * the status register will be correct
+		 */
+
+		mga_flush_write_combine();
+	   	MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL);
+
+		MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) |
+					   PDEA_pagpxfer_enable));
+
+	   	while(MGA_READ(MGAREG_DWGSYNC) != 0x0100) ;
+	}
+
+	if(mga_freelist_init(dev) != 0) {
+	   	DRM_ERROR("Could not initialize freelist\n");
+	   	mga_dma_cleanup(dev);
+	   	return -ENOMEM;
+	}
+	return 0;
+}
+
+int mga_dma_init(struct inode *inode, struct file *filp,
+		 unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_mga_init_t init;
+
+	if (copy_from_user(&init, (drm_mga_init_t *)arg, sizeof(init)))
+		return -EFAULT;
+
+	switch(init.func) {
+	case MGA_INIT_DMA:
+		return mga_dma_initialize(dev, &init);
+	case MGA_CLEANUP_DMA:
+		return mga_dma_cleanup(dev);
+	}
+
+	return -EINVAL;
+}
+
+int mga_irq_install(drm_device_t *dev, int irq)
+{
+	int retcode;
+
+	if (!irq)     return -EINVAL;
+
+	down(&dev->struct_sem);
+	if (dev->irq) {
+		up(&dev->struct_sem);
+		return -EBUSY;
+	}
+	dev->irq = irq;
+	up(&dev->struct_sem);
+
+	DRM_DEBUG("install irq handler %d\n", irq);
+
+	dev->context_flag     = 0;
+	dev->interrupt_flag   = 0;
+	dev->dma_flag	      = 0;
+	dev->dma->next_buffer = NULL;
+	dev->dma->next_queue  = NULL;
+	dev->dma->this_buffer = NULL;
+	INIT_LIST_HEAD(&dev->tq.list);
+	dev->tq.sync	      = 0;
+	dev->tq.routine	      = mga_dma_task_queue;
+	dev->tq.data	      = dev;
+
+				/* Before installing handler */
+	MGA_WRITE(MGAREG_IEN, 0);
+   				/* Install handler */
+	if ((retcode = request_irq(dev->irq,
+				   mga_dma_service,
+				   SA_SHIRQ,
+				   dev->devname,
+				   dev))) {
+		down(&dev->struct_sem);
+		dev->irq = 0;
+		up(&dev->struct_sem);
+		return retcode;
+	}
+				/* After installing handler */
+   	MGA_WRITE(MGAREG_ICLEAR, 0x00000001);
+	MGA_WRITE(MGAREG_IEN, 0x00000001);
+	return 0;
+}
+
+int mga_irq_uninstall(drm_device_t *dev)
+{
+	int irq;
+
+	down(&dev->struct_sem);
+	irq	 = dev->irq;
+	dev->irq = 0;
+	up(&dev->struct_sem);
+
+	if (!irq) return -EINVAL;
+   	DRM_DEBUG("remove irq handler %d\n", irq);
+      	MGA_WRITE(MGAREG_ICLEAR, 0x00000001);
+	MGA_WRITE(MGAREG_IEN, 0);
+	free_irq(irq, dev);
+	return 0;
+}
+
+int mga_control(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_control_t	ctl;
+
+	if (copy_from_user(&ctl, (drm_control_t *)arg, sizeof(ctl)))
+		return -EFAULT;
+
+	switch (ctl.func) {
+	case DRM_INST_HANDLER:
+		return mga_irq_install(dev, ctl.irq);
+	case DRM_UNINST_HANDLER:
+		return mga_irq_uninstall(dev);
+	default:
+		return -EINVAL;
+	}
+}
+
+static int mga_flush_queue(drm_device_t *dev)
+{
+   	DECLARE_WAITQUEUE(entry, current);
+  	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+   	int ret = 0;
+
+   	if(!dev_priv) return 0;
+
+   	if(dev_priv->next_prim->num_dwords != 0) {
+   		add_wait_queue(&dev_priv->flush_queue, &entry);
+		if (test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status)) 
+			DRM_ERROR("Incorrect mga_flush_queue logic\n");
+		set_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status);
+		mga_dma_schedule(dev, 0);
+   		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+	   		if (!test_bit(MGA_IN_FLUSH,
+				      &dev_priv->dispatch_status))
+				break;
+		   	atomic_inc(&dev->total_sleeps);
+	      		schedule();
+	      		if (signal_pending(current)) {
+		   		ret = -EINTR; /* Can't restart */
+				clear_bit(MGA_IN_FLUSH,
+					  &dev_priv->dispatch_status);
+		   		break;
+			}
+		}
+		current->state = TASK_RUNNING;
+   		remove_wait_queue(&dev_priv->flush_queue, &entry);
+	}
+   	return ret;
+}
+
+/* Must be called with the lock held */
+void mga_reclaim_buffers(drm_device_t *dev, pid_t pid)
+{
+	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+
+	if (!dma) return;
+      	if(dev->dev_private == NULL) return;
+	if(dma->buflist == NULL) return;
+
+	DRM_DEBUG("buf_count=%d\n", dma->buf_count);
+	
+        mga_flush_queue(dev);
+
+	for (i = 0; i < dma->buf_count; i++) {
+	   	drm_buf_t *buf = dma->buflist[ i ];
+	   	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
+
+		/* Only buffers that need to get reclaimed ever
+		 * get set to free
+		 */
+		if (buf->pid == pid  && buf_priv) {
+			if(buf_priv->my_freelist->age == MGA_BUF_USED)
+		     		buf_priv->my_freelist->age = MGA_BUF_FREE;
+		}
+	}
+}
+
+int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	DECLARE_WAITQUEUE(entry, current);
+	int		  ret	= 0;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	if (lock.context < 0) return -EINVAL;
+
+	/* Only one queue:
+	 */
+
+	if (!ret) {
+		add_wait_queue(&dev->lock.lock_queue, &entry);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!dev->lock.hw_lock) {
+				/* Device has been unregistered */
+				ret = -EINTR;
+				break;
+			}
+			if (drm_lock_take(&dev->lock.hw_lock->lock,
+					  lock.context)) {
+				dev->lock.pid	    = current->pid;
+				dev->lock.lock_time = jiffies;
+				atomic_inc(&dev->total_locks);
+				break;	/* Got lock */
+			}
+
+				/* Contention */
+			atomic_inc(&dev->total_sleeps);
+			schedule();
+			if (signal_pending(current)) {
+				ret = -ERESTARTSYS;
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&dev->lock.lock_queue, &entry);
+	}
+
+	if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+
+		if (lock.flags & _DRM_LOCK_QUIESCENT) {
+		   DRM_DEBUG("_DRM_LOCK_QUIESCENT\n");
+		   mga_flush_queue(dev);
+		   mga_dma_quiescent(dev);
+		}
+	}
+
+	if (ret) DRM_DEBUG("%d %s\n", lock.context,
+			   ret ? "interrupted" : "has lock");
+	return ret;
+}
+
+int mga_flush_ioctl(struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg)
+{
+       	drm_file_t	  *priv	  = filp->private_data;
+    	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+      	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("lock not held\n");
+		return -EINVAL;
+	}
+
+   	if(lock.flags & _DRM_LOCK_FLUSH || lock.flags & _DRM_LOCK_FLUSH_ALL) {
+		drm_mga_prim_buf_t *temp_buf;
+
+		temp_buf = dev_priv->current_prim;
+
+		if(temp_buf && temp_buf->num_dwords) {
+			set_bit(MGA_BUF_FORCE_FIRE, &temp_buf->buffer_status);
+			mga_advance_primary(dev);
+ 		}
+		mga_dma_schedule(dev, 1);
+	}
+   	if(lock.flags & _DRM_LOCK_QUIESCENT) {
+		mga_flush_queue(dev);
+		mga_dma_quiescent(dev);
+	}
+
+    	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_drm.h lia64-2.4/drivers/char/drm-4.0/mga_drm.h
--- linux-2.4.16/drivers/char/drm-4.0/mga_drm.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_drm.h	Wed Aug 15 20:52:11 2001
@@ -0,0 +1,274 @@
+/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
+ * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Jeff Hartmann <jhartmann@valinux.com>
+ *          Keith Whitwell <keithw@valinux.com>
+ *
+ */
+
+#ifndef _MGA_DRM_H_
+#define _MGA_DRM_H_
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmMga.h)
+ */
+#ifndef _MGA_DEFINES_
+#define _MGA_DEFINES_
+
+#define MGA_F  0x1		/* fog */
+#define MGA_A  0x2		/* alpha */
+#define MGA_S  0x4		/* specular */
+#define MGA_T2 0x8		/* multitexture */
+
+#define MGA_WARP_TGZ            0
+#define MGA_WARP_TGZF           (MGA_F)
+#define MGA_WARP_TGZA           (MGA_A)
+#define MGA_WARP_TGZAF          (MGA_F|MGA_A)
+#define MGA_WARP_TGZS           (MGA_S)
+#define MGA_WARP_TGZSF          (MGA_S|MGA_F)
+#define MGA_WARP_TGZSA          (MGA_S|MGA_A)
+#define MGA_WARP_TGZSAF         (MGA_S|MGA_F|MGA_A)
+#define MGA_WARP_T2GZ           (MGA_T2)
+#define MGA_WARP_T2GZF          (MGA_T2|MGA_F)
+#define MGA_WARP_T2GZA          (MGA_T2|MGA_A)
+#define MGA_WARP_T2GZAF         (MGA_T2|MGA_A|MGA_F)
+#define MGA_WARP_T2GZS          (MGA_T2|MGA_S)
+#define MGA_WARP_T2GZSF         (MGA_T2|MGA_S|MGA_F)
+#define MGA_WARP_T2GZSA         (MGA_T2|MGA_S|MGA_A)
+#define MGA_WARP_T2GZSAF        (MGA_T2|MGA_S|MGA_F|MGA_A)
+
+#define MGA_MAX_G400_PIPES 16
+#define MGA_MAX_G200_PIPES  8	/* no multitex */
+#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
+
+#define MGA_CARD_TYPE_G200 1
+#define MGA_CARD_TYPE_G400 2
+
+#define MGA_FRONT   0x1
+#define MGA_BACK    0x2
+#define MGA_DEPTH   0x4
+
+/* 3d state excluding texture units:
+ */
+#define MGA_CTXREG_DSTORG     0	/* validated */
+#define MGA_CTXREG_MACCESS    1	
+#define MGA_CTXREG_PLNWT      2 	
+#define MGA_CTXREG_DWGCTL     3	
+#define MGA_CTXREG_ALPHACTRL  4
+#define MGA_CTXREG_FOGCOLOR   5
+#define MGA_CTXREG_WFLAG      6
+#define MGA_CTXREG_TDUAL0     7
+#define MGA_CTXREG_TDUAL1     8
+#define MGA_CTXREG_FCOL       9
+#define MGA_CTXREG_STENCIL    10
+#define MGA_CTXREG_STENCILCTL 11
+#define MGA_CTX_SETUP_SIZE    12
+
+/* 2d state
+ */
+#define MGA_2DREG_PITCH 	0
+#define MGA_2D_SETUP_SIZE 	1
+
+/* Each texture unit has a state:
+ */
+#define MGA_TEXREG_CTL        0
+#define MGA_TEXREG_CTL2       1
+#define MGA_TEXREG_FILTER     2
+#define MGA_TEXREG_BORDERCOL  3
+#define MGA_TEXREG_ORG        4 /* validated */
+#define MGA_TEXREG_ORG1       5
+#define MGA_TEXREG_ORG2       6
+#define MGA_TEXREG_ORG3       7
+#define MGA_TEXREG_ORG4       8
+#define MGA_TEXREG_WIDTH      9
+#define MGA_TEXREG_HEIGHT     10
+#define MGA_TEX_SETUP_SIZE    11
+
+/* What needs to be changed for the current vertex dma buffer?
+ */
+#define MGA_UPLOAD_CTX        0x1
+#define MGA_UPLOAD_TEX0       0x2
+#define MGA_UPLOAD_TEX1       0x4
+#define MGA_UPLOAD_PIPE       0x8
+#define MGA_UPLOAD_TEX0IMAGE  0x10 /* handled client-side */
+#define MGA_UPLOAD_TEX1IMAGE  0x20 /* handled client-side */
+#define MGA_UPLOAD_2D 	      0x40
+#define MGA_WAIT_AGE          0x80 /* handled client-side */
+#define MGA_UPLOAD_CLIPRECTS  0x100 /* handled client-side */
+#define MGA_DMA_FLUSH	      0x200 /* set when someone gets the lock
+                                       quiescent */
+
+/* 32 buffers of 64k each, total 2 meg.
+ */
+#define MGA_DMA_BUF_ORDER     16
+#define MGA_DMA_BUF_SZ        (1<<MGA_DMA_BUF_ORDER)
+#define MGA_DMA_BUF_NR        31
+
+/* Keep these small for testing.
+ */
+#define MGA_NR_SAREA_CLIPRECTS 8
+
+/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
+ * regions, subject to a minimum region size of (1<<16) == 64k. 
+ *
+ * Clients may subdivide regions internally, but when sharing between
+ * clients, the region size is the minimum granularity. 
+ */
+
+#define MGA_CARD_HEAP 0
+#define MGA_AGP_HEAP  1
+#define MGA_NR_TEX_HEAPS 2
+#define MGA_NR_TEX_REGIONS 16
+#define MGA_LOG_MIN_TEX_REGION_SIZE 16
+#endif
+
+typedef struct _drm_mga_warp_index {
+   	int installed;
+   	unsigned long phys_addr;
+   	int size;
+} drm_mga_warp_index_t;
+
+typedef struct drm_mga_init {
+   	enum { 
+	   	MGA_INIT_DMA = 0x01,
+	       	MGA_CLEANUP_DMA = 0x02
+	} func;
+   	int reserved_map_agpstart;
+   	int reserved_map_idx;
+   	int buffer_map_idx;
+   	int sarea_priv_offset;
+   	int primary_size;
+   	int warp_ucode_size;
+   	unsigned int frontOffset;
+   	unsigned int backOffset;
+   	unsigned int depthOffset;
+   	unsigned int textureOffset;
+   	unsigned int textureSize;
+        unsigned int agpTextureOffset;
+        unsigned int agpTextureSize;
+   	unsigned int cpp;
+   	unsigned int stride;
+   	int sgram;
+	int chipset;
+   	drm_mga_warp_index_t WarpIndex[MGA_MAX_WARP_PIPES];
+	unsigned int mAccess;
+} drm_mga_init_t;
+
+/* Warning: if you change the sarea structure, you must change the Xserver
+ * structures as well */
+
+typedef struct _drm_mga_tex_region {
+	unsigned char next, prev;	
+	unsigned char in_use;	
+	unsigned int age;			
+} drm_mga_tex_region_t;
+
+typedef struct _drm_mga_sarea {
+	/* The channel for communication of state information to the kernel
+	 * on firing a vertex dma buffer.
+	 */
+   	unsigned int ContextState[MGA_CTX_SETUP_SIZE];
+   	unsigned int ServerState[MGA_2D_SETUP_SIZE];
+   	unsigned int TexState[2][MGA_TEX_SETUP_SIZE];
+   	unsigned int WarpPipe;
+   	unsigned int dirty;
+
+   	unsigned int nbox;
+   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
+
+
+	/* Information about the most recently used 3d drawable.  The
+	 * client fills in the req_* fields, the server fills in the 
+	 * exported_ fields and puts the cliprects into boxes, above.
+	 *
+	 * The client clears the exported_drawable field before
+	 * clobbering the boxes data.
+	 */
+        unsigned int req_drawable;	 /* the X drawable id */
+	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */
+
+        unsigned int exported_drawable;	 
+	unsigned int exported_index; 
+        unsigned int exported_stamp;	
+        unsigned int exported_buffers;	 
+        unsigned int exported_nfront;
+        unsigned int exported_nback;
+	int exported_back_x, exported_front_x, exported_w;	
+	int exported_back_y, exported_front_y, exported_h;
+   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
+   
+	/* Counters for aging textures and for client-side throttling.
+	 */
+        unsigned int last_enqueue;	/* last time a buffer was enqueued */
+	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
+	unsigned int last_quiescent;     /*  */
+
+
+	/* LRU lists for texture memory in agp space and on the card
+	 */
+	drm_mga_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
+	unsigned int texAge[MGA_NR_TEX_HEAPS];
+	
+	/* Mechanism to validate card state.
+	 */
+   	int ctxOwner;
+   	int vertexsize;
+} drm_mga_sarea_t;	
+
+/* Device specific ioctls:
+ */
+typedef struct _drm_mga_clear {
+	unsigned int clear_color;
+	unsigned int clear_depth;
+	unsigned int flags;
+	unsigned int clear_depth_mask;
+	unsigned int clear_color_mask;
+} drm_mga_clear_t;
+
+typedef struct _drm_mga_swap {
+   	int dummy;
+} drm_mga_swap_t;
+
+typedef struct _drm_mga_iload {
+	int idx;
+	int length;
+	unsigned int destOrg;
+} drm_mga_iload_t;
+
+typedef struct _drm_mga_vertex {
+   	int idx;		/* buffer to queue */
+	int used;		/* bytes in use */
+	int discard;		/* client finished with buffer?  */
+} drm_mga_vertex_t;
+
+typedef struct _drm_mga_indices {
+   	int idx;		/* buffer to queue */
+	unsigned int start;		
+	unsigned int end;		
+	int discard;		/* client finished with buffer?  */
+} drm_mga_indices_t;
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_drv.c lia64-2.4/drivers/char/drm-4.0/mga_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/mga_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,665 @@
+/* mga_drv.c -- Matrox g200/g400 driver -*- linux-c -*-
+ * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "mga_drv.h"
+
+#define MGA_NAME	 "mga"
+#define MGA_DESC	 "Matrox G200/G400"
+#define MGA_DATE	 "20000928"
+#define MGA_MAJOR	 2
+#define MGA_MINOR	 0
+#define MGA_PATCHLEVEL	 1
+
+static drm_device_t	      mga_device;
+drm_ctx_t		      mga_res_ctx;
+
+static struct file_operations mga_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 mga_open,
+	flush:	 drm_flush,
+	release: mga_release,
+	ioctl:	 mga_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+   	poll:	 drm_poll,
+};
+
+static struct miscdevice      mga_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  MGA_NAME,
+	fops:  &mga_fops,
+};
+
+static drm_ioctl_desc_t	      mga_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]     = { mga_version,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)]  = { drm_getunique,  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]   = { drm_getmagic,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]   = { drm_irq_busid,  0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)]  = { drm_setunique,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	      = { drm_block,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]     = { drm_unblock,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]     = { mga_control,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)]  = { drm_authmagic,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]     = { drm_addmap,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]    = { mga_addbufs,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]   = { mga_markbufs,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]   = { mga_infobufs,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)]    = { mga_mapbufs,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]   = { mga_freebufs,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]     = { mga_addctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]      = { mga_rmctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]     = { mga_modctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]     = { mga_getctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)]  = { mga_switchctx,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]     = { mga_newctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]     = { mga_resctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]    = { drm_adddraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]     = { drm_rmdraw,	  1, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	      = { mga_dma,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	      = { mga_lock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]      = { mga_unlock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]      = { drm_finish,	  1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]  = { drm_agp_enable,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]    = { drm_agp_info,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]   = { drm_agp_alloc,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]    = { drm_agp_free,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]    = { drm_agp_bind,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]  = { drm_agp_unbind,  1, 1 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)]    = { mga_dma_init,    1, 1 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)]    = { mga_swap_bufs,   1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)]   = { mga_clear_bufs,  1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)]   = { mga_iload,       1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)]  = { mga_vertex,      1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)]   = { mga_flush_ioctl, 1, 0 },
+   	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_indices,     1, 0 },
+};
+
+#define MGA_IOCTL_COUNT DRM_ARRAY_SIZE(mga_ioctls)
+
+#ifdef MODULE
+static char		      *mga = NULL;
+#endif
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("Matrox G200/G400");
+MODULE_PARM(mga, "s");
+
+#ifndef MODULE
+/* mga_options is called by the kernel to parse command-line options passed
+ * via the boot-loader (e.g., LILO).  It calls the insmod option routine,
+ * drm_parse_drm.
+ */
+
+static int __init mga_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("mga=", mga_options);
+#endif
+
+static int mga_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	drm_dma_setup(dev);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int mga_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	if (dev->dev_private) mga_dma_cleanup(dev);
+	if (dev->irq) mga_irq_uninstall(dev);
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+   				/* Clear AGP information */
+	if (dev->agp) {
+		drm_agp_mem_t *entry;
+		drm_agp_mem_t *nexte;
+
+				/* Remove AGP resources, but leave dev->agp
+                                   intact until cleanup is called. */
+		for (entry = dev->agp->memory; entry; entry = nexte) {
+			nexte = entry->next;
+			if (entry->bound) drm_unbind_agp(entry->memory);
+			drm_free_agp(entry->memory, entry->pages);
+			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		}
+		dev->agp->memory = NULL;
+
+		if (dev->agp->acquired)	_drm_agp_release();
+
+		dev->agp->acquired = 0;
+		dev->agp->enabled  = 0;
+	}
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	if (dev->queuelist) {
+		for (i = 0; i < dev->queue_count; i++) {
+			drm_waitlist_destroy(&dev->queuelist[i]->waitlist);
+			if (dev->queuelist[i]) {
+				drm_free(dev->queuelist[i],
+					 sizeof(*dev->queuelist[0]),
+					 DRM_MEM_QUEUES);
+				dev->queuelist[i] = NULL;
+			}
+		}
+		drm_free(dev->queuelist,
+			 dev->queue_slots * sizeof(*dev->queuelist),
+			 DRM_MEM_QUEUES);
+		dev->queuelist	 = NULL;
+	}
+
+	drm_dma_takedown(dev);
+
+	dev->queue_count     = 0;
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+/* mga_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init mga_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &mga_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(mga);
+#endif
+	if ((retcode = misc_register(&mga_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", MGA_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, mga_misc.minor);
+	dev->name   = MGA_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+	dev->agp    = drm_agp_init();
+      	if(dev->agp == NULL) {
+	   	DRM_INFO("The mga drm module requires the agpgart module"
+		         " to function correctly\nPlease load the agpgart"
+		         " module before you load the mga module\n");
+	   	drm_proc_cleanup();
+	   	misc_deregister(&mga_misc);
+	   	mga_takedown(dev);
+	   	return -ENOMEM;
+	}
+#ifdef CONFIG_MTRR
+   	dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base,
+				      dev->agp->agp_info.aper_size * 1024 * 1024,
+				      MTRR_TYPE_WRCOMB,
+				      1);
+#endif
+	if((retcode = drm_ctxbitmap_init(dev))) {
+		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+		drm_proc_cleanup();
+		misc_deregister(&mga_misc);
+		mga_takedown(dev);
+		return retcode;
+	}
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+		 MGA_NAME,
+		 MGA_MAJOR,
+		 MGA_MINOR,
+		 MGA_PATCHLEVEL,
+		 MGA_DATE,
+		 mga_misc.minor);
+
+	return 0;
+}
+
+/* mga_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit mga_cleanup(void)
+{
+	drm_device_t	      *dev = &mga_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&mga_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	drm_ctxbitmap_cleanup(dev);
+#ifdef CONFIG_MTRR
+   	if(dev->agp && dev->agp->agp_mtrr) {
+	   	int retval;
+	   	retval = mtrr_del(dev->agp->agp_mtrr,
+				  dev->agp->agp_info.aper_base,
+				  dev->agp->agp_info.aper_size * 1024*1024);
+	   	DRM_DEBUG("mtrr_del = %d\n", retval);
+	}
+#endif
+
+	mga_takedown(dev);
+	if (dev->agp) {
+		drm_agp_uninit();
+		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
+		dev->agp = NULL;
+	}
+}
+
+module_init(mga_init);
+module_exit(mga_cleanup);
+
+
+int mga_version(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)				     \
+	len = strlen(value);				     \
+	if (len > name##_len) len = name##_len;		     \
+	name##_len = strlen(value);			     \
+	if (len && name) {				     \
+		if (copy_to_user(name, value, len))	     \
+			return -EFAULT;			     \
+	}
+
+	version.version_major	   = MGA_MAJOR;
+	version.version_minor	   = MGA_MINOR;
+	version.version_patchlevel = MGA_PATCHLEVEL;
+
+	DRM_COPY(version.name, MGA_NAME);
+	DRM_COPY(version.date, MGA_DATE);
+	DRM_COPY(version.desc, MGA_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int mga_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &mga_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return mga_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+	return retcode;
+}
+
+int mga_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev    = priv->dev;
+	DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n",
+		  current->pid, dev->device, dev->open_count);
+
+	if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
+	    && dev->lock.pid == current->pid) {
+	      	mga_reclaim_buffers(dev, priv->pid);
+		DRM_INFO("Process %d dead (ctx %d, d_s = 0x%02lx)\n",
+			 current->pid,
+			 _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock),
+			 dev->dev_private ?
+			 ((drm_mga_private_t *)dev->dev_private)
+			 ->dispatch_status
+			 : 0);
+
+		if (dev->dev_private)
+			((drm_mga_private_t *)dev->dev_private)
+				->dispatch_status &= MGA_IN_DISPATCH;
+		
+		drm_lock_free(dev,
+			      &dev->lock.hw_lock->lock,
+			      _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	} else if (dev->lock.hw_lock) {
+	   	/* The lock is required to reclaim buffers */
+	   	DECLARE_WAITQUEUE(entry, current);
+	   	add_wait_queue(&dev->lock.lock_queue, &entry);
+		for (;;) {
+			current->state = TASK_INTERRUPTIBLE;
+			if (!dev->lock.hw_lock) {
+				/* Device has been unregistered */
+				retcode = -EINTR;
+				break;
+			}
+			if (drm_lock_take(&dev->lock.hw_lock->lock,
+					  DRM_KERNEL_CONTEXT)) {
+				dev->lock.pid	    = priv->pid;
+				dev->lock.lock_time = jiffies;
+				atomic_inc(&dev->total_locks);
+				break;	/* Got lock */
+			}
+				/* Contention */
+			atomic_inc(&dev->total_sleeps);
+			schedule();
+			if (signal_pending(current)) {
+				retcode = -ERESTARTSYS;
+				break;
+			}
+		}
+		current->state = TASK_RUNNING;
+		remove_wait_queue(&dev->lock.lock_queue, &entry);
+	   	if(!retcode) {
+		   	mga_reclaim_buffers(dev, priv->pid);
+			if (dev->dev_private)
+				((drm_mga_private_t *)dev->dev_private)
+					->dispatch_status &= MGA_IN_DISPATCH;
+		   	drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				      DRM_KERNEL_CONTEXT);
+		}
+	}
+	drm_fasync(-1, filp, 0);
+
+	down(&dev->struct_sem);
+	if (priv->remove_auth_on_close == 1) {
+		drm_file_t *temp = dev->file_first;
+		while(temp) {
+			temp->authenticated = 0;
+			temp = temp->next;
+		}
+	}
+	if (priv->prev) priv->prev->next = priv->next;
+	else		dev->file_first	 = priv->next;
+	if (priv->next) priv->next->prev = priv->prev;
+	else		dev->file_last	 = priv->prev;
+	up(&dev->struct_sem);
+
+	drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
+#if LINUX_VERSION_CODE < 0x020333
+	MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+   	atomic_inc(&dev->total_close);
+   	spin_lock(&dev->count_lock);
+   	if (!--dev->open_count) {
+	   	if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+		   	DRM_ERROR("Device busy: %d %d\n",
+				  atomic_read(&dev->ioctl_count),
+				  dev->blocked);
+		   	spin_unlock(&dev->count_lock);
+			unlock_kernel();
+		   	return -EBUSY;
+		}
+	   	spin_unlock(&dev->count_lock);
+		unlock_kernel();
+	   	return mga_takedown(dev);
+	}
+	spin_unlock(&dev->count_lock);
+	unlock_kernel();
+	return retcode;
+}
+
+
+/* drm_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+
+int mga_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	if (nr >= MGA_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &mga_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function: pid = %d, cmd = 0x%02x,"
+				  " nr = 0x%02x, dev 0x%x, auth = %d\n",
+				  current->pid, cmd, nr, dev->device,
+				  priv->authenticated);
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+int mga_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+	mga_dma_schedule(dev, 1);
+
+	if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+			  DRM_KERNEL_CONTEXT)) DRM_ERROR("\n");
+
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_drv.h lia64-2.4/drivers/char/drm-4.0/mga_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/mga_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_drv.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,520 @@
+/* mga_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
+ * 	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#ifndef _MGA_DRV_H_
+#define _MGA_DRV_H_
+
+#define MGA_BUF_IN_USE         0
+#define MGA_BUF_SWAP_PENDING   1
+#define MGA_BUF_FORCE_FIRE     2
+#define MGA_BUF_NEEDS_OVERFLOW 3
+
+typedef struct {
+	long buffer_status; /* long req'd for set_bit() --RR */
+   	int num_dwords;
+   	int max_dwords;
+   	u32 *current_dma_ptr;
+   	u32 *head;
+   	u32 phys_head;
+	unsigned int prim_age;
+   	int sec_used;
+   	int idx;
+} drm_mga_prim_buf_t;
+
+typedef struct _drm_mga_freelist {
+   	__volatile__ unsigned int age;
+   	drm_buf_t *buf;
+   	struct _drm_mga_freelist *next;
+   	struct _drm_mga_freelist *prev;
+} drm_mga_freelist_t;
+
+#define MGA_IN_DISPATCH   0
+#define MGA_IN_FLUSH      1
+#define MGA_IN_WAIT       2
+#define MGA_IN_GETBUF	  3
+
+typedef struct _drm_mga_private {
+   	long dispatch_status;  /* long req'd for set_bit() --RR */
+	unsigned int next_prim_age;
+	__volatile__ unsigned int last_prim_age;
+   	int reserved_map_idx;
+   	int buffer_map_idx;
+   	drm_mga_sarea_t *sarea_priv;
+   	int primary_size;
+   	int warp_ucode_size;
+   	int chipset;
+   	unsigned int frontOffset;
+   	unsigned int backOffset;
+   	unsigned int depthOffset;
+   	unsigned int textureOffset;
+   	unsigned int textureSize;
+   	int cpp;
+   	unsigned int stride;
+   	int sgram;
+	int use_agp;
+   	drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES];
+	unsigned int WarpPipe;
+	unsigned int vertexsize;
+   	atomic_t pending_bufs;
+   	void *status_page;
+   	unsigned long real_status_page;
+   	u8 *ioremap;
+   	drm_mga_prim_buf_t **prim_bufs;
+   	drm_mga_prim_buf_t *next_prim;
+   	drm_mga_prim_buf_t *last_prim;
+   	drm_mga_prim_buf_t *current_prim;
+   	int current_prim_idx;
+   	drm_mga_freelist_t *head;
+   	drm_mga_freelist_t *tail;
+   	wait_queue_head_t flush_queue;	/* Processes waiting until flush    */
+      	wait_queue_head_t wait_queue;	/* Processes waiting until interrupt */
+	wait_queue_head_t buf_queue;    /* Processes waiting for a free buf */
+	/* Some validated register values:
+	 */
+	u32 mAccess;
+} drm_mga_private_t;
+
+				/* mga_drv.c */
+extern int  mga_version(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  mga_open(struct inode *inode, struct file *filp);
+extern int  mga_release(struct inode *inode, struct file *filp);
+extern int  mga_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  mga_unlock(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+
+				/* mga_dma.c */
+extern int  mga_dma_schedule(drm_device_t *dev, int locked);
+extern int  mga_dma(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+extern int  mga_irq_install(drm_device_t *dev, int irq);
+extern int  mga_irq_uninstall(drm_device_t *dev);
+extern int  mga_control(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  mga_lock(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+
+/* mga_dma_init does init and release */
+extern int mga_dma_init(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int mga_dma_cleanup(drm_device_t *dev);
+extern int mga_flush_ioctl(struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg);
+extern unsigned int mga_create_sync_tag(drm_device_t *dev);
+extern drm_buf_t *mga_freelist_get(drm_device_t *dev);
+extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf);
+extern int mga_advance_primary(drm_device_t *dev);
+extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid);
+
+
+				/* mga_bufs.c */
+extern int  mga_addbufs(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  mga_infobufs(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+extern int  mga_markbufs(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+extern int  mga_freebufs(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+extern int  mga_mapbufs(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  mga_addmap(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+				/* mga_state.c */
+extern int  mga_clear_bufs(struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg);
+extern int  mga_swap_bufs(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  mga_iload(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+extern int  mga_vertex(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+extern int  mga_indices(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+				/* mga_context.c */
+extern int  mga_resctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  mga_addctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  mga_modctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  mga_getctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  mga_switchctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  mga_newctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  mga_rmctx(struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg);
+
+extern int  mga_context_switch(drm_device_t *dev, int old, int new);
+extern int  mga_context_switch_complete(drm_device_t *dev, int new);
+
+#define mga_flush_write_combine()	mb()
+
+typedef enum {
+	TT_GENERAL,
+	TT_BLIT,
+	TT_VECTOR,
+	TT_VERTEX
+} transferType_t;
+
+typedef struct {
+   	drm_mga_freelist_t *my_freelist;
+	int discard;
+	int dispatched;
+} drm_mga_buf_priv_t;
+
+#define DWGREG0 	0x1c00
+#define DWGREG0_END 	0x1dff
+#define DWGREG1		0x2c00
+#define DWGREG1_END	0x2dff
+
+#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
+#define ADRINDEX0(r)	(u8)((r - DWGREG0) >> 2)
+#define ADRINDEX1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
+#define ADRINDEX(r)	(ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r))
+
+#define MGA_VERBOSE 0
+#define MGA_NUM_PRIM_BUFS 	8
+
+#define PRIMLOCALS	u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \
+			int outcount, num_dwords
+
+#define PRIM_OVERFLOW(dev, dev_priv, length) do {			   \
+	drm_mga_prim_buf_t *tmp_buf =					   \
+ 		dev_priv->prim_bufs[dev_priv->current_prim_idx];	   \
+	if( test_bit(MGA_BUF_NEEDS_OVERFLOW, &tmp_buf->buffer_status)) {   \
+ 		mga_advance_primary(dev);				   \
+ 		mga_dma_schedule(dev, 1);				   \
+		tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
+ 	} else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length ||   \
+ 	           tmp_buf->sec_used > MGA_DMA_BUF_NR/2) {		   \
+		set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status);	   \
+ 		mga_advance_primary(dev);				   \
+ 		mga_dma_schedule(dev, 1);				   \
+		tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
+	}								   \
+	if(MGA_VERBOSE)							   \
+		DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__);		   \
+	dma_ptr = tmp_buf->current_dma_ptr;				   \
+	num_dwords = tmp_buf->num_dwords;				   \
+	phys_head = tmp_buf->phys_head;					   \
+	outcount = 0;							   \
+} while(0)
+
+#define PRIMGETPTR(dev_priv) do {					\
+	drm_mga_prim_buf_t *tmp_buf =					\
+		dev_priv->prim_bufs[dev_priv->current_prim_idx];	\
+	if(MGA_VERBOSE)							\
+		DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__);		\
+	dma_ptr = tmp_buf->current_dma_ptr;				\
+	num_dwords = tmp_buf->num_dwords;				\
+	phys_head = tmp_buf->phys_head;					\
+	outcount = 0;							\
+} while(0)
+
+#define PRIMPTR(prim_buf) do {					\
+	if(MGA_VERBOSE)						\
+		DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__);	\
+	dma_ptr = prim_buf->current_dma_ptr;			\
+	num_dwords = prim_buf->num_dwords;			\
+	phys_head = prim_buf->phys_head;			\
+	outcount = 0;						\
+} while(0)
+
+#define PRIMFINISH(prim_buf) do {				\
+	if (MGA_VERBOSE) {					\
+		DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__);	\
+                if (outcount & 3)				\
+                      DRM_DEBUG(" --- truncation\n");	        \
+        }							\
+	prim_buf->num_dwords = num_dwords;			\
+	prim_buf->current_dma_ptr = dma_ptr;			\
+} while(0)
+
+#define PRIMADVANCE(dev_priv)	do {				\
+drm_mga_prim_buf_t *tmp_buf = 					\
+	dev_priv->prim_bufs[dev_priv->current_prim_idx];	\
+	if (MGA_VERBOSE) {					\
+		DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__);	\
+                if (outcount & 3)				\
+                      DRM_DEBUG(" --- truncation\n");	\
+        }							\
+	tmp_buf->num_dwords = num_dwords;      			\
+	tmp_buf->current_dma_ptr = dma_ptr;    			\
+} while (0)
+
+#define PRIMUPDATE(dev_priv)	do {					\
+	drm_mga_prim_buf_t *tmp_buf =					\
+		dev_priv->prim_bufs[dev_priv->current_prim_idx];	\
+	tmp_buf->sec_used++;						\
+} while (0)
+
+#define AGEBUF(dev_priv, buf_priv)	do {				\
+	drm_mga_prim_buf_t *tmp_buf =					\
+		dev_priv->prim_bufs[dev_priv->current_prim_idx];	\
+	buf_priv->my_freelist->age = tmp_buf->prim_age;			\
+} while (0)
+
+
+#define PRIMOUTREG(reg, val) do {					\
+	tempIndex[outcount]=ADRINDEX(reg);				\
+	dma_ptr[1+outcount] = val;					\
+	if (MGA_VERBOSE)						\
+		DRM_DEBUG("   PRIMOUT %d: 0x%x -- 0x%x\n",		\
+		       num_dwords + 1 + outcount, ADRINDEX(reg), val);	\
+	if( ++outcount == 4) {						\
+		outcount = 0;						\
+		dma_ptr[0] = *(u32 *)tempIndex;				\
+		dma_ptr+=5;						\
+		num_dwords += 5;					\
+	}								\
+}while (0)
+
+/* A reduced set of the mga registers.
+ */
+
+#define MGAREG_MGA_EXEC 			0x0100
+#define MGAREG_ALPHACTRL 			0x2c7c
+#define MGAREG_AR0 				0x1c60
+#define MGAREG_AR1 				0x1c64
+#define MGAREG_AR2 				0x1c68
+#define MGAREG_AR3 				0x1c6c
+#define MGAREG_AR4 				0x1c70
+#define MGAREG_AR5 				0x1c74
+#define MGAREG_AR6 				0x1c78
+#define MGAREG_CXBNDRY				0x1c80
+#define MGAREG_CXLEFT 				0x1ca0
+#define MGAREG_CXRIGHT				0x1ca4
+#define MGAREG_DMAPAD 				0x1c54
+#define MGAREG_DSTORG 				0x2cb8
+#define MGAREG_DWGCTL 				0x1c00
+#define MGAREG_DWGSYNC				0x2c4c
+#define MGAREG_FCOL 				0x1c24
+#define MGAREG_FIFOSTATUS 			0x1e10
+#define MGAREG_FOGCOL 				0x1cf4
+#define MGAREG_FXBNDRY				0x1c84
+#define MGAREG_FXLEFT 				0x1ca8
+#define MGAREG_FXRIGHT				0x1cac
+#define MGAREG_ICLEAR 				0x1e18
+#define MGAREG_IEN 				0x1e1c
+#define MGAREG_LEN 				0x1c5c
+#define MGAREG_MACCESS				0x1c04
+#define MGAREG_PITCH 				0x1c8c
+#define MGAREG_PLNWT 				0x1c1c
+#define MGAREG_PRIMADDRESS 			0x1e58
+#define MGAREG_PRIMEND				0x1e5c
+#define MGAREG_PRIMPTR				0x1e50
+#define MGAREG_SECADDRESS 			0x2c40
+#define MGAREG_SECEND 				0x2c44
+#define MGAREG_SETUPADDRESS 			0x2cd0
+#define MGAREG_SETUPEND 			0x2cd4
+#define MGAREG_SOFTRAP				0x2c48
+#define MGAREG_SRCORG 				0x2cb4
+#define MGAREG_STATUS 				0x1e14
+#define MGAREG_STENCIL				0x2cc8
+#define MGAREG_STENCILCTL 			0x2ccc
+#define MGAREG_TDUALSTAGE0 			0x2cf8
+#define MGAREG_TDUALSTAGE1 			0x2cfc
+#define MGAREG_TEXBORDERCOL 			0x2c5c
+#define MGAREG_TEXCTL 				0x2c30
+#define MGAREG_TEXCTL2				0x2c3c
+#define MGAREG_TEXFILTER 			0x2c58
+#define MGAREG_TEXHEIGHT 			0x2c2c
+#define MGAREG_TEXORG 				0x2c24
+#define MGAREG_TEXORG1				0x2ca4
+#define MGAREG_TEXORG2				0x2ca8
+#define MGAREG_TEXORG3				0x2cac
+#define MGAREG_TEXORG4				0x2cb0
+#define MGAREG_TEXTRANS 			0x2c34
+#define MGAREG_TEXTRANSHIGH 			0x2c38
+#define MGAREG_TEXWIDTH 			0x2c28
+#define MGAREG_WACCEPTSEQ 			0x1dd4
+#define MGAREG_WCODEADDR 			0x1e6c
+#define MGAREG_WFLAG 				0x1dc4
+#define MGAREG_WFLAG1 				0x1de0
+#define MGAREG_WFLAGNB				0x1e64
+#define MGAREG_WFLAGNB1 			0x1e08
+#define MGAREG_WGETMSB				0x1dc8
+#define MGAREG_WIADDR 				0x1dc0
+#define MGAREG_WIADDR2				0x1dd8
+#define MGAREG_WMISC 				0x1e70
+#define MGAREG_WVRTXSZ				0x1dcc
+#define MGAREG_YBOT 				0x1c9c
+#define MGAREG_YDST 				0x1c90
+#define MGAREG_YDSTLEN				0x1c88
+#define MGAREG_YDSTORG				0x1c94
+#define MGAREG_YTOP 				0x1c98
+#define MGAREG_ZORG 				0x1c0c
+
+/* Warp registers */
+#define MGAREG_WR0                              0x2d00
+#define MGAREG_WR1                              0x2d04
+#define MGAREG_WR2                              0x2d08
+#define MGAREG_WR3                              0x2d0c
+#define MGAREG_WR4                              0x2d10
+#define MGAREG_WR5                              0x2d14
+#define MGAREG_WR6                              0x2d18
+#define MGAREG_WR7                              0x2d1c
+#define MGAREG_WR8                              0x2d20
+#define MGAREG_WR9                              0x2d24
+#define MGAREG_WR10                             0x2d28
+#define MGAREG_WR11                             0x2d2c
+#define MGAREG_WR12                             0x2d30
+#define MGAREG_WR13                             0x2d34
+#define MGAREG_WR14                             0x2d38
+#define MGAREG_WR15                             0x2d3c
+#define MGAREG_WR16                             0x2d40
+#define MGAREG_WR17                             0x2d44
+#define MGAREG_WR18                             0x2d48
+#define MGAREG_WR19                             0x2d4c
+#define MGAREG_WR20                             0x2d50
+#define MGAREG_WR21                             0x2d54
+#define MGAREG_WR22                             0x2d58
+#define MGAREG_WR23                             0x2d5c
+#define MGAREG_WR24                             0x2d60
+#define MGAREG_WR25                             0x2d64
+#define MGAREG_WR26                             0x2d68
+#define MGAREG_WR27                             0x2d6c
+#define MGAREG_WR28                             0x2d70
+#define MGAREG_WR29                             0x2d74
+#define MGAREG_WR30                             0x2d78
+#define MGAREG_WR31                             0x2d7c
+#define MGAREG_WR32                             0x2d80
+#define MGAREG_WR33                             0x2d84
+#define MGAREG_WR34                             0x2d88
+#define MGAREG_WR35                             0x2d8c
+#define MGAREG_WR36                             0x2d90
+#define MGAREG_WR37                             0x2d94
+#define MGAREG_WR38                             0x2d98
+#define MGAREG_WR39                             0x2d9c
+#define MGAREG_WR40                             0x2da0
+#define MGAREG_WR41                             0x2da4
+#define MGAREG_WR42                             0x2da8
+#define MGAREG_WR43                             0x2dac
+#define MGAREG_WR44                             0x2db0
+#define MGAREG_WR45                             0x2db4
+#define MGAREG_WR46                             0x2db8
+#define MGAREG_WR47                             0x2dbc
+#define MGAREG_WR48                             0x2dc0
+#define MGAREG_WR49                             0x2dc4
+#define MGAREG_WR50                             0x2dc8
+#define MGAREG_WR51                             0x2dcc
+#define MGAREG_WR52                             0x2dd0
+#define MGAREG_WR53                             0x2dd4
+#define MGAREG_WR54                             0x2dd8
+#define MGAREG_WR55                             0x2ddc
+#define MGAREG_WR56                             0x2de0
+#define MGAREG_WR57                             0x2de4
+#define MGAREG_WR58                             0x2de8
+#define MGAREG_WR59                             0x2dec
+#define MGAREG_WR60                             0x2df0
+#define MGAREG_WR61                             0x2df4
+#define MGAREG_WR62                             0x2df8
+#define MGAREG_WR63                             0x2dfc
+
+#define PDEA_pagpxfer_enable			0x2
+
+#define WIA_wmode_suspend			0x0
+#define WIA_wmode_start 			0x3
+#define WIA_wagp_agp				0x4
+
+#define DC_opcod_line_open 			0x0
+#define DC_opcod_autoline_open 			0x1
+#define DC_opcod_line_close 			0x2
+#define DC_opcod_autoline_close 		0x3
+#define DC_opcod_trap 				0x4
+#define DC_opcod_texture_trap 			0x6
+#define DC_opcod_bitblt 			0x8
+#define DC_opcod_iload 				0x9
+#define DC_atype_rpl 				0x0
+#define DC_atype_rstr 				0x10
+#define DC_atype_zi 				0x30
+#define DC_atype_blk 				0x40
+#define DC_atype_i 				0x70
+#define DC_linear_xy 				0x0
+#define DC_linear_linear 			0x80
+#define DC_zmode_nozcmp 			0x0
+#define DC_zmode_ze 				0x200
+#define DC_zmode_zne 				0x300
+#define DC_zmode_zlt 				0x400
+#define DC_zmode_zlte 				0x500
+#define DC_zmode_zgt 				0x600
+#define DC_zmode_zgte 				0x700
+#define DC_solid_disable 			0x0
+#define DC_solid_enable 			0x800
+#define DC_arzero_disable 			0x0
+#define DC_arzero_enable 			0x1000
+#define DC_sgnzero_disable 			0x0
+#define DC_sgnzero_enable 			0x2000
+#define DC_shftzero_disable 			0x0
+#define DC_shftzero_enable 			0x4000
+#define DC_bop_SHIFT 				16
+#define DC_trans_SHIFT 				20
+#define DC_bltmod_bmonolef 			0x0
+#define DC_bltmod_bmonowf 			0x8000000
+#define DC_bltmod_bplan 			0x2000000
+#define DC_bltmod_bfcol 			0x4000000
+#define DC_bltmod_bu32bgr 			0x6000000
+#define DC_bltmod_bu32rgb 			0xe000000
+#define DC_bltmod_bu24bgr 			0x16000000
+#define DC_bltmod_bu24rgb 			0x1e000000
+#define DC_pattern_disable 			0x0
+#define DC_pattern_enable 			0x20000000
+#define DC_transc_disable 			0x0
+#define DC_transc_enable 			0x40000000
+#define DC_clipdis_disable 			0x0
+#define DC_clipdis_enable 			0x80000000
+
+
+#define SETADD_mode_vertlist                   	0x0
+
+
+#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | 		\
+		       DC_sgnzero_enable | DC_shftzero_enable | 	\
+		       (0xC << DC_bop_SHIFT) | DC_clipdis_enable | 	\
+		       DC_solid_enable | DC_transc_enable)
+
+
+#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy |	\
+		      DC_solid_disable | DC_arzero_disable | 		\
+		      DC_sgnzero_enable | DC_shftzero_enable | 		\
+		      (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | 	\
+		      DC_pattern_disable | DC_transc_disable | 		\
+		      DC_clipdis_enable)				\
+
+#define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\
+		       DC_arzero_enable | DC_sgnzero_enable |		\
+		       DC_atype_i)
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/mga_state.c lia64-2.4/drivers/char/drm-4.0/mga_state.c
--- linux-2.4.16/drivers/char/drm-4.0/mga_state.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/mga_state.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,1017 @@
+/* mga_state.c -- State support for mga g200/g400 -*- linux-c -*-
+ * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Jeff Hartmann <jhartmann@valinux.com>
+ * 	    Keith Whitwell <keithw@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "mga_drv.h"
+#include "drm.h"
+
+/* If you change the functions to set state, PLEASE
+ * change these values
+ */
+
+#define MGAEMITCLIP_SIZE	10
+#define MGAEMITCTX_SIZE		20
+#define MGAG200EMITTEX_SIZE 	20
+#define MGAG400EMITTEX0_SIZE	30
+#define MGAG400EMITTEX1_SIZE	25
+#define MGAG400EMITPIPE_SIZE	50
+#define MGAG200EMITPIPE_SIZE	15
+
+#define MAX_STATE_SIZE ((MGAEMITCLIP_SIZE * MGA_NR_SAREA_CLIPRECTS) + \
+			MGAEMITCTX_SIZE + MGAG400EMITTEX0_SIZE + \
+			MGAG400EMITTEX1_SIZE + MGAG400EMITPIPE_SIZE)
+
+static void mgaEmitClipRect(drm_mga_private_t * dev_priv,
+			    drm_clip_rect_t * box)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->ContextState;
+	PRIMLOCALS;
+
+	/* This takes 10 dwords */
+	PRIMGETPTR(dev_priv);
+
+	/* Force reset of dwgctl on G400 (eliminates clip disable bit) */
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+#if 0
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DWGSYNC, 0);
+		PRIMOUTREG(MGAREG_DWGSYNC, 0);
+		PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+#else
+		PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+		PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
+		PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+		PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
+#endif
+	}
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_CXBNDRY, ((box->x2) << 16) | (box->x1));
+	PRIMOUTREG(MGAREG_YTOP, box->y1 * dev_priv->stride / dev_priv->cpp);
+	PRIMOUTREG(MGAREG_YBOT, box->y2 * dev_priv->stride / dev_priv->cpp);
+
+	PRIMADVANCE(dev_priv);
+}
+
+static void mgaEmitContext(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->ContextState;
+	PRIMLOCALS;
+
+	/* This takes a max of 20 dwords */
+	PRIMGETPTR(dev_priv);
+
+	PRIMOUTREG(MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG]);
+	PRIMOUTREG(MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS]);
+	PRIMOUTREG(MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT]);
+	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+
+	PRIMOUTREG(MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL]);
+	PRIMOUTREG(MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR]);
+	PRIMOUTREG(MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG]);
+	PRIMOUTREG(MGAREG_ZORG, dev_priv->depthOffset);	/* invarient */
+
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+		PRIMOUTREG(MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG]);
+		PRIMOUTREG(MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0]);
+		PRIMOUTREG(MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1]);
+		PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]);
+
+		PRIMOUTREG(MGAREG_STENCIL, regs[MGA_CTXREG_STENCIL]);
+		PRIMOUTREG(MGAREG_STENCILCTL, regs[MGA_CTXREG_STENCILCTL]);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+	} else {
+		PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+	}
+
+	PRIMADVANCE(dev_priv);
+}
+
+static void mgaG200EmitTex(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->TexState[0];
+	PRIMLOCALS;
+
+	PRIMGETPTR(dev_priv);
+
+	/* This takes 20 dwords */
+
+	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2]);
+	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
+	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
+	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
+
+	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
+	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
+	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
+	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);
+
+	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
+	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
+	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
+	PRIMOUTREG(MGAREG_WR24, regs[MGA_TEXREG_WIDTH]);
+
+	PRIMOUTREG(MGAREG_WR34, regs[MGA_TEXREG_HEIGHT]);
+	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
+	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+	PRIMADVANCE(dev_priv);
+}
+
+#define TMC_dualtex_enable 		0x80
+
+static void mgaG400EmitTex0(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->TexState[0];
+	PRIMLOCALS;
+
+	PRIMGETPTR(dev_priv);
+
+	/* This takes 30 dwords */
+
+	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
+	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
+	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
+	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
+
+	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
+	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
+	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
+	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);
+
+	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
+	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
+	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
+	PRIMOUTREG(MGAREG_WR49, 0);
+
+	PRIMOUTREG(MGAREG_WR57, 0);
+	PRIMOUTREG(MGAREG_WR53, 0);
+	PRIMOUTREG(MGAREG_WR61, 0);
+	PRIMOUTREG(MGAREG_WR52, 0x40);
+
+	PRIMOUTREG(MGAREG_WR60, 0x40);
+	PRIMOUTREG(MGAREG_WR54, regs[MGA_TEXREG_WIDTH] | 0x40);
+	PRIMOUTREG(MGAREG_WR62, regs[MGA_TEXREG_HEIGHT] | 0x40);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
+	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
+
+	PRIMADVANCE(dev_priv);
+}
+
+#define TMC_map1_enable 		0x80000000
+
+static void mgaG400EmitTex1(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->TexState[1];
+	PRIMLOCALS;
+
+	PRIMGETPTR(dev_priv);
+
+	/* This takes 25 dwords */
+
+	PRIMOUTREG(MGAREG_TEXCTL2,
+		   regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000);
+	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
+	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
+	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);
+
+	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
+	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
+	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
+	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);
+
+	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
+	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
+	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
+	PRIMOUTREG(MGAREG_WR49, 0);
+
+	PRIMOUTREG(MGAREG_WR57, 0);
+	PRIMOUTREG(MGAREG_WR53, 0);
+	PRIMOUTREG(MGAREG_WR61, 0);
+	PRIMOUTREG(MGAREG_WR52, regs[MGA_TEXREG_WIDTH] | 0x40);
+
+	PRIMOUTREG(MGAREG_WR60, regs[MGA_TEXREG_HEIGHT] | 0x40);
+	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
+	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
+	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
+
+	PRIMADVANCE(dev_priv);
+}
+
+#define MAGIC_FPARAM_HEX_VALUE 0x46480000
+/* This is the hex value of 12800.0f which is a magic value we must
+ * set in wr56.
+ */
+
+static void mgaG400EmitPipe(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int pipe = sarea_priv->WarpPipe;
+	PRIMLOCALS;
+
+	PRIMGETPTR(dev_priv);
+
+	/* This takes 50 dwords */
+
+	/* Establish vertex size.  
+	 */
+	PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+	if (pipe & MGA_T2) {
+		PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000);
+	} else {
+		if (dev_priv->WarpPipe & MGA_T2) {
+			/* Flush the WARP pipe */
+			PRIMOUTREG(MGAREG_YDST, 0);
+			PRIMOUTREG(MGAREG_FXLEFT, 0);
+			PRIMOUTREG(MGAREG_FXRIGHT, 1);
+			PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD);
+
+			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1);
+			PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
+			PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000);
+			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
+
+			PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000);
+			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
+			PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000);
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+		}
+
+		PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+		PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
+		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000);
+	}
+
+	PRIMOUTREG(MGAREG_WFLAG, 0);
+	PRIMOUTREG(MGAREG_WFLAG1, 0);
+	PRIMOUTREG(MGAREG_WR56, MAGIC_FPARAM_HEX_VALUE);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+
+	PRIMOUTREG(MGAREG_WR49, 0);	/* Tex stage 0 */
+	PRIMOUTREG(MGAREG_WR57, 0);	/* Tex stage 0 */
+	PRIMOUTREG(MGAREG_WR53, 0);	/* Tex stage 1 */
+	PRIMOUTREG(MGAREG_WR61, 0);	/* Tex stage 1 */
+
+	PRIMOUTREG(MGAREG_WR54, 0x40);	/* Tex stage 0 : w */
+	PRIMOUTREG(MGAREG_WR62, 0x40);	/* Tex stage 0 : h */
+	PRIMOUTREG(MGAREG_WR52, 0x40);	/* Tex stage 1 : w */
+	PRIMOUTREG(MGAREG_WR60, 0x40);	/* Tex stage 1 : h */
+
+	/* Dma pading required due to hw bug */
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_WIADDR2,
+		   (u32) (dev_priv->WarpIndex[pipe].
+			  phys_addr | WIA_wmode_start | WIA_wagp_agp));
+	PRIMADVANCE(dev_priv);
+}
+
+static void mgaG200EmitPipe(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int pipe = sarea_priv->WarpPipe;
+	PRIMLOCALS;
+
+	PRIMGETPTR(dev_priv);
+
+	/* This takes 15 dwords */
+
+	PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend);
+	PRIMOUTREG(MGAREG_WVRTXSZ, 7);
+	PRIMOUTREG(MGAREG_WFLAG, 0);
+	PRIMOUTREG(MGAREG_WR24, 0);	/* tex w/h */
+
+	PRIMOUTREG(MGAREG_WR25, 0x100);
+	PRIMOUTREG(MGAREG_WR34, 0);	/* tex w/h */
+	PRIMOUTREG(MGAREG_WR42, 0xFFFF);
+	PRIMOUTREG(MGAREG_WR60, 0xFFFF);
+
+	/* Dma pading required due to hw bug */
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
+	PRIMOUTREG(MGAREG_WIADDR,
+		   (u32) (dev_priv->WarpIndex[pipe].
+			  phys_addr | WIA_wmode_start | WIA_wagp_agp));
+
+	PRIMADVANCE( dev_priv );
+}
+
+static void mgaEmitState(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int dirty = sarea_priv->dirty;
+
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+		int multitex = sarea_priv->WarpPipe & MGA_T2;
+
+		if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
+			mgaG400EmitPipe(dev_priv);
+			dev_priv->WarpPipe = sarea_priv->WarpPipe;
+		}
+
+		if (dirty & MGA_UPLOAD_CTX) {
+			mgaEmitContext(dev_priv);
+			sarea_priv->dirty &= ~MGA_UPLOAD_CTX;
+		}
+
+		if (dirty & MGA_UPLOAD_TEX0) {
+			mgaG400EmitTex0(dev_priv);
+			sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
+		}
+
+		if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
+			mgaG400EmitTex1(dev_priv);
+			sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
+		}
+	} else {
+		if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
+			mgaG200EmitPipe(dev_priv);
+			dev_priv->WarpPipe = sarea_priv->WarpPipe;
+		}
+
+		if (dirty & MGA_UPLOAD_CTX) {
+			mgaEmitContext(dev_priv);
+			sarea_priv->dirty &= ~MGA_UPLOAD_CTX;
+		}
+
+		if (dirty & MGA_UPLOAD_TEX0) {
+			mgaG200EmitTex(dev_priv);
+			sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
+		}
+	}
+}
+
+/* Disallow all write destinations except the front and backbuffer.
+ */
+static int mgaVerifyContext(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->ContextState;
+
+	if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset &&
+	    regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) {
+		DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n",
+			  regs[MGA_CTXREG_DSTORG], dev_priv->frontOffset,
+			  dev_priv->backOffset);
+		regs[MGA_CTXREG_DSTORG] = 0;
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Disallow texture reads from PCI space.
+ */
+static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+
+	if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) {
+		DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n",
+			  sarea_priv->TexState[unit][MGA_TEXREG_ORG],
+			  unit);
+		sarea_priv->TexState[unit][MGA_TEXREG_ORG] = 0;
+		return -1;
+	}
+
+	return 0;
+}
+
+static int mgaVerifyState(drm_mga_private_t * dev_priv)
+{
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int dirty = sarea_priv->dirty;
+	int rv = 0;
+
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
+		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
+
+	if (dirty & MGA_UPLOAD_CTX)
+		rv |= mgaVerifyContext(dev_priv);
+
+	if (dirty & MGA_UPLOAD_TEX0)
+		rv |= mgaVerifyTex(dev_priv, 0);
+
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+		if (dirty & MGA_UPLOAD_TEX1)
+			rv |= mgaVerifyTex(dev_priv, 1);
+
+		if (dirty & MGA_UPLOAD_PIPE)
+			rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES);
+	} else {
+		if (dirty & MGA_UPLOAD_PIPE)
+			rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES);
+	}
+
+	return rv == 0;
+}
+
+static int mgaVerifyIload(drm_mga_private_t * dev_priv,
+			  unsigned long bus_address,
+			  unsigned int dstOrg, int length)
+{
+	if (dstOrg < dev_priv->textureOffset ||
+	    dstOrg + length >
+	    (dev_priv->textureOffset + dev_priv->textureSize)) {
+		return -EINVAL;
+	}
+	if (length % 64) {
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/* This copies a 64 byte aligned agp region to the frambuffer
+ * with a standard blit, the ioctl needs to do checking */
+
+static void mga_dma_dispatch_tex_blit(drm_device_t * dev,
+				      unsigned long bus_address,
+				      int length, unsigned int destOrg)
+{
+	drm_mga_private_t *dev_priv = dev->dev_private;
+	int use_agp = PDEA_pagpxfer_enable | 0x00000001;
+	u16 y2;
+	PRIMLOCALS;
+
+	y2 = length / 64;
+
+	PRIM_OVERFLOW(dev, dev_priv, 30);
+
+	PRIMOUTREG(MGAREG_DSTORG, destOrg);
+	PRIMOUTREG(MGAREG_MACCESS, 0x00000000);
+	PRIMOUTREG(MGAREG_SRCORG, (u32) bus_address | use_agp);
+	PRIMOUTREG(MGAREG_AR5, 64);
+
+	PRIMOUTREG(MGAREG_PITCH, 64);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD);
+
+	PRIMOUTREG(MGAREG_AR0, 63);
+	PRIMOUTREG(MGAREG_AR3, 0);
+	PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16));
+	PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, y2);
+
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_SRCORG, 0);
+	PRIMOUTREG(MGAREG_PITCH, dev_priv->stride / dev_priv->cpp);
+	PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
+	PRIMADVANCE(dev_priv);
+}
+
+static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
+{
+	drm_mga_private_t *dev_priv = dev->dev_private;
+	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned long address = (unsigned long) buf->bus_address;
+	int length = buf->used;
+	int use_agp = PDEA_pagpxfer_enable;
+	int i = 0;
+	PRIMLOCALS;
+
+	if (buf->used) {
+		/* WARNING: if you change any of the state functions verify
+		 * these numbers (Overestimating this doesn't hurt).
+		 */
+		buf_priv->dispatched = 1;
+		PRIM_OVERFLOW(dev, dev_priv,
+			      (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS)));
+		mgaEmitState(dev_priv);
+
+#if 0
+		length = dev_priv->vertexsize * 3 * 4;
+#endif
+
+		do {
+			if (i < sarea_priv->nbox) {
+				mgaEmitClipRect(dev_priv,
+						&sarea_priv->boxes[i]);
+			}
+
+			PRIMGETPTR(dev_priv);
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_SECADDRESS,
+				   ((u32) address) | TT_VERTEX);
+			PRIMOUTREG(MGAREG_SECEND,
+				   (((u32) (address + length)) | use_agp));
+			PRIMADVANCE(dev_priv);
+		} while (++i < sarea_priv->nbox);
+	}
+	if (buf_priv->discard) {
+		if (buf_priv->dispatched == 1)
+			AGEBUF(dev_priv, buf_priv);
+		buf_priv->dispatched = 0;
+		mga_freelist_put(dev, buf);
+	}
+
+
+}
+
+
+static void mga_dma_dispatch_indices(drm_device_t * dev,
+				     drm_buf_t * buf,
+				     unsigned int start, unsigned int end)
+{
+	drm_mga_private_t *dev_priv = dev->dev_private;
+	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int address = (unsigned int) buf->bus_address;
+	int use_agp = PDEA_pagpxfer_enable;
+	int i = 0;
+	PRIMLOCALS;
+
+	if (start != end) {
+		/* WARNING: if you change any of the state functions verify
+		 * these numbers (Overestimating this doesn't hurt).
+		 */
+		buf_priv->dispatched = 1;
+		PRIM_OVERFLOW(dev, dev_priv,
+			      (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS)));
+		mgaEmitState(dev_priv);
+
+		do {
+			if (i < sarea_priv->nbox) {
+				mgaEmitClipRect(dev_priv,
+						&sarea_priv->boxes[i]);
+			}
+
+			PRIMGETPTR(dev_priv);
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_SETUPADDRESS,
+				   ((address + start) |
+				    SETADD_mode_vertlist));
+			PRIMOUTREG(MGAREG_SETUPEND,
+				   ((address + end) | use_agp));
+/*  				   ((address + start + 12) | use_agp)); */
+			PRIMADVANCE(dev_priv);
+		} while (++i < sarea_priv->nbox);
+	}
+	if (buf_priv->discard) {
+		if (buf_priv->dispatched == 1)
+			AGEBUF(dev_priv, buf_priv);
+		buf_priv->dispatched = 0;
+		mga_freelist_put(dev, buf);
+	}
+}
+
+
+static void mga_dma_dispatch_clear(drm_device_t * dev, int flags,
+				   unsigned int clear_color,
+				   unsigned int clear_zval,
+				   unsigned int clear_colormask,
+				   unsigned int clear_depthmask)
+{
+	drm_mga_private_t *dev_priv = dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->ContextState;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	unsigned int cmd;
+	int i;
+	PRIMLOCALS;
+
+	if (dev_priv->sgram)
+		cmd = MGA_CLEAR_CMD | DC_atype_blk;
+	else
+		cmd = MGA_CLEAR_CMD | DC_atype_rstr;
+
+	PRIM_OVERFLOW(dev, dev_priv, 35 * MGA_NR_SAREA_CLIPRECTS);
+
+	for (i = 0; i < nbox; i++) {
+		unsigned int height = pbox[i].y2 - pbox[i].y1;
+
+		if (flags & MGA_FRONT) {
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_PLNWT, clear_colormask);
+			PRIMOUTREG(MGAREG_YDSTLEN,
+				   (pbox[i].y1 << 16) | height);
+			PRIMOUTREG(MGAREG_FXBNDRY,
+				   (pbox[i].x2 << 16) | pbox[i].x1);
+
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_FCOL, clear_color);
+			PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
+			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
+		}
+
+		if (flags & MGA_BACK) {
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_PLNWT, clear_colormask);
+			PRIMOUTREG(MGAREG_YDSTLEN,
+				   (pbox[i].y1 << 16) | height);
+			PRIMOUTREG(MGAREG_FXBNDRY,
+				   (pbox[i].x2 << 16) | pbox[i].x1);
+
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_FCOL, clear_color);
+			PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset);
+			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
+		}
+
+		if (flags & MGA_DEPTH) {
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_PLNWT, clear_depthmask);
+			PRIMOUTREG(MGAREG_YDSTLEN,
+				   (pbox[i].y1 << 16) | height);
+			PRIMOUTREG(MGAREG_FXBNDRY,
+				   (pbox[i].x2 << 16) | pbox[i].x1);
+
+			PRIMOUTREG(MGAREG_DMAPAD, 0);
+			PRIMOUTREG(MGAREG_FCOL, clear_zval);
+			PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset);
+			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
+		}
+	}
+
+	/* Force reset of DWGCTL */
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+	PRIMADVANCE(dev_priv);
+}
+
+static void mga_dma_dispatch_swap(drm_device_t * dev)
+{
+	drm_mga_private_t *dev_priv = dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int *regs = sarea_priv->ContextState;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	int i;
+	int pixel_stride = dev_priv->stride / dev_priv->cpp;
+
+	PRIMLOCALS;
+
+	PRIM_OVERFLOW(dev, dev_priv, (MGA_NR_SAREA_CLIPRECTS * 5) + 20);
+
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DWGSYNC, 0x7100);
+	PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
+
+	PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
+	PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess);
+	PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset);
+	PRIMOUTREG(MGAREG_AR5, pixel_stride);
+
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD);
+
+	for (i = 0; i < nbox; i++) {
+		unsigned int h = pbox[i].y2 - pbox[i].y1;
+		unsigned int start = pbox[i].y1 * pixel_stride;
+
+		PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1);
+		PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1);
+		PRIMOUTREG(MGAREG_FXBNDRY,
+			   pbox[i].x1 | ((pbox[i].x2 - 1) << 16));
+		PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC,
+			   (pbox[i].y1 << 16) | h);
+	}
+
+	/* Force reset of DWGCTL */
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_DMAPAD, 0);
+	PRIMOUTREG(MGAREG_SRCORG, 0);
+	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
+
+	PRIMADVANCE(dev_priv);
+}
+
+int mga_clear_bufs(struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_mga_private_t *dev_priv =
+	    (drm_mga_private_t *) dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_mga_clear_t clear;
+
+	if (copy_from_user(&clear, (drm_mga_clear_t *) arg, sizeof(clear)))
+		return -EFAULT;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_clear_bufs called without lock held\n");
+		return -EINVAL;
+	}
+
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
+		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
+
+	/* Make sure we restore the 3D state next time.
+	 */
+	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
+	mga_dma_dispatch_clear(dev, clear.flags,
+			       clear.clear_color,
+			       clear.clear_depth,
+			       clear.clear_color_mask,
+			       clear.clear_depth_mask);
+	PRIMUPDATE(dev_priv);
+	mga_flush_write_combine();
+	mga_dma_schedule(dev, 1);
+	return 0;
+}
+
+int mga_swap_bufs(struct inode *inode, struct file *filp,
+		  unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_mga_private_t *dev_priv =
+	    (drm_mga_private_t *) dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_swap_bufs called without lock held\n");
+		return -EINVAL;
+	}
+
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
+		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
+
+	/* Make sure we restore the 3D state next time.
+	 */
+	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
+	mga_dma_dispatch_swap(dev);
+	PRIMUPDATE(dev_priv);
+	set_bit(MGA_BUF_SWAP_PENDING,
+		&dev_priv->current_prim->buffer_status);
+	mga_flush_write_combine();
+	mga_dma_schedule(dev, 1);
+	return 0;
+}
+
+int mga_iload(struct inode *inode, struct file *filp,
+	      unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	drm_mga_private_t *dev_priv =
+	    (drm_mga_private_t *) dev->dev_private;
+	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_buf_t *buf;
+	drm_mga_buf_priv_t *buf_priv;
+	drm_mga_iload_t iload;
+	unsigned long bus_address;
+
+	if (copy_from_user(&iload, (drm_mga_iload_t *) arg, sizeof(iload)))
+		return -EFAULT;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_iload called without lock held\n");
+		return -EINVAL;
+	}
+
+	if(iload.idx < 0 || iload.idx > dma->buf_count) return -EINVAL;
+	buf = dma->buflist[iload.idx];
+	buf_priv = buf->dev_private;
+	bus_address = buf->bus_address;
+
+	if (mgaVerifyIload(dev_priv,
+			   bus_address, iload.destOrg, iload.length)) {
+		mga_freelist_put(dev, buf);
+		return -EINVAL;
+	}
+
+	sarea_priv->dirty |= MGA_UPLOAD_CTX;
+
+	mga_dma_dispatch_tex_blit(dev, bus_address, iload.length,
+				  iload.destOrg);
+	AGEBUF(dev_priv, buf_priv);
+	buf_priv->discard = 1;
+	mga_freelist_put(dev, buf);
+	mga_flush_write_combine();
+	mga_dma_schedule(dev, 1);
+	return 0;
+}
+
+int mga_vertex(struct inode *inode, struct file *filp,
+	       unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_mga_private_t *dev_priv =
+	    (drm_mga_private_t *) dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_mga_buf_priv_t *buf_priv;
+	drm_mga_vertex_t vertex;
+
+	if (copy_from_user(&vertex, (drm_mga_vertex_t *) arg, sizeof(vertex)))
+		return -EFAULT;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_vertex called without lock held\n");
+		return -EINVAL;
+	}
+
+	if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
+
+	buf = dma->buflist[vertex.idx];
+	buf_priv = buf->dev_private;
+
+	buf->used = vertex.used;
+	buf_priv->discard = vertex.discard;
+
+	if (!mgaVerifyState(dev_priv)) {
+		if (vertex.discard) {
+			if (buf_priv->dispatched == 1)
+				AGEBUF(dev_priv, buf_priv);
+			buf_priv->dispatched = 0;
+			mga_freelist_put(dev, buf);
+		}
+		return -EINVAL;
+	}
+
+	mga_dma_dispatch_vertex(dev, buf);
+
+	PRIMUPDATE(dev_priv);
+	mga_flush_write_combine();
+	mga_dma_schedule(dev, 1);
+	return 0;
+}
+
+
+int mga_indices(struct inode *inode, struct file *filp,
+		unsigned int cmd, unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_mga_private_t *dev_priv =
+	    (drm_mga_private_t *) dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_mga_buf_priv_t *buf_priv;
+	drm_mga_indices_t indices;
+
+	if (copy_from_user(&indices,
+			   (drm_mga_indices_t *)arg, sizeof(indices)))
+		return -EFAULT;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_indices called without lock held\n");
+		return -EINVAL;
+	}
+
+	if(indices.idx < 0 || indices.idx > dma->buf_count) return -EINVAL;
+	buf = dma->buflist[indices.idx];
+	buf_priv = buf->dev_private;
+
+	buf_priv->discard = indices.discard;
+
+	if (!mgaVerifyState(dev_priv)) {
+		if (indices.discard) {
+			if (buf_priv->dispatched == 1)
+				AGEBUF(dev_priv, buf_priv);
+			buf_priv->dispatched = 0;
+			mga_freelist_put(dev, buf);
+		}
+		return -EINVAL;
+	}
+
+	mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
+
+	PRIMUPDATE(dev_priv);
+	mga_flush_write_combine();
+	mga_dma_schedule(dev, 1);
+	return 0;
+}
+
+
+
+static int mga_dma_get_buffers(drm_device_t * dev, drm_dma_t * d)
+{
+	int i;
+	drm_buf_t *buf;
+
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = mga_freelist_get(dev);
+		if (!buf)
+			break;
+		buf->pid = current->pid;
+		if (copy_to_user(&d->request_indices[i],
+				 &buf->idx, sizeof(buf->idx)))
+			return -EFAULT;
+		if (copy_to_user(&d->request_sizes[i],
+				 &buf->total, sizeof(buf->total)))
+			return -EFAULT;
+		++d->granted_count;
+	}
+	return 0;
+}
+
+int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
+	    unsigned long arg)
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	int retcode = 0;
+	drm_dma_t d;
+
+	if (copy_from_user(&d, (drm_dma_t *) arg, sizeof(d)))
+		return -EFAULT;
+
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("mga_dma called without lock held\n");
+		return -EINVAL;
+	}
+
+	/* Please don't send us buffers.
+	 */
+	if (d.send_count != 0) {
+		DRM_ERROR
+		    ("Process %d trying to send %d buffers via drmDMA\n",
+		     current->pid, d.send_count);
+		return -EINVAL;
+	}
+
+	/* We'll send you buffers.
+	 */
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR
+		    ("Process %d trying to get %d buffers (of %d max)\n",
+		     current->pid, d.request_count, dma->buf_count);
+		return -EINVAL;
+	}
+
+	d.granted_count = 0;
+
+	if (d.request_count) {
+		retcode = mga_dma_get_buffers(dev, &d);
+	}
+
+	if (copy_to_user((drm_dma_t *) arg, &d, sizeof(d)))
+		return -EFAULT;
+	return retcode;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/proc.c lia64-2.4/drivers/char/drm-4.0/proc.c
--- linux-2.4.16/drivers/char/drm-4.0/proc.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/proc.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,578 @@
+/* proc.c -- /proc support for DRM -*- linux-c -*-
+ * Created: Mon Jan 11 09:48:47 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+
+static struct proc_dir_entry *drm_root	   = NULL;
+static struct proc_dir_entry *drm_dev_root = NULL;
+static char		     drm_slot_name[64];
+
+static int	   drm_name_info(char *buf, char **start, off_t offset,
+				 int len, int *eof, void *data);
+static int	   drm_vm_info(char *buf, char **start, off_t offset,
+			       int len, int *eof, void *data);
+static int	   drm_clients_info(char *buf, char **start, off_t offset,
+				    int len, int *eof, void *data);
+static int	   drm_queues_info(char *buf, char **start, off_t offset,
+				   int len, int *eof, void *data);
+static int	   drm_bufs_info(char *buf, char **start, off_t offset,
+				 int len, int *eof, void *data);
+#if DRM_DEBUG_CODE
+static int	   drm_vma_info(char *buf, char **start, off_t offset,
+				int len, int *eof, void *data);
+#endif
+#if DRM_DMA_HISTOGRAM
+static int	   drm_histo_info(char *buf, char **start, off_t offset,
+				  int len, int *eof, void *data);
+#endif
+
+struct drm_proc_list {
+	const char *name;
+	int	   (*f)(char *, char **, off_t, int, int *, void *);
+} drm_proc_list[] = {
+	{ "name",    drm_name_info    },
+	{ "mem",     drm_mem_info     },
+	{ "vm",	     drm_vm_info      },
+	{ "clients", drm_clients_info },
+	{ "queues",  drm_queues_info  },
+	{ "bufs",    drm_bufs_info    },
+#if DRM_DEBUG_CODE
+	{ "vma",     drm_vma_info     },
+#endif
+#if DRM_DMA_HISTOGRAM
+	{ "histo",   drm_histo_info   },
+#endif
+};
+#define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0]))
+
+int drm_proc_init(drm_device_t *dev)
+{
+	struct proc_dir_entry *ent;
+	int		      i, j;
+
+	drm_root = create_proc_entry("dri", S_IFDIR, NULL);
+	if (!drm_root) {
+		DRM_ERROR("Cannot create /proc/dri\n");
+		return -1;
+	}
+
+				/* Instead of doing this search, we should
+				   add some global support for /proc/dri. */
+	for (i = 0; i < 8; i++) {
+		sprintf(drm_slot_name, "dri/%d", i);
+		drm_dev_root = create_proc_entry(drm_slot_name, S_IFDIR, NULL);
+		if (!drm_dev_root) {
+			DRM_ERROR("Cannot create /proc/%s\n", drm_slot_name);
+			remove_proc_entry("dri", NULL);
+			break;
+		}
+		if (drm_dev_root->nlink == 2) break;
+		drm_dev_root = NULL;
+	}
+	if (!drm_dev_root) {
+		DRM_ERROR("Cannot find slot in /proc/dri\n");
+		return -1;
+	}
+
+	for (i = 0; i < DRM_PROC_ENTRIES; i++) {
+		ent = create_proc_entry(drm_proc_list[i].name,
+					S_IFREG|S_IRUGO, drm_dev_root);
+		if (!ent) {
+			DRM_ERROR("Cannot create /proc/%s/%s\n",
+				  drm_slot_name, drm_proc_list[i].name);
+			for (j = 0; j < i; j++)
+				remove_proc_entry(drm_proc_list[i].name,
+						  drm_dev_root);
+			remove_proc_entry(drm_slot_name, NULL);
+			remove_proc_entry("dri", NULL);
+			return -1;
+		}
+		ent->read_proc = drm_proc_list[i].f;
+		ent->data      = dev;
+	}
+
+	return 0;
+}
+
+
+int drm_proc_cleanup(void)
+{
+	int i;
+	
+	if (drm_root) {
+		if (drm_dev_root) {
+			for (i = 0; i < DRM_PROC_ENTRIES; i++) {
+				remove_proc_entry(drm_proc_list[i].name,
+						  drm_dev_root);
+			}
+			remove_proc_entry(drm_slot_name, NULL);
+		}
+		remove_proc_entry("dri", NULL);
+		remove_proc_entry(DRM_NAME, NULL);
+	}
+	drm_root = drm_dev_root = NULL;
+	return 0;
+}
+
+static int drm_name_info(char *buf, char **start, off_t offset, int len,
+			 int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+
+	if (dev->unique) {
+		DRM_PROC_PRINT("%s 0x%x %s\n",
+			       dev->name, dev->device, dev->unique);
+	} else {
+		DRM_PROC_PRINT("%s 0x%x\n", dev->name, dev->device);
+	}
+	return len;
+}
+
+static int _drm_vm_info(char *buf, char **start, off_t offset, int len,
+			int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	drm_map_t    *map;
+				/* Hardcoded from _DRM_FRAME_BUFFER,
+                                   _DRM_REGISTERS, _DRM_SHM, and
+                                   _DRM_AGP. */
+	const char   *types[] = { "FB", "REG", "SHM", "AGP" };
+	const char   *type;
+	int	     i;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT("slot	 offset	      size type flags	 "
+		       "address mtrr\n\n");
+	for (i = 0; i < dev->map_count; i++) {
+		map = dev->maplist[i];
+		if (map->type < 0 || map->type > 3) type = "??";
+		else				    type = types[map->type];
+		DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s  0x%02x 0x%08lx ",
+			       i,
+			       map->offset,
+			       map->size,
+			       type,
+			       map->flags,
+			       (unsigned long)map->handle);
+		if (map->mtrr < 0) {
+			DRM_PROC_PRINT("none\n");
+		} else {
+			DRM_PROC_PRINT("%4d\n", map->mtrr);
+		}
+	}
+
+	return len;
+}
+
+static int drm_vm_info(char *buf, char **start, off_t offset, int len,
+		       int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_vm_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+
+
+static int _drm_queues_info(char *buf, char **start, off_t offset, int len,
+			    int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     i;
+	drm_queue_t  *q;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT("  ctx/flags   use   fin"
+		       "   blk/rw/rwf  wait    flushed	   queued"
+		       "      locks\n\n");
+	for (i = 0; i < dev->queue_count; i++) {
+		q = dev->queuelist[i];
+		atomic_inc(&q->use_count);
+		DRM_PROC_PRINT_RET(atomic_dec(&q->use_count),
+				   "%5d/0x%03x %5d %5d"
+				   " %5d/%c%c/%c%c%c %5Zd %10d %10d %10d\n",
+				   i,
+				   q->flags,
+				   atomic_read(&q->use_count),
+				   atomic_read(&q->finalization),
+				   atomic_read(&q->block_count),
+				   atomic_read(&q->block_read) ? 'r' : '-',
+				   atomic_read(&q->block_write) ? 'w' : '-',
+				   waitqueue_active(&q->read_queue) ? 'r':'-',
+				   waitqueue_active(&q->write_queue) ? 'w':'-',
+				   waitqueue_active(&q->flush_queue) ? 'f':'-',
+				   DRM_BUFCOUNT(&q->waitlist),
+				   atomic_read(&q->total_flushed),
+				   atomic_read(&q->total_queued),
+				   atomic_read(&q->total_locks));
+		atomic_dec(&q->use_count);
+	}
+	
+	return len;
+}
+
+static int drm_queues_info(char *buf, char **start, off_t offset, int len,
+			   int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_queues_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+
+/* drm_bufs_info is called whenever a process reads
+   /dev/drm/<dev>/bufs. */
+
+static int _drm_bufs_info(char *buf, char **start, off_t offset, int len,
+			  int *eof, void *data)
+{
+	drm_device_t	 *dev = (drm_device_t *)data;
+	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+
+	if (!dma)	return 0;
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT(" o     size count  free	 segs pages    kB\n\n");
+	for (i = 0; i <= DRM_MAX_ORDER; i++) {
+		if (dma->bufs[i].buf_count)
+			DRM_PROC_PRINT("%2d %8d %5d %5d %5d %5d %5ld\n",
+				       i,
+				       dma->bufs[i].buf_size,
+				       dma->bufs[i].buf_count,
+				       atomic_read(&dma->bufs[i]
+						   .freelist.count),
+				       dma->bufs[i].seg_count,
+				       dma->bufs[i].seg_count
+				       *(1 << dma->bufs[i].page_order),
+				       (dma->bufs[i].seg_count
+					* (1 << dma->bufs[i].page_order))
+				       * PAGE_SIZE / 1024);
+	}
+	DRM_PROC_PRINT("\n");
+	for (i = 0; i < dma->buf_count; i++) {
+		if (i && !(i%32)) DRM_PROC_PRINT("\n");
+		DRM_PROC_PRINT(" %d", dma->buflist[i]->list);
+	}
+	DRM_PROC_PRINT("\n");
+
+	return len;
+}
+
+static int drm_bufs_info(char *buf, char **start, off_t offset, int len,
+			 int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_bufs_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+
+
+static int _drm_clients_info(char *buf, char **start, off_t offset, int len,
+			     int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	drm_file_t   *priv;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT("a dev	pid    uid	magic	  ioctls\n\n");
+	for (priv = dev->file_first; priv; priv = priv->next) {
+		DRM_PROC_PRINT("%c %3d %5d %5d %10u %10lu\n",
+			       priv->authenticated ? 'y' : 'n',
+			       priv->minor,
+			       priv->pid,
+			       priv->uid,
+			       priv->magic,
+			       priv->ioctl_count);
+	}
+
+	return len;
+}
+
+static int drm_clients_info(char *buf, char **start, off_t offset, int len,
+			    int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_clients_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+
+#if DRM_DEBUG_CODE
+
+#define DRM_VMA_VERBOSE 0
+
+static int _drm_vma_info(char *buf, char **start, off_t offset, int len,
+			 int *eof, void *data)
+{
+	drm_device_t	      *dev = (drm_device_t *)data;
+	drm_vma_entry_t	      *pt;
+	struct vm_area_struct *vma;
+#if DRM_VMA_VERBOSE
+	unsigned long	      i;
+	unsigned long	      address;
+	pgd_t		      *pgd;
+	pmd_t		      *pmd;
+	pte_t		      *pte;
+#endif
+#if defined(__i386__)
+	unsigned int	      pgprot;
+#endif
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+	DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n",
+		       atomic_read(&dev->vma_count),
+		       high_memory, virt_to_phys(high_memory));
+	for (pt = dev->vmalist; pt; pt = pt->next) {
+		if (!(vma = pt->vma)) continue;
+		DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx",
+			       pt->pid,
+			       vma->vm_start,
+			       vma->vm_end,
+			       vma->vm_flags & VM_READ	   ? 'r' : '-',
+			       vma->vm_flags & VM_WRITE	   ? 'w' : '-',
+			       vma->vm_flags & VM_EXEC	   ? 'x' : '-',
+			       vma->vm_flags & VM_MAYSHARE ? 's' : 'p',
+			       vma->vm_flags & VM_LOCKED   ? 'l' : '-',
+			       vma->vm_flags & VM_IO	   ? 'i' : '-',
+			       VM_OFFSET(vma));
+		
+#if defined(__i386__)
+		pgprot = pgprot_val(vma->vm_page_prot);
+		DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c",
+			       pgprot & _PAGE_PRESENT  ? 'p' : '-',
+			       pgprot & _PAGE_RW       ? 'w' : 'r',
+			       pgprot & _PAGE_USER     ? 'u' : 's',
+			       pgprot & _PAGE_PWT      ? 't' : 'b',
+			       pgprot & _PAGE_PCD      ? 'u' : 'c',
+			       pgprot & _PAGE_ACCESSED ? 'a' : '-',
+			       pgprot & _PAGE_DIRTY    ? 'd' : '-',
+			       pgprot & _PAGE_PSE      ? 'm' : 'k',
+			       pgprot & _PAGE_GLOBAL   ? 'g' : 'l' );
+#endif		
+		DRM_PROC_PRINT("\n");
+#if 0
+		for (i = vma->vm_start; i < vma->vm_end; i += PAGE_SIZE) {
+			pgd = pgd_offset(vma->vm_mm, i);
+			pmd = pmd_offset(pgd, i);
+			pte = pte_offset(pmd, i);
+			if (pte_present(*pte)) {
+				address = __pa(pte_page(*pte))
+					+ (i & (PAGE_SIZE-1));
+				DRM_PROC_PRINT("      0x%08lx -> 0x%08lx"
+					       " %c%c%c%c%c\n",
+					       i,
+					       address,
+					       pte_read(*pte)  ? 'r' : '-',
+					       pte_write(*pte) ? 'w' : '-',
+					       pte_exec(*pte)  ? 'x' : '-',
+					       pte_dirty(*pte) ? 'd' : '-',
+					       pte_young(*pte) ? 'a' : '-' );
+			} else {
+				DRM_PROC_PRINT("      0x%08lx\n", i);
+			}
+		}
+#endif
+	}
+	
+	return len;
+}
+
+static int drm_vma_info(char *buf, char **start, off_t offset, int len,
+			int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_vma_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+#endif
+
+
+#if DRM_DMA_HISTOGRAM
+static int _drm_histo_info(char *buf, char **start, off_t offset, int len,
+			   int *eof, void *data)
+{
+	drm_device_t	 *dev = (drm_device_t *)data;
+	drm_device_dma_t *dma = dev->dma;
+	int		 i;
+	unsigned long	 slot_value = DRM_DMA_HISTOGRAM_INITIAL;
+	unsigned long	 prev_value = 0;
+	drm_buf_t	 *buffer;
+
+	if (offset > 0) return 0; /* no partial requests */
+	len  = 0;
+	*eof = 1;
+
+	DRM_PROC_PRINT("general statistics:\n");
+	DRM_PROC_PRINT("total	 %10u\n", atomic_read(&dev->histo.total));
+	DRM_PROC_PRINT("open	 %10u\n", atomic_read(&dev->total_open));
+	DRM_PROC_PRINT("close	 %10u\n", atomic_read(&dev->total_close));
+	DRM_PROC_PRINT("ioctl	 %10u\n", atomic_read(&dev->total_ioctl));
+	DRM_PROC_PRINT("irq	 %10u\n", atomic_read(&dev->total_irq));
+	DRM_PROC_PRINT("ctx	 %10u\n", atomic_read(&dev->total_ctx));
+	
+	DRM_PROC_PRINT("\nlock statistics:\n");
+	DRM_PROC_PRINT("locks	 %10u\n", atomic_read(&dev->total_locks));
+	DRM_PROC_PRINT("unlocks	 %10u\n", atomic_read(&dev->total_unlocks));
+	DRM_PROC_PRINT("contends %10u\n", atomic_read(&dev->total_contends));
+	DRM_PROC_PRINT("sleeps	 %10u\n", atomic_read(&dev->total_sleeps));
+
+
+	if (dma) {
+		DRM_PROC_PRINT("\ndma statistics:\n");
+		DRM_PROC_PRINT("prio	 %10u\n",
+			       atomic_read(&dma->total_prio));
+		DRM_PROC_PRINT("bytes	 %10u\n",
+			       atomic_read(&dma->total_bytes));
+		DRM_PROC_PRINT("dmas	 %10u\n",
+			       atomic_read(&dma->total_dmas));
+		DRM_PROC_PRINT("missed:\n");
+		DRM_PROC_PRINT("  dma	 %10u\n",
+			       atomic_read(&dma->total_missed_dma));
+		DRM_PROC_PRINT("  lock	 %10u\n",
+			       atomic_read(&dma->total_missed_lock));
+		DRM_PROC_PRINT("  free	 %10u\n",
+			       atomic_read(&dma->total_missed_free));
+		DRM_PROC_PRINT("  sched	 %10u\n",
+			       atomic_read(&dma->total_missed_sched));
+		DRM_PROC_PRINT("tried	 %10u\n",
+			       atomic_read(&dma->total_tried));
+		DRM_PROC_PRINT("hit	 %10u\n",
+			       atomic_read(&dma->total_hit));
+		DRM_PROC_PRINT("lost	 %10u\n",
+			       atomic_read(&dma->total_lost));
+		
+		buffer = dma->next_buffer;
+		if (buffer) {
+			DRM_PROC_PRINT("next_buffer %7d\n", buffer->idx);
+		} else {
+			DRM_PROC_PRINT("next_buffer    none\n");
+		}
+		buffer = dma->this_buffer;
+		if (buffer) {
+			DRM_PROC_PRINT("this_buffer %7d\n", buffer->idx);
+		} else {
+			DRM_PROC_PRINT("this_buffer    none\n");
+		}
+	}
+	
+
+	DRM_PROC_PRINT("\nvalues:\n");
+	if (dev->lock.hw_lock) {
+		DRM_PROC_PRINT("lock	       0x%08x\n",
+			       dev->lock.hw_lock->lock);
+	} else {
+		DRM_PROC_PRINT("lock		     none\n");
+	}
+	DRM_PROC_PRINT("context_flag   0x%08lx\n", dev->context_flag);
+	DRM_PROC_PRINT("interrupt_flag 0x%08lx\n", dev->interrupt_flag);
+	DRM_PROC_PRINT("dma_flag       0x%08lx\n", dev->dma_flag);
+
+	DRM_PROC_PRINT("queue_count    %10d\n",	 dev->queue_count);
+	DRM_PROC_PRINT("last_context   %10d\n",	 dev->last_context);
+	DRM_PROC_PRINT("last_switch    %10lu\n", dev->last_switch);
+	DRM_PROC_PRINT("last_checked   %10d\n",	 dev->last_checked);
+		
+	
+	DRM_PROC_PRINT("\n		       q2d	  d2c	     c2f"
+		       "	q2c	   q2f	      dma	 sch"
+		       "	ctx	  lacq	     lhld\n\n");
+	for (i = 0; i < DRM_DMA_HISTOGRAM_SLOTS; i++) {
+		DRM_PROC_PRINT("%s %10lu %10u %10u %10u %10u %10u"
+			       " %10u %10u %10u %10u %10u\n",
+			       i == DRM_DMA_HISTOGRAM_SLOTS - 1 ? ">=" : "< ",
+			       i == DRM_DMA_HISTOGRAM_SLOTS - 1
+			       ? prev_value : slot_value ,
+			       
+			       atomic_read(&dev->histo
+					   .queued_to_dispatched[i]),
+			       atomic_read(&dev->histo
+					   .dispatched_to_completed[i]),
+			       atomic_read(&dev->histo
+					   .completed_to_freed[i]),
+			       
+			       atomic_read(&dev->histo
+					   .queued_to_completed[i]),
+			       atomic_read(&dev->histo
+					   .queued_to_freed[i]),
+			       atomic_read(&dev->histo.dma[i]),
+			       atomic_read(&dev->histo.schedule[i]),
+			       atomic_read(&dev->histo.ctx[i]),
+			       atomic_read(&dev->histo.lacq[i]),
+			       atomic_read(&dev->histo.lhld[i]));
+		prev_value = slot_value;
+		slot_value = DRM_DMA_HISTOGRAM_NEXT(slot_value);
+	}
+	return len;
+}
+
+static int drm_histo_info(char *buf, char **start, off_t offset, int len,
+			  int *eof, void *data)
+{
+	drm_device_t *dev = (drm_device_t *)data;
+	int	     ret;
+
+	down(&dev->struct_sem);
+	ret = _drm_histo_info(buf, start, offset, len, eof, data);
+	up(&dev->struct_sem);
+	return ret;
+}
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_bufs.c lia64-2.4/drivers/char/drm-4.0/r128_bufs.c
--- linux-2.4.16/drivers/char/drm-4.0/r128_bufs.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_bufs.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,319 @@
+/* r128_bufs.c -- IOCTLs to manage buffers -*- linux-c -*-
+ * Created: Wed Apr 12 16:19:08 2000 by kevin@precisioninsight.com
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Kevin E. Martin <martin@valinux.com>
+ *          Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include <linux/config.h>
+#include "drmP.h"
+#include "r128_drv.h"
+#include "linux/un.h"
+
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+int r128_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd,
+		     unsigned long arg)
+{
+	drm_file_t       *priv = filp->private_data;
+	drm_device_t     *dev  = priv->dev;
+	drm_device_dma_t *dma  = dev->dma;
+	drm_buf_desc_t    request;
+	drm_buf_entry_t  *entry;
+	drm_buf_t        *buf;
+	unsigned long     offset;
+	unsigned long     agp_offset;
+	int               count;
+	int               order;
+	int               size;
+	int               alignment;
+	int               page_order;
+	int               total;
+	int               byte_count;
+	int               i;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	count      = request.count;
+	order      = drm_order(request.size);
+	size       = 1 << order;
+
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total      = PAGE_SIZE << page_order;
+
+	byte_count = 0;
+	agp_offset = dev->agp->base + request.agp_start;
+
+	DRM_DEBUG("count:      %d\n",  count);
+	DRM_DEBUG("order:      %d\n",  order);
+	DRM_DEBUG("size:       %d\n",  size);
+	DRM_DEBUG("agp_offset: %ld\n", agp_offset);
+	DRM_DEBUG("alignment:  %d\n",  alignment);
+	DRM_DEBUG("page_order: %d\n",  page_order);
+	DRM_DEBUG("total:      %d\n",  total);
+
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM; /* May only call once for each order */
+	}
+
+	/* Might be a poor limit, but take that up with XFree86 
+	   if its a problem */
+	   
+	if(count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -EINVAL;
+	}
+		
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+
+	entry->buf_size   = size;
+	entry->page_order = page_order;
+	offset            = 0;
+
+	for (offset = 0;
+	     entry->buf_count < count;
+	     offset += alignment, ++entry->buf_count) {
+		buf          = &entry->buflist[entry->buf_count];
+		buf->idx     = dma->buf_count + entry->buf_count;
+		buf->total   = alignment;
+		buf->order   = order;
+		buf->used    = 0;
+		buf->offset  = (dma->byte_count + offset);
+		buf->address = (void *)(agp_offset + offset);
+		buf->next    = NULL;
+		buf->waiting = 0;
+		buf->pending = 0;
+		init_waitqueue_head(&buf->dma_wait);
+		buf->pid     = 0;
+
+		buf->dev_priv_size = sizeof(drm_r128_buf_priv_t);
+		buf->dev_private   = drm_alloc(sizeof(drm_r128_buf_priv_t),
+					       DRM_MEM_BUFS);
+		memset(buf->dev_private, 0, buf->dev_priv_size);
+
+#if DRM_DMA_HISTOGRAM
+		buf->time_queued     = 0;
+		buf->time_dispatched = 0;
+		buf->time_completed  = 0;
+		buf->time_freed      = 0;
+#endif
+
+		byte_count += PAGE_SIZE << page_order;
+
+		DRM_DEBUG("buffer %d @ %p\n",
+			  entry->buf_count, buf->address);
+	}
+
+	DRM_DEBUG("byte_count: %d\n", byte_count);
+
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+
+	dma->buf_count  += entry->buf_count;
+	dma->byte_count += byte_count;
+
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+
+	up(&dev->struct_sem);
+
+	request.count = entry->buf_count;
+	request.size  = size;
+
+	if (copy_to_user((drm_buf_desc_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+
+	dma->flags = _DRM_DMA_USE_AGP;
+
+	atomic_dec(&dev->buf_alloc);
+	return 0;
+}
+#endif
+
+int r128_addbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t		*priv		= filp->private_data;
+	drm_device_t		*dev		= priv->dev;
+	drm_r128_private_t	*dev_priv	= dev->dev_private;
+	drm_buf_desc_t		request;
+
+	if (!dev_priv || dev_priv->is_pci) return -EINVAL;
+
+	if (copy_from_user(&request,
+			   (drm_buf_desc_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	if (request.flags & _DRM_AGP_BUFFER)
+		return r128_addbufs_agp(inode, filp, cmd, arg);
+	else
+#endif
+		return -EINVAL;
+}
+
+int r128_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t		*priv		= filp->private_data;
+	drm_device_t		*dev		= priv->dev;
+	drm_r128_private_t	*dev_priv	= dev->dev_private;
+	drm_device_dma_t	*dma		= dev->dma;
+	int			 retcode	= 0;
+	const int		 zero		= 0;
+	unsigned long		 virtual;
+	unsigned long		 address;
+	drm_buf_map_t		 request;
+	int			 i;
+
+	if (!dma || !dev_priv || dev_priv->is_pci) return -EINVAL;
+
+	DRM_DEBUG("\n");
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request,
+			   (drm_buf_map_t *)arg,
+			   sizeof(request)))
+		return -EFAULT;
+
+	if (request.count >= dma->buf_count) {
+		if (dma->flags & _DRM_DMA_USE_AGP) {
+			drm_map_t *map;
+
+			map = dev_priv->buffers;
+			if (!map) {
+				retcode = -EINVAL;
+				goto done;
+			}
+
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, map->size,
+					  PROT_READ|PROT_WRITE,
+					  MAP_SHARED,
+					  (unsigned long)map->offset);
+			up_write(&current->mm->mmap_sem);
+		} else {
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, dma->byte_count,
+					  PROT_READ|PROT_WRITE, MAP_SHARED, 0);
+			up_write(&current->mm->mmap_sem);
+		}
+		if (virtual > -1024UL) {
+			/* Real error */
+			retcode = (signed long)virtual;
+			goto done;
+		}
+		request.virtual = (void *)virtual;
+
+		for (i = 0; i < dma->buf_count; i++) {
+			if (copy_to_user(&request.list[i].idx,
+					 &dma->buflist[i]->idx,
+					 sizeof(request.list[0].idx))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].total,
+					 &dma->buflist[i]->total,
+					 sizeof(request.list[0].total))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].used,
+					 &zero,
+					 sizeof(zero))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			address = virtual + dma->buflist[i]->offset;
+			if (copy_to_user(&request.list[i].address,
+					 &address,
+					 sizeof(address))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+		}
+	}
+ done:
+	request.count = dma->buf_count;
+	DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode);
+
+	if (copy_to_user((drm_buf_map_t *)arg,
+			 &request,
+			 sizeof(request)))
+		return -EFAULT;
+
+	return retcode;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_cce.c lia64-2.4/drivers/char/drm-4.0/r128_cce.c
--- linux-2.4.16/drivers/char/drm-4.0/r128_cce.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_cce.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,1305 @@
+/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
+ * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *   Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "r128_drv.h"
+
+#include <linux/interrupt.h>	/* For task queue support */
+#include <linux/delay.h>
+
+
+/* FIXME: Temporary CCE packet buffer */
+u32 r128_cce_buffer[(1 << 14)] __attribute__ ((aligned (32)));
+
+/* CCE microcode (from ATI) */
+static u32 r128_cce_microcode[] = {
+	0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
+	1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
+	599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
+	11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
+	262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
+	1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
+	30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
+	1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
+	15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
+	12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
+	46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
+	459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
+	18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
+	15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
+	268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
+	15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
+	1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
+	3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
+	1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
+	15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
+	180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
+	114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
+	33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
+	1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
+	14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
+	1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
+	198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
+	114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
+	1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
+	1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
+	16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
+	174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
+	33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
+	33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
+	409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+
+#define DO_REMAP(_m, _d) (_m)->handle = drm_ioremap((_m)->offset,           \
+							 (_m)->size, (_d))
+
+#define DO_REMAPFREE(_m, _d)                                                \
+	do {                                                                \
+		if ((_m)->handle && (_m)->size)                             \
+			drm_ioremapfree((_m)->handle, (_m)->size, (_d));    \
+	} while (0)
+
+#define DO_FIND_MAP(_m, _o)                                                 \
+	do {                                                                \
+		int _i;                                                     \
+		for (_i = 0; _i < dev->map_count; _i++) {                   \
+			if (dev->maplist[_i]->offset == _o) {               \
+				_m = dev->maplist[_i];                      \
+				break;                                      \
+			}                                                   \
+		}                                                           \
+	} while (0)
+
+
+int R128_READ_PLL(drm_device_t *dev, int addr)
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+
+	R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
+	return R128_READ(R128_CLOCK_CNTL_DATA);
+}
+
+#if 0
+static void r128_status( drm_r128_private_t *dev_priv )
+{
+	printk( "GUI_STAT           = 0x%08x\n",
+		(unsigned int)R128_READ( R128_GUI_STAT ) );
+	printk( "PM4_STAT           = 0x%08x\n",
+		(unsigned int)R128_READ( R128_PM4_STAT ) );
+	printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
+		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
+	printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
+		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
+	printk( "PM4_MICRO_CNTL     = 0x%08x\n",
+		(unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
+	printk( "PM4_BUFFER_CNTL    = 0x%08x\n",
+		(unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
+}
+#endif
+
+
+/* ================================================================
+ * Engine, FIFO control
+ */
+
+static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
+{
+	u32 tmp;
+	int i;
+
+	tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
+	R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
+			return 0;
+		}
+		udelay( 1 );
+	}
+
+	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+	return -EBUSY;
+}
+
+static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
+{
+	int i;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
+		if ( slots >= entries ) return 0;
+		udelay( 1 );
+	}
+
+	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+	return -EBUSY;
+}
+
+static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
+{
+	int i, ret;
+
+	ret = r128_do_wait_for_fifo( dev_priv, 64 );
+	if ( !ret ) return ret;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
+			r128_do_pixcache_flush( dev_priv );
+			return 0;
+		}
+		udelay( 1 );
+	}
+
+	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+	return -EBUSY;
+}
+
+
+/* ================================================================
+ * CCE control, initialization
+ */
+
+/* Load the microcode for the CCE */
+static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
+{
+	int i;
+
+	r128_do_wait_for_idle( dev_priv );
+
+	R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
+	for ( i = 0 ; i < 256 ; i++ ) {
+		R128_WRITE( R128_PM4_MICROCODE_DATAH,
+			    r128_cce_microcode[i * 2] );
+		R128_WRITE( R128_PM4_MICROCODE_DATAL,
+			    r128_cce_microcode[i * 2 + 1] );
+	}
+}
+
+/* Flush any pending commands to the CCE.  This should only be used just
+ * prior to a wait for idle, as it informs the engine that the command
+ * stream is ending.
+ */
+static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
+{
+	u32 tmp;
+
+	tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
+}
+
+/* Wait for the CCE to go idle.
+ */
+static int r128_do_cce_idle( drm_r128_private_t *dev_priv )
+{
+	int i;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+#ifndef CONFIG_AGP_I460
+		if ( *dev_priv->ring.head == dev_priv->ring.tail ) {
+#else
+		/*
+		 * XXX - this is (I think) a 460GX specific hack
+		 *
+		 * When doing texturing, ring.tail sometimes gets ahead of
+		 * PM4_BUFFER_DL_WPTR by 2; consequently, the card processes
+		 * its whole quota of instructions and *ring.head is still 2
+		 * short of ring.tail.  Work around this for now in lieu of
+		 * a better solution.
+		 */
+		if ( (*dev_priv->ring.head == dev_priv->ring.tail) ||
+			((dev_priv->ring.tail - *dev_priv->ring.head) == 2) ) {
+#endif
+			int pm4stat = R128_READ( R128_PM4_STAT );
+			if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
+			       dev_priv->cce_fifo_size ) &&
+			     !(pm4stat & (R128_PM4_BUSY |
+					  R128_PM4_GUI_ACTIVE)) ) {
+				return r128_do_pixcache_flush( dev_priv );
+			}
+		}
+		udelay( 1 );
+	}
+
+#if 0
+	DRM_ERROR( "failed!\n" );
+	r128_status( dev_priv );
+#endif
+	return -EBUSY;
+}
+
+/* Start the Concurrent Command Engine.
+ */
+static void r128_do_cce_start( drm_r128_private_t *dev_priv )
+{
+	r128_do_wait_for_idle( dev_priv );
+
+	R128_WRITE( R128_PM4_BUFFER_CNTL,
+		    dev_priv->cce_mode | dev_priv->ring.size_l2qw );
+	R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
+	R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
+
+	dev_priv->cce_running = 1;
+}
+
+/* Reset the Concurrent Command Engine.  This will not flush any pending
+ * commangs, so you must wait for the CCE command stream to complete
+ * before calling this routine.
+ */
+static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
+{
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
+	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
+	*dev_priv->ring.head = 0;
+	dev_priv->ring.tail = 0;
+}
+
+/* Stop the Concurrent Command Engine.  This will not flush any pending
+ * commangs, so you must flush the command stream and wait for the CCE
+ * to go idle before calling this routine.
+ */
+static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
+{
+	R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
+	R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
+
+	dev_priv->cce_running = 0;
+}
+
+/* Reset the engine.  This will stop the CCE if it is running.
+ */
+static int r128_do_engine_reset( drm_device_t *dev )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
+
+	r128_do_pixcache_flush( dev_priv );
+
+	clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
+	mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
+
+	R128_WRITE_PLL( R128_MCLK_CNTL,
+			mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
+
+	gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
+
+	/* Taken from the sample code - do not change */
+	R128_WRITE( R128_GEN_RESET_CNTL,
+		    gen_reset_cntl | R128_SOFT_RESET_GUI );
+	R128_READ( R128_GEN_RESET_CNTL );
+	R128_WRITE( R128_GEN_RESET_CNTL,
+		    gen_reset_cntl & ~R128_SOFT_RESET_GUI );
+	R128_READ( R128_GEN_RESET_CNTL );
+
+	R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
+	R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
+	R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
+
+	/* Reset the CCE ring */
+	r128_do_cce_reset( dev_priv );
+
+	/* The CCE is no longer running after an engine reset */
+	dev_priv->cce_running = 0;
+
+	/* Reset any pending vertex, indirect buffers */
+	r128_freelist_reset( dev );
+
+	return 0;
+}
+
+static void r128_cce_init_ring_buffer( drm_device_t *dev )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	u32 ring_start;
+	u32 tmp;
+
+	/* The manual (p. 2) says this address is in "VM space".  This
+	 * means it's an offset from the start of AGP space.
+	 */
+	ring_start = dev_priv->cce_ring->offset - dev->agp->base;
+	R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
+
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
+	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
+
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+	/*
+	 * XXX - This is a 460GX specific hack
+	 *
+	 * We have to hack this right now.  460GX isn't claiming PCI writes
+	 * from the card into the AGP aperture.  Because of this, we have
+	 * to get space outside of the aperture for RPTR_ADDR.
+	 */
+	if(dev->agp->agp_info.chipset == INTEL_460GX) {
+		dev_priv->ring.head = (void *) 
+					__get_free_page(GFP_KERNEL | GFP_DMA);
+		atomic_inc(&virt_to_page(dev_priv->ring.head)->count);
+		set_bit(PG_locked, &virt_to_page(dev_priv->ring.head)->flags);
+		dev_priv->ring.head = __va(dev_priv->ring.head);
+
+		*dev_priv->ring.head = 0;
+		R128_WRITE(R128_PM4_BUFFER_DL_RPTR_ADDR, 
+					__pa(dev_priv->ring.head));
+	} else {
+#else
+	/* DL_RPTR_ADDR is a physical address in AGP space. */
+	*dev_priv->ring.head = 0;
+	R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
+		    dev_priv->ring_rptr->offset );
+#endif
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+	}
+#endif
+
+	/* Set watermark control */
+	R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
+		    ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
+		    | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
+		    | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
+		    | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
+
+	/* Force read.  Why?  Because it's in the examples... */
+	R128_READ( R128_PM4_BUFFER_ADDR );
+
+	/* Turn on bus mastering */
+	tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
+	R128_WRITE( R128_BUS_CNTL, tmp );
+}
+
+static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
+{
+	drm_r128_private_t *dev_priv;
+        int i;
+
+	dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
+	if ( dev_priv == NULL )
+		return -ENOMEM;
+	dev->dev_private = (void *)dev_priv;
+
+	memset( dev_priv, 0, sizeof(drm_r128_private_t) );
+
+	dev_priv->is_pci = init->is_pci;
+
+	/* GH: We don't support PCI cards until PCI GART is implemented.
+	 * Fail here so we can remove all checks for PCI cards around
+	 * the CCE ring code.
+	 */
+	if ( dev_priv->is_pci ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	dev_priv->usec_timeout = init->usec_timeout;
+	if ( dev_priv->usec_timeout < 1 ||
+	     dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	dev_priv->cce_mode = init->cce_mode;
+	dev_priv->cce_secure = init->cce_secure;
+
+	/* GH: Simple idle check.
+	 */
+	atomic_set( &dev_priv->idle_count, 0 );
+
+	/* We don't support anything other than bus-mastering ring mode,
+	 * but the ring can be in either AGP or PCI space for the ring
+	 * read pointer.
+	 */
+	if ( ( init->cce_mode != R128_PM4_192BM ) &&
+	     ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
+	     ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
+	     ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	switch ( init->cce_mode ) {
+	case R128_PM4_NONPM4:
+		dev_priv->cce_fifo_size = 0;
+		break;
+	case R128_PM4_192PIO:
+	case R128_PM4_192BM:
+		dev_priv->cce_fifo_size = 192;
+		break;
+	case R128_PM4_128PIO_64INDBM:
+	case R128_PM4_128BM_64INDBM:
+		dev_priv->cce_fifo_size = 128;
+		break;
+	case R128_PM4_64PIO_128INDBM:
+	case R128_PM4_64BM_128INDBM:
+	case R128_PM4_64PIO_64VCBM_64INDBM:
+	case R128_PM4_64BM_64VCBM_64INDBM:
+	case R128_PM4_64PIO_64VCPIO_64INDPIO:
+		dev_priv->cce_fifo_size = 64;
+		break;
+	}
+
+	dev_priv->fb_bpp	= init->fb_bpp;
+	dev_priv->front_offset	= init->front_offset;
+	dev_priv->front_pitch	= init->front_pitch;
+	dev_priv->back_offset	= init->back_offset;
+	dev_priv->back_pitch	= init->back_pitch;
+
+	dev_priv->depth_bpp	= init->depth_bpp;
+	dev_priv->depth_offset	= init->depth_offset;
+	dev_priv->depth_pitch	= init->depth_pitch;
+	dev_priv->span_offset	= init->span_offset;
+
+	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
+					  (dev_priv->front_offset >> 5));
+	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
+					 (dev_priv->back_offset >> 5));
+	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
+					  (dev_priv->depth_offset >> 5) |
+					  R128_DST_TILE);
+	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
+					 (dev_priv->span_offset >> 5));
+
+	/* FIXME: We want multiple shared areas, including one shared
+	 * only by the X Server and kernel module.
+	 */
+	for ( i = 0 ; i < dev->map_count ; i++ ) {
+		if ( dev->maplist[i]->type == _DRM_SHM ) {
+			dev_priv->sarea = dev->maplist[i];
+			break;
+		}
+	}
+
+	DO_FIND_MAP( dev_priv->fb, init->fb_offset );
+	DO_FIND_MAP( dev_priv->mmio, init->mmio_offset );
+	DO_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
+	DO_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
+	DO_FIND_MAP( dev_priv->buffers, init->buffers_offset );
+
+	if ( !dev_priv->is_pci ) {
+		DO_FIND_MAP( dev_priv->agp_textures,
+			     init->agp_textures_offset );
+	}
+
+	dev_priv->sarea_priv =
+		(drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
+				     init->sarea_priv_offset);
+
+	DO_REMAP( dev_priv->cce_ring, dev );
+	DO_REMAP( dev_priv->ring_rptr, dev );
+	DO_REMAP( dev_priv->buffers, dev );
+#if 0
+	if ( !dev_priv->is_pci ) {
+		DO_REMAP( dev_priv->agp_textures, dev );
+	}
+#endif
+
+	dev_priv->ring.head = ((__volatile__ u32 *)
+			       dev_priv->ring_rptr->handle);
+
+	dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
+	dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
+			      + init->ring_size / sizeof(u32));
+	dev_priv->ring.size = init->ring_size;
+	dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
+
+	dev_priv->ring.tail_mask =
+		(dev_priv->ring.size / sizeof(u32)) - 1;
+
+	dev_priv->sarea_priv->last_frame = 0;
+	R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
+
+	dev_priv->sarea_priv->last_dispatch = 0;
+	R128_WRITE( R128_LAST_DISPATCH_REG,
+		    dev_priv->sarea_priv->last_dispatch );
+
+	r128_cce_init_ring_buffer( dev );
+	r128_cce_load_microcode( dev_priv );
+	r128_do_engine_reset( dev );
+
+	return 0;
+}
+
+static int r128_do_cleanup_cce( drm_device_t *dev )
+{
+	if ( dev->dev_private ) {
+		drm_r128_private_t *dev_priv = dev->dev_private;
+
+		DO_REMAPFREE( dev_priv->cce_ring, dev );
+		DO_REMAPFREE( dev_priv->ring_rptr, dev );
+		DO_REMAPFREE( dev_priv->buffers, dev );
+#if 0
+		if ( !dev_priv->is_pci ) {
+			DO_REMAPFREE( dev_priv->agp_textures, dev );
+		}
+#endif
+
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * Free the page we grabbed for RPTR_ADDR
+		 */
+		if(dev->agp->agp_info.chipset == INTEL_460GX) {
+			atomic_dec(&virt_to_page(dev_priv->ring.head)->count);
+			clear_bit(PG_locked, 
+				     &virt_to_page(dev_priv->ring.head)->flags);
+			wake_up(&virt_to_page(dev_priv->ring.head)->wait);
+			free_page((unsigned long) dev_priv->ring.head);
+		}
+#endif
+	
+		drm_free( dev->dev_private, sizeof(drm_r128_private_t),
+			  DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+	}
+
+	return 0;
+}
+
+int r128_cce_init( struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_init_t init;
+
+	if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) )
+		return -EFAULT;
+
+	switch ( init.func ) {
+	case R128_INIT_CCE:
+		return r128_do_init_cce( dev, &init );
+	case R128_CLEANUP_CCE:
+		return r128_do_cleanup_cce( dev );
+	}
+
+	return -EINVAL;
+}
+
+int r128_cce_start( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
+		DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
+		return 0;
+	}
+
+	r128_do_cce_start( dev_priv );
+
+	return 0;
+}
+
+/* Stop the CCE.  The engine must have been idled before calling this
+ * routine.
+ */
+int r128_cce_stop( struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_cce_stop_t stop;
+	int ret;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) )
+		return -EFAULT;
+
+	/* Flush any pending CCE commands.  This ensures any outstanding
+	 * commands are exectuted by the engine before we turn it off.
+	 */
+	if ( stop.flush ) {
+		r128_do_cce_flush( dev_priv );
+	}
+
+	/* If we fail to make the engine go idle, we return an error
+	 * code so that the DRM ioctl wrapper can try again.
+	 */
+	if ( stop.idle ) {
+		ret = r128_do_cce_idle( dev_priv );
+		if ( ret < 0 ) return ret;
+	}
+
+	/* Finally, we can turn off the CCE.  If the engine isn't idle,
+	 * we will get some dropped triangles as they won't be fully
+	 * rendered before the CCE is shut down.
+	 */
+	r128_do_cce_stop( dev_priv );
+
+	/* Reset the engine */
+	r128_do_engine_reset( dev );
+
+	return 0;
+}
+
+/* Just reset the CCE ring.  Called as part of an X Server engine reset.
+ */
+int r128_cce_reset( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv ) {
+		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	r128_do_cce_reset( dev_priv );
+
+	/* The CCE is no longer running after an engine reset */
+	dev_priv->cce_running = 0;
+
+	return 0;
+}
+
+int r128_cce_idle( struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( dev_priv->cce_running ) {
+		r128_do_cce_flush( dev_priv );
+	}
+
+	return r128_do_cce_idle( dev_priv );
+}
+
+int r128_engine_reset( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	return r128_do_engine_reset( dev );
+}
+
+
+/* ================================================================
+ * Freelist management
+ */
+#define R128_BUFFER_USED	0xffffffff
+#define R128_BUFFER_FREE	0
+
+#if 0
+static int r128_freelist_init( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_buf_t *buf;
+	drm_r128_buf_priv_t *buf_priv;
+	drm_r128_freelist_t *entry;
+	int i;
+
+	dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t),
+				    DRM_MEM_DRIVER );
+	if ( dev_priv->head == NULL )
+		return -ENOMEM;
+
+	memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
+	dev_priv->head->age = R128_BUFFER_USED;
+
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		buf = dma->buflist[i];
+		buf_priv = buf->dev_private;
+
+		entry = drm_alloc( sizeof(drm_r128_freelist_t),
+				   DRM_MEM_DRIVER );
+		if ( !entry ) return -ENOMEM;
+
+		entry->age = R128_BUFFER_FREE;
+		entry->buf = buf;
+		entry->prev = dev_priv->head;
+		entry->next = dev_priv->head->next;
+		if ( !entry->next )
+			dev_priv->tail = entry;
+
+		buf_priv->discard = 0;
+		buf_priv->dispatched = 0;
+		buf_priv->list_entry = entry;
+
+		dev_priv->head->next = entry;
+
+		if ( dev_priv->head->next )
+			dev_priv->head->next->prev = entry;
+	}
+
+	return 0;
+
+}
+#endif
+
+drm_buf_t *r128_freelist_get( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_buf_priv_t *buf_priv;
+	drm_buf_t *buf;
+	int i, t;
+
+	/* FIXME: Optimize -- use freelist code */
+
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		buf = dma->buflist[i];
+		buf_priv = buf->dev_private;
+		if ( buf->pid == 0 )
+			return buf;
+	}
+
+	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
+		u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
+
+		for ( i = 0 ; i < dma->buf_count ; i++ ) {
+			buf = dma->buflist[i];
+			buf_priv = buf->dev_private;
+			if ( buf->pending && buf_priv->age <= done_age ) {
+				/* The buffer has been processed, so it
+				 * can now be used.
+				 */
+				buf->pending = 0;
+				return buf;
+			}
+		}
+		udelay( 1 );
+	}
+
+	DRM_ERROR( "returning NULL!\n" );
+	return NULL;
+}
+
+void r128_freelist_reset( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+	int i;
+
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		drm_buf_t *buf = dma->buflist[i];
+		drm_r128_buf_priv_t *buf_priv = buf->dev_private;
+		buf_priv->age = 0;
+	}
+}
+
+
+/* ================================================================
+ * CCE packet submission
+ */
+
+int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
+{
+	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
+	int i;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		ring->space = *ring->head - ring->tail;
+		if ( ring->space <= 0 )
+			ring->space += ring->size;
+
+		if ( ring->space >= n )
+			return 0;
+
+		udelay( 1 );
+	}
+
+	return -EBUSY;
+}
+
+void r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
+{
+	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
+
+	ring->space = *ring->head - ring->tail;
+#if R128_PERFORMANCE_BOXES
+	if ( ring->space == 0 )
+		atomic_inc( &dev_priv->idle_count );
+#endif
+	if ( ring->space <= 0 )
+		ring->space += ring->size;
+}
+
+#if 0
+static int r128_verify_command( drm_r128_private_t *dev_priv,
+				u32 cmd, int *size )
+{
+	int writing = 1;
+
+	*size = 0;
+
+	switch ( cmd & R128_CCE_PACKET_MASK ) {
+	case R128_CCE_PACKET0:
+		if ( (cmd & R128_CCE_PACKET0_REG_MASK) <= (0x1004 >> 2) &&
+		     (cmd & R128_CCE_PACKET0_REG_MASK) !=
+		     (R128_PM4_VC_FPU_SETUP >> 2) ) {
+			writing = 0;
+		}
+		*size = ((cmd & R128_CCE_PACKET_COUNT_MASK) >> 16) + 2;
+		break;
+
+	case R128_CCE_PACKET1:
+		if ( (cmd & R128_CCE_PACKET1_REG0_MASK) <= (0x1004 >> 2) &&
+		     (cmd & R128_CCE_PACKET1_REG0_MASK) !=
+		     (R128_PM4_VC_FPU_SETUP >> 2) ) {
+			writing = 0;
+		}
+		if ( (cmd & R128_CCE_PACKET1_REG1_MASK) <= (0x1004 << 9) &&
+		     (cmd & R128_CCE_PACKET1_REG1_MASK) !=
+		     (R128_PM4_VC_FPU_SETUP << 9) ) {
+			writing = 0;
+		}
+		*size = 3;
+		break;
+
+	case R128_CCE_PACKET2:
+		break;
+
+	case R128_CCE_PACKET3:
+		*size = ((cmd & R128_CCE_PACKET_COUNT_MASK) >> 16) + 2;
+		break;
+
+	}
+
+	return writing;
+}
+
+static int r128_submit_packet_ring_secure( drm_r128_private_t *dev_priv,
+					   u32 *commands, int *count )
+{
+#if 0
+	int write = dev_priv->sarea_priv->ring_write;
+	int *write_ptr = dev_priv->ring_start + write;
+	int c = *count;
+	u32 tmp = 0;
+	int psize = 0;
+	int writing = 1;
+	int timeout;
+
+	while ( c > 0 ) {
+		tmp = *commands++;
+		if ( !psize ) {
+			writing = r128_verify_command( dev_priv, tmp, &psize );
+		}
+		psize--;
+
+		if ( writing ) {
+			write++;
+			*write_ptr++ = tmp;
+		}
+		if ( write >= dev_priv->ring_entries ) {
+			write = 0;
+			write_ptr = dev_priv->ring_start;
+		}
+		timeout = 0;
+		while ( write == *dev_priv->ring_read_ptr ) {
+			R128_READ( R128_PM4_BUFFER_DL_RPTR );
+			if ( timeout++ >= dev_priv->usec_timeout )
+				return -EBUSY;
+			udelay( 1 );
+		}
+		c--;
+	}
+
+	if ( write < 32 ) {
+		memcpy( dev_priv->ring_end,
+			dev_priv->ring_start,
+			write * sizeof(u32) );
+	}
+
+	/* Make sure WC cache has been flushed */
+	r128_flush_write_combine();
+
+	dev_priv->sarea_priv->ring_write = write;
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );
+
+	*count = 0;
+#endif
+	return 0;
+}
+
+static int r128_submit_packet_ring_insecure( drm_r128_private_t *dev_priv,
+					     u32 *commands, int *count )
+{
+#if 0
+	int write = dev_priv->sarea_priv->ring_write;
+	int *write_ptr = dev_priv->ring_start + write;
+	int c = *count;
+	int timeout;
+
+	while ( c > 0 ) {
+		write++;
+		*write_ptr++ = *commands++;
+		if ( write >= dev_priv->ring_entries ) {
+			write = 0;
+			write_ptr = dev_priv->ring_start;
+		}
+
+		timeout = 0;
+		while ( write == *dev_priv->ring_read_ptr ) {
+			R128_READ( R128_PM4_BUFFER_DL_RPTR );
+			if ( timeout++ >= dev_priv->usec_timeout )
+				return -EBUSY;
+			udelay( 1 );
+		}
+		c--;
+	}
+
+	if ( write < 32 ) {
+		memcpy( dev_priv->ring_end,
+			dev_priv->ring_start,
+			write * sizeof(u32) );
+	}
+
+	/* Make sure WC cache has been flushed */
+	r128_flush_write_combine();
+
+	dev_priv->sarea_priv->ring_write = write;
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );
+
+	*count = 0;
+#endif
+	return 0;
+}
+#endif
+
+/* Internal packet submission routine.  This uses the insecure versions
+ * of the packet submission functions, and thus should only be used for
+ * packets generated inside the kernel module.
+ */
+int r128_do_submit_packet( drm_r128_private_t *dev_priv,
+			   u32 *buffer, int count )
+{
+	int c = count;
+	int ret = 0;
+
+#if 0
+	int left = 0;
+
+	if ( c >= dev_priv->ring_entries ) {
+		c = dev_priv->ring_entries - 1;
+		left = count - c;
+	}
+
+	/* Since this is only used by the kernel we can use the
+	 * insecure ring buffer submit packet routine.
+	 */
+	ret = r128_submit_packet_ring_insecure( dev_priv, buffer, &c );
+	c += left;
+#endif
+
+	return ( ret < 0 ) ? ret : c;
+}
+
+/* External packet submission routine.  This uses the secure versions
+ * by default, and can thus submit packets received from user space.
+ */
+int r128_cce_packet( struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_packet_t packet;
+	u32 *buffer;
+	int c;
+	int size;
+	int ret = 0;
+
+#if 0
+	/* GH: Disable packet submission for now.
+	 */
+	return -EINVAL;
+#endif
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "r128_submit_packet called without lock held\n" );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &packet, (drm_r128_packet_t *)arg,
+			     sizeof(packet) ) )
+		return -EFAULT;
+
+#if 0
+	c = packet.count;
+	size = c * sizeof(*buffer);
+
+	{
+		int left = 0;
+
+		if ( c >= dev_priv->ring_entries ) {
+			c = dev_priv->ring_entries - 1;
+			size = c * sizeof(*buffer);
+			left = packet.count - c;
+		}
+
+		buffer = kmalloc( size, 0 );
+		if ( buffer == NULL)
+			return -ENOMEM;
+		if ( copy_from_user( buffer, packet.buffer, size ) )
+			return -EFAULT;
+
+		if ( dev_priv->cce_secure ) {
+			ret = r128_submit_packet_ring_secure( dev_priv,
+							      buffer, &c );
+		} else {
+			ret = r128_submit_packet_ring_insecure( dev_priv,
+								buffer, &c );
+		}
+		c += left;
+	}
+
+	kfree( buffer );
+#else
+	c = 0;
+#endif
+
+	packet.count = c;
+	if ( copy_to_user( (drm_r128_packet_t *)arg, &packet,
+			   sizeof(packet) ) )
+		return -EFAULT;
+
+	if ( ret ) {
+		return ret;
+	} else if ( c > 0 ) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+#if 0
+static int r128_send_vertbufs( drm_device_t *dev, drm_r128_vertex_t *v )
+{
+	drm_device_dma_t    *dma      = dev->dma;
+	drm_r128_private_t  *dev_priv = dev->dev_private;
+	drm_r128_buf_priv_t *buf_priv;
+	drm_buf_t           *buf;
+	int                  i, ret;
+	RING_LOCALS;
+
+	/* Make sure we have valid data */
+	for (i = 0; i < v->send_count; i++) {
+		int idx = v->send_indices[i];
+
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+				  idx, dma->buf_count - 1);
+			return -EINVAL;
+		}
+		buf = dma->buflist[idx];
+		if (buf->pid != current->pid) {
+			DRM_ERROR("Process %d using buffer owned by %d\n",
+				  current->pid, buf->pid);
+			return -EINVAL;
+		}
+		if (buf->pending) {
+			DRM_ERROR("Sending pending buffer:"
+				  " buffer %d, offset %d\n",
+				  v->send_indices[i], i);
+			return -EINVAL;
+		}
+	}
+
+	/* Wait for idle, if we've wrapped to make sure that all pending
+           buffers have been processed */
+	if (dev_priv->submit_age == R128_MAX_VBUF_AGE) {
+		if ((ret = r128_do_cce_idle(dev)) < 0) return ret;
+		dev_priv->submit_age = 0;
+		r128_freelist_reset(dev);
+	}
+
+	/* Make sure WC cache has been flushed (if in PIO mode) */
+	if (!dev_priv->cce_is_bm_mode) r128_flush_write_combine();
+
+	/* FIXME: Add support for sending vertex buffer to the CCE here
+	   instead of in client code.  The v->prim holds the primitive
+	   type that should be drawn.  Loop over the list buffers in
+	   send_indices[] and submit a packet for each VB.
+
+	   This will require us to loop over the clip rects here as
+	   well, which implies that we extend the kernel driver to allow
+	   cliprects to be stored here.  Note that the cliprects could
+	   possibly come from the X server instead of the client, but
+	   this will require additional changes to the DRI to allow for
+	   this optimization. */
+
+	/* Submit a CCE packet that writes submit_age to R128_VB_AGE_REG */
+#if 0
+	cce_buffer[0] = R128CCE0(R128_CCE_PACKET0, R128_VB_AGE_REG, 0);
+	cce_buffer[1] = dev_priv->submit_age;
+
+	if ((ret = r128_do_submit_packet(dev, cce_buffer, 2)) < 0) {
+		/* Until we add support for sending VBs to the CCE in
+		   this routine, we can recover from this error.  After
+		   we add that support, we won't be able to easily
+		   recover, so we will probably have to implement
+		   another mechanism for handling timeouts from packets
+		   submitted directly by the kernel. */
+		return ret;
+	}
+#else
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_VB_AGE_REG, 0 ) );
+	OUT_RING( dev_priv->submit_age );
+
+	ADVANCE_RING();
+#endif
+	/* Now that the submit packet request has succeeded, we can mark
+           the buffers as pending */
+	for (i = 0; i < v->send_count; i++) {
+		buf = dma->buflist[v->send_indices[i]];
+		buf->pending = 1;
+
+		buf_priv      = buf->dev_private;
+		buf_priv->age = dev_priv->submit_age;
+	}
+
+	dev_priv->submit_age++;
+
+	return 0;
+}
+#endif
+
+
+
+
+static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
+{
+	int i;
+	drm_buf_t *buf;
+
+	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
+		buf = r128_freelist_get( dev );
+		if ( !buf ) return -EAGAIN;
+
+		buf->pid = current->pid;
+
+		if ( copy_to_user( &d->request_indices[i], &buf->idx,
+				   sizeof(buf->idx) ) )
+			return -EFAULT;
+		if ( copy_to_user( &d->request_sizes[i], &buf->total,
+				   sizeof(buf->total) ) )
+			return -EFAULT;
+
+		d->granted_count++;
+	}
+	return 0;
+}
+
+int r128_cce_buffers( struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	int ret = 0;
+	drm_dma_t d;
+
+	if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
+		return -EFAULT;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	/* Please don't send us buffers.
+	 */
+	if ( d.send_count != 0 ) {
+		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
+			   current->pid, d.send_count );
+		return -EINVAL;
+	}
+
+	/* We'll send you buffers.
+	 */
+	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
+		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
+			   current->pid, d.request_count, dma->buf_count );
+		return -EINVAL;
+	}
+
+	d.granted_count = 0;
+
+	if ( d.request_count ) {
+		ret = r128_cce_get_buffers( dev, &d );
+	}
+
+	if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
+		return -EFAULT;
+
+	return ret;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_context.c lia64-2.4/drivers/char/drm-4.0/r128_context.c
--- linux-2.4.16/drivers/char/drm-4.0/r128_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_context.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,217 @@
+/* r128_context.c -- IOCTLs for r128 contexts -*- linux-c -*-
+ * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "r128_drv.h"
+
+extern drm_ctx_t r128_res_ctx;
+
+static int r128_alloc_queue(drm_device_t *dev)
+{
+	return drm_ctxbitmap_next(dev);
+}
+
+int r128_context_switch(drm_device_t *dev, int old, int new)
+{
+        char        buf[64];
+
+        atomic_inc(&dev->total_ctx);
+
+        if (test_and_set_bit(0, &dev->context_flag)) {
+                DRM_ERROR("Reentering -- FIXME\n");
+                return -EBUSY;
+        }
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context) {
+                clear_bit(0, &dev->context_flag);
+                return 0;
+        }
+
+        if (drm_flags & DRM_FLAG_NOCTX) {
+                r128_context_switch_complete(dev, new);
+        } else {
+                sprintf(buf, "C %d %d\n", old, new);
+                drm_write_string(dev, buf);
+        }
+
+        return 0;
+}
+
+int r128_context_switch_complete(drm_device_t *dev, int new)
+{
+        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+        dev->last_switch  = jiffies;
+
+        if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+                DRM_ERROR("Lock isn't held after context switch\n");
+        }
+
+				/* If a context switch is ever initiated
+                                   when the kernel holds the lock, release
+                                   that lock here. */
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+                                                      - dev->ctx_start)]);
+
+#endif
+        clear_bit(0, &dev->context_flag);
+        wake_up(&dev->context_wait);
+
+        return 0;
+}
+
+
+int r128_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+
+int r128_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = r128_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Skip kernel's context and get a new one. */
+		ctx.handle = r128_alloc_queue(dev);
+	}
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (ctx.handle == -1) {
+		DRM_DEBUG("Not enough free contexts.\n");
+				/* Should this return -EBUSY instead? */
+		return -ENOMEM;
+	}
+
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int r128_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	if (ctx.flags==_DRM_CONTEXT_PRESERVED)
+		r128_res_ctx.handle=ctx.handle;
+	return 0;
+}
+
+int r128_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	/* This is 0, because we don't hanlde any context flags */
+	ctx.flags = 0;
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int r128_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return r128_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int r128_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	r128_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int r128_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	drm_ctxbitmap_free(dev, ctx.handle);
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_drm.h lia64-2.4/drivers/char/drm-4.0/r128_drm.h
--- linux-2.4.16/drivers/char/drm-4.0/r128_drm.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_drm.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,272 @@
+/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
+ * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#ifndef _R128_DRM_H_
+#define _R128_DRM_H_
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the X server file (r128_sarea.h)
+ */
+#ifndef __R128_SAREA_DEFINES__
+#define __R128_SAREA_DEFINES__
+
+/* What needs to be changed for the current vertex buffer?
+ */
+#define R128_UPLOAD_CONTEXT		0x001
+#define R128_UPLOAD_SETUP		0x002
+#define R128_UPLOAD_TEX0		0x004
+#define R128_UPLOAD_TEX1		0x008
+#define R128_UPLOAD_TEX0IMAGES		0x010
+#define R128_UPLOAD_TEX1IMAGES		0x020
+#define R128_UPLOAD_CORE		0x040
+#define R128_UPLOAD_MASKS		0x080
+#define R128_UPLOAD_WINDOW		0x100
+#define R128_UPLOAD_CLIPRECTS		0x200	/* handled client-side */
+#define R128_REQUIRE_QUIESCENCE		0x400
+#define R128_UPLOAD_ALL			0x7ff
+
+#define R128_FRONT			0x1
+#define R128_BACK			0x2
+#define R128_DEPTH			0x4
+
+/* Primitive types
+ */
+#define R128_POINTS			0x1
+#define R128_LINES			0x2
+#define R128_LINE_STRIP			0x3
+#define R128_TRIANGLES			0x4
+#define R128_TRIANGLE_FAN		0x5
+#define R128_TRIANGLE_STRIP		0x6
+
+/* Vertex/indirect buffer size
+ */
+#if 1
+#define R128_BUFFER_SIZE		16384
+#else
+#define R128_BUFFER_SIZE		(128 * 1024)
+#endif
+
+/* Byte offsets for indirect buffer data
+ */
+#define R128_INDEX_PRIM_OFFSET		20
+#define R128_HOSTDATA_BLIT_OFFSET	32
+
+/* 2048x2048 @ 32bpp texture requires this many indirect buffers
+ */
+#define R128_MAX_BLIT_BUFFERS		((2048 * 2048 * 4) / R128_BUFFER_SIZE)
+
+/* Keep these small for testing.
+ */
+#define R128_NR_SAREA_CLIPRECTS		12
+
+/* There are 2 heaps (local/AGP).  Each region within a heap is a
+ *  minimum of 64k, and there are at most 64 of them per heap.
+ */
+#define R128_LOCAL_TEX_HEAP		0
+#define R128_AGP_TEX_HEAP		1
+#define R128_NR_TEX_HEAPS		2
+#define R128_NR_TEX_REGIONS		64
+#define R128_LOG_TEX_GRANULARITY	16
+
+#define R128_NR_CONTEXT_REGS		12
+#define R128_TEX_MAXLEVELS		11
+
+#endif /* __R128_SAREA_DEFINES__ */
+
+typedef struct {
+	/* Context state - can be written in one large chunk */
+	unsigned int dst_pitch_offset_c;
+	unsigned int dp_gui_master_cntl_c;
+	unsigned int sc_top_left_c;
+	unsigned int sc_bottom_right_c;
+	unsigned int z_offset_c;
+	unsigned int z_pitch_c;
+	unsigned int z_sten_cntl_c;
+	unsigned int tex_cntl_c;
+	unsigned int misc_3d_state_cntl_reg;
+	unsigned int texture_clr_cmp_clr_c;
+	unsigned int texture_clr_cmp_msk_c;
+	unsigned int fog_color_c;
+
+	/* Texture state */
+	unsigned int tex_size_pitch_c;
+	unsigned int constant_color_c;
+
+	/* Setup state */
+	unsigned int pm4_vc_fpu_setup;
+	unsigned int setup_cntl;
+
+	/* Mask state */
+	unsigned int dp_write_mask;
+	unsigned int sten_ref_mask_c;
+	unsigned int plane_3d_mask_c;
+
+	/* Window state */
+	unsigned int window_xy_offset;
+
+	/* Core state */
+	unsigned int scale_3d_cntl;
+} drm_r128_context_regs_t;
+
+/* Setup registers for each texture unit */
+typedef struct {
+	unsigned int tex_cntl;
+	unsigned int tex_combine_cntl;
+	unsigned int tex_size_pitch;
+	unsigned int tex_offset[R128_TEX_MAXLEVELS];
+	unsigned int tex_border_color;
+} drm_r128_texture_regs_t;
+
+
+typedef struct drm_tex_region {
+	unsigned char next, prev;
+	unsigned char in_use;
+	int age;
+} drm_tex_region_t;
+
+typedef struct drm_r128_sarea {
+	/* The channel for communication of state information to the kernel
+	 * on firing a vertex buffer.
+	 */
+	drm_r128_context_regs_t context_state;
+	drm_r128_texture_regs_t tex_state[R128_NR_TEX_HEAPS];
+	unsigned int dirty;
+	unsigned int vertsize;
+	unsigned int vc_format;
+
+	/* The current cliprects, or a subset thereof.
+	 */
+	drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
+	unsigned int nbox;
+
+	/* Counters for client-side throttling of rendering clients.
+	 */
+	unsigned int last_frame;
+	unsigned int last_dispatch;
+
+	drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
+	int tex_age[R128_NR_TEX_HEAPS];
+	int ctx_owner;
+} drm_r128_sarea_t;
+
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmR128.h)
+ */
+typedef struct drm_r128_init {
+	enum {
+		R128_INIT_CCE    = 0x01,
+		R128_CLEANUP_CCE = 0x02
+	} func;
+	int sarea_priv_offset;
+	int is_pci;
+	int cce_mode;
+	int cce_secure;
+	int ring_size;
+	int usec_timeout;
+
+	unsigned int fb_bpp;
+	unsigned int front_offset, front_pitch;
+	unsigned int back_offset, back_pitch;
+	unsigned int depth_bpp;
+	unsigned int depth_offset, depth_pitch;
+	unsigned int span_offset;
+
+	unsigned int fb_offset;
+	unsigned int mmio_offset;
+	unsigned int ring_offset;
+	unsigned int ring_rptr_offset;
+	unsigned int buffers_offset;
+	unsigned int agp_textures_offset;
+} drm_r128_init_t;
+
+typedef struct drm_r128_cce_stop {
+	int flush;
+	int idle;
+} drm_r128_cce_stop_t;
+
+typedef struct drm_r128_clear {
+	unsigned int flags;
+	int x, y, w, h;
+	unsigned int clear_color;
+	unsigned int clear_depth;
+} drm_r128_clear_t;
+
+typedef struct drm_r128_vertex {
+	int prim;
+	int idx;			/* Index of vertex buffer */
+	int count;			/* Number of vertices in buffer */
+	int discard;			/* Client finished with buffer? */
+} drm_r128_vertex_t;
+
+typedef struct drm_r128_indices {
+	int prim;
+	int idx;
+	int start;
+	int end;
+	int discard;			/* Client finished with buffer? */
+} drm_r128_indices_t;
+
+typedef struct drm_r128_blit {
+	int idx;
+	int pitch;
+	int offset;
+	int format;
+	unsigned short x, y;
+	unsigned short width, height;
+} drm_r128_blit_t;
+
+typedef struct drm_r128_depth {
+	enum {
+		R128_WRITE_SPAN		= 0x01,
+		R128_WRITE_PIXELS	= 0x02,
+		R128_READ_SPAN		= 0x03,
+		R128_READ_PIXELS	= 0x04
+	} func;
+	int n;
+	int *x;
+	int *y;
+	unsigned int *buffer;
+	unsigned char *mask;
+} drm_r128_depth_t;
+
+typedef struct drm_r128_stipple {
+	unsigned int *mask;
+} drm_r128_stipple_t;
+
+typedef struct drm_r128_packet {
+	unsigned int *buffer;
+	int count;
+	int flags;
+} drm_r128_packet_t;
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_drv.c lia64-2.4/drivers/char/drm-4.0/r128_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/r128_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,699 @@
+/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*-
+ * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "r128_drv.h"
+
+#define R128_NAME		"r128"
+#define R128_DESC		"ATI Rage 128"
+#define R128_DATE		"20001215"
+#define R128_MAJOR		2
+#define R128_MINOR		1
+#define R128_PATCHLEVEL		2
+
+static drm_device_t	r128_device;
+drm_ctx_t		r128_res_ctx;
+
+static struct file_operations r128_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 r128_open,
+	flush:	 drm_flush,
+	release: r128_release,
+	ioctl:	 r128_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+	poll:	 drm_poll,
+};
+
+static struct miscdevice      r128_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  R128_NAME,
+	fops:  &r128_fops,
+};
+
+static drm_ioctl_desc_t	      r128_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]      = { r128_version,      0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)]   = { drm_getunique,     0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]    = { drm_getmagic,      0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]    = { drm_irq_busid,     0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)]   = { drm_setunique,     1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	       = { drm_block,         1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]      = { drm_unblock,       1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)]   = { drm_authmagic,     1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]      = { drm_addmap,        1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]     = { r128_addbufs,      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]    = { drm_markbufs,      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]    = { drm_infobufs,      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)]     = { r128_mapbufs,      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]    = { drm_freebufs,      1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]      = { r128_addctx,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]       = { r128_rmctx,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]      = { r128_modctx,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]      = { r128_getctx,	      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)]   = { r128_switchctx,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]      = { r128_newctx,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]      = { r128_resctx,	      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]     = { drm_adddraw,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]      = { drm_rmdraw,	      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	       = { r128_cce_buffers,  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	       = { r128_lock,	      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]       = { r128_unlock,	      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]       = { drm_finish,	      1, 0 },
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)]  = { drm_agp_acquire,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)]  = { drm_agp_release,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]   = { drm_agp_enable,    1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]     = { drm_agp_info,      1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]    = { drm_agp_alloc,     1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]     = { drm_agp_free,      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]     = { drm_agp_bind,      1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]   = { drm_agp_unbind,    1, 1 },
+#endif
+
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)]    = { r128_cce_init,     1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)]  = { r128_cce_stop,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)]  = { r128_cce_idle,   1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)]   = { r128_engine_reset, 1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)]    = { r128_cce_swap,     1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)]   = { r128_cce_clear,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)]  = { r128_cce_vertex,   1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices,  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)]    = { r128_cce_blit,     1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)]   = { r128_cce_depth,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple,  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)]  = { r128_cce_packet,   1, 0 },
+};
+#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls)
+
+#ifdef MODULE
+static char		      *r128 = NULL;
+#endif
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("r128");
+MODULE_PARM(r128, "s");
+
+#ifndef MODULE
+/* r128_options is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+
+static int __init r128_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("r128=", r128_options);
+#endif
+
+static int r128_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	drm_dma_setup(dev);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	r128_res_ctx.handle=-1;
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int r128_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+				/* Clear AGP information */
+	if (dev->agp) {
+		drm_agp_mem_t *entry;
+		drm_agp_mem_t *nexte;
+
+				/* Remove AGP resources, but leave dev->agp
+                                   intact until r128_cleanup is called. */
+		for (entry = dev->agp->memory; entry; entry = nexte) {
+			nexte = entry->next;
+			if (entry->bound) drm_unbind_agp(entry->memory);
+			drm_free_agp(entry->memory, entry->pages);
+			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		}
+		dev->agp->memory = NULL;
+
+		if (dev->agp->acquired)	_drm_agp_release();
+
+		dev->agp->acquired = 0;
+		dev->agp->enabled  = 0;
+	}
+#endif
+
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				/* Do nothing here, because this is all
+                                   handled in the AGP/GART driver. */
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	drm_dma_takedown(dev);
+
+	dev->queue_count     = 0;
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+/* r128_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init r128_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &r128_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(r128);
+#endif
+
+	if ((retcode = misc_register(&r128_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", R128_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, r128_misc.minor);
+	dev->name   = R128_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	dev->agp    = drm_agp_init();
+	if (dev->agp == NULL) {
+		DRM_ERROR("Cannot initialize agpgart module.\n");
+		drm_proc_cleanup();
+		misc_deregister(&r128_misc);
+		r128_takedown(dev);
+		return -ENOMEM;
+	}
+
+#ifdef CONFIG_MTRR
+	dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base,
+				      dev->agp->agp_info.aper_size*1024*1024,
+				      MTRR_TYPE_WRCOMB,
+				      1);
+#endif
+#endif
+
+	if((retcode = drm_ctxbitmap_init(dev))) {
+		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+		drm_proc_cleanup();
+		misc_deregister(&r128_misc);
+		r128_takedown(dev);
+		return retcode;
+	}
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+		 R128_NAME,
+		 R128_MAJOR,
+		 R128_MINOR,
+		 R128_PATCHLEVEL,
+		 R128_DATE,
+		 r128_misc.minor);
+
+	return 0;
+}
+
+/* r128_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit r128_cleanup(void)
+{
+	drm_device_t	      *dev = &r128_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&r128_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	drm_ctxbitmap_cleanup(dev);
+	r128_takedown(dev);
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	if (dev->agp) {
+		drm_agp_uninit();
+		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
+		dev->agp = NULL;
+	}
+#endif
+}
+
+module_init(r128_init);
+module_exit(r128_cleanup);
+
+
+int r128_version(struct inode *inode, struct file *filp,
+		 unsigned int cmd, unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)					\
+	len = strlen(value);					\
+	if (len > name##_len) len = name##_len;			\
+	name##_len = strlen(value);				\
+	if (len && name) {					\
+		if (copy_to_user(name, value, len))		\
+			return -EFAULT;				\
+	}
+
+	version.version_major	   = R128_MAJOR;
+	version.version_minor	   = R128_MINOR;
+	version.version_patchlevel = R128_PATCHLEVEL;
+
+	DRM_COPY(version.name, R128_NAME);
+	DRM_COPY(version.date, R128_DATE);
+	DRM_COPY(version.desc, R128_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int r128_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &r128_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return r128_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	return retcode;
+}
+
+int r128_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev = priv->dev;
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_release(inode, filp))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_close);
+		spin_lock(&dev->count_lock);
+		if (!--dev->open_count) {
+			if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+				DRM_ERROR("Device busy: %d %d\n",
+					  atomic_read(&dev->ioctl_count),
+					  dev->blocked);
+				spin_unlock(&dev->count_lock);
+				unlock_kernel();
+				return -EBUSY;
+			}
+			spin_unlock(&dev->count_lock);
+			unlock_kernel();
+			return r128_takedown(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	unlock_kernel();
+	return retcode;
+}
+
+/* r128_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+int r128_ioctl(struct inode *inode, struct file *filp,
+	       unsigned int cmd, unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= R128_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &r128_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			   || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+#if 0
+	if ( retcode ) {
+		DRM_INFO( "%s 0x%x ret = %d\n", __FUNCTION__, nr, retcode );
+	}
+#endif
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+int r128_lock(struct inode *inode, struct file *filp,
+	      unsigned int cmd, unsigned long arg)
+{
+        drm_file_t        *priv   = filp->private_data;
+        drm_device_t      *dev    = priv->dev;
+        DECLARE_WAITQUEUE(entry, current);
+        int               ret   = 0;
+        drm_lock_t        lock;
+#if DRM_DMA_HISTOGRAM
+        cycles_t          start;
+
+        dev->lck_start = start = get_cycles();
+#endif
+
+        if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+        if (lock.context == DRM_KERNEL_CONTEXT) {
+                DRM_ERROR("Process %d using kernel context %d\n",
+                          current->pid, lock.context);
+                return -EINVAL;
+        }
+
+        DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+                  lock.context, current->pid, dev->lock.hw_lock->lock,
+                  lock.flags);
+
+        if (lock.context < 0)
+                return -EINVAL;
+
+        if (!ret) {
+                add_wait_queue(&dev->lock.lock_queue, &entry);
+                for (;;) {
+                        current->state = TASK_INTERRUPTIBLE;
+                        if (!dev->lock.hw_lock) {
+                                /* Device has been unregistered */
+                                ret = -EINTR;
+                                break;
+                        }
+                        if (drm_lock_take(&dev->lock.hw_lock->lock,
+                                          lock.context)) {
+                                dev->lock.pid       = current->pid;
+                                dev->lock.lock_time = jiffies;
+                                atomic_inc(&dev->total_locks);
+                                break;  /* Got lock */
+                        }
+
+                                /* Contention */
+                        atomic_inc(&dev->total_sleeps);
+                        schedule();
+                        if (signal_pending(current)) {
+                                ret = -ERESTARTSYS;
+                                break;
+                        }
+                }
+                current->state = TASK_RUNNING;
+                remove_wait_queue(&dev->lock.lock_queue, &entry);
+        }
+
+        if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+                if (lock.flags & _DRM_LOCK_READY) {
+				/* Wait for space in DMA/FIFO */
+		}
+                if (lock.flags & _DRM_LOCK_QUIESCENT) {
+				/* Make hardware quiescent */
+			DRM_DEBUG( "not quiescent!\n" );
+#if 0
+                        r128_quiescent(dev);
+#endif
+		}
+        }
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != r128_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY/4;
+	}
+#endif
+        DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]);
+#endif
+
+        return ret;
+}
+
+
+int r128_unlock(struct inode *inode, struct file *filp,
+		unsigned int cmd, unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+				/* FIXME: Try to send data to card here */
+	if (!dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != r128_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY;
+	}
+#endif
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_drv.h lia64-2.4/drivers/char/drm-4.0/r128_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/r128_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_drv.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,469 @@
+/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
+ * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *   Rickard E. (Rik) Faith <faith@valinux.com>
+ *   Kevin E. Martin <martin@valinux.com>
+ *   Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#ifndef __R128_DRV_H__
+#define __R128_DRV_H__
+
+typedef struct drm_r128_freelist {
+   	unsigned int age;
+   	drm_buf_t *buf;
+   	struct drm_r128_freelist *next;
+   	struct drm_r128_freelist *prev;
+} drm_r128_freelist_t;
+
+typedef struct drm_r128_ring_buffer {
+	u32 *start;
+	u32 *end;
+	int size;
+	int size_l2qw;
+
+	volatile u32 *head;
+	u32 tail;
+	u32 tail_mask;
+	int space;
+} drm_r128_ring_buffer_t;
+
+typedef struct drm_r128_private {
+	drm_r128_ring_buffer_t ring;
+	drm_r128_sarea_t *sarea_priv;
+
+	int cce_mode;
+	int cce_fifo_size;
+	int cce_secure;
+	int cce_running;
+
+   	drm_r128_freelist_t *head;
+   	drm_r128_freelist_t *tail;
+
+	int usec_timeout;
+	int is_pci;
+
+	atomic_t idle_count;
+
+	unsigned int fb_bpp;
+	unsigned int front_offset;
+	unsigned int front_pitch;
+	unsigned int back_offset;
+	unsigned int back_pitch;
+
+	unsigned int depth_bpp;
+	unsigned int depth_offset;
+	unsigned int depth_pitch;
+	unsigned int span_offset;
+
+	u32 front_pitch_offset_c;
+	u32 back_pitch_offset_c;
+	u32 depth_pitch_offset_c;
+	u32 span_pitch_offset_c;
+
+	drm_map_t *sarea;
+	drm_map_t *fb;
+	drm_map_t *mmio;
+	drm_map_t *cce_ring;
+	drm_map_t *ring_rptr;
+	drm_map_t *buffers;
+	drm_map_t *agp_textures;
+} drm_r128_private_t;
+
+typedef struct drm_r128_buf_priv {
+	u32 age;
+	int prim;
+	int discard;
+	int dispatched;
+   	drm_r128_freelist_t *list_entry;
+} drm_r128_buf_priv_t;
+
+				/* r128_drv.c */
+extern int  r128_version( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int  r128_open( struct inode *inode, struct file *filp );
+extern int  r128_release( struct inode *inode, struct file *filp );
+extern int  r128_ioctl( struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg );
+extern int  r128_lock( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg );
+extern int  r128_unlock( struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg );
+
+				/* r128_cce.c */
+extern int r128_cce_init( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int r128_cce_start( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int r128_cce_stop( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int r128_cce_reset( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int r128_cce_idle( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int r128_engine_reset( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
+extern int r128_cce_packet( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int r128_cce_buffers( struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg );
+
+extern void r128_freelist_reset( drm_device_t *dev );
+extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
+
+extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
+extern void r128_update_ring_snapshot( drm_r128_private_t *dev_priv );
+
+				/* r128_state.c */
+extern int r128_cce_clear( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int r128_cce_swap( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int r128_cce_vertex( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int r128_cce_indices( struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg );
+extern int r128_cce_blit( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int r128_cce_depth( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int r128_cce_stipple( struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg );
+
+				/* r128_bufs.c */
+extern int r128_addbufs(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int r128_mapbufs(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+
+				/* r128_context.c */
+extern int  r128_resctx(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  r128_addctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  r128_modctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  r128_getctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  r128_switchctx(struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg);
+extern int  r128_newctx(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  r128_rmctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+
+extern int  r128_context_switch(drm_device_t *dev, int old, int new);
+extern int  r128_context_switch_complete(drm_device_t *dev, int new);
+
+
+/* Register definitions, register access macros and drmAddMap constants
+ * for Rage 128 kernel driver.
+ */
+
+#define R128_AUX_SC_CNTL		0x1660
+#	define R128_AUX1_SC_EN			(1 << 0)
+#	define R128_AUX1_SC_MODE_OR		(0 << 1)
+#	define R128_AUX1_SC_MODE_NAND		(1 << 1)
+#	define R128_AUX2_SC_EN			(1 << 2)
+#	define R128_AUX2_SC_MODE_OR		(0 << 3)
+#	define R128_AUX2_SC_MODE_NAND		(1 << 3)
+#	define R128_AUX3_SC_EN			(1 << 4)
+#	define R128_AUX3_SC_MODE_OR		(0 << 5)
+#	define R128_AUX3_SC_MODE_NAND		(1 << 5)
+#define R128_AUX1_SC_LEFT		0x1664
+#define R128_AUX1_SC_RIGHT		0x1668
+#define R128_AUX1_SC_TOP		0x166c
+#define R128_AUX1_SC_BOTTOM		0x1670
+#define R128_AUX2_SC_LEFT		0x1674
+#define R128_AUX2_SC_RIGHT		0x1678
+#define R128_AUX2_SC_TOP		0x167c
+#define R128_AUX2_SC_BOTTOM		0x1680
+#define R128_AUX3_SC_LEFT		0x1684
+#define R128_AUX3_SC_RIGHT		0x1688
+#define R128_AUX3_SC_TOP		0x168c
+#define R128_AUX3_SC_BOTTOM		0x1690
+
+#define R128_BRUSH_DATA0		0x1480
+#define R128_BUS_CNTL			0x0030
+#	define R128_BUS_MASTER_DIS		(1 << 6)
+
+#define R128_CLOCK_CNTL_INDEX		0x0008
+#define R128_CLOCK_CNTL_DATA		0x000c
+#	define R128_PLL_WR_EN			(1 << 7)
+
+#define R128_CONSTANT_COLOR_C		0x1d34
+
+#define R128_DP_GUI_MASTER_CNTL		0x146c
+#       define R128_GMC_SRC_PITCH_OFFSET_CNTL	(1    <<  0)
+#       define R128_GMC_DST_PITCH_OFFSET_CNTL	(1    <<  1)
+#	define R128_GMC_BRUSH_SOLID_COLOR	(13   <<  4)
+#	define R128_GMC_BRUSH_NONE		(15   <<  4)
+#	define R128_GMC_DST_16BPP		(4    <<  8)
+#	define R128_GMC_DST_24BPP		(5    <<  8)
+#	define R128_GMC_DST_32BPP		(6    <<  8)
+#       define R128_GMC_DST_DATATYPE_SHIFT	8
+#	define R128_GMC_SRC_DATATYPE_COLOR	(3    << 12)
+#	define R128_DP_SRC_SOURCE_MEMORY	(2    << 24)
+#	define R128_DP_SRC_SOURCE_HOST_DATA	(3    << 24)
+#	define R128_GMC_CLR_CMP_CNTL_DIS	(1    << 28)
+#	define R128_GMC_AUX_CLIP_DIS		(1    << 29)
+#	define R128_GMC_WR_MSK_DIS		(1    << 30)
+#	define R128_ROP3_S			0x00cc0000
+#	define R128_ROP3_P			0x00f00000
+#define R128_DP_WRITE_MASK		0x16cc
+#define R128_DST_PITCH_OFFSET_C		0x1c80
+#	define R128_DST_TILE			(1 << 31)
+
+#define R128_GEN_RESET_CNTL		0x00f0
+#	define R128_SOFT_RESET_GUI		(1 <<  0)
+
+#define R128_GUI_SCRATCH_REG0		0x15e0
+#define R128_GUI_SCRATCH_REG1		0x15e4
+#define R128_GUI_SCRATCH_REG2		0x15e8
+#define R128_GUI_SCRATCH_REG3		0x15ec
+#define R128_GUI_SCRATCH_REG4		0x15f0
+#define R128_GUI_SCRATCH_REG5		0x15f4
+
+#define R128_GUI_STAT			0x1740
+#	define R128_GUI_FIFOCNT_MASK		0x0fff
+#	define R128_GUI_ACTIVE			(1 << 31)
+
+#define R128_MCLK_CNTL			0x000f
+#	define R128_FORCE_GCP			(1 << 16)
+#	define R128_FORCE_PIPE3D_CP		(1 << 17)
+#	define R128_FORCE_RCP			(1 << 18)
+
+#define R128_PC_GUI_CTLSTAT		0x1748
+#define R128_PC_NGUI_CTLSTAT		0x0184
+#	define R128_PC_FLUSH_GUI		(3 << 0)
+#	define R128_PC_RI_GUI			(1 << 2)
+#	define R128_PC_FLUSH_ALL		0x00ff
+#	define R128_PC_BUSY			(1 << 31)
+
+#define R128_PRIM_TEX_CNTL_C		0x1cb0
+
+#define R128_SCALE_3D_CNTL		0x1a00
+#define R128_SEC_TEX_CNTL_C		0x1d00
+#define R128_SEC_TEXTURE_BORDER_COLOR_C	0x1d3c
+#define R128_SETUP_CNTL			0x1bc4
+#define R128_STEN_REF_MASK_C		0x1d40
+
+#define R128_TEX_CNTL_C			0x1c9c
+#	define R128_TEX_CACHE_FLUSH		(1 << 23)
+
+#define R128_WINDOW_XY_OFFSET		0x1bcc
+
+
+/* CCE registers
+ */
+#define R128_PM4_BUFFER_OFFSET		0x0700
+#define R128_PM4_BUFFER_CNTL		0x0704
+#	define R128_PM4_MASK			(15 << 28)
+#	define R128_PM4_NONPM4			(0  << 28)
+#	define R128_PM4_192PIO			(1  << 28)
+#	define R128_PM4_192BM			(2  << 28)
+#	define R128_PM4_128PIO_64INDBM		(3  << 28)
+#	define R128_PM4_128BM_64INDBM		(4  << 28)
+#	define R128_PM4_64PIO_128INDBM		(5  << 28)
+#	define R128_PM4_64BM_128INDBM		(6  << 28)
+#	define R128_PM4_64PIO_64VCBM_64INDBM	(7  << 28)
+#	define R128_PM4_64BM_64VCBM_64INDBM	(8  << 28)
+#	define R128_PM4_64PIO_64VCPIO_64INDPIO	(15 << 28)
+
+#define R128_PM4_BUFFER_WM_CNTL		0x0708
+#	define R128_WMA_SHIFT			0
+#	define R128_WMB_SHIFT			8
+#	define R128_WMC_SHIFT			16
+#	define R128_WB_WM_SHIFT			24
+
+#define R128_PM4_BUFFER_DL_RPTR_ADDR	0x070c
+#define R128_PM4_BUFFER_DL_RPTR		0x0710
+#define R128_PM4_BUFFER_DL_WPTR		0x0714
+#	define R128_PM4_BUFFER_DL_DONE		(1 << 31)
+
+#define R128_PM4_VC_FPU_SETUP		0x071c
+
+#define R128_PM4_IW_INDOFF		0x0738
+#define R128_PM4_IW_INDSIZE		0x073c
+
+#define R128_PM4_STAT			0x07b8
+#	define R128_PM4_FIFOCNT_MASK		0x0fff
+#	define R128_PM4_BUSY			(1 << 16)
+#	define R128_PM4_GUI_ACTIVE		(1 << 31)
+
+#define R128_PM4_MICROCODE_ADDR		0x07d4
+#define R128_PM4_MICROCODE_RADDR	0x07d8
+#define R128_PM4_MICROCODE_DATAH	0x07dc
+#define R128_PM4_MICROCODE_DATAL	0x07e0
+
+#define R128_PM4_BUFFER_ADDR		0x07f0
+#define R128_PM4_MICRO_CNTL		0x07fc
+#	define R128_PM4_MICRO_FREERUN		(1 << 30)
+
+#define R128_PM4_FIFO_DATA_EVEN		0x1000
+#define R128_PM4_FIFO_DATA_ODD		0x1004
+
+
+/* CCE command packets
+ */
+#define R128_CCE_PACKET0		0x00000000
+#define R128_CCE_PACKET1		0x40000000
+#define R128_CCE_PACKET2		0x80000000
+#define R128_CCE_PACKET3		0xC0000000
+#	define R128_CNTL_HOSTDATA_BLT		0x00009400
+#	define R128_CNTL_PAINT_MULTI		0x00009A00
+#	define R128_CNTL_BITBLT_MULTI		0x00009B00
+#	define R128_3D_RNDR_GEN_INDX_PRIM	0x00002300
+
+#define R128_CCE_PACKET_MASK		0xC0000000
+#define R128_CCE_PACKET_COUNT_MASK	0x3fff0000
+#define R128_CCE_PACKET0_REG_MASK	0x000007ff
+#define R128_CCE_PACKET1_REG0_MASK	0x000007ff
+#define R128_CCE_PACKET1_REG1_MASK	0x003ff800
+
+#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE		0x00000000
+#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT	0x00000001
+#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE		0x00000002
+#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE	0x00000003
+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST	0x00000004
+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN	0x00000005
+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP	0x00000006
+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2	0x00000007
+#define R128_CCE_VC_CNTL_PRIM_WALK_IND		0x00000010
+#define R128_CCE_VC_CNTL_PRIM_WALK_LIST		0x00000020
+#define R128_CCE_VC_CNTL_PRIM_WALK_RING		0x00000030
+#define R128_CCE_VC_CNTL_NUM_SHIFT		16
+
+#define R128_DATATYPE_CI8		2
+#define R128_DATATYPE_ARGB1555		3
+#define R128_DATATYPE_RGB565		4
+#define R128_DATATYPE_RGB888		5
+#define R128_DATATYPE_ARGB8888		6
+#define R128_DATATYPE_RGB332		7
+#define R128_DATATYPE_RGB8		9
+#define R128_DATATYPE_ARGB4444		15
+
+/* Constants */
+#define R128_AGP_OFFSET			0x02000000
+
+#define R128_WATERMARK_L		16
+#define R128_WATERMARK_M		8
+#define R128_WATERMARK_N		8
+#define R128_WATERMARK_K		128
+
+#define R128_MAX_USEC_TIMEOUT	100000	/* 100 ms */
+
+#define R128_LAST_FRAME_REG		R128_GUI_SCRATCH_REG0
+#define R128_LAST_DISPATCH_REG		R128_GUI_SCRATCH_REG1
+#define R128_MAX_VB_AGE			0xffffffff
+
+#define R128_MAX_VB_VERTS		(0xffff)
+
+
+#define R128_BASE(reg)		((unsigned long)(dev_priv->mmio->handle))
+#define R128_ADDR(reg)		(R128_BASE(reg) + reg)
+
+#define R128_READ(reg)		readl(R128_ADDR(reg))
+#define R128_WRITE(reg,val)	writel(val,R128_ADDR(reg))
+
+#define R128_READ8(reg)		readb(R128_ADDR(reg))
+#define R128_WRITE8(reg,val)	writeb(val,R128_ADDR(reg))
+
+#define R128_WRITE_PLL(addr,val)                                              \
+do {                                                                          \
+	R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
+	R128_WRITE(R128_CLOCK_CNTL_DATA, (val));                              \
+} while (0)
+
+extern int R128_READ_PLL(drm_device_t *dev, int addr);
+
+#define R128CCE0(p,r,n)   ((p) | ((n) << 16) | ((r) >> 2))
+#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2))
+#define R128CCE2(p)       ((p))
+#define R128CCE3(p,n)     ((p) | ((n) << 16))
+
+
+
+
+#define CCE_PACKET0( reg, n )		(R128_CCE_PACKET0 |		\
+					 ((n) << 16) | ((reg) >> 2))
+#define CCE_PACKET1( reg0, reg1 )	(R128_CCE_PACKET1 |		\
+					 (((reg1) >> 2) << 11) | ((reg0) >> 2))
+#define CCE_PACKET2()			(R128_CCE_PACKET2)
+#define CCE_PACKET3( pkt, n )		(R128_CCE_PACKET3 |		\
+					 (pkt) | ((n) << 16))
+
+
+#define r128_flush_write_combine()		mb()
+
+
+#define R128_VERBOSE	0
+
+#define RING_LOCALS	int write; unsigned int tail_mask; volatile u32 *ring;
+
+#define BEGIN_RING( n ) do {						\
+	if ( R128_VERBOSE ) {						\
+		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
+			   n, __FUNCTION__ );				\
+	}								\
+	if ( dev_priv->ring.space < n * sizeof(u32) ) {			\
+		r128_wait_ring( dev_priv, n * sizeof(u32) );		\
+	}								\
+	dev_priv->ring.space -= n * sizeof(u32);			\
+	ring = dev_priv->ring.start;					\
+	write = dev_priv->ring.tail;					\
+	tail_mask = dev_priv->ring.tail_mask;				\
+} while (0)
+
+#define ADVANCE_RING() do {						\
+	if ( R128_VERBOSE ) {						\
+		DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n",	\
+			  write, dev_priv->ring.tail );			\
+	}								\
+	if ( write < 32 ) {						\
+		memcpy( dev_priv->ring.end,				\
+			dev_priv->ring.start,				\
+			write * sizeof(u32) );				\
+	}								\
+	r128_flush_write_combine();					\
+	dev_priv->ring.tail = write;					\
+	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );			\
+} while (0)
+
+#define OUT_RING( x ) do {						\
+	if ( R128_VERBOSE ) {						\
+		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
+			   (unsigned int)(x), write );			\
+	}								\
+	ring[write++] = x;						\
+	write &= tail_mask;						\
+} while (0)
+
+#define R128_PERFORMANCE_BOXES	0
+
+#endif /* __R128_DRV_H__ */
diff -urN linux-2.4.16/drivers/char/drm-4.0/r128_state.c lia64-2.4/drivers/char/drm-4.0/r128_state.c
--- linux-2.4.16/drivers/char/drm-4.0/r128_state.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/r128_state.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,1605 @@
+/* r128_state.c -- State support for r128 -*- linux-c -*-
+ * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
+ *
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "r128_drv.h"
+#include "drm.h"
+
+
+/* ================================================================
+ * CCE hardware state programming functions
+ */
+
+static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
+				  drm_clip_rect_t *boxes, int count )
+{
+	u32 aux_sc_cntl = 0x00000000;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 17 );
+
+	if ( count >= 1 ) {
+		OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
+		OUT_RING( boxes[0].x1 );
+		OUT_RING( boxes[0].x2 - 1 );
+		OUT_RING( boxes[0].y1 );
+		OUT_RING( boxes[0].y2 - 1 );
+
+		aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
+	}
+	if ( count >= 2 ) {
+		OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) );
+		OUT_RING( boxes[1].x1 );
+		OUT_RING( boxes[1].x2 - 1 );
+		OUT_RING( boxes[1].y1 );
+		OUT_RING( boxes[1].y2 - 1 );
+
+		aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
+	}
+	if ( count >= 3 ) {
+		OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) );
+		OUT_RING( boxes[2].x1 );
+		OUT_RING( boxes[2].x2 - 1 );
+		OUT_RING( boxes[2].y1 );
+		OUT_RING( boxes[2].y2 - 1 );
+
+		aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
+	}
+
+	OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) );
+	OUT_RING( aux_sc_cntl );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_core( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) );
+	OUT_RING( ctx->scale_3d_cntl );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_context( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 13 );
+
+	OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) );
+	OUT_RING( ctx->dst_pitch_offset_c );
+	OUT_RING( ctx->dp_gui_master_cntl_c );
+	OUT_RING( ctx->sc_top_left_c );
+	OUT_RING( ctx->sc_bottom_right_c );
+	OUT_RING( ctx->z_offset_c );
+	OUT_RING( ctx->z_pitch_c );
+	OUT_RING( ctx->z_sten_cntl_c );
+	OUT_RING( ctx->tex_cntl_c );
+	OUT_RING( ctx->misc_3d_state_cntl_reg );
+	OUT_RING( ctx->texture_clr_cmp_clr_c );
+	OUT_RING( ctx->texture_clr_cmp_msk_c );
+	OUT_RING( ctx->fog_color_c );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_setup( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 3 );
+
+	OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) );
+	OUT_RING( ctx->setup_cntl );
+	OUT_RING( ctx->pm4_vc_fpu_setup );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_masks( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 5 );
+
+	OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
+	OUT_RING( ctx->dp_write_mask );
+
+	OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) );
+	OUT_RING( ctx->sten_ref_mask_c );
+	OUT_RING( ctx->plane_3d_mask_c );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_window( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) );
+	OUT_RING( ctx->window_xy_offset );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
+	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 7 + R128_TEX_MAXLEVELS );
+
+	OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
+			       2 + R128_TEX_MAXLEVELS ) );
+	OUT_RING( tex->tex_cntl );
+	OUT_RING( tex->tex_combine_cntl );
+	OUT_RING( ctx->tex_size_pitch_c );
+	for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) {
+		OUT_RING( tex->tex_offset[i] );
+	}
+
+	OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) );
+	OUT_RING( ctx->constant_color_c );
+	OUT_RING( tex->tex_border_color );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 5 + R128_TEX_MAXLEVELS );
+
+	OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
+			       1 + R128_TEX_MAXLEVELS ) );
+	OUT_RING( tex->tex_cntl );
+	OUT_RING( tex->tex_combine_cntl );
+	for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) {
+		OUT_RING( tex->tex_offset[i] );
+	}
+
+	OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
+	OUT_RING( tex->tex_border_color );
+
+	ADVANCE_RING();
+}
+
+static inline void r128_emit_state( drm_r128_private_t *dev_priv )
+{
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int dirty = sarea_priv->dirty;
+
+	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
+
+	if ( dirty & R128_UPLOAD_CORE ) {
+		r128_emit_core( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_CORE;
+	}
+
+	if ( dirty & R128_UPLOAD_CONTEXT ) {
+		r128_emit_context( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
+	}
+
+	if ( dirty & R128_UPLOAD_SETUP ) {
+		r128_emit_setup( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
+	}
+
+	if ( dirty & R128_UPLOAD_MASKS ) {
+		r128_emit_masks( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
+	}
+
+	if ( dirty & R128_UPLOAD_WINDOW ) {
+		r128_emit_window( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
+	}
+
+	if ( dirty & R128_UPLOAD_TEX0 ) {
+		r128_emit_tex0( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
+	}
+
+	if ( dirty & R128_UPLOAD_TEX1 ) {
+		r128_emit_tex1( dev_priv );
+		sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
+	}
+
+	/* Turn off the texture cache flushing */
+	sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
+
+	sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
+}
+
+
+#if R128_PERFORMANCE_BOXES
+/* ================================================================
+ * Performance monitoring functions
+ */
+
+static void r128_clear_box( drm_r128_private_t *dev_priv,
+			    int x, int y, int w, int h,
+			    int r, int g, int b )
+{
+	u32 pitch, offset;
+	u32 fb_bpp, color;
+	RING_LOCALS;
+
+	switch ( dev_priv->fb_bpp ) {
+	case 16:
+		fb_bpp = R128_GMC_DST_16BPP;
+		color = (((r & 0xf8) << 8) |
+			 ((g & 0xfc) << 3) |
+			 ((b & 0xf8) >> 3));
+		break;
+	case 24:
+		fb_bpp = R128_GMC_DST_24BPP;
+		color = ((r << 16) | (g << 8) | b);
+		break;
+	case 32:
+		fb_bpp = R128_GMC_DST_32BPP;
+		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
+		break;
+	default:
+		return;
+	}
+
+	offset = dev_priv->back_offset;
+	pitch = dev_priv->back_pitch >> 3;
+
+	BEGIN_RING( 6 );
+
+	OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+	OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+		  | R128_GMC_BRUSH_SOLID_COLOR
+		  | fb_bpp
+		  | R128_GMC_SRC_DATATYPE_COLOR
+		  | R128_ROP3_P
+		  | R128_GMC_CLR_CMP_CNTL_DIS
+		  | R128_GMC_AUX_CLIP_DIS );
+
+	OUT_RING( (pitch << 21) | (offset >> 5) );
+	OUT_RING( color );
+
+	OUT_RING( (x << 16) | y );
+	OUT_RING( (w << 16) | h );
+
+	ADVANCE_RING();
+}
+
+static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv )
+{
+	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
+		r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
+	} else {
+		atomic_set( &dev_priv->idle_count, 0 );
+	}
+}
+
+#endif
+
+
+/* ================================================================
+ * CCE command dispatch functions
+ */
+
+static void r128_print_dirty( const char *msg, unsigned int flags )
+{
+	DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
+		  msg,
+		  flags,
+		  (flags & R128_UPLOAD_CORE)        ? "core, " : "",
+		  (flags & R128_UPLOAD_CONTEXT)     ? "context, " : "",
+		  (flags & R128_UPLOAD_SETUP)       ? "setup, " : "",
+		  (flags & R128_UPLOAD_TEX0)        ? "tex0, " : "",
+		  (flags & R128_UPLOAD_TEX1)        ? "tex1, " : "",
+		  (flags & R128_UPLOAD_MASKS)       ? "masks, " : "",
+		  (flags & R128_UPLOAD_WINDOW)      ? "window, " : "",
+		  (flags & R128_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
+		  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
+}
+
+static void r128_cce_dispatch_clear( drm_device_t *dev,
+				     unsigned int flags,
+				     int cx, int cy, int cw, int ch,
+				     unsigned int clear_color,
+				     unsigned int clear_depth )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	u32 fb_bpp, depth_bpp;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	switch ( dev_priv->fb_bpp ) {
+	case 16:
+		fb_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 32:
+		fb_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return;
+	}
+	switch ( dev_priv->depth_bpp ) {
+	case 16:
+		depth_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 24:
+	case 32:
+		depth_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return;
+	}
+
+	for ( i = 0 ; i < nbox ; i++ ) {
+		int x = pbox[i].x1;
+		int y = pbox[i].y1;
+		int w = pbox[i].x2 - x;
+		int h = pbox[i].y2 - y;
+
+		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
+			   pbox[i].x1, pbox[i].y1, pbox[i].x2,
+			   pbox[i].y2, flags );
+
+		if ( flags & (R128_FRONT | R128_BACK) ) {
+			BEGIN_RING( 2 );
+
+			OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
+			OUT_RING( sarea_priv->context_state.plane_3d_mask_c );
+
+			ADVANCE_RING();
+		}
+
+		if ( flags & R128_FRONT ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+				  | R128_GMC_BRUSH_SOLID_COLOR
+				  | fb_bpp
+				  | R128_GMC_SRC_DATATYPE_COLOR
+				  | R128_ROP3_P
+				  | R128_GMC_CLR_CMP_CNTL_DIS
+				  | R128_GMC_AUX_CLIP_DIS );
+
+			OUT_RING( dev_priv->front_pitch_offset_c );
+			OUT_RING( clear_color );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (w << 16) | h );
+
+			ADVANCE_RING();
+		}
+
+		if ( flags & R128_BACK ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+				  | R128_GMC_BRUSH_SOLID_COLOR
+				  | fb_bpp
+				  | R128_GMC_SRC_DATATYPE_COLOR
+				  | R128_ROP3_P
+				  | R128_GMC_CLR_CMP_CNTL_DIS
+				  | R128_GMC_AUX_CLIP_DIS );
+
+			OUT_RING( dev_priv->back_pitch_offset_c );
+			OUT_RING( clear_color );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (w << 16) | h );
+
+			ADVANCE_RING();
+		}
+
+		if ( flags & R128_DEPTH ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+				  | R128_GMC_BRUSH_SOLID_COLOR
+				  | depth_bpp
+				  | R128_GMC_SRC_DATATYPE_COLOR
+				  | R128_ROP3_P
+				  | R128_GMC_CLR_CMP_CNTL_DIS
+				  | R128_GMC_AUX_CLIP_DIS
+				  | R128_GMC_WR_MSK_DIS );
+
+			OUT_RING( dev_priv->depth_pitch_offset_c );
+			OUT_RING( clear_depth );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (w << 16) | h );
+
+			ADVANCE_RING();
+		}
+	}
+}
+
+static void r128_cce_dispatch_swap( drm_device_t *dev )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	u32 fb_bpp;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+#if R128_PERFORMANCE_BOXES
+	/* Do some trivial performance monitoring...
+	 */
+	r128_cce_performance_boxes( dev_priv );
+#endif
+
+	switch ( dev_priv->fb_bpp ) {
+	case 16:
+		fb_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 32:
+	default:
+		fb_bpp = R128_GMC_DST_32BPP;
+		break;
+	}
+
+	for ( i = 0 ; i < nbox ; i++ ) {
+		int x = pbox[i].x1;
+		int y = pbox[i].y1;
+		int w = pbox[i].x2 - x;
+		int h = pbox[i].y2 - y;
+
+		BEGIN_RING( 7 );
+
+		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
+		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL
+			  | R128_GMC_DST_PITCH_OFFSET_CNTL
+			  | R128_GMC_BRUSH_NONE
+			  | fb_bpp
+			  | R128_GMC_SRC_DATATYPE_COLOR
+			  | R128_ROP3_S
+			  | R128_DP_SRC_SOURCE_MEMORY
+			  | R128_GMC_CLR_CMP_CNTL_DIS
+			  | R128_GMC_AUX_CLIP_DIS
+			  | R128_GMC_WR_MSK_DIS );
+
+		OUT_RING( dev_priv->back_pitch_offset_c );
+		OUT_RING( dev_priv->front_pitch_offset_c );
+
+		OUT_RING( (x << 16) | y );
+		OUT_RING( (x << 16) | y );
+		OUT_RING( (w << 16) | h );
+
+		ADVANCE_RING();
+	}
+
+	/* Increment the frame counter.  The client-side 3D driver must
+	 * throttle the framerate by waiting for this value before
+	 * performing the swapbuffer ioctl.
+	 */
+	dev_priv->sarea_priv->last_frame++;
+
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
+	OUT_RING( dev_priv->sarea_priv->last_frame );
+
+	ADVANCE_RING();
+}
+
+static void r128_cce_dispatch_vertex( drm_device_t *dev,
+				      drm_buf_t *buf )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int format = sarea_priv->vc_format;
+	int offset = dev_priv->buffers->offset + buf->offset - dev->agp->base;
+	int size = buf->used;
+	int prim = buf_priv->prim;
+	int i = 0;
+	RING_LOCALS;
+	DRM_DEBUG( "%s: buf=%d nbox=%d\n",
+		   __FUNCTION__, buf->idx, sarea_priv->nbox );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	if ( 0 )
+		r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
+
+	if ( buf->used ) {
+		buf_priv->dispatched = 1;
+
+		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
+			r128_emit_state( dev_priv );
+		}
+
+		do {
+			/* Emit the next set of up to three cliprects */
+			if ( i < sarea_priv->nbox ) {
+				r128_emit_clip_rects( dev_priv,
+						      &sarea_priv->boxes[i],
+						      sarea_priv->nbox - i );
+			}
+
+			/* Emit the vertex buffer rendering commands */
+			BEGIN_RING( 5 );
+
+			OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) );
+			OUT_RING( offset );
+			OUT_RING( size );
+			OUT_RING( format );
+			OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
+				  (size << R128_CCE_VC_CNTL_NUM_SHIFT) );
+
+			ADVANCE_RING();
+
+			i += 3;
+		} while ( i < sarea_priv->nbox );
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
+
+		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
+		OUT_RING( buf_priv->age );
+
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		buf->used = 0;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+
+#if 0
+	if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
+		ret = r128_do_cce_idle( dev_priv );
+		if ( ret < 0 ) return ret;
+		dev_priv->submit_age = 0;
+		r128_freelist_reset( dev );
+	}
+#endif
+
+	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
+	sarea_priv->nbox = 0;
+}
+
+
+
+
+static void r128_cce_dispatch_indirect( drm_device_t *dev,
+					drm_buf_t *buf,
+					int start, int end )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
+	RING_LOCALS;
+	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
+		   buf->idx, start, end );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	if ( start != end ) {
+		int offset = (dev_priv->buffers->offset - dev->agp->base
+			      + buf->offset + start);
+		int dwords = (end - start + 3) / sizeof(u32);
+
+		/* Indirect buffer data must be an even number of
+		 * dwords, so if we've been given an odd number we must
+		 * pad the data with a Type-2 CCE packet.
+		 */
+		if ( dwords & 1 ) {
+			u32 *data = (u32 *)
+				((char *)dev_priv->buffers->handle
+				 + buf->offset + start);
+			data[dwords++] = R128_CCE_PACKET2;
+		}
+
+		buf_priv->dispatched = 1;
+
+		/* Fire off the indirect buffer */
+		BEGIN_RING( 3 );
+
+		OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
+		OUT_RING( offset );
+		OUT_RING( dwords );
+
+		ADVANCE_RING();
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the indirect buffer age */
+		BEGIN_RING( 2 );
+
+		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
+		OUT_RING( buf_priv->age );
+
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		buf->used = 0;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+
+#if 0
+	if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
+		ret = r128_do_cce_idle( dev_priv );
+		if ( ret < 0 ) return ret;
+		dev_priv->submit_age = 0;
+		r128_freelist_reset( dev );
+	}
+#endif
+}
+
+static void r128_cce_dispatch_indices( drm_device_t *dev,
+				       drm_buf_t *buf,
+				       int start, int end,
+				       int count )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int format = sarea_priv->vc_format;
+	int offset = dev_priv->buffers->offset - dev->agp->base;
+	int prim = buf_priv->prim;
+	u32 *data;
+	int dwords;
+	int i = 0;
+	RING_LOCALS;
+	DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	if ( 0 )
+		r128_print_dirty( "dispatch_indices", sarea_priv->dirty );
+
+	if ( start != end ) {
+		buf_priv->dispatched = 1;
+
+		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
+			r128_emit_state( dev_priv );
+		}
+
+		dwords = (end - start + 3) / sizeof(u32);
+
+		data = (u32 *)((char *)dev_priv->buffers->handle
+			       + buf->offset + start);
+
+		data[0] = CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
+
+		data[1] = offset;
+		data[2] = R128_MAX_VB_VERTS;
+		data[3] = format;
+		data[4] = (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
+			   (count << 16));
+
+		if ( count & 0x1 ) {
+			data[dwords-1] &= 0x0000ffff;
+		}
+
+		do {
+			/* Emit the next set of up to three cliprects */
+			if ( i < sarea_priv->nbox ) {
+				r128_emit_clip_rects( dev_priv,
+						      &sarea_priv->boxes[i],
+						      sarea_priv->nbox - i );
+			}
+
+			r128_cce_dispatch_indirect( dev, buf, start, end );
+
+			i += 3;
+		} while ( i < sarea_priv->nbox );
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
+
+		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
+		OUT_RING( buf_priv->age );
+
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+
+#if 0
+	if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
+		ret = r128_do_cce_idle( dev_priv );
+		if ( ret < 0 ) return ret;
+		dev_priv->submit_age = 0;
+		r128_freelist_reset( dev );
+	}
+#endif
+
+	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
+	sarea_priv->nbox = 0;
+}
+
+static int r128_cce_dispatch_blit( drm_device_t *dev,
+				   drm_r128_blit_t *blit )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_r128_buf_priv_t *buf_priv;
+	u32 *data;
+	int dword_shift, dwords;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	/* The compiler won't optimize away a division by a variable,
+	 * even if the only legal values are powers of two.  Thus, we'll
+	 * use a shift instead.
+	 */
+	switch ( blit->format ) {
+	case R128_DATATYPE_ARGB1555:
+	case R128_DATATYPE_RGB565:
+	case R128_DATATYPE_ARGB4444:
+		dword_shift = 1;
+		break;
+	case R128_DATATYPE_ARGB8888:
+		dword_shift = 0;
+		break;
+	default:
+		DRM_ERROR( "invalid blit format %d\n", blit->format );
+		return -EINVAL;
+	}
+
+	/* Flush the pixel cache, and mark the contents as Read Invalid.
+	 * This ensures no pixel data gets mixed up with the texture
+	 * data from the host data blit, otherwise part of the texture
+	 * image may be corrupted.
+	 */
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
+	OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
+
+	ADVANCE_RING();
+
+	/* Dispatch the indirect buffer.
+	 */
+	buf = dma->buflist[blit->idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
+		return -EINVAL;
+	}
+
+	buf_priv->discard = 1;
+
+	dwords = (blit->width * blit->height) >> dword_shift;
+
+	data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
+
+	data[0] = CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 );
+	data[1] = ( R128_GMC_DST_PITCH_OFFSET_CNTL
+		    | R128_GMC_BRUSH_NONE
+		    | (blit->format << 8)
+		    | R128_GMC_SRC_DATATYPE_COLOR
+		    | R128_ROP3_S
+		    | R128_DP_SRC_SOURCE_HOST_DATA
+		    | R128_GMC_CLR_CMP_CNTL_DIS
+		    | R128_GMC_AUX_CLIP_DIS
+		    | R128_GMC_WR_MSK_DIS );
+
+	data[2] = (blit->pitch << 21) | (blit->offset >> 5);
+	data[3] = 0xffffffff;
+	data[4] = 0xffffffff;
+	data[5] = (blit->y << 16) | blit->x;
+	data[6] = (blit->height << 16) | blit->width;
+	data[7] = dwords;
+
+	buf->used = (dwords + 8) * sizeof(u32);
+
+	r128_cce_dispatch_indirect( dev, buf, 0, buf->used );
+
+	/* Flush the pixel cache after the blit completes.  This ensures
+	 * the texture data is written out to memory before rendering
+	 * continues.
+	 */
+	BEGIN_RING( 2 );
+
+	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
+	OUT_RING( R128_PC_FLUSH_GUI );
+
+	ADVANCE_RING();
+
+	return 0;
+}
+
+
+/* ================================================================
+ * Tiled depth buffer management
+ *
+ * FIXME: These should all set the destination write mask for when we
+ * have hardware stencil support.
+ */
+
+static int r128_cce_dispatch_write_span( drm_device_t *dev,
+					 drm_r128_depth_t *depth )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	int count, x, y;
+	u32 *buffer;
+	u8 *mask;
+	u32 depth_bpp;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	switch ( dev_priv->depth_bpp ) {
+	case 16:
+		depth_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 24:
+	case 32:
+		depth_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	count = depth->n;
+	if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
+		return -EFAULT;
+	}
+	if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
+		return -EFAULT;
+	}
+
+	buffer = kmalloc( depth->n * sizeof(u32), 0 );
+	if ( buffer == NULL )
+		return -ENOMEM;
+	if ( copy_from_user( buffer, depth->buffer,
+			     depth->n * sizeof(u32) ) ) {
+		kfree( buffer );
+		return -EFAULT;
+	}
+
+	if ( depth->mask ) {
+		mask = kmalloc( depth->n * sizeof(u8), 0 );
+		if ( mask == NULL ) {
+			kfree( buffer );
+			return -ENOMEM;
+		}
+		if ( copy_from_user( mask, depth->mask,
+				     depth->n * sizeof(u8) ) ) {
+			kfree( buffer );
+			kfree( mask );
+			return -EFAULT;
+		}
+
+		for ( i = 0 ; i < count ; i++, x++ ) {
+			if ( mask[i] ) {
+				BEGIN_RING( 6 );
+
+				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI,
+						       4 ) );
+				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+					  | R128_GMC_BRUSH_SOLID_COLOR
+					  | depth_bpp
+					  | R128_GMC_SRC_DATATYPE_COLOR
+					  | R128_ROP3_P
+					  | R128_GMC_CLR_CMP_CNTL_DIS
+					  | R128_GMC_WR_MSK_DIS );
+
+				OUT_RING( dev_priv->depth_pitch_offset_c );
+				OUT_RING( buffer[i] );
+
+				OUT_RING( (x << 16) | y );
+				OUT_RING( (1 << 16) | 1 );
+
+				ADVANCE_RING();
+			}
+		}
+
+		kfree( mask );
+	} else {
+		for ( i = 0 ; i < count ; i++, x++ ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+				  | R128_GMC_BRUSH_SOLID_COLOR
+				  | depth_bpp
+				  | R128_GMC_SRC_DATATYPE_COLOR
+				  | R128_ROP3_P
+				  | R128_GMC_CLR_CMP_CNTL_DIS
+				  | R128_GMC_WR_MSK_DIS );
+
+			OUT_RING( dev_priv->depth_pitch_offset_c );
+			OUT_RING( buffer[i] );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (1 << 16) | 1 );
+
+			ADVANCE_RING();
+		}
+	}
+
+	kfree( buffer );
+
+	return 0;
+}
+
+static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
+					   drm_r128_depth_t *depth )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	int count, *x, *y;
+	u32 *buffer;
+	u8 *mask;
+	u32 depth_bpp;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	switch ( dev_priv->depth_bpp ) {
+	case 16:
+		depth_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 24:
+	case 32:
+		depth_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	count = depth->n;
+
+	x = kmalloc( count * sizeof(*x), 0 );
+	if ( x == NULL ) {
+		return -ENOMEM;
+	}
+	y = kmalloc( count * sizeof(*y), 0 );
+	if ( y == NULL ) {
+		kfree( x );
+		return -ENOMEM;
+	}
+	if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
+		kfree( x );
+		kfree( y );
+		return -EFAULT;
+	}
+	if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
+		kfree( x );
+		kfree( y );
+		return -EFAULT;
+	}
+
+	buffer = kmalloc( depth->n * sizeof(u32), 0 );
+	if ( buffer == NULL ) {
+		kfree( x );
+		kfree( y );
+		return -ENOMEM;
+	}
+	if ( copy_from_user( buffer, depth->buffer,
+			     depth->n * sizeof(u32) ) ) {
+		kfree( x );
+		kfree( y );
+		kfree( buffer );
+		return -EFAULT;
+	}
+
+	if ( depth->mask ) {
+		mask = kmalloc( depth->n * sizeof(u8), 0 );
+		if ( mask == NULL ) {
+			kfree( x );
+			kfree( y );
+			kfree( buffer );
+			return -ENOMEM;
+		}
+		if ( copy_from_user( mask, depth->mask,
+				     depth->n * sizeof(u8) ) ) {
+			kfree( x );
+			kfree( y );
+			kfree( buffer );
+			kfree( mask );
+			return -EFAULT;
+		}
+
+		for ( i = 0 ; i < count ; i++ ) {
+			if ( mask[i] ) {
+				BEGIN_RING( 6 );
+
+				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI,
+						       4 ) );
+				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+					  | R128_GMC_BRUSH_SOLID_COLOR
+					  | depth_bpp
+					  | R128_GMC_SRC_DATATYPE_COLOR
+					  | R128_ROP3_P
+					  | R128_GMC_CLR_CMP_CNTL_DIS
+					  | R128_GMC_WR_MSK_DIS );
+
+				OUT_RING( dev_priv->depth_pitch_offset_c );
+				OUT_RING( buffer[i] );
+
+				OUT_RING( (x[i] << 16) | y[i] );
+				OUT_RING( (1 << 16) | 1 );
+
+				ADVANCE_RING();
+			}
+		}
+
+		kfree( mask );
+	} else {
+		for ( i = 0 ; i < count ; i++ ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL
+				  | R128_GMC_BRUSH_SOLID_COLOR
+				  | depth_bpp
+				  | R128_GMC_SRC_DATATYPE_COLOR
+				  | R128_ROP3_P
+				  | R128_GMC_CLR_CMP_CNTL_DIS
+				  | R128_GMC_WR_MSK_DIS );
+
+			OUT_RING( dev_priv->depth_pitch_offset_c );
+			OUT_RING( buffer[i] );
+
+			OUT_RING( (x[i] << 16) | y[i] );
+			OUT_RING( (1 << 16) | 1 );
+
+			ADVANCE_RING();
+		}
+	}
+
+	kfree( x );
+	kfree( y );
+	kfree( buffer );
+
+	return 0;
+}
+
+static int r128_cce_dispatch_read_span( drm_device_t *dev,
+					drm_r128_depth_t *depth )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	int count, x, y;
+	u32 depth_bpp;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	switch ( dev_priv->depth_bpp ) {
+	case 16:
+		depth_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 24:
+	case 32:
+		depth_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	count = depth->n;
+	if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
+		return -EFAULT;
+	}
+	if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
+		return -EFAULT;
+	}
+
+	BEGIN_RING( 7 );
+
+	OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
+	OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL
+		  | R128_GMC_DST_PITCH_OFFSET_CNTL
+		  | R128_GMC_BRUSH_NONE
+		  | depth_bpp
+		  | R128_GMC_SRC_DATATYPE_COLOR
+		  | R128_ROP3_S
+		  | R128_DP_SRC_SOURCE_MEMORY
+		  | R128_GMC_CLR_CMP_CNTL_DIS
+		  | R128_GMC_WR_MSK_DIS );
+
+	OUT_RING( dev_priv->depth_pitch_offset_c );
+	OUT_RING( dev_priv->span_pitch_offset_c );
+
+	OUT_RING( (x << 16) | y );
+	OUT_RING( (0 << 16) | 0 );
+	OUT_RING( (count << 16) | 1 );
+
+	ADVANCE_RING();
+
+	return 0;
+}
+
+static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
+					  drm_r128_depth_t *depth )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	int count, *x, *y;
+	u32 depth_bpp;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	switch ( dev_priv->depth_bpp ) {
+	case 16:
+		depth_bpp = R128_GMC_DST_16BPP;
+		break;
+	case 24:
+	case 32:
+		depth_bpp = R128_GMC_DST_32BPP;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	count = depth->n;
+	if ( count > dev_priv->depth_pitch ) {
+		count = dev_priv->depth_pitch;
+	}
+
+	x = kmalloc( count * sizeof(*x), 0 );
+	if ( x == NULL ) {
+		return -ENOMEM;
+	}
+	y = kmalloc( count * sizeof(*y), 0 );
+	if ( y == NULL ) {
+		kfree( x );
+		return -ENOMEM;
+	}
+	if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
+		kfree( x );
+		kfree( y );
+		return -EFAULT;
+	}
+	if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
+		kfree( x );
+		kfree( y );
+		return -EFAULT;
+	}
+
+	for ( i = 0 ; i < count ; i++ ) {
+		BEGIN_RING( 7 );
+
+		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
+		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL
+			  | R128_GMC_DST_PITCH_OFFSET_CNTL
+			  | R128_GMC_BRUSH_NONE
+			  | depth_bpp
+			  | R128_GMC_SRC_DATATYPE_COLOR
+			  | R128_ROP3_S
+			  | R128_DP_SRC_SOURCE_MEMORY
+			  | R128_GMC_CLR_CMP_CNTL_DIS
+			  | R128_GMC_WR_MSK_DIS );
+
+		OUT_RING( dev_priv->depth_pitch_offset_c );
+		OUT_RING( dev_priv->span_pitch_offset_c );
+
+		OUT_RING( (x[i] << 16) | y[i] );
+		OUT_RING( (i << 16) | 0 );
+		OUT_RING( (1 << 16) | 1 );
+
+		ADVANCE_RING();
+	}
+
+	kfree( x );
+	kfree( y );
+
+	return 0;
+}
+
+
+/* ================================================================
+ * Polygon stipple
+ */
+
+static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
+{
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	r128_update_ring_snapshot( dev_priv );
+
+	BEGIN_RING( 33 );
+
+	OUT_RING(  CCE_PACKET0( R128_BRUSH_DATA0, 31 ) );
+	for ( i = 0 ; i < 32 ; i++ ) {
+		OUT_RING( stipple[i] );
+	}
+
+	ADVANCE_RING();
+}
+
+
+/* ================================================================
+ * IOCTL functions
+ */
+
+int r128_cce_clear( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_clear_t clear;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "r128_cce_clear called without lock held\n" );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &clear, (drm_r128_clear_t *) arg,
+			     sizeof(clear) ) )
+		return -EFAULT;
+
+	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
+		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
+
+	r128_cce_dispatch_clear( dev, clear.flags,
+				 clear.x, clear.y, clear.w, clear.h,
+				 clear.clear_color, clear.clear_depth );
+
+	/* Make sure we restore the 3D state next time.
+	 */
+	dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
+
+	return 0;
+}
+
+int r128_cce_swap( struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "r128_cce_swap called without lock held\n" );
+		return -EINVAL;
+	}
+
+	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
+		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
+
+	r128_cce_dispatch_swap( dev );
+
+	/* Make sure we restore the 3D state next time.
+	 */
+	dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
+
+	return 0;
+}
+
+int r128_cce_vertex( struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_r128_buf_priv_t *buf_priv;
+	drm_r128_vertex_t vertex;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv || dev_priv->is_pci ) {
+		DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &vertex, (drm_r128_vertex_t *)arg,
+			     sizeof(vertex) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
+		   __FUNCTION__, current->pid,
+		   vertex.idx, vertex.count, vertex.discard );
+
+	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   vertex.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+	if ( vertex.prim < 0 ||
+	     vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
+		DRM_ERROR( "buffer prim %d\n", vertex.prim );
+		return -EINVAL;
+	}
+
+	buf = dma->buflist[vertex.idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
+		return -EINVAL;
+	}
+
+	buf->used = vertex.count;
+	buf_priv->prim = vertex.prim;
+	buf_priv->discard = vertex.discard;
+
+	r128_cce_dispatch_vertex( dev, buf );
+
+	return 0;
+}
+
+int r128_cce_indices( struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_r128_buf_priv_t *buf_priv;
+	drm_r128_indices_t elts;
+	int count;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv || dev_priv->is_pci ) {
+		DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &elts, (drm_r128_indices_t *)arg,
+			     sizeof(elts) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n",
+		   __FUNCTION__, current->pid,
+		   elts.idx, elts.start, elts.end, elts.discard );
+
+	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   elts.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+	if ( elts.prim < 0 ||
+	     elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
+		DRM_ERROR( "buffer prim %d\n", elts.prim );
+		return -EINVAL;
+	}
+
+	buf = dma->buflist[elts.idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
+		return -EINVAL;
+	}
+
+	count = (elts.end - elts.start) / sizeof(u16);
+	elts.start -= R128_INDEX_PRIM_OFFSET;
+
+	if ( elts.start & 0x7 ) {
+		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
+		return -EINVAL;
+	}
+	if ( elts.start < buf->used ) {
+		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
+		return -EINVAL;
+	}
+
+	buf->used = elts.end;
+	buf_priv->prim = elts.prim;
+	buf_priv->discard = elts.discard;
+
+	r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
+
+	return 0;
+}
+
+int r128_cce_blit( struct inode *inode, struct file *filp,
+		   unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	drm_r128_blit_t blit;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &blit, (drm_r128_blit_t *)arg,
+			     sizeof(blit) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d index=%d\n",
+		   __FUNCTION__, current->pid, blit.idx );
+
+	if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   blit.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+
+	return r128_cce_dispatch_blit( dev, &blit );
+}
+
+int r128_cce_depth( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_depth_t depth;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &depth, (drm_r128_depth_t *)arg,
+			     sizeof(depth) ) )
+		return -EFAULT;
+
+	switch ( depth.func ) {
+	case R128_WRITE_SPAN:
+		return r128_cce_dispatch_write_span( dev, &depth );
+	case R128_WRITE_PIXELS:
+		return r128_cce_dispatch_write_pixels( dev, &depth );
+	case R128_READ_SPAN:
+		return r128_cce_dispatch_read_span( dev, &depth );
+	case R128_READ_PIXELS:
+		return r128_cce_dispatch_read_pixels( dev, &depth );
+	}
+
+	return -EINVAL;
+}
+
+int r128_cce_stipple( struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_r128_stipple_t stipple;
+	u32 mask[32];
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &stipple, (drm_r128_stipple_t *)arg,
+			     sizeof(stipple) ) )
+		return -EFAULT;
+
+	if ( copy_from_user( &mask, stipple.mask,
+			     32 * sizeof(u32) ) )
+		return -EFAULT;
+
+	r128_cce_dispatch_stipple( dev, mask );
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_bufs.c lia64-2.4/drivers/char/drm-4.0/radeon_bufs.c
--- linux-2.4.16/drivers/char/drm-4.0/radeon_bufs.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_bufs.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,312 @@
+/* radeon_bufs.c -- IOCTLs to manage buffers -*- linux-c -*-
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Kevin E. Martin <martin@valinux.com>
+ *          Rickard E. (Rik) Faith <faith@valinux.com>
+ *	    Jeff Hartmann <jhartmann@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include <linux/config.h>
+#include "drmP.h"
+#include "radeon_drv.h"
+#include "linux/un.h"
+
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+int radeon_addbufs_agp(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg)
+{
+	drm_file_t       *priv = filp->private_data;
+	drm_device_t     *dev  = priv->dev;
+	drm_device_dma_t *dma  = dev->dma;
+	drm_buf_desc_t    request;
+	drm_buf_entry_t  *entry;
+	drm_buf_t        *buf;
+	unsigned long     offset;
+	unsigned long     agp_offset;
+	int               count;
+	int               order;
+	int               size;
+	int               alignment;
+	int               page_order;
+	int               total;
+	int               byte_count;
+	int               i;
+
+	if (!dma) return -EINVAL;
+
+	if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request)))
+		return -EFAULT;
+
+	count      = request.count;
+	order      = drm_order(request.size);
+	size       = 1 << order;
+
+	alignment  = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size;
+	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+	total      = PAGE_SIZE << page_order;
+
+	byte_count = 0;
+	agp_offset = dev->agp->base + request.agp_start;
+
+	DRM_DEBUG("count:      %d\n",  count);
+	DRM_DEBUG("order:      %d\n",  order);
+	DRM_DEBUG("size:       %d\n",  size);
+	DRM_DEBUG("agp_offset: %ld\n", agp_offset);
+	DRM_DEBUG("alignment:  %d\n",  alignment);
+	DRM_DEBUG("page_order: %d\n",  page_order);
+	DRM_DEBUG("total:      %d\n",  total);
+
+	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL;
+	if (dev->queue_count) return -EBUSY; /* Not while in use */
+
+	spin_lock(&dev->count_lock);
+	if (dev->buf_use) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	atomic_inc(&dev->buf_alloc);
+	spin_unlock(&dev->count_lock);
+
+	down(&dev->struct_sem);
+	entry = &dma->bufs[order];
+	if (entry->buf_count) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM; /* May only call once for each order */
+	}
+
+	/* Might be too low a limit. XFree folks need to fix this properly */
+	
+	if(count < 0 || count > 4096)
+	{
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -EINVAL;
+	}
+		
+	entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
+				   DRM_MEM_BUFS);
+	if (!entry->buflist) {
+		up(&dev->struct_sem);
+		atomic_dec(&dev->buf_alloc);
+		return -ENOMEM;
+	}
+	memset(entry->buflist, 0, count * sizeof(*entry->buflist));
+
+	entry->buf_size   = size;
+	entry->page_order = page_order;
+	offset            = 0;
+
+	for (offset = 0;
+	     entry->buf_count < count;
+	     offset += alignment, ++entry->buf_count) {
+		buf          = &entry->buflist[entry->buf_count];
+		buf->idx     = dma->buf_count + entry->buf_count;
+		buf->total   = alignment;
+		buf->order   = order;
+		buf->used    = 0;
+		buf->offset  = (dma->byte_count + offset);
+		buf->address = (void *)(agp_offset + offset);
+		buf->next    = NULL;
+		buf->waiting = 0;
+		buf->pending = 0;
+		init_waitqueue_head(&buf->dma_wait);
+		buf->pid     = 0;
+
+		buf->dev_priv_size = sizeof(drm_radeon_buf_priv_t);
+		buf->dev_private   = drm_alloc(sizeof(drm_radeon_buf_priv_t),
+					       DRM_MEM_BUFS);
+                if (!buf->dev_private) {
+                        up(&dev->struct_sem);
+                        atomic_dec(&dev->buf_alloc);
+                        return -ENOMEM;
+                }
+		memset(buf->dev_private, 0, buf->dev_priv_size);
+
+#if DRM_DMA_HISTOGRAM
+		buf->time_queued     = 0;
+		buf->time_dispatched = 0;
+		buf->time_completed  = 0;
+		buf->time_freed      = 0;
+#endif
+
+		byte_count += PAGE_SIZE << page_order;
+
+		DRM_DEBUG("buffer %d @ %p\n",
+			  entry->buf_count, buf->address);
+	}
+
+	DRM_DEBUG("byte_count: %d\n", byte_count);
+
+	dma->buflist = drm_realloc(dma->buflist,
+				   dma->buf_count * sizeof(*dma->buflist),
+				   (dma->buf_count + entry->buf_count)
+				   * sizeof(*dma->buflist),
+				   DRM_MEM_BUFS);
+	for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++)
+		dma->buflist[i] = &entry->buflist[i - dma->buf_count];
+
+	dma->buf_count  += entry->buf_count;
+	dma->byte_count += byte_count;
+
+	drm_freelist_create(&entry->freelist, entry->buf_count);
+	for (i = 0; i < entry->buf_count; i++) {
+		drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]);
+	}
+
+	up(&dev->struct_sem);
+
+	request.count = entry->buf_count;
+	request.size  = size;
+
+	if (copy_to_user((drm_buf_desc_t *)arg, &request, sizeof(request)))
+		return -EFAULT;
+
+	dma->flags = _DRM_DMA_USE_AGP;
+
+	atomic_dec(&dev->buf_alloc);
+	return 0;
+}
+#endif
+
+int radeon_addbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t		*priv		= filp->private_data;
+	drm_device_t		*dev		= priv->dev;
+	drm_radeon_private_t	*dev_priv	= dev->dev_private;
+	drm_buf_desc_t		request;
+
+	if (!dev_priv || dev_priv->is_pci) return -EINVAL;
+
+	if (copy_from_user(&request, (drm_buf_desc_t *)arg, sizeof(request)))
+		return -EFAULT;
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	if (request.flags & _DRM_AGP_BUFFER)
+		return radeon_addbufs_agp(inode, filp, cmd, arg);
+	else
+#endif
+		return -EINVAL;
+}
+
+int radeon_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t		*priv		= filp->private_data;
+	drm_device_t		*dev		= priv->dev;
+	drm_radeon_private_t	*dev_priv	= dev->dev_private;
+	drm_device_dma_t	*dma		= dev->dma;
+	int			 retcode	= 0;
+	const int		 zero		= 0;
+	unsigned long		 virtual;
+	unsigned long		 address;
+	drm_buf_map_t		 request;
+	int			 i;
+
+	if (!dma || !dev_priv || dev_priv->is_pci) return -EINVAL;
+
+	DRM_DEBUG("\n");
+
+	spin_lock(&dev->count_lock);
+	if (atomic_read(&dev->buf_alloc)) {
+		spin_unlock(&dev->count_lock);
+		return -EBUSY;
+	}
+	++dev->buf_use;		/* Can't allocate more after this call */
+	spin_unlock(&dev->count_lock);
+
+	if (copy_from_user(&request, (drm_buf_map_t *)arg, sizeof(request)))
+		return -EFAULT;
+
+	if (request.count >= dma->buf_count) {
+		if (dma->flags & _DRM_DMA_USE_AGP) {
+			drm_map_t *map;
+
+			map = dev_priv->buffers;
+			if (!map) {
+				retcode = -EINVAL;
+				goto done;
+			}
+
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, map->size,
+					  PROT_READ|PROT_WRITE,
+					  MAP_SHARED,
+					  (unsigned long)map->offset);
+			up_write(&current->mm->mmap_sem);
+		} else {
+			down_write(&current->mm->mmap_sem);
+			virtual = do_mmap(filp, 0, dma->byte_count,
+					  PROT_READ|PROT_WRITE, MAP_SHARED, 0);
+			up_write(&current->mm->mmap_sem);
+		}
+		if (virtual > -1024UL) {
+			/* Real error */
+			retcode = (signed long)virtual;
+			goto done;
+		}
+		request.virtual = (void *)virtual;
+
+		for (i = 0; i < dma->buf_count; i++) {
+			if (copy_to_user(&request.list[i].idx,
+					 &dma->buflist[i]->idx,
+					 sizeof(request.list[0].idx))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].total,
+					 &dma->buflist[i]->total,
+					 sizeof(request.list[0].total))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			if (copy_to_user(&request.list[i].used,
+					 &zero,
+					 sizeof(zero))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+			address = virtual + dma->buflist[i]->offset;
+			if (copy_to_user(&request.list[i].address,
+					 &address,
+					 sizeof(address))) {
+				retcode = -EFAULT;
+				goto done;
+			}
+		}
+	}
+ done:
+	request.count = dma->buf_count;
+	DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode);
+
+	if (copy_to_user((drm_buf_map_t *)arg, &request, sizeof(request)))
+		return -EFAULT;
+
+	return retcode;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_context.c lia64-2.4/drivers/char/drm-4.0/radeon_context.c
--- linux-2.4.16/drivers/char/drm-4.0/radeon_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_context.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,215 @@
+/* radeon_context.c -- IOCTLs for Radeon contexts -*- linux-c -*-
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Kevin E. Martin <martin@valinux.com>
+ *         Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "radeon_drv.h"
+
+extern drm_ctx_t radeon_res_ctx;
+
+static int radeon_alloc_queue(drm_device_t *dev)
+{
+	return drm_ctxbitmap_next(dev);
+}
+
+int radeon_context_switch(drm_device_t *dev, int old, int new)
+{
+        char        buf[64];
+
+        atomic_inc(&dev->total_ctx);
+
+        if (test_and_set_bit(0, &dev->context_flag)) {
+                DRM_ERROR("Reentering -- FIXME\n");
+                return -EBUSY;
+        }
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context) {
+                clear_bit(0, &dev->context_flag);
+                return 0;
+        }
+
+        if (drm_flags & DRM_FLAG_NOCTX) {
+                radeon_context_switch_complete(dev, new);
+        } else {
+                sprintf(buf, "C %d %d\n", old, new);
+                drm_write_string(dev, buf);
+        }
+
+        return 0;
+}
+
+int radeon_context_switch_complete(drm_device_t *dev, int new)
+{
+        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+        dev->last_switch  = jiffies;
+
+        if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+                DRM_ERROR("Lock isn't held after context switch\n");
+        }
+
+				/* If a context switch is ever initiated
+                                   when the kernel holds the lock, release
+                                   that lock here. */
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+                                                      - dev->ctx_start)]);
+
+#endif
+        clear_bit(0, &dev->context_flag);
+        wake_up(&dev->context_wait);
+
+        return 0;
+}
+
+
+int radeon_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i], &i, sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+
+int radeon_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = radeon_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Skip kernel's context and get a new one. */
+		ctx.handle = radeon_alloc_queue(dev);
+	}
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (ctx.handle == -1) {
+		DRM_DEBUG("Not enough free contexts.\n");
+				/* Should this return -EBUSY instead? */
+		return -ENOMEM;
+	}
+
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int radeon_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	if (ctx.flags==_DRM_CONTEXT_PRESERVED)
+		radeon_res_ctx.handle=ctx.handle;
+	return 0;
+}
+
+int radeon_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	/* This is 0, because we don't hanlde any context flags */
+	ctx.flags = 0;
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int radeon_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		     unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return radeon_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int radeon_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	radeon_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int radeon_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	drm_ctxbitmap_free(dev, ctx.handle);
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_cp.c lia64-2.4/drivers/char/drm-4.0/radeon_cp.c
--- linux-2.4.16/drivers/char/drm-4.0/radeon_cp.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_cp.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,1353 @@
+/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *   Kevin E. Martin <martin@valinux.com>
+ *   Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "radeon_drv.h"
+
+#include <linux/interrupt.h>	/* For task queue support */
+#include <linux/delay.h>
+
+#define RADEON_FIFO_DEBUG	0
+
+
+/* CP microcode (from ATI) */
+static u32 radeon_cp_microcode[][2] = {
+	{ 0x21007000, 0000000000 },
+	{ 0x20007000, 0000000000 },
+	{ 0x000000b4, 0x00000004 },
+	{ 0x000000b8, 0x00000004 },
+	{ 0x6f5b4d4c, 0000000000 },
+	{ 0x4c4c427f, 0000000000 },
+	{ 0x5b568a92, 0000000000 },
+	{ 0x4ca09c6d, 0000000000 },
+	{ 0xad4c4c4c, 0000000000 },
+	{ 0x4ce1af3d, 0000000000 },
+	{ 0xd8afafaf, 0000000000 },
+	{ 0xd64c4cdc, 0000000000 },
+	{ 0x4cd10d10, 0000000000 },
+	{ 0x000f0000, 0x00000016 },
+	{ 0x362f242d, 0000000000 },
+	{ 0x00000012, 0x00000004 },
+	{ 0x000f0000, 0x00000016 },
+	{ 0x362f282d, 0000000000 },
+	{ 0x000380e7, 0x00000002 },
+	{ 0x04002c97, 0x00000002 },
+	{ 0x000f0001, 0x00000016 },
+	{ 0x333a3730, 0000000000 },
+	{ 0x000077ef, 0x00000002 },
+	{ 0x00061000, 0x00000002 },
+	{ 0x00000021, 0x0000001a },
+	{ 0x00004000, 0x0000001e },
+	{ 0x00061000, 0x00000002 },
+	{ 0x00000021, 0x0000001a },
+	{ 0x00004000, 0x0000001e },
+	{ 0x00061000, 0x00000002 },
+	{ 0x00000021, 0x0000001a },
+	{ 0x00004000, 0x0000001e },
+	{ 0x00000017, 0x00000004 },
+	{ 0x0003802b, 0x00000002 },
+	{ 0x040067e0, 0x00000002 },
+	{ 0x00000017, 0x00000004 },
+	{ 0x000077e0, 0x00000002 },
+	{ 0x00065000, 0x00000002 },
+	{ 0x000037e1, 0x00000002 },
+	{ 0x040067e1, 0x00000006 },
+	{ 0x000077e0, 0x00000002 },
+	{ 0x000077e1, 0x00000002 },
+	{ 0x000077e1, 0x00000006 },
+	{ 0xffffffff, 0000000000 },
+	{ 0x10000000, 0000000000 },
+	{ 0x0003802b, 0x00000002 },
+	{ 0x040067e0, 0x00000006 },
+	{ 0x00007675, 0x00000002 },
+	{ 0x00007676, 0x00000002 },
+	{ 0x00007677, 0x00000002 },
+	{ 0x00007678, 0x00000006 },
+	{ 0x0003802c, 0x00000002 },
+	{ 0x04002676, 0x00000002 },
+	{ 0x00007677, 0x00000002 },
+	{ 0x00007678, 0x00000006 },
+	{ 0x0000002f, 0x00000018 },
+	{ 0x0000002f, 0x00000018 },
+	{ 0000000000, 0x00000006 },
+	{ 0x00000030, 0x00000018 },
+	{ 0x00000030, 0x00000018 },
+	{ 0000000000, 0x00000006 },
+	{ 0x01605000, 0x00000002 },
+	{ 0x00065000, 0x00000002 },
+	{ 0x00098000, 0x00000002 },
+	{ 0x00061000, 0x00000002 },
+	{ 0x64c0603e, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00080000, 0x00000016 },
+	{ 0000000000, 0000000000 },
+	{ 0x0400251d, 0x00000002 },
+	{ 0x00007580, 0x00000002 },
+	{ 0x00067581, 0x00000002 },
+	{ 0x04002580, 0x00000002 },
+	{ 0x00067581, 0x00000002 },
+	{ 0x00000049, 0x00000004 },
+	{ 0x00005000, 0000000000 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00061000, 0x00000002 },
+	{ 0x0000750e, 0x00000002 },
+	{ 0x00019000, 0x00000002 },
+	{ 0x00011055, 0x00000014 },
+	{ 0x00000055, 0x00000012 },
+	{ 0x0400250f, 0x00000002 },
+	{ 0x0000504f, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00007565, 0x00000002 },
+	{ 0x00007566, 0x00000002 },
+	{ 0x00000058, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x01e655b4, 0x00000002 },
+	{ 0x4401b0e4, 0x00000002 },
+	{ 0x01c110e4, 0x00000002 },
+	{ 0x26667066, 0x00000018 },
+	{ 0x040c2565, 0x00000002 },
+	{ 0x00000066, 0x00000018 },
+	{ 0x04002564, 0x00000002 },
+	{ 0x00007566, 0x00000002 },
+	{ 0x0000005d, 0x00000004 },
+	{ 0x00401069, 0x00000008 },
+	{ 0x00101000, 0x00000002 },
+	{ 0x000d80ff, 0x00000002 },
+	{ 0x0080006c, 0x00000008 },
+	{ 0x000f9000, 0x00000002 },
+	{ 0x000e00ff, 0x00000002 },
+	{ 0000000000, 0x00000006 },
+	{ 0x0000008f, 0x00000018 },
+	{ 0x0000005b, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00007576, 0x00000002 },
+	{ 0x00065000, 0x00000002 },
+	{ 0x00009000, 0x00000002 },
+	{ 0x00041000, 0x00000002 },
+	{ 0x0c00350e, 0x00000002 },
+	{ 0x00049000, 0x00000002 },
+	{ 0x00051000, 0x00000002 },
+	{ 0x01e785f8, 0x00000002 },
+	{ 0x00200000, 0x00000002 },
+	{ 0x0060007e, 0x0000000c },
+	{ 0x00007563, 0x00000002 },
+	{ 0x006075f0, 0x00000021 },
+	{ 0x20007073, 0x00000004 },
+	{ 0x00005073, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00007576, 0x00000002 },
+	{ 0x00007577, 0x00000002 },
+	{ 0x0000750e, 0x00000002 },
+	{ 0x0000750f, 0x00000002 },
+	{ 0x00a05000, 0x00000002 },
+	{ 0x00600083, 0x0000000c },
+	{ 0x006075f0, 0x00000021 },
+	{ 0x000075f8, 0x00000002 },
+	{ 0x00000083, 0x00000004 },
+	{ 0x000a750e, 0x00000002 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x0020750f, 0x00000002 },
+	{ 0x00600086, 0x00000004 },
+	{ 0x00007570, 0x00000002 },
+	{ 0x00007571, 0x00000002 },
+	{ 0x00007572, 0x00000006 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00005000, 0x00000002 },
+	{ 0x00a05000, 0x00000002 },
+	{ 0x00007568, 0x00000002 },
+	{ 0x00061000, 0x00000002 },
+	{ 0x00000095, 0x0000000c },
+	{ 0x00058000, 0x00000002 },
+	{ 0x0c607562, 0x00000002 },
+	{ 0x00000097, 0x00000004 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x00600096, 0x00000004 },
+	{ 0x400070e5, 0000000000 },
+	{ 0x000380e6, 0x00000002 },
+	{ 0x040025c5, 0x00000002 },
+	{ 0x000380e5, 0x00000002 },
+	{ 0x000000a8, 0x0000001c },
+	{ 0x000650aa, 0x00000018 },
+	{ 0x040025bb, 0x00000002 },
+	{ 0x000610ab, 0x00000018 },
+	{ 0x040075bc, 0000000000 },
+	{ 0x000075bb, 0x00000002 },
+	{ 0x000075bc, 0000000000 },
+	{ 0x00090000, 0x00000006 },
+	{ 0x00090000, 0x00000002 },
+	{ 0x000d8002, 0x00000006 },
+	{ 0x00007832, 0x00000002 },
+	{ 0x00005000, 0x00000002 },
+	{ 0x000380e7, 0x00000002 },
+	{ 0x04002c97, 0x00000002 },
+	{ 0x00007820, 0x00000002 },
+	{ 0x00007821, 0x00000002 },
+	{ 0x00007800, 0000000000 },
+	{ 0x01200000, 0x00000002 },
+	{ 0x20077000, 0x00000002 },
+	{ 0x01200000, 0x00000002 },
+	{ 0x20007000, 0x00000002 },
+	{ 0x00061000, 0x00000002 },
+	{ 0x0120751b, 0x00000002 },
+	{ 0x8040750a, 0x00000002 },
+	{ 0x8040750b, 0x00000002 },
+	{ 0x00110000, 0x00000002 },
+	{ 0x000380e5, 0x00000002 },
+	{ 0x000000c6, 0x0000001c },
+	{ 0x000610ab, 0x00000018 },
+	{ 0x844075bd, 0x00000002 },
+	{ 0x000610aa, 0x00000018 },
+	{ 0x840075bb, 0x00000002 },
+	{ 0x000610ab, 0x00000018 },
+	{ 0x844075bc, 0x00000002 },
+	{ 0x000000c9, 0x00000004 },
+	{ 0x804075bd, 0x00000002 },
+	{ 0x800075bb, 0x00000002 },
+	{ 0x804075bc, 0x00000002 },
+	{ 0x00108000, 0x00000002 },
+	{ 0x01400000, 0x00000002 },
+	{ 0x006000cd, 0x0000000c },
+	{ 0x20c07000, 0x00000020 },
+	{ 0x000000cf, 0x00000012 },
+	{ 0x00800000, 0x00000006 },
+	{ 0x0080751d, 0x00000006 },
+	{ 0000000000, 0000000000 },
+	{ 0x0000775c, 0x00000002 },
+	{ 0x00a05000, 0x00000002 },
+	{ 0x00661000, 0x00000002 },
+	{ 0x0460275d, 0x00000020 },
+	{ 0x00004000, 0000000000 },
+	{ 0x01e00830, 0x00000002 },
+	{ 0x21007000, 0000000000 },
+	{ 0x6464614d, 0000000000 },
+	{ 0x69687420, 0000000000 },
+	{ 0x00000073, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0x00005000, 0x00000002 },
+	{ 0x000380d0, 0x00000002 },
+	{ 0x040025e0, 0x00000002 },
+	{ 0x000075e1, 0000000000 },
+	{ 0x00000001, 0000000000 },
+	{ 0x000380e0, 0x00000002 },
+	{ 0x04002394, 0x00000002 },
+	{ 0x00005000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0x00000008, 0000000000 },
+	{ 0x00000004, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+	{ 0000000000, 0000000000 },
+};
+
+
+#define DO_IOREMAP(_m, _d) (_m)->handle = drm_ioremap((_m)->offset,	\
+						 	(_m)->size, (_d))
+
+#define DO_IOREMAPFREE(_m, _d)						\
+	do {								\
+		if ((_m)->handle && (_m)->size)				\
+			drm_ioremapfree((_m)->handle, (_m)->size, (_d));\
+	} while (0)
+
+#define DO_FIND_MAP(_m, _o)						\
+	do {								\
+		int _i;							\
+		for (_i = 0; _i < dev->map_count; _i++) {		\
+			if (dev->maplist[_i]->offset == _o) {		\
+				_m = dev->maplist[_i];			\
+				break;					\
+			}						\
+		}							\
+	} while (0)
+
+
+int RADEON_READ_PLL(drm_device_t *dev, int addr)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+}
+
+#if RADEON_FIFO_DEBUG
+static void radeon_status( drm_radeon_private_t *dev_priv )
+{
+	printk( "%s:\n", __FUNCTION__ );
+	printk( "RBBM_STATUS = 0x%08x\n",
+		(unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
+	printk( "CP_RB_RTPR = 0x%08x\n",
+		(unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
+	printk( "CP_RB_WTPR = 0x%08x\n",
+		(unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
+}
+#endif
+
+
+/* ================================================================
+ * Engine, FIFO control
+ */
+
+static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
+{
+	u32 tmp;
+	int i;
+
+	tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
+	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
+	RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
+		       & RADEON_RB2D_DC_BUSY) ) {
+			return 0;
+		}
+		udelay( 1 );
+	}
+
+#if RADEON_FIFO_DEBUG
+	DRM_ERROR( "failed!\n" );
+	radeon_status( dev_priv );
+#endif
+	return -EBUSY;
+}
+
+static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
+				    int entries )
+{
+	int i;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
+			      & RADEON_RBBM_FIFOCNT_MASK );
+		if ( slots >= entries ) return 0;
+		udelay( 1 );
+	}
+
+#if RADEON_FIFO_DEBUG
+	DRM_ERROR( "failed!\n" );
+	radeon_status( dev_priv );
+#endif
+	return -EBUSY;
+}
+
+static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
+{
+	int i, ret;
+
+	ret = radeon_do_wait_for_fifo( dev_priv, 64 );
+	if ( ret < 0 ) return ret;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		if ( !(RADEON_READ( RADEON_RBBM_STATUS )
+		       & RADEON_RBBM_ACTIVE) ) {
+			radeon_do_pixcache_flush( dev_priv );
+			return 0;
+		}
+		udelay( 1 );
+	}
+
+#if RADEON_FIFO_DEBUG
+	DRM_ERROR( "failed!\n" );
+	radeon_status( dev_priv );
+#endif
+	return -EBUSY;
+}
+
+
+/* ================================================================
+ * CP control, initialization
+ */
+
+/* Load the microcode for the CP */
+static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
+{
+	int i;
+
+	radeon_do_wait_for_idle( dev_priv );
+
+	RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
+	for ( i = 0 ; i < 256 ; i++ ) {
+		RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
+			      radeon_cp_microcode[i][1] );
+		RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
+			      radeon_cp_microcode[i][0] );
+	}
+}
+
+/* Flush any pending commands to the CP.  This should only be used just
+ * prior to a wait for idle, as it informs the engine that the command
+ * stream is ending.
+ */
+static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
+{
+#if 0
+	u32 tmp;
+
+	tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
+	RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
+#endif
+}
+
+/* Wait for the CP to go idle.
+ */
+int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
+{
+	RING_LOCALS;
+
+	BEGIN_RING( 6 );
+
+	RADEON_PURGE_CACHE();
+	RADEON_PURGE_ZCACHE();
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
+
+	return radeon_do_wait_for_idle( dev_priv );
+}
+
+/* Start the Command Processor.
+ */
+static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
+{
+	RING_LOCALS;
+
+	radeon_do_wait_for_idle( dev_priv );
+
+	RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
+
+	dev_priv->cp_running = 1;
+
+	BEGIN_RING( 6 );
+
+	RADEON_PURGE_CACHE();
+	RADEON_PURGE_ZCACHE();
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
+}
+
+/* Reset the Command Processor.  This will not flush any pending
+ * commands, so you must wait for the CP command stream to complete
+ * before calling this routine.
+ */
+static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
+{
+	u32 cur_read_ptr;
+
+	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
+	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
+	*dev_priv->ring.head = cur_read_ptr;
+	dev_priv->ring.tail = cur_read_ptr;
+}
+
+/* Stop the Command Processor.  This will not flush any pending
+ * commands, so you must flush the command stream and wait for the CP
+ * to go idle before calling this routine.
+ */
+static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
+{
+	RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
+
+	dev_priv->cp_running = 0;
+}
+
+/* Reset the engine.  This will stop the CP if it is running.
+ */
+static int radeon_do_engine_reset( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	radeon_do_pixcache_flush( dev_priv );
+
+	clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
+	mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
+
+	/* FIXME: remove magic number here and in radeon ddx driver!!! */
+	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl | 0x003f00000 );
+
+	rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
+
+	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
+						RADEON_SOFT_RESET_CP |
+						RADEON_SOFT_RESET_HI |
+						RADEON_SOFT_RESET_SE |
+						RADEON_SOFT_RESET_RE |
+						RADEON_SOFT_RESET_PP |
+						RADEON_SOFT_RESET_E2 |
+						RADEON_SOFT_RESET_RB |
+						RADEON_SOFT_RESET_HDP ) );
+	RADEON_READ( RADEON_RBBM_SOFT_RESET );
+	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
+						~( RADEON_SOFT_RESET_CP |
+						   RADEON_SOFT_RESET_HI |
+						   RADEON_SOFT_RESET_SE |
+						   RADEON_SOFT_RESET_RE |
+						   RADEON_SOFT_RESET_PP |
+						   RADEON_SOFT_RESET_E2 |
+						   RADEON_SOFT_RESET_RB |
+						   RADEON_SOFT_RESET_HDP ) ) );
+	RADEON_READ( RADEON_RBBM_SOFT_RESET );
+
+
+	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
+	RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
+	RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
+
+	/* Reset the CP ring */
+	radeon_do_cp_reset( dev_priv );
+
+	/* The CP is no longer running after an engine reset */
+	dev_priv->cp_running = 0;
+
+	/* Reset any pending vertex, indirect buffers */
+	radeon_freelist_reset( dev );
+
+	return 0;
+}
+
+static void radeon_cp_init_ring_buffer( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	u32 ring_start, cur_read_ptr;
+	u32 tmp;
+
+	/* Initialize the memory controller */
+	RADEON_WRITE( RADEON_MC_FB_LOCATION,
+		      (dev_priv->agp_vm_start - 1) & 0xffff0000 );
+	RADEON_WRITE( RADEON_MC_AGP_LOCATION,
+		      (((dev_priv->agp_vm_start - 1 +
+			 dev_priv->agp_size) & 0xffff0000) |
+		       (dev_priv->agp_vm_start >> 16)) );
+
+	ring_start = (dev_priv->cp_ring->offset
+		      - dev->agp->base
+		      + dev_priv->agp_vm_start);
+
+	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
+
+	/* Set the write pointer delay */
+	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
+
+	/* Initialize the ring buffer's read and write pointers */
+	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
+	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
+
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+	/*
+	 * XXX - This is a 460GX specific hack
+	 *
+	 * We have to hack this right now.  The GXB isn't claiming PCI writes
+	 * from the card into the AGP aperture.  Because of this, we have
+	 * to get space outside of the aperture for RPTR_ADDR.
+	 */
+	if(dev->agp->agp_info.chipset == INTEL_460GX) {
+		dev_priv->ring.head = (void *) 
+					__get_free_page(GFP_KERNEL | GFP_DMA);
+		atomic_inc(&virt_to_page(dev_priv->ring.head)->count);
+		set_bit(PG_locked, &virt_to_page(dev_priv->ring.head)->flags);
+		dev_priv->ring.head = __va(dev_priv->ring.head);
+
+		*dev_priv->ring.head = cur_read_ptr;
+		dev_priv->ring.tail = cur_read_ptr;
+
+		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, __pa(dev_priv->ring.head));
+	} else {
+#else
+	*dev_priv->ring.head = cur_read_ptr;
+	dev_priv->ring.tail = cur_read_ptr;
+
+	RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, dev_priv->ring_rptr->offset );
+#endif
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+	}
+#endif
+	/* Set ring buffer size */
+	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
+
+	radeon_do_wait_for_idle( dev_priv );
+
+	/* Turn off PCI GART */
+	tmp = RADEON_READ( RADEON_AIC_CNTL ) & ~RADEON_PCIGART_TRANSLATE_EN;
+	RADEON_WRITE( RADEON_AIC_CNTL, tmp );
+
+	/* Turn on bus mastering */
+	tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
+	RADEON_WRITE( RADEON_BUS_CNTL, tmp );
+
+	/* Sync everything up */
+	RADEON_WRITE( RADEON_ISYNC_CNTL,
+		      (RADEON_ISYNC_ANY2D_IDLE3D |
+		       RADEON_ISYNC_ANY3D_IDLE2D |
+		       RADEON_ISYNC_WAIT_IDLEGUI |
+		       RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
+}
+
+static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
+{
+	drm_radeon_private_t *dev_priv;
+        int i;
+
+	dev_priv = drm_alloc( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
+	if ( dev_priv == NULL )
+		return -ENOMEM;
+	dev->dev_private = (void *)dev_priv;
+
+	memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
+
+	dev_priv->is_pci = init->is_pci;
+
+	/* We don't support PCI cards until PCI GART is implemented.
+	 * Fail here so we can remove all checks for PCI cards around
+	 * the CP ring code.
+	 */
+	if ( dev_priv->is_pci ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	dev_priv->usec_timeout = init->usec_timeout;
+	if ( dev_priv->usec_timeout < 1 ||
+	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	dev_priv->cp_mode = init->cp_mode;
+
+	/* Simple idle check.
+	 */
+	atomic_set( &dev_priv->idle_count, 0 );
+
+	/* We don't support anything other than bus-mastering ring mode,
+	 * but the ring can be in either AGP or PCI space for the ring
+	 * read pointer.
+	 */
+	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
+	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
+		drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+		return -EINVAL;
+	}
+
+	switch ( init->fb_bpp ) {
+	case 16:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
+		break;
+	case 32:
+	default:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
+		break;
+	}
+	dev_priv->front_offset	= init->front_offset;
+	dev_priv->front_pitch	= init->front_pitch;
+	dev_priv->back_offset	= init->back_offset;
+	dev_priv->back_pitch	= init->back_pitch;
+
+	switch ( init->depth_bpp ) {
+	case 16:
+		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
+		break;
+	case 32:
+	default:
+		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
+		break;
+	}
+	dev_priv->depth_offset	= init->depth_offset;
+	dev_priv->depth_pitch	= init->depth_pitch;
+
+	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
+					(dev_priv->front_offset >> 10));
+	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
+				       (dev_priv->back_offset >> 10));
+	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
+					(dev_priv->depth_offset >> 10));
+
+	/* Hardware state for depth clears.  Remove this if/when we no
+	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
+	 * all values to prevent unwanted 3D state from slipping through
+	 * and screwing with the clear operation.
+	 */
+	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
+					   RADEON_Z_ENABLE |
+					   (dev_priv->color_fmt << 10) |
+					   RADEON_ZBLOCK16);
+
+	dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt |
+						   RADEON_Z_TEST_ALWAYS |
+						   RADEON_STENCIL_TEST_ALWAYS |
+						   RADEON_STENCIL_S_FAIL_KEEP |
+						   RADEON_STENCIL_ZPASS_KEEP |
+						   RADEON_STENCIL_ZFAIL_KEEP |
+						   RADEON_Z_WRITE_ENABLE);
+
+	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
+					 RADEON_BFACE_SOLID |
+					 RADEON_FFACE_SOLID |
+					 RADEON_FLAT_SHADE_VTX_LAST |
+
+					 RADEON_DIFFUSE_SHADE_FLAT |
+					 RADEON_ALPHA_SHADE_FLAT |
+					 RADEON_SPECULAR_SHADE_FLAT |
+					 RADEON_FOG_SHADE_FLAT |
+
+					 RADEON_VTX_PIX_CENTER_OGL |
+					 RADEON_ROUND_MODE_TRUNC |
+					 RADEON_ROUND_PREC_8TH_PIX);
+
+	/* FIXME: We want multiple shared areas, including one shared
+	 * only by the X Server and kernel module.
+	 */
+	for ( i = 0 ; i < dev->map_count ; i++ ) {
+		if ( dev->maplist[i]->type == _DRM_SHM ) {
+			dev_priv->sarea = dev->maplist[i];
+			break;
+		}
+	}
+
+	DO_FIND_MAP( dev_priv->fb, init->fb_offset );
+	DO_FIND_MAP( dev_priv->mmio, init->mmio_offset );
+	DO_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
+	DO_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
+	DO_FIND_MAP( dev_priv->buffers, init->buffers_offset );
+
+	if ( !dev_priv->is_pci ) {
+		DO_FIND_MAP( dev_priv->agp_textures,
+			     init->agp_textures_offset );
+	}
+
+	dev_priv->sarea_priv =
+		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
+				       init->sarea_priv_offset);
+
+	DO_IOREMAP( dev_priv->cp_ring, dev );
+	DO_IOREMAP( dev_priv->ring_rptr, dev );
+	DO_IOREMAP( dev_priv->buffers, dev );
+#if 0
+	if ( !dev_priv->is_pci ) {
+		DO_IOREMAP( dev_priv->agp_textures, dev );
+	}
+#endif
+
+	dev_priv->agp_size = init->agp_size;
+	dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
+	dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
+					- dev->agp->base
+					+ dev_priv->agp_vm_start);
+
+	dev_priv->ring.head = ((__volatile__ u32 *)
+			       dev_priv->ring_rptr->handle);
+
+	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
+	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
+			      + init->ring_size / sizeof(u32));
+	dev_priv->ring.size = init->ring_size;
+	dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
+
+	dev_priv->ring.tail_mask =
+		(dev_priv->ring.size / sizeof(u32)) - 1;
+
+#if 0
+	/* Initialize the scratch register pointer.  This will cause
+	 * the scratch register values to be written out to memory
+	 * whenever they are updated.
+	 * FIXME: This doesn't quite work yet, so we're disabling it
+	 * for the release.
+	 */
+	RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
+					    RADEON_SCRATCH_REG_OFFSET) );
+	RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
+#endif
+
+	dev_priv->scratch = ((__volatile__ u32 *)
+			     dev_priv->ring_rptr->handle +
+			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
+
+	dev_priv->sarea_priv->last_frame = 0;
+	RADEON_WRITE( RADEON_LAST_FRAME_REG,
+		      dev_priv->sarea_priv->last_frame );
+
+	dev_priv->sarea_priv->last_dispatch = 0;
+	RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
+		      dev_priv->sarea_priv->last_dispatch );
+
+	dev_priv->sarea_priv->last_clear = 0;
+	RADEON_WRITE( RADEON_LAST_CLEAR_REG,
+		      dev_priv->sarea_priv->last_clear );
+
+	radeon_cp_load_microcode( dev_priv );
+	radeon_cp_init_ring_buffer( dev );
+	radeon_do_engine_reset( dev );
+
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
+
+	return 0;
+}
+
+static int radeon_do_cleanup_cp( drm_device_t *dev )
+{
+	if ( dev->dev_private ) {
+		drm_radeon_private_t *dev_priv = dev->dev_private;
+
+		DO_IOREMAPFREE( dev_priv->cp_ring, dev );
+		DO_IOREMAPFREE( dev_priv->ring_rptr, dev );
+		DO_IOREMAPFREE( dev_priv->buffers, dev );
+#if 0
+		if ( !dev_priv->is_pci ) {
+			DO_IOREMAPFREE( dev_priv->agp_textures, dev );
+		}
+#endif
+
+#if defined(CONFIG_AGP_I460) && defined(__ia64__)
+		/*
+		 * Free the page we grabbed for RPTR_ADDR.
+		 */
+		if(dev->agp->agp_info.chipset == INTEL_460GX) {
+			atomic_dec(&virt_to_page(dev_priv->ring.head)->count);
+			clear_bit(PG_locked, 
+				     &virt_to_page(dev_priv->ring.head)->flags);
+			wake_up(&virt_to_page(dev_priv->ring.head)->wait);
+			free_page((unsigned long) dev_priv->ring.head);
+		}
+#endif
+		
+		drm_free( dev->dev_private, sizeof(drm_radeon_private_t),
+			  DRM_MEM_DRIVER );
+		dev->dev_private = NULL;
+	}
+
+	return 0;
+}
+
+int radeon_cp_init( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_init_t init;
+
+	if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) )
+		return -EFAULT;
+
+	switch ( init.func ) {
+	case RADEON_INIT_CP:
+		return radeon_do_init_cp( dev, &init );
+	case RADEON_CLEANUP_CP:
+		return radeon_do_cleanup_cp( dev );
+	}
+
+	return -EINVAL;
+}
+
+int radeon_cp_start( struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( dev_priv->cp_running ) {
+		DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
+		return 0;
+	}
+	if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
+		DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
+			   __FUNCTION__, dev_priv->cp_mode );
+		return 0;
+	}
+
+	radeon_do_cp_start( dev_priv );
+
+	return 0;
+}
+
+/* Stop the CP.  The engine must have been idled before calling this
+ * routine.
+ */
+int radeon_cp_stop( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_cp_stop_t stop;
+	int ret;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) )
+		return -EFAULT;
+
+	/* Flush any pending CP commands.  This ensures any outstanding
+	 * commands are exectuted by the engine before we turn it off.
+	 */
+	if ( stop.flush ) {
+		radeon_do_cp_flush( dev_priv );
+	}
+
+	/* If we fail to make the engine go idle, we return an error
+	 * code so that the DRM ioctl wrapper can try again.
+	 */
+	if ( stop.idle ) {
+		ret = radeon_do_cp_idle( dev_priv );
+		if ( ret < 0 ) return ret;
+	}
+
+	/* Finally, we can turn off the CP.  If the engine isn't idle,
+	 * we will get some dropped triangles as they won't be fully
+	 * rendered before the CP is shut down.
+	 */
+	radeon_do_cp_stop( dev_priv );
+
+	/* Reset the engine */
+	radeon_do_engine_reset( dev );
+
+	return 0;
+}
+
+/* Just reset the CP ring.  Called as part of an X Server engine reset.
+ */
+int radeon_cp_reset( struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv ) {
+		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	radeon_do_cp_reset( dev_priv );
+
+	/* The CP is no longer running after an engine reset */
+	dev_priv->cp_running = 0;
+
+	return 0;
+}
+
+int radeon_cp_idle( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	return radeon_do_cp_idle( dev_priv );
+}
+
+int radeon_engine_reset( struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	return radeon_do_engine_reset( dev );
+}
+
+
+/* ================================================================
+ * Fullscreen mode
+ */
+
+static int radeon_do_init_pageflip( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	dev_priv->crtc_offset =      RADEON_READ( RADEON_CRTC_OFFSET );
+	dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
+
+	RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
+	RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
+		      dev_priv->crtc_offset_cntl |
+		      RADEON_CRTC_OFFSET_FLIP_CNTL );
+
+	dev_priv->page_flipping = 1;
+	dev_priv->current_page = 0;
+
+	return 0;
+}
+
+int radeon_do_cleanup_pageflip( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	RADEON_WRITE( RADEON_CRTC_OFFSET,      dev_priv->crtc_offset );
+	RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
+
+	dev_priv->page_flipping = 0;
+	dev_priv->current_page = 0;
+
+	return 0;
+}
+
+int radeon_fullscreen( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg )
+{
+        drm_file_t *priv = filp->private_data;
+        drm_device_t *dev = priv->dev;
+	drm_radeon_fullscreen_t fs;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &fs, (drm_radeon_fullscreen_t *)arg,
+			     sizeof(fs) ) )
+		return -EFAULT;
+
+	switch ( fs.func ) {
+	case RADEON_INIT_FULLSCREEN:
+		return radeon_do_init_pageflip( dev );
+	case RADEON_CLEANUP_FULLSCREEN:
+		return radeon_do_cleanup_pageflip( dev );
+	}
+
+	return -EINVAL;
+}
+
+
+/* ================================================================
+ * Freelist management
+ */
+#define RADEON_BUFFER_USED	0xffffffff
+#define RADEON_BUFFER_FREE	0
+
+#if 0
+static int radeon_freelist_init( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_buf_t *buf;
+	drm_radeon_buf_priv_t *buf_priv;
+	drm_radeon_freelist_t *entry;
+	int i;
+
+	dev_priv->head = drm_alloc( sizeof(drm_radeon_freelist_t),
+				    DRM_MEM_DRIVER );
+	if ( dev_priv->head == NULL )
+		return -ENOMEM;
+
+	memset( dev_priv->head, 0, sizeof(drm_radeon_freelist_t) );
+	dev_priv->head->age = RADEON_BUFFER_USED;
+
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		buf = dma->buflist[i];
+		buf_priv = buf->dev_private;
+
+		entry = drm_alloc( sizeof(drm_radeon_freelist_t),
+				   DRM_MEM_DRIVER );
+		if ( !entry ) return -ENOMEM;
+
+		entry->age = RADEON_BUFFER_FREE;
+		entry->buf = buf;
+		entry->prev = dev_priv->head;
+		entry->next = dev_priv->head->next;
+		if ( !entry->next )
+			dev_priv->tail = entry;
+
+		buf_priv->discard = 0;
+		buf_priv->dispatched = 0;
+		buf_priv->list_entry = entry;
+
+		dev_priv->head->next = entry;
+
+		if ( dev_priv->head->next )
+			dev_priv->head->next->prev = entry;
+	}
+
+	return 0;
+
+}
+#endif
+
+drm_buf_t *radeon_freelist_get( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_buf_priv_t *buf_priv;
+	drm_buf_t *buf;
+	int i, t;
+#if ROTATE_BUFS
+	int start;
+#endif
+
+	/* FIXME: Optimize -- use freelist code */
+
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		buf = dma->buflist[i];
+		buf_priv = buf->dev_private;
+		if ( buf->pid == 0 ) {
+			DRM_DEBUG( "  ret buf=%d last=%d pid=0\n",
+				   buf->idx, dev_priv->last_buf );
+			return buf;
+		}
+		DRM_DEBUG( "    skipping buf=%d pid=%d\n",
+			   buf->idx, buf->pid );
+	}
+
+#if ROTATE_BUFS
+	if ( ++dev_priv->last_buf >= dma->buf_count )
+		dev_priv->last_buf = 0;
+	start = dev_priv->last_buf;
+#endif
+	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
+#if 0
+		/* FIXME: Disable this for now */
+		u32 done_age = dev_priv->scratch[RADEON_LAST_DISPATCH];
+#else
+		u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
+#endif
+#if ROTATE_BUFS
+		for ( i = start ; i < dma->buf_count ; i++ ) {
+#else
+		for ( i = 0 ; i < dma->buf_count ; i++ ) {
+#endif
+			buf = dma->buflist[i];
+			buf_priv = buf->dev_private;
+			if ( buf->pending && buf_priv->age <= done_age ) {
+				/* The buffer has been processed, so it
+				 * can now be used.
+				 */
+				buf->pending = 0;
+				DRM_DEBUG( "  ret buf=%d last=%d age=%d done=%d\n", buf->idx, dev_priv->last_buf, buf_priv->age, done_age );
+				return buf;
+			}
+			DRM_DEBUG( "    skipping buf=%d age=%d done=%d\n",
+				   buf->idx, buf_priv->age,
+				   done_age );
+#if ROTATE_BUFS
+			start = 0;
+#endif
+		}
+		udelay( 1 );
+	}
+
+	DRM_ERROR( "returning NULL!\n" );
+	return NULL;
+}
+
+void radeon_freelist_reset( drm_device_t *dev )
+{
+	drm_device_dma_t *dma = dev->dma;
+#if ROTATE_BUFS
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+#endif
+	int i;
+
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
+	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		drm_buf_t *buf = dma->buflist[i];
+		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
+		buf_priv->age = 0;
+	}
+}
+
+
+/* ================================================================
+ * CP command submission
+ */
+
+int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
+{
+	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
+	int i;
+
+	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
+		ring->space = *ring->head - ring->tail;
+		if ( ring->space <= 0 )
+			ring->space += ring->size;
+
+		if ( ring->space >= n )
+			return 0;
+
+		udelay( 1 );
+	}
+
+	/* FIXME: This return value is ignored in the BEGIN_RING macro! */
+	DRM_ERROR( "failed!\n" );
+	return -EBUSY;
+}
+
+void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
+
+	ring->space = *ring->head - ring->tail;
+	if ( ring->space == 0 )
+		atomic_inc( &dev_priv->idle_count );
+	if ( ring->space <= 0 )
+		ring->space += ring->size;
+}
+
+static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
+{
+	int i;
+	drm_buf_t *buf;
+
+	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
+		buf = radeon_freelist_get( dev );
+		if ( !buf ) return -EAGAIN;
+
+		buf->pid = current->pid;
+
+		if ( copy_to_user( &d->request_indices[i], &buf->idx,
+				   sizeof(buf->idx) ) )
+			return -EFAULT;
+		if ( copy_to_user( &d->request_sizes[i], &buf->total,
+				   sizeof(buf->total) ) )
+			return -EFAULT;
+
+		d->granted_count++;
+	}
+	return 0;
+}
+
+int radeon_cp_buffers( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+	int ret = 0;
+	drm_dma_t d;
+
+	if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
+		return -EFAULT;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	/* Please don't send us buffers.
+	 */
+	if ( d.send_count != 0 ) {
+		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
+			   current->pid, d.send_count );
+		return -EINVAL;
+	}
+
+	/* We'll send you buffers.
+	 */
+	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
+		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
+			   current->pid, d.request_count, dma->buf_count );
+		return -EINVAL;
+	}
+
+	d.granted_count = 0;
+
+	if ( d.request_count ) {
+		ret = radeon_cp_get_buffers( dev, &d );
+	}
+
+	if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
+		return -EFAULT;
+
+	return ret;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_drm.h lia64-2.4/drivers/char/drm-4.0/radeon_drm.h
--- linux-2.4.16/drivers/char/drm-4.0/radeon_drm.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_drm.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,325 @@
+/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
+ *
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#ifndef __RADEON_DRM_H__
+#define __RADEON_DRM_H__
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the X server file (radeon_sarea.h)
+ */
+#ifndef __RADEON_SAREA_DEFINES__
+#define __RADEON_SAREA_DEFINES__
+
+/* What needs to be changed for the current vertex buffer?
+ */
+#define RADEON_UPLOAD_CONTEXT		0x00000001
+#define RADEON_UPLOAD_VERTFMT		0x00000002
+#define RADEON_UPLOAD_LINE		0x00000004
+#define RADEON_UPLOAD_BUMPMAP		0x00000008
+#define RADEON_UPLOAD_MASKS		0x00000010
+#define RADEON_UPLOAD_VIEWPORT		0x00000020
+#define RADEON_UPLOAD_SETUP		0x00000040
+#define RADEON_UPLOAD_TCL		0x00000080
+#define RADEON_UPLOAD_MISC		0x00000100
+#define RADEON_UPLOAD_TEX0		0x00000200
+#define RADEON_UPLOAD_TEX1		0x00000400
+#define RADEON_UPLOAD_TEX2		0x00000800
+#define RADEON_UPLOAD_TEX0IMAGES	0x00001000
+#define RADEON_UPLOAD_TEX1IMAGES	0x00002000
+#define RADEON_UPLOAD_TEX2IMAGES	0x00004000
+#define RADEON_UPLOAD_CLIPRECTS		0x00008000 /* handled client-side */
+#define RADEON_REQUIRE_QUIESCENCE	0x00010000
+#define RADEON_UPLOAD_ALL		0x0001ffff
+
+#define RADEON_FRONT			0x1
+#define RADEON_BACK			0x2
+#define RADEON_DEPTH			0x4
+
+/* Primitive types
+ */
+#define RADEON_POINTS			0x1
+#define RADEON_LINES			0x2
+#define RADEON_LINE_STRIP		0x3
+#define RADEON_TRIANGLES		0x4
+#define RADEON_TRIANGLE_FAN		0x5
+#define RADEON_TRIANGLE_STRIP		0x6
+
+/* Vertex/indirect buffer size
+ */
+#define RADEON_BUFFER_SIZE		16384
+
+/* Byte offsets for indirect buffer data
+ */
+#define RADEON_INDEX_PRIM_OFFSET	20
+#define RADEON_HOSTDATA_BLIT_OFFSET	32
+
+#define RADEON_SCRATCH_REG_OFFSET	32
+
+/* Keep these small for testing
+ */
+#define RADEON_NR_SAREA_CLIPRECTS	12
+
+/* There are 2 heaps (local/AGP).  Each region within a heap is a
+ * minimum of 64k, and there are at most 64 of them per heap.
+ */
+#define RADEON_LOCAL_TEX_HEAP		0
+#define RADEON_AGP_TEX_HEAP		1
+#define RADEON_NR_TEX_HEAPS		2
+#define RADEON_NR_TEX_REGIONS		64
+#define RADEON_LOG_TEX_GRANULARITY	16
+
+#define RADEON_MAX_TEXTURE_LEVELS	11
+#define RADEON_MAX_TEXTURE_UNITS	3
+
+#endif /* __RADEON_SAREA_DEFINES__ */
+
+typedef struct {
+	unsigned int red;
+	unsigned int green;
+	unsigned int blue;
+	unsigned int alpha;
+} radeon_color_regs_t;
+
+typedef struct {
+	/* Context state */
+	unsigned int pp_misc;				/* 0x1c14 */
+	unsigned int pp_fog_color;
+	unsigned int re_solid_color;
+	unsigned int rb3d_blendcntl;
+	unsigned int rb3d_depthoffset;
+	unsigned int rb3d_depthpitch;
+	unsigned int rb3d_zstencilcntl;
+
+	unsigned int pp_cntl;				/* 0x1c38 */
+	unsigned int rb3d_cntl;
+	unsigned int rb3d_coloroffset;
+	unsigned int re_width_height;
+	unsigned int rb3d_colorpitch;
+	unsigned int se_cntl;
+
+	/* Vertex format state */
+	unsigned int se_coord_fmt;			/* 0x1c50 */
+
+	/* Line state */
+	unsigned int re_line_pattern;			/* 0x1cd0 */
+	unsigned int re_line_state;
+
+	unsigned int se_line_width;			/* 0x1db8 */
+
+	/* Bumpmap state */
+	unsigned int pp_lum_matrix;			/* 0x1d00 */
+
+	unsigned int pp_rot_matrix_0;			/* 0x1d58 */
+	unsigned int pp_rot_matrix_1;
+
+	/* Mask state */
+	unsigned int rb3d_stencilrefmask;		/* 0x1d7c */
+	unsigned int rb3d_ropcntl;
+	unsigned int rb3d_planemask;
+
+	/* Viewport state */
+	unsigned int se_vport_xscale;			/* 0x1d98 */
+	unsigned int se_vport_xoffset;
+	unsigned int se_vport_yscale;
+	unsigned int se_vport_yoffset;
+	unsigned int se_vport_zscale;
+	unsigned int se_vport_zoffset;
+
+	/* Setup state */
+	unsigned int se_cntl_status;			/* 0x2140 */
+
+#ifdef TCL_ENABLE
+	/* TCL state */
+	radeon_color_regs_t se_tcl_material_emmissive;	/* 0x2210 */
+	radeon_color_regs_t se_tcl_material_ambient;
+	radeon_color_regs_t se_tcl_material_diffuse;
+	radeon_color_regs_t se_tcl_material_specular;
+	unsigned int se_tcl_shininess;
+	unsigned int se_tcl_output_vtx_fmt;
+	unsigned int se_tcl_output_vtx_sel;
+	unsigned int se_tcl_matrix_select_0;
+	unsigned int se_tcl_matrix_select_1;
+	unsigned int se_tcl_ucp_vert_blend_ctl;
+	unsigned int se_tcl_texture_proc_ctl;
+	unsigned int se_tcl_light_model_ctl;
+	unsigned int se_tcl_per_light_ctl[4];
+#endif
+
+	/* Misc state */
+	unsigned int re_top_left;			/* 0x26c0 */
+	unsigned int re_misc;
+} drm_radeon_context_regs_t;
+
+/* Setup registers for each texture unit
+ */
+typedef struct {
+	unsigned int pp_txfilter;
+	unsigned int pp_txformat;
+	unsigned int pp_txoffset;
+	unsigned int pp_txcblend;
+	unsigned int pp_txablend;
+	unsigned int pp_tfactor;
+
+	unsigned int pp_border_color;
+
+#ifdef CUBIC_ENABLE
+	unsigned int pp_cubic_faces;
+	unsigned int pp_cubic_offset[5];
+#endif
+} drm_radeon_texture_regs_t;
+
+typedef struct {
+	unsigned char next, prev;
+	unsigned char in_use;
+	int age;
+} drm_radeon_tex_region_t;
+
+typedef struct {
+	/* The channel for communication of state information to the kernel
+	 * on firing a vertex buffer.
+	 */
+	drm_radeon_context_regs_t context_state;
+	drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
+	unsigned int dirty;
+	unsigned int vertsize;
+	unsigned int vc_format;
+
+	/* The current cliprects, or a subset thereof.
+	 */
+	drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
+	unsigned int nbox;
+
+	/* Counters for client-side throttling of rendering clients.
+	 */
+	unsigned int last_frame;
+	unsigned int last_dispatch;
+	unsigned int last_clear;
+
+	drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
+	int tex_age[RADEON_NR_TEX_HEAPS];
+	int ctx_owner;
+} drm_radeon_sarea_t;
+
+
+/* WARNING: If you change any of these defines, make sure to change the
+ * defines in the Xserver file (xf86drmRadeon.h)
+ */
+typedef struct drm_radeon_init {
+	enum {
+		RADEON_INIT_CP    = 0x01,
+		RADEON_CLEANUP_CP = 0x02
+	} func;
+	int sarea_priv_offset;
+	int is_pci;
+	int cp_mode;
+	int agp_size;
+	int ring_size;
+	int usec_timeout;
+
+	unsigned int fb_bpp;
+	unsigned int front_offset, front_pitch;
+	unsigned int back_offset, back_pitch;
+	unsigned int depth_bpp;
+	unsigned int depth_offset, depth_pitch;
+
+	unsigned int fb_offset;
+	unsigned int mmio_offset;
+	unsigned int ring_offset;
+	unsigned int ring_rptr_offset;
+	unsigned int buffers_offset;
+	unsigned int agp_textures_offset;
+} drm_radeon_init_t;
+
+typedef struct drm_radeon_cp_stop {
+	int flush;
+	int idle;
+} drm_radeon_cp_stop_t;
+
+typedef struct drm_radeon_fullscreen {
+	enum {
+		RADEON_INIT_FULLSCREEN    = 0x01,
+		RADEON_CLEANUP_FULLSCREEN = 0x02
+	} func;
+} drm_radeon_fullscreen_t;
+
+#define CLEAR_X1	0
+#define CLEAR_Y1	1
+#define CLEAR_X2	2
+#define CLEAR_Y2	3
+#define CLEAR_DEPTH	4
+
+typedef struct drm_radeon_clear {
+	unsigned int flags;
+	int x, y, w, h;
+	unsigned int clear_color;
+	unsigned int clear_depth;
+	union {
+		float f[5];
+		unsigned int ui[5];
+	} rect;
+} drm_radeon_clear_t;
+
+typedef struct drm_radeon_vertex {
+	int prim;
+	int idx;			/* Index of vertex buffer */
+	int count;			/* Number of vertices in buffer */
+	int discard;			/* Client finished with buffer? */
+} drm_radeon_vertex_t;
+
+typedef struct drm_radeon_indices {
+	int prim;
+	int idx;
+	int start;
+	int end;
+	int discard;			/* Client finished with buffer? */
+} drm_radeon_indices_t;
+
+typedef struct drm_radeon_blit {
+	int idx;
+	int pitch;
+	int offset;
+	int format;
+	unsigned short x, y;
+	unsigned short width, height;
+} drm_radeon_blit_t;
+
+typedef struct drm_radeon_stipple {
+	unsigned int *mask;
+} drm_radeon_stipple_t;
+
+typedef struct drm_radeon_indirect {
+	int idx;
+	int start;
+	int end;
+	int discard;
+} drm_radeon_indirect_t;
+
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_drv.c lia64-2.4/drivers/char/drm-4.0/radeon_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/radeon_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,702 @@
+/* radeon_drv.c -- ATI Radeon driver -*- linux-c -*-
+ *
+ * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Kevin E. Martin <martin@valinux.com>
+ *          Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "radeon_drv.h"
+
+#define RADEON_NAME		"radeon"
+#define RADEON_DESC		"ATI Radeon"
+#define RADEON_DATE		"20010105"
+#define RADEON_MAJOR		1
+#define RADEON_MINOR		0
+#define RADEON_PATCHLEVEL	0
+
+static drm_device_t	      radeon_device;
+drm_ctx_t	              radeon_res_ctx;
+
+static struct file_operations radeon_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 radeon_open,
+	flush:	 drm_flush,
+	release: radeon_release,
+	ioctl:	 radeon_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+	poll:	 drm_poll,
+};
+
+static struct miscdevice      radeon_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  RADEON_NAME,
+	fops:  &radeon_fops,
+};
+
+static drm_ioctl_desc_t	      radeon_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]       = { radeon_version,	0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)]    = { drm_getunique,	0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]     = { drm_getmagic,	0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]     = { drm_irq_busid,	0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)]    = { drm_setunique,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	        = { drm_block,		1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]       = { drm_unblock,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)]    = { drm_authmagic,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]       = { drm_addmap,		1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)]      = { radeon_addbufs,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)]     = { drm_markbufs,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)]     = { drm_infobufs,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)]      = { radeon_mapbufs,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)]     = { drm_freebufs,	1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]       = { radeon_addctx,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]        = { radeon_rmctx,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]       = { radeon_modctx,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]       = { radeon_getctx,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)]    = { radeon_switchctx,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]       = { radeon_newctx,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]       = { radeon_resctx,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]      = { drm_adddraw,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]       = { drm_rmdraw,		1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	        = { radeon_cp_buffers,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	        = { radeon_lock,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]        = { radeon_unlock,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]        = { drm_finish,		1, 0 },
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)]   = { drm_agp_acquire,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)]   = { drm_agp_release,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]    = { drm_agp_enable,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]      = { drm_agp_info,	1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]     = { drm_agp_alloc,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]      = { drm_agp_free,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]      = { drm_agp_bind,	1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]    = { drm_agp_unbind,	1, 1 },
+#endif
+
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)]  = { radeon_cp_init,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)]  = { radeon_cp_stop,   1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)]  = { radeon_cp_idle,   1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)]    = { radeon_cp_swap,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)]   = { radeon_cp_clear,   1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)]  = { radeon_cp_vertex,  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_BLIT)]    = { radeon_cp_blit,    1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)]= { radeon_cp_indirect,1, 1 },
+};
+#define RADEON_IOCTL_COUNT DRM_ARRAY_SIZE(radeon_ioctls)
+
+#ifdef MODULE
+static char		      *radeon = NULL;
+#endif
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("radeon");
+MODULE_PARM(radeon, "s");
+
+#ifndef MODULE
+/* radeon_options is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+
+static int __init radeon_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("radeon=", radeon_options);
+#endif
+
+static int radeon_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	drm_dma_setup(dev);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	    = dev->buf;
+	dev->buf_wp	    = dev->buf;
+	dev->buf_end	    = dev->buf + DRM_BSZ;
+	dev->buf_async	    = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	radeon_res_ctx.handle = -1;
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int radeon_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+				/* Clear AGP information */
+	if (dev->agp) {
+		drm_agp_mem_t *entry;
+		drm_agp_mem_t *nexte;
+
+				/* Remove AGP resources, but leave dev->agp
+                                   intact until radeon_cleanup is called. */
+		for (entry = dev->agp->memory; entry; entry = nexte) {
+			nexte = entry->next;
+			if (entry->bound) drm_unbind_agp(entry->memory);
+			drm_free_agp(entry->memory, entry->pages);
+			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
+		}
+		dev->agp->memory = NULL;
+
+		if (dev->agp->acquired)	_drm_agp_release();
+
+		dev->agp->acquired = 0;
+		dev->agp->enabled  = 0;
+	}
+#endif
+
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				/* Do nothing here, because this is all
+                                   handled in the AGP/GART driver. */
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	drm_dma_takedown(dev);
+
+	dev->queue_count     = 0;
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+/* radeon_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init radeon_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &radeon_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(radeon);
+#endif
+
+	if ((retcode = misc_register(&radeon_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", RADEON_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, radeon_misc.minor);
+	dev->name   = RADEON_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	dev->agp    = drm_agp_init();
+      	if (dev->agp == NULL) {
+	   	DRM_ERROR("Cannot initialize agpgart module.\n");
+	   	drm_proc_cleanup();
+	   	misc_deregister(&radeon_misc);
+	   	radeon_takedown(dev);
+	   	return -ENOMEM;
+	}
+
+#ifdef CONFIG_MTRR
+	dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base,
+				      dev->agp->agp_info.aper_size*1024*1024,
+				      MTRR_TYPE_WRCOMB,
+				      1);
+#endif
+#endif
+
+	if((retcode = drm_ctxbitmap_init(dev))) {
+		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+		drm_proc_cleanup();
+		misc_deregister(&radeon_misc);
+		radeon_takedown(dev);
+		return retcode;
+	}
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+		 RADEON_NAME,
+		 RADEON_MAJOR,
+		 RADEON_MINOR,
+		 RADEON_PATCHLEVEL,
+		 RADEON_DATE,
+		 radeon_misc.minor);
+
+	return 0;
+}
+
+/* radeon_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit radeon_cleanup(void)
+{
+	drm_device_t	      *dev = &radeon_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&radeon_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	drm_ctxbitmap_cleanup(dev);
+	radeon_takedown(dev);
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	if (dev->agp) {
+		drm_agp_uninit();
+		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
+		dev->agp = NULL;
+	}
+#endif
+}
+
+module_init(radeon_init);
+module_exit(radeon_cleanup);
+
+
+int radeon_version(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)				     \
+	len = strlen(value);				     \
+	if (len > name##_len) len = name##_len;		     \
+	name##_len = strlen(value);			     \
+	if (len && name) {				     \
+		if (copy_to_user(name, value, len))	     \
+			return -EFAULT;			     \
+	}
+
+	version.version_major	   = RADEON_MAJOR;
+	version.version_minor	   = RADEON_MINOR;
+	version.version_patchlevel = RADEON_PATCHLEVEL;
+
+	DRM_COPY(version.name, RADEON_NAME);
+	DRM_COPY(version.date, RADEON_DATE);
+	DRM_COPY(version.desc, RADEON_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int radeon_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &radeon_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return radeon_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	return retcode;
+}
+
+int radeon_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev = priv->dev;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+
+	/* Force the cleanup of page flipping when required */
+	if ( dev->dev_private ) {
+		drm_radeon_private_t *dev_priv = dev->dev_private;
+		if ( dev_priv->page_flipping ) {
+			radeon_do_cleanup_pageflip( dev );
+		}
+	}
+
+	if (!(retcode = drm_release(inode, filp))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_close);
+		spin_lock(&dev->count_lock);
+		if (!--dev->open_count) {
+			if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+				DRM_ERROR("Device busy: %d %d\n",
+					  atomic_read(&dev->ioctl_count),
+					  dev->blocked);
+				spin_unlock(&dev->count_lock);
+				unlock_kernel();
+				return -EBUSY;
+			}
+			spin_unlock(&dev->count_lock);
+			unlock_kernel();
+			return radeon_takedown(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	unlock_kernel();
+	return retcode;
+}
+
+/* radeon_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+
+int radeon_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= RADEON_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &radeon_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+int radeon_lock(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+        drm_file_t        *priv   = filp->private_data;
+        drm_device_t      *dev    = priv->dev;
+        DECLARE_WAITQUEUE(entry, current);
+        int               ret   = 0;
+        drm_lock_t        lock;
+#if DRM_DMA_HISTOGRAM
+        cycles_t          start;
+
+        dev->lck_start = start = get_cycles();
+#endif
+
+        if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+        if (lock.context == DRM_KERNEL_CONTEXT) {
+                DRM_ERROR("Process %d using kernel context %d\n",
+                          current->pid, lock.context);
+                return -EINVAL;
+        }
+
+        DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+                  lock.context, current->pid, dev->lock.hw_lock->lock,
+                  lock.flags);
+
+        if (lock.context < 0 /* || lock.context >= dev->queue_count */)
+                return -EINVAL;
+
+        if (!ret) {
+                add_wait_queue(&dev->lock.lock_queue, &entry);
+                for (;;) {
+                        current->state = TASK_INTERRUPTIBLE;
+                        if (!dev->lock.hw_lock) {
+                                /* Device has been unregistered */
+                                ret = -EINTR;
+                                break;
+                        }
+                        if (drm_lock_take(&dev->lock.hw_lock->lock,
+                                          lock.context)) {
+                                dev->lock.pid       = current->pid;
+                                dev->lock.lock_time = jiffies;
+                                atomic_inc(&dev->total_locks);
+                                break;  /* Got lock */
+                        }
+
+                                /* Contention */
+                        atomic_inc(&dev->total_sleeps);
+                        schedule();
+                        if (signal_pending(current)) {
+                                ret = -ERESTARTSYS;
+                                break;
+                        }
+                }
+                current->state = TASK_RUNNING;
+                remove_wait_queue(&dev->lock.lock_queue, &entry);
+        }
+
+        if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+                if (lock.flags & _DRM_LOCK_READY) {
+				/* Wait for space in DMA/FIFO */
+		}
+                if (lock.flags & _DRM_LOCK_QUIESCENT) {
+				/* Make hardware quiescent */
+			DRM_DEBUG("not quiescent!\n");
+#if 0
+                        radeon_quiescent(dev);
+#endif
+		}
+        }
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != radeon_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY/4;
+	}
+#endif
+        DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]);
+#endif
+
+        return ret;
+}
+
+
+int radeon_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+				/* FIXME: Try to send data to card here */
+	if (!dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != radeon_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY;
+	}
+#endif
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_drv.h lia64-2.4/drivers/char/drm-4.0/radeon_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/radeon_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_drv.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,709 @@
+/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *   Rickard E. (Rik) Faith <faith@valinux.com>
+ *   Kevin E. Martin <martin@valinux.com>
+ *   Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#ifndef __RADEON_DRV_H__
+#define __RADEON_DRV_H__
+
+typedef struct drm_radeon_freelist {
+   	unsigned int age;
+   	drm_buf_t *buf;
+   	struct drm_radeon_freelist *next;
+   	struct drm_radeon_freelist *prev;
+} drm_radeon_freelist_t;
+
+typedef struct drm_radeon_ring_buffer {
+	u32 *start;
+	u32 *end;
+	int size;
+	int size_l2qw;
+
+	volatile u32 *head;
+	u32 tail;
+	u32 tail_mask;
+	int space;
+} drm_radeon_ring_buffer_t;
+
+typedef struct drm_radeon_depth_clear_t {
+	u32 rb3d_cntl;
+	u32 rb3d_zstencilcntl;
+	u32 se_cntl;
+} drm_radeon_depth_clear_t;
+
+typedef struct drm_radeon_private {
+	drm_radeon_ring_buffer_t ring;
+	drm_radeon_sarea_t *sarea_priv;
+
+	int agp_size;
+	u32 agp_vm_start;
+	u32 agp_buffers_offset;
+
+	int cp_mode;
+	int cp_running;
+
+   	drm_radeon_freelist_t *head;
+   	drm_radeon_freelist_t *tail;
+/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
+   code is used.  Note this hides a problem with the scratch register
+   (used to keep track of last buffer completed) being written to before
+   the last buffer has actually completed rendering. */
+#define ROTATE_BUFS 1
+#if ROTATE_BUFS
+	int last_buf;
+#endif
+	volatile u32 *scratch;
+
+	int usec_timeout;
+	int is_pci;
+
+	atomic_t idle_count;
+
+	int page_flipping;
+	int current_page;
+	u32 crtc_offset;
+	u32 crtc_offset_cntl;
+
+	unsigned int color_fmt;
+	unsigned int front_offset;
+	unsigned int front_pitch;
+	unsigned int back_offset;
+	unsigned int back_pitch;
+
+	unsigned int depth_fmt;
+	unsigned int depth_offset;
+	unsigned int depth_pitch;
+
+	u32 front_pitch_offset;
+	u32 back_pitch_offset;
+	u32 depth_pitch_offset;
+
+	drm_radeon_depth_clear_t depth_clear;
+
+	drm_map_t *sarea;
+	drm_map_t *fb;
+	drm_map_t *mmio;
+	drm_map_t *cp_ring;
+	drm_map_t *ring_rptr;
+	drm_map_t *buffers;
+	drm_map_t *agp_textures;
+} drm_radeon_private_t;
+
+typedef struct drm_radeon_buf_priv {
+	u32 age;
+	int prim;
+	int discard;
+	int dispatched;
+   	drm_radeon_freelist_t *list_entry;
+} drm_radeon_buf_priv_t;
+
+				/* radeon_drv.c */
+extern int  radeon_version( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int  radeon_open( struct inode *inode, struct file *filp );
+extern int  radeon_release( struct inode *inode, struct file *filp );
+extern int  radeon_ioctl( struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg );
+extern int  radeon_lock( struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg );
+extern int  radeon_unlock( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+
+				/* radeon_cp.c */
+extern int radeon_cp_init( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int radeon_cp_start( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int radeon_cp_stop( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int radeon_cp_reset( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int radeon_cp_idle( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int radeon_engine_reset( struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long arg );
+extern int radeon_fullscreen( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
+extern int radeon_cp_buffers( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
+
+extern void radeon_freelist_reset( drm_device_t *dev );
+extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
+
+extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
+extern void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv );
+
+extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
+extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
+
+				/* radeon_state.c */
+extern int radeon_cp_clear( struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg );
+extern int radeon_cp_swap( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int radeon_cp_vertex( struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg );
+extern int radeon_cp_indices( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
+extern int radeon_cp_blit( struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg );
+extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
+extern int radeon_cp_indirect( struct inode *inode, struct file *filp,
+			       unsigned int cmd, unsigned long arg );
+
+				/* radeon_bufs.c */
+extern int radeon_addbufs(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int radeon_mapbufs(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+
+				/* radeon_context.c */
+extern int  radeon_resctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  radeon_addctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  radeon_modctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  radeon_getctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  radeon_switchctx(struct inode *inode, struct file *filp,
+			     unsigned int cmd, unsigned long arg);
+extern int  radeon_newctx(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  radeon_rmctx(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+
+extern int  radeon_context_switch(drm_device_t *dev, int old, int new);
+extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
+
+
+/* Register definitions, register access macros and drmAddMap constants
+ * for Radeon kernel driver.
+ */
+
+#define RADEON_AUX_SCISSOR_CNTL		0x26f0
+#	define RADEON_EXCLUSIVE_SCISSOR_0	(1 << 24)
+#	define RADEON_EXCLUSIVE_SCISSOR_1	(1 << 25)
+#	define RADEON_EXCLUSIVE_SCISSOR_2	(1 << 26)
+#	define RADEON_SCISSOR_0_ENABLE		(1 << 28)
+#	define RADEON_SCISSOR_1_ENABLE		(1 << 29)
+#	define RADEON_SCISSOR_2_ENABLE		(1 << 30)
+
+#define RADEON_BUS_CNTL			0x0030
+#	define RADEON_BUS_MASTER_DIS		(1 << 6)
+
+#define RADEON_CLOCK_CNTL_DATA		0x000c
+#	define RADEON_PLL_WR_EN			(1 << 7)
+#define RADEON_CLOCK_CNTL_INDEX		0x0008
+#define RADEON_CONFIG_APER_SIZE		0x0108
+#define RADEON_CRTC_OFFSET		0x0224
+#define RADEON_CRTC_OFFSET_CNTL		0x0228
+#	define RADEON_CRTC_TILE_EN		(1 << 15)
+#	define RADEON_CRTC_OFFSET_FLIP_CNTL	(1 << 16)
+
+#define RADEON_RB3D_COLORPITCH		0x1c48
+#define RADEON_RB3D_DEPTHCLEARVALUE	0x1c30
+#define RADEON_RB3D_DEPTHXY_OFFSET	0x1c60
+
+#define RADEON_DP_GUI_MASTER_CNTL	0x146c
+#	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)
+#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
+#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)
+#	define RADEON_GMC_BRUSH_NONE		(15 << 4)
+#	define RADEON_GMC_DST_16BPP		(4 << 8)
+#	define RADEON_GMC_DST_24BPP		(5 << 8)
+#	define RADEON_GMC_DST_32BPP		(6 << 8)
+#	define RADEON_GMC_DST_DATATYPE_SHIFT	8
+#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3 << 12)
+#	define RADEON_DP_SRC_SOURCE_MEMORY	(2 << 24)
+#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3 << 24)
+#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1 << 28)
+#	define RADEON_GMC_WR_MSK_DIS		(1 << 30)
+#	define RADEON_ROP3_S			0x00cc0000
+#	define RADEON_ROP3_P			0x00f00000
+#define RADEON_DP_WRITE_MASK		0x16cc
+#define RADEON_DST_PITCH_OFFSET		0x142c
+#define RADEON_DST_PITCH_OFFSET_C	0x1c80
+#	define RADEON_DST_TILE_LINEAR		(0 << 30)
+#	define RADEON_DST_TILE_MACRO		(1 << 30)
+#	define RADEON_DST_TILE_MICRO		(2 << 30)
+#	define RADEON_DST_TILE_BOTH		(3 << 30)
+
+#define RADEON_SCRATCH_REG0		0x15e0
+#define RADEON_SCRATCH_REG1		0x15e4
+#define RADEON_SCRATCH_REG2		0x15e8
+#define RADEON_SCRATCH_REG3		0x15ec
+#define RADEON_SCRATCH_REG4		0x15f0
+#define RADEON_SCRATCH_REG5		0x15f4
+#define RADEON_SCRATCH_UMSK		0x0770
+#define RADEON_SCRATCH_ADDR		0x0774
+
+#define RADEON_HOST_PATH_CNTL		0x0130
+#	define RADEON_HDP_SOFT_RESET		(1 << 26)
+#	define RADEON_HDP_WC_TIMEOUT_MASK	(7 << 28)
+#	define RADEON_HDP_WC_TIMEOUT_28BCLK	(7 << 28)
+
+#define RADEON_ISYNC_CNTL		0x1724
+#	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)
+#	define RADEON_ISYNC_ANY3D_IDLE2D	(1 << 1)
+#	define RADEON_ISYNC_TRIG2D_IDLE3D	(1 << 2)
+#	define RADEON_ISYNC_TRIG3D_IDLE2D	(1 << 3)
+#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)
+#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
+
+#define RADEON_MC_AGP_LOCATION		0x014c
+#define RADEON_MC_FB_LOCATION		0x0148
+#define RADEON_MCLK_CNTL		0x0012
+
+#define RADEON_PP_BORDER_COLOR_0	0x1d40
+#define RADEON_PP_BORDER_COLOR_1	0x1d44
+#define RADEON_PP_BORDER_COLOR_2	0x1d48
+#define RADEON_PP_CNTL			0x1c38
+#	define RADEON_SCISSOR_ENABLE		(1 <<  1)
+#define RADEON_PP_LUM_MATRIX		0x1d00
+#define RADEON_PP_MISC			0x1c14
+#define RADEON_PP_ROT_MATRIX_0		0x1d58
+#define RADEON_PP_TXFILTER_0		0x1c54
+#define RADEON_PP_TXFILTER_1		0x1c6c
+#define RADEON_PP_TXFILTER_2		0x1c84
+
+#define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
+#	define RADEON_RB2D_DC_FLUSH		(3 << 0)
+#	define RADEON_RB2D_DC_FREE		(3 << 2)
+#	define RADEON_RB2D_DC_FLUSH_ALL		0xf
+#	define RADEON_RB2D_DC_BUSY		(1 << 31)
+#define RADEON_RB3D_CNTL		0x1c3c
+#	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
+#	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
+#	define RADEON_DITHER_ENABLE		(1 << 2)
+#	define RADEON_ROUND_ENABLE		(1 << 3)
+#	define RADEON_SCALE_DITHER_ENABLE	(1 << 4)
+#	define RADEON_DITHER_INIT		(1 << 5)
+#	define RADEON_ROP_ENABLE		(1 << 6)
+#	define RADEON_STENCIL_ENABLE		(1 << 7)
+#	define RADEON_Z_ENABLE			(1 << 8)
+#	define RADEON_DEPTH_XZ_OFFEST_ENABLE	(1 << 9)
+#	define RADEON_ZBLOCK8			(0 << 15)
+#	define RADEON_ZBLOCK16			(1 << 15)
+#define RADEON_RB3D_DEPTHOFFSET		0x1c24
+#define RADEON_RB3D_PLANEMASK		0x1d84
+#define RADEON_RB3D_STENCILREFMASK	0x1d7c
+#define RADEON_RB3D_ZCACHE_MODE		0x3250
+#define RADEON_RB3D_ZCACHE_CTLSTAT	0x3254
+#	define RADEON_RB3D_ZC_FLUSH		(1 << 0)
+#	define RADEON_RB3D_ZC_FREE		(1 << 2)
+#	define RADEON_RB3D_ZC_FLUSH_ALL		0x5
+#	define RADEON_RB3D_ZC_BUSY		(1 << 31)
+#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
+#	define RADEON_Z_TEST_MASK		(7 << 4)
+#	define RADEON_Z_TEST_ALWAYS		(7 << 4)
+#	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)
+#	define RADEON_STENCIL_S_FAIL_KEEP	(0 << 16)
+#	define RADEON_STENCIL_ZPASS_KEEP	(0 << 20)
+#	define RADEON_STENCIL_ZFAIL_KEEP	(0 << 20)
+#	define RADEON_Z_WRITE_ENABLE		(1 << 30)
+#define RADEON_RBBM_SOFT_RESET		0x00f0
+#	define RADEON_SOFT_RESET_CP		(1 <<  0)
+#	define RADEON_SOFT_RESET_HI		(1 <<  1)
+#	define RADEON_SOFT_RESET_SE		(1 <<  2)
+#	define RADEON_SOFT_RESET_RE		(1 <<  3)
+#	define RADEON_SOFT_RESET_PP		(1 <<  4)
+#	define RADEON_SOFT_RESET_E2		(1 <<  5)
+#	define RADEON_SOFT_RESET_RB		(1 <<  6)
+#	define RADEON_SOFT_RESET_HDP		(1 <<  7)
+#define RADEON_RBBM_STATUS		0x0e40
+#	define RADEON_RBBM_FIFOCNT_MASK		0x007f
+#	define RADEON_RBBM_ACTIVE		(1 << 31)
+#define RADEON_RE_LINE_PATTERN		0x1cd0
+#define RADEON_RE_MISC			0x26c4
+#define RADEON_RE_TOP_LEFT		0x26c0
+#define RADEON_RE_WIDTH_HEIGHT		0x1c44
+#define RADEON_RE_STIPPLE_ADDR		0x1cc8
+#define RADEON_RE_STIPPLE_DATA		0x1ccc
+
+#define RADEON_SCISSOR_TL_0		0x1cd8
+#define RADEON_SCISSOR_BR_0		0x1cdc
+#define RADEON_SCISSOR_TL_1		0x1ce0
+#define RADEON_SCISSOR_BR_1		0x1ce4
+#define RADEON_SCISSOR_TL_2		0x1ce8
+#define RADEON_SCISSOR_BR_2		0x1cec
+#define RADEON_SE_COORD_FMT		0x1c50
+#define RADEON_SE_CNTL			0x1c4c
+#	define RADEON_FFACE_CULL_CW		(0 << 0)
+#	define RADEON_BFACE_SOLID		(3 << 1)
+#	define RADEON_FFACE_SOLID		(3 << 3)
+#	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)
+#	define RADEON_DIFFUSE_SHADE_FLAT	(1 << 8)
+#	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)
+#	define RADEON_ALPHA_SHADE_FLAT		(1 << 10)
+#	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)
+#	define RADEON_SPECULAR_SHADE_FLAT	(1 << 12)
+#	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)
+#	define RADEON_FOG_SHADE_FLAT		(1 << 14)
+#	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)
+#	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)
+#	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)
+#	define RADEON_VTX_PIX_CENTER_OGL	(1 << 27)
+#	define RADEON_ROUND_MODE_TRUNC		(0 << 28)
+#	define RADEON_ROUND_PREC_8TH_PIX	(1 << 30)
+#define RADEON_SE_CNTL_STATUS		0x2140
+#define RADEON_SE_LINE_WIDTH		0x1db8
+#define RADEON_SE_VPORT_XSCALE		0x1d98
+#define RADEON_SURFACE_ACCESS_FLAGS	0x0bf8
+#define RADEON_SURFACE_ACCESS_CLR	0x0bfc
+#define RADEON_SURFACE_CNTL		0x0b00
+#	define RADEON_SURF_TRANSLATION_DIS	(1 << 8)
+#	define RADEON_NONSURF_AP0_SWP_MASK	(3 << 20)
+#	define RADEON_NONSURF_AP0_SWP_LITTLE	(0 << 20)
+#	define RADEON_NONSURF_AP0_SWP_BIG16	(1 << 20)
+#	define RADEON_NONSURF_AP0_SWP_BIG32	(2 << 20)
+#	define RADEON_NONSURF_AP1_SWP_MASK	(3 << 22)
+#	define RADEON_NONSURF_AP1_SWP_LITTLE	(0 << 22)
+#	define RADEON_NONSURF_AP1_SWP_BIG16	(1 << 22)
+#	define RADEON_NONSURF_AP1_SWP_BIG32	(2 << 22)
+#define RADEON_SURFACE0_INFO		0x0b0c
+#	define RADEON_SURF_PITCHSEL_MASK	(0x1ff << 0)
+#	define RADEON_SURF_TILE_MODE_MASK	(3 << 16)
+#	define RADEON_SURF_TILE_MODE_MACRO	(0 << 16)
+#	define RADEON_SURF_TILE_MODE_MICRO	(1 << 16)
+#	define RADEON_SURF_TILE_MODE_32BIT_Z	(2 << 16)
+#	define RADEON_SURF_TILE_MODE_16BIT_Z	(3 << 16)
+#define RADEON_SURFACE0_LOWER_BOUND	0x0b04
+#define RADEON_SURFACE0_UPPER_BOUND	0x0b08
+#define RADEON_SURFACE1_INFO		0x0b1c
+#define RADEON_SURFACE1_LOWER_BOUND	0x0b14
+#define RADEON_SURFACE1_UPPER_BOUND	0x0b18
+#define RADEON_SURFACE2_INFO		0x0b2c
+#define RADEON_SURFACE2_LOWER_BOUND	0x0b24
+#define RADEON_SURFACE2_UPPER_BOUND	0x0b28
+#define RADEON_SURFACE3_INFO		0x0b3c
+#define RADEON_SURFACE3_LOWER_BOUND	0x0b34
+#define RADEON_SURFACE3_UPPER_BOUND	0x0b38
+#define RADEON_SURFACE4_INFO		0x0b4c
+#define RADEON_SURFACE4_LOWER_BOUND	0x0b44
+#define RADEON_SURFACE4_UPPER_BOUND	0x0b48
+#define RADEON_SURFACE5_INFO		0x0b5c
+#define RADEON_SURFACE5_LOWER_BOUND	0x0b54
+#define RADEON_SURFACE5_UPPER_BOUND	0x0b58
+#define RADEON_SURFACE6_INFO		0x0b6c
+#define RADEON_SURFACE6_LOWER_BOUND	0x0b64
+#define RADEON_SURFACE6_UPPER_BOUND	0x0b68
+#define RADEON_SURFACE7_INFO		0x0b7c
+#define RADEON_SURFACE7_LOWER_BOUND	0x0b74
+#define RADEON_SURFACE7_UPPER_BOUND	0x0b78
+#define RADEON_SW_SEMAPHORE		0x013c
+
+#define RADEON_WAIT_UNTIL		0x1720
+#	define RADEON_WAIT_CRTC_PFLIP		(1 << 0)
+#	define RADEON_WAIT_2D_IDLECLEAN		(1 << 16)
+#	define RADEON_WAIT_3D_IDLECLEAN		(1 << 17)
+#	define RADEON_WAIT_HOST_IDLECLEAN	(1 << 18)
+
+#define RADEON_RB3D_ZMASKOFFSET		0x1c34
+#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
+#	define RADEON_DEPTH_FORMAT_16BIT_INT_Z	(0 << 0)
+#	define RADEON_DEPTH_FORMAT_24BIT_INT_Z	(2 << 0)
+
+
+/* CP registers */
+#define RADEON_CP_ME_RAM_ADDR		0x07d4
+#define RADEON_CP_ME_RAM_RADDR		0x07d8
+#define RADEON_CP_ME_RAM_DATAH		0x07dc
+#define RADEON_CP_ME_RAM_DATAL		0x07e0
+
+#define RADEON_CP_RB_BASE		0x0700
+#define RADEON_CP_RB_CNTL		0x0704
+#define RADEON_CP_RB_RPTR_ADDR		0x070c
+#define RADEON_CP_RB_RPTR		0x0710
+#define RADEON_CP_RB_WPTR		0x0714
+
+#define RADEON_CP_RB_WPTR_DELAY		0x0718
+#	define RADEON_PRE_WRITE_TIMER_SHIFT	0
+#	define RADEON_PRE_WRITE_LIMIT_SHIFT	23
+
+#define RADEON_CP_IB_BASE		0x0738
+
+#define RADEON_CP_CSQ_CNTL		0x0740
+#	define RADEON_CSQ_CNT_PRIMARY_MASK	(0xff << 0)
+#	define RADEON_CSQ_PRIDIS_INDDIS		(0 << 28)
+#	define RADEON_CSQ_PRIPIO_INDDIS		(1 << 28)
+#	define RADEON_CSQ_PRIBM_INDDIS		(2 << 28)
+#	define RADEON_CSQ_PRIPIO_INDBM		(3 << 28)
+#	define RADEON_CSQ_PRIBM_INDBM		(4 << 28)
+#	define RADEON_CSQ_PRIPIO_INDPIO		(15 << 28)
+
+#define RADEON_AIC_CNTL			0x01d0
+#	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
+
+/* CP command packets */
+#define RADEON_CP_PACKET0		0x00000000
+#	define RADEON_ONE_REG_WR		(1 << 15)
+#define RADEON_CP_PACKET1		0x40000000
+#define RADEON_CP_PACKET2		0x80000000
+#define RADEON_CP_PACKET3		0xC0000000
+#	define RADEON_3D_RNDR_GEN_INDX_PRIM	0x00002300
+#	define RADEON_WAIT_FOR_IDLE		0x00002600
+#	define RADEON_3D_DRAW_IMMD		0x00002900
+#	define RADEON_3D_CLEAR_ZMASK		0x00003200
+#	define RADEON_CNTL_HOSTDATA_BLT		0x00009400
+#	define RADEON_CNTL_PAINT_MULTI		0x00009A00
+#	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
+
+#define RADEON_CP_PACKET_MASK		0xC0000000
+#define RADEON_CP_PACKET_COUNT_MASK	0x3fff0000
+#define RADEON_CP_PACKET0_REG_MASK	0x000007ff
+#define RADEON_CP_PACKET1_REG0_MASK	0x000007ff
+#define RADEON_CP_PACKET1_REG1_MASK	0x003ff800
+
+#define RADEON_VTX_Z_PRESENT			(1 << 31)
+
+#define RADEON_PRIM_TYPE_NONE			(0 << 0)
+#define RADEON_PRIM_TYPE_POINT			(1 << 0)
+#define RADEON_PRIM_TYPE_LINE			(2 << 0)
+#define RADEON_PRIM_TYPE_LINE_STRIP		(3 << 0)
+#define RADEON_PRIM_TYPE_TRI_LIST		(4 << 0)
+#define RADEON_PRIM_TYPE_TRI_FAN		(5 << 0)
+#define RADEON_PRIM_TYPE_TRI_STRIP		(6 << 0)
+#define RADEON_PRIM_TYPE_TRI_TYPE2		(7 << 0)
+#define RADEON_PRIM_TYPE_RECT_LIST		(8 << 0)
+#define RADEON_PRIM_TYPE_3VRT_POINT_LIST	(9 << 0)
+#define RADEON_PRIM_TYPE_3VRT_LINE_LIST		(10 << 0)
+#define RADEON_PRIM_WALK_IND			(1 << 4)
+#define RADEON_PRIM_WALK_LIST			(2 << 4)
+#define RADEON_PRIM_WALK_RING			(3 << 4)
+#define RADEON_COLOR_ORDER_BGRA			(0 << 6)
+#define RADEON_COLOR_ORDER_RGBA			(1 << 6)
+#define RADEON_MAOS_ENABLE			(1 << 7)
+#define RADEON_VTX_FMT_R128_MODE		(0 << 8)
+#define RADEON_VTX_FMT_RADEON_MODE		(1 << 8)
+#define RADEON_NUM_VERTICES_SHIFT		16
+
+#define RADEON_COLOR_FORMAT_CI8		2
+#define RADEON_COLOR_FORMAT_ARGB1555	3
+#define RADEON_COLOR_FORMAT_RGB565	4
+#define RADEON_COLOR_FORMAT_ARGB8888	6
+#define RADEON_COLOR_FORMAT_RGB332	7
+#define RADEON_COLOR_FORMAT_RGB8	9
+#define RADEON_COLOR_FORMAT_ARGB4444	15
+
+#define RADEON_TXF_8BPP_I		0
+#define RADEON_TXF_16BPP_AI88		1
+#define RADEON_TXF_8BPP_RGB332		2
+#define RADEON_TXF_16BPP_ARGB1555	3
+#define RADEON_TXF_16BPP_RGB565		4
+#define RADEON_TXF_16BPP_ARGB4444	5
+#define RADEON_TXF_32BPP_ARGB8888	6
+#define RADEON_TXF_32BPP_RGBA8888	7
+
+/* Constants */
+#define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
+
+#define RADEON_LAST_FRAME_REG		RADEON_SCRATCH_REG0
+#define RADEON_LAST_DISPATCH_REG	RADEON_SCRATCH_REG1
+#define RADEON_LAST_CLEAR_REG		RADEON_SCRATCH_REG2
+#define RADEON_LAST_DISPATCH		1
+
+#define RADEON_MAX_VB_AGE		0x7fffffff
+#define RADEON_MAX_VB_VERTS		(0xffff)
+
+
+#define RADEON_BASE(reg)	((unsigned long)(dev_priv->mmio->handle))
+#define RADEON_ADDR(reg)	(RADEON_BASE(reg) + reg)
+
+#define RADEON_DEREF(reg)	*(__volatile__ u32 *)RADEON_ADDR(reg)
+#define RADEON_READ(reg)	RADEON_DEREF(reg)
+#define RADEON_WRITE(reg,val)	do { RADEON_DEREF(reg) = val; } while (0)
+
+#define RADEON_DEREF8(reg)	*(__volatile__ u8 *)RADEON_ADDR(reg)
+#define RADEON_READ8(reg)	RADEON_DEREF8(reg)
+#define RADEON_WRITE8(reg,val)	do { RADEON_DEREF8(reg) = val; } while (0)
+
+#define RADEON_WRITE_PLL(addr,val)                                            \
+do {                                                                          \
+	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,                                \
+		      ((addr) & 0x1f) | RADEON_PLL_WR_EN);                    \
+	RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));                          \
+} while (0)
+
+extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
+
+
+
+#define CP_PACKET0( reg, n )						\
+	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
+#define CP_PACKET0_TABLE( reg, n )					\
+	(RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
+#define CP_PACKET1( reg0, reg1 )					\
+	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
+#define CP_PACKET2()							\
+	(RADEON_CP_PACKET2)
+#define CP_PACKET3( pkt, n )						\
+	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
+
+
+/* ================================================================
+ * Engine control helper macros
+ */
+
+#define RADEON_WAIT_UNTIL_2D_IDLE()					\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
+	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
+		   RADEON_WAIT_HOST_IDLECLEAN) );			\
+} while (0)
+
+#define RADEON_WAIT_UNTIL_3D_IDLE()					\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
+	OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |				\
+		   RADEON_WAIT_HOST_IDLECLEAN) );			\
+} while (0)
+
+#define RADEON_WAIT_UNTIL_IDLE()					\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
+	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
+		   RADEON_WAIT_3D_IDLECLEAN |				\
+		   RADEON_WAIT_HOST_IDLECLEAN) );			\
+} while (0)
+
+#define RADEON_WAIT_UNTIL_PAGE_FLIPPED()				\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
+	OUT_RING( RADEON_WAIT_CRTC_PFLIP );				\
+} while (0)
+
+#define RADEON_FLUSH_CACHE()						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
+	OUT_RING( RADEON_RB2D_DC_FLUSH );				\
+} while (0)
+
+#define RADEON_PURGE_CACHE()						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
+	OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );				\
+} while (0)
+
+#define RADEON_FLUSH_ZCACHE()						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
+	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
+} while (0)
+
+#define RADEON_PURGE_ZCACHE()						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
+	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
+} while (0)
+
+
+/* ================================================================
+ * Misc helper macros
+ */
+
+#define VB_AGE_CHECK_WITH_RET( dev_priv )				\
+do {									\
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
+	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
+		int __ret = radeon_do_cp_idle( dev_priv );		\
+		if ( __ret < 0 ) return __ret;				\
+		sarea_priv->last_dispatch = 0;				\
+		radeon_freelist_reset( dev );				\
+	}								\
+} while (0)
+
+#define RADEON_DISPATCH_AGE( age )					\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );		\
+	OUT_RING( age );						\
+} while (0)
+
+#define RADEON_FRAME_AGE( age )						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );		\
+	OUT_RING( age );						\
+} while (0)
+
+#define RADEON_CLEAR_AGE( age )						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );		\
+	OUT_RING( age );						\
+} while (0)
+
+
+/* ================================================================
+ * Ring control
+ */
+
+#define radeon_flush_write_combine()	mb()
+
+
+#define RADEON_VERBOSE	0
+
+#define RING_LOCALS	int write; unsigned int mask; volatile u32 *ring;
+
+#define BEGIN_RING( n ) do {						\
+	if ( RADEON_VERBOSE ) {						\
+		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
+			   n, __FUNCTION__ );				\
+	}								\
+	if ( dev_priv->ring.space < (n) * sizeof(u32) ) {		\
+		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
+	}								\
+	dev_priv->ring.space -= (n) * sizeof(u32);			\
+	ring = dev_priv->ring.start;					\
+	write = dev_priv->ring.tail;					\
+	mask = dev_priv->ring.tail_mask;				\
+} while (0)
+
+#define ADVANCE_RING() do {						\
+	if ( RADEON_VERBOSE ) {						\
+		DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n",	\
+			  write, dev_priv->ring.tail );			\
+	}								\
+	radeon_flush_write_combine();					\
+	dev_priv->ring.tail = write;					\
+	RADEON_WRITE( RADEON_CP_RB_WPTR, write );			\
+} while (0)
+
+#define OUT_RING( x ) do {						\
+	if ( RADEON_VERBOSE ) {						\
+		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
+			   (unsigned int)(x), write );			\
+	}								\
+	ring[write++] = (x);						\
+	write &= mask;							\
+} while (0)
+
+#define RADEON_PERFORMANCE_BOXES	0
+
+#endif /* __RADEON_DRV_H__ */
diff -urN linux-2.4.16/drivers/char/drm-4.0/radeon_state.c lia64-2.4/drivers/char/drm-4.0/radeon_state.c
--- linux-2.4.16/drivers/char/drm-4.0/radeon_state.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/radeon_state.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,1447 @@
+/* radeon_state.c -- State support for Radeon -*- linux-c -*-
+ *
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "radeon_drv.h"
+#include "drm.h"
+#include <linux/delay.h>
+
+
+/* ================================================================
+ * CP hardware state programming functions
+ */
+
+static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
+					  drm_clip_rect_t *box )
+{
+	RING_LOCALS;
+
+	DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
+		   box->x1, box->y1, box->x2, box->y2 );
+
+	BEGIN_RING( 4 );
+
+	OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
+	OUT_RING( (box->y1 << 16) | box->x1 );
+
+	OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
+	OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_context( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 14 );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
+	OUT_RING( ctx->pp_misc );
+	OUT_RING( ctx->pp_fog_color );
+	OUT_RING( ctx->re_solid_color );
+	OUT_RING( ctx->rb3d_blendcntl );
+	OUT_RING( ctx->rb3d_depthoffset );
+	OUT_RING( ctx->rb3d_depthpitch );
+	OUT_RING( ctx->rb3d_zstencilcntl );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
+	OUT_RING( ctx->pp_cntl );
+	OUT_RING( ctx->rb3d_cntl );
+	OUT_RING( ctx->rb3d_coloroffset );
+
+	OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
+	OUT_RING( ctx->rb3d_colorpitch );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 2 );
+
+	OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
+	OUT_RING( ctx->se_coord_fmt );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_line( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 5 );
+
+	OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
+	OUT_RING( ctx->re_line_pattern );
+	OUT_RING( ctx->re_line_state );
+
+	OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
+	OUT_RING( ctx->se_line_width );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 5 );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
+	OUT_RING( ctx->pp_lum_matrix );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
+	OUT_RING( ctx->pp_rot_matrix_0 );
+	OUT_RING( ctx->pp_rot_matrix_1 );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_masks( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 4 );
+
+	OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
+	OUT_RING( ctx->rb3d_stencilrefmask );
+	OUT_RING( ctx->rb3d_ropcntl );
+	OUT_RING( ctx->rb3d_planemask );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_viewport( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 7 );
+
+	OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
+	OUT_RING( ctx->se_vport_xscale );
+	OUT_RING( ctx->se_vport_xoffset );
+	OUT_RING( ctx->se_vport_yscale );
+	OUT_RING( ctx->se_vport_yoffset );
+	OUT_RING( ctx->se_vport_zscale );
+	OUT_RING( ctx->se_vport_zoffset );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 4 );
+
+	OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
+	OUT_RING( ctx->se_cntl );
+	OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
+	OUT_RING( ctx->se_cntl_status );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_tcl( drm_radeon_private_t *dev_priv )
+{
+#ifdef TCL_ENABLE
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 29 );
+
+	OUT_RING( CP_PACKET0( RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 27 ) );
+	OUT_RING( ctx->se_tcl_material_emmissive.red );
+	OUT_RING( ctx->se_tcl_material_emmissive.green );
+	OUT_RING( ctx->se_tcl_material_emmissive.blue );
+	OUT_RING( ctx->se_tcl_material_emmissive.alpha );
+	OUT_RING( ctx->se_tcl_material_ambient.red );
+	OUT_RING( ctx->se_tcl_material_ambient.green );
+	OUT_RING( ctx->se_tcl_material_ambient.blue );
+	OUT_RING( ctx->se_tcl_material_ambient.alpha );
+	OUT_RING( ctx->se_tcl_material_diffuse.red );
+	OUT_RING( ctx->se_tcl_material_diffuse.green );
+	OUT_RING( ctx->se_tcl_material_diffuse.blue );
+	OUT_RING( ctx->se_tcl_material_diffuse.alpha );
+	OUT_RING( ctx->se_tcl_material_specular.red );
+	OUT_RING( ctx->se_tcl_material_specular.green );
+	OUT_RING( ctx->se_tcl_material_specular.blue );
+	OUT_RING( ctx->se_tcl_material_specular.alpha );
+	OUT_RING( ctx->se_tcl_shininess );
+	OUT_RING( ctx->se_tcl_output_vtx_fmt );
+	OUT_RING( ctx->se_tcl_output_vtx_sel );
+	OUT_RING( ctx->se_tcl_matrix_select_0 );
+	OUT_RING( ctx->se_tcl_matrix_select_1 );
+	OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl );
+	OUT_RING( ctx->se_tcl_texture_proc_ctl );
+	OUT_RING( ctx->se_tcl_light_model_ctl );
+	for ( i = 0 ; i < 4 ; i++ ) {
+		OUT_RING( ctx->se_tcl_per_light_ctl[i] );
+	}
+
+	ADVANCE_RING();
+#else
+	DRM_ERROR( "TCL not enabled!\n" );
+#endif
+}
+
+static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 2 );
+
+	OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
+	OUT_RING( ctx->re_misc );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
+	RING_LOCALS;
+	DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
+
+	BEGIN_RING( 9 );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
+	OUT_RING( tex->pp_border_color );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
+	RING_LOCALS;
+	DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
+
+	BEGIN_RING( 9 );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
+	OUT_RING( tex->pp_border_color );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
+	RING_LOCALS;
+	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+
+	BEGIN_RING( 9 );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
+
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
+	OUT_RING( tex->pp_border_color );
+
+	ADVANCE_RING();
+}
+
+static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
+{
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	unsigned int dirty = sarea_priv->dirty;
+
+	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
+
+	if ( dirty & RADEON_UPLOAD_CONTEXT ) {
+		radeon_emit_context( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_CONTEXT;
+	}
+
+	if ( dirty & RADEON_UPLOAD_VERTFMT ) {
+		radeon_emit_vertfmt( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_VERTFMT;
+	}
+
+	if ( dirty & RADEON_UPLOAD_LINE ) {
+		radeon_emit_line( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_LINE;
+	}
+
+	if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
+		radeon_emit_bumpmap( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_BUMPMAP;
+	}
+
+	if ( dirty & RADEON_UPLOAD_MASKS ) {
+		radeon_emit_masks( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_MASKS;
+	}
+
+	if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
+		radeon_emit_viewport( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_VIEWPORT;
+	}
+
+	if ( dirty & RADEON_UPLOAD_SETUP ) {
+		radeon_emit_setup( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP;
+	}
+
+	if ( dirty & RADEON_UPLOAD_TCL ) {
+#ifdef TCL_ENABLE
+		radeon_emit_tcl( dev_priv );
+#endif
+		sarea_priv->dirty &= ~RADEON_UPLOAD_TCL;
+	}
+
+	if ( dirty & RADEON_UPLOAD_MISC ) {
+		radeon_emit_misc( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_MISC;
+	}
+
+	if ( dirty & RADEON_UPLOAD_TEX0 ) {
+		radeon_emit_tex0( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_TEX0;
+	}
+
+	if ( dirty & RADEON_UPLOAD_TEX1 ) {
+		radeon_emit_tex1( dev_priv );
+		sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1;
+	}
+
+	if ( dirty & RADEON_UPLOAD_TEX2 ) {
+#if 0
+		radeon_emit_tex2( dev_priv );
+#endif
+		sarea_priv->dirty &= ~RADEON_UPLOAD_TEX2;
+	}
+
+	sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
+			       RADEON_UPLOAD_TEX1IMAGES |
+			       RADEON_UPLOAD_TEX2IMAGES |
+			       RADEON_REQUIRE_QUIESCENCE);
+}
+
+
+#if RADEON_PERFORMANCE_BOXES
+/* ================================================================
+ * Performance monitoring functions
+ */
+
+static void radeon_clear_box( drm_radeon_private_t *dev_priv,
+			      int x, int y, int w, int h,
+			      int r, int g, int b )
+{
+	u32 pitch, offset;
+	u32 color;
+	RING_LOCALS;
+
+	switch ( dev_priv->color_fmt ) {
+	case RADEON_COLOR_FORMAT_RGB565:
+		color = (((r & 0xf8) << 8) |
+			 ((g & 0xfc) << 3) |
+			 ((b & 0xf8) >> 3));
+		break;
+	case RADEON_COLOR_FORMAT_ARGB8888:
+	default:
+		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
+		break;
+	}
+
+	offset = dev_priv->back_offset;
+	pitch = dev_priv->back_pitch >> 3;
+
+	BEGIN_RING( 6 );
+
+	OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+	OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+		  RADEON_GMC_BRUSH_SOLID_COLOR |
+		  (dev_priv->color_fmt << 8) |
+		  RADEON_GMC_SRC_DATATYPE_COLOR |
+		  RADEON_ROP3_P |
+		  RADEON_GMC_CLR_CMP_CNTL_DIS );
+
+	OUT_RING( (pitch << 22) | (offset >> 5) );
+	OUT_RING( color );
+
+	OUT_RING( (x << 16) | y );
+	OUT_RING( (w << 16) | h );
+
+	ADVANCE_RING();
+}
+
+static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
+{
+	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
+		radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
+	} else {
+		atomic_set( &dev_priv->idle_count, 0 );
+	}
+}
+
+#endif
+
+
+/* ================================================================
+ * CP command dispatch functions
+ */
+
+static void radeon_print_dirty( const char *msg, unsigned int flags )
+{
+	DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+		   msg,
+		   flags,
+		   (flags & RADEON_UPLOAD_CONTEXT)     ? "context, " : "",
+		   (flags & RADEON_UPLOAD_VERTFMT)     ? "vertfmt, " : "",
+		   (flags & RADEON_UPLOAD_LINE)        ? "line, " : "",
+		   (flags & RADEON_UPLOAD_BUMPMAP)     ? "bumpmap, " : "",
+		   (flags & RADEON_UPLOAD_MASKS)       ? "masks, " : "",
+		   (flags & RADEON_UPLOAD_VIEWPORT)    ? "viewport, " : "",
+		   (flags & RADEON_UPLOAD_SETUP)       ? "setup, " : "",
+		   (flags & RADEON_UPLOAD_TCL)         ? "tcl, " : "",
+		   (flags & RADEON_UPLOAD_MISC)        ? "misc, " : "",
+		   (flags & RADEON_UPLOAD_TEX0)        ? "tex0, " : "",
+		   (flags & RADEON_UPLOAD_TEX1)        ? "tex1, " : "",
+		   (flags & RADEON_UPLOAD_TEX2)        ? "tex2, " : "",
+		   (flags & RADEON_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
+		   (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
+}
+
+static void radeon_cp_dispatch_clear( drm_device_t *dev,
+				      drm_radeon_clear_t *clear )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	unsigned int flags = clear->flags;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
+		unsigned int tmp = flags;
+
+		flags &= ~(RADEON_FRONT | RADEON_BACK);
+		if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
+		if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
+	}
+
+	for ( i = 0 ; i < nbox ; i++ ) {
+		int x = pbox[i].x1;
+		int y = pbox[i].y1;
+		int w = pbox[i].x2 - x;
+		int h = pbox[i].y2 - y;
+
+		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
+			   x, y, w, h, flags );
+
+		if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
+			BEGIN_RING( 4 );
+
+			/* Ensure the 3D stream is idle before doing a
+			 * 2D fill to clear the front or back buffer.
+			 */
+			RADEON_WAIT_UNTIL_3D_IDLE();
+
+			OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
+			OUT_RING( sarea_priv->context_state.rb3d_planemask );
+
+			ADVANCE_RING();
+
+			/* Make sure we restore the 3D state next time.
+			 */
+			dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
+							RADEON_UPLOAD_MASKS);
+		}
+
+		if ( flags & RADEON_FRONT ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+				  RADEON_GMC_BRUSH_SOLID_COLOR |
+				  (dev_priv->color_fmt << 8) |
+				  RADEON_GMC_SRC_DATATYPE_COLOR |
+				  RADEON_ROP3_P |
+				  RADEON_GMC_CLR_CMP_CNTL_DIS );
+
+			OUT_RING( dev_priv->front_pitch_offset );
+			OUT_RING( clear->clear_color );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (w << 16) | h );
+
+			ADVANCE_RING();
+		}
+
+		if ( flags & RADEON_BACK ) {
+			BEGIN_RING( 6 );
+
+			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+				  RADEON_GMC_BRUSH_SOLID_COLOR |
+				  (dev_priv->color_fmt << 8) |
+				  RADEON_GMC_SRC_DATATYPE_COLOR |
+				  RADEON_ROP3_P |
+				  RADEON_GMC_CLR_CMP_CNTL_DIS );
+
+			OUT_RING( dev_priv->back_pitch_offset );
+			OUT_RING( clear->clear_color );
+
+			OUT_RING( (x << 16) | y );
+			OUT_RING( (w << 16) | h );
+
+			ADVANCE_RING();
+
+		}
+
+		if ( flags & RADEON_DEPTH ) {
+			drm_radeon_depth_clear_t *depth_clear =
+			   &dev_priv->depth_clear;
+
+			if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
+				radeon_emit_state( dev_priv );
+			}
+
+			/* FIXME: Render a rectangle to clear the depth
+			 * buffer.  So much for those "fast Z clears"...
+			 */
+			BEGIN_RING( 23 );
+
+			RADEON_WAIT_UNTIL_2D_IDLE();
+
+			OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
+			OUT_RING( 0x00000000 );
+			OUT_RING( depth_clear->rb3d_cntl );
+			OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
+			OUT_RING( depth_clear->rb3d_zstencilcntl );
+			OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
+			OUT_RING( 0x00000000 );
+			OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
+			OUT_RING( depth_clear->se_cntl );
+
+			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
+			OUT_RING( RADEON_VTX_Z_PRESENT );
+			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
+				   RADEON_PRIM_WALK_RING |
+				   RADEON_MAOS_ENABLE |
+				   RADEON_VTX_FMT_RADEON_MODE |
+				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
+
+			OUT_RING( clear->rect.ui[CLEAR_X1] );
+			OUT_RING( clear->rect.ui[CLEAR_Y1] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
+
+			OUT_RING( clear->rect.ui[CLEAR_X1] );
+			OUT_RING( clear->rect.ui[CLEAR_Y2] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
+
+			OUT_RING( clear->rect.ui[CLEAR_X2] );
+			OUT_RING( clear->rect.ui[CLEAR_Y2] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
+
+			ADVANCE_RING();
+
+			/* Make sure we restore the 3D state next time.
+			 */
+			dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
+							RADEON_UPLOAD_SETUP |
+							RADEON_UPLOAD_MASKS);
+		}
+	}
+
+	/* Increment the clear counter.  The client-side 3D driver must
+	 * wait on this value before performing the clear ioctl.  We
+	 * need this because the card's so damned fast...
+	 */
+	dev_priv->sarea_priv->last_clear++;
+
+	BEGIN_RING( 4 );
+
+	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
+}
+
+static void radeon_cp_dispatch_swap( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+#if RADEON_PERFORMANCE_BOXES
+	/* Do some trivial performance monitoring...
+	 */
+	radeon_cp_performance_boxes( dev_priv );
+#endif
+
+	/* Wait for the 3D stream to idle before dispatching the bitblt.
+	 * This will prevent data corruption between the two streams.
+	 */
+	BEGIN_RING( 2 );
+
+	RADEON_WAIT_UNTIL_3D_IDLE();
+
+	ADVANCE_RING();
+
+	for ( i = 0 ; i < nbox ; i++ ) {
+		int x = pbox[i].x1;
+		int y = pbox[i].y1;
+		int w = pbox[i].x2 - x;
+		int h = pbox[i].y2 - y;
+
+		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
+			   x, y, w, h );
+
+		BEGIN_RING( 7 );
+
+		OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
+		OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+			  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+			  RADEON_GMC_BRUSH_NONE |
+			  (dev_priv->color_fmt << 8) |
+			  RADEON_GMC_SRC_DATATYPE_COLOR |
+			  RADEON_ROP3_S |
+			  RADEON_DP_SRC_SOURCE_MEMORY |
+			  RADEON_GMC_CLR_CMP_CNTL_DIS |
+			  RADEON_GMC_WR_MSK_DIS );
+
+		OUT_RING( dev_priv->back_pitch_offset );
+		OUT_RING( dev_priv->front_pitch_offset );
+
+		OUT_RING( (x << 16) | y );
+		OUT_RING( (x << 16) | y );
+		OUT_RING( (w << 16) | h );
+
+		ADVANCE_RING();
+	}
+
+	/* Increment the frame counter.  The client-side 3D driver must
+	 * throttle the framerate by waiting for this value before
+	 * performing the swapbuffer ioctl.
+	 */
+	dev_priv->sarea_priv->last_frame++;
+
+	BEGIN_RING( 4 );
+
+	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
+	RADEON_WAIT_UNTIL_2D_IDLE();
+
+	ADVANCE_RING();
+}
+
+static void radeon_cp_dispatch_flip( drm_device_t *dev )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	RING_LOCALS;
+	DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+#if RADEON_PERFORMANCE_BOXES
+	/* Do some trivial performance monitoring...
+	 */
+	radeon_cp_performance_boxes( dev_priv );
+#endif
+
+	BEGIN_RING( 6 );
+
+	RADEON_WAIT_UNTIL_3D_IDLE();
+	RADEON_WAIT_UNTIL_PAGE_FLIPPED();
+
+	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
+
+	if ( dev_priv->current_page == 0 ) {
+		OUT_RING( dev_priv->back_offset );
+		dev_priv->current_page = 1;
+	} else {
+		OUT_RING( dev_priv->front_offset );
+		dev_priv->current_page = 0;
+	}
+
+	ADVANCE_RING();
+
+	/* Increment the frame counter.  The client-side 3D driver must
+	 * throttle the framerate by waiting for this value before
+	 * performing the swapbuffer ioctl.
+	 */
+	dev_priv->sarea_priv->last_frame++;
+
+	BEGIN_RING( 2 );
+
+	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
+
+	ADVANCE_RING();
+}
+
+static void radeon_cp_dispatch_vertex( drm_device_t *dev,
+				       drm_buf_t *buf )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int format = sarea_priv->vc_format;
+	int offset = dev_priv->agp_buffers_offset + buf->offset;
+	int size = buf->used;
+	int prim = buf_priv->prim;
+	int i = 0;
+	RING_LOCALS;
+	DRM_DEBUG( "%s: nbox=%d\n", __FUNCTION__, sarea_priv->nbox );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	if ( 0 )
+		radeon_print_dirty( "dispatch_vertex", sarea_priv->dirty );
+
+	if ( buf->used ) {
+		buf_priv->dispatched = 1;
+
+		if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
+			radeon_emit_state( dev_priv );
+		}
+
+		do {
+			/* Emit the next set of up to three cliprects */
+			if ( i < sarea_priv->nbox ) {
+				radeon_emit_clip_rect( dev_priv,
+						       &sarea_priv->boxes[i] );
+			}
+
+			/* Emit the vertex buffer rendering commands */
+			BEGIN_RING( 5 );
+
+			OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
+			OUT_RING( offset );
+			OUT_RING( size );
+			OUT_RING( format );
+			OUT_RING( prim | RADEON_PRIM_WALK_LIST |
+				  RADEON_COLOR_ORDER_RGBA |
+				  RADEON_VTX_FMT_RADEON_MODE |
+				  (size << RADEON_NUM_VERTICES_SHIFT) );
+
+			ADVANCE_RING();
+
+			i++;
+		} while ( i < sarea_priv->nbox );
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
+		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		buf->used = 0;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+
+	sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
+	sarea_priv->nbox = 0;
+}
+
+
+static void radeon_cp_dispatch_indirect( drm_device_t *dev,
+					 drm_buf_t *buf,
+					 int start, int end )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
+	RING_LOCALS;
+	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
+		   buf->idx, start, end );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	if ( start != end ) {
+		int offset = (dev_priv->agp_buffers_offset
+			      + buf->offset + start);
+		int dwords = (end - start + 3) / sizeof(u32);
+
+		/* Indirect buffer data must be an even number of
+		 * dwords, so if we've been given an odd number we must
+		 * pad the data with a Type-2 CP packet.
+		 */
+		if ( dwords & 1 ) {
+			u32 *data = (u32 *)
+				((char *)dev_priv->buffers->handle
+				 + buf->offset + start);
+			data[dwords++] = RADEON_CP_PACKET2;
+		}
+
+		buf_priv->dispatched = 1;
+
+		/* Fire off the indirect buffer */
+		BEGIN_RING( 3 );
+
+		OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
+		OUT_RING( offset );
+		OUT_RING( dwords );
+
+		ADVANCE_RING();
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the indirect buffer age */
+		BEGIN_RING( 2 );
+		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		buf->used = 0;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+}
+
+static void radeon_cp_dispatch_indices( drm_device_t *dev,
+					drm_buf_t *buf,
+					int start, int end,
+					int count )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	int format = sarea_priv->vc_format;
+	int offset = dev_priv->agp_buffers_offset;
+	int prim = buf_priv->prim;
+	u32 *data;
+	int dwords;
+	int i = 0;
+	RING_LOCALS;
+	DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	if ( 0 )
+		radeon_print_dirty( "dispatch_indices", sarea_priv->dirty );
+
+	if ( start != end ) {
+		buf_priv->dispatched = 1;
+
+		if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
+			radeon_emit_state( dev_priv );
+		}
+
+		dwords = (end - start + 3) / sizeof(u32);
+
+		data = (u32 *)((char *)dev_priv->buffers->handle
+			       + buf->offset + start);
+
+		data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
+
+		data[1] = offset;
+		data[2] = RADEON_MAX_VB_VERTS;
+		data[3] = format;
+		data[4] = (prim | RADEON_PRIM_WALK_IND |
+			   RADEON_COLOR_ORDER_RGBA |
+			   RADEON_VTX_FMT_RADEON_MODE |
+			   (count << RADEON_NUM_VERTICES_SHIFT) );
+
+		if ( count & 0x1 ) {
+			data[dwords-1] &= 0x0000ffff;
+		}
+
+		do {
+			/* Emit the next set of up to three cliprects */
+			if ( i < sarea_priv->nbox ) {
+				radeon_emit_clip_rect( dev_priv,
+						       &sarea_priv->boxes[i] );
+			}
+
+			radeon_cp_dispatch_indirect( dev, buf, start, end );
+
+			i++;
+		} while ( i < sarea_priv->nbox );
+	}
+
+	if ( buf_priv->discard ) {
+		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
+
+		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
+		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
+
+		buf->pending = 1;
+		/* FIXME: Check dispatched field */
+		buf_priv->dispatched = 0;
+	}
+
+	dev_priv->sarea_priv->last_dispatch++;
+
+	sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
+	sarea_priv->nbox = 0;
+}
+
+static int radeon_cp_dispatch_blit( drm_device_t *dev,
+				    drm_radeon_blit_t *blit )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_radeon_buf_priv_t *buf_priv;
+	u32 format;
+	u32 *data;
+	int dword_shift, dwords;
+	RING_LOCALS;
+	DRM_DEBUG( "blit: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
+		   blit->offset >> 10, blit->pitch, blit->format,
+		   blit->x, blit->y, blit->width, blit->height );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	/* The compiler won't optimize away a division by a variable,
+	 * even if the only legal values are powers of two.  Thus, we'll
+	 * use a shift instead.
+	 */
+	switch ( blit->format ) {
+	case RADEON_TXF_32BPP_ARGB8888:
+	case RADEON_TXF_32BPP_RGBA8888:
+		format = RADEON_COLOR_FORMAT_ARGB8888;
+		dword_shift = 0;
+		break;
+	case RADEON_TXF_16BPP_AI88:
+	case RADEON_TXF_16BPP_ARGB1555:
+	case RADEON_TXF_16BPP_RGB565:
+	case RADEON_TXF_16BPP_ARGB4444:
+		format = RADEON_COLOR_FORMAT_RGB565;
+		dword_shift = 1;
+		break;
+	case RADEON_TXF_8BPP_I:
+	case RADEON_TXF_8BPP_RGB332:
+		format = RADEON_COLOR_FORMAT_CI8;
+		dword_shift = 2;
+		break;
+	default:
+		DRM_ERROR( "invalid blit format %d\n", blit->format );
+		return -EINVAL;
+	}
+
+	/* Flush the pixel cache.  This ensures no pixel data gets mixed
+	 * up with the texture data from the host data blit, otherwise
+	 * part of the texture image may be corrupted.
+	 */
+	BEGIN_RING( 4 );
+
+	RADEON_FLUSH_CACHE();
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
+
+	/* Dispatch the indirect buffer.
+	 */
+	buf = dma->buflist[blit->idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
+		return -EINVAL;
+	}
+
+	buf_priv->discard = 1;
+
+	dwords = (blit->width * blit->height) >> dword_shift;
+	if ( !dwords ) dwords = 1;
+
+	data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
+
+	data[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
+	data[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+		   RADEON_GMC_BRUSH_NONE |
+		   (format << 8) |
+		   RADEON_GMC_SRC_DATATYPE_COLOR |
+		   RADEON_ROP3_S |
+		   RADEON_DP_SRC_SOURCE_HOST_DATA |
+		   RADEON_GMC_CLR_CMP_CNTL_DIS |
+		   RADEON_GMC_WR_MSK_DIS);
+
+	data[2] = (blit->pitch << 22) | (blit->offset >> 10);
+	data[3] = 0xffffffff;
+	data[4] = 0xffffffff;
+	data[5] = (blit->y << 16) | blit->x;
+	data[6] = (blit->height << 16) | blit->width;
+	data[7] = dwords;
+
+	buf->used = (dwords + 8) * sizeof(u32);
+
+	radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
+
+	/* Flush the pixel cache after the blit completes.  This ensures
+	 * the texture data is written out to memory before rendering
+	 * continues.
+	 */
+	BEGIN_RING( 4 );
+
+	RADEON_FLUSH_CACHE();
+	RADEON_WAIT_UNTIL_2D_IDLE();
+
+	ADVANCE_RING();
+
+	return 0;
+}
+
+static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	int i;
+	RING_LOCALS;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	radeon_update_ring_snapshot( dev_priv );
+
+	BEGIN_RING( 35 );
+
+	OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
+	OUT_RING( 0x00000000 );
+
+	OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
+	for ( i = 0 ; i < 32 ; i++ ) {
+		OUT_RING( stipple[i] );
+	}
+
+	ADVANCE_RING();
+}
+
+
+/* ================================================================
+ * IOCTL functions
+ */
+
+int radeon_cp_clear( struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_radeon_clear_t clear;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &clear, (drm_radeon_clear_t *) arg,
+			     sizeof(clear) ) )
+		return -EFAULT;
+
+	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
+		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
+
+	radeon_cp_dispatch_clear( dev, &clear );
+
+	return 0;
+}
+
+int radeon_cp_swap( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
+		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
+
+	if ( !dev_priv->page_flipping ) {
+		radeon_cp_dispatch_swap( dev );
+		dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
+						RADEON_UPLOAD_MASKS);
+	} else {
+		radeon_cp_dispatch_flip( dev );
+	}
+
+	return 0;
+}
+
+int radeon_cp_vertex( struct inode *inode, struct file *filp,
+		      unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_radeon_buf_priv_t *buf_priv;
+	drm_radeon_vertex_t vertex;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv || dev_priv->is_pci ) {
+		DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
+			     sizeof(vertex) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
+		   __FUNCTION__, current->pid,
+		   vertex.idx, vertex.count, vertex.discard );
+
+	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   vertex.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+	if ( vertex.prim < 0 ||
+	     vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
+		DRM_ERROR( "buffer prim %d\n", vertex.prim );
+		return -EINVAL;
+	}
+
+	VB_AGE_CHECK_WITH_RET( dev_priv );
+
+	buf = dma->buflist[vertex.idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
+		return -EINVAL;
+	}
+
+	buf->used = vertex.count;
+	buf_priv->prim = vertex.prim;
+	buf_priv->discard = vertex.discard;
+
+	radeon_cp_dispatch_vertex( dev, buf );
+
+	return 0;
+}
+
+int radeon_cp_indices( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_radeon_buf_priv_t *buf_priv;
+	drm_radeon_indices_t elts;
+	int count;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv || dev_priv->is_pci ) {
+		DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg,
+			     sizeof(elts) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
+		   __FUNCTION__, current->pid,
+		   elts.idx, elts.start, elts.end, elts.discard );
+
+	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   elts.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+	if ( elts.prim < 0 ||
+	     elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
+		DRM_ERROR( "buffer prim %d\n", elts.prim );
+		return -EINVAL;
+	}
+
+	VB_AGE_CHECK_WITH_RET( dev_priv );
+
+	buf = dma->buflist[elts.idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
+		return -EINVAL;
+	}
+
+	count = (elts.end - elts.start) / sizeof(u16);
+	elts.start -= RADEON_INDEX_PRIM_OFFSET;
+
+	if ( elts.start & 0x7 ) {
+		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
+		return -EINVAL;
+	}
+	if ( elts.start < buf->used ) {
+		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
+		return -EINVAL;
+	}
+
+	buf->used = elts.end;
+	buf_priv->prim = elts.prim;
+	buf_priv->discard = elts.discard;
+
+	radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end, count );
+
+	return 0;
+}
+
+int radeon_cp_blit( struct inode *inode, struct file *filp,
+		    unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_radeon_blit_t blit;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &blit, (drm_radeon_blit_t *)arg,
+			     sizeof(blit) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "%s: pid=%d index=%d\n",
+		   __FUNCTION__, current->pid, blit.idx );
+
+	if ( blit.idx < 0 || blit.idx > dma->buf_count ) {
+		DRM_ERROR( "sending %d buffers (of %d max)\n",
+			   blit.idx, dma->buf_count );
+		return -EINVAL;
+	}
+
+	VB_AGE_CHECK_WITH_RET( dev_priv );
+
+	return radeon_cp_dispatch_blit( dev, &blit );
+}
+
+int radeon_cp_stipple( struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_stipple_t stipple;
+	u32 mask[32];
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg,
+			     sizeof(stipple) ) )
+		return -EFAULT;
+
+	if ( copy_from_user( &mask, stipple.mask,
+			     32 * sizeof(u32) ) )
+		return -EFAULT;
+
+	radeon_cp_dispatch_stipple( dev, mask );
+
+	return 0;
+}
+
+int radeon_cp_indirect( struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+	drm_buf_t *buf;
+	drm_radeon_buf_priv_t *buf_priv;
+	drm_radeon_indirect_t indirect;
+	RING_LOCALS;
+
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+	     dev->lock.pid != current->pid ) {
+		DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+	if ( !dev_priv || dev_priv->is_pci ) {
+		DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
+		return -EINVAL;
+	}
+
+	if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg,
+			     sizeof(indirect) ) )
+		return -EFAULT;
+
+	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
+		   indirect.idx, indirect.start,
+		   indirect.end, indirect.discard );
+
+	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
+		DRM_ERROR( "buffer index %d (of %d max)\n",
+			   indirect.idx, dma->buf_count - 1 );
+		return -EINVAL;
+	}
+
+	buf = dma->buflist[indirect.idx];
+	buf_priv = buf->dev_private;
+
+	if ( buf->pid != current->pid ) {
+		DRM_ERROR( "process %d using buffer owned by %d\n",
+			   current->pid, buf->pid );
+		return -EINVAL;
+	}
+	if ( buf->pending ) {
+		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
+		return -EINVAL;
+	}
+
+	if ( indirect.start < buf->used ) {
+		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
+			   indirect.start, buf->used );
+		return -EINVAL;
+	}
+
+	VB_AGE_CHECK_WITH_RET( dev_priv );
+
+	buf->used = indirect.end;
+	buf_priv->discard = indirect.discard;
+
+	/* Wait for the 3D stream to idle before the indirect buffer
+	 * containing 2D acceleration commands is processed.
+	 */
+	BEGIN_RING( 2 );
+
+	RADEON_WAIT_UNTIL_3D_IDLE();
+
+	ADVANCE_RING();
+
+	/* Dispatch the indirect buffer full of commands from the
+	 * X server.  This is insecure and is thus only available to
+	 * privileged clients.
+	 */
+	radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/tdfx_context.c lia64-2.4/drivers/char/drm-4.0/tdfx_context.c
--- linux-2.4.16/drivers/char/drm-4.0/tdfx_context.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/tdfx_context.c	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,219 @@
+/* tdfx_context.c -- IOCTLs for tdfx contexts -*- linux-c -*-
+ * Created: Thu Oct  7 10:50:22 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *    Daryll Strauss <daryll@valinux.com>
+ * 
+ */
+
+#define __NO_VERSION__
+#include "drmP.h"
+#include "tdfx_drv.h"
+
+extern drm_ctx_t tdfx_res_ctx;
+
+static int tdfx_alloc_queue(drm_device_t *dev)
+{
+	return drm_ctxbitmap_next(dev);
+}
+
+int tdfx_context_switch(drm_device_t *dev, int old, int new)
+{
+        char        buf[64];
+
+        atomic_inc(&dev->total_ctx);
+
+        if (test_and_set_bit(0, &dev->context_flag)) {
+                DRM_ERROR("Reentering -- FIXME\n");
+                return -EBUSY;
+        }
+
+#if DRM_DMA_HISTOGRAM
+        dev->ctx_start = get_cycles();
+#endif
+        
+        DRM_DEBUG("Context switch from %d to %d\n", old, new);
+
+        if (new == dev->last_context) {
+                clear_bit(0, &dev->context_flag);
+                return 0;
+        }
+        
+        if (drm_flags & DRM_FLAG_NOCTX) {
+                tdfx_context_switch_complete(dev, new);
+        } else {
+                sprintf(buf, "C %d %d\n", old, new);
+                drm_write_string(dev, buf);
+        }
+        
+        return 0;
+}
+
+int tdfx_context_switch_complete(drm_device_t *dev, int new)
+{
+        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+        dev->last_switch  = jiffies;
+        
+        if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+                DRM_ERROR("Lock isn't held after context switch\n");
+        }
+
+				/* If a context switch is ever initiated
+                                   when the kernel holds the lock, release
+                                   that lock here. */
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles()
+                                                      - dev->ctx_start)]);
+                   
+#endif
+        clear_bit(0, &dev->context_flag);
+        wake_up(&dev->context_wait);
+        
+        return 0;
+}
+
+
+int tdfx_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_ctx_res_t	res;
+	drm_ctx_t	ctx;
+	int		i;
+
+	DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
+	if (copy_from_user(&res, (drm_ctx_res_t *)arg, sizeof(res)))
+		return -EFAULT;
+	if (res.count >= DRM_RESERVED_CONTEXTS) {
+		memset(&ctx, 0, sizeof(ctx));
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
+			ctx.handle = i;
+			if (copy_to_user(&res.contexts[i],
+					 &i,
+					 sizeof(i)))
+				return -EFAULT;
+		}
+	}
+	res.count = DRM_RESERVED_CONTEXTS;
+	if (copy_to_user((drm_ctx_res_t *)arg, &res, sizeof(res)))
+		return -EFAULT;
+	return 0;
+}
+
+
+int tdfx_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	if ((ctx.handle = tdfx_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) {
+				/* Skip kernel's context and get a new one. */
+		ctx.handle = tdfx_alloc_queue(dev);
+	}
+	DRM_DEBUG("%d\n", ctx.handle);
+	if (ctx.handle == -1) {
+		DRM_DEBUG("Not enough free contexts.\n");
+				/* Should this return -EBUSY instead? */
+		return -ENOMEM;
+	}
+   
+	if (copy_to_user((drm_ctx_t *)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int tdfx_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	if (ctx.flags==_DRM_CONTEXT_PRESERVED)
+		tdfx_res_ctx.handle=ctx.handle;
+	return 0;
+}
+
+int tdfx_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	unsigned long arg)
+{
+	drm_ctx_t ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t*)arg, sizeof(ctx)))
+		return -EFAULT;
+	/* This is 0, because we don't handle any context flags */
+	ctx.flags = 0;
+	if (copy_to_user((drm_ctx_t*)arg, &ctx, sizeof(ctx)))
+		return -EFAULT;
+	return 0;
+}
+
+int tdfx_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		   unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	return tdfx_context_switch(dev, dev->last_context, ctx.handle);
+}
+
+int tdfx_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	tdfx_context_switch_complete(dev, ctx.handle);
+
+	return 0;
+}
+
+int tdfx_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
+	       unsigned long arg)
+{
+	drm_file_t      *priv   = filp->private_data;
+	drm_device_t    *dev    = priv->dev;
+	drm_ctx_t	ctx;
+
+	if (copy_from_user(&ctx, (drm_ctx_t *)arg, sizeof(ctx)))
+		return -EFAULT;
+	DRM_DEBUG("%d\n", ctx.handle);
+	drm_ctxbitmap_free(dev, ctx.handle);
+
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/tdfx_drv.c lia64-2.4/drivers/char/drm-4.0/tdfx_drv.c
--- linux-2.4.16/drivers/char/drm-4.0/tdfx_drv.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/tdfx_drv.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,696 @@
+/* tdfx_drv.c -- tdfx driver -*- linux-c -*-
+ * Created: Thu Oct  7 10:38:32 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *    Daryll Strauss <daryll@valinux.com>
+ *
+ */
+
+#include <linux/config.h>
+#include "drmP.h"
+#include "tdfx_drv.h"
+
+#define TDFX_NAME	 "tdfx"
+#define TDFX_DESC	 "3dfx Banshee/Voodoo3+"
+#define TDFX_DATE	 "20000928"
+#define TDFX_MAJOR	 1
+#define TDFX_MINOR	 0
+#define TDFX_PATCHLEVEL  0
+
+static drm_device_t	      tdfx_device;
+drm_ctx_t	              tdfx_res_ctx;
+
+static struct file_operations tdfx_fops = {
+#if LINUX_VERSION_CODE >= 0x020400
+				/* This started being used during 2.4.0-test */
+	owner:   THIS_MODULE,
+#endif
+	open:	 tdfx_open,
+	flush:	 drm_flush,
+	release: tdfx_release,
+	ioctl:	 tdfx_ioctl,
+	mmap:	 drm_mmap,
+	read:	 drm_read,
+	fasync:	 drm_fasync,
+	poll:	 drm_poll,
+};
+
+static struct miscdevice      tdfx_misc = {
+	minor: MISC_DYNAMIC_MINOR,
+	name:  TDFX_NAME,
+	fops:  &tdfx_fops,
+};
+
+static drm_ioctl_desc_t	      tdfx_ioctls[] = {
+	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)]    = { tdfx_version,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)]  = { drm_getmagic,	  0, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)]  = { drm_irq_busid,	  0, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)]	     = { drm_block,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)]    = { drm_unblock,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)]    = { drm_addmap,	  1, 1 },
+
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)]    = { tdfx_addctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)]     = { tdfx_rmctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)]    = { tdfx_modctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)]    = { tdfx_getctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { tdfx_switchctx,  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)]    = { tdfx_newctx,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)]    = { tdfx_resctx,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)]   = { drm_adddraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)]    = { drm_rmdraw,	  1, 1 },
+	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)]	     = { tdfx_lock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)]     = { tdfx_unlock,	  1, 0 },
+	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)]     = { drm_finish,	  1, 0 },
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)]   = {drm_agp_acquire, 1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)]   = {drm_agp_release, 1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)]    = {drm_agp_enable,  1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)]      = {drm_agp_info,    1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)]     = {drm_agp_alloc,   1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)]      = {drm_agp_free,    1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)]      = {drm_agp_unbind,  1, 1},
+	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)]    = {drm_agp_bind,    1, 1},
+#endif
+};
+#define TDFX_IOCTL_COUNT DRM_ARRAY_SIZE(tdfx_ioctls)
+
+#ifdef MODULE
+static char		      *tdfx = NULL;
+#endif
+
+MODULE_AUTHOR("VA Linux Systems, Inc.");
+MODULE_DESCRIPTION("tdfx");
+MODULE_PARM(tdfx, "s");
+
+#ifndef MODULE
+/* tdfx_options is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+
+static int __init tdfx_options(char *str)
+{
+	drm_parse_options(str);
+	return 1;
+}
+
+__setup("tdfx=", tdfx_options);
+#endif
+
+static int tdfx_setup(drm_device_t *dev)
+{
+	int i;
+
+	atomic_set(&dev->ioctl_count, 0);
+	atomic_set(&dev->vma_count, 0);
+	dev->buf_use	  = 0;
+	atomic_set(&dev->buf_alloc, 0);
+
+	atomic_set(&dev->total_open, 0);
+	atomic_set(&dev->total_close, 0);
+	atomic_set(&dev->total_ioctl, 0);
+	atomic_set(&dev->total_irq, 0);
+	atomic_set(&dev->total_ctx, 0);
+	atomic_set(&dev->total_locks, 0);
+	atomic_set(&dev->total_unlocks, 0);
+	atomic_set(&dev->total_contends, 0);
+	atomic_set(&dev->total_sleeps, 0);
+
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		dev->magiclist[i].head = NULL;
+		dev->magiclist[i].tail = NULL;
+	}
+	dev->maplist	    = NULL;
+	dev->map_count	    = 0;
+	dev->vmalist	    = NULL;
+	dev->lock.hw_lock   = NULL;
+	init_waitqueue_head(&dev->lock.lock_queue);
+	dev->queue_count    = 0;
+	dev->queue_reserved = 0;
+	dev->queue_slots    = 0;
+	dev->queuelist	    = NULL;
+	dev->irq	    = 0;
+	dev->context_flag   = 0;
+	dev->interrupt_flag = 0;
+	dev->dma            = 0;
+	dev->dma_flag	    = 0;
+	dev->last_context   = 0;
+	dev->last_switch    = 0;
+	dev->last_checked   = 0;
+	init_timer(&dev->timer);
+	init_waitqueue_head(&dev->context_wait);
+
+	dev->ctx_start	    = 0;
+	dev->lck_start	    = 0;
+
+	dev->buf_rp	  = dev->buf;
+	dev->buf_wp	  = dev->buf;
+	dev->buf_end	  = dev->buf + DRM_BSZ;
+	dev->buf_async	  = NULL;
+	init_waitqueue_head(&dev->buf_readers);
+	init_waitqueue_head(&dev->buf_writers);
+
+	tdfx_res_ctx.handle=-1;
+
+	DRM_DEBUG("\n");
+
+	/* The kernel's context could be created here, but is now created
+	   in drm_dma_enqueue.	This is more resource-efficient for
+	   hardware that does not do DMA, but may mean that
+	   drm_select_queue fails between the time the interrupt is
+	   initialized and the time the queues are initialized. */
+
+	return 0;
+}
+
+
+static int tdfx_takedown(drm_device_t *dev)
+{
+	int		  i;
+	drm_magic_entry_t *pt, *next;
+	drm_map_t	  *map;
+	drm_vma_entry_t	  *vma, *vma_next;
+
+	DRM_DEBUG("\n");
+
+	down(&dev->struct_sem);
+	del_timer(&dev->timer);
+
+	if (dev->devname) {
+		drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER);
+		dev->devname = NULL;
+	}
+
+	if (dev->unique) {
+		drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER);
+		dev->unique = NULL;
+		dev->unique_len = 0;
+	}
+				/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
+			next = pt->next;
+			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
+		}
+		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
+	}
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+				/* Clear AGP information */
+	if (dev->agp) {
+		drm_agp_mem_t *temp;
+		drm_agp_mem_t *temp_next;
+
+		temp = dev->agp->memory;
+		while(temp != NULL) {
+			temp_next = temp->next;
+			drm_free_agp(temp->memory, temp->pages);
+			drm_free(temp, sizeof(*temp), DRM_MEM_AGPLISTS);
+			temp = temp_next;
+		}
+		if (dev->agp->acquired) _drm_agp_release();
+	}
+#endif
+				/* Clear vma list (only built for debugging) */
+	if (dev->vmalist) {
+		for (vma = dev->vmalist; vma; vma = vma_next) {
+			vma_next = vma->next;
+			drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
+		}
+		dev->vmalist = NULL;
+	}
+
+				/* Clear map area and mtrr information */
+	if (dev->maplist) {
+		for (i = 0; i < dev->map_count; i++) {
+			map = dev->maplist[i];
+			switch (map->type) {
+			case _DRM_REGISTERS:
+			case _DRM_FRAME_BUFFER:
+#ifdef CONFIG_MTRR
+				if (map->mtrr >= 0) {
+					int retcode;
+					retcode = mtrr_del(map->mtrr,
+							   map->offset,
+							   map->size);
+					DRM_DEBUG("mtrr_del = %d\n", retcode);
+				}
+#endif
+				drm_ioremapfree(map->handle, map->size, dev);
+				break;
+			case _DRM_SHM:
+				drm_free_pages((unsigned long)map->handle,
+					       drm_order(map->size)
+					       - PAGE_SHIFT,
+					       DRM_MEM_SAREA);
+				break;
+			case _DRM_AGP:
+				/* Do nothing here, because this is all
+                                   handled in the AGP/GART driver. */
+				break;
+			}
+			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+		}
+		drm_free(dev->maplist,
+			 dev->map_count * sizeof(*dev->maplist),
+			 DRM_MEM_MAPS);
+		dev->maplist   = NULL;
+		dev->map_count = 0;
+	}
+
+	if (dev->lock.hw_lock) {
+		dev->lock.hw_lock    = NULL; /* SHM removed */
+		dev->lock.pid	     = 0;
+		wake_up_interruptible(&dev->lock.lock_queue);
+	}
+	up(&dev->struct_sem);
+
+	return 0;
+}
+
+/* tdfx_init is called via init_module at module load time, or via
+ * linux/init/main.c (this is not currently supported). */
+
+static int __init tdfx_init(void)
+{
+	int		      retcode;
+	drm_device_t	      *dev = &tdfx_device;
+
+	DRM_DEBUG("\n");
+
+	memset((void *)dev, 0, sizeof(*dev));
+	dev->count_lock	  = SPIN_LOCK_UNLOCKED;
+	sema_init(&dev->struct_sem, 1);
+
+#ifdef MODULE
+	drm_parse_options(tdfx);
+#endif
+
+	if ((retcode = misc_register(&tdfx_misc))) {
+		DRM_ERROR("Cannot register \"%s\"\n", TDFX_NAME);
+		return retcode;
+	}
+	dev->device = MKDEV(MISC_MAJOR, tdfx_misc.minor);
+	dev->name   = TDFX_NAME;
+
+	drm_mem_init();
+	drm_proc_init(dev);
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	dev->agp    = drm_agp_init();
+#endif
+	if((retcode = drm_ctxbitmap_init(dev))) {
+		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+		drm_proc_cleanup();
+		misc_deregister(&tdfx_misc);
+		tdfx_takedown(dev);
+		return retcode;
+	}
+
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+		 TDFX_NAME,
+		 TDFX_MAJOR,
+		 TDFX_MINOR,
+		 TDFX_PATCHLEVEL,
+		 TDFX_DATE,
+		 tdfx_misc.minor);
+
+	return 0;
+}
+
+/* tdfx_cleanup is called via cleanup_module at module unload time. */
+
+static void __exit tdfx_cleanup(void)
+{
+	drm_device_t	      *dev = &tdfx_device;
+
+	DRM_DEBUG("\n");
+
+	drm_proc_cleanup();
+	if (misc_deregister(&tdfx_misc)) {
+		DRM_ERROR("Cannot unload module\n");
+	} else {
+		DRM_INFO("Module unloaded\n");
+	}
+	drm_ctxbitmap_cleanup(dev);
+	tdfx_takedown(dev);
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+	if (dev->agp) {
+		drm_agp_uninit();
+		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
+		dev->agp = NULL;
+	}
+#endif
+}
+
+module_init(tdfx_init);
+module_exit(tdfx_cleanup);
+
+
+int tdfx_version(struct inode *inode, struct file *filp, unsigned int cmd,
+		  unsigned long arg)
+{
+	drm_version_t version;
+	int	      len;
+
+	if (copy_from_user(&version,
+			   (drm_version_t *)arg,
+			   sizeof(version)))
+		return -EFAULT;
+
+#define DRM_COPY(name,value)				     \
+	len = strlen(value);				     \
+	if (len > name##_len) len = name##_len;		     \
+	name##_len = strlen(value);			     \
+	if (len && name) {				     \
+		if (copy_to_user(name, value, len))	     \
+			return -EFAULT;			     \
+	}
+
+	version.version_major	   = TDFX_MAJOR;
+	version.version_minor	   = TDFX_MINOR;
+	version.version_patchlevel = TDFX_PATCHLEVEL;
+
+	DRM_COPY(version.name, TDFX_NAME);
+	DRM_COPY(version.date, TDFX_DATE);
+	DRM_COPY(version.desc, TDFX_DESC);
+
+	if (copy_to_user((drm_version_t *)arg,
+			 &version,
+			 sizeof(version)))
+		return -EFAULT;
+	return 0;
+}
+
+int tdfx_open(struct inode *inode, struct file *filp)
+{
+	drm_device_t  *dev    = &tdfx_device;
+	int	      retcode = 0;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_open_helper(inode, filp, dev))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_open);
+		spin_lock(&dev->count_lock);
+		if (!dev->open_count++) {
+			spin_unlock(&dev->count_lock);
+			return tdfx_setup(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+	return retcode;
+}
+
+int tdfx_release(struct inode *inode, struct file *filp)
+{
+	drm_file_t    *priv   = filp->private_data;
+	drm_device_t  *dev;
+	int	      retcode = 0;
+
+	lock_kernel();
+	dev = priv->dev;
+
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
+	if (!(retcode = drm_release(inode, filp))) {
+#if LINUX_VERSION_CODE < 0x020333
+		MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+		atomic_inc(&dev->total_close);
+		spin_lock(&dev->count_lock);
+		if (!--dev->open_count) {
+			if (atomic_read(&dev->ioctl_count) || dev->blocked) {
+				DRM_ERROR("Device busy: %d %d\n",
+					  atomic_read(&dev->ioctl_count),
+					  dev->blocked);
+				spin_unlock(&dev->count_lock);
+				unlock_kernel();
+				return -EBUSY;
+			}
+			spin_unlock(&dev->count_lock);
+			unlock_kernel();
+			return tdfx_takedown(dev);
+		}
+		spin_unlock(&dev->count_lock);
+	}
+
+	unlock_kernel();
+	return retcode;
+}
+
+/* tdfx_ioctl is called whenever a process performs an ioctl on /dev/drm. */
+
+int tdfx_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+		unsigned long arg)
+{
+	int		 nr	 = DRM_IOCTL_NR(cmd);
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	int		 retcode = 0;
+	drm_ioctl_desc_t *ioctl;
+	drm_ioctl_t	 *func;
+
+	atomic_inc(&dev->ioctl_count);
+	atomic_inc(&dev->total_ioctl);
+	++priv->ioctl_count;
+
+	DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n",
+		  current->pid, cmd, nr, dev->device, priv->authenticated);
+
+	if (nr >= TDFX_IOCTL_COUNT) {
+		retcode = -EINVAL;
+	} else {
+		ioctl	  = &tdfx_ioctls[nr];
+		func	  = ioctl->func;
+
+		if (!func) {
+			DRM_DEBUG("no function\n");
+			retcode = -EINVAL;
+		} else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN))
+			    || (ioctl->auth_needed && !priv->authenticated)) {
+			retcode = -EACCES;
+		} else {
+			retcode = (func)(inode, filp, cmd, arg);
+		}
+	}
+
+	atomic_dec(&dev->ioctl_count);
+	return retcode;
+}
+
+int tdfx_lock(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+        drm_file_t        *priv   = filp->private_data;
+        drm_device_t      *dev    = priv->dev;
+        DECLARE_WAITQUEUE(entry, current);
+        int               ret   = 0;
+        drm_lock_t        lock;
+#if DRM_DMA_HISTOGRAM
+        cycles_t          start;
+
+        dev->lck_start = start = get_cycles();
+#endif
+
+        if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+        if (lock.context == DRM_KERNEL_CONTEXT) {
+                DRM_ERROR("Process %d using kernel context %d\n",
+                          current->pid, lock.context);
+                return -EINVAL;
+        }
+
+        DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+                  lock.context, current->pid, dev->lock.hw_lock->lock,
+                  lock.flags);
+
+#if 0
+				/* dev->queue_count == 0 right now for
+                                   tdfx.  FIXME? */
+        if (lock.context < 0 || lock.context >= dev->queue_count)
+                return -EINVAL;
+#endif
+
+        if (!ret) {
+#if 0
+                if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)
+                    != lock.context) {
+                        long j = jiffies - dev->lock.lock_time;
+
+                        if (lock.context == tdfx_res_ctx.handle &&
+				j >= 0 && j < DRM_LOCK_SLICE) {
+                                /* Can't take lock if we just had it and
+                                   there is contention. */
+                                DRM_DEBUG("%d (pid %d) delayed j=%d dev=%d jiffies=%d\n",
+					lock.context, current->pid, j,
+					dev->lock.lock_time, jiffies);
+                                current->state = TASK_INTERRUPTIBLE;
+				current->policy |= SCHED_YIELD;
+                                schedule_timeout(DRM_LOCK_SLICE-j);
+				DRM_DEBUG("jiffies=%d\n", jiffies);
+                        }
+                }
+#endif
+                add_wait_queue(&dev->lock.lock_queue, &entry);
+                for (;;) {
+                        current->state = TASK_INTERRUPTIBLE;
+                        if (!dev->lock.hw_lock) {
+                                /* Device has been unregistered */
+                                ret = -EINTR;
+                                break;
+                        }
+                        if (drm_lock_take(&dev->lock.hw_lock->lock,
+                                          lock.context)) {
+                                dev->lock.pid       = current->pid;
+                                dev->lock.lock_time = jiffies;
+                                atomic_inc(&dev->total_locks);
+                                break;  /* Got lock */
+                        }
+
+                                /* Contention */
+                        atomic_inc(&dev->total_sleeps);
+#if 1
+			current->policy |= SCHED_YIELD;
+#endif
+                        schedule();
+                        if (signal_pending(current)) {
+                                ret = -ERESTARTSYS;
+                                break;
+                        }
+                }
+                current->state = TASK_RUNNING;
+                remove_wait_queue(&dev->lock.lock_queue, &entry);
+        }
+
+#if 0
+	if (!ret && dev->last_context != lock.context &&
+		lock.context != tdfx_res_ctx.handle &&
+		dev->last_context != tdfx_res_ctx.handle) {
+		add_wait_queue(&dev->context_wait, &entry);
+	        current->state = TASK_INTERRUPTIBLE;
+                /* PRE: dev->last_context != lock.context */
+	        tdfx_context_switch(dev, dev->last_context, lock.context);
+		/* POST: we will wait for the context
+                   switch and will dispatch on a later call
+                   when dev->last_context == lock.context
+                   NOTE WE HOLD THE LOCK THROUGHOUT THIS
+                   TIME! */
+		current->policy |= SCHED_YIELD;
+	        schedule();
+	        current->state = TASK_RUNNING;
+	        remove_wait_queue(&dev->context_wait, &entry);
+	        if (signal_pending(current)) {
+	                ret = -EINTR;
+	        } else if (dev->last_context != lock.context) {
+			DRM_ERROR("Context mismatch: %d %d\n",
+                        	dev->last_context, lock.context);
+	        }
+	}
+#endif
+
+        if (!ret) {
+		sigemptyset(&dev->sigmask);
+		sigaddset(&dev->sigmask, SIGSTOP);
+		sigaddset(&dev->sigmask, SIGTSTP);
+		sigaddset(&dev->sigmask, SIGTTIN);
+		sigaddset(&dev->sigmask, SIGTTOU);
+		dev->sigdata.context = lock.context;
+		dev->sigdata.lock    = dev->lock.hw_lock;
+		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
+
+                if (lock.flags & _DRM_LOCK_READY) {
+				/* Wait for space in DMA/FIFO */
+		}
+                if (lock.flags & _DRM_LOCK_QUIESCENT) {
+				/* Make hardware quiescent */
+#if 0
+                        tdfx_quiescent(dev);
+#endif
+		}
+        }
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != tdfx_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY/4;
+	}
+#endif
+        DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
+
+#if DRM_DMA_HISTOGRAM
+        atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]);
+#endif
+
+        return ret;
+}
+
+
+int tdfx_unlock(struct inode *inode, struct file *filp, unsigned int cmd,
+		 unsigned long arg)
+{
+	drm_file_t	  *priv	  = filp->private_data;
+	drm_device_t	  *dev	  = priv->dev;
+	drm_lock_t	  lock;
+
+	if (copy_from_user(&lock, (drm_lock_t *)arg, sizeof(lock)))
+		return -EFAULT;
+
+	if (lock.context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
+			  current->pid, lock.context);
+		return -EINVAL;
+	}
+
+	DRM_DEBUG("%d frees lock (%d holds)\n",
+		  lock.context,
+		  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
+	atomic_inc(&dev->total_unlocks);
+	if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock))
+		atomic_inc(&dev->total_contends);
+	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+				/* FIXME: Try to send data to card here */
+	if (!dev->context_flag) {
+		if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
+				  DRM_KERNEL_CONTEXT)) {
+			DRM_ERROR("\n");
+		}
+	}
+
+#if LINUX_VERSION_CODE < 0x020400
+	if (lock.context != tdfx_res_ctx.handle) {
+		current->counter = 5;
+		current->priority = DEF_PRIORITY;
+	}
+#endif
+
+	unblock_all_signals();
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/drm-4.0/tdfx_drv.h lia64-2.4/drivers/char/drm-4.0/tdfx_drv.h
--- linux-2.4.16/drivers/char/drm-4.0/tdfx_drv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/tdfx_drv.h	Wed Aug 15 20:52:12 2001
@@ -0,0 +1,67 @@
+/* tdfx_drv.h -- Private header for tdfx driver -*- linux-c -*-
+ * Created: Thu Oct  7 10:40:04 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *    Daryll Strauss <daryll@valinux.com>
+ * 
+ */
+
+#ifndef _TDFX_DRV_H_
+#define _TDFX_DRV_H_
+
+				/* tdfx_drv.c */
+extern int  tdfx_version(struct inode *inode, struct file *filp,
+			  unsigned int cmd, unsigned long arg);
+extern int  tdfx_open(struct inode *inode, struct file *filp);
+extern int  tdfx_release(struct inode *inode, struct file *filp);
+extern int  tdfx_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  tdfx_lock(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+extern int  tdfx_unlock(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg);
+
+				/* tdfx_context.c */
+
+extern int  tdfx_resctx(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  tdfx_addctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  tdfx_modctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  tdfx_getctx(struct inode *inode, struct file *filp,
+		        unsigned int cmd, unsigned long arg);
+extern int  tdfx_switchctx(struct inode *inode, struct file *filp,
+			   unsigned int cmd, unsigned long arg);
+extern int  tdfx_newctx(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg);
+extern int  tdfx_rmctx(struct inode *inode, struct file *filp,
+		       unsigned int cmd, unsigned long arg);
+
+extern int  tdfx_context_switch(drm_device_t *dev, int old, int new);
+extern int  tdfx_context_switch_complete(drm_device_t *dev, int new);
+#endif
diff -urN linux-2.4.16/drivers/char/drm-4.0/vm.c lia64-2.4/drivers/char/drm-4.0/vm.c
--- linux-2.4.16/drivers/char/drm-4.0/vm.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/drm-4.0/vm.c	Mon Aug 20 18:09:34 2001
@@ -0,0 +1,451 @@
+/* vm.c -- Memory mapping for DRM -*- linux-c -*-
+ * Created: Mon Jan  4 08:58:31 1999 by faith@precisioninsight.com
+ *
+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * Authors:
+ *    Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+#define __NO_VERSION__
+#include <linux/config.h>
+#include "drmP.h"
+
+struct vm_operations_struct   drm_vm_ops = {
+	nopage:	 drm_vm_nopage,
+	open:	 drm_vm_open,
+	close:	 drm_vm_close,
+};
+
+struct vm_operations_struct   drm_vm_shm_ops = {
+	nopage:	 drm_vm_shm_nopage,
+	open:	 drm_vm_open,
+	close:	 drm_vm_close,
+};
+
+struct vm_operations_struct   drm_vm_shm_lock_ops = {
+	nopage:	 drm_vm_shm_nopage_lock,
+	open:	 drm_vm_open,
+	close:	 drm_vm_close,
+};
+
+struct vm_operations_struct   drm_vm_dma_ops = {
+	nopage:	 drm_vm_dma_nopage,
+	open:	 drm_vm_open,
+	close:	 drm_vm_close,
+};
+
+#if LINUX_VERSION_CODE < 0x020317
+unsigned long drm_vm_nopage(struct vm_area_struct *vma,
+			    unsigned long address,
+			    int write_access)
+#else
+				/* Return type changed in 2.3.23 */
+struct page *drm_vm_nopage(struct vm_area_struct *vma,
+			   unsigned long address,
+			   int write_access)
+#endif
+{
+#if defined(__ia64__)
+        drm_file_t *priv  = vma->vm_file->private_data;
+        drm_device_t *dev = priv->dev;
+        drm_map_t *map    = NULL;
+	int i;
+
+        /*
+         * Find the right map
+         */
+
+	if(!dev->agp->cant_use_aperture) goto vm_nopage_error;
+
+	for (i = 0; i < dev->map_count; i++) {
+                map = dev->maplist[i];
+                if (!map) continue;
+                if (map->offset == VM_OFFSET(vma)) break;
+        }
+
+        if (map && map->type == _DRM_AGP) {
+                unsigned long offset = address - vma->vm_start;
+                unsigned long baddr = VM_OFFSET(vma) + offset, paddr;
+                struct drm_agp_mem *agpmem;
+                struct page *page;
+
+                /*
+                 * It's AGP memory - find the real physical page to map
+                 */
+                for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) {
+                        if (agpmem->bound <= baddr &&
+                            agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) 
+                                break;
+                }
+
+                if (!agpmem) goto vm_nopage_error;
+
+                /*
+                 * Get the page, inc the use count, and return it
+                 */
+                offset = (baddr - agpmem->bound) >> PAGE_SHIFT;
+
+		/*
+		 * This is bad.  What we really want to do here is unmask
+		 * the GART table entry held in the agp_memory structure.
+		 * There isn't a convenient way to call agp_bridge.unmask_
+		 * memory from here, so hard code it for now.
+		 */
+		paddr = (agpmem->memory->memory[offset] & 0xffffff) << 12;
+
+                page = virt_to_page(__va(paddr));
+                get_page(page);
+
+#if LINUX_VERSION_CODE < 0x020317
+		return page_address(page);
+#else
+		return page;
+#endif
+        }
+vm_nopage_error:
+#endif
+	return NOPAGE_SIGBUS;		/* Disallow mremap */
+}
+
+#if LINUX_VERSION_CODE < 0x020317
+unsigned long drm_vm_shm_nopage(struct vm_area_struct *vma,
+				unsigned long address,
+				int write_access)
+#else
+				/* Return type changed in 2.3.23 */
+struct page *drm_vm_shm_nopage(struct vm_area_struct *vma,
+			       unsigned long address,
+			       int write_access)
+#endif
+{
+#if LINUX_VERSION_CODE >= 0x020300
+	drm_map_t	 *map	 = (drm_map_t *)vma->vm_private_data;
+#else
+	drm_map_t	 *map	 = (drm_map_t *)vma->vm_pte;
+#endif
+	unsigned long	 physical;
+	unsigned long	 offset;
+
+	if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */
+	if (!map)    		   return NOPAGE_OOM;  /* Nothing allocated */
+
+	offset	 = address - vma->vm_start;
+	physical = (unsigned long)map->handle + offset;
+	atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */
+
+	DRM_DEBUG("0x%08lx => 0x%08lx\n", address, physical);
+#if LINUX_VERSION_CODE < 0x020317
+	return physical;
+#else
+	return virt_to_page(physical);
+#endif
+}
+
+#if LINUX_VERSION_CODE < 0x020317
+unsigned long drm_vm_shm_nopage_lock(struct vm_area_struct *vma,
+				     unsigned long address,
+				     int write_access)
+#else
+				/* Return type changed in 2.3.23 */
+struct page *drm_vm_shm_nopage_lock(struct vm_area_struct *vma,
+				    unsigned long address,
+				    int write_access)
+#endif
+{
+	drm_file_t	 *priv	 = vma->vm_file->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	unsigned long	 physical;
+	unsigned long	 offset;
+	unsigned long	 page;
+
+	if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */
+	if (!dev->lock.hw_lock)    return NOPAGE_OOM;  /* Nothing allocated */
+
+	offset	 = address - vma->vm_start;
+	page	 = offset >> PAGE_SHIFT;
+	physical = (unsigned long)dev->lock.hw_lock + offset;
+	atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */
+
+	DRM_DEBUG("0x%08lx (page %lu) => 0x%08lx\n", address, page, physical);
+#if LINUX_VERSION_CODE < 0x020317
+	return physical;
+#else
+	return virt_to_page(physical);
+#endif
+}
+
+#if LINUX_VERSION_CODE < 0x020317
+unsigned long drm_vm_dma_nopage(struct vm_area_struct *vma,
+				unsigned long address,
+				int write_access)
+#else
+				/* Return type changed in 2.3.23 */
+struct page *drm_vm_dma_nopage(struct vm_area_struct *vma,
+			       unsigned long address,
+			       int write_access)
+#endif
+{
+	drm_file_t	 *priv	 = vma->vm_file->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	unsigned long	 physical;
+	unsigned long	 offset;
+	unsigned long	 page;
+
+	if (!dma)		   return NOPAGE_SIGBUS; /* Error */
+	if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */
+	if (!dma->pagelist)	   return NOPAGE_OOM ; /* Nothing allocated */
+
+	offset	 = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */
+	page	 = offset >> PAGE_SHIFT;
+	physical = dma->pagelist[page] + (offset & (~PAGE_MASK));
+	atomic_inc(&virt_to_page(physical)->count); /* Dec. by kernel */
+
+	DRM_DEBUG("0x%08lx (page %lu) => 0x%08lx\n", address, page, physical);
+#if LINUX_VERSION_CODE < 0x020317
+	return physical;
+#else
+	return virt_to_page(physical);
+#endif
+}
+
+void drm_vm_open(struct vm_area_struct *vma)
+{
+	drm_file_t	*priv	= vma->vm_file->private_data;
+	drm_device_t	*dev	= priv->dev;
+#if DRM_DEBUG_CODE
+	drm_vma_entry_t *vma_entry;
+#endif
+
+	DRM_DEBUG("0x%08lx,0x%08lx\n",
+		  vma->vm_start, vma->vm_end - vma->vm_start);
+	atomic_inc(&dev->vma_count);
+#if LINUX_VERSION_CODE < 0x020333
+				/* The map can exist after the fd is closed. */
+	MOD_INC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+
+
+#if DRM_DEBUG_CODE
+	vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS);
+	if (vma_entry) {
+		down(&dev->struct_sem);
+		vma_entry->vma	= vma;
+		vma_entry->next = dev->vmalist;
+		vma_entry->pid	= current->pid;
+		dev->vmalist	= vma_entry;
+		up(&dev->struct_sem);
+	}
+#endif
+}
+
+void drm_vm_close(struct vm_area_struct *vma)
+{
+	drm_file_t	*priv	= vma->vm_file->private_data;
+	drm_device_t	*dev	= priv->dev;
+#if DRM_DEBUG_CODE
+	drm_vma_entry_t *pt, *prev;
+#endif
+
+	DRM_DEBUG("0x%08lx,0x%08lx\n",
+		  vma->vm_start, vma->vm_end - vma->vm_start);
+#if LINUX_VERSION_CODE < 0x020333
+	MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
+#endif
+	atomic_dec(&dev->vma_count);
+
+#if DRM_DEBUG_CODE
+	down(&dev->struct_sem);
+	for (pt = dev->vmalist, prev = NULL; pt; prev = pt, pt = pt->next) {
+		if (pt->vma == vma) {
+			if (prev) {
+				prev->next = pt->next;
+			} else {
+				dev->vmalist = pt->next;
+			}
+			drm_free(pt, sizeof(*pt), DRM_MEM_VMAS);
+			break;
+		}
+	}
+	up(&dev->struct_sem);
+#endif
+}
+
+int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma)
+{
+	drm_file_t	 *priv	 = filp->private_data;
+	drm_device_t	 *dev;
+	drm_device_dma_t *dma;
+	unsigned long	 length	 = vma->vm_end - vma->vm_start;
+	
+	lock_kernel();
+	dev	 = priv->dev;
+	dma	 = dev->dma;
+	DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
+		  vma->vm_start, vma->vm_end, VM_OFFSET(vma));
+
+				/* Length must match exact page count */
+	if (!dma || (length >> PAGE_SHIFT) != dma->page_count) {
+		unlock_kernel();
+		return -EINVAL;
+	}
+	unlock_kernel();
+
+	vma->vm_ops   = &drm_vm_dma_ops;
+	vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */
+	
+#if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */
+				/* In Linux 2.2.3 and above, this is
+				   handled in do_mmap() in mm/mmap.c. */
+	++filp->f_count;
+#endif
+	vma->vm_file  =	 filp;	/* Needed for drm_vm_open() */
+	drm_vm_open(vma);
+	return 0;
+}
+
+int drm_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	drm_file_t	*priv	= filp->private_data;
+	drm_device_t	*dev	= priv->dev;
+	drm_map_t	*map	= NULL;
+	unsigned long	off;
+	int		i;
+	
+	DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
+		  vma->vm_start, vma->vm_end, VM_OFFSET(vma));
+
+	if (!VM_OFFSET(vma)) return drm_mmap_dma(filp, vma);
+
+				/* A sequential search of a linked list is
+				   fine here because: 1) there will only be
+				   about 5-10 entries in the list and, 2) a
+				   DRI client only has to do this mapping
+				   once, so it doesn't have to be optimized
+				   for performance, even if the list was a
+				   bit longer. */
+	for (i = 0; i < dev->map_count; i++) {
+		map = dev->maplist[i];
+		off = map->offset ^ VM_OFFSET(vma);
+#ifdef	__ia64__
+		/*
+		 * Ignore region bits, makes IA32 processes happier
+		 * XXX This is a hack...
+		 */
+		off &= ~0xe000000000000000;
+#endif	// __ia64__
+		if (off == 0)
+			break;
+	}
+	
+	if (i >= dev->map_count) return -EINVAL;
+	if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN)))
+		return -EPERM;
+
+				/* Check for valid size. */
+	if (map->size != vma->vm_end - vma->vm_start) return -EINVAL;
+	
+	if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) {
+		vma->vm_flags &= VM_MAYWRITE;
+#if defined(__i386__)
+		pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW;
+#else
+				/* Ye gads this is ugly.  With more thought
+                                   we could move this up higher and use
+                                   `protection_map' instead.  */
+		vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect(
+			__pte(pgprot_val(vma->vm_page_prot)))));
+#endif
+	}
+
+	switch (map->type) {
+	case _DRM_AGP:
+#if defined(__ia64__)
+                /*
+                 * On ia64 we can't talk to bus dma address from
+                 * the CPU, so for memory of type DRM_AGP, we'll deal with
+                 * sorting out the real physical pages and mappings in
+                 * in nopage()
+                 */
+                vma->vm_ops = &drm_vm_ops;
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+                break;
+#endif
+	case _DRM_FRAME_BUFFER:
+	case _DRM_REGISTERS:
+		if (VM_OFFSET(vma) >= __pa(high_memory)) {
+#if defined(__i386__)
+			if (boot_cpu_data.x86 > 3 && map->type != _DRM_AGP) {
+				pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
+				pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT;
+			}
+#elif defined(__ia64__)
+			if (map->type != _DRM_AGP)
+				vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+#endif
+			vma->vm_flags |= VM_IO;	/* not in core dump */
+		}
+		if (remap_page_range(vma->vm_start,
+				     VM_OFFSET(vma),
+				     vma->vm_end - vma->vm_start,
+				     vma->vm_page_prot))
+				return -EAGAIN;
+		DRM_DEBUG("   Type = %d; start = 0x%lx, end = 0x%lx,"
+			  " offset = 0x%lx\n",
+			  map->type,
+			  vma->vm_start, vma->vm_end, VM_OFFSET(vma));
+		vma->vm_ops = &drm_vm_ops;
+		break;
+	case _DRM_SHM:
+		if (map->flags & _DRM_CONTAINS_LOCK)
+			vma->vm_ops = &drm_vm_shm_lock_ops;
+		else {
+			vma->vm_ops = &drm_vm_shm_ops;
+#if LINUX_VERSION_CODE >= 0x020300
+			vma->vm_private_data = (void *)map;
+#else
+			vma->vm_pte = (unsigned long)map;
+#endif
+		}
+
+				/* Don't let this area swap.  Change when
+				   DRM_KERNEL advisory is supported. */
+		vma->vm_flags |= VM_LOCKED;
+		break;
+	default:
+		return -EINVAL;	/* This should never happen. */
+	}
+	vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */
+
+#if LINUX_VERSION_CODE < 0x020203 /* KERNEL_VERSION(2,2,3) */
+				/* In Linux 2.2.3 and above, this is
+				   handled in do_mmap() in mm/mmap.c. */
+	++filp->f_count;
+#endif
+	vma->vm_file  =	 filp;	/* Needed for drm_vm_open() */
+	drm_vm_open(vma);
+	return 0;
+}
diff -urN linux-2.4.16/drivers/char/efirtc.c lia64-2.4/drivers/char/efirtc.c
--- linux-2.4.16/drivers/char/efirtc.c	Mon Sep 24 15:06:59 2001
+++ lia64-2.4/drivers/char/efirtc.c	Mon Sep 24 15:22:31 2001
@@ -40,7 +40,7 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 
-#define EFI_RTC_VERSION		"0.2"
+#define EFI_RTC_VERSION		"0.3"
 
 #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT)
 /*
@@ -315,56 +315,45 @@
 	spin_unlock_irqrestore(&efi_rtc_lock,flags);
 
 	p += sprintf(p,
-		     "Time      :\n"
-		     "Year      : %u\n"
-		     "Month     : %u\n"
-		     "Day       : %u\n"
-		     "Hour      : %u\n"
-		     "Minute    : %u\n"
-		     "Second    : %u\n"
-		     "Nanosecond: %u\n"
-		     "Daylight  : %u\n",
-		     eft.year, eft.month, eft.day, eft.hour, eft.minute,
-		     eft.second, eft.nanosecond, eft.daylight);
+		     "Time          : %u:%u:%u.%09u\n"
+		     "Date          : %u-%u-%u\n"
+		     "Daylight      : %u\n",
+		     eft.hour, eft.minute, eft.second, eft.nanosecond, 
+		     eft.year, eft.month, eft.day,
+		     eft.daylight);
 
 	if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE)
-		p += sprintf(p, "Timezone  : unspecified\n");
+		p += sprintf(p, "Timezone       : unspecified\n");
 	else
 		/* XXX fixme: convert to string? */
-		p += sprintf(p, "Timezone  : %u\n", eft.timezone);
+		p += sprintf(p, "Timezone       : %u\n", eft.timezone);
 		
 
 	p += sprintf(p,
-		     "\nWakeup Alm:\n"
-		     "Enabled   : %s\n"
-		     "Pending   : %s\n"
-		     "Year      : %u\n"
-		     "Month     : %u\n"
-		     "Day       : %u\n"
-		     "Hour      : %u\n"
-		     "Minute    : %u\n"
-		     "Second    : %u\n"
-		     "Nanosecond: %u\n"
-		     "Daylight  : %u\n",
-		     enabled == 1 ? "Yes" : "No",
-		     pending == 1 ? "Yes" : "No",
-		     alm.year, alm.month, alm.day, alm.hour, alm.minute,
-		     alm.second, alm.nanosecond, alm.daylight);
+		     "Alarm Time     : %u:%u:%u.%09u\n"
+		     "Alarm Date     : %u-%u-%u\n"
+		     "Alarm Daylight : %u\n"
+		     "Enabled        : %s\n"
+		     "Pending        : %s\n",
+		     alm.hour, alm.minute, alm.second, alm.nanosecond, 
+		     alm.year, alm.month, alm.day, 
+		     alm.daylight,
+		     enabled == 1 ? "yes" : "no",
+		     pending == 1 ? "yes" : "no");
 
 	if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE)
-		p += sprintf(p, "Timezone  : unspecified\n");
+		p += sprintf(p, "Timezone       : unspecified\n");
 	else
 		/* XXX fixme: convert to string? */
-		p += sprintf(p, "Timezone  : %u\n", eft.timezone);
+		p += sprintf(p, "Timezone       : %u\n", alm.timezone);
 
 	/*
 	 * now prints the capabilities
 	 */
 	p += sprintf(p,
-		     "\nClock Cap :\n"
-		     "Resolution: %u\n"
-		     "Accuracy  : %u\n"
-		     "SetstoZero: %u\n",
+		     "Resolution     : %u\n"
+		     "Accuracy       : %u\n"
+		     "SetstoZero     : %u\n",
 		      cap.resolution, cap.accuracy, cap.sets_to_zero);
 
 	return  p - buf;
@@ -390,7 +379,7 @@
 
 	misc_register(&efi_rtc_dev);
 
-	create_proc_read_entry ("efirtc", 0, NULL, efi_rtc_read_proc, NULL);
+	create_proc_read_entry ("driver/efirtc", 0, NULL, efi_rtc_read_proc, NULL);
 
 	return 0;
 }
diff -urN linux-2.4.16/drivers/char/mem.c lia64-2.4/drivers/char/mem.c
--- linux-2.4.16/drivers/char/mem.c	Mon Sep 24 15:07:02 2001
+++ lia64-2.4/drivers/char/mem.c	Mon Sep 24 15:22:34 2001
@@ -191,9 +191,13 @@
 	 * through a file pointer that was marked O_SYNC will be
 	 * done non-cached.
 	 */
-	if (noncached_address(offset) || (file->f_flags & O_SYNC))
+	if (noncached_address(offset) || (file->f_flags & O_SYNC)
+	    || (vma->vm_flags & VM_NONCACHED))
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
+	if (vma->vm_flags & VM_WRITECOMBINED)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
 	/* Don't try to swap out physical pages.. */
 	vma->vm_flags |= VM_RESERVED;
 
@@ -470,13 +474,15 @@
 	switch (orig) {
 		case 0:
 			file->f_pos = offset;
-			return file->f_pos;
+			break;
 		case 1:
 			file->f_pos += offset;
-			return file->f_pos;
+			break;
 		default:
 			return -EINVAL;
 	}
+	force_successful_syscall_return();
+	return file->f_pos;
 }
 
 static int open_port(struct inode * inode, struct file * filp)
diff -urN linux-2.4.16/drivers/char/simserial.c lia64-2.4/drivers/char/simserial.c
--- linux-2.4.16/drivers/char/simserial.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/char/simserial.c	Mon Nov 26 17:16:34 2001
@@ -0,0 +1,1095 @@
+/*
+ * Simulated Serial Driver (fake serial)
+ *
+ * This driver is mostly used for bringup purposes and will go away.
+ * It has a strong dependency on the system console. All outputs
+ * are rerouted to the same facility as the one used by printk which, in our
+ * case means sys_sim.c console (goes via the simulator). The code hereafter
+ * is completely leveraged from the serial.c driver.
+ *
+ * Copyright (C) 1999-2000 Hewlett-Packard Co
+ * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * 02/04/00 D. Mosberger	Merged in serial.c bug fixes in rs_close().
+ * 02/25/00 D. Mosberger	Synced up with 2.3.99pre-5 version of serial.c.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/major.h>
+#include <linux/fcntl.h>
+#include <linux/mm.h>
+#include <linux/malloc.h>
+#include <linux/console.h>
+#include <linux/module.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#undef SIMSERIAL_DEBUG	/* define this to get some debug information */
+
+#define KEYBOARD_INTR	3	/* must match with simulator! */
+
+#define NR_PORTS	1	/* only one port for now */
+#define SERIAL_INLINE	1
+
+#ifdef SERIAL_INLINE
+#define _INLINE_ inline
+#endif
+
+#ifndef MIN
+#define MIN(a,b)	((a) < (b) ? (a) : (b))
+#endif
+
+#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT)
+
+#define SSC_GETCHAR	21
+
+extern long ia64_ssc (long, long, long, long, int);
+extern void ia64_ssc_connect_irq (long intr, long irq);
+
+static char *serial_name = "SimSerial driver";
+static char *serial_version = "0.6";
+
+/*
+ * This has been extracted from asm/serial.h. We need one eventually but
+ * I don't know exactly what we're going to put in it so just fake one
+ * for now.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+/*
+ * Most of the values here are meaningless to this particular driver.
+ * However some values must be preserved for the code (leveraged from serial.c
+ * to work correctly).
+ * port must not be 0
+ * type must not be UNKNOWN
+ * So I picked arbitrary (guess from where?) values instead
+ */
+static struct serial_state rs_table[NR_PORTS]={
+  /* UART CLK   PORT IRQ     FLAGS        */
+  { 0, BASE_BAUD, 0x3F8, 0, STD_COM_FLAGS,0,PORT_16550 }  /* ttyS0 */
+};
+
+/*
+ * Just for the fun of it !
+ */
+static struct serial_uart_config uart_config[] = {
+	{ "unknown", 1, 0 },
+	{ "8250", 1, 0 },
+	{ "16450", 1, 0 },
+	{ "16550", 1, 0 },
+	{ "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
+	{ "cirrus", 1, 0 },
+	{ "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
+	{ "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO |
+		  UART_STARTECH },
+	{ "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO},
+	{ 0, 0}
+};
+
+static struct tty_driver serial_driver, callout_driver;
+static int serial_refcount;
+
+static struct async_struct *IRQ_ports[NR_IRQS];
+static struct tty_struct *serial_table[NR_PORTS];
+static struct termios *serial_termios[NR_PORTS];
+static struct termios *serial_termios_locked[NR_PORTS];
+
+static struct console *console;
+
+static unsigned char *tmp_buf;
+static DECLARE_MUTEX(tmp_buf_sem);
+
+extern struct console *console_drivers; /* from kernel/printk.c */
+
+/*
+ * ------------------------------------------------------------
+ * rs_stop() and rs_start()
+ *
+ * This routines are called before setting or resetting tty->stopped.
+ * They enable or disable transmitter interrupts, as necessary.
+ * ------------------------------------------------------------
+ */
+static void rs_stop(struct tty_struct *tty)
+{
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_stop: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n",
+		tty->stopped, tty->hw_stopped, tty->flow_stopped);
+#endif
+
+}
+
+static void rs_start(struct tty_struct *tty)
+{
+#if SIMSERIAL_DEBUG
+	printk("rs_start: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n",
+		tty->stopped, tty->hw_stopped, tty->flow_stopped);
+#endif
+}
+
+static  void receive_chars(struct tty_struct *tty, struct pt_regs *regs)
+{
+	unsigned char ch;
+	static unsigned char seen_esc = 0;
+
+	while ( (ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR)) ) {
+		if ( ch == 27 && seen_esc == 0 ) {
+			seen_esc = 1;
+			continue;
+		} else {
+			if ( seen_esc==1 && ch == 'O' ) {
+				seen_esc = 2;
+				continue;
+			} else if ( seen_esc == 2 ) {
+				if ( ch == 'P' ) show_state();		/* F1 key */
+				if ( ch == 'Q' ) show_buffers();	/* F2 key */
+				seen_esc = 0;
+				continue;
+			}
+		}
+		seen_esc = 0;
+		if (tty->flip.count >= TTY_FLIPBUF_SIZE) break;
+
+		*tty->flip.char_buf_ptr = ch;
+
+		*tty->flip.flag_buf_ptr = 0;
+
+		tty->flip.flag_buf_ptr++;
+		tty->flip.char_buf_ptr++;
+		tty->flip.count++;
+	}
+	tty_flip_buffer_push(tty);
+}
+
+/*
+ * This is the serial driver's interrupt routine for a single port
+ */
+static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct async_struct * info;
+
+	/*
+	 * I don't know exactly why they don't use the dev_id opaque data
+	 * pointer instead of this extra lookup table
+	 */
+	info = IRQ_ports[irq];
+	if (!info || !info->tty) {
+		printk("simrs_interrupt_single: info|tty=0 info=%p problem\n", info);
+		return;
+	}
+	/*
+	 * pretty simple in our case, because we only get interrupts
+	 * on inbound traffic
+	 */
+	receive_chars(info->tty, regs);
+}
+
+/*
+ * -------------------------------------------------------------------
+ * Here ends the serial interrupt routines.
+ * -------------------------------------------------------------------
+ */
+
+#if 0
+/*
+ * not really used in our situation so keep them commented out for now
+ */
+static DECLARE_TASK_QUEUE(tq_serial); /* used to be at the top of the file */
+static void do_serial_bh(void)
+{
+	run_task_queue(&tq_serial);
+	printk("do_serial_bh: called\n");
+}
+#endif
+
+static void do_softint(void *private_)
+{
+	printk("simserial: do_softint called\n");
+}
+
+static void rs_put_char(struct tty_struct *tty, unsigned char ch)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	if (!tty || !info->xmit.buf) return;
+
+	save_flags(flags); cli();
+	if (CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) == 0) {
+		restore_flags(flags);
+		return;
+	}
+	info->xmit.buf[info->xmit.head] = ch;
+	info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
+	restore_flags(flags);
+}
+
+static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done)
+{
+	int count;
+	unsigned long flags;
+
+	save_flags(flags); cli();
+
+	if (info->x_char) {
+		char c = info->x_char;
+
+		console->write(console, &c, 1);
+
+		info->state->icount.tx++;
+		info->x_char = 0;
+
+		goto out;
+	}
+
+	if (info->xmit.head == info->xmit.tail || info->tty->stopped || info->tty->hw_stopped) {
+#ifdef SIMSERIAL_DEBUG
+		printk("transmit_chars: head=%d, tail=%d, stopped=%d\n",
+		       info->xmit.head, info->xmit.tail, info->tty->stopped);
+#endif
+		goto out;
+	}
+	/*
+	 * We removed the loop and try to do it in to chunks. We need
+	 * 2 operations maximum because it's a ring buffer.
+	 *
+	 * First from current to tail if possible.
+	 * Then from the beginning of the buffer until necessary
+	 */
+
+	count = MIN(CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE),
+		    SERIAL_XMIT_SIZE - info->xmit.tail);
+	console->write(console, info->xmit.buf+info->xmit.tail, count);
+
+	info->xmit.tail = (info->xmit.tail+count) & (SERIAL_XMIT_SIZE-1);
+
+	/*
+	 * We have more at the beginning of the buffer
+	 */
+	count = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+	if (count) {
+		console->write(console, info->xmit.buf, count);
+		info->xmit.tail += count;
+	}
+out:
+	restore_flags(flags);
+}
+
+static void rs_flush_chars(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	if (info->xmit.head == info->xmit.tail || tty->stopped || tty->hw_stopped ||
+	    !info->xmit.buf)
+		return;
+
+	transmit_chars(info, NULL);
+}
+
+
+static int rs_write(struct tty_struct * tty, int from_user,
+		    const unsigned char *buf, int count)
+{
+	int	c, ret = 0;
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	if (!tty || !info->xmit.buf || !tmp_buf) return 0;
+
+	save_flags(flags);
+	if (from_user) {
+		down(&tmp_buf_sem);
+		while (1) {
+			int c1;
+			c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (count < c)
+				c = count;
+			if (c <= 0)
+				break;
+
+			c -= copy_from_user(tmp_buf, buf, c);
+			if (!c) {
+				if (!ret)
+					ret = -EFAULT;
+				break;
+			}
+			cli();
+			c1 = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (c1 < c)
+				c = c1;
+			memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c);
+			info->xmit.head = ((info->xmit.head + c) &
+					   (SERIAL_XMIT_SIZE-1));
+			restore_flags(flags);
+			buf += c;
+			count -= c;
+			ret += c;
+		}
+		up(&tmp_buf_sem);
+	} else {
+		cli();
+		while (1) {
+			c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (count < c)
+				c = count;
+			if (c <= 0) {
+				break;
+			}
+			memcpy(info->xmit.buf + info->xmit.head, buf, c);
+			info->xmit.head = ((info->xmit.head + c) &
+					   (SERIAL_XMIT_SIZE-1));
+			buf += c;
+			count -= c;
+			ret += c;
+		}
+		restore_flags(flags);
+	}
+	/*
+	 * Hey, we transmit directly from here in our case
+	 */
+	if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE)
+	    && !tty->stopped && !tty->hw_stopped) {
+		transmit_chars(info, NULL);
+	}
+	return ret;
+}
+
+static int rs_write_room(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+}
+
+static int rs_chars_in_buffer(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+}
+
+static void rs_flush_buffer(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	save_flags(flags); cli();
+	info->xmit.head = info->xmit.tail = 0;
+	restore_flags(flags);
+
+	wake_up_interruptible(&tty->write_wait);
+
+	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
+	    tty->ldisc.write_wakeup)
+		(tty->ldisc.write_wakeup)(tty);
+}
+
+/*
+ * This function is used to send a high-priority XON/XOFF character to
+ * the device
+ */
+static void rs_send_xchar(struct tty_struct *tty, char ch)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	info->x_char = ch;
+	if (ch) {
+		/*
+		 * I guess we could call console->write() directly but
+		 * let's do that for now.
+		 */
+		transmit_chars(info, NULL);
+	}
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_throttle()
+ *
+ * This routine is called by the upper-layer tty layer to signal that
+ * incoming characters should be throttled.
+ * ------------------------------------------------------------
+ */
+static void rs_throttle(struct tty_struct * tty)
+{
+	if (I_IXOFF(tty)) rs_send_xchar(tty, STOP_CHAR(tty));
+
+	printk("simrs_throttle called\n");
+}
+
+static void rs_unthrottle(struct tty_struct * tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	if (I_IXOFF(tty)) {
+		if (info->x_char)
+			info->x_char = 0;
+		else
+			rs_send_xchar(tty, START_CHAR(tty));
+	}
+	printk("simrs_unthrottle called\n");
+}
+
+/*
+ * rs_break() --- routine which turns the break handling on or off
+ */
+static void rs_break(struct tty_struct *tty, int break_state)
+{
+}
+
+static int rs_ioctl(struct tty_struct *tty, struct file * file,
+		    unsigned int cmd, unsigned long arg)
+{
+	if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
+	    (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) &&
+	    (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
+		if (tty->flags & (1 << TTY_IO_ERROR))
+		    return -EIO;
+	}
+
+	switch (cmd) {
+		case TIOCMGET:
+			printk("rs_ioctl: TIOCMGET called\n");
+			return -EINVAL;
+		case TIOCMBIS:
+		case TIOCMBIC:
+		case TIOCMSET:
+			printk("rs_ioctl: TIOCMBIS/BIC/SET called\n");
+			return -EINVAL;
+		case TIOCGSERIAL:
+			printk("simrs_ioctl TIOCGSERIAL called\n");
+			return 0;
+		case TIOCSSERIAL:
+			printk("simrs_ioctl TIOCSSERIAL called\n");
+			return 0;
+		case TIOCSERCONFIG:
+			printk("rs_ioctl: TIOCSERCONFIG called\n");
+			return -EINVAL;
+
+		case TIOCSERGETLSR: /* Get line status register */
+			printk("rs_ioctl: TIOCSERGETLSR called\n");
+			return  -EINVAL;
+
+		case TIOCSERGSTRUCT:
+			printk("rs_ioctl: TIOCSERGSTRUCT called\n");
+#if 0
+			if (copy_to_user((struct async_struct *) arg,
+					 info, sizeof(struct async_struct)))
+				return -EFAULT;
+#endif
+			return 0;
+
+		/*
+		 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
+		 * - mask passed in arg for lines of interest
+		 *   (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
+		 * Caller should use TIOCGICOUNT to see which one it was
+		 */
+		case TIOCMIWAIT:
+			printk("rs_ioctl: TIOCMIWAIT: called\n");
+			return 0;
+		/*
+		 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
+		 * Return: write counters to the user passed counter struct
+		 * NB: both 1->0 and 0->1 transitions are counted except for
+		 *     RI where only 0->1 is counted.
+		 */
+		case TIOCGICOUNT:
+			printk("rs_ioctl: TIOCGICOUNT called\n");
+			return 0;
+
+		case TIOCSERGWILD:
+		case TIOCSERSWILD:
+			/* "setserial -W" is called in Debian boot */
+			printk ("TIOCSER?WILD ioctl obsolete, ignored.\n");
+			return 0;
+
+		default:
+			return -ENOIOCTLCMD;
+		}
+	return 0;
+}
+
+#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
+
+static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios)
+{
+	unsigned int cflag = tty->termios->c_cflag;
+
+	if (   (cflag == old_termios->c_cflag)
+	    && (   RELEVANT_IFLAG(tty->termios->c_iflag)
+		== RELEVANT_IFLAG(old_termios->c_iflag)))
+	  return;
+
+
+	/* Handle turning off CRTSCTS */
+	if ((old_termios->c_cflag & CRTSCTS) &&
+	    !(tty->termios->c_cflag & CRTSCTS)) {
+		tty->hw_stopped = 0;
+		rs_start(tty);
+	}
+}
+/*
+ * This routine will shutdown a serial port; interrupts are disabled, and
+ * DTR is dropped if the hangup on close termio flag is on.
+ */
+static void shutdown(struct async_struct * info)
+{
+	unsigned long	flags;
+	struct serial_state *state;
+	int		retval;
+
+	if (!(info->flags & ASYNC_INITIALIZED)) return;
+
+	state = info->state;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("Shutting down serial port %d (irq %d)....", info->line,
+	       state->irq);
+#endif
+
+	save_flags(flags); cli(); /* Disable interrupts */
+
+	/*
+	 * First unlink the serial port from the IRQ chain...
+	 */
+	if (info->next_port)
+		info->next_port->prev_port = info->prev_port;
+	if (info->prev_port)
+		info->prev_port->next_port = info->next_port;
+	else
+		IRQ_ports[state->irq] = info->next_port;
+
+	/*
+	 * Free the IRQ, if necessary
+	 */
+	if (state->irq && (!IRQ_ports[state->irq] ||
+			  !IRQ_ports[state->irq]->next_port)) {
+		if (IRQ_ports[state->irq]) {
+			free_irq(state->irq, NULL);
+			retval = request_irq(state->irq, rs_interrupt_single,
+					     IRQ_T(info), "serial", NULL);
+
+			if (retval)
+				printk("serial shutdown: request_irq: error %d"
+				       "  Couldn't reacquire IRQ.\n", retval);
+		} else
+			free_irq(state->irq, NULL);
+	}
+
+	if (info->xmit.buf) {
+		free_page((unsigned long) info->xmit.buf);
+		info->xmit.buf = 0;
+	}
+
+	if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags);
+
+	info->flags &= ~ASYNC_INITIALIZED;
+	restore_flags(flags);
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_close()
+ *
+ * This routine is called when the serial port gets closed.  First, we
+ * wait for the last remaining data to be sent.  Then, we unlink its
+ * async structure from the interrupt chain if necessary, and we free
+ * that IRQ if nothing is left in the chain.
+ * ------------------------------------------------------------
+ */
+static void rs_close(struct tty_struct *tty, struct file * filp)
+{
+	struct async_struct * info = (struct async_struct *)tty->driver_data;
+	struct serial_state *state;
+	unsigned long flags;
+
+	if (!info ) return;
+
+	state = info->state;
+
+	save_flags(flags); cli();
+
+	if (tty_hung_up_p(filp)) {
+#ifdef SIMSERIAL_DEBUG
+		printk("rs_close: hung_up\n");
+#endif
+		MOD_DEC_USE_COUNT;
+		restore_flags(flags);
+		return;
+	}
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_close ttys%d, count = %d\n", info->line, state->count);
+#endif
+	if ((tty->count == 1) && (state->count != 1)) {
+		/*
+		 * Uh, oh.  tty->count is 1, which means that the tty
+		 * structure will be freed.  state->count should always
+		 * be one in these conditions.  If it's greater than
+		 * one, we've got real problems, since it means the
+		 * serial port won't be shutdown.
+		 */
+		printk("rs_close: bad serial port count; tty->count is 1, "
+		       "state->count is %d\n", state->count);
+		state->count = 1;
+	}
+	if (--state->count < 0) {
+		printk("rs_close: bad serial port count for ttys%d: %d\n",
+		       info->line, state->count);
+		state->count = 0;
+	}
+	if (state->count) {
+		MOD_DEC_USE_COUNT;
+		restore_flags(flags);
+		return;
+	}
+	info->flags |= ASYNC_CLOSING;
+	restore_flags(flags);
+
+	/*
+	 * Now we wait for the transmit buffer to clear; and we notify
+	 * the line discipline to only process XON/XOFF characters.
+	 */
+	shutdown(info);
+	if (tty->driver.flush_buffer) tty->driver.flush_buffer(tty);
+	if (tty->ldisc.flush_buffer) tty->ldisc.flush_buffer(tty);
+	info->event = 0;
+	info->tty = 0;
+	if (info->blocked_open) {
+		if (info->close_delay) {
+			current->state = TASK_INTERRUPTIBLE;
+			schedule_timeout(info->close_delay);
+		}
+		wake_up_interruptible(&info->open_wait);
+	}
+	info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|ASYNC_CLOSING);
+	wake_up_interruptible(&info->close_wait);
+	MOD_DEC_USE_COUNT;
+}
+
+/*
+ * rs_wait_until_sent() --- wait until the transmitter is empty
+ */
+static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
+{
+}
+
+
+/*
+ * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
+ */
+static void rs_hangup(struct tty_struct *tty)
+{
+	struct async_struct * info = (struct async_struct *)tty->driver_data;
+	struct serial_state *state = info->state;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_hangup: called\n");
+#endif
+
+	state = info->state;
+
+	rs_flush_buffer(tty);
+	if (info->flags & ASYNC_CLOSING)
+		return;
+	shutdown(info);
+
+	info->event = 0;
+	state->count = 0;
+	info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
+	info->tty = 0;
+	wake_up_interruptible(&info->open_wait);
+}
+
+
+static int get_async_struct(int line, struct async_struct **ret_info)
+{
+	struct async_struct *info;
+	struct serial_state *sstate;
+
+	sstate = rs_table + line;
+	sstate->count++;
+	if (sstate->info) {
+		*ret_info = sstate->info;
+		return 0;
+	}
+	info = kmalloc(sizeof(struct async_struct), GFP_KERNEL);
+	if (!info) {
+		sstate->count--;
+		return -ENOMEM;
+	}
+	memset(info, 0, sizeof(struct async_struct));
+	init_waitqueue_head(&info->open_wait);
+	init_waitqueue_head(&info->close_wait);
+	init_waitqueue_head(&info->delta_msr_wait);
+	info->magic = SERIAL_MAGIC;
+	info->port = sstate->port;
+	info->flags = sstate->flags;
+	info->xmit_fifo_size = sstate->xmit_fifo_size;
+	info->line = line;
+	info->tqueue.routine = do_softint;
+	info->tqueue.data = info;
+	info->state = sstate;
+	if (sstate->info) {
+		kfree(info);
+		*ret_info = sstate->info;
+		return 0;
+	}
+	*ret_info = sstate->info = info;
+	return 0;
+}
+
+static int
+startup(struct async_struct *info)
+{
+	unsigned long flags;
+	int	retval=0;
+	void (*handler)(int, void *, struct pt_regs *);
+	struct serial_state *state= info->state;
+	unsigned long page;
+
+	page = get_free_page(GFP_KERNEL);
+	if (!page)
+		return -ENOMEM;
+
+	save_flags(flags); cli();
+
+	if (info->flags & ASYNC_INITIALIZED) {
+		free_page(page);
+		goto errout;
+	}
+
+	if (!state->port || !state->type) {
+		if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags);
+		free_page(page);
+		goto errout;
+	}
+	if (info->xmit.buf)
+		free_page(page);
+	else
+		info->xmit.buf = (unsigned char *) page;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("startup: ttys%d (irq %d)...", info->line, state->irq);
+#endif
+
+	/*
+	 * Allocate the IRQ if necessary
+	 */
+	if (state->irq && (!IRQ_ports[state->irq] ||
+			  !IRQ_ports[state->irq]->next_port)) {
+		if (IRQ_ports[state->irq]) {
+			retval = -EBUSY;
+			goto errout;
+		} else
+			handler = rs_interrupt_single;
+
+		retval = request_irq(state->irq, handler, IRQ_T(info),
+				     "simserial", NULL);
+		if (retval) {
+			if (capable(CAP_SYS_ADMIN)) {
+				if (info->tty)
+					set_bit(TTY_IO_ERROR,
+						&info->tty->flags);
+				retval = 0;
+			}
+			goto errout;
+		}
+	}
+
+	/*
+	 * Insert serial port into IRQ chain.
+	 */
+	info->prev_port = 0;
+	info->next_port = IRQ_ports[state->irq];
+	if (info->next_port)
+		info->next_port->prev_port = info;
+	IRQ_ports[state->irq] = info;
+
+	if (info->tty) clear_bit(TTY_IO_ERROR, &info->tty->flags);
+
+	info->xmit.head = info->xmit.tail = 0;
+
+#if 0
+	/*
+	 * Set up serial timers...
+	 */
+	timer_table[RS_TIMER].expires = jiffies + 2*HZ/100;
+	timer_active |= 1 << RS_TIMER;
+#endif
+
+	/*
+	 * Set up the tty->alt_speed kludge
+	 */
+	if (info->tty) {
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
+			info->tty->alt_speed = 57600;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
+			info->tty->alt_speed = 115200;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
+			info->tty->alt_speed = 230400;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
+			info->tty->alt_speed = 460800;
+	}
+
+	info->flags |= ASYNC_INITIALIZED;
+	restore_flags(flags);
+	return 0;
+
+errout:
+	restore_flags(flags);
+	return retval;
+}
+
+
+/*
+ * This routine is called whenever a serial port is opened.  It
+ * enables interrupts for a serial port, linking in its async structure into
+ * the IRQ chain.   It also performs the serial-specific
+ * initialization for the tty structure.
+ */
+static int rs_open(struct tty_struct *tty, struct file * filp)
+{
+	struct async_struct	*info;
+	int			retval, line;
+	unsigned long		page;
+
+	MOD_INC_USE_COUNT;
+	line = MINOR(tty->device) - tty->driver.minor_start;
+	if ((line < 0) || (line >= NR_PORTS)) {
+		MOD_DEC_USE_COUNT;
+		return -ENODEV;
+	}
+	retval = get_async_struct(line, &info);
+	if (retval) {
+		MOD_DEC_USE_COUNT;
+		return retval;
+	}
+	tty->driver_data = info;
+	info->tty = tty;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line,
+	       info->state->count);
+#endif
+	info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
+
+	if (!tmp_buf) {
+		page = get_free_page(GFP_KERNEL);
+		if (!page) {
+			/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+			return -ENOMEM;
+		}
+		if (tmp_buf)
+			free_page(page);
+		else
+			tmp_buf = (unsigned char *) page;
+	}
+
+	/*
+	 * If the port is the middle of closing, bail out now
+	 */
+	if (tty_hung_up_p(filp) ||
+	    (info->flags & ASYNC_CLOSING)) {
+		if (info->flags & ASYNC_CLOSING)
+			interruptible_sleep_on(&info->close_wait);
+		/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+#ifdef SERIAL_DO_RESTART
+		return ((info->flags & ASYNC_HUP_NOTIFY) ?
+			-EAGAIN : -ERESTARTSYS);
+#else
+		return -EAGAIN;
+#endif
+	}
+
+	/*
+	 * Start up serial port
+	 */
+	retval = startup(info);
+	if (retval) {
+		/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+		return retval;
+	}
+
+	if ((info->state->count == 1) &&
+	    (info->flags & ASYNC_SPLIT_TERMIOS)) {
+		if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
+			*tty->termios = info->state->normal_termios;
+		else
+			*tty->termios = info->state->callout_termios;
+	}
+
+	/*
+	 * figure out which console to use (should be one already)
+	 */
+	console = console_drivers;
+	while (console) {
+		if ((console->flags & CON_ENABLED) && console->write) break;
+		console = console->next;
+	}
+
+	info->session = current->session;
+	info->pgrp = current->pgrp;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_open ttys%d successful\n", info->line);
+#endif
+	return 0;
+}
+
+/*
+ * /proc fs routines....
+ */
+
+static inline int line_info(char *buf, struct serial_state *state)
+{
+	return sprintf(buf, "%d: uart:%s port:%lX irq:%d\n",
+		       state->line, uart_config[state->type].name,
+		       state->port, state->irq);
+}
+
+int rs_read_proc(char *page, char **start, off_t off, int count,
+		 int *eof, void *data)
+{
+	int i, len = 0, l;
+	off_t	begin = 0;
+
+	len += sprintf(page, "simserinfo:1.0 driver:%s\n", serial_version);
+	for (i = 0; i < NR_PORTS && len < 4000; i++) {
+		l = line_info(page + len, &rs_table[i]);
+		len += l;
+		if (len+begin > off+count)
+			goto done;
+		if (len+begin < off) {
+			begin += len;
+			len = 0;
+		}
+	}
+	*eof = 1;
+done:
+	if (off >= len+begin)
+		return 0;
+	*start = page + (begin-off);
+	return ((count < begin+len-off) ? count : begin+len-off);
+}
+
+/*
+ * ---------------------------------------------------------------------
+ * rs_init() and friends
+ *
+ * rs_init() is called at boot-time to initialize the serial driver.
+ * ---------------------------------------------------------------------
+ */
+
+/*
+ * This routine prints out the appropriate serial driver version
+ * number, and identifies which options were configured into this
+ * driver.
+ */
+static inline void show_serial_version(void)
+{
+	printk(KERN_INFO "%s version %s with", serial_name, serial_version);
+	printk(" no serial options enabled\n");
+}
+
+/*
+ * The serial driver boot-time initialization code!
+ */
+static int __init
+simrs_init (void)
+{
+	int			i;
+	struct serial_state	*state;
+
+	show_serial_version();
+
+	/* Initialize the tty_driver structure */
+
+	memset(&serial_driver, 0, sizeof(struct tty_driver));
+	serial_driver.magic = TTY_DRIVER_MAGIC;
+	serial_driver.driver_name = "simserial";
+	serial_driver.name = "ttyS";
+	serial_driver.major = TTY_MAJOR;
+	serial_driver.minor_start = 64;
+	serial_driver.num = 1;
+	serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
+	serial_driver.subtype = SERIAL_TYPE_NORMAL;
+	serial_driver.init_termios = tty_std_termios;
+	serial_driver.init_termios.c_cflag =
+		B9600 | CS8 | CREAD | HUPCL | CLOCAL;
+	serial_driver.flags = TTY_DRIVER_REAL_RAW;
+	serial_driver.refcount = &serial_refcount;
+	serial_driver.table = serial_table;
+	serial_driver.termios = serial_termios;
+	serial_driver.termios_locked = serial_termios_locked;
+
+	serial_driver.open = rs_open;
+	serial_driver.close = rs_close;
+	serial_driver.write = rs_write;
+	serial_driver.put_char = rs_put_char;
+	serial_driver.flush_chars = rs_flush_chars;
+	serial_driver.write_room = rs_write_room;
+	serial_driver.chars_in_buffer = rs_chars_in_buffer;
+	serial_driver.flush_buffer = rs_flush_buffer;
+	serial_driver.ioctl = rs_ioctl;
+	serial_driver.throttle = rs_throttle;
+	serial_driver.unthrottle = rs_unthrottle;
+	serial_driver.send_xchar = rs_send_xchar;
+	serial_driver.set_termios = rs_set_termios;
+	serial_driver.stop = rs_stop;
+	serial_driver.start = rs_start;
+	serial_driver.hangup = rs_hangup;
+	serial_driver.break_ctl = rs_break;
+	serial_driver.wait_until_sent = rs_wait_until_sent;
+	serial_driver.read_proc = rs_read_proc;
+
+	/*
+	 * Let's have a little bit of fun !
+	 */
+	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
+
+		if (state->type == PORT_UNKNOWN) continue;
+
+		if (!state->irq) {
+			state->irq = ia64_alloc_irq();
+			ia64_ssc_connect_irq(KEYBOARD_INTR, state->irq);
+		}
+
+		printk(KERN_INFO "ttyS%02d at 0x%04lx (irq = %d) is a %s\n",
+		       state->line,
+		       state->port, state->irq,
+		       uart_config[state->type].name);
+	}
+	/*
+	 * The callout device is just like normal device except for
+	 * major number and the subtype code.
+	 */
+	callout_driver = serial_driver;
+	callout_driver.name = "cua";
+	callout_driver.major = TTYAUX_MAJOR;
+	callout_driver.subtype = SERIAL_TYPE_CALLOUT;
+	callout_driver.read_proc = 0;
+	callout_driver.proc_entry = 0;
+
+	if (tty_register_driver(&serial_driver))
+		panic("Couldn't register simserial driver\n");
+
+	if (tty_register_driver(&callout_driver))
+		panic("Couldn't register callout driver\n");
+
+	return 0;
+}
+
+#ifndef MODULE
+__initcall(simrs_init);
+#endif
diff -urN linux-2.4.16/drivers/ide/ide-geometry.c lia64-2.4/drivers/ide/ide-geometry.c
--- linux-2.4.16/drivers/ide/ide-geometry.c	Mon Nov 26 11:18:36 2001
+++ lia64-2.4/drivers/ide/ide-geometry.c	Mon Nov 26 11:21:31 2001
@@ -3,8 +3,11 @@
  */
 #include <linux/config.h>
 #include <linux/ide.h>
-#include <linux/mc146818rtc.h>
 #include <asm/io.h>
+
+#ifdef __i386__
+# include <linux/mc146818rtc.h>
+#endif
 
 /*
  * We query CMOS about hard disks : it could be that we have a SCSI/ESDI/etc
diff -urN linux-2.4.16/drivers/input/joydev.c lia64-2.4/drivers/input/joydev.c
--- linux-2.4.16/drivers/input/joydev.c	Wed Oct 10 16:31:46 2001
+++ lia64-2.4/drivers/input/joydev.c	Wed Oct 10 16:34:43 2001
@@ -87,6 +87,12 @@
 MODULE_LICENSE("GPL");
 MODULE_SUPPORTED_DEVICE("input/js");
 
+static inline unsigned long
+jiffies_to_msec (unsigned long t)
+{
+	return 1000*(t / HZ) + 1000*(t % HZ)/HZ;
+}
+
 static int joydev_correct(int value, struct js_corr *corr)
 {
 	switch (corr->type) {
@@ -134,7 +140,7 @@
 			return;
 	}  
 
-	event.time = jiffies * (1000 / HZ);
+	event.time = jiffies_to_msec(jiffies);
 
 	while (list) {
 
@@ -279,7 +285,7 @@
 
 		struct js_event event;
 
-		event.time = jiffies * (1000/HZ);
+		event.time = jiffies_to_msec(jiffies);
 
 		if (list->startup < joydev->nkey) {
 			event.type = JS_EVENT_BUTTON | JS_EVENT_INIT;
diff -urN linux-2.4.16/drivers/media/radio/Makefile lia64-2.4/drivers/media/radio/Makefile
--- linux-2.4.16/drivers/media/radio/Makefile	Sun Aug  5 13:15:05 2001
+++ lia64-2.4/drivers/media/radio/Makefile	Mon Aug 13 23:45:57 2001
@@ -11,7 +11,7 @@
 
 # Object file lists.
 
-obj-y		:=
+obj-y		:= dummy.o
 obj-m		:=
 obj-n		:=
 obj-		:=
diff -urN linux-2.4.16/drivers/media/radio/dummy.c lia64-2.4/drivers/media/radio/dummy.c
--- linux-2.4.16/drivers/media/radio/dummy.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/media/radio/dummy.c	Tue Jan 23 01:18:20 2001
@@ -0,0 +1 @@
+/* just so the linker knows what kind of object files it's deadling with... */
diff -urN linux-2.4.16/drivers/media/video/Makefile lia64-2.4/drivers/media/video/Makefile
--- linux-2.4.16/drivers/media/video/Makefile	Mon Nov 26 11:18:38 2001
+++ lia64-2.4/drivers/media/video/Makefile	Mon Nov 26 11:21:33 2001
@@ -11,7 +11,7 @@
 
 # Object file lists.
 
-obj-y		:=
+obj-y		:= dummy.o
 obj-m		:=
 obj-n		:=
 obj-		:=
diff -urN linux-2.4.16/drivers/media/video/dummy.c lia64-2.4/drivers/media/video/dummy.c
--- linux-2.4.16/drivers/media/video/dummy.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/media/video/dummy.c	Mon Oct 30 22:17:11 2000
@@ -0,0 +1 @@
+/* just so the linker knows what kind of object files it's deadling with... */
diff -urN linux-2.4.16/drivers/net/Makefile lia64-2.4/drivers/net/Makefile
--- linux-2.4.16/drivers/net/Makefile	Wed Oct 24 10:17:52 2001
+++ lia64-2.4/drivers/net/Makefile	Wed Oct 24 10:24:32 2001
@@ -129,6 +129,7 @@
 obj-$(CONFIG_ES3210) += es3210.o 8390.o
 obj-$(CONFIG_LNE390) += lne390.o 8390.o
 obj-$(CONFIG_NE3210) += ne3210.o 8390.o
+obj-$(CONFIG_SIMETH) += simeth.o
 
 obj-$(CONFIG_PPP) += ppp_generic.o slhc.o
 obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
diff -urN linux-2.4.16/drivers/net/eepro100.c lia64-2.4/drivers/net/eepro100.c
--- linux-2.4.16/drivers/net/eepro100.c	Mon Nov 26 11:18:42 2001
+++ lia64-2.4/drivers/net/eepro100.c	Mon Nov 26 11:21:36 2001
@@ -25,6 +25,8 @@
 		Disabled FC and ER, to avoid lockups when when we get FCP interrupts.
 	2000 Jul 17 Goutham Rao <goutham.rao@intel.com>
 		PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary
+    2000 Aug 31 David Mosberger <davidm@hpl.hp.com>
+	    RX_ALIGN support: enables rx DMA without causing unaligned accesses.
 */
 
 static const char *version =
@@ -41,14 +43,18 @@
 static int txdmacount = 128;
 static int rxdmacount /* = 0 */;
 
+#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) || defined(__mips__) || \
+	defined(__arm__)
+  /* align rx buffers to 2 bytes so that IP header is aligned */
+# define RX_ALIGN
+# define RxFD_ALIGNMENT		__attribute__ ((aligned (2), packed))
+#else
+# define RxFD_ALIGNMENT
+#endif
+
 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx method.
    Lower values use more memory, but are faster. */
-#if defined(__alpha__) || defined(__sparc__) || defined(__mips__) || \
-    defined(__arm__)
-static int rx_copybreak = 1518;
-#else
 static int rx_copybreak = 200;
-#endif
 
 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 static int max_interrupt_work = 20;
@@ -385,18 +391,18 @@
 
 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
 struct descriptor {			    /* A generic descriptor. */
-	s32 cmd_status;				/* All command and status fields. */
+	volatile s32 cmd_status;	/* All command and status fields. */
 	u32 link;				    /* struct descriptor *  */
 	unsigned char params[0];
 };
 
 /* The Speedo3 Rx and Tx buffer descriptors. */
 struct RxFD {					/* Receive frame descriptor. */
-	s32 status;
+	volatile s32 status;
 	u32 link;					/* struct RxFD * */
 	u32 rx_buf_addr;			/* void * */
 	u32 count;
-};
+} RxFD_ALIGNMENT;
 
 /* Selected elements of the Tx/RxFD.status word. */
 enum RxFD_bits {
@@ -1185,6 +1191,9 @@
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		struct sk_buff *skb;
 		skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD));
+#ifdef RX_ALIGN
+		skb_reserve(skb, 2);	/* Align IP on 16 byte boundary */
+#endif
 		sp->rx_skbuff[i] = skb;
 		if (skb == NULL)
 			break;			/* OK.  Just initially short of Rx bufs. */
@@ -1617,6 +1626,9 @@
 	struct sk_buff *skb;
 	/* Get a fresh skbuff to replace the consumed one. */
 	skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD));
+#ifdef RX_ALIGN
+	skb_reserve(skb, 2);	/* Align IP on 16 byte boundary */
+#endif
 	sp->rx_skbuff[entry] = skb;
 	if (skb == NULL) {
 		sp->rx_ringp[entry] = NULL;
diff -urN linux-2.4.16/drivers/net/simeth.c lia64-2.4/drivers/net/simeth.c
--- linux-2.4.16/drivers/net/simeth.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/net/simeth.c	Wed Nov  1 23:19:29 2000
@@ -0,0 +1,596 @@
+/*
+ * Simulated Ethernet Driver
+ *
+ * Copyright (C) 1999-2000 Hewlett-Packard Co
+ * Copyright (C) 1999-2000 Stephane Eranain <eranian@hpl.hp.com>
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/in.h>
+#include <linux/malloc.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/if_ether.h>
+#include <linux/if_arp.h>
+#include <linux/skbuff.h>
+#include <linux/notifier.h>
+#include <asm/bitops.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+
+
+#define SIMETH_RECV_MAX	10
+
+/*
+ * Maximum possible received frame for Ethernet.
+ * We preallocate an sk_buff of that size to avoid costly 
+ * memcpy for temporary buffer into sk_buff. We do basically
+ * what's done in other drivers, like eepro with a ring.
+ * The difference is, of course, that we don't have real DMA !!!
+ */
+#define SIMETH_FRAME_SIZE	ETH_FRAME_LEN	
+
+
+#define SSC_NETDEV_PROBE		100
+#define SSC_NETDEV_SEND			101
+#define SSC_NETDEV_RECV			102
+#define SSC_NETDEV_ATTACH		103
+#define SSC_NETDEV_DETACH		104
+
+#define NETWORK_INTR			8
+
+/*
+ * This structure is need for the module version
+ * It hasn't been tested yet
+ */
+struct simeth_local {
+	struct net_device	*next_module;
+	struct net_device_stats stats;
+	int 			simfd;	 /* descriptor in the simulator */
+};
+
+static int simeth_probe1(void);
+static int simeth_open(struct net_device *dev);
+static int simeth_close(struct net_device *dev);
+static int simeth_tx(struct sk_buff *skb, struct net_device *dev);
+static int simeth_rx(struct net_device *dev);
+static struct net_device_stats *simeth_get_stats(struct net_device *dev);
+static void simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static void set_multicast_list(struct net_device *dev);
+static int simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr);
+
+static char *simeth_version="v0.2";
+
+/*
+ * This variable is used to establish a mapping between the Linux/ia64 kernel
+ * and the host linux kernel.
+ *
+ * As of today, we support only one card, even though most of the code
+ * is ready for many more. The mapping is then:
+ *	linux/ia64 -> linux/x86
+ * 	   eth0    -> eth1
+ *
+ * In the future, we some string operations, we could easily support up
+ * to 10 cards (0-9).
+ *
+ * The default mapping can be changed on the kernel command line by
+ * specifying simeth=ethX (or whatever string you want).
+ */
+static char *simeth_device="eth0";	 /* default host interface to use */
+
+
+
+static volatile unsigned int card_count; /* how many cards "found" so far */
+static int simeth_debug=0;		/* set to 1 to get debug information */
+
+/*
+ * Used to catch IFF_UP & IFF_DOWN events
+ */
+static struct notifier_block simeth_dev_notifier = {
+	simeth_device_event,
+	0
+};
+
+
+/*
+ * Function used when using a kernel command line option.
+ *
+ * Format: simeth=interface_name (like eth0)
+ */
+static int __init
+simeth_setup(char *str)
+{
+	simeth_device = str;
+	return 1;
+}
+
+__setup("simeth=", simeth_setup);
+
+/*
+ * Function used to probe for simeth devices when not installed
+ * as a loadable module
+ */
+
+int __init
+simeth_probe (void)
+{
+	return simeth_probe1();
+}
+
+extern long ia64_ssc (long, long, long, long, int);
+extern void ia64_ssc_connect_irq (long intr, long irq);
+
+static inline int
+netdev_probe(char *name, unsigned char *ether)
+{
+	return ia64_ssc(__pa(name), __pa(ether), 0,0, SSC_NETDEV_PROBE);
+}
+
+
+static inline int
+netdev_connect(int irq)
+{
+	/* XXX Fix me
+	 * this does not support multiple cards
+	 * also no return value
+	 */
+	ia64_ssc_connect_irq(NETWORK_INTR, irq);
+	return 0;
+}
+
+static inline int
+netdev_attach(int fd, int irq, unsigned int ipaddr)
+{
+	/* this puts the host interface in the right mode (start interupting) */
+	return ia64_ssc(fd, ipaddr, 0,0, SSC_NETDEV_ATTACH);
+}
+
+
+static inline int
+netdev_detach(int fd)
+{
+	/*
+	 * inactivate the host interface (don't interrupt anymore) */
+	return ia64_ssc(fd, 0,0,0, SSC_NETDEV_DETACH);
+}
+
+static inline int
+netdev_send(int fd, unsigned char *buf, unsigned int len)
+{
+	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_SEND);
+}
+
+static inline int
+netdev_read(int fd, unsigned char *buf, unsigned int len)
+{
+	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_RECV);
+}
+
+/*
+ * Function shared with module code, so cannot be in init section
+ *
+ * So far this function "detects" only one card (test_&_set) but could 
+ * be extended easily.
+ *
+ * Return:
+ * 	- -ENODEV is no device found
+ *	- -ENOMEM is no more memory
+ *	- 0 otherwise
+ */
+static int
+simeth_probe1(void)
+{
+	unsigned char mac_addr[ETH_ALEN];
+	struct simeth_local *local;
+	struct net_device *dev;
+	int fd, i;
+
+	/*
+	 * XXX Fix me 
+	 * let's support just one card for now
+	 */
+	if (test_and_set_bit(0, &card_count))
+		return -ENODEV;
+
+	/*
+	 * check with the simulator for the device
+	 */
+	fd = netdev_probe(simeth_device, mac_addr);
+	if (fd == -1)
+		return -ENODEV;
+
+	dev = init_etherdev(NULL, sizeof(struct simeth_local));
+	if (!dev)
+		return -ENOMEM;
+
+	memcpy(dev->dev_addr, mac_addr, sizeof(mac_addr));
+
+	dev->irq = ia64_alloc_irq();
+
+	/*
+	 * attach the interrupt in the simulator, this does enable interrupts
+	 * until a netdev_attach() is called
+	 */
+	netdev_connect(dev->irq);
+
+	memset(dev->priv, 0, sizeof(struct simeth_local));
+
+	local = dev->priv;
+	local->simfd = fd; /* keep track of underlying file descriptor */
+	local->next_module = NULL;
+
+	dev->open		= simeth_open;
+	dev->stop		= simeth_close;
+	dev->hard_start_xmit	= simeth_tx;
+	dev->get_stats		= simeth_get_stats;
+	dev->set_multicast_list = set_multicast_list; /* no yet used */
+
+	/* Fill in the fields of the device structure with ethernet-generic values. */
+	ether_setup(dev);
+
+	printk("simeth:  %s alpha\n", simeth_version);
+	printk("%s: hosteth=%s simfd=%d, HwAddr", dev->name, simeth_device, local->simfd);
+	for(i = 0; i < ETH_ALEN; i++) {
+		printk(" %2.2x", dev->dev_addr[i]);
+	}
+	printk(", IRQ %d\n", dev->irq);
+
+#ifdef MODULE
+	local->next_module = simeth_dev;
+	simeth_dev  = dev;
+#endif
+	/*
+	 * XXX Fix me
+	 * would not work with more than one device !
+	 */
+	register_netdevice_notifier(&simeth_dev_notifier);
+
+	return 0;
+}
+
+/*
+ * actually binds the device to an interrupt vector
+ */
+static int
+simeth_open(struct net_device *dev)
+{
+	if (request_irq(dev->irq, simeth_interrupt, 0, "simeth", dev)) {
+		printk ("simeth: unable to get IRQ %d.\n", dev->irq);
+		return -EAGAIN;
+	}
+
+	netif_start_queue(dev);
+	MOD_INC_USE_COUNT;
+
+	return 0;
+}
+
+/* copied from lapbether.c */
+static __inline__ int dev_is_ethdev(struct net_device *dev)
+{
+       return ( dev->type == ARPHRD_ETHER && strncmp(dev->name, "dummy", 5));
+}
+
+
+/*
+ * Handler for IFF_UP or IFF_DOWN
+ *
+ * The reason for that is that we don't want to be interrupted when the
+ * interface is down. There is no way to unconnect in the simualtor. Instead
+ * we use this function to shutdown packet processing in the frame filter 
+ * in the simulator. Thus no interrupts are generated
+ *
+ *
+ * That's also the place where we pass the IP address of this device to the
+ * simulator so that that we can start filtering packets for it
+ *
+ * There may be a better way of doing this, but I don't know which yet.
+ */
+static int
+simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr)
+{
+	struct net_device *dev = (struct net_device *)ptr;
+	struct simeth_local *local;
+	struct in_device *in_dev;
+	struct in_ifaddr **ifap = NULL;
+	struct in_ifaddr *ifa = NULL;
+	int r;
+
+
+	if ( ! dev ) {
+		printk(KERN_WARNING "simeth_device_event dev=0\n");
+		return NOTIFY_DONE;
+	}
+
+	if ( event != NETDEV_UP && event != NETDEV_DOWN ) return NOTIFY_DONE;
+
+	/*
+	 * Check whether or not it's for an ethernet device
+	 *
+	 * XXX Fixme: This works only as long as we support one
+	 * type of ethernet device.
+	 */
+	if ( !dev_is_ethdev(dev) ) return NOTIFY_DONE;
+
+	if ((in_dev=dev->ip_ptr) != NULL) {
+		for (ifap=&in_dev->ifa_list; (ifa=*ifap) != NULL; ifap=&ifa->ifa_next)
+			if (strcmp(dev->name, ifa->ifa_label) == 0) break;
+	}
+	if ( ifa == NULL ) {
+		printk("simeth_open: can't find device %s's ifa\n", dev->name);
+		return NOTIFY_DONE;
+	}
+
+	printk("simeth_device_event: %s ipaddr=0x%x\n", dev->name, htonl(ifa->ifa_local));
+
+	/*
+	 * XXX Fix me
+	 * if the device was up, and we're simply reconfiguring it, not sure
+	 * we get DOWN then UP.
+	 */
+
+	local = dev->priv;
+	/* now do it for real */
+	r = event == NETDEV_UP ? 
+		netdev_attach(local->simfd, dev->irq, htonl(ifa->ifa_local)):
+		netdev_detach(local->simfd);
+
+	printk("simeth: netdev_attach/detach: event=%s ->%d\n", event == NETDEV_UP ? "attach":"detach", r);
+
+	return NOTIFY_DONE;
+}
+
+static int
+simeth_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+
+	free_irq(dev->irq, dev);
+
+	MOD_DEC_USE_COUNT;
+
+	return 0;
+}
+
+/*
+ * Only used for debug
+ */
+static void
+frame_print(unsigned char *from, unsigned char *frame, int len)
+{
+	int i;
+
+	printk("%s: (%d) %02x", from, len, frame[0] & 0xff);
+	for(i=1; i < 6; i++ ) {
+		printk(":%02x", frame[i] &0xff);
+	}
+	printk(" %2x", frame[6] &0xff);
+	for(i=7; i < 12; i++ ) {
+		printk(":%02x", frame[i] &0xff);
+	}
+	printk(" [%02x%02x]\n", frame[12], frame[13]);
+
+	for(i=14; i < len; i++ ) {
+		printk("%02x ", frame[i] &0xff);
+		if ( (i%10)==0) printk("\n");
+	}
+	printk("\n");
+}
+
+
+/*
+ * Function used to transmit of frame, very last one on the path before
+ * going to the simulator.
+ */
+static int
+simeth_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	struct simeth_local *local = (struct simeth_local *)dev->priv;
+
+#if 0
+	/* ensure we have at least ETH_ZLEN bytes (min frame size) */
+	unsigned int length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
+	/* Where do the extra padding bytes comes from inthe skbuff ? */
+#else
+	/* the real driver in the host system is going to take care of that
+	 * or maybe it's the NIC itself.
+	 */
+	unsigned int length = skb->len;
+#endif
+
+	local->stats.tx_bytes += skb->len;
+	local->stats.tx_packets++;
+
+
+	if (simeth_debug > 5) frame_print("simeth_tx", skb->data, length);
+
+	netdev_send(local->simfd, skb->data, length);
+
+	/*
+	 * we are synchronous on write, so we don't simulate a
+	 * trasnmit complete interrupt, thus we don't need to arm a tx
+	 */
+
+	dev_kfree_skb(skb);
+	return 0;
+}
+
+static inline struct sk_buff * 
+make_new_skb(struct net_device *dev)
+{
+	struct sk_buff *nskb;
+
+	/*
+	 * The +2 is used to make sure that the IP header is nicely
+	 * aligned (on 4byte boundary I assume 14+2=16)
+	 */
+	nskb = dev_alloc_skb(SIMETH_FRAME_SIZE + 2);
+	if ( nskb == NULL ) {
+		printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
+		return NULL;
+	}
+	nskb->dev = dev;
+
+	skb_reserve(nskb, 2);	/* Align IP on 16 byte boundaries */
+
+	skb_put(nskb,SIMETH_FRAME_SIZE);
+
+	return nskb;
+}
+
+/*
+ * called from interrupt handler to process a received frame
+ */
+static int
+simeth_rx(struct net_device *dev)
+{
+	struct simeth_local	*local;
+	struct sk_buff		*skb;
+	int			len;
+	int			rcv_count = SIMETH_RECV_MAX;
+
+	local = (struct simeth_local *)dev->priv;
+	/*
+	 * the loop concept has been borrowed from other drivers
+	 * looks to me like it's a throttling thing to avoid pushing to many
+	 * packets at one time into the stack. Making sure we can process them
+	 * upstream and make forward progress overall
+	 */
+	do { 
+		if ( (skb=make_new_skb(dev)) == NULL ) {
+			printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
+			local->stats.rx_dropped++;
+			return 0;
+		}
+		/*
+		 * Read only one frame at a time
+		 */
+		len = netdev_read(local->simfd, skb->data, SIMETH_FRAME_SIZE);
+		if ( len == 0 ) {
+			if ( simeth_debug > 0 ) printk(KERN_WARNING "%s: count=%d netdev_read=0\n", dev->name, SIMETH_RECV_MAX-rcv_count);
+			break;
+		}
+#if 0
+		/*
+		 * XXX Fix me
+		 * Should really do a csum+copy here
+		 */
+		memcpy(skb->data, frame, len);
+#endif
+		skb->protocol = eth_type_trans(skb, dev);
+
+		if ( simeth_debug > 6 ) frame_print("simeth_rx", skb->data, len);
+
+		/*
+		 * push the packet up & trigger software interrupt
+		 */
+		netif_rx(skb);
+
+		local->stats.rx_packets++;
+		local->stats.rx_bytes += len;
+
+	} while ( --rcv_count );
+
+	return len; /* 0 = nothing left to read, otherwise, we can try again */
+}
+
+/*
+ * Interrupt handler (Yes, we can do it too !!!)
+ */
+static void
+simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = dev_id;
+
+	if ( dev == NULL ) {
+		printk(KERN_WARNING "simeth: irq %d for unknown device\n", irq);
+		return;
+	}
+
+	/*
+	 * very simple loop because we get interrupts only when receving
+	 */
+	while (simeth_rx(dev));
+}
+
+static struct net_device_stats *
+simeth_get_stats(struct net_device *dev)
+{
+	struct simeth_local  *local = (struct simeth_local *) dev->priv;
+
+	return &local->stats;
+}
+
+/* fake multicast ability */
+static void
+set_multicast_list(struct net_device *dev)
+{
+	printk(KERN_WARNING "%s: set_multicast_list called\n", dev->name);
+}
+
+#ifdef CONFIG_NET_FASTROUTE
+static int
+simeth_accept_fastpath(struct net_device *dev, struct dst_entry *dst)
+{
+	printk(KERN_WARNING "%s: simeth_accept_fastpath called\n", dev->name);
+	return -1;
+}
+#endif
+
+
+#ifdef MODULE
+static int
+simeth_init(void)
+{
+	unsigned int cards_found = 0;
+
+	/* iterate over probe */
+
+	while ( simeth_probe1() == 0 ) cards_found++;
+
+	return cards_found ? 0 : -ENODEV;
+}
+
+
+int
+init_module(void)
+{
+	simeth_dev = NULL;
+
+	/* the register_netdev is done "indirectly by ether_initdev() */
+
+	return simeth_init();
+}
+
+void
+cleanup_module(void)
+{
+	struct net_device *next;
+
+	while ( simeth_dev ) {
+
+		next = ((struct simeth_private *)simeth_dev->priv)->next_module;
+
+		unregister_netdev(simeth_dev);
+
+		kfree(simeth_dev);
+
+		simeth_dev = next;
+	}
+	/*
+	 * XXX fix me
+	 * not clean wihen multiple devices
+	 */
+	unregister_netdevice_notifier(&simeth_dev_notifier);
+}
+#else /* !MODULE */
+__initcall(simeth_probe);
+#endif /* !MODULE */
diff -urN linux-2.4.16/drivers/pci/pci.c lia64-2.4/drivers/pci/pci.c
--- linux-2.4.16/drivers/pci/pci.c	Mon Nov 26 11:18:48 2001
+++ lia64-2.4/drivers/pci/pci.c	Mon Nov 26 11:21:43 2001
@@ -1565,10 +1565,10 @@
 
 	switch (rqst) {
 	case PM_SAVE_STATE:
-		error = pci_pm_save_state((u32)data);
+		error = pci_pm_save_state((unsigned long)data);
 		break;
 	case PM_SUSPEND:
-		error = pci_pm_suspend((u32)data);
+		error = pci_pm_suspend((unsigned long)data);
 		break;
 	case PM_RESUME:
 		error = pci_pm_resume();
@@ -1886,16 +1886,16 @@
 	int			map, block;
 
 	if ((page = pool_find_page (pool, dma)) == 0) {
-		printk (KERN_ERR "pci_pool_free %s/%s, %p/%x (bad dma)\n",
+		printk (KERN_ERR "pci_pool_free %s/%s, %p/%lx (bad dma)\n",
 			pool->dev ? pool->dev->slot_name : NULL,
-			pool->name, vaddr, (int) (dma & 0xffffffff));
+			pool->name, vaddr, (unsigned long) dma);
 		return;
 	}
 #ifdef	CONFIG_PCIPOOL_DEBUG
 	if (((dma - page->dma) + (void *)page->vaddr) != vaddr) {
 		printk (KERN_ERR "pci_pool_free %s/%s, %p (bad vaddr)/%x\n",
 			pool->dev ? pool->dev->slot_name : NULL,
-			pool->name, vaddr, (int) (dma & 0xffffffff));
+			pool->name, vaddr, dma);
 		return;
 	}
 #endif
diff -urN linux-2.4.16/drivers/scsi/Config.in lia64-2.4/drivers/scsi/Config.in
--- linux-2.4.16/drivers/scsi/Config.in	Mon Nov 26 11:18:51 2001
+++ lia64-2.4/drivers/scsi/Config.in	Mon Nov 26 11:21:48 2001
@@ -179,6 +179,7 @@
       bool '   Include loadable firmware in driver' CONFIG_SCSI_QLOGIC_FC_FIRMWARE
    fi
    dep_tristate 'Qlogic QLA 1280 SCSI support' CONFIG_SCSI_QLOGIC_1280 $CONFIG_SCSI
+   dep_tristate 'Qlogic QLA 2100 driver support' CONFIG_SCSI_QLOGIC_QLA2100 $CONFIG_SCSI
 fi
 if [ "$CONFIG_X86" = "y" ]; then
    dep_tristate 'Seagate ST-02 and Future Domain TMC-8xx SCSI support' CONFIG_SCSI_SEAGATE $CONFIG_SCSI
diff -urN linux-2.4.16/drivers/scsi/Makefile lia64-2.4/drivers/scsi/Makefile
--- linux-2.4.16/drivers/scsi/Makefile	Mon Nov 26 11:18:51 2001
+++ lia64-2.4/drivers/scsi/Makefile	Mon Nov 26 11:21:49 2001
@@ -52,6 +52,7 @@
 obj-$(CONFIG_SUN3_SCSI)		+= sun3_scsi.o
 obj-$(CONFIG_MVME16x_SCSI)	+= mvme16x.o	53c7xx.o
 obj-$(CONFIG_BVME6000_SCSI)	+= bvme6000.o	53c7xx.o
+obj-$(CONFIG_SCSI_SIM)		+= simscsi.o
 obj-$(CONFIG_SCSI_SIM710)	+= sim710.o
 obj-$(CONFIG_SCSI_ADVANSYS)	+= advansys.o
 obj-$(CONFIG_SCSI_PCI2000)	+= pci2000.o
@@ -80,6 +81,7 @@
 obj-$(CONFIG_SCSI_QLOGIC_ISP)	+= qlogicisp.o 
 obj-$(CONFIG_SCSI_QLOGIC_FC)	+= qlogicfc.o 
 obj-$(CONFIG_SCSI_QLOGIC_1280)	+= qla1280.o 
+obj-$(CONFIG_SCSI_QLOGIC_QLA2100) += qla2x00.o
 obj-$(CONFIG_SCSI_PAS16)	+= pas16.o
 obj-$(CONFIG_SCSI_SEAGATE)	+= seagate.o
 obj-$(CONFIG_SCSI_FD_8xx)	+= seagate.o
diff -urN linux-2.4.16/drivers/scsi/ql12160_fw.h lia64-2.4/drivers/scsi/ql12160_fw.h
--- linux-2.4.16/drivers/scsi/ql12160_fw.h	Mon Feb  7 19:45:28 2000
+++ lia64-2.4/drivers/scsi/ql12160_fw.h	Mon Oct 30 22:17:11 2000
@@ -1,56 +1,93 @@
 /*
+
  ************************************************************************
+
  *									*
+
  * 	           --- ISP12160 Initiator Firmware ---               	*
+
  *			      32 LUN Support				*
+
  *									*
+
  ************************************************************************
+
  *									*
+
  * Copyright (C) 1999,2000 Qlogic, Corporation
+
  * All rights reserved.
+
  *
+
  * Redistribution and use in source and binary forms are permitted provided
+
  * that the following conditions are met:
+
  * 1. Redistribution of source code must retain the above copyright
+
  *    notice, this list of conditions and the following disclaimer.
- * 2. The name of the author may not be used to endorse or promote products
+
+ * 2. Redistribution in binary form must reproduce the above copyright
+
+ *    notice, this list of conditions and the following disclaimer in the
+
+ *    documentation and/or other materials provided with the distribution.
+
+ * 3. The name of the author may not be used to endorse or promote products
+
  *    derived from this software without specific prior written permission
+
  *
+
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
  *									*
+
  ************************************************************************
+
  */
 
 
+
 /*
- *	Firmware Version 10.01.19 (12:38 Oct 12, 1999)
+ *	Firmware Version 10.04.08 (11:30 May 31, 2000)
  */
 
 #ifdef UNIQUE_FW_NAME
-unsigned short fw12160i_version = 10*1024+1;
+unsigned short fw12160i_version = 10*1024+4;
 #else
-unsigned short risc_code_version = 10*1024+1;
+unsigned short risc_code_version = 10*1024+4;
 #endif
 
 #ifdef UNIQUE_FW_NAME
-unsigned char fw12160i_version_str[] = {10,1,19};
+unsigned char fw12160i_version_str[] = {10,4,8};
 #else
-unsigned char firmware_version[] = {10,1,19};
+unsigned char firmware_version[] = {10,4,8};
 #endif
 
 #ifdef UNIQUE_FW_NAME
-#define fw12160i_VERSION_STRING "10.1.19"
+#define fw12160i_VERSION_STRING "10.04.08"
 #else
-#define FW_VERSION_STRING "10.1.19"
+#define FW_VERSION_STRING "10.04.08"
 #endif
 
 #ifdef UNIQUE_FW_NAME
@@ -64,1326 +101,1383 @@
 #else
 unsigned short risc_code01[] = { 
 #endif
-	0x0804, 0x1041, 0x0000, 0x32f8, 0x0000, 0x2043, 0x4f50, 0x5952,
+	0x0804, 0x1041, 0x0000, 0x34e5, 0x0000, 0x2043, 0x4f50, 0x5952,
 	0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31,
 	0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320,
 	0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350,
 	0x3132, 0x3136, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056,
-	0x6572, 0x7369, 0x6f6e, 0x2031, 0x302e, 0x3031, 0x2020, 0x2043,
+	0x6572, 0x7369, 0x6f6e, 0x2031, 0x302e, 0x3034, 0x2020, 0x2043,
 	0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050,
 	0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020,
-	0x2400, 0x20c9, 0x8cff, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2001,
+	0x2400, 0x20c9, 0x8eff, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2001,
 	0x01ff, 0x2004, 0xd0fc, 0x1120, 0x2071, 0x0100, 0x70a0, 0x70a2,
-	0x20c1, 0x0020, 0x2089, 0x1223, 0x2071, 0x0010, 0x70c3, 0x0004,
+	0x20c1, 0x0020, 0x2089, 0x1221, 0x2071, 0x0010, 0x70c3, 0x0004,
 	0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x000a,
 	0x2001, 0x04fd, 0x2004, 0x70d6, 0x2009, 0xfeff, 0x2130, 0x2128,
-	0xa1a2, 0x4300, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424,
-	0xa192, 0x8d00, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1d83,
-	0x2218, 0x2079, 0x4300, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9,
+	0xa1a2, 0x4500, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424,
+	0xa192, 0x8f00, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1dcf,
+	0x2218, 0x2079, 0x4500, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9,
 	0x0040, 0x42a4, 0x8109, 0x1dd8, 0x2009, 0xff00, 0x3400, 0xa102,
 	0x0218, 0x0110, 0x20a8, 0x42a4, 0x781b, 0x0064, 0x7814, 0xc0cd,
-	0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4340, 0x080c,
-	0x42d8, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4380,
-	0x2071, 0x0100, 0x080c, 0x42d8, 0x7814, 0xc0d4, 0x7816, 0x00de,
+	0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4540, 0x080c,
+	0x44bd, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4580,
+	0x2071, 0x0100, 0x080c, 0x44bd, 0x7814, 0xc0d4, 0x7816, 0x00de,
 	0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802,
 	0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002,
-	0x2009, 0x0002, 0x2069, 0x4340, 0x681b, 0x0003, 0x6823, 0x0007,
-	0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0000,
-	0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000, 0x8109, 0x0500,
-	0x68d3, 0x000a, 0x68c3, 0x43c0, 0x2079, 0x4300, 0x68d7, 0x762d,
-	0x68c7, 0x48c0, 0x68cb, 0x47c0, 0x68cf, 0x88c0, 0x68ab, 0x8b44,
-	0x68af, 0x8b49, 0x68b3, 0x8b44, 0x68b7, 0x8b44, 0x68a7, 0x0001,
-	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x11c8, 0x2069, 0x4380, 0x0860,
-	0x68d3, 0x000a, 0x68c3, 0x45c0, 0x68d7, 0x7839, 0x68c7, 0x68c0,
-	0x68cb, 0x4840, 0x68cf, 0x89d0, 0x68ab, 0x8b49, 0x68af, 0x8b4e,
-	0x68b3, 0x8b49, 0x68b7, 0x8b49, 0x68a7, 0x0001, 0x00e6, 0x2069,
-	0x47c0, 0x2071, 0x0200, 0x70ec, 0xd0e4, 0x2019, 0x1c09, 0x2021,
-	0x0009, 0x1120, 0x2019, 0x1c0c, 0x2021, 0x000c, 0x080c, 0x1cf3,
-	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1188, 0x2069, 0x4840, 0x2071,
-	0x0100, 0x70ec, 0xd0e4, 0x2019, 0x1c09, 0x2021, 0x0009, 0x1120,
-	0x2019, 0x1c0c, 0x2021, 0x000c, 0x080c, 0x1cf3, 0x00ee, 0x2011,
-	0x0002, 0x2069, 0x48c0, 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837,
-	0x0000, 0x680b, 0x0040, 0x7bc8, 0xa386, 0xfeff, 0x1128, 0x6817,
-	0x0100, 0x681f, 0x0064, 0x0020, 0x6817, 0x0064, 0x681f, 0x0002,
-	0xade8, 0x0010, 0x1f04, 0x1137, 0x8109, 0x1d38, 0x2001, 0x01ff,
-	0x2004, 0xd0fc, 0x1128, 0x8211, 0x0118, 0x2069, 0x68c0, 0x08d8,
-	0x080c, 0x2254, 0x080c, 0x3e39, 0x080c, 0x1b0f, 0x080c, 0x42a0,
-	0x2091, 0x2200, 0x2079, 0x4300, 0x2071, 0x0050, 0x2091, 0x2400,
-	0x2079, 0x4300, 0x2071, 0x0020, 0x2091, 0x2600, 0x2079, 0x0200,
-	0x2071, 0x4340, 0x2091, 0x2800, 0x2079, 0x0100, 0x2071, 0x4380,
-	0x2091, 0x2000, 0x2079, 0x4300, 0x2071, 0x0010, 0x3200, 0xa085,
-	0x303d, 0x2090, 0x2071, 0x0010, 0x70c3, 0x0000, 0x1004, 0x118e,
-	0x70c0, 0xa086, 0x0002, 0x1110, 0x080c, 0x13a3, 0x2039, 0x0000,
-	0x080c, 0x129c, 0x78ac, 0xa005, 0x1180, 0x0e04, 0x119c, 0x786c,
-	0xa065, 0x0110, 0x080c, 0x1ffe, 0x080c, 0x1da4, 0x0e04, 0x11b1,
-	0x786c, 0xa065, 0x0110, 0x080c, 0x1ffe, 0x0e04, 0x11b1, 0x2009,
-	0x4347, 0x2011, 0x4387, 0x2104, 0x220c, 0xa105, 0x0110, 0x080c,
-	0x1c21, 0x2071, 0x4340, 0x70a4, 0xa005, 0x01e8, 0x7450, 0xa485,
-	0x0000, 0x01c8, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4, 0xa28c,
-	0x303d, 0x2190, 0x080c, 0x260d, 0x2091, 0x8000, 0x2091, 0x303d,
-	0x0e04, 0x11d3, 0x2079, 0x4300, 0x786c, 0xa065, 0x0120, 0x2071,
-	0x0010, 0x080c, 0x1ffe, 0x1d04, 0x11db, 0x2079, 0x4300, 0x2071,
-	0x0010, 0x080c, 0x40ed, 0x2071, 0x4380, 0x70a4, 0xa005, 0x0188,
-	0x7050, 0xa025, 0x0170, 0x2079, 0x0100, 0x2091, 0x8000, 0x72d4,
-	0xa28c, 0x303d, 0x2190, 0x080c, 0x260d, 0x2091, 0x8000, 0x2091,
-	0x303d, 0x2079, 0x4300, 0x2071, 0x0010, 0x0e04, 0x11fc, 0x786c,
-	0xa065, 0x0110, 0x080c, 0x1ffe, 0x1d04, 0x1190, 0x080c, 0x40ed,
-	0x0804, 0x1190, 0x3c00, 0xa084, 0x0007, 0x0002, 0x120e, 0x120e,
-	0x1210, 0x1210, 0x1215, 0x1215, 0x121a, 0x121a, 0x080c, 0x243b,
-	0x2091, 0x2400, 0x080c, 0x3e9c, 0x0005, 0x2091, 0x2200, 0x080c,
-	0x3e9c, 0x0005, 0x2091, 0x2200, 0x080c, 0x3e9c, 0x2091, 0x2400,
-	0x080c, 0x3e9c, 0x0005, 0x1243, 0x1243, 0x1244, 0x1244, 0x124f,
-	0x124f, 0x124f, 0x124f, 0x1258, 0x1258, 0x1263, 0x1263, 0x124f,
-	0x124f, 0x124f, 0x124f, 0x1272, 0x1272, 0x1272, 0x1272, 0x1272,
-	0x1272, 0x1272, 0x1272, 0x1272, 0x1272, 0x1272, 0x1272, 0x1272,
-	0x1272, 0x1272, 0x1272, 0x0cf8, 0x0006, 0x0106, 0x0126, 0x2091,
-	0x2800, 0x080c, 0x2458, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006,
-	0x0106, 0x0126, 0x080c, 0x1202, 0x012e, 0x010e, 0x000e, 0x000d,
-	0x0006, 0x0106, 0x0126, 0x2091, 0x2600, 0x080c, 0x2458, 0x012e,
-	0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126, 0x2091, 0x2600,
-	0x080c, 0x2458, 0x2091, 0x2800, 0x080c, 0x2458, 0x012e, 0x010e,
-	0x000e, 0x000d, 0x0006, 0x0106, 0x0126, 0x00e6, 0x00f6, 0x2079,
-	0x4300, 0x2071, 0x0200, 0x2069, 0x4340, 0x3d00, 0xd08c, 0x1120,
-	0x2069, 0x4380, 0x2071, 0x0100, 0x080c, 0x42d8, 0x00fe, 0x00ee,
-	0x012e, 0x010e, 0x000e, 0x000d, 0x7008, 0x800b, 0x1240, 0x7007,
-	0x0002, 0xa08c, 0x01e0, 0x1120, 0xd09c, 0x0108, 0x0887, 0x0897,
-	0x70c3, 0x4002, 0x0804, 0x13a6, 0x0e04, 0x1308, 0x2061, 0x0000,
-	0x6018, 0xd084, 0x1904, 0x1308, 0x7828, 0xa005, 0x1120, 0x0004,
-	0x1309, 0x0804, 0x1308, 0xd0fc, 0x0148, 0x0006, 0x080c, 0x1aa9,
-	0x000e, 0x0168, 0x2001, 0x4007, 0x0804, 0x13a5, 0x0006, 0x080c,
-	0x1a9b, 0x000e, 0x0120, 0x2001, 0x4007, 0x0804, 0x13a5, 0x7910,
-	0xd0fc, 0x1128, 0x2061, 0x4340, 0xc19c, 0xc7fc, 0x0020, 0x2061,
-	0x4380, 0xc19d, 0xc7fd, 0x6064, 0xa005, 0x15d0, 0x7912, 0x6083,
-	0x0000, 0x7828, 0xc0fc, 0xa086, 0x0018, 0x1120, 0x00c6, 0x080c,
-	0x18c9, 0x00ce, 0x782b, 0x0000, 0x607c, 0xa065, 0x0190, 0x00c6,
-	0x609c, 0x080c, 0x1b76, 0x00ce, 0x609f, 0x0000, 0x080c, 0x19db,
-	0x2009, 0x0018, 0x6087, 0x0103, 0x080c, 0x1ab7, 0x1198, 0x080c,
-	0x1b02, 0x7810, 0xd09c, 0x1118, 0x2061, 0x4340, 0x0020, 0x2061,
-	0x4380, 0xc09c, 0x7812, 0x607f, 0x0000, 0x60d4, 0xd0c4, 0x0130,
-	0xc0c4, 0x60d6, 0x2001, 0x4005, 0x0804, 0x13a5, 0x0804, 0x13a3,
-	0x0005, 0xa006, 0x70c2, 0x70c6, 0x70ca, 0x70ce, 0x70da, 0x70c0,
-	0xa08a, 0x0040, 0x1a04, 0x1355, 0x0002, 0x13a3, 0x13f1, 0x13bf,
-	0x1425, 0x1459, 0x1459, 0x13b7, 0x19f3, 0x1463, 0x13b1, 0x13c3,
-	0x13c4, 0x13c5, 0x13c6, 0x19f7, 0x13b1, 0x1470, 0x14c5, 0x18e4,
-	0x19ed, 0x13c7, 0x1795, 0x17cb, 0x17fa, 0x183d, 0x1752, 0x175f,
-	0x1772, 0x1784, 0x159a, 0x13b1, 0x14f7, 0x1502, 0x1510, 0x151e,
-	0x1535, 0x1543, 0x1546, 0x1554, 0x1562, 0x156c, 0x1580, 0x158c,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x15a7, 0x15b8, 0x15d2, 0x1606,
-	0x162f, 0x1641, 0x1644, 0x1677, 0x16aa, 0x16bc, 0x1720, 0x1730,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x1742, 0x2100, 0xa08a, 0x0040,
-	0x1a04, 0x13b1, 0x0002, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1,
-	0x1a19, 0x1a1f, 0x13b1, 0x13b1, 0x13b1, 0x1a23, 0x1a63, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x13ec, 0x1454, 0x146b, 0x14c0, 0x18df,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x1a67, 0x1a0b, 0x1a15, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1, 0x13b1,
-	0x13b1, 0x13b1, 0x13b1, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0028,
-	0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0e04, 0x13a6,
+	0x2009, 0x0002, 0x2069, 0x4540, 0x681b, 0x0003, 0x6823, 0x0007,
+	0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0006,
+	0x6833, 0x0008, 0x683b, 0x0000, 0x8109, 0x0500, 0x68cf, 0x000a,
+	0x68bf, 0x45c0, 0x2079, 0x4500, 0x68d3, 0x762d, 0x68c3, 0x4ac0,
+	0x68c7, 0x49c0, 0x68cb, 0x8ac0, 0x68a7, 0x8d44, 0x68ab, 0x8d49,
+	0x68af, 0x8d44, 0x68b3, 0x8d44, 0x68a3, 0x0001, 0x2001, 0x01ff,
+	0x2004, 0xd0fc, 0x11c8, 0x2069, 0x4580, 0x0870, 0x68cf, 0x000a,
+	0x68bf, 0x47c0, 0x68d3, 0x7839, 0x68c3, 0x6ac0, 0x68c7, 0x4a40,
+	0x68cb, 0x8bd0, 0x68a7, 0x8d49, 0x68ab, 0x8d4e, 0x68af, 0x8d49,
+	0x68b3, 0x8d49, 0x68a3, 0x0001, 0x00e6, 0x2069, 0x49c0, 0x2071,
+	0x0200, 0x70ec, 0xd0e4, 0x2019, 0x1c09, 0x2021, 0x0009, 0x1120,
+	0x2019, 0x1c0c, 0x2021, 0x000c, 0x080c, 0x1d3f, 0x2001, 0x01ff,
+	0x2004, 0xd0fc, 0x1188, 0x2069, 0x4a40, 0x2071, 0x0100, 0x70ec,
+	0xd0e4, 0x2019, 0x1c09, 0x2021, 0x0009, 0x1120, 0x2019, 0x1c0c,
+	0x2021, 0x000c, 0x080c, 0x1d3f, 0x00ee, 0x2011, 0x0002, 0x2069,
+	0x4ac0, 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b,
+	0x0040, 0x7bc8, 0xa386, 0xfeff, 0x1128, 0x6817, 0x0100, 0x681f,
+	0x0064, 0x0020, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010,
+	0x1f04, 0x1135, 0x8109, 0x1d38, 0x2001, 0x01ff, 0x2004, 0xd0fc,
+	0x1128, 0x8211, 0x0118, 0x2069, 0x6ac0, 0x08d8, 0x080c, 0x22b7,
+	0x080c, 0x3fba, 0x080c, 0x1b51, 0x080c, 0x4489, 0x2091, 0x2200,
+	0x2079, 0x4500, 0x2071, 0x0050, 0x2091, 0x2400, 0x2079, 0x4500,
+	0x2071, 0x0020, 0x2091, 0x2600, 0x2079, 0x0200, 0x2071, 0x4540,
+	0x2091, 0x2800, 0x2079, 0x0100, 0x2071, 0x4580, 0x2091, 0x2000,
+	0x2079, 0x4500, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090,
+	0x2071, 0x0010, 0x70c3, 0x0000, 0x1004, 0x118c, 0x70c0, 0xa086,
+	0x0002, 0x1110, 0x080c, 0x13b3, 0x2039, 0x0000, 0x080c, 0x12ab,
+	0x78ac, 0xa005, 0x1180, 0x0e04, 0x119a, 0x786c, 0xa065, 0x0110,
+	0x080c, 0x2061, 0x080c, 0x1df0, 0x0e04, 0x11af, 0x786c, 0xa065,
+	0x0110, 0x080c, 0x2061, 0x0e04, 0x11af, 0x2009, 0x4547, 0x2011,
+	0x4587, 0x2104, 0x220c, 0xa105, 0x0110, 0x080c, 0x1c63, 0x2071,
+	0x4540, 0x70a0, 0xa005, 0x01e8, 0x744c, 0xa485, 0x0000, 0x01c8,
+	0x2079, 0x0200, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d, 0x2190,
+	0x080c, 0x26ff, 0x2091, 0x8000, 0x2091, 0x303d, 0x0e04, 0x11d1,
+	0x2079, 0x4500, 0x786c, 0xa065, 0x0120, 0x2071, 0x0010, 0x080c,
+	0x2061, 0x1d04, 0x11d9, 0x2079, 0x4500, 0x2071, 0x0010, 0x080c,
+	0x42c7, 0x2071, 0x4580, 0x70a0, 0xa005, 0x0188, 0x704c, 0xa025,
+	0x0170, 0x2079, 0x0100, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d,
+	0x2190, 0x080c, 0x26ff, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079,
+	0x4500, 0x2071, 0x0010, 0x0e04, 0x11fa, 0x786c, 0xa065, 0x0110,
+	0x080c, 0x2061, 0x1d04, 0x118e, 0x080c, 0x42c7, 0x0804, 0x118e,
+	0x3c00, 0xa084, 0x0007, 0x0002, 0x120c, 0x120c, 0x120e, 0x120e,
+	0x1213, 0x1213, 0x1218, 0x1218, 0x080c, 0x252b, 0x2091, 0x2400,
+	0x080c, 0x4052, 0x0005, 0x2091, 0x2200, 0x080c, 0x4052, 0x0005,
+	0x2091, 0x2200, 0x080c, 0x4052, 0x2091, 0x2400, 0x080c, 0x4052,
+	0x0005, 0x1241, 0x1241, 0x1242, 0x1242, 0x124d, 0x124d, 0x124d,
+	0x124d, 0x1256, 0x1256, 0x1261, 0x1261, 0x124d, 0x124d, 0x124d,
+	0x124d, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270,
+	0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270,
+	0x1270, 0x0cf8, 0x0006, 0x0106, 0x0126, 0x2091, 0x2800, 0x080c,
+	0x2548, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126,
+	0x080c, 0x1200, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106,
+	0x0126, 0x2091, 0x2600, 0x080c, 0x2548, 0x012e, 0x010e, 0x000e,
+	0x000d, 0x0006, 0x0106, 0x0126, 0x2091, 0x2600, 0x080c, 0x2548,
+	0x2091, 0x2800, 0x080c, 0x2548, 0x012e, 0x010e, 0x000e, 0x000d,
+	0x0006, 0x0106, 0x0126, 0x00d6, 0x00e6, 0x00f6, 0x2079, 0x4500,
+	0x2071, 0x0200, 0x2069, 0x4540, 0x3d00, 0xd08c, 0x0130, 0x70ec,
+	0xa084, 0x1c00, 0x78e2, 0x080c, 0x44bd, 0x3d00, 0xd084, 0x0150,
+	0x2069, 0x4580, 0x2071, 0x0100, 0x70ec, 0xa084, 0x1c00, 0x78e6,
+	0x080c, 0x44bd, 0x080c, 0x24dc, 0x00fe, 0x00ee, 0x00de, 0x012e,
+	0x010e, 0x000e, 0x000d, 0x7008, 0x800b, 0x1240, 0x7007, 0x0002,
+	0xa08c, 0x01e0, 0x1120, 0xd09c, 0x0108, 0x0887, 0x0897, 0x70c3,
+	0x4002, 0x0804, 0x13b6, 0x0e04, 0x1317, 0x2061, 0x0000, 0x6018,
+	0xd084, 0x1904, 0x1317, 0x7828, 0xa005, 0x1120, 0x0004, 0x1318,
+	0x0804, 0x1317, 0xd0fc, 0x0148, 0x0006, 0x080c, 0x1aeb, 0x000e,
+	0x0168, 0x2001, 0x4007, 0x0804, 0x13b5, 0x0006, 0x080c, 0x1add,
+	0x000e, 0x0120, 0x2001, 0x4007, 0x0804, 0x13b5, 0x7910, 0xd0fc,
+	0x1128, 0x2061, 0x4540, 0xc19c, 0xc7fc, 0x0020, 0x2061, 0x4580,
+	0xc19d, 0xc7fd, 0x6060, 0xa005, 0x15d0, 0x7912, 0x607f, 0x0000,
+	0x7828, 0xc0fc, 0xa086, 0x0018, 0x1120, 0x00c6, 0x080c, 0x190a,
+	0x00ce, 0x782b, 0x0000, 0x6078, 0xa065, 0x0190, 0x00c6, 0x609c,
+	0x080c, 0x1bb8, 0x00ce, 0x609f, 0x0000, 0x080c, 0x1a1b, 0x2009,
+	0x0018, 0x6087, 0x0103, 0x080c, 0x1af9, 0x1198, 0x080c, 0x1b44,
+	0x7810, 0xd09c, 0x1118, 0x2061, 0x4540, 0x0020, 0x2061, 0x4580,
+	0xc09c, 0x7812, 0x607b, 0x0000, 0x60d0, 0xd0c4, 0x0130, 0xc0c4,
+	0x60d2, 0x2001, 0x4005, 0x0804, 0x13b5, 0x0804, 0x13b3, 0x0005,
+	0xa006, 0x70c2, 0x70c6, 0x70ca, 0x70ce, 0x70da, 0x70c0, 0xa03d,
+	0xa08a, 0x0040, 0x1a04, 0x1365, 0x0002, 0x13b3, 0x1401, 0x13cf,
+	0x1435, 0x1469, 0x1469, 0x13c7, 0x1a33, 0x1473, 0x13c1, 0x13d3,
+	0x13d4, 0x13d5, 0x13d6, 0x1a37, 0x13c1, 0x1480, 0x14d5, 0x1925,
+	0x1a2d, 0x13d7, 0x17b4, 0x17ea, 0x1819, 0x185c, 0x1771, 0x177e,
+	0x1791, 0x17a3, 0x15aa, 0x13c1, 0x1507, 0x1512, 0x1520, 0x152e,
+	0x1545, 0x1553, 0x1556, 0x1564, 0x1572, 0x157c, 0x1590, 0x159c,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x15b7, 0x15c8, 0x15e2, 0x1616,
+	0x163f, 0x1651, 0x1654, 0x167f, 0x16b8, 0x16ca, 0x173f, 0x174f,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x1761, 0x2100, 0xa08a, 0x0040,
+	0x1a04, 0x13c1, 0x0002, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1,
+	0x1a59, 0x1a5f, 0x13c1, 0x13c1, 0x13c1, 0x1a63, 0x1aa3, 0x13c1,
+	0x13c1, 0x13c1, 0x13c1, 0x13fc, 0x1464, 0x147b, 0x14d0, 0x1920,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x1aa7, 0x1a4b, 0x1a55, 0x18ef,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1,
+	0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1, 0x13c1,
+	0x13c1, 0x13c1, 0x13c1, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0028,
+	0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0e04, 0x13b6,
 	0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080,
 	0x0005, 0x70c3, 0x4001, 0x0c90, 0x70c3, 0x4006, 0x0c78, 0x2099,
 	0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, 0x53a3, 0x0c20, 0x70c4,
 	0x70c3, 0x0004, 0x0807, 0x08f8, 0x08f0, 0x08e8, 0x08e0, 0x2091,
 	0x8000, 0x70c3, 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf,
-	0x2020, 0x70d3, 0x000a, 0x2001, 0x0001, 0x70d6, 0x2079, 0x0000,
+	0x2020, 0x70d3, 0x000a, 0x2001, 0x0004, 0x70d6, 0x2079, 0x0000,
 	0x781b, 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x041a,
 	0x2051, 0x0445, 0x2061, 0x0447, 0x20c1, 0x0020, 0x2091, 0x5000,
 	0x2091, 0x4080, 0x0804, 0x0418, 0x75d8, 0x74dc, 0x75da, 0x74de,
 	0x0018, 0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8, 0x73cc, 0x70c4,
 	0x20a0, 0x2099, 0x0030, 0x7003, 0x0001, 0x7007, 0x0006, 0x731a,
-	0x721e, 0x7422, 0x7526, 0x2021, 0x0040, 0x81ff, 0x0904, 0x13a3,
+	0x721e, 0x7422, 0x7526, 0x2021, 0x0040, 0x81ff, 0x0904, 0x13b3,
 	0xa182, 0x0040, 0x1210, 0x2120, 0xa006, 0x2008, 0x8403, 0x7012,
 	0x7007, 0x0004, 0x7007, 0x0001, 0x7008, 0xd0fc, 0x0de8, 0x7007,
-	0x0002, 0xa084, 0x01e0, 0x0120, 0x70c3, 0x4002, 0x0804, 0x13a6,
-	0x24a8, 0x53a5, 0x0c10, 0x0804, 0x13a3, 0x2029, 0x0000, 0x2520,
+	0x0002, 0xa084, 0x01e0, 0x0120, 0x70c3, 0x4002, 0x0804, 0x13b6,
+	0x24a8, 0x53a5, 0x0c10, 0x0804, 0x13b3, 0x2029, 0x0000, 0x2520,
 	0x71d0, 0x72c8, 0x73cc, 0x70c4, 0x2098, 0x20a1, 0x0030, 0x7003,
 	0x0000, 0x7007, 0x0006, 0x731a, 0x721e, 0x7422, 0x7526, 0x2021,
-	0x0040, 0x7007, 0x0006, 0x81ff, 0x0904, 0x13a3, 0xa182, 0x0040,
+	0x0040, 0x7007, 0x0006, 0x81ff, 0x0904, 0x13b3, 0xa182, 0x0040,
 	0x1210, 0x2120, 0xa006, 0x2008, 0x8403, 0x7012, 0x24a8, 0x53a6,
 	0x7007, 0x0001, 0x7008, 0xd0fc, 0x0de8, 0xa084, 0x01e0, 0x0d48,
-	0x70c3, 0x4002, 0x0804, 0x13a6, 0x75d8, 0x74dc, 0x75da, 0x74de,
+	0x70c3, 0x4002, 0x0804, 0x13b6, 0x75d8, 0x74dc, 0x75da, 0x74de,
 	0x0878, 0x71c4, 0x70c8, 0x2114, 0xa79e, 0x0004, 0x1108, 0x200a,
-	0x72ca, 0x0804, 0x13a2, 0x70c7, 0x000a, 0x70cb, 0x0001, 0x70cf,
-	0x0013, 0x0804, 0x13a3, 0x75d8, 0x76dc, 0x75da, 0x76de, 0x0018,
+	0x72ca, 0x0804, 0x13b2, 0x70c7, 0x000a, 0x70cb, 0x0004, 0x70cf,
+	0x0008, 0x0804, 0x13b3, 0x75d8, 0x76dc, 0x75da, 0x76de, 0x0018,
 	0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d0, 0x70c6,
 	0x72ca, 0x73ce, 0x74d2, 0xa005, 0x05f0, 0xa40a, 0x0110, 0x1a04,
-	0x13a5, 0x8001, 0x7872, 0xa084, 0xfc00, 0x0138, 0x78ac, 0xc085,
-	0x78ae, 0x2001, 0x4005, 0x0804, 0x13a5, 0x7b7e, 0x7a7a, 0x7e86,
+	0x13b5, 0x8001, 0x7872, 0xa084, 0xfc00, 0x0138, 0x78ac, 0xc085,
+	0x78ae, 0x2001, 0x4005, 0x0804, 0x13b5, 0x7b7e, 0x7a7a, 0x7e86,
 	0x7d82, 0x7c76, 0xa48c, 0xff00, 0x0170, 0x8407, 0x8004, 0x8004,
 	0x810c, 0x810c, 0x810f, 0xa118, 0xa291, 0x0000, 0xa6b1, 0x0000,
 	0xa581, 0x0000, 0x0050, 0x8407, 0x8004, 0x8004, 0xa318, 0xa291,
 	0x0000, 0xa6b1, 0x0000, 0xa581, 0x0000, 0x731a, 0x721e, 0x7622,
 	0x7026, 0xa605, 0x0118, 0x7a10, 0xc2c5, 0x7a12, 0x78ac, 0xa084,
-	0xfffc, 0x78ae, 0x0018, 0x78ac, 0xc085, 0x78ae, 0x0804, 0x13a3,
+	0xfffc, 0x78ae, 0x0018, 0x78ac, 0xc085, 0x78ae, 0x0804, 0x13b3,
 	0x75d8, 0x76dc, 0x75da, 0x76de, 0x0018, 0x2029, 0x0000, 0x2530,
 	0x70c4, 0x72c8, 0x73cc, 0x74d4, 0x70c6, 0x72ca, 0x73ce, 0x74d6,
-	0xa005, 0x0500, 0xa40a, 0x0110, 0x1a04, 0x13a5, 0x8001, 0x7892,
+	0xa005, 0x0500, 0xa40a, 0x0110, 0x1a04, 0x13b5, 0x8001, 0x7892,
 	0xa084, 0xfc00, 0x0138, 0x78ac, 0xc0c5, 0x78ae, 0x2001, 0x4005,
-	0x0804, 0x13a5, 0x7a9a, 0x7b9e, 0x7da2, 0x7ea6, 0x2600, 0xa505,
+	0x0804, 0x13b5, 0x7a9a, 0x7b9e, 0x7da2, 0x7ea6, 0x2600, 0xa505,
 	0x0118, 0x7a10, 0xc2c5, 0x7a12, 0x7c96, 0x78ac, 0xa084, 0xfcff,
-	0x78ae, 0x0018, 0x78ac, 0xc0c5, 0x78ae, 0x0804, 0x13a3, 0x2009,
+	0x78ae, 0x0018, 0x78ac, 0xc0c5, 0x78ae, 0x0804, 0x13b3, 0x2009,
 	0x0000, 0x786c, 0xa065, 0x0118, 0x8108, 0x6000, 0x0cd8, 0x7ac4,
-	0x0804, 0x13a1, 0x2009, 0x4348, 0x210c, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x1904, 0x13a2, 0x2011, 0x4388, 0x2214, 0x0804, 0x13a1,
-	0x2009, 0x4349, 0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
-	0x13a2, 0x2011, 0x4389, 0x2214, 0x0804, 0x13a1, 0x2061, 0x4340,
+	0x0804, 0x13b1, 0x2009, 0x4548, 0x210c, 0x2001, 0x01ff, 0x2004,
+	0xd0fc, 0x1904, 0x13b2, 0x2011, 0x4588, 0x2214, 0x0804, 0x13b1,
+	0x2009, 0x4549, 0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
+	0x13b2, 0x2011, 0x4589, 0x2214, 0x0804, 0x13b1, 0x2061, 0x4540,
 	0x6128, 0x622c, 0x8214, 0x8214, 0x8214, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x1148, 0x2061, 0x4380, 0x6328, 0x73da, 0x632c, 0x831c,
-	0x831c, 0x831c, 0x73de, 0x0804, 0x13a1, 0x2009, 0x434c, 0x210c,
-	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13a2, 0x2011, 0x438c,
-	0x2214, 0x0804, 0x13a1, 0x7918, 0x0804, 0x13a2, 0x2009, 0x434d,
-	0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13a2, 0x2011,
-	0x438d, 0x2214, 0x0804, 0x13a1, 0x2009, 0x434e, 0x210c, 0x2001,
-	0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13a2, 0x2011, 0x438e, 0x2214,
-	0x0804, 0x13a1, 0x7920, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
-	0x13a2, 0x7a24, 0x0804, 0x13a1, 0x2011, 0x4840, 0x71c4, 0xd1fc,
-	0x1110, 0x2011, 0x47c0, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003,
-	0x8003, 0xa268, 0x6a00, 0x6b08, 0x6c1c, 0x74da, 0x0804, 0x13a0,
-	0x77c4, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6b1c, 0x6a14, 0x2091,
-	0x8001, 0x2708, 0x0804, 0x13a0, 0x2061, 0x4340, 0x6118, 0x2001,
-	0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13a2, 0x2061, 0x4380, 0x6218,
-	0x0804, 0x13a1, 0x77c4, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6908,
-	0x6a18, 0x6b10, 0x77da, 0x2091, 0x8001, 0x0804, 0x13a0, 0x71c4,
-	0x2110, 0xa294, 0x000f, 0xa282, 0x0010, 0x1a04, 0x139c, 0x080c,
-	0x230e, 0xa384, 0x4000, 0x0110, 0xa295, 0x0020, 0x0804, 0x13a0,
-	0x71c4, 0x2100, 0xc0bc, 0xa082, 0x0010, 0x1a04, 0x139c, 0xd1bc,
-	0x1120, 0x2011, 0x4348, 0x2204, 0x0020, 0x2011, 0x4388, 0x2204,
-	0xc0bd, 0x0006, 0x2100, 0xc0bc, 0x2012, 0x080c, 0x22b4, 0x001e,
-	0x0804, 0x13a2, 0x71c4, 0x2021, 0x4349, 0x2404, 0x70c6, 0x2019,
-	0x0000, 0x0030, 0x71c8, 0x2021, 0x4389, 0x2404, 0x70ca, 0xc3fd,
-	0x2011, 0x15fe, 0x20a9, 0x0008, 0x2204, 0xa106, 0x0138, 0x8210,
-	0x1f04, 0x15e4, 0x71c4, 0x72c8, 0x0804, 0x139b, 0xa292, 0x15fe,
-	0x0026, 0x2122, 0x001e, 0x080c, 0x22c6, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x1110, 0xd3fc, 0x09f0, 0x0804, 0x13a3, 0x03e8, 0x00fa,
-	0x01f4, 0x02ee, 0x0064, 0x0019, 0x0032, 0x004b, 0x2061, 0x4340,
+	0xd0fc, 0x1148, 0x2061, 0x4580, 0x6328, 0x73da, 0x632c, 0x831c,
+	0x831c, 0x831c, 0x73de, 0x0804, 0x13b1, 0x2009, 0x454c, 0x210c,
+	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13b2, 0x2011, 0x458c,
+	0x2214, 0x0804, 0x13b1, 0x7918, 0x0804, 0x13b2, 0x2009, 0x0202,
+	0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13b2, 0x2011,
+	0x0102, 0x2214, 0x0804, 0x13b1, 0x2009, 0x454d, 0x210c, 0x2001,
+	0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13b2, 0x2011, 0x458d, 0x2214,
+	0x0804, 0x13b1, 0x7920, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
+	0x13b2, 0x7a24, 0x0804, 0x13b1, 0x2011, 0x4a40, 0x71c4, 0xd1fc,
+	0x1110, 0x2011, 0x49c0, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003,
+	0x8003, 0xa268, 0x6a00, 0x6b08, 0x6c1c, 0x74da, 0x0804, 0x13b0,
+	0x77c4, 0x080c, 0x1b5f, 0x2091, 0x8000, 0x6b1c, 0x6a14, 0x2091,
+	0x8001, 0x2708, 0x0804, 0x13b0, 0x2061, 0x4540, 0x6118, 0x2001,
+	0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13b2, 0x2061, 0x4580, 0x6218,
+	0x0804, 0x13b1, 0x77c4, 0x080c, 0x1b5f, 0x2091, 0x8000, 0x6908,
+	0x6a18, 0x6b10, 0x77da, 0x2091, 0x8001, 0x0804, 0x13b0, 0x71c4,
+	0x2110, 0xa294, 0x000f, 0xa282, 0x0010, 0x1a04, 0x13ac, 0x080c,
+	0x2373, 0xa384, 0x4000, 0x0110, 0xa295, 0x0020, 0x0804, 0x13b0,
+	0x71c4, 0x2100, 0xc0bc, 0xa082, 0x0010, 0x1a04, 0x13ac, 0xd1bc,
+	0x1120, 0x2011, 0x4548, 0x2204, 0x0020, 0x2011, 0x4588, 0x2204,
+	0xc0bd, 0x0006, 0x2100, 0xc0bc, 0x2012, 0x080c, 0x2319, 0x001e,
+	0x0804, 0x13b2, 0x71c4, 0x2021, 0x4549, 0x2404, 0x70c6, 0x2019,
+	0x0000, 0x0030, 0x71c8, 0x2021, 0x4589, 0x2404, 0x70ca, 0xc3fd,
+	0x2011, 0x160e, 0x20a9, 0x0008, 0x2204, 0xa106, 0x0138, 0x8210,
+	0x1f04, 0x15f4, 0x71c4, 0x72c8, 0x0804, 0x13ab, 0xa292, 0x160e,
+	0x0026, 0x2122, 0x001e, 0x080c, 0x232b, 0x2001, 0x01ff, 0x2004,
+	0xd0fc, 0x1110, 0xd3fc, 0x09f0, 0x0804, 0x13b3, 0x03e8, 0x00fa,
+	0x01f4, 0x02ee, 0x0064, 0x0019, 0x0032, 0x004b, 0x2061, 0x4540,
 	0x6128, 0x622c, 0x8214, 0x8214, 0x8214, 0x70c4, 0x602a, 0x70c8,
 	0x8003, 0x8003, 0x8003, 0x602e, 0x2001, 0x01ff, 0x2004, 0xd0fc,
-	0x11a0, 0x0026, 0x0016, 0x2061, 0x4380, 0x6128, 0x622c, 0x8214,
+	0x11a0, 0x0026, 0x0016, 0x2061, 0x4580, 0x6128, 0x622c, 0x8214,
 	0x8214, 0x8214, 0x70d8, 0x602a, 0x70dc, 0x8003, 0x8003, 0x8003,
-	0x602e, 0x71da, 0x72de, 0x001e, 0x002e, 0x0804, 0x13a1, 0x2061,
-	0x4340, 0x6130, 0x70c4, 0x6032, 0x2001, 0x01ff, 0x2004, 0xd0fc,
-	0x1904, 0x13a2, 0x2061, 0x4380, 0x6230, 0x70c8, 0x6032, 0x0804,
-	0x13a1, 0x7918, 0x0804, 0x13a2, 0x71c4, 0xa184, 0xffcf, 0x0148,
-	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x139c, 0x72c8, 0x0804,
-	0x139b, 0x2011, 0x434d, 0x2204, 0x2112, 0x0006, 0x2019, 0x0000,
-	0x080c, 0x2302, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x0118, 0x001e,
-	0x0804, 0x13a2, 0x71c8, 0xa184, 0xffcf, 0x0128, 0x0006, 0x2110,
-	0x71c4, 0x0804, 0x139b, 0x2011, 0x438d, 0x2204, 0x2112, 0x0006,
-	0xc3fd, 0x080c, 0x2302, 0x002e, 0x001e, 0x0804, 0x13a1, 0x71c4,
+	0x602e, 0x71da, 0x72de, 0x001e, 0x002e, 0x0804, 0x13b1, 0x2061,
+	0x4540, 0x6130, 0x70c4, 0x6032, 0x2001, 0x01ff, 0x2004, 0xd0fc,
+	0x1904, 0x13b2, 0x2061, 0x4580, 0x6230, 0x70c8, 0x6032, 0x0804,
+	0x13b1, 0x7918, 0x0804, 0x13b2, 0x71c4, 0xa184, 0xf0cf, 0x0148,
+	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x13ac, 0x72c8, 0x0804,
+	0x13ab, 0x0006, 0x2019, 0x0000, 0x080c, 0x2367, 0x2001, 0x01ff,
+	0x2004, 0xd0fc, 0x0118, 0x001e, 0x0804, 0x13b2, 0x71c8, 0xa184,
+	0xf0cf, 0x0128, 0x0006, 0x2110, 0x71c4, 0x0804, 0x13ab, 0x0006,
+	0xc3fd, 0x080c, 0x2367, 0x002e, 0x001e, 0x0804, 0x13b1, 0x71c4,
 	0xa182, 0x0010, 0x0248, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
-	0x139c, 0x72c8, 0x0804, 0x139b, 0x2011, 0x434e, 0x2204, 0x0006,
-	0x2112, 0x2019, 0x0000, 0x080c, 0x22ef, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x0118, 0x001e, 0x0804, 0x13a2, 0x71c8, 0xa182, 0x0010,
-	0x0228, 0x0006, 0x2110, 0x71c4, 0x0804, 0x139b, 0x2011, 0x438e,
-	0x2204, 0x0006, 0x2112, 0xc3fd, 0x080c, 0x22ef, 0x002e, 0x001e,
-	0x0804, 0x13a1, 0x71c4, 0x72c8, 0xa184, 0xfffd, 0x1904, 0x139b,
-	0xa284, 0xfffd, 0x1904, 0x139b, 0x2100, 0x7920, 0x7822, 0x2200,
-	0x7a24, 0x7826, 0x0804, 0x13a1, 0x2011, 0x4840, 0x71c4, 0xd1fc,
-	0x1110, 0x2011, 0x47c0, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003,
-	0x8003, 0xa268, 0x72c8, 0x73cc, 0x74d8, 0x71c6, 0x6800, 0x70ca,
-	0x73ce, 0x74da, 0x2091, 0x8000, 0x6a02, 0xd2ac, 0x1118, 0x2021,
-	0x0000, 0x0078, 0xa484, 0x00ff, 0xa082, 0x0002, 0x16e8, 0x843f,
-	0xa7bc, 0x00ff, 0x0130, 0xa786, 0x0002, 0x15b0, 0xa484, 0x00ff,
-	0x0598, 0x2061, 0x0200, 0xd1fc, 0x0110, 0x2061, 0x0100, 0x2029,
-	0x0009, 0x2031, 0x0062, 0x843f, 0xa7bc, 0x00ff, 0x0130, 0x8307,
-	0xa084, 0x00ff, 0x1110, 0xa73d, 0x11f8, 0x2041, 0x001d, 0x8307,
-	0xa084, 0x00ff, 0x0150, 0xa842, 0x02b8, 0xa3bc, 0x00ff, 0x2500,
-	0xa702, 0x0290, 0x2600, 0xa702, 0x1278, 0x2039, 0x003a, 0x6804,
-	0xa705, 0x6806, 0x6b0a, 0x6b0c, 0x73ce, 0x681c, 0x70da, 0x6c1e,
-	0x2091, 0x8001, 0x0804, 0x13a3, 0x2091, 0x8001, 0x0804, 0x139d,
-	0x77c4, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6a14, 0x6b1c, 0x2091,
-	0x8001, 0x70c8, 0x6816, 0x70cc, 0x681e, 0x2708, 0x0804, 0x13a0,
-	0x70c4, 0x2061, 0x4340, 0x6118, 0x601a, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x1904, 0x13a2, 0x70c8, 0x2061, 0x4380, 0x6218, 0x601a,
-	0x0804, 0x13a1, 0x71c4, 0x72c8, 0x73cc, 0xa182, 0x0010, 0x1a04,
-	0x139c, 0x080c, 0x2332, 0xa384, 0x4000, 0x0110, 0xa295, 0x0020,
-	0x0804, 0x13a0, 0x77c4, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6a08,
-	0xc28d, 0x6a0a, 0x2091, 0x8001, 0x2708, 0x0804, 0x13a1, 0x77c4,
-	0x080c, 0x1b1d, 0x2091, 0x8000, 0x6a08, 0xa294, 0xfff9, 0x6a0a,
-	0x6804, 0xa005, 0x0110, 0x080c, 0x2233, 0x2091, 0x8001, 0x2708,
-	0x0804, 0x13a1, 0x77c4, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6a08,
-	0xc295, 0x6a0a, 0x6804, 0xa005, 0x0110, 0x080c, 0x2233, 0x2091,
-	0x8001, 0x2708, 0x0804, 0x13a1, 0x77c4, 0x2041, 0x0001, 0x2049,
-	0x0005, 0x2051, 0x0020, 0x2091, 0x8000, 0x080c, 0x1b35, 0x2091,
-	0x8001, 0x2708, 0x6a08, 0x0804, 0x13a1, 0x77c4, 0xd7fc, 0x0128,
-	0x080c, 0x1aa9, 0x0138, 0x0804, 0x13a5, 0x080c, 0x1a9b, 0x0110,
-	0x0804, 0x13a5, 0x73c8, 0x72cc, 0x77c6, 0x73ca, 0x72ce, 0x080c,
-	0x1bad, 0x11e8, 0x6818, 0xa005, 0x01a0, 0x2708, 0x0076, 0x080c,
-	0x2351, 0x007e, 0x1170, 0x2001, 0x0015, 0xd7fc, 0x1118, 0x2061,
-	0x4340, 0x0018, 0xc0fd, 0x2061, 0x4380, 0x782a, 0x2091, 0x8001,
-	0x0005, 0x2091, 0x8001, 0x2001, 0x4005, 0x0804, 0x13a5, 0x2091,
-	0x8001, 0x0804, 0x13a3, 0x77c4, 0xd7fc, 0x0128, 0x080c, 0x1aa9,
-	0x0138, 0x0804, 0x13a5, 0x080c, 0x1a9b, 0x0110, 0x0804, 0x13a5,
-	0x77c6, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0020, 0x2091,
-	0x8000, 0x080c, 0x1b35, 0x2009, 0x0016, 0xd7fc, 0x1118, 0x2061,
-	0x4340, 0x0018, 0x2061, 0x4380, 0xc1fd, 0x6067, 0x0003, 0x607f,
-	0x0000, 0x6776, 0x6083, 0x000f, 0x792a, 0x080c, 0x2233, 0x2091,
-	0x8001, 0x0005, 0x77c8, 0x77ca, 0x77c4, 0x77c6, 0xd7fc, 0x0128,
-	0x080c, 0x1aa9, 0x0138, 0x0804, 0x13a5, 0x080c, 0x1a9b, 0x0110,
-	0x0804, 0x13a5, 0xa7bc, 0xff00, 0x2091, 0x8000, 0x2009, 0x0017,
-	0xd7fc, 0x1118, 0x2061, 0x4340, 0x0018, 0x2061, 0x4380, 0xc1fd,
-	0x607f, 0x0000, 0x6067, 0x0002, 0x6776, 0x6083, 0x000f, 0x792a,
-	0x080c, 0x2233, 0x2091, 0x8001, 0x2041, 0x0021, 0x2049, 0x0005,
-	0x2051, 0x0010, 0x2091, 0x8000, 0x70c8, 0xa005, 0x0118, 0x60d4,
-	0xc0fd, 0x60d6, 0x080c, 0x1b35, 0x70c8, 0x6836, 0x8738, 0xa784,
-	0x001f, 0x1dc0, 0x2091, 0x8001, 0x0005, 0x72c8, 0xd284, 0x0128,
-	0x080c, 0x1aa9, 0x0138, 0x0804, 0x13a5, 0x080c, 0x1a9b, 0x0110,
-	0x0804, 0x13a5, 0x72c8, 0x72ca, 0x78ac, 0xa084, 0x0003, 0x1508,
-	0x2039, 0x0000, 0xd284, 0x0108, 0xc7fd, 0x2041, 0x0021, 0x2049,
-	0x0004, 0x2051, 0x0008, 0x080c, 0x1b1d, 0x2091, 0x8000, 0x6808,
-	0xc0d4, 0xa80d, 0x690a, 0x2091, 0x8001, 0x8738, 0xa784, 0x001f,
-	0x1d90, 0xa7bc, 0xff00, 0x873f, 0x8738, 0x873f, 0xa784, 0x0f00,
-	0x1d50, 0x2091, 0x8000, 0x72c8, 0x2069, 0x0100, 0xd284, 0x1110,
-	0x2069, 0x0200, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4,
-	0x01b0, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0110,
-	0x1f04, 0x1885, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xd084,
-	0x0110, 0x1f04, 0x188e, 0x20a9, 0x00fa, 0x1f04, 0x1895, 0x2079,
-	0x4300, 0x2009, 0x0018, 0x72c8, 0xd284, 0x1118, 0x2061, 0x4340,
-	0x0018, 0x2061, 0x4380, 0xc1fd, 0x792a, 0x6067, 0x0001, 0x6083,
-	0x000f, 0x60a7, 0x0000, 0x60a8, 0x60b2, 0x60b6, 0x60d4, 0xd0b4,
-	0x0160, 0xc0b4, 0x60d6, 0x00c6, 0x60b8, 0xa065, 0x6008, 0xc0d4,
-	0x600a, 0x6018, 0x8001, 0x601a, 0x00ce, 0x60d4, 0xa084, 0x7eff,
-	0x60d6, 0x78ac, 0xc08d, 0x78ae, 0x681b, 0x0054, 0x2091, 0x8001,
-	0x0005, 0xd7fc, 0x1118, 0x2069, 0x4340, 0x0010, 0x2069, 0x4380,
-	0x71c4, 0x71c6, 0x6916, 0x81ff, 0x1110, 0x68a7, 0x0001, 0x78ac,
-	0xc08c, 0x78ae, 0xd084, 0x1110, 0x080c, 0x1c00, 0x0005, 0x75d8,
-	0x74dc, 0x75da, 0x74de, 0x0018, 0x2029, 0x0000, 0x2520, 0x71c4,
-	0x73c8, 0x72cc, 0x71c6, 0x73ca, 0x72ce, 0x2079, 0x4300, 0x7dde,
-	0x7cda, 0x7bd6, 0x7ad2, 0x080c, 0x1afa, 0x0904, 0x19d7, 0x20a9,
-	0x0005, 0x20a1, 0x4314, 0x2091, 0x8000, 0x41a1, 0x2091, 0x8001,
-	0x2009, 0x0040, 0x080c, 0x1cbf, 0x0120, 0x080c, 0x1b02, 0x0804,
-	0x19d7, 0x6004, 0xa08c, 0x00ff, 0xa18e, 0x0009, 0x1120, 0x0006,
-	0x080c, 0x1fe3, 0x000e, 0xa084, 0xff00, 0x8007, 0x8009, 0x0904,
-	0x1981, 0x00c6, 0x2c68, 0x080c, 0x1afa, 0x05a8, 0x2c00, 0x689e,
-	0x8109, 0x1dc0, 0x609f, 0x0000, 0x00ce, 0x00c6, 0x7ddc, 0x7cd8,
-	0x7bd4, 0x7ad0, 0xa290, 0x0040, 0xa399, 0x0000, 0xa4a1, 0x0000,
-	0xa5a9, 0x0000, 0x7dde, 0x7cda, 0x7bd6, 0x7ad2, 0x2c68, 0x689c,
-	0xa065, 0x0904, 0x1980, 0x2009, 0x0040, 0x080c, 0x1cbf, 0x1550,
-	0x6004, 0xa084, 0x00ff, 0xa086, 0x0002, 0x1168, 0x6004, 0xa084,
-	0x00ff, 0xa086, 0x000a, 0x1120, 0x0016, 0x080c, 0x1fe0, 0x001e,
-	0x2d00, 0x6002, 0x0898, 0x00ce, 0x00c6, 0x609c, 0x080c, 0x1b76,
-	0x00ce, 0x609f, 0x0000, 0x080c, 0x19db, 0x2009, 0x0018, 0x6008,
-	0xc0cd, 0x600a, 0x6004, 0x6086, 0x080c, 0x1ab7, 0x080c, 0x1b02,
-	0x0804, 0x19d7, 0x00ce, 0x00c6, 0x609c, 0x080c, 0x1b76, 0x00ce,
-	0x609f, 0x0000, 0x080c, 0x19db, 0x2009, 0x0018, 0x6087, 0x0103,
-	0x601b, 0x0003, 0x080c, 0x1ab7, 0x080c, 0x1b02, 0x0804, 0x19d7,
-	0x00ce, 0x6114, 0xd1fc, 0x0120, 0x080c, 0x1aa9, 0x01b8, 0x0018,
-	0x080c, 0x1a9b, 0x0198, 0x2029, 0x0000, 0x2520, 0x2009, 0x0018,
-	0x73c8, 0x72cc, 0x6087, 0x0103, 0x601b, 0x0021, 0x080c, 0x1ab7,
-	0x080c, 0x1b02, 0x2001, 0x4007, 0x0804, 0x13a5, 0x74c4, 0x73c8,
-	0x72cc, 0x6014, 0x2091, 0x8000, 0x00e6, 0x2009, 0x0012, 0xd0fc,
-	0x1118, 0x2071, 0x4340, 0x0018, 0x2071, 0x4380, 0xc1fd, 0x792a,
-	0x7067, 0x0005, 0x71d4, 0xa18c, 0xfe7f, 0x71d6, 0x736a, 0x726e,
-	0x7472, 0x7076, 0x707b, 0x0000, 0x2c00, 0x707e, 0xa02e, 0x2530,
-	0x611c, 0xa184, 0x0060, 0x0110, 0x080c, 0x3de5, 0x00ee, 0x6596,
+	0x13ac, 0x72c8, 0x0804, 0x13ab, 0x2011, 0x454d, 0x2204, 0x0006,
+	0x8104, 0x1208, 0x8108, 0x2112, 0x2019, 0x0000, 0x080c, 0x2354,
+	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x0118, 0x001e, 0x0804, 0x13b2,
+	0x71c8, 0xa182, 0x0010, 0x0228, 0x0006, 0x2110, 0x71c4, 0x0804,
+	0x13ab, 0x2011, 0x458d, 0x2204, 0x0006, 0x8104, 0x1208, 0x8108,
+	0x2112, 0xc3fd, 0x080c, 0x2354, 0x002e, 0x001e, 0x0804, 0x13b1,
+	0x71c4, 0x72c8, 0xa184, 0xfffd, 0x1904, 0x13ab, 0xa284, 0xfffd,
+	0x1904, 0x13ab, 0x2100, 0x7920, 0x7822, 0x2200, 0x7a24, 0x7826,
+	0x0804, 0x13b1, 0x2011, 0x4a40, 0x71c4, 0xd1fc, 0x1110, 0x2011,
+	0x49c0, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xa268,
+	0x72c8, 0x73cc, 0x74d8, 0x71c6, 0x6800, 0x70ca, 0x73ce, 0x74da,
+	0x2091, 0x8000, 0x6a02, 0xd2ac, 0x1118, 0x2021, 0x0000, 0x0090,
+	0xa484, 0x00ff, 0xa082, 0x0002, 0x1a04, 0x173b, 0x843f, 0xa7bc,
+	0x00ff, 0x0140, 0xa786, 0x0002, 0x1904, 0x173b, 0xa484, 0x00ff,
+	0x0904, 0x173b, 0x2061, 0x0200, 0xd1fc, 0x0110, 0x2061, 0x0100,
+	0x2029, 0x0009, 0x2031, 0x0062, 0x843f, 0xa7bc, 0x00ff, 0x0130,
+	0x8307, 0xa084, 0x00ff, 0x1110, 0xa73d, 0x1138, 0x2041, 0x001d,
+	0xa384, 0x00ff, 0xa082, 0x001a, 0x0210, 0xa4a4, 0x00ff, 0x8307,
+	0xa084, 0x00ff, 0x0188, 0xa842, 0x02f0, 0xa086, 0x0010, 0x1120,
+	0xa39c, 0x00ff, 0xa39d, 0x0f00, 0xa3bc, 0x00ff, 0x2500, 0xa702,
+	0x0290, 0x2600, 0xa702, 0x1278, 0x2039, 0x003a, 0x6804, 0xa705,
+	0x6806, 0x6b0a, 0x6b0c, 0x73ce, 0x681c, 0x70da, 0x6c1e, 0x2091,
+	0x8001, 0x0804, 0x13b3, 0x2091, 0x8001, 0x0804, 0x13ad, 0x77c4,
+	0x080c, 0x1b5f, 0x2091, 0x8000, 0x6a14, 0x6b1c, 0x2091, 0x8001,
+	0x70c8, 0x6816, 0x70cc, 0x681e, 0x2708, 0x0804, 0x13b0, 0x70c4,
+	0x2061, 0x4540, 0x6118, 0x601a, 0x2001, 0x01ff, 0x2004, 0xd0fc,
+	0x1904, 0x13b2, 0x70c8, 0x2061, 0x4580, 0x6218, 0x601a, 0x0804,
+	0x13b1, 0x71c4, 0x72c8, 0x73cc, 0xa182, 0x0010, 0x1a04, 0x13ac,
+	0x080c, 0x2397, 0xa384, 0x4000, 0x0110, 0xa295, 0x0020, 0x0804,
+	0x13b0, 0x77c4, 0x080c, 0x1b5f, 0x2091, 0x8000, 0x6a08, 0xc28d,
+	0x6a0a, 0x2091, 0x8001, 0x2708, 0x0804, 0x13b1, 0x77c4, 0x080c,
+	0x1b5f, 0x2091, 0x8000, 0x6a08, 0xa294, 0xfff9, 0x6a0a, 0x6804,
+	0xa005, 0x0110, 0x080c, 0x2296, 0x2091, 0x8001, 0x2708, 0x0804,
+	0x13b1, 0x77c4, 0x080c, 0x1b5f, 0x2091, 0x8000, 0x6a08, 0xc295,
+	0x6a0a, 0x6804, 0xa005, 0x0110, 0x080c, 0x2296, 0x2091, 0x8001,
+	0x2708, 0x0804, 0x13b1, 0x77c4, 0x2041, 0x0001, 0x2049, 0x0005,
+	0x2051, 0x0020, 0x2091, 0x8000, 0x080c, 0x1b77, 0x2091, 0x8001,
+	0x2708, 0x6a08, 0x0804, 0x13b1, 0x77c4, 0xd7fc, 0x0128, 0x080c,
+	0x1aeb, 0x0138, 0x0804, 0x13b5, 0x080c, 0x1add, 0x0110, 0x0804,
+	0x13b5, 0x73c8, 0x72cc, 0x77c6, 0x73ca, 0x72ce, 0x080c, 0x1bef,
+	0x11e8, 0x6818, 0xa005, 0x01a0, 0x2708, 0x0076, 0x080c, 0x23b6,
+	0x007e, 0x1170, 0x2001, 0x0015, 0xd7fc, 0x1118, 0x2061, 0x4540,
+	0x0018, 0xc0fd, 0x2061, 0x4580, 0x782a, 0x2091, 0x8001, 0x0005,
+	0x2091, 0x8001, 0x2001, 0x4005, 0x0804, 0x13b5, 0x2091, 0x8001,
+	0x0804, 0x13b3, 0x77c4, 0xd7fc, 0x0128, 0x080c, 0x1aeb, 0x0138,
+	0x0804, 0x13b5, 0x080c, 0x1add, 0x0110, 0x0804, 0x13b5, 0x77c6,
+	0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0020, 0x2091, 0x8000,
+	0x080c, 0x1b77, 0x2009, 0x0016, 0xd7fc, 0x1118, 0x2061, 0x4540,
+	0x0018, 0x2061, 0x4580, 0xc1fd, 0x6063, 0x0003, 0x607b, 0x0000,
+	0x6772, 0x607f, 0x000f, 0x792a, 0x080c, 0x2296, 0x2091, 0x8001,
+	0x0005, 0x77c8, 0x77ca, 0x77c4, 0x77c6, 0xd7fc, 0x0128, 0x080c,
+	0x1aeb, 0x0138, 0x0804, 0x13b5, 0x080c, 0x1add, 0x0110, 0x0804,
+	0x13b5, 0xa7bc, 0xff00, 0x2091, 0x8000, 0x2009, 0x0017, 0xd7fc,
+	0x1118, 0x2061, 0x4540, 0x0018, 0x2061, 0x4580, 0xc1fd, 0x607b,
+	0x0000, 0x6063, 0x0002, 0x6772, 0x607f, 0x000f, 0x792a, 0x080c,
+	0x2296, 0x2091, 0x8001, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051,
+	0x0010, 0x2091, 0x8000, 0x70c8, 0xa005, 0x0118, 0x60d0, 0xc0fd,
+	0x60d2, 0x080c, 0x1b77, 0x70c8, 0x6836, 0x8738, 0xa784, 0x001f,
+	0x1dc0, 0x2091, 0x8001, 0x0005, 0x2019, 0x0000, 0x72c8, 0xd284,
+	0x0128, 0x080c, 0x1aeb, 0x0138, 0x0804, 0x13b5, 0x080c, 0x1add,
+	0x0110, 0x0804, 0x13b5, 0x72c8, 0x72ca, 0x78ac, 0xa084, 0x0003,
+	0x1508, 0x2039, 0x0000, 0xd284, 0x0108, 0xc7fd, 0x2041, 0x0021,
+	0x2049, 0x0004, 0x2051, 0x0008, 0x080c, 0x1b5f, 0x2091, 0x8000,
+	0x6808, 0xc0d4, 0xa80d, 0x690a, 0x2091, 0x8001, 0x8738, 0xa784,
+	0x001f, 0x1d90, 0xa7bc, 0xff00, 0x873f, 0x8738, 0x873f, 0xa784,
+	0x0f00, 0x1d50, 0x2091, 0x8000, 0x72c8, 0x2069, 0x0100, 0xd284,
+	0x1110, 0x2069, 0x0200, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830,
+	0xd0b4, 0x01b0, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094,
+	0x0110, 0x1f04, 0x18a6, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848,
+	0xd084, 0x0110, 0x1f04, 0x18af, 0x20a9, 0x00fa, 0x1f04, 0x18b6,
+	0x2079, 0x4500, 0x2009, 0x0018, 0x72c8, 0xd284, 0x1118, 0x2061,
+	0x4540, 0x0018, 0x2061, 0x4580, 0xc1fd, 0x607b, 0x0000, 0x792a,
+	0x6063, 0x0001, 0x607f, 0x000f, 0x60a3, 0x0000, 0x60a4, 0x60ae,
+	0x60b2, 0x60d0, 0xd0b4, 0x0160, 0xc0b4, 0x60d2, 0x00c6, 0x60b4,
+	0xa065, 0x6008, 0xc0d4, 0x600a, 0x6018, 0x8001, 0x601a, 0x00ce,
+	0x60d0, 0xa084, 0x7eff, 0x60d2, 0x78ac, 0xc08d, 0x78ae, 0x83ff,
+	0x0108, 0x0005, 0x681b, 0x0054, 0x2091, 0x8001, 0x0005, 0x73cc,
+	0x080c, 0x185e, 0x69ec, 0x6a48, 0xa185, 0x1800, 0x684a, 0xa185,
+	0x0040, 0x68ee, 0x73cc, 0x2021, 0x0004, 0x20a9, 0x09ff, 0x1f04,
+	0x18ff, 0x8421, 0x1dd0, 0x8319, 0x1db0, 0x69ee, 0x6a4a, 0x2091,
+	0x8001, 0x0005, 0xd7fc, 0x1118, 0x2069, 0x4540, 0x0010, 0x2069,
+	0x4580, 0x71c4, 0x71c6, 0x6916, 0x81ff, 0x1110, 0x68a3, 0x0001,
+	0x78ac, 0xc08c, 0x78ae, 0xd084, 0x1110, 0x080c, 0x1c42, 0x0005,
+	0x75d8, 0x74dc, 0x75da, 0x74de, 0x0018, 0x2029, 0x0000, 0x2520,
+	0x71c4, 0x73c8, 0x72cc, 0x71c6, 0x73ca, 0x72ce, 0x2079, 0x4500,
+	0x7dde, 0x7cda, 0x7bd6, 0x7ad2, 0x080c, 0x1b3c, 0x0904, 0x1a17,
+	0x20a9, 0x0005, 0x20a1, 0x4514, 0x2091, 0x8000, 0x41a1, 0x2091,
+	0x8001, 0x2009, 0x0040, 0x080c, 0x1d0b, 0x0120, 0x080c, 0x1b44,
+	0x0804, 0x1a17, 0x6004, 0xa08c, 0x00ff, 0xa18e, 0x0009, 0x1120,
+	0x0006, 0x080c, 0x2046, 0x000e, 0xa084, 0xff00, 0x8007, 0x8009,
+	0x0904, 0x19c2, 0x00c6, 0x2c68, 0x080c, 0x1b3c, 0x05a8, 0x2c00,
+	0x689e, 0x8109, 0x1dc0, 0x609f, 0x0000, 0x00ce, 0x00c6, 0x7ddc,
+	0x7cd8, 0x7bd4, 0x7ad0, 0xa290, 0x0040, 0xa399, 0x0000, 0xa4a1,
+	0x0000, 0xa5a9, 0x0000, 0x7dde, 0x7cda, 0x7bd6, 0x7ad2, 0x2c68,
+	0x689c, 0xa065, 0x0904, 0x19c1, 0x2009, 0x0040, 0x080c, 0x1d0b,
+	0x1550, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0002, 0x1168, 0x6004,
+	0xa084, 0x00ff, 0xa086, 0x000a, 0x1120, 0x0016, 0x080c, 0x2043,
+	0x001e, 0x2d00, 0x6002, 0x0898, 0x00ce, 0x00c6, 0x609c, 0x080c,
+	0x1bb8, 0x00ce, 0x609f, 0x0000, 0x080c, 0x1a1b, 0x2009, 0x0018,
+	0x6008, 0xc0cd, 0x600a, 0x6004, 0x6086, 0x080c, 0x1af9, 0x080c,
+	0x1b44, 0x0804, 0x1a17, 0x00ce, 0x00c6, 0x609c, 0x080c, 0x1bb8,
+	0x00ce, 0x609f, 0x0000, 0x080c, 0x1a1b, 0x2009, 0x0018, 0x6087,
+	0x0103, 0x601b, 0x0003, 0x080c, 0x1af9, 0x080c, 0x1b44, 0x0804,
+	0x1a17, 0x00ce, 0x6114, 0xd1fc, 0x0120, 0x080c, 0x1aeb, 0x01b8,
+	0x0018, 0x080c, 0x1add, 0x0198, 0x2029, 0x0000, 0x2520, 0x2009,
+	0x0018, 0x73c8, 0x72cc, 0x6087, 0x0103, 0x601b, 0x0021, 0x080c,
+	0x1af9, 0x080c, 0x1b44, 0x2001, 0x4007, 0x0804, 0x13b5, 0x74c4,
+	0x73c8, 0x72cc, 0x6014, 0x2091, 0x8000, 0x00e6, 0x2009, 0x0012,
+	0xd0fc, 0x1118, 0x2071, 0x4540, 0x0018, 0x2071, 0x4580, 0xc1fd,
+	0x792a, 0x7063, 0x0005, 0x71d0, 0xc1c4, 0x71d2, 0x7366, 0x726a,
+	0x746e, 0x7072, 0x7077, 0x0000, 0x2c00, 0x707a, 0xa02e, 0x2530,
+	0x611c, 0xa184, 0x0060, 0x0110, 0x080c, 0x3f66, 0x00ee, 0x6596,
 	0x65a6, 0x669a, 0x66aa, 0x60af, 0x0000, 0x60b3, 0x0000, 0x6714,
-	0x6023, 0x0000, 0x080c, 0x2233, 0x2091, 0x8001, 0x0005, 0x70c3,
-	0x4005, 0x0804, 0x13a6, 0x20a9, 0x0005, 0x2099, 0x4314, 0x2091,
+	0x6023, 0x0000, 0x080c, 0x2296, 0x2091, 0x8001, 0x0005, 0x70c3,
+	0x4005, 0x0804, 0x13b6, 0x20a9, 0x0005, 0x2099, 0x4514, 0x2091,
 	0x8000, 0x530a, 0x2091, 0x8001, 0x2100, 0xa210, 0xa399, 0x0000,
 	0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x0005, 0x71c4, 0x70c7, 0x0000,
-	0x791e, 0x0804, 0x13a3, 0x71c4, 0x71c6, 0x2168, 0x0010, 0x2069,
+	0x791e, 0x0804, 0x13b3, 0x71c4, 0x71c6, 0x2168, 0x0010, 0x2069,
 	0x1000, 0x690c, 0xa016, 0x2d04, 0xa210, 0x8d68, 0x8109, 0x1dd8,
 	0xa285, 0x0000, 0x1118, 0x70c3, 0x4000, 0x0010, 0x70c3, 0x4003,
-	0x70ca, 0x0804, 0x13a6, 0x7964, 0x71c6, 0x71c4, 0xa182, 0x0003,
-	0x1a04, 0x139c, 0x7966, 0x0804, 0x13a3, 0x7964, 0x71c6, 0x0804,
-	0x13a3, 0x7900, 0x71c6, 0x71c4, 0x7902, 0x0804, 0x13a3, 0x7900,
-	0x71c6, 0x0804, 0x13a3, 0x70c4, 0x2011, 0x0000, 0xa08c, 0x000d,
+	0x70ca, 0x0804, 0x13b6, 0x7964, 0x71c6, 0x71c4, 0xa182, 0x0003,
+	0x1a04, 0x13ac, 0x7966, 0x0804, 0x13b3, 0x7964, 0x71c6, 0x0804,
+	0x13b3, 0x7900, 0x71c6, 0x71c4, 0x7902, 0x0804, 0x13b3, 0x7900,
+	0x71c6, 0x0804, 0x13b3, 0x70c4, 0x2011, 0x0000, 0xa08c, 0x000d,
 	0x0160, 0x810c, 0x0230, 0x8210, 0x810c, 0x810c, 0x0210, 0x8210,
-	0x810c, 0x81ff, 0x1904, 0x139d, 0x8210, 0x7a0e, 0xd28c, 0x0538,
+	0x810c, 0x81ff, 0x1904, 0x13ad, 0x8210, 0x7a0e, 0xd28c, 0x0538,
 	0x7910, 0xc1cd, 0x7912, 0x2009, 0x0021, 0x2019, 0x0003, 0xd284,
-	0x01c0, 0x8108, 0x2019, 0x0041, 0x2011, 0x8b4e, 0x2312, 0x2019,
+	0x01c0, 0x8108, 0x2019, 0x0041, 0x2011, 0x8d4e, 0x2312, 0x2019,
 	0x0042, 0x8210, 0x2312, 0x2019, 0x0043, 0x8210, 0x2312, 0x2019,
 	0x0046, 0x8210, 0x2312, 0x2019, 0x0047, 0x8210, 0x2312, 0x2019,
-	0x0006, 0x2011, 0x8b53, 0x2112, 0x2011, 0x8b73, 0x2312, 0x7904,
-	0x7806, 0x0804, 0x13a2, 0x7804, 0x70c6, 0x0804, 0x13a3, 0x71c4,
-	0xd1fc, 0x1118, 0x2011, 0x47c0, 0x0010, 0x2011, 0x4840, 0x8107,
+	0x0006, 0x2011, 0x8d53, 0x2112, 0x2011, 0x8d73, 0x2312, 0x7904,
+	0x7806, 0x0804, 0x13b2, 0x7804, 0x70c6, 0x0804, 0x13b3, 0x71c4,
+	0xd1fc, 0x1118, 0x2011, 0x49c0, 0x0010, 0x2011, 0x4a40, 0x8107,
 	0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xa268, 0x2011, 0x0000,
 	0x6814, 0xd0fc, 0x0110, 0xa295, 0x0200, 0xd0b4, 0x0110, 0xa295,
-	0x0001, 0x6b0c, 0x0804, 0x13a0, 0x0016, 0x7814, 0xd0f4, 0x0138,
-	0x2001, 0x4007, 0x70db, 0x0000, 0xa18d, 0x0001, 0x0050, 0xd0fc,
-	0x0138, 0x2001, 0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0008,
-	0xa006, 0x001e, 0x0005, 0x0016, 0x7814, 0xd0f4, 0x0138, 0x2001,
-	0x4007, 0x70db, 0x0000, 0xa18d, 0x0001, 0x0008, 0xa006, 0x001e,
-	0x0005, 0x0016, 0x7814, 0xd0fc, 0x0138, 0x2001, 0x4007, 0x70db,
-	0x0001, 0xa18d, 0x0001, 0x0008, 0xa006, 0x001e, 0x0005, 0x7112,
-	0x721a, 0x731e, 0x7810, 0xd0c4, 0x0110, 0x7422, 0x7526, 0xac80,
-	0x0001, 0x8108, 0x810c, 0x81a9, 0x8098, 0x20a1, 0x0030, 0x7003,
-	0x0000, 0x6084, 0x20a2, 0x53a6, 0x7007, 0x0001, 0x7974, 0xa184,
-	0xff00, 0x0140, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007,
-	0xa100, 0x0018, 0x8107, 0x8004, 0x8004, 0x797c, 0xa108, 0x7a78,
-	0xa006, 0xa211, 0x7d10, 0xd5c4, 0x0120, 0x7b84, 0xa319, 0x7c80,
-	0xa421, 0x7008, 0xd0fc, 0x0de8, 0x7003, 0x0001, 0x7007, 0x0006,
-	0x711a, 0x721e, 0x7d10, 0xd5c4, 0x0110, 0x7322, 0x7426, 0xa084,
-	0x01e0, 0x0005, 0x7848, 0xa065, 0x0120, 0x2c04, 0x784a, 0x2063,
-	0x0000, 0x0005, 0x00f6, 0x2079, 0x4300, 0x7848, 0x2062, 0x2c00,
-	0xa005, 0x1110, 0x080c, 0x243b, 0x784a, 0x00fe, 0x0005, 0x2011,
-	0x8d00, 0x7a4a, 0x7bc4, 0x8319, 0x0128, 0xa280, 0x0032, 0x2012,
-	0x2010, 0x0cc8, 0x2013, 0x0000, 0x0005, 0x0016, 0x0026, 0xd7fc,
-	0x1118, 0x2011, 0x48c0, 0x0010, 0x2011, 0x68c0, 0xa784, 0x0f00,
-	0x800b, 0xa784, 0x001f, 0x0120, 0x8003, 0x8003, 0x8003, 0x8003,
-	0xa105, 0xa268, 0x002e, 0x001e, 0x0005, 0x0c39, 0x2900, 0x682a,
-	0x2a00, 0x682e, 0x6808, 0xa084, 0xf9ef, 0xa80d, 0x690a, 0x00e6,
-	0xd7fc, 0x1128, 0x2009, 0x4353, 0x2071, 0x4340, 0x0020, 0x2009,
-	0x4393, 0x2071, 0x4380, 0x210c, 0x6804, 0xa005, 0x0148, 0xa116,
-	0x1138, 0x2060, 0x6000, 0x6806, 0x0016, 0x200b, 0x0000, 0x0018,
-	0x2009, 0x0000, 0x0016, 0x6804, 0xa065, 0x0178, 0x6000, 0x6806,
-	0x0421, 0x080c, 0x1d30, 0x6810, 0x7908, 0x8109, 0x790a, 0x8001,
-	0x6812, 0x1d88, 0x7910, 0xc1a5, 0x7912, 0x001e, 0x6902, 0x6906,
-	0x2d00, 0x2060, 0x080c, 0x2580, 0x00ee, 0x0005, 0xa065, 0x0160,
-	0x2008, 0x609c, 0xa005, 0x0128, 0x2062, 0x609f, 0x0000, 0xa065,
-	0x0cc0, 0x7848, 0x794a, 0x2062, 0x0005, 0x6007, 0x0103, 0x608f,
-	0x0000, 0x20a9, 0x001c, 0xac80, 0x0005, 0x20a0, 0x2001, 0x0000,
-	0x40a4, 0x6828, 0x601a, 0x682c, 0x6022, 0x0005, 0x00e6, 0xd7fc,
-	0x1128, 0x2071, 0x4340, 0x2031, 0x43c0, 0x0020, 0x2071, 0x4380,
-	0x2031, 0x45c0, 0x7050, 0xa08c, 0x0200, 0x1128, 0xa608, 0x2d0a,
-	0x8000, 0x7052, 0xa006, 0x00ee, 0x0005, 0x00f6, 0xd7fc, 0x1118,
-	0x2079, 0x4340, 0x0010, 0x2079, 0x4380, 0x080c, 0x1b1d, 0x2091,
-	0x8000, 0x6804, 0x780a, 0xa065, 0x0904, 0x1bfe, 0x0030, 0x2c00,
-	0x780a, 0x2060, 0x6000, 0xa065, 0x05c8, 0x6010, 0xa306, 0x1db8,
-	0x600c, 0xa206, 0x1da0, 0x2c28, 0x784c, 0xac06, 0x1108, 0x0458,
-	0x6804, 0xac06, 0x1140, 0x6000, 0x2060, 0x6806, 0xa005, 0x1118,
-	0x6803, 0x0000, 0x0048, 0x6400, 0x7808, 0x2060, 0x6402, 0xa486,
-	0x0000, 0x1110, 0x2c00, 0x6802, 0x2560, 0x00fe, 0x080c, 0x1b85,
-	0x00f6, 0x601b, 0x0005, 0x6023, 0x0020, 0x00fe, 0x080c, 0x1d30,
-	0x00f6, 0x7908, 0x8109, 0x790a, 0x6810, 0x8001, 0x6812, 0x1118,
-	0x7810, 0xc0a5, 0x7812, 0x2001, 0xffff, 0xa005, 0x00fe, 0x0005,
-	0x0076, 0x2700, 0x2039, 0x0000, 0xd0fc, 0x0108, 0xc7fd, 0x2041,
-	0x0021, 0x2049, 0x0004, 0x2051, 0x0008, 0x2091, 0x8000, 0x080c,
-	0x1b35, 0x8738, 0xa784, 0x001f, 0x1dd0, 0xa7bc, 0xff00, 0x873f,
-	0x8738, 0x873f, 0xa784, 0x0f00, 0x1d90, 0x2091, 0x8001, 0x007e,
-	0x0005, 0x786c, 0x2009, 0x8b74, 0x210c, 0xa10d, 0x0118, 0xa065,
-	0x0804, 0x1ffe, 0x2061, 0x0000, 0x6018, 0xd084, 0x11b8, 0x7810,
-	0xd08c, 0x0130, 0xc08c, 0x7812, 0xc7fc, 0x2069, 0x4340, 0x0028,
-	0xc08d, 0x7812, 0x2069, 0x4380, 0xc7fd, 0x2091, 0x8000, 0x681c,
-	0x681f, 0x0000, 0x2091, 0x8001, 0xa005, 0x1108, 0x0005, 0xa08c,
-	0xfff0, 0x0110, 0x080c, 0x243b, 0x0002, 0x1c5d, 0x1c60, 0x1c66,
-	0x1c6a, 0x1c5e, 0x1c6e, 0x1c5e, 0x1c5e, 0x1c5e, 0x1c73, 0x1c9f,
-	0x1ca2, 0x1ca7, 0x1c5e, 0x1c5e, 0x1c5e, 0x0005, 0x080c, 0x243b,
-	0x080c, 0x1c00, 0x2001, 0x8001, 0x0804, 0x1cb0, 0x2001, 0x8003,
-	0x0804, 0x1cb0, 0x2001, 0x8004, 0x0804, 0x1cb0, 0x080c, 0x1c00,
-	0x2001, 0x8006, 0x04e8, 0x2091, 0x8000, 0x0076, 0xd7fc, 0x1128,
-	0x2069, 0x4340, 0x2039, 0x0009, 0x0020, 0x2069, 0x4380, 0x2039,
-	0x0009, 0x6800, 0xa086, 0x0000, 0x0128, 0x000e, 0x6f1e, 0x2091,
-	0x8001, 0x0005, 0x6874, 0x007e, 0xa0bc, 0xff00, 0x2041, 0x0021,
-	0x2049, 0x0004, 0x2051, 0x0010, 0x080c, 0x1b35, 0x8738, 0xa784,
-	0x001f, 0x1dd0, 0x2091, 0x8001, 0x2001, 0x800a, 0x0088, 0x2001,
-	0x800c, 0x0070, 0x080c, 0x1c00, 0x2001, 0x800d, 0x0048, 0xd7fc,
-	0x0110, 0x78ec, 0x0008, 0x78e4, 0x70c6, 0x2001, 0x800e, 0x0000,
-	0x70c2, 0xd7fc, 0x1118, 0x70db, 0x0000, 0x0010, 0x70db, 0x0001,
-	0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x4080, 0x0005, 0xac80,
-	0x0001, 0x81ff, 0x0518, 0x2099, 0x0030, 0x20a0, 0x700c, 0xa084,
-	0x07ff, 0x0100, 0x7018, 0x0006, 0x701c, 0x0006, 0x7020, 0x0006,
-	0x7024, 0x0006, 0x7112, 0x81ac, 0x721a, 0x731e, 0x7422, 0x7526,
-	0x7003, 0x0001, 0x7007, 0x0001, 0x7008, 0x800b, 0x1ee8, 0x7007,
-	0x0002, 0xa08c, 0x01e0, 0x1110, 0x53a5, 0xa006, 0x7003, 0x0000,
-	0x7007, 0x0004, 0x000e, 0x7026, 0x000e, 0x7022, 0x000e, 0x701e,
-	0x000e, 0x701a, 0x0005, 0x2011, 0x0020, 0x2009, 0x0010, 0x6b0a,
-	0x6c0e, 0x681f, 0x0201, 0x6803, 0xfd20, 0x6807, 0x0038, 0x6a1a,
-	0x2d00, 0xa0e8, 0x0008, 0xa290, 0x0004, 0x8109, 0x1d80, 0x0005,
-	0x70ec, 0xd0dc, 0x1520, 0x2029, 0x0001, 0x7814, 0xd0cc, 0x1160,
-	0x70ec, 0xd0e4, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1120, 0x2019,
-	0x0c0c, 0x2021, 0x000c, 0x0070, 0x70ec, 0xd0e4, 0x1128, 0x2019,
-	0x1c0c, 0x2021, 0x000c, 0x0030, 0x2019, 0x1c09, 0x2021, 0x0009,
-	0xa5ad, 0x0200, 0x6b0a, 0x6c0e, 0x6d1e, 0x6807, 0x0038, 0x0005,
-	0x6004, 0x6086, 0x2c08, 0x2063, 0x0000, 0x7868, 0xa005, 0x796a,
-	0x0110, 0x2c02, 0x0008, 0x796e, 0x0005, 0x00c6, 0x2061, 0x4300,
-	0x6887, 0x0103, 0x2d08, 0x206b, 0x0000, 0x6068, 0xa005, 0x616a,
-	0x0110, 0x2d02, 0x0008, 0x616e, 0x00ce, 0x0005, 0x2091, 0x8000,
-	0x2c04, 0x786e, 0xa005, 0x1108, 0x786a, 0x2091, 0x8001, 0x609c,
-	0xa005, 0x0188, 0x00c6, 0x2060, 0x2008, 0x609c, 0xa005, 0x0138,
-	0x2062, 0x609f, 0x0000, 0xa065, 0x609c, 0xa005, 0x1dc8, 0x7848,
-	0x794a, 0x2062, 0x00ce, 0x7848, 0x2062, 0x609f, 0x0000, 0xac85,
-	0x0000, 0x1110, 0x080c, 0x243b, 0x784a, 0x0005, 0x20a9, 0x0010,
-	0xa006, 0x8004, 0x8086, 0x818e, 0x1208, 0xa200, 0x1f04, 0x1d7a,
-	0x8086, 0x818e, 0x0005, 0x0156, 0x20a9, 0x0010, 0xa005, 0x01b8,
-	0xa11a, 0x12a8, 0x8213, 0x818d, 0x0228, 0xa11a, 0x1220, 0x1f04,
-	0x1d8a, 0x0028, 0xa11a, 0x2308, 0x8210, 0x1f04, 0x1d8a, 0x0006,
-	0x3200, 0xa084, 0xefff, 0x2080, 0x000e, 0x015e, 0x0005, 0x0006,
-	0x3200, 0xa085, 0x1000, 0x0cb8, 0x7d74, 0x70d0, 0xa506, 0x0904,
-	0x1e5b, 0x7810, 0x2050, 0x7800, 0xd08c, 0x0100, 0x080c, 0x1afa,
-	0x0904, 0x1e5b, 0xa046, 0x7970, 0x2500, 0x8000, 0xa112, 0x2009,
-	0x0040, 0x1208, 0x0030, 0x72d0, 0xa206, 0x0118, 0x8840, 0x2009,
-	0x0080, 0x00c6, 0x7112, 0x7007, 0x0001, 0x2099, 0x0030, 0x20a9,
-	0x0020, 0xac80, 0x0001, 0x20a0, 0x2061, 0x0000, 0x88ff, 0x0110,
-	0x080c, 0x1afa, 0x7008, 0xd0fc, 0x0de8, 0x7007, 0x0002, 0x2091,
-	0x8001, 0xa08c, 0x01e0, 0x1538, 0x53a5, 0x8cff, 0x1120, 0x88ff,
-	0x0904, 0x1e48, 0x0050, 0x2c00, 0x788e, 0x20a9, 0x0020, 0xac80,
-	0x0001, 0x20a0, 0x53a5, 0x0804, 0x1e48, 0xa046, 0x7218, 0x731c,
-	0xdac4, 0x0110, 0x7420, 0x7524, 0xa292, 0x0040, 0xa39b, 0x0000,
-	0xa4a3, 0x0000, 0xa5ab, 0x0000, 0x721a, 0x731e, 0xdac4, 0x0118,
-	0x7422, 0x7526, 0xa006, 0x7007, 0x0004, 0x0904, 0x1e48, 0x8cff,
-	0x0110, 0x080c, 0x1b02, 0x00ce, 0x080c, 0x1b02, 0xa046, 0x7888,
-	0x8000, 0x788a, 0xa086, 0x0002, 0x01c0, 0x7a7c, 0x7b78, 0xdac4,
-	0x0110, 0x7c84, 0x7d80, 0x7974, 0x8107, 0x8004, 0x8004, 0xa210,
-	0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x721a, 0x731e,
-	0xdac4, 0x0588, 0x7422, 0x7526, 0x0470, 0x6014, 0xd0fc, 0x1118,
-	0x2069, 0x4340, 0x0010, 0x2069, 0x4380, 0x2091, 0x8000, 0x681f,
-	0x0002, 0x88ff, 0x0120, 0xa046, 0x788c, 0x2060, 0x0c70, 0x788b,
-	0x0000, 0x78ac, 0xa085, 0x0003, 0x78ae, 0x2091, 0x8001, 0x0098,
-	0x00ce, 0x788b, 0x0000, 0x080c, 0x1fb9, 0x6004, 0xa084, 0x000f,
-	0x0059, 0x88ff, 0x0130, 0x788c, 0x2060, 0x6004, 0xa084, 0x000f,
-	0x0019, 0x0804, 0x1da4, 0x0005, 0x0002, 0x1e6d, 0x1e88, 0x1ea1,
-	0x1e6d, 0x1eae, 0x1e7e, 0x1e6d, 0x1e6d, 0x1e6d, 0x1e86, 0x1e9f,
-	0x1e6d, 0x1e6d, 0x1e6d, 0x1e6d, 0x1e6d, 0x2039, 0x0400, 0x78bc,
-	0xa705, 0x78be, 0x6008, 0xa705, 0x600a, 0x080c, 0x1eea, 0x609c,
-	0x78ba, 0x609f, 0x0000, 0x080c, 0x1fa5, 0x0005, 0x78bc, 0xd0c4,
-	0x0108, 0x0c58, 0x601c, 0xc0bd, 0x601e, 0x0030, 0x080c, 0x1fe3,
-	0x78bc, 0xd0c4, 0x0108, 0x0c08, 0x78bf, 0x0000, 0x6004, 0x8007,
-	0xa084, 0x00ff, 0x78b2, 0x8001, 0x0138, 0x080c, 0x1eea, 0x0120,
-	0x78bc, 0xc0c5, 0x78be, 0x0010, 0x0804, 0x1f05, 0x0005, 0x080c,
-	0x1fe0, 0x78bc, 0xa08c, 0x0e00, 0x1110, 0xd0c4, 0x1108, 0x0828,
-	0x080c, 0x1eea, 0x1110, 0x0804, 0x1f05, 0x0005, 0x78bc, 0xd0c4,
-	0x0110, 0x0804, 0x1e6d, 0x78bf, 0x0000, 0x6714, 0x2011, 0x0001,
-	0x22a8, 0x6018, 0xa084, 0x00ff, 0xa005, 0x0188, 0xa7bc, 0xff00,
-	0x20a9, 0x0020, 0xa08e, 0x0001, 0x0150, 0xa7bc, 0x8000, 0x2011,
-	0x0002, 0x20a9, 0x0100, 0xa08e, 0x0002, 0x0108, 0x00c0, 0x080c,
-	0x1b1d, 0x2d00, 0x2091, 0x8000, 0x682b, 0x0000, 0x682f, 0x0000,
-	0x6808, 0xa084, 0xffde, 0x680a, 0xade8, 0x0010, 0x2091, 0x8001,
-	0x1f04, 0x1ed2, 0x8211, 0x0118, 0x20a9, 0x0100, 0x0c58, 0x080c,
-	0x1b02, 0x0005, 0x609f, 0x0000, 0x78b4, 0xa06d, 0x2c00, 0x78b6,
-	0x1110, 0x78ba, 0x0038, 0x689e, 0x2d00, 0x6002, 0x78b8, 0xad06,
-	0x1108, 0x6002, 0x78b0, 0x8001, 0x78b2, 0x1130, 0x78bc, 0xc0c4,
-	0x78be, 0x78b8, 0x2060, 0xa006, 0x0005, 0x00e6, 0xa02e, 0x2530,
-	0x7dba, 0x7db6, 0x65ae, 0x65b2, 0x601c, 0x60a2, 0x2048, 0xa984,
-	0xe1ff, 0x601e, 0xa984, 0x0060, 0x0110, 0x080c, 0x3de5, 0x6596,
-	0x65a6, 0x669a, 0x66aa, 0x6714, 0x2071, 0x4380, 0xd7fc, 0x1110,
-	0x2071, 0x4340, 0xa784, 0x0f00, 0x800b, 0xa784, 0x001f, 0x0120,
-	0x8003, 0x8003, 0x8003, 0x8003, 0xa105, 0x71c4, 0xa168, 0x2700,
-	0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0x71c8, 0xa100,
-	0x60c2, 0x2091, 0x8000, 0x6e08, 0xd684, 0x0170, 0xd9fc, 0x1160,
-	0x2091, 0x8001, 0x080c, 0x1b85, 0x2091, 0x8000, 0x080c, 0x1d30,
-	0x2091, 0x8001, 0x0804, 0x1fa3, 0x6024, 0xa096, 0x0001, 0x1110,
-	0x8000, 0x6026, 0x6a10, 0x6814, 0xa202, 0x0268, 0x0160, 0x2091,
-	0x8001, 0x2039, 0x0200, 0x609c, 0x78ba, 0x609f, 0x0000, 0x080c,
-	0x1fa5, 0x0804, 0x1fa3, 0x2c08, 0xd9fc, 0x01f0, 0x6800, 0xa065,
-	0x01d8, 0x6a04, 0x7000, 0xa084, 0x0002, 0x0168, 0x704c, 0xa206,
-	0x1150, 0x6b04, 0x2160, 0x2304, 0x6002, 0xa005, 0x1108, 0x6902,
-	0x2260, 0x6102, 0x0098, 0x2d00, 0x2060, 0x080c, 0x2580, 0x6e08,
-	0x2160, 0x6202, 0x6906, 0x0050, 0x6800, 0x6902, 0xa065, 0x0110,
-	0x6102, 0x0008, 0x6906, 0x2160, 0x6003, 0x0000, 0x2160, 0xd9fc,
-	0x0118, 0xa6b4, 0xfffc, 0x6e0a, 0x6810, 0x7d08, 0x8528, 0x7d0a,
-	0x8000, 0x6812, 0x2091, 0x8001, 0xd6b4, 0x0128, 0xa6b6, 0x0040,
-	0x6e0a, 0x080c, 0x1b96, 0x00ee, 0x0005, 0x6008, 0xa705, 0x600a,
-	0x2091, 0x8000, 0x080c, 0x1d30, 0x2091, 0x8001, 0x78b8, 0xa065,
-	0x0128, 0x609c, 0x78ba, 0x609f, 0x0000, 0x0c78, 0x78b6, 0x78ba,
-	0x0005, 0x7970, 0x7874, 0x2818, 0xd384, 0x0118, 0x8000, 0xa112,
-	0x0220, 0x8000, 0xa112, 0x1278, 0xc384, 0x7a7c, 0x721a, 0x7a78,
-	0x721e, 0xdac4, 0x0120, 0x7a84, 0x7222, 0x7a80, 0x7226, 0xa006,
-	0xd384, 0x0108, 0x8000, 0x7876, 0x70d2, 0x781c, 0xa005, 0x0138,
-	0x8001, 0x781e, 0x1120, 0x0e04, 0x1fdf, 0x2091, 0x4080, 0x0005,
-	0x2039, 0x1ff5, 0x0010, 0x2039, 0x1ffb, 0x2704, 0xa005, 0x0160,
-	0xac00, 0x2068, 0x6908, 0x6810, 0x6912, 0x680a, 0x690c, 0x6814,
-	0x6916, 0x680e, 0x8738, 0x0c88, 0x0005, 0x0003, 0x0009, 0x000f,
-	0x0015, 0x001b, 0x0000, 0x0015, 0x001b, 0x0000, 0x2041, 0x0000,
-	0x780c, 0x0002, 0x21a7, 0x2182, 0x2006, 0x2076, 0x2039, 0x8b74,
-	0x2734, 0x7d10, 0x00c0, 0x6084, 0xa086, 0x0103, 0x1904, 0x2060,
-	0x6114, 0x6018, 0xa105, 0x0120, 0x86ff, 0x11d8, 0x0804, 0x2060,
-	0x8603, 0xa080, 0x8b55, 0x620c, 0x2202, 0x8000, 0x6210, 0x2202,
-	0x080c, 0x1d4e, 0x8630, 0xa68e, 0x000f, 0x0904, 0x20e1, 0x786c,
-	0xa065, 0x1d08, 0x7808, 0xa602, 0x1220, 0xd5ac, 0x1110, 0x263a,
-	0x0005, 0xa682, 0x0003, 0x1a04, 0x20e1, 0x2091, 0x8000, 0x2069,
-	0x0000, 0x6818, 0xd084, 0x11f8, 0x2011, 0x8b55, 0x2204, 0x70c6,
-	0x8210, 0x2204, 0x70ca, 0xd684, 0x1130, 0x8210, 0x2204, 0x70da,
-	0x8210, 0x2204, 0x70de, 0xa685, 0x8020, 0x70c2, 0x681b, 0x0001,
-	0x2091, 0x4080, 0x7810, 0xa084, 0xffcf, 0x7812, 0x2091, 0x8001,
-	0x203b, 0x0000, 0x0005, 0x7810, 0xc0ad, 0x7812, 0x0804, 0x20e1,
-	0x263a, 0x080c, 0x21ad, 0x1904, 0x21c9, 0x786c, 0xa065, 0x1904,
-	0x200b, 0x2091, 0x8000, 0x7810, 0xa084, 0xffcf, 0x86ff, 0x0108,
-	0xc0ad, 0x7812, 0x2091, 0x8001, 0x0804, 0x21c9, 0x2039, 0x8b74,
-	0x2734, 0x7d10, 0x00a0, 0x6084, 0xa086, 0x0103, 0x1904, 0x20cb,
-	0x6114, 0x6018, 0xa105, 0x0120, 0x86ff, 0x11b8, 0x0804, 0x20cb,
-	0xa680, 0x8b55, 0x620c, 0x2202, 0x080c, 0x1d4e, 0x8630, 0xa68e,
-	0x001e, 0x0904, 0x20e1, 0x786c, 0xa065, 0x1d28, 0x7808, 0xa602,
-	0x1220, 0xd5ac, 0x1110, 0x263a, 0x0005, 0xa682, 0x0006, 0x1a04,
-	0x20e1, 0x2091, 0x8000, 0x2069, 0x0000, 0x6818, 0xd084, 0x11f8,
-	0x2011, 0x8b55, 0x2009, 0x8b4e, 0x26a8, 0x211c, 0x2204, 0x201a,
-	0x8108, 0x8210, 0x1f04, 0x20ad, 0xa685, 0x8030, 0x70c2, 0x681b,
-	0x0001, 0x2091, 0x4080, 0x7810, 0xa084, 0xffcf, 0x7812, 0x2091,
-	0x8001, 0xa006, 0x2009, 0x8b75, 0x200a, 0x203a, 0x0005, 0x7810,
-	0xc0ad, 0x7812, 0x00b0, 0x263a, 0x080c, 0x21ad, 0x1904, 0x21c9,
-	0x786c, 0xa065, 0x1904, 0x207b, 0x2091, 0x8000, 0x7810, 0xa084,
-	0xffcf, 0x86ff, 0x0108, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0804,
-	0x21c9, 0x2091, 0x8000, 0x7007, 0x0004, 0x7994, 0x70d4, 0xa102,
-	0x0228, 0x0168, 0x7b90, 0xa302, 0x1150, 0x0010, 0x8002, 0x1138,
-	0x263a, 0x7810, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0005, 0xa184,
-	0xff00, 0x0140, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007,
-	0xa100, 0x0018, 0x8107, 0x8004, 0x8004, 0x7a9c, 0xa210, 0x721a,
-	0x7a98, 0xa006, 0xa211, 0x721e, 0xd4c4, 0x0130, 0x7aa4, 0xa211,
-	0x7222, 0x7aa0, 0xa211, 0x7226, 0x20a1, 0x0030, 0x7003, 0x0000,
-	0x2009, 0x8b54, 0x260a, 0x8109, 0x2198, 0x2104, 0xd084, 0x0108,
-	0x8633, 0xa6b0, 0x0002, 0x26a8, 0x53a6, 0x8603, 0x7012, 0x7007,
-	0x0001, 0x7990, 0x7894, 0x8000, 0xa10a, 0x1208, 0xa006, 0x2028,
+	0x0001, 0x6b0c, 0x6800, 0x70da, 0x0804, 0x13b0, 0x0016, 0x7814,
+	0xd0f4, 0x0138, 0x2001, 0x4007, 0x70db, 0x0000, 0xa18d, 0x0001,
+	0x0050, 0xd0fc, 0x0138, 0x2001, 0x4007, 0x70db, 0x0001, 0xa18d,
+	0x0001, 0x0008, 0xa006, 0x001e, 0x0005, 0x0016, 0x7814, 0xd0f4,
+	0x0138, 0x2001, 0x4007, 0x70db, 0x0000, 0xa18d, 0x0001, 0x0008,
+	0xa006, 0x001e, 0x0005, 0x0016, 0x7814, 0xd0fc, 0x0138, 0x2001,
+	0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0008, 0xa006, 0x001e,
+	0x0005, 0x7112, 0x721a, 0x731e, 0x7810, 0xd0c4, 0x0110, 0x7422,
+	0x7526, 0xac80, 0x0001, 0x8108, 0x810c, 0x81a9, 0x8098, 0x20a1,
+	0x0030, 0x7003, 0x0000, 0x6084, 0x20a2, 0x53a6, 0x7007, 0x0001,
 	0x7974, 0xa184, 0xff00, 0x0140, 0x810f, 0x810c, 0x810c, 0x8004,
 	0x8004, 0x8007, 0xa100, 0x0018, 0x8107, 0x8004, 0x8004, 0x797c,
-	0xa108, 0x7a78, 0xa006, 0xa211, 0xd4c4, 0x0120, 0x7b84, 0xa319,
-	0x7c80, 0xa421, 0x7008, 0xd0fc, 0x0de8, 0xa084, 0x01e0, 0x01d0,
-	0x7d10, 0x2031, 0x8b54, 0x2634, 0x78a8, 0x8000, 0x78aa, 0xd08c,
-	0x1138, 0x7007, 0x0006, 0x7004, 0xd094, 0x1de8, 0x0804, 0x20e3,
-	0x2069, 0x4347, 0x206b, 0x0003, 0x78ac, 0xa085, 0x0300, 0x78ae,
-	0xa006, 0x0048, 0x2030, 0x75d6, 0x2091, 0x4080, 0x7d96, 0x7d10,
-	0xa5ac, 0xffcf, 0x7d12, 0x2091, 0x8001, 0x78aa, 0x7007, 0x0006,
-	0x263a, 0x7003, 0x0001, 0x711a, 0x721e, 0xd5c4, 0x0110, 0x7322,
-	0x7426, 0x0005, 0x6084, 0xa086, 0x0103, 0x11d8, 0x6114, 0x6018,
-	0xa105, 0x11b8, 0x2069, 0x0000, 0x6818, 0xd084, 0x1190, 0x600c,
-	0x70c6, 0x6010, 0x70ca, 0x70c3, 0x8020, 0x681b, 0x0001, 0x2091,
-	0x4080, 0x080c, 0x1d4e, 0x0e04, 0x21a0, 0x786c, 0xa065, 0x1d10,
-	0x0005, 0x0059, 0x1530, 0x786c, 0xa065, 0x19e0, 0x0410, 0x0029,
-	0x1500, 0x786c, 0xa065, 0x1dd8, 0x00e0, 0x6084, 0xa086, 0x0103,
-	0x1168, 0x6018, 0xc0fc, 0x601a, 0xa086, 0x0004, 0x1138, 0x7804,
-	0xd0a4, 0x0120, 0x080c, 0x1d4e, 0xa006, 0x0005, 0x0079, 0x1118,
-	0xa085, 0x0001, 0x0005, 0x00b9, 0x1110, 0x2041, 0x0001, 0x7d10,
-	0x0005, 0x88ff, 0x0110, 0x2091, 0x4080, 0x0005, 0x7b90, 0x7994,
-	0x70d4, 0xa102, 0x1118, 0xa385, 0x0000, 0x0005, 0x0210, 0xa302,
-	0x0005, 0x8002, 0x0005, 0xa184, 0xff00, 0x0140, 0x810f, 0x810c,
-	0x810c, 0x8004, 0x8004, 0x8007, 0xa100, 0x0018, 0x8107, 0x8004,
-	0x8004, 0x7a9c, 0x7b98, 0x7ca4, 0x7da0, 0xa210, 0xa006, 0xa319,
-	0xa421, 0xa529, 0x2009, 0x0018, 0x6028, 0xa005, 0x0110, 0x2009,
-	0x0040, 0x080c, 0x1ab7, 0x01d0, 0x78a8, 0x8000, 0x78aa, 0xd08c,
-	0x1510, 0x6014, 0xd0fc, 0x1118, 0x2069, 0x4340, 0x0010, 0x2069,
-	0x4380, 0x2091, 0x8000, 0x681f, 0x0003, 0x78ab, 0x0000, 0x78ac,
-	0xa085, 0x0300, 0x78ae, 0x2091, 0x8001, 0x0068, 0x78ab, 0x0000,
-	0x080c, 0x1d4e, 0x7990, 0x7894, 0x8000, 0xa10a, 0x1208, 0xa006,
-	0x7896, 0x70d6, 0xa006, 0x2071, 0x0010, 0x2091, 0x8001, 0x0005,
-	0x2138, 0xd7fc, 0x1118, 0x2009, 0x4359, 0x0010, 0x2009, 0x4399,
-	0x2091, 0x8000, 0x200a, 0x00f6, 0x2009, 0x4380, 0x2079, 0x0100,
-	0xd7fc, 0x1120, 0x2009, 0x4340, 0x2079, 0x0200, 0x2104, 0xa086,
-	0x0000, 0x1180, 0xd7fc, 0x1118, 0x2009, 0x4345, 0x0010, 0x2009,
-	0x4385, 0x2104, 0xa005, 0x1130, 0x7830, 0xa084, 0x00c0, 0x1110,
-	0x781b, 0x0052, 0x00fe, 0x0005, 0x2009, 0x0002, 0x2069, 0x4300,
-	0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x22a9, 0x2071, 0x4380,
-	0x2079, 0x0100, 0x2021, 0x45bf, 0x784b, 0x000f, 0x2001, 0x01ff,
-	0x2004, 0xd0fc, 0x0118, 0x2019, 0x3c3b, 0x0030, 0x20a1, 0x012b,
-	0x2019, 0x3c3b, 0xd184, 0x0110, 0x20a1, 0x022b, 0x2304, 0xa005,
-	0x0140, 0x789a, 0x8318, 0x23ac, 0x8318, 0x2398, 0x53a6, 0x3318,
-	0x0ca8, 0x789b, 0x0000, 0x789b, 0x0020, 0x20a9, 0x0010, 0x78af,
-	0x0000, 0x78af, 0x2020, 0x1f04, 0x2287, 0x7003, 0x0000, 0x0016,
-	0xd18c, 0x2009, 0x0000, 0x0108, 0xc1bd, 0x080c, 0x23bd, 0x001e,
-	0x7020, 0xa084, 0x000f, 0xa085, 0x6300, 0x7806, 0x780f, 0x9000,
-	0x7843, 0x00d8, 0x7853, 0x0090, 0x780b, 0x0308, 0x7456, 0x7053,
-	0x0000, 0x8109, 0x0140, 0x2071, 0x4340, 0x2079, 0x0200, 0x2021,
-	0x43bf, 0x0804, 0x2264, 0x0005, 0x0016, 0x2011, 0x0101, 0xd1bc,
-	0x1110, 0x2011, 0x0201, 0xa18c, 0x000f, 0x2204, 0xa084, 0xfff0,
-	0xa105, 0x2012, 0x001e, 0x080c, 0x23bd, 0x0005, 0x2011, 0x0101,
-	0xd3fc, 0x1110, 0x2011, 0x0201, 0x20a9, 0x0009, 0x810b, 0x1f04,
-	0x22ce, 0xa18c, 0x0e00, 0x2204, 0xa084, 0xf1ff, 0xa105, 0x2012,
-	0x0005, 0x2019, 0x0002, 0x2009, 0x0101, 0x20a9, 0x0005, 0x8213,
-	0x1f04, 0x22df, 0xa294, 0x00e0, 0x2104, 0xa084, 0xff1f, 0xa205,
-	0x200a, 0x8319, 0x0118, 0x2009, 0x0201, 0x0c78, 0x0005, 0x2011,
-	0x0101, 0xd3fc, 0x1110, 0x2011, 0x0201, 0x20a9, 0x000c, 0x810b,
-	0x1f04, 0x22f7, 0xa18c, 0xf000, 0x2204, 0xa084, 0x0fff, 0xa105,
-	0x2012, 0x0005, 0x2011, 0x0102, 0xd3fc, 0x1110, 0x2011, 0x0202,
-	0x2204, 0xa084, 0xffcf, 0xa105, 0x2012, 0x0005, 0x00c6, 0x2061,
-	0x0100, 0xd1bc, 0x1110, 0x2061, 0x0200, 0xc1bc, 0x8103, 0x8003,
-	0xa080, 0x0020, 0x609a, 0x62ac, 0x63ac, 0x00ce, 0x0005, 0x00c6,
+	0xa108, 0x7a78, 0xa006, 0xa211, 0x7d10, 0xd5c4, 0x0120, 0x7b84,
+	0xa319, 0x7c80, 0xa421, 0x7008, 0xd0fc, 0x0de8, 0x7003, 0x0001,
+	0x7007, 0x0006, 0x711a, 0x721e, 0x7d10, 0xd5c4, 0x0110, 0x7322,
+	0x7426, 0xa084, 0x01e0, 0x0005, 0x7848, 0xa065, 0x0120, 0x2c04,
+	0x784a, 0x2063, 0x0000, 0x0005, 0x00f6, 0x2079, 0x4500, 0x7848,
+	0x2062, 0x2c00, 0xa005, 0x1110, 0x080c, 0x252b, 0x784a, 0x00fe,
+	0x0005, 0x2011, 0x8f00, 0x7a4a, 0x7bc4, 0x8319, 0x0128, 0xa280,
+	0x0032, 0x2012, 0x2010, 0x0cc8, 0x2013, 0x0000, 0x0005, 0x0016,
+	0x0026, 0xd7fc, 0x1118, 0x2011, 0x4ac0, 0x0010, 0x2011, 0x6ac0,
+	0xa784, 0x0f00, 0x800b, 0xa784, 0x001f, 0x0120, 0x8003, 0x8003,
+	0x8003, 0x8003, 0xa105, 0xa268, 0x002e, 0x001e, 0x0005, 0x0c39,
+	0x2900, 0x682a, 0x2a00, 0x682e, 0x6808, 0xa084, 0xf9ef, 0xa80d,
+	0x690a, 0x00e6, 0xd7fc, 0x1128, 0x2009, 0x4552, 0x2071, 0x4540,
+	0x0020, 0x2009, 0x4592, 0x2071, 0x4580, 0x210c, 0x6804, 0xa005,
+	0x0148, 0xa116, 0x1138, 0x2060, 0x6000, 0x6806, 0x0016, 0x200b,
+	0x0000, 0x0018, 0x2009, 0x0000, 0x0016, 0x6804, 0xa065, 0x0178,
+	0x6000, 0x6806, 0x0421, 0x080c, 0x1d7c, 0x6810, 0x7908, 0x8109,
+	0x790a, 0x8001, 0x6812, 0x1d88, 0x7910, 0xc1a5, 0x7912, 0x001e,
+	0x6902, 0x6906, 0x2d00, 0x2060, 0x080c, 0x2672, 0x00ee, 0x0005,
+	0xa065, 0x0160, 0x2008, 0x609c, 0xa005, 0x0128, 0x2062, 0x609f,
+	0x0000, 0xa065, 0x0cc0, 0x7848, 0x794a, 0x2062, 0x0005, 0x6007,
+	0x0103, 0x608f, 0x0000, 0x20a9, 0x001c, 0xac80, 0x0005, 0x20a0,
+	0x2001, 0x0000, 0x40a4, 0x6828, 0x601a, 0x682c, 0x6022, 0x0005,
+	0x00e6, 0xd7fc, 0x1128, 0x2071, 0x4540, 0x2031, 0x45c0, 0x0020,
+	0x2071, 0x4580, 0x2031, 0x47c0, 0x704c, 0xa08c, 0x0200, 0x1128,
+	0xa608, 0x2d0a, 0x8000, 0x704e, 0xa006, 0x00ee, 0x0005, 0x00f6,
+	0xd7fc, 0x1118, 0x2079, 0x4540, 0x0010, 0x2079, 0x4580, 0x080c,
+	0x1b5f, 0x2091, 0x8000, 0x6804, 0x780a, 0xa065, 0x0904, 0x1c40,
+	0x0030, 0x2c00, 0x780a, 0x2060, 0x6000, 0xa065, 0x05c8, 0x6010,
+	0xa306, 0x1db8, 0x600c, 0xa206, 0x1da0, 0x2c28, 0x7848, 0xac06,
+	0x1108, 0x0458, 0x6804, 0xac06, 0x1140, 0x6000, 0x2060, 0x6806,
+	0xa005, 0x1118, 0x6803, 0x0000, 0x0048, 0x6400, 0x7808, 0x2060,
+	0x6402, 0xa486, 0x0000, 0x1110, 0x2c00, 0x6802, 0x2560, 0x00fe,
+	0x080c, 0x1bc7, 0x00f6, 0x601b, 0x0005, 0x6023, 0x0020, 0x00fe,
+	0x080c, 0x1d7c, 0x00f6, 0x7908, 0x8109, 0x790a, 0x6810, 0x8001,
+	0x6812, 0x1118, 0x7810, 0xc0a5, 0x7812, 0x2001, 0xffff, 0xa005,
+	0x00fe, 0x0005, 0x0076, 0x2700, 0x2039, 0x0000, 0xd0fc, 0x0108,
+	0xc7fd, 0x2041, 0x0021, 0x2049, 0x0004, 0x2051, 0x0008, 0x2091,
+	0x8000, 0x080c, 0x1b77, 0x8738, 0xa784, 0x001f, 0x1dd0, 0xa7bc,
+	0xff00, 0x873f, 0x8738, 0x873f, 0xa784, 0x0f00, 0x1d90, 0x2091,
+	0x8001, 0x007e, 0x0005, 0x786c, 0x2009, 0x8d74, 0x210c, 0xa10d,
+	0x0118, 0xa065, 0x0804, 0x2061, 0x2061, 0x0000, 0x6018, 0xd084,
+	0x11b8, 0x7810, 0xd08c, 0x0130, 0xc08c, 0x7812, 0xc7fc, 0x2069,
+	0x4540, 0x0028, 0xc08d, 0x7812, 0x2069, 0x4580, 0xc7fd, 0x2091,
+	0x8000, 0x681c, 0x681f, 0x0000, 0x2091, 0x8001, 0xa005, 0x1108,
+	0x0005, 0xa08c, 0xfff0, 0x0110, 0x080c, 0x252b, 0x0002, 0x1c9f,
+	0x1ca2, 0x1ca8, 0x1cac, 0x1ca0, 0x1cb0, 0x1ca0, 0x1ca0, 0x1ca0,
+	0x1cb6, 0x1ce2, 0x1ce5, 0x1cea, 0x1cf3, 0x1ca0, 0x1ca0, 0x0005,
+	0x080c, 0x252b, 0x080c, 0x1c42, 0x2001, 0x8001, 0x0804, 0x1cfc,
+	0x2001, 0x8003, 0x0804, 0x1cfc, 0x2001, 0x8004, 0x0804, 0x1cfc,
+	0x080c, 0x1c42, 0x2001, 0x8006, 0x0804, 0x1cfc, 0x2091, 0x8000,
+	0x0076, 0xd7fc, 0x1128, 0x2069, 0x4540, 0x2039, 0x0009, 0x0020,
+	0x2069, 0x4580, 0x2039, 0x0009, 0x6800, 0xa086, 0x0000, 0x0128,
+	0x000e, 0x6f1e, 0x2091, 0x8001, 0x0005, 0x6870, 0x007e, 0xa0bc,
+	0xff00, 0x2041, 0x0021, 0x2049, 0x0004, 0x2051, 0x0010, 0x080c,
+	0x1b77, 0x8738, 0xa784, 0x001f, 0x1dd0, 0x2091, 0x8001, 0x2001,
+	0x800a, 0x00d0, 0x2001, 0x800c, 0x00b8, 0x080c, 0x1c42, 0x2001,
+	0x800d, 0x0090, 0xd7fc, 0x0110, 0x78e4, 0x0008, 0x78e0, 0x70c6,
+	0x2001, 0x800e, 0x0048, 0xd7fc, 0x0110, 0x78ec, 0x0008, 0x78e8,
+	0x70c6, 0x2001, 0x000d, 0x0000, 0x70c2, 0xd7fc, 0x1118, 0x70db,
+	0x0000, 0x0010, 0x70db, 0x0001, 0x2061, 0x0000, 0x601b, 0x0001,
+	0x2091, 0x4080, 0x0005, 0xac80, 0x0001, 0x81ff, 0x0518, 0x2099,
+	0x0030, 0x20a0, 0x700c, 0xa084, 0x07ff, 0x0100, 0x7018, 0x0006,
+	0x701c, 0x0006, 0x7020, 0x0006, 0x7024, 0x0006, 0x7112, 0x81ac,
+	0x721a, 0x731e, 0x7422, 0x7526, 0x7003, 0x0001, 0x7007, 0x0001,
+	0x7008, 0x800b, 0x1ee8, 0x7007, 0x0002, 0xa08c, 0x01e0, 0x1110,
+	0x53a5, 0xa006, 0x7003, 0x0000, 0x7007, 0x0004, 0x000e, 0x7026,
+	0x000e, 0x7022, 0x000e, 0x701e, 0x000e, 0x701a, 0x0005, 0x2011,
+	0x0020, 0x2009, 0x0010, 0x6b0a, 0x6c0e, 0x681f, 0x0201, 0x6803,
+	0xfd20, 0x6807, 0x0038, 0x6a1a, 0x2d00, 0xa0e8, 0x0008, 0xa290,
+	0x0004, 0x8109, 0x1d80, 0x0005, 0x70ec, 0xd0dc, 0x1520, 0x2029,
+	0x0001, 0x7814, 0xd0cc, 0x1160, 0x70ec, 0xd0e4, 0x2019, 0x0c0a,
+	0x2021, 0x000a, 0x1120, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x0070,
+	0x70ec, 0xd0e4, 0x1128, 0x2019, 0x1c0c, 0x2021, 0x000c, 0x0030,
+	0x2019, 0x1c09, 0x2021, 0x0009, 0xa5ad, 0x0200, 0x6b0a, 0x6c0e,
+	0x6d1e, 0x6807, 0x0038, 0x0005, 0x6004, 0x6086, 0x2c08, 0x2063,
+	0x0000, 0x7868, 0xa005, 0x796a, 0x0110, 0x2c02, 0x0008, 0x796e,
+	0x0005, 0x00c6, 0x2061, 0x4500, 0x6887, 0x0103, 0x2d08, 0x206b,
+	0x0000, 0x6068, 0xa005, 0x616a, 0x0110, 0x2d02, 0x0008, 0x616e,
+	0x00ce, 0x0005, 0x2091, 0x8000, 0x2c04, 0x786e, 0xa005, 0x1108,
+	0x786a, 0x2091, 0x8001, 0x609c, 0xa005, 0x0188, 0x00c6, 0x2060,
+	0x2008, 0x609c, 0xa005, 0x0138, 0x2062, 0x609f, 0x0000, 0xa065,
+	0x609c, 0xa005, 0x1dc8, 0x7848, 0x794a, 0x2062, 0x00ce, 0x7848,
+	0x2062, 0x609f, 0x0000, 0xac85, 0x0000, 0x1110, 0x080c, 0x252b,
+	0x784a, 0x0005, 0x20a9, 0x0010, 0xa006, 0x8004, 0x8086, 0x818e,
+	0x1208, 0xa200, 0x1f04, 0x1dc6, 0x8086, 0x818e, 0x0005, 0x0156,
+	0x20a9, 0x0010, 0xa005, 0x01b8, 0xa11a, 0x12a8, 0x8213, 0x818d,
+	0x0228, 0xa11a, 0x1220, 0x1f04, 0x1dd6, 0x0028, 0xa11a, 0x2308,
+	0x8210, 0x1f04, 0x1dd6, 0x0006, 0x3200, 0xa084, 0xefff, 0x2080,
+	0x000e, 0x015e, 0x0005, 0x0006, 0x3200, 0xa085, 0x1000, 0x0cb8,
+	0x7d74, 0x70d0, 0xa506, 0x0904, 0x1ea4, 0x7810, 0x2050, 0x080c,
+	0x1b3c, 0x0904, 0x1ea4, 0xa046, 0x7970, 0x2500, 0x8000, 0xa112,
+	0x2009, 0x0040, 0x1208, 0x0030, 0x72d0, 0xa206, 0x0118, 0x8840,
+	0x2009, 0x0080, 0x00c6, 0x7112, 0x7007, 0x0001, 0x2099, 0x0030,
+	0x20a9, 0x0020, 0xac80, 0x0001, 0x20a0, 0x2061, 0x0000, 0x88ff,
+	0x0110, 0x080c, 0x1b3c, 0x7008, 0xd0fc, 0x0de8, 0x7007, 0x0002,
+	0x2091, 0x8001, 0xa08c, 0x01e0, 0x1538, 0x53a5, 0x8cff, 0x1120,
+	0x88ff, 0x0904, 0x1e91, 0x0050, 0x2c00, 0x788e, 0x20a9, 0x0020,
+	0xac80, 0x0001, 0x20a0, 0x53a5, 0x0804, 0x1e91, 0xa046, 0x7218,
+	0x731c, 0xdac4, 0x0110, 0x7420, 0x7524, 0xa292, 0x0040, 0xa39b,
+	0x0000, 0xa4a3, 0x0000, 0xa5ab, 0x0000, 0x721a, 0x731e, 0xdac4,
+	0x0118, 0x7422, 0x7526, 0xa006, 0x7007, 0x0004, 0x0904, 0x1e91,
+	0x8cff, 0x0110, 0x080c, 0x1b44, 0x00ce, 0x080c, 0x1b44, 0xa046,
+	0x7888, 0x8000, 0x788a, 0xa086, 0x0002, 0x01c0, 0x7a7c, 0x7b78,
+	0xdac4, 0x0110, 0x7c84, 0x7d80, 0x7974, 0x8107, 0x8004, 0x8004,
+	0xa210, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x721a,
+	0x731e, 0xdac4, 0x0588, 0x7422, 0x7526, 0x0470, 0x6014, 0xd0fc,
+	0x1118, 0x2069, 0x4540, 0x0010, 0x2069, 0x4580, 0x2091, 0x8000,
+	0x681f, 0x0002, 0x88ff, 0x0120, 0xa046, 0x788c, 0x2060, 0x0c70,
+	0x788b, 0x0000, 0x78ac, 0xa085, 0x0003, 0x78ae, 0x2091, 0x8001,
+	0x0098, 0x00ce, 0x788b, 0x0000, 0x080c, 0x201c, 0x6004, 0xa084,
+	0x000f, 0x0059, 0x88ff, 0x0130, 0x788c, 0x2060, 0x6004, 0xa084,
+	0x000f, 0x0019, 0x0804, 0x1df0, 0x0005, 0x0002, 0x1eb6, 0x1ed1,
+	0x1eea, 0x1eb6, 0x1ef7, 0x1ec7, 0x1eb6, 0x1eb6, 0x1eb6, 0x1ecf,
+	0x1ee8, 0x1eb6, 0x1eb6, 0x1eb6, 0x1eb6, 0x1eb6, 0x2039, 0x0400,
+	0x78bc, 0xa705, 0x78be, 0x6008, 0xa705, 0x600a, 0x080c, 0x1f33,
+	0x609c, 0x78ba, 0x609f, 0x0000, 0x080c, 0x2008, 0x0005, 0x78bc,
+	0xd0c4, 0x0108, 0x0c58, 0x601c, 0xc0bd, 0x601e, 0x0030, 0x080c,
+	0x2046, 0x78bc, 0xd0c4, 0x0108, 0x0c08, 0x78bf, 0x0000, 0x6004,
+	0x8007, 0xa084, 0x00ff, 0x78b2, 0x8001, 0x0138, 0x080c, 0x1f33,
+	0x0120, 0x78bc, 0xc0c5, 0x78be, 0x0010, 0x0804, 0x1f4e, 0x0005,
+	0x080c, 0x2043, 0x78bc, 0xa08c, 0x0e00, 0x1110, 0xd0c4, 0x1108,
+	0x0828, 0x080c, 0x1f33, 0x1110, 0x0804, 0x1f4e, 0x0005, 0x78bc,
+	0xd0c4, 0x0110, 0x0804, 0x1eb6, 0x78bf, 0x0000, 0x6714, 0x2011,
+	0x0001, 0x22a8, 0x6018, 0xa084, 0x00ff, 0xa005, 0x0188, 0xa7bc,
+	0xff00, 0x20a9, 0x0020, 0xa08e, 0x0001, 0x0150, 0xa7bc, 0x8000,
+	0x2011, 0x0002, 0x20a9, 0x0100, 0xa08e, 0x0002, 0x0108, 0x00c0,
+	0x080c, 0x1b5f, 0x2d00, 0x2091, 0x8000, 0x682b, 0x0000, 0x682f,
+	0x0000, 0x6808, 0xa084, 0xffde, 0x680a, 0xade8, 0x0010, 0x2091,
+	0x8001, 0x1f04, 0x1f1b, 0x8211, 0x0118, 0x20a9, 0x0100, 0x0c58,
+	0x080c, 0x1b44, 0x0005, 0x609f, 0x0000, 0x78b4, 0xa06d, 0x2c00,
+	0x78b6, 0x1110, 0x78ba, 0x0038, 0x689e, 0x2d00, 0x6002, 0x78b8,
+	0xad06, 0x1108, 0x6002, 0x78b0, 0x8001, 0x78b2, 0x1130, 0x78bc,
+	0xc0c4, 0x78be, 0x78b8, 0x2060, 0xa006, 0x0005, 0x00e6, 0xa02e,
+	0x2530, 0x7dba, 0x7db6, 0x65ae, 0x65b2, 0x601c, 0x60a2, 0x2048,
+	0xa984, 0xe1ff, 0x601e, 0xa984, 0x0060, 0x0110, 0x080c, 0x3f66,
+	0x6596, 0x65a6, 0x669a, 0x66aa, 0x6714, 0x2071, 0x4580, 0xd7fc,
+	0x1110, 0x2071, 0x4540, 0xa784, 0x0f00, 0x800b, 0xa784, 0x001f,
+	0x0120, 0x8003, 0x8003, 0x8003, 0x8003, 0xa105, 0x71c0, 0xa168,
+	0x2700, 0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0x71c4,
+	0xa100, 0x60c2, 0x2091, 0x8000, 0x7814, 0xd0c4, 0x0138, 0xd7fc,
+	0x1118, 0xd0f4, 0x1140, 0x0010, 0xd0fc, 0x1128, 0x6e08, 0xd684,
+	0x01f0, 0xd9fc, 0x11e0, 0x2091, 0x8001, 0x080c, 0x1bc7, 0x2091,
+	0x8000, 0x080c, 0x1d7c, 0x2091, 0x8001, 0x7814, 0xd0c4, 0x0904,
+	0x2006, 0xd7fc, 0x1120, 0xd0f4, 0x1130, 0x0804, 0x2006, 0xd0fc,
+	0x1110, 0x0804, 0x2006, 0x601b, 0x0021, 0x0804, 0x2006, 0x6024,
+	0xa096, 0x0001, 0x1110, 0x8000, 0x6026, 0x6a10, 0x6814, 0xa202,
+	0x0268, 0x0160, 0x2091, 0x8001, 0x2039, 0x0200, 0x609c, 0x78ba,
+	0x609f, 0x0000, 0x080c, 0x2008, 0x0804, 0x2006, 0x2c08, 0xd9fc,
+	0x01f0, 0x6800, 0xa065, 0x01d8, 0x6a04, 0x7000, 0xa084, 0x0002,
+	0x0168, 0x7048, 0xa206, 0x1150, 0x6b04, 0x2160, 0x2304, 0x6002,
+	0xa005, 0x1108, 0x6902, 0x2260, 0x6102, 0x0098, 0x2d00, 0x2060,
+	0x080c, 0x2672, 0x6e08, 0x2160, 0x6202, 0x6906, 0x0050, 0x6800,
+	0x6902, 0xa065, 0x0110, 0x6102, 0x0008, 0x6906, 0x2160, 0x6003,
+	0x0000, 0x2160, 0xd9fc, 0x0118, 0xa6b4, 0xfffc, 0x6e0a, 0x6810,
+	0x7d08, 0x8528, 0x7d0a, 0x8000, 0x6812, 0x2091, 0x8001, 0xd6b4,
+	0x0128, 0xa6b6, 0x0040, 0x6e0a, 0x080c, 0x1bd8, 0x00ee, 0x0005,
+	0x6008, 0xa705, 0x600a, 0x2091, 0x8000, 0x080c, 0x1d7c, 0x2091,
+	0x8001, 0x78b8, 0xa065, 0x0128, 0x609c, 0x78ba, 0x609f, 0x0000,
+	0x0c78, 0x78b6, 0x78ba, 0x0005, 0x7970, 0x7874, 0x2818, 0xd384,
+	0x0118, 0x8000, 0xa112, 0x0220, 0x8000, 0xa112, 0x1278, 0xc384,
+	0x7a7c, 0x721a, 0x7a78, 0x721e, 0xdac4, 0x0120, 0x7a84, 0x7222,
+	0x7a80, 0x7226, 0xa006, 0xd384, 0x0108, 0x8000, 0x7876, 0x70d2,
+	0x781c, 0xa005, 0x0138, 0x8001, 0x781e, 0x1120, 0x0e04, 0x2042,
+	0x2091, 0x4080, 0x0005, 0x2039, 0x2058, 0x0010, 0x2039, 0x205e,
+	0x2704, 0xa005, 0x0160, 0xac00, 0x2068, 0x6908, 0x6810, 0x6912,
+	0x680a, 0x690c, 0x6814, 0x6916, 0x680e, 0x8738, 0x0c88, 0x0005,
+	0x0003, 0x0009, 0x000f, 0x0015, 0x001b, 0x0000, 0x0015, 0x001b,
+	0x0000, 0x2041, 0x0000, 0x780c, 0x0002, 0x220a, 0x21e5, 0x2069,
+	0x20d9, 0x2039, 0x8d74, 0x2734, 0x7d10, 0x00c0, 0x6084, 0xa086,
+	0x0103, 0x1904, 0x20c3, 0x6114, 0x6018, 0xa105, 0x0120, 0x86ff,
+	0x11d8, 0x0804, 0x20c3, 0x8603, 0xa080, 0x8d55, 0x620c, 0x2202,
+	0x8000, 0x6210, 0x2202, 0x080c, 0x1d9a, 0x8630, 0xa68e, 0x000f,
+	0x0904, 0x2144, 0x786c, 0xa065, 0x1d08, 0x7808, 0xa602, 0x1220,
+	0xd5ac, 0x1110, 0x263a, 0x0005, 0xa682, 0x0003, 0x1a04, 0x2144,
+	0x2091, 0x8000, 0x2069, 0x0000, 0x6818, 0xd084, 0x11f8, 0x2011,
+	0x8d55, 0x2204, 0x70c6, 0x8210, 0x2204, 0x70ca, 0xd684, 0x1130,
+	0x8210, 0x2204, 0x70da, 0x8210, 0x2204, 0x70de, 0xa685, 0x8020,
+	0x70c2, 0x681b, 0x0001, 0x2091, 0x4080, 0x7810, 0xa084, 0xffcf,
+	0x7812, 0x2091, 0x8001, 0x203b, 0x0000, 0x0005, 0x7810, 0xc0ad,
+	0x7812, 0x0804, 0x2144, 0x263a, 0x080c, 0x2210, 0x1904, 0x222c,
+	0x786c, 0xa065, 0x1904, 0x206e, 0x2091, 0x8000, 0x7810, 0xa084,
+	0xffcf, 0x86ff, 0x0108, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0804,
+	0x222c, 0x2039, 0x8d74, 0x2734, 0x7d10, 0x00a0, 0x6084, 0xa086,
+	0x0103, 0x1904, 0x212e, 0x6114, 0x6018, 0xa105, 0x0120, 0x86ff,
+	0x11b8, 0x0804, 0x212e, 0xa680, 0x8d55, 0x620c, 0x2202, 0x080c,
+	0x1d9a, 0x8630, 0xa68e, 0x001e, 0x0904, 0x2144, 0x786c, 0xa065,
+	0x1d28, 0x7808, 0xa602, 0x1220, 0xd5ac, 0x1110, 0x263a, 0x0005,
+	0xa682, 0x0006, 0x1a04, 0x2144, 0x2091, 0x8000, 0x2069, 0x0000,
+	0x6818, 0xd084, 0x11f8, 0x2011, 0x8d55, 0x2009, 0x8d4e, 0x26a8,
+	0x211c, 0x2204, 0x201a, 0x8108, 0x8210, 0x1f04, 0x2110, 0xa685,
+	0x8030, 0x70c2, 0x681b, 0x0001, 0x2091, 0x4080, 0x7810, 0xa084,
+	0xffcf, 0x7812, 0x2091, 0x8001, 0xa006, 0x2009, 0x8d75, 0x200a,
+	0x203a, 0x0005, 0x7810, 0xc0ad, 0x7812, 0x00b0, 0x263a, 0x080c,
+	0x2210, 0x1904, 0x222c, 0x786c, 0xa065, 0x1904, 0x20de, 0x2091,
+	0x8000, 0x7810, 0xa084, 0xffcf, 0x86ff, 0x0108, 0xc0ad, 0x7812,
+	0x2091, 0x8001, 0x0804, 0x222c, 0x2091, 0x8000, 0x7007, 0x0004,
+	0x7994, 0x70d4, 0xa102, 0x0228, 0x0168, 0x7b90, 0xa302, 0x1150,
+	0x0010, 0x8002, 0x1138, 0x263a, 0x7810, 0xc0ad, 0x7812, 0x2091,
+	0x8001, 0x0005, 0xa184, 0xff00, 0x0140, 0x810f, 0x810c, 0x810c,
+	0x8004, 0x8004, 0x8007, 0xa100, 0x0018, 0x8107, 0x8004, 0x8004,
+	0x7a9c, 0xa210, 0x721a, 0x7a98, 0xa006, 0xa211, 0x721e, 0xd4c4,
+	0x0130, 0x7aa4, 0xa211, 0x7222, 0x7aa0, 0xa211, 0x7226, 0x20a1,
+	0x0030, 0x7003, 0x0000, 0x2009, 0x8d54, 0x260a, 0x8109, 0x2198,
+	0x2104, 0xd084, 0x0108, 0x8633, 0xa6b0, 0x0002, 0x26a8, 0x53a6,
+	0x8603, 0x7012, 0x7007, 0x0001, 0x7990, 0x7894, 0x8000, 0xa10a,
+	0x1208, 0xa006, 0x2028, 0x7974, 0xa184, 0xff00, 0x0140, 0x810f,
+	0x810c, 0x810c, 0x8004, 0x8004, 0x8007, 0xa100, 0x0018, 0x8107,
+	0x8004, 0x8004, 0x797c, 0xa108, 0x7a78, 0xa006, 0xa211, 0xd4c4,
+	0x0120, 0x7b84, 0xa319, 0x7c80, 0xa421, 0x7008, 0xd0fc, 0x0de8,
+	0xa084, 0x01e0, 0x01d0, 0x7d10, 0x2031, 0x8d54, 0x2634, 0x78a8,
+	0x8000, 0x78aa, 0xd08c, 0x1138, 0x7007, 0x0006, 0x7004, 0xd094,
+	0x1de8, 0x0804, 0x2146, 0x2069, 0x4547, 0x206b, 0x0003, 0x78ac,
+	0xa085, 0x0300, 0x78ae, 0xa006, 0x0048, 0x2030, 0x75d6, 0x2091,
+	0x4080, 0x7d96, 0x7d10, 0xa5ac, 0xffcf, 0x7d12, 0x2091, 0x8001,
+	0x78aa, 0x7007, 0x0006, 0x263a, 0x7003, 0x0001, 0x711a, 0x721e,
+	0xd5c4, 0x0110, 0x7322, 0x7426, 0x0005, 0x6084, 0xa086, 0x0103,
+	0x11d8, 0x6114, 0x6018, 0xa105, 0x11b8, 0x2069, 0x0000, 0x6818,
+	0xd084, 0x1190, 0x600c, 0x70c6, 0x6010, 0x70ca, 0x70c3, 0x8020,
+	0x681b, 0x0001, 0x2091, 0x4080, 0x080c, 0x1d9a, 0x0e04, 0x2203,
+	0x786c, 0xa065, 0x1d10, 0x0005, 0x0059, 0x1530, 0x786c, 0xa065,
+	0x19e0, 0x0410, 0x0029, 0x1500, 0x786c, 0xa065, 0x1dd8, 0x00e0,
+	0x6084, 0xa086, 0x0103, 0x1168, 0x6018, 0xc0fc, 0x601a, 0xa086,
+	0x0004, 0x1138, 0x7804, 0xd0a4, 0x0120, 0x080c, 0x1d9a, 0xa006,
+	0x0005, 0x0079, 0x1118, 0xa085, 0x0001, 0x0005, 0x00b9, 0x1110,
+	0x2041, 0x0001, 0x7d10, 0x0005, 0x88ff, 0x0110, 0x2091, 0x4080,
+	0x0005, 0x7b90, 0x7994, 0x70d4, 0xa102, 0x1118, 0xa385, 0x0000,
+	0x0005, 0x0210, 0xa302, 0x0005, 0x8002, 0x0005, 0xa184, 0xff00,
+	0x0140, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007, 0xa100,
+	0x0018, 0x8107, 0x8004, 0x8004, 0x7a9c, 0x7b98, 0x7ca4, 0x7da0,
+	0xa210, 0xa006, 0xa319, 0xa421, 0xa529, 0x2009, 0x0018, 0x6028,
+	0xa005, 0x0110, 0x2009, 0x0040, 0x080c, 0x1af9, 0x01d0, 0x78a8,
+	0x8000, 0x78aa, 0xd08c, 0x1510, 0x6014, 0xd0fc, 0x1118, 0x2069,
+	0x4540, 0x0010, 0x2069, 0x4580, 0x2091, 0x8000, 0x681f, 0x0003,
+	0x78ab, 0x0000, 0x78ac, 0xa085, 0x0300, 0x78ae, 0x2091, 0x8001,
+	0x0068, 0x78ab, 0x0000, 0x080c, 0x1d9a, 0x7990, 0x7894, 0x8000,
+	0xa10a, 0x1208, 0xa006, 0x7896, 0x70d6, 0xa006, 0x2071, 0x0010,
+	0x2091, 0x8001, 0x0005, 0x2138, 0xd7fc, 0x1118, 0x2009, 0x4558,
+	0x0010, 0x2009, 0x4598, 0x2091, 0x8000, 0x200a, 0x00f6, 0x2009,
+	0x4580, 0x2079, 0x0100, 0xd7fc, 0x1120, 0x2009, 0x4540, 0x2079,
+	0x0200, 0x2104, 0xa086, 0x0000, 0x1180, 0xd7fc, 0x1118, 0x2009,
+	0x4545, 0x0010, 0x2009, 0x4585, 0x2104, 0xa005, 0x1130, 0x7830,
+	0xa084, 0x00c0, 0x1110, 0x781b, 0x0052, 0x00fe, 0x0005, 0x2009,
+	0x0002, 0x2069, 0x4500, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904,
+	0x230c, 0x2071, 0x4580, 0x2079, 0x0100, 0x2021, 0x47bf, 0x784b,
+	0x000f, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x0118, 0x2019, 0x3dc2,
+	0x0030, 0x20a1, 0x012b, 0x2019, 0x3dc2, 0xd184, 0x0110, 0x20a1,
+	0x022b, 0x2304, 0xa005, 0x0140, 0x789a, 0x8318, 0x23ac, 0x8318,
+	0x2398, 0x53a6, 0x3318, 0x0ca8, 0x789b, 0x0000, 0x789b, 0x0020,
+	0x20a9, 0x0010, 0x78af, 0x0000, 0x78af, 0x2020, 0x1f04, 0x22ea,
+	0x7003, 0x0000, 0x0016, 0xd18c, 0x2009, 0x0000, 0x0108, 0xc1bd,
+	0x080c, 0x2422, 0x001e, 0x7020, 0xa084, 0x000f, 0xa085, 0x6300,
+	0x7806, 0x780f, 0x9000, 0x7843, 0x00d8, 0x7853, 0x0090, 0x780b,
+	0x2f08, 0x7452, 0x704f, 0x0000, 0x8109, 0x0140, 0x2071, 0x4540,
+	0x2079, 0x0200, 0x2021, 0x45bf, 0x0804, 0x22c7, 0x080c, 0x24dc,
+	0x0005, 0x0016, 0x2011, 0x0101, 0xd1bc, 0x1110, 0x2011, 0x0201,
+	0xa18c, 0x000f, 0x2204, 0xa084, 0xfff0, 0xa105, 0x2012, 0x001e,
+	0x080c, 0x2422, 0x0005, 0x2011, 0x0101, 0xd3fc, 0x1110, 0x2011,
+	0x0201, 0x20a9, 0x0009, 0x810b, 0x1f04, 0x2333, 0xa18c, 0x0e00,
+	0x2204, 0xa084, 0xf1ff, 0xa105, 0x2012, 0x0005, 0x2019, 0x0002,
+	0x2009, 0x0101, 0x20a9, 0x0005, 0x8213, 0x1f04, 0x2344, 0xa294,
+	0x00e0, 0x2104, 0xa084, 0xff1f, 0xa205, 0x200a, 0x8319, 0x0118,
+	0x2009, 0x0201, 0x0c78, 0x0005, 0x2011, 0x0101, 0xd3fc, 0x1110,
+	0x2011, 0x0201, 0x20a9, 0x000c, 0x810b, 0x1f04, 0x235c, 0xa18c,
+	0xf000, 0x2204, 0xa084, 0x0fff, 0xa105, 0x2012, 0x0005, 0x2011,
+	0x0102, 0xd3fc, 0x1110, 0x2011, 0x0202, 0x2204, 0xa084, 0xf0cf,
+	0xa105, 0x2012, 0x0005, 0x00c6, 0x2061, 0x0100, 0xd1bc, 0x1110,
+	0x2061, 0x0200, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0020, 0x609a,
+	0x62ac, 0x63ac, 0x00ce, 0x0005, 0x00c6, 0x2061, 0x0100, 0xd1bc,
+	0x1110, 0x2061, 0x0200, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0022,
+	0x609a, 0x60a4, 0xa084, 0xffdf, 0x60ae, 0x00ce, 0x0005, 0x00c6,
 	0x2061, 0x0100, 0xd1bc, 0x1110, 0x2061, 0x0200, 0xc1bc, 0x8103,
-	0x8003, 0xa080, 0x0022, 0x609a, 0x60a4, 0xa084, 0xffdf, 0x60ae,
-	0x00ce, 0x0005, 0x00c6, 0x2061, 0x0100, 0xd1bc, 0x1110, 0x2061,
-	0x0200, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0020, 0x609a, 0x60a4,
-	0xa28c, 0x0020, 0x0118, 0xc2ac, 0xa39d, 0x4000, 0xc3ec, 0xd3b4,
-	0x1108, 0xc3ed, 0x62ae, 0x2010, 0x60a4, 0x63ae, 0x2018, 0x00ce,
-	0x0005, 0x2091, 0x8000, 0x00c6, 0x00e6, 0x6818, 0xa005, 0x0904,
-	0x23a1, 0xd1fc, 0x0118, 0x2061, 0x8ad0, 0x0010, 0x2061, 0x89c0,
-	0x080c, 0x23a9, 0x0538, 0x20a9, 0x0101, 0xd1fc, 0x0118, 0x2061,
-	0x89d0, 0x0010, 0x2061, 0x88c0, 0x00c6, 0x04d9, 0x0128, 0x00ce,
-	0x8c60, 0x1f04, 0x236c, 0x0468, 0x000e, 0xd1fc, 0x0128, 0xa082,
-	0x89d0, 0x2071, 0x4380, 0x0020, 0xa082, 0x88c0, 0x2071, 0x4340,
-	0x707a, 0x7176, 0x2001, 0x0004, 0x7066, 0x7083, 0x000f, 0x080c,
-	0x2228, 0x00a0, 0xd1fc, 0x1118, 0x2071, 0x4340, 0x0010, 0x2071,
-	0x4380, 0x6020, 0xc0dd, 0x6022, 0x7176, 0x2c00, 0x707e, 0x2001,
-	0x0006, 0x7066, 0x7083, 0x000f, 0x080c, 0x2228, 0x2001, 0x0000,
-	0x0010, 0x2001, 0x0001, 0x2091, 0x8001, 0xa005, 0x00ee, 0x00ce,
-	0x0005, 0x2c04, 0xa005, 0x0170, 0x2060, 0x6010, 0xa306, 0x1140,
-	0x600c, 0xa206, 0x1128, 0x6014, 0xa106, 0x1110, 0xa006, 0x0020,
-	0x6000, 0x0c80, 0xa085, 0x0001, 0x0005, 0x00f6, 0x00e6, 0x0016,
-	0x2079, 0x4380, 0x2071, 0x0100, 0xd1bc, 0x1120, 0x2079, 0x4340,
-	0x2071, 0x0200, 0x7920, 0xa18c, 0x000f, 0x70ec, 0xd0c4, 0x1110,
-	0x001e, 0x0060, 0x810b, 0x810b, 0x810b, 0x810b, 0x000e, 0xa18d,
-	0x0800, 0xd0bc, 0x1110, 0xa18d, 0x0f00, 0x2104, 0x00ee, 0x00fe,
-	0x0005, 0x00e6, 0x2001, 0x4301, 0x2004, 0xd0ac, 0x1904, 0x2439,
-	0x68e4, 0xd0ac, 0x0904, 0x2439, 0xa084, 0x0006, 0x1904, 0x2439,
-	0x6014, 0xd0fc, 0x1118, 0x2071, 0x47c0, 0x0010, 0x2071, 0x4840,
-	0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xae70, 0x7004,
-	0xa084, 0x000a, 0x15b0, 0x7108, 0xa194, 0xff00, 0x0590, 0xa18c,
-	0x00ff, 0x2001, 0x000a, 0xa106, 0x01a8, 0x2001, 0x000c, 0xa106,
-	0x01a0, 0x2001, 0x0012, 0xa106, 0x0198, 0x2001, 0x0014, 0xa106,
-	0x0190, 0x2001, 0x0019, 0xa106, 0x0188, 0x2001, 0x0032, 0xa106,
-	0x0180, 0x0090, 0x2009, 0x000c, 0x0088, 0x2009, 0x0012, 0x0070,
-	0x2009, 0x0014, 0x0058, 0x2009, 0x0019, 0x0040, 0x2009, 0x0020,
-	0x0028, 0x2009, 0x003f, 0x0010, 0x2011, 0x0000, 0x2100, 0xa205,
-	0x700a, 0x00ee, 0x0005, 0x0e04, 0x243b, 0x2091, 0x8000, 0x2071,
+	0x8003, 0xa080, 0x0020, 0x609a, 0x60a4, 0xa28c, 0x0020, 0x0118,
+	0xc2ac, 0xa39d, 0x4000, 0xc3ec, 0xd3b4, 0x1108, 0xc3ed, 0x62ae,
+	0x2010, 0x60a4, 0x63ae, 0x2018, 0x00ce, 0x0005, 0x2091, 0x8000,
+	0x00c6, 0x00e6, 0x6818, 0xa005, 0x0904, 0x2406, 0xd1fc, 0x0118,
+	0x2061, 0x8cd0, 0x0010, 0x2061, 0x8bc0, 0x080c, 0x240e, 0x0538,
+	0x20a9, 0x0101, 0xd1fc, 0x0118, 0x2061, 0x8bd0, 0x0010, 0x2061,
+	0x8ac0, 0x00c6, 0x04d9, 0x0128, 0x00ce, 0x8c60, 0x1f04, 0x23d1,
+	0x0468, 0x000e, 0xd1fc, 0x0128, 0xa082, 0x8bd0, 0x2071, 0x4580,
+	0x0020, 0xa082, 0x8ac0, 0x2071, 0x4540, 0x7076, 0x7172, 0x2001,
+	0x0004, 0x7062, 0x707f, 0x000f, 0x080c, 0x228b, 0x00a0, 0xd1fc,
+	0x1118, 0x2071, 0x4540, 0x0010, 0x2071, 0x4580, 0x6020, 0xc0dd,
+	0x6022, 0x7172, 0x2c00, 0x707a, 0x2001, 0x0006, 0x7062, 0x707f,
+	0x000f, 0x080c, 0x228b, 0x2001, 0x0000, 0x0010, 0x2001, 0x0001,
+	0x2091, 0x8001, 0xa005, 0x00ee, 0x00ce, 0x0005, 0x2c04, 0xa005,
+	0x0170, 0x2060, 0x6010, 0xa306, 0x1140, 0x600c, 0xa206, 0x1128,
+	0x6014, 0xa106, 0x1110, 0xa006, 0x0020, 0x6000, 0x0c80, 0xa085,
+	0x0001, 0x0005, 0x00f6, 0x00e6, 0x0016, 0x2079, 0x4580, 0x2071,
+	0x0100, 0xd1bc, 0x1120, 0x2079, 0x4540, 0x2071, 0x0200, 0x7920,
+	0xa18c, 0x000f, 0x70ec, 0xd0c4, 0x1110, 0x001e, 0x0060, 0x810b,
+	0x810b, 0x810b, 0x810b, 0x000e, 0xa18d, 0x0800, 0xd0bc, 0x1110,
+	0xa18d, 0x0f00, 0x2104, 0x00ee, 0x00fe, 0x0005, 0x2001, 0x4501,
+	0x2004, 0xd0ac, 0x1138, 0x68e4, 0xd0ac, 0x0120, 0xa084, 0x0006,
+	0x1108, 0x0009, 0x0005, 0x6014, 0x00e6, 0x0036, 0x2018, 0x2071,
+	0x4a40, 0xd0fc, 0x1110, 0x2071, 0x49c0, 0x8007, 0xa084, 0x000f,
+	0x8003, 0x8003, 0x8003, 0xae70, 0x7004, 0xa084, 0x000a, 0x1904,
+	0x24d9, 0x7108, 0xa194, 0xff00, 0x0904, 0x24d9, 0xa18c, 0x00ff,
+	0x701c, 0xa084, 0xff00, 0x01c0, 0x7004, 0xa085, 0x003a, 0x7006,
+	0x2001, 0x0009, 0xa102, 0x16d8, 0x2001, 0x000a, 0xa102, 0x16d0,
+	0x2001, 0x000c, 0xa102, 0x16c8, 0x701c, 0xa084, 0x00ff, 0x701e,
+	0x7004, 0xa084, 0xffdf, 0x7006, 0x2001, 0x000a, 0xa106, 0x01a8,
+	0x2001, 0x000c, 0xa106, 0x01a0, 0x2001, 0x0012, 0xa106, 0x0198,
+	0x2001, 0x0014, 0xa106, 0x0190, 0x2001, 0x0019, 0xa106, 0x0188,
+	0x2001, 0x0032, 0xa106, 0x0180, 0x00d8, 0x2009, 0x000c, 0x00d0,
+	0x2009, 0x0012, 0x00b8, 0x2009, 0x0014, 0x00a0, 0x2009, 0x0019,
+	0x0088, 0x2009, 0x0020, 0x0070, 0x2009, 0x003f, 0x0058, 0x2009,
+	0x000a, 0x0040, 0x2009, 0x000c, 0x0028, 0x2009, 0x0019, 0x0010,
+	0x2011, 0x0000, 0x2100, 0xa205, 0x700a, 0x7004, 0xa085, 0x000a,
+	0x7006, 0x2071, 0x4500, 0x7004, 0xd0bc, 0x0158, 0xd3fc, 0x1120,
+	0x73ea, 0x2071, 0x4540, 0x0018, 0x73ee, 0x2071, 0x4580, 0x701f,
+	0x800f, 0x003e, 0x00ee, 0x0005, 0x2001, 0x01ff, 0x2004, 0xd0fc,
+	0x11d0, 0x2001, 0x04fd, 0x2004, 0xa082, 0x0005, 0x12a0, 0x2071,
+	0x0200, 0x71ec, 0xa18c, 0x1c00, 0x810f, 0x810c, 0x810c, 0x2079,
+	0x0100, 0x78ec, 0xa084, 0x1c00, 0x8007, 0x8004, 0x8004, 0xa105,
+	0xa08a, 0x0007, 0x0208, 0x0005, 0x0002, 0x252a, 0x2511, 0x252a,
+	0x2511, 0x2504, 0x251e, 0x2504, 0x7008, 0xa084, 0xc3ff, 0xa085,
+	0x3000, 0x700a, 0x7808, 0xa084, 0xc3ff, 0xa085, 0x3000, 0x780a,
+	0x0005, 0x7008, 0xa084, 0xc3ff, 0xa085, 0x2000, 0x700a, 0x7808,
+	0xa084, 0xc3ff, 0xa085, 0x2000, 0x780a, 0x0005, 0x7008, 0xa084,
+	0xc3ff, 0xa085, 0x0c00, 0x700a, 0x7808, 0xa084, 0xc3ff, 0xa085,
+	0x0c00, 0x780a, 0x0005, 0x0e04, 0x252b, 0x2091, 0x8000, 0x2071,
 	0x0000, 0x0006, 0x7018, 0xd084, 0x1de8, 0x000e, 0x2071, 0x0010,
-	0x70ca, 0x000e, 0x70c6, 0x70c3, 0x8002, 0x70db, 0x0a01, 0x70df,
-	0x0013, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0cf8,
-	0x7f3c, 0x7e58, 0x7c30, 0x7d38, 0x78a0, 0x708e, 0x7592, 0x7496,
-	0x769a, 0x779e, 0xa594, 0x003f, 0xd4f4, 0x0138, 0xd7bc, 0x1128,
-	0xa784, 0x007d, 0x1904, 0x3ace, 0x0871, 0xa49c, 0x000f, 0xa382,
+	0x70ca, 0x000e, 0x70c6, 0x70c3, 0x8002, 0x70db, 0x0a04, 0x70df,
+	0x0008, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0cf8,
+	0x7f3c, 0x7e58, 0x7c30, 0x7d38, 0x78a0, 0x708a, 0x758e, 0x7492,
+	0x7696, 0x779a, 0xa594, 0x003f, 0xd4f4, 0x0138, 0xd7bc, 0x1128,
+	0xa784, 0x007d, 0x1904, 0x3c3a, 0x0871, 0xa49c, 0x000f, 0xa382,
 	0x0004, 0x0320, 0xa3a6, 0x0007, 0x1930, 0x2418, 0x8507, 0xa084,
-	0x000f, 0x0002, 0x2a4f, 0x2b10, 0x2b38, 0x2d71, 0x30cc, 0x3112,
-	0x31a7, 0x3220, 0x32db, 0x33a6, 0x248d, 0x248a, 0x285b, 0x295c,
-	0x30a0, 0x248a, 0x080c, 0x243b, 0x0005, 0xa006, 0x0038, 0x7808,
-	0xc08d, 0x780a, 0xa006, 0x7002, 0x704e, 0x7046, 0x70d2, 0x7060,
-	0xa005, 0x1904, 0x25d9, 0x7064, 0xa084, 0x0007, 0x0002, 0x24a7,
-	0x2513, 0x251b, 0x2524, 0x252d, 0x25bf, 0x2536, 0x2513, 0x7830,
-	0xd0bc, 0x1d10, 0x71d4, 0xd1b4, 0x1904, 0x24f0, 0x70a4, 0xa086,
-	0x0001, 0x09d0, 0x70b4, 0xa06d, 0x6800, 0xa065, 0xa055, 0x789b,
-	0x0080, 0x6b0c, 0x7baa, 0x6808, 0xa045, 0x6d10, 0x6804, 0xa06d,
-	0xa05d, 0xa886, 0x0001, 0x0118, 0x69bc, 0x7daa, 0x79aa, 0x68c0,
-	0xa04d, 0x6e1c, 0x2001, 0x0010, 0x0804, 0x270a, 0x7060, 0xa005,
-	0x1904, 0x248c, 0x00c6, 0x00d6, 0x70b4, 0xa06d, 0x6800, 0xa065,
+	0x000f, 0x0002, 0x2b40, 0x2c01, 0x2c29, 0x2e64, 0x31f1, 0x3243,
+	0x32e8, 0x3361, 0x341f, 0x34f6, 0x257d, 0x257a, 0x294d, 0x2a4d,
+	0x31c5, 0x257a, 0x080c, 0x252b, 0x0005, 0xa006, 0x0038, 0x7808,
+	0xc08d, 0x780a, 0xa006, 0x7002, 0x704a, 0x7042, 0x70ce, 0x705c,
+	0xa005, 0x1904, 0x26cb, 0x7060, 0xa084, 0x0007, 0x0002, 0x2597,
+	0x2605, 0x260d, 0x2616, 0x261f, 0x26b1, 0x2628, 0x2605, 0x7830,
+	0xd0bc, 0x1d10, 0x71d0, 0xd1bc, 0x19f8, 0xd1b4, 0x1904, 0x25e2,
+	0x70a0, 0xa086, 0x0001, 0x09c0, 0x70b0, 0xa06d, 0x6800, 0xa065,
 	0xa055, 0x789b, 0x0080, 0x6b0c, 0x7baa, 0x6808, 0xa045, 0x6d10,
 	0x6804, 0xa06d, 0xa05d, 0xa886, 0x0001, 0x0118, 0x69bc, 0x7daa,
-	0x79aa, 0x68c0, 0xa04d, 0x6e1c, 0x2001, 0x0020, 0x0804, 0x270a,
-	0x080c, 0x3a8d, 0x1904, 0x248c, 0x781b, 0x0068, 0x70bc, 0xa06d,
+	0x79aa, 0x68c0, 0xa04d, 0x6e1c, 0x2001, 0x0010, 0x0804, 0x27fc,
+	0x705c, 0xa005, 0x1904, 0x257c, 0x00c6, 0x00d6, 0x70b0, 0xa06d,
+	0x6800, 0xa065, 0xa055, 0x789b, 0x0080, 0x6b0c, 0x7baa, 0x6808,
+	0xa045, 0x6d10, 0x6804, 0xa06d, 0xa05d, 0xa886, 0x0001, 0x0118,
+	0x69bc, 0x7daa, 0x79aa, 0x68c0, 0xa04d, 0x6e1c, 0x2001, 0x0020,
+	0x0804, 0x27fc, 0x080c, 0x3bf9, 0x1904, 0x257c, 0x781b, 0x0068,
+	0x70b8, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898,
+	0x78d2, 0x78da, 0x7808, 0xc08d, 0x780a, 0x68bc, 0x703e, 0xc1b4,
+	0x71d2, 0x70b4, 0xa065, 0x68c0, 0x7056, 0x7003, 0x0002, 0x2d00,
+	0x704a, 0xad80, 0x0009, 0x7042, 0x0005, 0x080c, 0x3bf9, 0x1120,
+	0x781b, 0x0054, 0x7003, 0x0004, 0x0005, 0x080c, 0x3bf9, 0x1128,
+	0x2011, 0x000c, 0x0419, 0x7003, 0x0004, 0x0005, 0x080c, 0x3bf9,
+	0x1128, 0x2011, 0x0006, 0x00d1, 0x7003, 0x0004, 0x0005, 0x080c,
+	0x3bf9, 0x1128, 0x2011, 0x000d, 0x0089, 0x7003, 0x0004, 0x0005,
+	0x080c, 0x3bf9, 0x1150, 0x2011, 0x0006, 0x0041, 0x7078, 0x707b,
+	0x0000, 0x2068, 0x704a, 0x7003, 0x0001, 0x0005, 0x7170, 0xc1fc,
+	0x8107, 0x7882, 0x789b, 0x0080, 0xa286, 0x000c, 0x1120, 0x7aaa,
+	0x2001, 0x0001, 0x0098, 0xa18c, 0x001f, 0xa18d, 0x00c0, 0x79aa,
+	0xa286, 0x000d, 0x0120, 0x7aaa, 0x2001, 0x0002, 0x0038, 0x78ab,
+	0x0020, 0x7174, 0x79aa, 0x7aaa, 0x2001, 0x0004, 0x789b, 0x0060,
+	0x78aa, 0x785b, 0x0004, 0x781b, 0x0113, 0x080c, 0x3c0c, 0x707f,
+	0x000f, 0x70d0, 0xd0b4, 0x0168, 0xc0b4, 0x70d2, 0x00c6, 0x70b4,
+	0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a,
+	0x00ce, 0x0005, 0x7014, 0xa005, 0x1138, 0x70d0, 0xd0b4, 0x0128,
+	0x70b4, 0xac06, 0x1110, 0x0c29, 0x0005, 0x0016, 0x71a0, 0xa186,
+	0x0001, 0x0528, 0x00d6, 0x0026, 0x2100, 0x2011, 0x0001, 0xa212,
+	0x70b0, 0x2068, 0x6800, 0xac06, 0x0120, 0x8211, 0x01b0, 0x00c9,
+	0x0cc8, 0x00c6, 0x2100, 0x2011, 0x0001, 0xa212, 0x70b0, 0x2068,
+	0x6800, 0x2060, 0x6008, 0xa084, 0xfbef, 0x600a, 0x8211, 0x0110,
+	0x0041, 0x0cb0, 0x70a3, 0x0001, 0x00ce, 0x002e, 0x00de, 0x001e,
+	0x0005, 0xade8, 0x0005, 0x70a8, 0xad06, 0x1110, 0x70a4, 0x2068,
+	0x0005, 0x080c, 0x3bf9, 0x1904, 0x257c, 0x7078, 0x2068, 0x7770,
+	0x080c, 0x3b35, 0x2c50, 0x080c, 0x3c94, 0x789b, 0x0080, 0x6814,
+	0xa084, 0x001f, 0xc0bd, 0x78aa, 0x6e1c, 0x2041, 0x0001, 0x2001,
+	0x0004, 0x0804, 0x2801, 0x080c, 0x3bf9, 0x1904, 0x257c, 0x789b,
+	0x0080, 0x705c, 0x2068, 0x6f14, 0x70d0, 0xd0b4, 0x0168, 0xc0b4,
+	0x70d2, 0x00c6, 0x70b4, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a,
+	0x6018, 0x8001, 0x601a, 0x00ce, 0x080c, 0x3b35, 0x2c50, 0x080c,
+	0x3c94, 0x6824, 0xa005, 0x0130, 0xa082, 0x0006, 0x0208, 0x0010,
+	0x6827, 0x0005, 0x6814, 0xa084, 0x001f, 0xc0bd, 0x78aa, 0x2031,
+	0x0020, 0x2041, 0x0001, 0x2001, 0x0003, 0x0804, 0x2801, 0xc28d,
+	0x72d2, 0x72bc, 0xa200, 0xa015, 0x7150, 0x8108, 0xa12a, 0x0208,
+	0x71bc, 0x2164, 0x6504, 0x85ff, 0x1170, 0x7152, 0x8421, 0x1da8,
+	0x70d0, 0xd08c, 0x0128, 0x70cc, 0xa005, 0x1110, 0x70cf, 0x000a,
+	0x0005, 0x2200, 0x0c90, 0x70d0, 0xc08c, 0x70d2, 0x70cf, 0x0000,
+	0x6034, 0xa005, 0x1db0, 0x6708, 0xa784, 0x073f, 0x01d0, 0xd7d4,
+	0x1d80, 0xa784, 0x0021, 0x1d68, 0xa784, 0x0002, 0x0130, 0xa784,
+	0x0004, 0x0d38, 0xa7bc, 0xfffb, 0x670a, 0xa784, 0x0218, 0x1d08,
+	0xa784, 0x0100, 0x0130, 0x6018, 0xa005, 0x19d8, 0xa7bc, 0xfeff,
+	0x670a, 0x2568, 0x6823, 0x0000, 0x6e1c, 0xa684, 0x000e, 0x6318,
+	0x0128, 0x601c, 0xa302, 0x0220, 0x0118, 0x0858, 0x83ff, 0x1948,
+	0x2d58, 0x2c50, 0x7152, 0xd7bc, 0x1110, 0x7028, 0x6022, 0xc7bc,
+	0x670a, 0x68c0, 0xa065, 0xa04d, 0x6100, 0x2a60, 0x2041, 0x0001,
+	0x6b14, 0xa39c, 0x001f, 0xa39d, 0x00c0, 0xd1fc, 0x0110, 0xd684,
+	0x0110, 0xa39c, 0xffbf, 0xd6a4, 0x0110, 0xa39d, 0x0020, 0xa684,
+	0x000e, 0x1904, 0x27b3, 0xc7a5, 0x670a, 0x2c00, 0x68c6, 0x77a0,
+	0xa786, 0x0001, 0x1178, 0x70d0, 0xd0b4, 0x1160, 0x7000, 0xa082,
+	0x0002, 0x1240, 0x7830, 0xd0bc, 0x1128, 0x789b, 0x0080, 0x7baa,
+	0x0804, 0x27fa, 0x8739, 0x77a2, 0x2750, 0x77ac, 0xa7b0, 0x0005,
+	0x70a8, 0xa606, 0x1108, 0x76a4, 0x76ae, 0x2c3a, 0x8738, 0x2d3a,
+	0x8738, 0x283a, 0x8738, 0x233a, 0x8738, 0x253a, 0x7830, 0xd0bc,
+	0x0150, 0x2091, 0x8000, 0x2091, 0x303d, 0x70d0, 0xa084, 0x303d,
+	0x2091, 0x8000, 0x2090, 0xaad5, 0x0000, 0x0120, 0x8421, 0x2200,
+	0x1904, 0x2704, 0x0005, 0xd1dc, 0x0904, 0x3796, 0x2029, 0x0020,
+	0xd69c, 0x1120, 0x8528, 0xd68c, 0x1108, 0x8528, 0x8840, 0x6f14,
+	0x610c, 0x8108, 0xa18c, 0x00ff, 0x70c8, 0xa160, 0x2c64, 0x8cff,
+	0x0188, 0x6014, 0xa706, 0x1dd0, 0x60b8, 0x8001, 0x60ba, 0x1d88,
+	0x2a60, 0x6008, 0xa085, 0x0100, 0x600a, 0x2200, 0x8421, 0x1904,
+	0x2704, 0x0005, 0x2a60, 0x610e, 0x69be, 0x2c00, 0x68c6, 0x8840,
+	0x6008, 0xc0d5, 0x600a, 0x77a0, 0xa786, 0x0001, 0x1904, 0x278a,
+	0x70d0, 0xd0b4, 0x1904, 0x278a, 0x7000, 0xa082, 0x0002, 0x1a04,
+	0x278a, 0x7830, 0xd0bc, 0x1904, 0x278a, 0x789b, 0x0080, 0x7baa,
+	0x7daa, 0x79aa, 0x2001, 0x0002, 0x0006, 0x6018, 0x8000, 0x601a,
+	0x0008, 0x0006, 0x2960, 0x6104, 0x2a60, 0x080c, 0x3ca7, 0x1590,
+	0xa184, 0x0018, 0x0180, 0xa184, 0x0010, 0x0118, 0x080c, 0x393d,
+	0x1548, 0xa184, 0x0008, 0x0138, 0x69a0, 0xa184, 0x0600, 0x1118,
+	0x080c, 0x385d, 0x00f8, 0x69a0, 0xa184, 0x1e00, 0x0528, 0xa184,
+	0x0800, 0x0178, 0x00c6, 0x2960, 0x6000, 0xa085, 0x2000, 0x6002,
+	0x6104, 0xa18d, 0x0010, 0x6106, 0x00ce, 0x080c, 0x393d, 0x1150,
+	0x69a0, 0xa184, 0x0200, 0x0118, 0x080c, 0x38a0, 0x0018, 0xa184,
+	0x0400, 0x19f0, 0x69a0, 0xa184, 0x1000, 0x0130, 0x6914, 0xa18c,
+	0xff00, 0x810f, 0x080c, 0x2384, 0x002e, 0xa68c, 0x00e0, 0xa684,
+	0x0060, 0x0128, 0xa086, 0x0060, 0x1110, 0xa18d, 0x4000, 0xa18d,
+	0x0104, 0x69b6, 0x789b, 0x0060, 0x2800, 0x78aa, 0x6818, 0xc0fd,
+	0x681a, 0xd6bc, 0x0168, 0xc0fc, 0x7083, 0x0000, 0xa08a, 0x000d,
+	0x0328, 0xa08a, 0x000c, 0x7182, 0x2001, 0x000c, 0x800c, 0x7186,
+	0x78aa, 0x3518, 0x3340, 0x3428, 0x8000, 0x80ac, 0xaf80, 0x002b,
+	0x20a0, 0x789b, 0x0000, 0xad80, 0x000b, 0x2098, 0x53a6, 0x23a8,
+	0x2898, 0x25a0, 0xa286, 0x0020, 0x1508, 0x70d0, 0xc0b5, 0x70d2,
+	0x2c00, 0x70b6, 0x2d00, 0x70ba, 0x6814, 0xc0fc, 0x8007, 0x7882,
+	0xa286, 0x0002, 0x0904, 0x28d2, 0x70a0, 0x8000, 0x70a2, 0x74b0,
+	0xa498, 0x0005, 0x70a8, 0xa306, 0x1108, 0x73a4, 0x73b2, 0xa286,
+	0x0010, 0x0904, 0x257c, 0x00de, 0x00ce, 0x0005, 0x7000, 0xa005,
+	0x19e0, 0xa286, 0x0002, 0x1904, 0x28e9, 0x080c, 0x3bf9, 0x19a8,
+	0x6814, 0xc0fc, 0x8007, 0x7882, 0x2091, 0x8000, 0x781b, 0x0068,
 	0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da,
-	0x7808, 0xc08d, 0x780a, 0x68bc, 0x7042, 0xc1b4, 0x71d6, 0x70b8,
-	0xa065, 0x68c0, 0x705a, 0x7003, 0x0002, 0x2d00, 0x704e, 0xad80,
-	0x0009, 0x7046, 0x0005, 0x080c, 0x3a8d, 0x1120, 0x781b, 0x0054,
-	0x7003, 0x0004, 0x0005, 0x080c, 0x3a8d, 0x1128, 0x2011, 0x000c,
-	0x0419, 0x7003, 0x0004, 0x0005, 0x080c, 0x3a8d, 0x1128, 0x2011,
-	0x0006, 0x00d1, 0x7003, 0x0004, 0x0005, 0x080c, 0x3a8d, 0x1128,
-	0x2011, 0x000d, 0x0089, 0x7003, 0x0004, 0x0005, 0x080c, 0x3a8d,
-	0x1150, 0x2011, 0x0006, 0x0041, 0x707c, 0x707f, 0x0000, 0x2068,
-	0x704e, 0x7003, 0x0001, 0x0005, 0x7174, 0xc1fc, 0x8107, 0x7882,
-	0x789b, 0x0080, 0xa286, 0x000c, 0x1120, 0x7aaa, 0x2001, 0x0001,
-	0x0098, 0xa18c, 0x001f, 0xa18d, 0x00c0, 0x79aa, 0xa286, 0x000d,
-	0x0120, 0x7aaa, 0x2001, 0x0002, 0x0038, 0x78ab, 0x0020, 0x7178,
-	0x79aa, 0x7aaa, 0x2001, 0x0004, 0x789b, 0x0060, 0x78aa, 0x785b,
-	0x0004, 0x781b, 0x0113, 0x080c, 0x3aa0, 0x7083, 0x000f, 0x70d4,
-	0xd0b4, 0x0168, 0xc0b4, 0x70d6, 0x00c6, 0x70b8, 0xa065, 0x6008,
-	0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x00ce, 0x0005,
-	0x7014, 0xa005, 0x1138, 0x70d4, 0xd0b4, 0x0128, 0x70b8, 0xac06,
-	0x1110, 0x0c29, 0x0005, 0x0016, 0x71a4, 0xa186, 0x0001, 0x0528,
-	0x00d6, 0x0026, 0x2100, 0x2011, 0x0001, 0xa212, 0x70b4, 0x2068,
-	0x6800, 0xac06, 0x0120, 0x8211, 0x01b0, 0x00c9, 0x0cc8, 0x00c6,
-	0x2100, 0x2011, 0x0001, 0xa212, 0x70b4, 0x2068, 0x6800, 0x2060,
-	0x6008, 0xa084, 0xfbef, 0x600a, 0x8211, 0x0110, 0x0041, 0x0cb0,
-	0x70a7, 0x0001, 0x00ce, 0x002e, 0x00de, 0x001e, 0x0005, 0xade8,
-	0x0005, 0x70ac, 0xad06, 0x1110, 0x70a8, 0x2068, 0x0005, 0x080c,
-	0x3a8d, 0x1904, 0x248c, 0x707c, 0x2068, 0x7774, 0x080c, 0x396d,
-	0x2c50, 0x080c, 0x3b28, 0x789b, 0x0080, 0x6814, 0xa084, 0x001f,
-	0xc0bd, 0x78aa, 0x6e1c, 0x2041, 0x0001, 0x2001, 0x0004, 0x0804,
-	0x270f, 0x080c, 0x3a8d, 0x1904, 0x248c, 0x789b, 0x0080, 0x7060,
-	0x2068, 0x6f14, 0x70d4, 0xd0b4, 0x0168, 0xc0b4, 0x70d6, 0x00c6,
-	0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001,
-	0x601a, 0x00ce, 0x080c, 0x396d, 0x2c50, 0x080c, 0x3b28, 0x6824,
-	0xa005, 0x0130, 0xa082, 0x0006, 0x0208, 0x0010, 0x6827, 0x0005,
-	0x6814, 0xa084, 0x001f, 0xc0bd, 0x78aa, 0x2031, 0x0020, 0x2041,
-	0x0001, 0x2001, 0x0003, 0x0804, 0x270f, 0xc28d, 0x72d6, 0x72c0,
-	0xa200, 0xa015, 0x7154, 0x8108, 0xa12a, 0x0208, 0x71c0, 0x2164,
-	0x6504, 0x85ff, 0x1170, 0x7156, 0x8421, 0x1da8, 0x70d4, 0xd08c,
-	0x0128, 0x70d0, 0xa005, 0x1110, 0x70d3, 0x000a, 0x0005, 0x2200,
-	0x0c90, 0x70d4, 0xc08c, 0x70d6, 0x70d3, 0x0000, 0x6034, 0xa005,
-	0x1db0, 0x6708, 0xa784, 0x073f, 0x01d0, 0xd7d4, 0x1d80, 0xa784,
-	0x0021, 0x1d68, 0xa784, 0x0002, 0x0130, 0xa784, 0x0004, 0x0d38,
-	0xa7bc, 0xfffb, 0x670a, 0xa784, 0x0218, 0x1d08, 0xa784, 0x0100,
-	0x0130, 0x6018, 0xa005, 0x19d8, 0xa7bc, 0xfeff, 0x670a, 0x2568,
-	0x6823, 0x0000, 0x6e1c, 0xa684, 0x000e, 0x6318, 0x0128, 0x601c,
-	0xa302, 0x0220, 0x0118, 0x0858, 0x83ff, 0x1948, 0x2d58, 0x2c50,
-	0x7156, 0xd7bc, 0x1110, 0x7028, 0x6022, 0xc7bc, 0x670a, 0x68c0,
-	0xa065, 0xa04d, 0x6100, 0x2a60, 0x2041, 0x0001, 0x6b14, 0xa39c,
-	0x001f, 0xa39d, 0x00c0, 0xd1fc, 0x0110, 0xd684, 0x0110, 0xa39c,
-	0xffbf, 0xd6a4, 0x0110, 0xa39d, 0x0020, 0xa684, 0x000e, 0x1904,
-	0x26c1, 0xc7a5, 0x670a, 0x2c00, 0x68c6, 0x77a4, 0xa786, 0x0001,
-	0x1178, 0x70d4, 0xd0b4, 0x1160, 0x7000, 0xa082, 0x0002, 0x1240,
-	0x7830, 0xd0bc, 0x1128, 0x789b, 0x0080, 0x7baa, 0x0804, 0x2708,
-	0x8739, 0x77a6, 0x2750, 0x77b0, 0xa7b0, 0x0005, 0x70ac, 0xa606,
-	0x1108, 0x76a8, 0x76b2, 0x2c3a, 0x8738, 0x2d3a, 0x8738, 0x283a,
-	0x8738, 0x233a, 0x8738, 0x253a, 0x7830, 0xd0bc, 0x0150, 0x2091,
-	0x8000, 0x2091, 0x303d, 0x70d4, 0xa084, 0x303d, 0x2091, 0x8000,
-	0x2090, 0xaad5, 0x0000, 0x0120, 0x8421, 0x2200, 0x1904, 0x2612,
-	0x0005, 0xd1dc, 0x0904, 0x35d5, 0x2029, 0x0020, 0xd69c, 0x1120,
-	0x8528, 0xd68c, 0x1108, 0x8528, 0x8840, 0x6f14, 0x610c, 0x8108,
-	0xa18c, 0x00ff, 0x70cc, 0xa160, 0x2c64, 0x8cff, 0x0188, 0x6014,
-	0xa706, 0x1dd0, 0x60b8, 0x8001, 0x60ba, 0x1d88, 0x2a60, 0x6008,
-	0xa085, 0x0100, 0x600a, 0x2200, 0x8421, 0x1904, 0x2612, 0x0005,
-	0x2a60, 0x610e, 0x69be, 0x2c00, 0x68c6, 0x8840, 0x6008, 0xc0d5,
-	0x600a, 0x77a4, 0xa786, 0x0001, 0x1904, 0x2698, 0x70d4, 0xd0b4,
-	0x1904, 0x2698, 0x7000, 0xa082, 0x0002, 0x1a04, 0x2698, 0x7830,
-	0xd0bc, 0x1904, 0x2698, 0x789b, 0x0080, 0x7baa, 0x7daa, 0x79aa,
-	0x2001, 0x0002, 0x0006, 0x6018, 0x8000, 0x601a, 0x0008, 0x0006,
-	0x2960, 0x6104, 0x2a60, 0x080c, 0x3b3b, 0x1590, 0xa184, 0x0018,
-	0x0180, 0xa184, 0x0010, 0x0118, 0x080c, 0x3776, 0x1548, 0xa184,
-	0x0008, 0x0138, 0x69a0, 0xa184, 0x0600, 0x1118, 0x080c, 0x3696,
-	0x00f8, 0x69a0, 0xa184, 0x1e00, 0x0528, 0xa184, 0x0800, 0x0178,
-	0x00c6, 0x2960, 0x6000, 0xa085, 0x2000, 0x6002, 0x6104, 0xa18d,
-	0x0010, 0x6106, 0x00ce, 0x080c, 0x3776, 0x1150, 0x69a0, 0xa184,
-	0x0200, 0x0118, 0x080c, 0x36d9, 0x0018, 0xa184, 0x0400, 0x19f0,
-	0x69a0, 0xa184, 0x1000, 0x0130, 0x6914, 0xa18c, 0xff00, 0x810f,
-	0x080c, 0x231f, 0x002e, 0xa68c, 0x00e0, 0xa684, 0x0060, 0x0128,
-	0xa086, 0x0060, 0x1110, 0xa18d, 0x4000, 0xa18d, 0x0104, 0x69b6,
-	0x789b, 0x0060, 0x2800, 0x78aa, 0x6818, 0xc0fd, 0x681a, 0xd6bc,
-	0x0168, 0xc0fc, 0x7087, 0x0000, 0xa08a, 0x000d, 0x0328, 0xa08a,
-	0x000c, 0x7186, 0x2001, 0x000c, 0x800c, 0x718a, 0x78aa, 0x3518,
-	0x3340, 0x3428, 0x8000, 0x80ac, 0xaf80, 0x002b, 0x20a0, 0x789b,
-	0x0000, 0xad80, 0x000b, 0x2098, 0x53a6, 0x23a8, 0x2898, 0x25a0,
-	0xa286, 0x0020, 0x1508, 0x70d4, 0xc0b5, 0x70d6, 0x2c00, 0x70ba,
-	0x2d00, 0x70be, 0x6814, 0xc0fc, 0x8007, 0x7882, 0xa286, 0x0002,
-	0x0904, 0x27e0, 0x70a4, 0x8000, 0x70a6, 0x74b4, 0xa498, 0x0005,
-	0x70ac, 0xa306, 0x1108, 0x73a8, 0x73b6, 0xa286, 0x0010, 0x0904,
-	0x248c, 0x00de, 0x00ce, 0x0005, 0x7000, 0xa005, 0x19e0, 0xa286,
-	0x0002, 0x1904, 0x27f7, 0x080c, 0x3a8d, 0x19a8, 0x6814, 0xc0fc,
-	0x8007, 0x7882, 0x2091, 0x8000, 0x781b, 0x0068, 0x68b4, 0x785a,
-	0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0x2091, 0x8001,
-	0x7808, 0xc08d, 0x780a, 0x0126, 0x00d6, 0x00c6, 0x70d4, 0xa084,
-	0x2e00, 0x2090, 0x00ce, 0x00de, 0x012e, 0x2900, 0x705a, 0x68bc,
-	0x7042, 0x7003, 0x0002, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046,
-	0x7830, 0xd0bc, 0x0140, 0x2091, 0x303d, 0x70d4, 0xa084, 0x303d,
-	0x2091, 0x8000, 0x2090, 0x70a4, 0xa005, 0x1108, 0x0005, 0x8421,
-	0x0de8, 0x7250, 0x70c0, 0xa200, 0xa015, 0x0804, 0x2612, 0xa286,
-	0x0010, 0x1560, 0x080c, 0x3a8d, 0x1904, 0x278b, 0x6814, 0xc0fc,
-	0x8007, 0x7882, 0x781b, 0x0068, 0x68b4, 0x785a, 0x6894, 0x78d6,
-	0x78de, 0x6898, 0x78d2, 0x78da, 0x7808, 0xc08d, 0x780a, 0x70a4,
-	0x8000, 0x70a6, 0x74b4, 0xa490, 0x0005, 0x70ac, 0xa206, 0x1108,
-	0x72a8, 0x72b6, 0x2900, 0x705a, 0x68bc, 0x7042, 0x7003, 0x0002,
-	0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x0005, 0x6bb4, 0xa39d,
-	0x2000, 0x7b5a, 0x6814, 0xc0fc, 0x8007, 0x7882, 0x6b94, 0x7bd6,
-	0x7bde, 0x6e98, 0x7ed2, 0x7eda, 0x781b, 0x0068, 0x2900, 0x705a,
-	0x7202, 0x7808, 0xc08d, 0x780a, 0x2300, 0xa605, 0x0170, 0x70d4,
-	0xa084, 0x2e00, 0xa086, 0x2600, 0x1118, 0x2009, 0x0000, 0x0010,
-	0x2009, 0x0001, 0xa284, 0x000f, 0x0023, 0xad80, 0x0009, 0x7046,
-	0x0005, 0x2859, 0x3fb8, 0x3fb8, 0x3fa6, 0x3fb8, 0x2859, 0x2859,
-	0x2859, 0x080c, 0x243b, 0x7808, 0xa084, 0xfffd, 0x780a, 0x00f6,
-	0x2079, 0x4300, 0x78ac, 0x00fe, 0xd084, 0x01c0, 0x7064, 0xa086,
-	0x0001, 0x1118, 0x7066, 0x0804, 0x293a, 0x7064, 0xa086, 0x0005,
-	0x1158, 0x707c, 0x2068, 0x681b, 0x0004, 0x6817, 0x0000, 0x6820,
-	0xa084, 0x00ff, 0xc09d, 0x6822, 0x7067, 0x0000, 0x70a7, 0x0000,
-	0x70a8, 0x70b2, 0x70b6, 0x080c, 0x256f, 0x0156, 0x2011, 0x0004,
-	0x7164, 0xa186, 0x0001, 0x0170, 0xa186, 0x0007, 0x1118, 0x701f,
-	0x0005, 0x0040, 0x701f, 0x0001, 0x7067, 0x0000, 0x70d4, 0xc0c5,
-	0x70d6, 0x0010, 0x7067, 0x0000, 0x2001, 0x430a, 0x2004, 0xa084,
-	0x00ff, 0xa086, 0x0018, 0x0130, 0x7018, 0x7016, 0xa005, 0x1110,
-	0x70a7, 0x0001, 0x0066, 0x080c, 0x3d52, 0x20a9, 0x0010, 0x2039,
-	0x0000, 0x080c, 0x3861, 0xa7b8, 0x0100, 0x1f04, 0x28b1, 0x006e,
-	0x7000, 0x0002, 0x28ee, 0x28cc, 0x28cc, 0x28c4, 0x28ee, 0x28ee,
-	0x28ee, 0x28c2, 0x080c, 0x243b, 0x7060, 0xa005, 0x0538, 0xad06,
-	0x1118, 0x6800, 0x7062, 0x0080, 0x6820, 0xd084, 0x1148, 0x6f14,
-	0x080c, 0x396d, 0x6008, 0xc0d4, 0x600a, 0x080c, 0x35ab, 0x0020,
-	0x705c, 0x2060, 0x6800, 0x6002, 0xa684, 0x5f00, 0x681e, 0x6818,
-	0xd0fc, 0x0108, 0x6a1a, 0x6817, 0x0000, 0x682b, 0x0000, 0x6820,
-	0xa084, 0x00ff, 0xc09d, 0x6822, 0x080c, 0x1d3d, 0xb284, 0x0800,
-	0x0118, 0x2021, 0x8ad0, 0x0010, 0x2021, 0x89c0, 0x080c, 0x293f,
-	0xb284, 0x0800, 0x0118, 0x2021, 0x4398, 0x0010, 0x2021, 0x4358,
-	0x04f1, 0x20a9, 0x0101, 0xb284, 0x0800, 0x0118, 0x2021, 0x89d0,
-	0x0010, 0x2021, 0x88c0, 0x0499, 0x8420, 0x1f04, 0x290b, 0xb284,
-	0x0600, 0x0118, 0x2061, 0x48c0, 0x0010, 0x2061, 0x68c0, 0x2021,
-	0x0002, 0x20a9, 0x0100, 0x6110, 0x81ff, 0x0198, 0x6018, 0x0016,
-	0x0006, 0x2011, 0x4302, 0x220c, 0xa102, 0x2012, 0x000e, 0x001e,
-	0xa102, 0x0338, 0x6012, 0x1128, 0x2011, 0x4304, 0x2204, 0xc0a5,
-	0x2012, 0x601b, 0x0000, 0xace0, 0x0010, 0x1f04, 0x291b, 0x8421,
-	0x1d00, 0x015e, 0x7003, 0x0000, 0x704f, 0x0000, 0x0005, 0x0046,
-	0x2404, 0xa005, 0x01a8, 0x2068, 0x6800, 0x0006, 0x6a1a, 0x6817,
+	0x2091, 0x8001, 0x7808, 0xc08d, 0x780a, 0x0126, 0x00d6, 0x00c6,
+	0x70d0, 0xa084, 0x2e00, 0x2090, 0x00ce, 0x00de, 0x012e, 0x2900,
+	0x7056, 0x68bc, 0x703e, 0x7003, 0x0002, 0x2d00, 0x704a, 0xad80,
+	0x0009, 0x7042, 0x7830, 0xd0bc, 0x0140, 0x2091, 0x303d, 0x70d0,
+	0xa084, 0x303d, 0x2091, 0x8000, 0x2090, 0x70a0, 0xa005, 0x1108,
+	0x0005, 0x8421, 0x0de8, 0x724c, 0x70bc, 0xa200, 0xa015, 0x0804,
+	0x2704, 0xa286, 0x0010, 0x1560, 0x080c, 0x3bf9, 0x1904, 0x287d,
+	0x6814, 0xc0fc, 0x8007, 0x7882, 0x781b, 0x0068, 0x68b4, 0x785a,
+	0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0x7808, 0xc08d,
+	0x780a, 0x70a0, 0x8000, 0x70a2, 0x74b0, 0xa490, 0x0005, 0x70a8,
+	0xa206, 0x1108, 0x72a4, 0x72b2, 0x2900, 0x7056, 0x68bc, 0x703e,
+	0x7003, 0x0002, 0x2d00, 0x704a, 0xad80, 0x0009, 0x7042, 0x0005,
+	0x6bb4, 0xa39d, 0x2000, 0x7b5a, 0x6814, 0xc0fc, 0x8007, 0x7882,
+	0x6b94, 0x7bd6, 0x7bde, 0x6e98, 0x7ed2, 0x7eda, 0x781b, 0x0068,
+	0x2900, 0x7056, 0x7202, 0x7808, 0xc08d, 0x780a, 0x2300, 0xa605,
+	0x0170, 0x70d0, 0xa084, 0x2e00, 0xa086, 0x2600, 0x1118, 0x2009,
+	0x0000, 0x0010, 0x2009, 0x0001, 0xa284, 0x000f, 0x0023, 0xad80,
+	0x0009, 0x7042, 0x0005, 0x294b, 0x4180, 0x4180, 0x416e, 0x4180,
+	0x294b, 0x294b, 0x294b, 0x080c, 0x252b, 0x7808, 0xa084, 0xfffd,
+	0x780a, 0x00f6, 0x2079, 0x4500, 0x78ac, 0x00fe, 0xd084, 0x01b0,
+	0x7060, 0xa086, 0x0001, 0x0904, 0x2a29, 0x7060, 0xa086, 0x0005,
+	0x1158, 0x7078, 0x2068, 0x681b, 0x0004, 0x6817, 0x0000, 0x6820,
+	0xa084, 0x00ff, 0xc09d, 0x6822, 0x7063, 0x0000, 0x70a3, 0x0000,
+	0x70a4, 0x70ae, 0x70b2, 0x080c, 0x2661, 0x0156, 0x2011, 0x0004,
+	0x7160, 0xa186, 0x0001, 0x0160, 0xa186, 0x0007, 0x1118, 0x701f,
+	0x0005, 0x0030, 0x701f, 0x0001, 0x70d0, 0xc0c5, 0x70d2, 0x0000,
+	0x2001, 0x450a, 0x2004, 0xa084, 0x00ff, 0xa086, 0x0018, 0x0130,
+	0x7018, 0x7016, 0xa005, 0x1110, 0x70a3, 0x0001, 0x0066, 0x080c,
+	0x3ed9, 0x20a9, 0x0010, 0x2039, 0x0000, 0x080c, 0x3a29, 0xa7b8,
+	0x0100, 0x1f04, 0x299d, 0x006e, 0x7000, 0x0002, 0x29da, 0x29b8,
+	0x29b8, 0x29b0, 0x29da, 0x29da, 0x29da, 0x29ae, 0x080c, 0x252b,
+	0x705c, 0xa005, 0x0538, 0xad06, 0x1118, 0x6800, 0x705e, 0x0080,
+	0x6820, 0xd084, 0x1148, 0x6f14, 0x080c, 0x3b35, 0x6008, 0xc0d4,
+	0x600a, 0x080c, 0x376c, 0x0020, 0x7058, 0x2060, 0x6800, 0x6002,
+	0xa684, 0x5f00, 0x681e, 0x6818, 0xd0fc, 0x0108, 0x6a1a, 0x6817,
+	0x0000, 0x682b, 0x0000, 0x6820, 0xa084, 0x00ff, 0xc09d, 0x6822,
+	0x080c, 0x1d89, 0x2011, 0x0004, 0xb284, 0x0800, 0x0118, 0x2021,
+	0x8cd0, 0x0010, 0x2021, 0x8bc0, 0x080c, 0x2a30, 0xb284, 0x0800,
+	0x0118, 0x2021, 0x4597, 0x0010, 0x2021, 0x4557, 0x080c, 0x2a30,
+	0x20a9, 0x0101, 0xb284, 0x0800, 0x0118, 0x2021, 0x8bd0, 0x0010,
+	0x2021, 0x8ac0, 0x04a9, 0x8420, 0x1f04, 0x29fa, 0xb284, 0x0600,
+	0x0118, 0x2061, 0x4ac0, 0x0010, 0x2061, 0x6ac0, 0x2021, 0x0002,
+	0x20a9, 0x0100, 0x6110, 0x81ff, 0x0198, 0x6018, 0x0016, 0x0006,
+	0x2011, 0x4502, 0x220c, 0xa102, 0x2012, 0x000e, 0x001e, 0xa102,
+	0x0338, 0x6012, 0x1128, 0x2011, 0x4504, 0x2204, 0xc0a5, 0x2012,
+	0x601b, 0x0000, 0xace0, 0x0010, 0x1f04, 0x2a0a, 0x8421, 0x1d00,
+	0x015e, 0x7063, 0x0000, 0x7003, 0x0000, 0x704b, 0x0000, 0x0005,
+	0x0046, 0x2404, 0xa005, 0x01a8, 0x2068, 0x6800, 0x0006, 0x6a1a,
+	0x6817, 0x0000, 0x682b, 0x0000, 0x68b4, 0xa084, 0x5f00, 0x681e,
+	0x6820, 0xa084, 0x00ff, 0xc09d, 0x6822, 0x080c, 0x1d89, 0x000e,
+	0x0c48, 0x004e, 0x2023, 0x0000, 0x0005, 0xa282, 0x0003, 0x0310,
+	0x080c, 0x252b, 0x2300, 0x0002, 0x2a57, 0x2ad4, 0x2aee, 0xa282,
+	0x0002, 0x0110, 0x080c, 0x252b, 0x7060, 0x7063, 0x0000, 0x707f,
+	0x0000, 0x0022, 0x77d0, 0xc7c5, 0x77d2, 0x0002, 0x2a6e, 0x2a6e,
+	0x2a70, 0x2aa8, 0x37a0, 0x2a6e, 0x2aa8, 0x2a6e, 0x080c, 0x252b,
+	0x7770, 0x080c, 0x3a29, 0x7770, 0xa7bc, 0x8f00, 0x080c, 0x3b35,
+	0x6018, 0xa005, 0x0528, 0xd7fc, 0x1118, 0x2021, 0x8bc0, 0x0010,
+	0x2021, 0x8cd0, 0x2009, 0x0005, 0x2011, 0x0010, 0x080c, 0x2b08,
+	0x01b8, 0x0156, 0x20a9, 0x0101, 0xd7fc, 0x1118, 0x2021, 0x8ac0,
+	0x0010, 0x2021, 0x8bd0, 0x0046, 0x2009, 0x0005, 0x2011, 0x0010,
+	0x080c, 0x2b08, 0x004e, 0x0118, 0x8420, 0x1f04, 0x2a93, 0x015e,
+	0x8738, 0xa784, 0x001f, 0x1990, 0x0804, 0x257f, 0x0804, 0x257f,
+	0x7770, 0x080c, 0x3b35, 0x6018, 0xa005, 0x0520, 0xd7fc, 0x1118,
+	0x2021, 0x8bc0, 0x0010, 0x2021, 0x8cd0, 0x2009, 0x0005, 0x2011,
+	0x0020, 0x080c, 0x2b08, 0x01b0, 0x0156, 0x20a9, 0x0101, 0xd7fc,
+	0x1118, 0x2021, 0x8ac0, 0x0010, 0x2021, 0x8bd0, 0x0046, 0x2009,
+	0x0005, 0x2011, 0x0020, 0x04e1, 0x004e, 0x0118, 0x8420, 0x1f04,
+	0x2ac6, 0x015e, 0x0804, 0x257f, 0x2200, 0x0002, 0x2ad9, 0x2adb,
+	0x2adb, 0x080c, 0x252b, 0x2009, 0x0012, 0x7060, 0xa086, 0x0002,
+	0x0110, 0x2009, 0x000e, 0x6818, 0xd0fc, 0x0108, 0x691a, 0x7063,
+	0x0000, 0x70d0, 0xc0c5, 0x70d2, 0x0804, 0x3bab, 0x2200, 0x0002,
+	0x2af5, 0x2adb, 0x2af3, 0x080c, 0x252b, 0x080c, 0x3ed9, 0x7000,
+	0xa086, 0x0002, 0x1904, 0x3725, 0x080c, 0x3786, 0x6008, 0xa084,
+	0xfbef, 0x600a, 0x080c, 0x3717, 0x0904, 0x3725, 0x0804, 0x257f,
+	0x2404, 0xa005, 0x0590, 0x2068, 0x2d04, 0x0006, 0x6814, 0xa706,
+	0x0118, 0x2d20, 0x000e, 0x0ca8, 0x000e, 0x2022, 0x691a, 0x6817,
 	0x0000, 0x682b, 0x0000, 0x68b4, 0xa084, 0x5f00, 0x681e, 0x6820,
-	0xa084, 0x00ff, 0xc09d, 0x6822, 0x080c, 0x1d3d, 0x000e, 0x0c48,
-	0x004e, 0x2023, 0x0000, 0x0005, 0xa282, 0x0003, 0x0310, 0x080c,
-	0x243b, 0x2300, 0x0002, 0x2966, 0x29e3, 0x29fd, 0xa282, 0x0002,
-	0x0110, 0x080c, 0x243b, 0x7064, 0x7067, 0x0000, 0x7083, 0x0000,
-	0x0022, 0x77d4, 0xc7c5, 0x77d6, 0x0002, 0x297d, 0x297d, 0x297f,
-	0x29b7, 0x35df, 0x297d, 0x29b7, 0x297d, 0x080c, 0x243b, 0x7774,
-	0x080c, 0x3861, 0x7774, 0xa7bc, 0x8f00, 0x080c, 0x396d, 0x6018,
-	0xa005, 0x0528, 0xd7fc, 0x1118, 0x2021, 0x89c0, 0x0010, 0x2021,
-	0x8ad0, 0x2009, 0x0005, 0x2011, 0x0010, 0x080c, 0x2a17, 0x01b8,
-	0x0156, 0x20a9, 0x0101, 0xd7fc, 0x1118, 0x2021, 0x88c0, 0x0010,
-	0x2021, 0x89d0, 0x0046, 0x2009, 0x0005, 0x2011, 0x0010, 0x080c,
-	0x2a17, 0x004e, 0x0118, 0x8420, 0x1f04, 0x29a2, 0x015e, 0x8738,
-	0xa784, 0x001f, 0x1990, 0x0804, 0x248f, 0x0804, 0x248f, 0x7774,
-	0x080c, 0x396d, 0x6018, 0xa005, 0x0520, 0xd7fc, 0x1118, 0x2021,
-	0x89c0, 0x0010, 0x2021, 0x8ad0, 0x2009, 0x0005, 0x2011, 0x0020,
-	0x080c, 0x2a17, 0x01b0, 0x0156, 0x20a9, 0x0101, 0xd7fc, 0x1118,
-	0x2021, 0x88c0, 0x0010, 0x2021, 0x89d0, 0x0046, 0x2009, 0x0005,
-	0x2011, 0x0020, 0x04e1, 0x004e, 0x0118, 0x8420, 0x1f04, 0x29d5,
-	0x015e, 0x0804, 0x248f, 0x2200, 0x0002, 0x29e8, 0x29ea, 0x29ea,
-	0x080c, 0x243b, 0x2009, 0x0012, 0x7064, 0xa086, 0x0002, 0x0110,
-	0x2009, 0x000e, 0x6818, 0xd0fc, 0x0108, 0x691a, 0x7067, 0x0000,
-	0x70d4, 0xc0c5, 0x70d6, 0x0804, 0x3a3f, 0x2200, 0x0002, 0x2a04,
-	0x29ea, 0x2a02, 0x080c, 0x243b, 0x080c, 0x3d52, 0x7000, 0xa086,
-	0x0002, 0x1904, 0x356d, 0x080c, 0x35c5, 0x6008, 0xa084, 0xfbef,
-	0x600a, 0x080c, 0x355f, 0x0904, 0x356d, 0x0804, 0x248f, 0x2404,
-	0xa005, 0x0590, 0x2068, 0x2d04, 0x0006, 0x6814, 0xa706, 0x0118,
-	0x2d20, 0x000e, 0x0ca8, 0x000e, 0x2022, 0x691a, 0x6817, 0x0000,
-	0x682b, 0x0000, 0x68b4, 0xa084, 0x5f00, 0x681e, 0x6820, 0xa084,
-	0x00ff, 0xa205, 0x6822, 0x080c, 0x1d3d, 0x2021, 0x4302, 0x241c,
-	0x8319, 0x2322, 0x6010, 0x8001, 0x6012, 0x1128, 0x2021, 0x4304,
-	0x2404, 0xc0a5, 0x2022, 0x6008, 0xa084, 0xf9ef, 0x600a, 0x080c,
-	0x258b, 0x080c, 0x35c5, 0x0005, 0xa085, 0x0001, 0x0ce0, 0x2300,
-	0x0002, 0x2a56, 0x2a54, 0x2abc, 0x080c, 0x243b, 0x78e4, 0xa005,
-	0x1708, 0x3208, 0xa18c, 0x0800, 0x0118, 0x0104, 0x248c, 0x0010,
-	0x0304, 0x248c, 0x2008, 0xa084, 0x0030, 0x1110, 0x0804, 0x30a0,
-	0x78ec, 0xa084, 0x0003, 0x0dd0, 0x2100, 0xa084, 0x0007, 0x0002,
-	0x2a9f, 0x2aa8, 0x2a95, 0x2a78, 0x3a83, 0x3a83, 0x2a78, 0x2ab2,
-	0x080c, 0x243b, 0x7000, 0xa086, 0x0004, 0x1190, 0x7064, 0xa086,
-	0x0002, 0x1130, 0x2011, 0x0002, 0x2019, 0x0000, 0x0804, 0x295c,
-	0x7064, 0xa086, 0x0006, 0x0db0, 0x7064, 0xa086, 0x0004, 0x0d90,
-	0x79e4, 0x2001, 0x0003, 0x0804, 0x2daa, 0x6818, 0xd0fc, 0x0110,
-	0x681b, 0x001d, 0x080c, 0x3837, 0x781b, 0x006e, 0x0005, 0x6818,
-	0xd0fc, 0x0110, 0x681b, 0x001d, 0x080c, 0x3837, 0x0804, 0x3a61,
-	0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d, 0x080c, 0x3837, 0x781b,
-	0x00fa, 0x0005, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d, 0x080c,
-	0x3837, 0x781b, 0x00cb, 0x0005, 0xa584, 0x000f, 0x11c0, 0x7000,
-	0x0002, 0x248f, 0x2ac9, 0x2acb, 0x356d, 0x356d, 0x356d, 0x2ac9,
-	0x2ac9, 0x080c, 0x243b, 0x080c, 0x35c5, 0x6008, 0xa084, 0xfbef,
-	0x600a, 0x080c, 0x355f, 0x0904, 0x356d, 0x0804, 0x248f, 0x78e4,
-	0xa005, 0x1b04, 0x2a7a, 0x3208, 0xa18c, 0x0800, 0x0118, 0x0104,
-	0x2a7a, 0x0010, 0x0304, 0x2a7a, 0x2008, 0xa084, 0x0030, 0x1118,
-	0x781b, 0x0068, 0x0005, 0x78ec, 0xa084, 0x0003, 0x0dc8, 0x2100,
-	0xa184, 0x0007, 0x0002, 0x2b02, 0x2b06, 0x2afd, 0x2afb, 0x3a83,
-	0x3a83, 0x2afb, 0x3a7d, 0x080c, 0x243b, 0x080c, 0x383d, 0x781b,
-	0x006e, 0x0005, 0x080c, 0x383d, 0x0804, 0x3a61, 0x080c, 0x383d,
-	0x781b, 0x00fa, 0x0005, 0x080c, 0x383d, 0x781b, 0x00cb, 0x0005,
-	0x2300, 0x0002, 0x2b17, 0x2b15, 0x2b19, 0x080c, 0x243b, 0x0804,
-	0x3220, 0x681b, 0x0016, 0x78a3, 0x0000, 0x79e4, 0xa184, 0x0030,
-	0x0904, 0x3220, 0x78ec, 0xa084, 0x0003, 0x0904, 0x3220, 0xa184,
-	0x0100, 0x0d98, 0xa184, 0x0007, 0x0002, 0x2b35, 0x2b06, 0x2a95,
-	0x3a3f, 0x3a83, 0x3a83, 0x3a3f, 0x3a7d, 0x080c, 0x3a4b, 0x0005,
-	0xa282, 0x0005, 0x0310, 0x080c, 0x243b, 0x7898, 0x2040, 0x2300,
-	0x0002, 0x2b44, 0x2d41, 0x2d4b, 0x2200, 0x0002, 0x2b60, 0x2b4d,
-	0x2b60, 0x2b4b, 0x2d25, 0x080c, 0x243b, 0x789b, 0x0018, 0x78a8,
-	0x2010, 0xa084, 0x00ff, 0xa082, 0x0020, 0x0a04, 0x3809, 0xa08a,
-	0x0004, 0x1a04, 0x3809, 0x0002, 0x3809, 0x3809, 0x3809, 0x37bf,
-	0x789b, 0x0018, 0x79a8, 0xa184, 0x0080, 0x0148, 0x0804, 0x3809,
-	0x7000, 0xa005, 0x1dd8, 0x2011, 0x0004, 0x0804, 0x33b2, 0xa184,
-	0x00ff, 0xa08a, 0x0010, 0x1a04, 0x3809, 0x0002, 0x2b88, 0x2b86,
-	0x2b9a, 0x2b9e, 0x2c3c, 0x3809, 0x3809, 0x2c3e, 0x3809, 0x3809,
-	0x2d21, 0x2d21, 0x3809, 0x3809, 0x3809, 0x2d23, 0x080c, 0x243b,
-	0xd6e4, 0x0140, 0x2001, 0x0300, 0x8000, 0x8000, 0x783a, 0x781b,
-	0x00c6, 0x0005, 0x6818, 0xd0fc, 0x0118, 0x681b, 0x001d, 0x0c90,
-	0x0804, 0x3a3f, 0x681b, 0x001d, 0x0804, 0x3831, 0x6920, 0x6922,
-	0xa684, 0x1800, 0x15e0, 0x6820, 0xd084, 0x1904, 0x2be7, 0x6818,
-	0xa086, 0x0008, 0x1110, 0x681b, 0x0000, 0xd6d4, 0x0568, 0xd6bc,
-	0x0558, 0x7087, 0x0000, 0x6818, 0xa084, 0x003f, 0xa08a, 0x000d,
-	0x0718, 0xa08a, 0x000c, 0x7186, 0x2001, 0x000c, 0x800c, 0x718a,
-	0x789b, 0x0061, 0x78aa, 0x0156, 0x0136, 0x0146, 0x0016, 0x3208,
-	0xa18c, 0x0600, 0x0118, 0x20a1, 0x022b, 0x0010, 0x20a1, 0x012b,
-	0x001e, 0x789b, 0x0000, 0x8000, 0x80ac, 0xad80, 0x000b, 0x2098,
-	0x53a6, 0x014e, 0x013e, 0x015e, 0x781b, 0x0071, 0x0005, 0xd6e4,
-	0x0130, 0x781b, 0x0083, 0x0005, 0x781b, 0x0083, 0x0005, 0xa684,
-	0x0060, 0x0dd0, 0xd6dc, 0x0dc0, 0xd6fc, 0x01a0, 0xc6fc, 0x7e5a,
-	0x6eb6, 0x7adc, 0x79d8, 0x78d0, 0x8007, 0xa084, 0x007f, 0xa108,
-	0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200,
-	0xa303, 0x68ae, 0xd6f4, 0x0118, 0xc6f4, 0x7e5a, 0x6eb6, 0x7000,
-	0xa086, 0x0003, 0x1148, 0x0006, 0x080c, 0x3d52, 0x080c, 0x3fb8,
-	0x000e, 0x781b, 0x0080, 0x0005, 0xa006, 0x080c, 0x4083, 0x6ab0,
-	0x69ac, 0x6c98, 0x6b94, 0x2200, 0xa105, 0x0120, 0x2200, 0xa422,
-	0x2100, 0xa31b, 0x6caa, 0x7cd2, 0x7cda, 0x6ba6, 0x7bd6, 0x7bde,
-	0x2300, 0xa405, 0x1130, 0xc6f5, 0x7e5a, 0x6eb6, 0x781b, 0x0080,
-	0x0005, 0x781b, 0x0080, 0x2200, 0xa115, 0x1118, 0x080c, 0x3fb8,
-	0x0005, 0x080c, 0x3fe5, 0x0005, 0x080c, 0x243b, 0x0804, 0x2cbd,
-	0x00c6, 0x7058, 0x2060, 0x7aa8, 0xa294, 0x00ff, 0xa286, 0x0004,
-	0x11d8, 0x6920, 0xd1e4, 0x1170, 0x2039, 0x0000, 0x2041, 0x0000,
-	0x2031, 0x0000, 0xa006, 0x2010, 0x080c, 0x36f6, 0x080c, 0x379a,
-	0x0804, 0x2cb1, 0xa18c, 0xecff, 0x6922, 0x6104, 0xa18c, 0xffdd,
-	0x6106, 0x6000, 0xc0ac, 0x6002, 0xa286, 0x0003, 0x01d0, 0x6104,
-	0xa18c, 0x0010, 0x0548, 0x080c, 0x3969, 0x080c, 0x3776, 0x88ff,
-	0x0518, 0x00ce, 0x789b, 0x0060, 0x2800, 0x78aa, 0x7e58, 0xc695,
-	0x7e5a, 0xd6d4, 0x1118, 0x781b, 0x006e, 0x0005, 0x781b, 0x0082,
-	0x0005, 0x6920, 0xd1cc, 0x0130, 0xa18c, 0xfdff, 0x6922, 0x6000,
-	0xc0ec, 0x6002, 0x2039, 0x0000, 0x2041, 0x0000, 0x2031, 0x0000,
-	0xa006, 0x2010, 0x080c, 0x379a, 0xa286, 0x0001, 0x0158, 0x6104,
-	0xa18c, 0x0008, 0x01b0, 0x080c, 0x3969, 0x080c, 0x3696, 0x88ff,
-	0x1980, 0x0078, 0x6920, 0xd1c4, 0x0130, 0xa18c, 0xfeff, 0x6922,
-	0x6000, 0xc0e4, 0x6002, 0x2031, 0x0000, 0xa006, 0x2010, 0x080c,
-	0x36f6, 0x00ce, 0x7e58, 0xd6d4, 0x1118, 0x781b, 0x0071, 0x0005,
-	0x781b, 0x0083, 0x0005, 0x0804, 0x382d, 0x2808, 0x789b, 0x0080,
-	0x2019, 0x0080, 0x78a8, 0xa094, 0x00ff, 0xa286, 0x0001, 0x1188,
-	0x7ca8, 0xa4a4, 0x00ff, 0xa480, 0x0002, 0xa300, 0x2018, 0xa102,
-	0x0a04, 0x2c40, 0x0904, 0x2c40, 0x24a8, 0x7aa8, 0x1f04, 0x2cd5,
-	0x0c48, 0xa284, 0x00f0, 0xa082, 0x0020, 0x06b8, 0x2200, 0xa082,
-	0x0021, 0x1698, 0x7aa8, 0x8318, 0x8318, 0x2100, 0xa302, 0x0ad0,
-	0xa286, 0x0023, 0x0980, 0x681c, 0xa084, 0xfff1, 0x681e, 0x7e58,
-	0xa684, 0xfff1, 0xc0a5, 0x2030, 0x7e5a, 0x6008, 0xc0a5, 0x600a,
-	0x78a0, 0x8001, 0x0904, 0x2cb1, 0x20a8, 0x7998, 0x789b, 0x0060,
-	0x78aa, 0x2011, 0x0080, 0x799a, 0x78a8, 0x7998, 0x7a9a, 0x78aa,
-	0x7a98, 0x1f04, 0x2d03, 0xc695, 0x7e5a, 0xd6d4, 0x1118, 0x781b,
-	0x006e, 0x0005, 0x781b, 0x0082, 0x0005, 0x8318, 0x2100, 0xa302,
-	0x0a04, 0x2cc2, 0xa284, 0x0080, 0x1904, 0x3831, 0x78a0, 0xa005,
-	0x08c8, 0x0804, 0x3831, 0x0804, 0x3809, 0x7058, 0xa04d, 0x789b,
-	0x0018, 0x78a8, 0xa084, 0x00ff, 0xa08e, 0x0001, 0x0110, 0x080c,
-	0x243b, 0x7aa8, 0xa294, 0x00ff, 0x78a8, 0xa084, 0x00ff, 0xa08a,
-	0x0005, 0x1a04, 0x3809, 0x0002, 0x3809, 0x3615, 0x3809, 0x3726,
-	0x3b83, 0xa282, 0x0000, 0x1110, 0x080c, 0x243b, 0x080c, 0x3837,
-	0x781b, 0x0082, 0x0005, 0xa282, 0x0003, 0x1110, 0x080c, 0x243b,
-	0xd4fc, 0x11d0, 0x7064, 0xa005, 0x0110, 0x080c, 0x243b, 0x6f14,
-	0x7776, 0xa7bc, 0x8f00, 0x080c, 0x396d, 0x6008, 0xa085, 0x0021,
-	0x600a, 0x8738, 0xa784, 0x001f, 0x1db0, 0x080c, 0x383a, 0x7067,
-	0x0002, 0x701f, 0x0009, 0x0010, 0x080c, 0x3846, 0x781b, 0x0082,
-	0x0005, 0xa282, 0x0004, 0x0310, 0x080c, 0x243b, 0x2300, 0x0002,
-	0x2d7b, 0x2eff, 0x2f3b, 0xa286, 0x0003, 0x0560, 0x7200, 0x7cd8,
-	0x7ddc, 0x7fd0, 0x71d4, 0xd1b4, 0x00f0, 0x7868, 0xa084, 0x00ff,
-	0x11d0, 0xa282, 0x0002, 0x12b8, 0x00d6, 0x783b, 0x8300, 0x781b,
-	0x0059, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de,
-	0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030, 0x00de,
-	0x2001, 0x0000, 0x0058, 0x783b, 0x1300, 0x781b, 0x0057, 0x2001,
-	0x0000, 0x0020, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0, 0x704a, 0x68a0,
-	0xd0ec, 0x0118, 0x6008, 0xc08d, 0x600a, 0xa284, 0x000f, 0x0002,
-	0x2ee0, 0x2dc5, 0x2dc2, 0x3012, 0x3085, 0x248f, 0x2dc0, 0x2dc0,
-	0x080c, 0x243b, 0x6008, 0xc0d4, 0x600a, 0xd6e4, 0x0120, 0x7048,
-	0xa086, 0x0014, 0x11e8, 0x080c, 0x3d52, 0x2009, 0x0000, 0x6818,
-	0xd0fc, 0x0108, 0x7048, 0xa086, 0x0014, 0x0168, 0x6818, 0xa086,
-	0x0008, 0x1904, 0x2ea2, 0x7858, 0xd09c, 0x0904, 0x2ea2, 0x6820,
-	0xd0ac, 0x0904, 0x2ea2, 0x681b, 0x0014, 0x2009, 0x0002, 0x04a8,
-	0x7868, 0xa08c, 0x00ff, 0x0588, 0xa186, 0x0008, 0x1158, 0x6008,
-	0xc0a4, 0x600a, 0x080c, 0x355f, 0x0540, 0x080c, 0x35c5, 0x080c,
-	0x3d52, 0x0060, 0xa186, 0x0028, 0x1500, 0x6018, 0xa005, 0x0d78,
-	0x8001, 0x0d68, 0x8001, 0x0d58, 0x601e, 0x0c48, 0x6820, 0xd084,
-	0x0904, 0x248f, 0xc084, 0x6822, 0x080c, 0x2580, 0x705c, 0x00c6,
-	0x2060, 0x6800, 0x6002, 0x00ce, 0x6004, 0x6802, 0xa005, 0x2d00,
-	0x1108, 0x6002, 0x6006, 0x0804, 0x248f, 0x0016, 0x81ff, 0x15e0,
-	0x7000, 0xa086, 0x0030, 0x05c0, 0x71d4, 0xd1b4, 0x11e8, 0x7060,
-	0xa005, 0x1590, 0x70a4, 0xa086, 0x0001, 0x0570, 0x7003, 0x0000,
-	0x0046, 0x0056, 0x0076, 0x0066, 0x00c6, 0x00d6, 0x080c, 0x24b2,
-	0x00de, 0x00ce, 0x006e, 0x007e, 0x005e, 0x004e, 0x71d4, 0xd1b4,
-	0x11d8, 0x7003, 0x0040, 0x00c0, 0x080c, 0x3a8d, 0x11a8, 0x781b,
-	0x0068, 0x00d6, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6,
-	0x78de, 0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030,
-	0x7808, 0xc08d, 0x780a, 0x00de, 0x080c, 0x2f63, 0x001e, 0x81ff,
-	0x0904, 0x2ea2, 0xa684, 0xdf00, 0x681e, 0x682b, 0x0000, 0x6f14,
-	0xa186, 0x0002, 0x15c0, 0x6818, 0xa086, 0x0014, 0x1130, 0x2008,
-	0xd6e4, 0x0118, 0x7868, 0xa08c, 0x00ff, 0x080c, 0x3850, 0x080c,
-	0x258b, 0x6820, 0xd0dc, 0x1538, 0x8717, 0xa294, 0x000f, 0x8213,
-	0x8213, 0x8213, 0xb284, 0x0600, 0x0118, 0xa290, 0x47c0, 0x0010,
-	0xa290, 0x4840, 0xa290, 0x0000, 0x221c, 0xd3c4, 0x0130, 0x8210,
-	0x2204, 0xa085, 0x0038, 0x2012, 0x8211, 0xd3d4, 0x0138, 0x68a0,
-	0xd0c4, 0x1120, 0x080c, 0x2fcb, 0x0804, 0x248f, 0x6008, 0xc08d,
-	0x600a, 0x0008, 0x692a, 0x6916, 0x6818, 0xd0fc, 0x0110, 0x7048,
-	0x681a, 0xa68c, 0xdf00, 0x691e, 0x6410, 0x84ff, 0x0168, 0x2009,
-	0x4302, 0x2104, 0x8001, 0x200a, 0x8421, 0x6412, 0x1128, 0x2021,
-	0x4304, 0x2404, 0xc0a5, 0x2022, 0x6018, 0xa005, 0x0118, 0x8001,
-	0x601a, 0x1118, 0x6008, 0xc0a4, 0x600a, 0x6820, 0xd084, 0x1130,
-	0x6800, 0xa005, 0x1108, 0x6002, 0x6006, 0x0020, 0x705c, 0x2060,
-	0x6800, 0x6002, 0x2061, 0x4300, 0x6887, 0x0103, 0x2d08, 0x206b,
-	0x0000, 0x6068, 0xa005, 0x616a, 0x0110, 0x2d02, 0x0008, 0x616e,
-	0x7200, 0xa286, 0x0030, 0x0158, 0xa286, 0x0040, 0x1904, 0x248f,
-	0x7003, 0x0002, 0x704c, 0x2068, 0x68c4, 0x2060, 0x0005, 0x7003,
-	0x0002, 0x70bc, 0xa06d, 0x68bc, 0x7042, 0x70b8, 0xa065, 0x68c0,
-	0x705a, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x0005, 0xa282,
-	0x0004, 0x0210, 0x080c, 0x243b, 0x2200, 0x0002, 0x2f0a, 0x2f19,
-	0x2f25, 0x2f19, 0xa586, 0x1300, 0x0160, 0xa586, 0x8300, 0x1d90,
-	0x7003, 0x0000, 0x6018, 0x8001, 0x601a, 0x6008, 0xa084, 0xfbef,
-	0x600a, 0x7000, 0xa086, 0x0005, 0x0128, 0x080c, 0x3837, 0x781b,
-	0x0082, 0x0005, 0x781b, 0x0083, 0x0005, 0x7890, 0x8007, 0x8001,
-	0xa084, 0x0007, 0xa080, 0x0018, 0x789a, 0x79a8, 0xa18c, 0x00ff,
-	0xa186, 0x0003, 0x0128, 0xa186, 0x0000, 0x0110, 0x0804, 0x3809,
-	0x781b, 0x0083, 0x0005, 0x6820, 0xc095, 0x6822, 0x82ff, 0x1118,
-	0x080c, 0x3837, 0x0030, 0x8211, 0x0110, 0x080c, 0x243b, 0x080c,
-	0x3846, 0x781b, 0x0082, 0x0005, 0x080c, 0x3aa0, 0x7830, 0xa084,
-	0x00c0, 0x1170, 0x0016, 0x3208, 0xa18c, 0x0800, 0x001e, 0x0118,
-	0x0104, 0x2f60, 0x0010, 0x0304, 0x2f60, 0x791a, 0xa006, 0x0005,
-	0xa085, 0x0001, 0x0005, 0xa684, 0x0060, 0x1130, 0x682f, 0x0000,
-	0x6833, 0x0000, 0x0804, 0x2fca, 0xd6dc, 0x1198, 0x68b4, 0xd0dc,
-	0x1180, 0x6998, 0x6a94, 0x692e, 0x6a32, 0x7048, 0xa005, 0x1130,
-	0x2200, 0xa105, 0x0904, 0x3d52, 0x704b, 0x0015, 0x0804, 0x3d52,
-	0x0005, 0xd6ac, 0x01f0, 0xd6f4, 0x0130, 0x682f, 0x0000, 0x6833,
-	0x0000, 0x0804, 0x3d52, 0x68b4, 0xa084, 0x4000, 0xa635, 0xd6f4,
-	0x1da0, 0x7048, 0xa005, 0x1110, 0x704b, 0x0015, 0xd6dc, 0x1128,
-	0x68b4, 0xd0dc, 0x0110, 0x6ca8, 0x6da4, 0x6c2e, 0x6d32, 0x0804,
-	0x3d52, 0xd6f4, 0x0130, 0x682f, 0x0000, 0x6833, 0x0000, 0x0804,
-	0x3d52, 0x68b4, 0xa084, 0x4800, 0xa635, 0xd6f4, 0x1da0, 0x7048,
-	0xa005, 0x1110, 0x704b, 0x0015, 0x2408, 0x2510, 0x2700, 0x8007,
-	0xa084, 0x007f, 0xa108, 0xa291, 0x0000, 0x692e, 0x6a32, 0x2100,
-	0xa205, 0x1110, 0x0804, 0x3d52, 0x7000, 0xa086, 0x0006, 0x0110,
-	0x0804, 0x3d52, 0x0005, 0x6946, 0x6008, 0xc0cd, 0xd3cc, 0x0108,
-	0xc08d, 0x600a, 0x6818, 0x683a, 0x681b, 0x0006, 0x688f, 0x0000,
-	0x6893, 0x0000, 0x6a30, 0x692c, 0x6a3e, 0x6942, 0x682f, 0x0003,
-	0x6833, 0x0000, 0x6837, 0x0020, 0x6897, 0x0000, 0x689b, 0x0020,
-	0x7000, 0x0002, 0x248f, 0x2ffa, 0x2ff4, 0x2ff2, 0x2ff2, 0x2ff2,
-	0x2ff2, 0x2ff2, 0x080c, 0x243b, 0x6820, 0xd084, 0x1118, 0x080c,
-	0x35ab, 0x0030, 0x705c, 0x2c50, 0x2060, 0x6800, 0x6002, 0x2a60,
-	0x3208, 0xa18c, 0x0600, 0x0118, 0x2021, 0x4358, 0x0010, 0x2021,
-	0x4398, 0x2404, 0xa005, 0x0110, 0x2020, 0x0cd8, 0x2d22, 0x206b,
-	0x0000, 0x0005, 0x080c, 0x35b1, 0x080c, 0x35c5, 0x6008, 0xc0cc,
-	0x600a, 0x682b, 0x0000, 0x789b, 0x000e, 0x6f14, 0x6938, 0x691a,
-	0x6944, 0x6916, 0x3208, 0xa18c, 0x0600, 0x0118, 0x2009, 0x0000,
-	0x0010, 0x2009, 0x0001, 0x080c, 0x40b1, 0xd6dc, 0x0118, 0x691c,
-	0xc1ed, 0x691e, 0x6818, 0xd0fc, 0x0148, 0x7868, 0xa08c, 0x00ff,
-	0x0118, 0x681b, 0x001e, 0x0010, 0x681b, 0x0000, 0xb284, 0x0600,
-	0x1118, 0x2021, 0x4398, 0x0010, 0x2021, 0x4358, 0x6800, 0x2022,
-	0x6a3c, 0x6940, 0x6a32, 0x692e, 0x68c0, 0x2060, 0x6000, 0xd0a4,
-	0x0580, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0020, 0x00d6,
-	0x00f6, 0x0156, 0x0146, 0x2079, 0x4300, 0x080c, 0x1b35, 0x014e,
-	0x015e, 0x00fe, 0x70cc, 0x2010, 0x2009, 0x0101, 0x0026, 0x2204,
-	0xa06d, 0x0140, 0x6814, 0xa706, 0x0110, 0x6800, 0x0cc8, 0x6820,
-	0xc0d5, 0x6822, 0x002e, 0x8210, 0x8109, 0x1d80, 0x00de, 0x7067,
-	0x0003, 0x707f, 0x0000, 0x7776, 0x7083, 0x000f, 0x71d4, 0xc1c4,
-	0x71d6, 0x080c, 0x1d3d, 0x0804, 0x248f, 0x7cd8, 0x7ddc, 0x7fd0,
-	0x080c, 0x2f63, 0x682b, 0x0000, 0x789b, 0x000e, 0x6f14, 0x080c,
-	0x3aa4, 0xa08c, 0x00ff, 0x6916, 0x6818, 0xd0fc, 0x0110, 0x7048,
-	0x681a, 0xa68c, 0xdf00, 0x691e, 0x7067, 0x0000, 0x0804, 0x248f,
-	0x7000, 0xa005, 0x1110, 0x0804, 0x248f, 0xa006, 0x080c, 0x3d52,
-	0x6920, 0xd1ac, 0x1110, 0x681b, 0x0014, 0xa68c, 0xdf00, 0x691e,
-	0x682b, 0x0000, 0x6820, 0xa084, 0x00ff, 0x6822, 0x7000, 0x0002,
-	0x248f, 0x30c2, 0x30c2, 0x30c5, 0x30c5, 0x30c5, 0x30c0, 0x30c0,
-	0x080c, 0x243b, 0x6818, 0x0804, 0x2daa, 0x6008, 0xc0a4, 0x600a,
-	0x6817, 0x0000, 0x0804, 0x357a, 0x2300, 0x0002, 0x30d1, 0x30d3,
-	0x3110, 0x080c, 0x243b, 0xd6fc, 0x1904, 0x2bee, 0x7000, 0xa00d,
-	0x0002, 0x248f, 0x30e3, 0x30e3, 0x3104, 0x30e3, 0x310d, 0x30e1,
-	0x30e1, 0x080c, 0x243b, 0xa684, 0x0060, 0xa086, 0x0060, 0x11d0,
-	0xc6ac, 0xc6f4, 0xc6ed, 0x7e5a, 0x681c, 0xc0ac, 0x681e, 0xa186,
-	0x0002, 0x0110, 0x080c, 0x3d52, 0x080c, 0x3fb8, 0x781b, 0x0083,
-	0x71d4, 0xd1b4, 0x1904, 0x248c, 0x70a4, 0xa086, 0x0001, 0x1904,
-	0x24ce, 0x0005, 0xd6ec, 0x0d30, 0x6818, 0xd0fc, 0x0130, 0x681b,
-	0x0015, 0xd6f4, 0x0110, 0x681b, 0x0007, 0x080c, 0x3a4b, 0x0005,
-	0x080c, 0x243b, 0x2300, 0x0002, 0x3119, 0x3134, 0x3182, 0x080c,
-	0x243b, 0x7000, 0x0002, 0x3123, 0x3125, 0x3125, 0x3123, 0x3123,
-	0x3123, 0x3123, 0x3123, 0x080c, 0x243b, 0x080c, 0x3fb8, 0x681c,
-	0xc0b4, 0x681e, 0x70d4, 0xd0b4, 0x1904, 0x248c, 0x70a4, 0xa086,
-	0x0001, 0x1904, 0x24ce, 0x0005, 0xd6fc, 0x15e0, 0x7000, 0xa00d,
-	0x0002, 0x248f, 0x3149, 0x3143, 0x316a, 0x3149, 0x316f, 0x3141,
-	0x3141, 0x080c, 0x243b, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2,
-	0x78da, 0xa684, 0x0060, 0xa086, 0x0060, 0x11d0, 0xa6b4, 0xbfbf,
-	0xc6ed, 0x7e5a, 0xa186, 0x0002, 0x0110, 0x080c, 0x3d52, 0x080c,
-	0x3fb8, 0x781b, 0x0083, 0x681c, 0xc0b4, 0x681e, 0x71d4, 0xd1b4,
-	0x1904, 0x248c, 0x70a4, 0xa086, 0x0001, 0x1904, 0x24ce, 0x0005,
-	0xd6ec, 0x0d30, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x0007, 0x781b,
-	0x00fb, 0x0005, 0xc6fc, 0x7e5a, 0x7adc, 0x79d8, 0x6b98, 0x2100,
-	0xa302, 0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae, 0x79d2, 0x781b,
-	0x0083, 0x0005, 0xd6dc, 0x0130, 0x782b, 0x3009, 0x781b, 0x0083,
-	0x0804, 0x248c, 0x7884, 0xc0ac, 0x7886, 0x78e4, 0xa084, 0x0008,
-	0x1150, 0xa484, 0x0200, 0x0108, 0xc6f5, 0xc6dd, 0x7e5a, 0x781b,
-	0x0083, 0x0804, 0x248c, 0x6820, 0xc095, 0x6822, 0x080c, 0x39ca,
-	0xc6dd, 0x080c, 0x3837, 0x781b, 0x0082, 0x0804, 0x248c, 0x2300,
-	0x0002, 0x31ac, 0x31ae, 0x31b0, 0x080c, 0x243b, 0x0804, 0x3831,
-	0x7d98, 0xd6d4, 0x11f8, 0x79e4, 0xd1ac, 0x0130, 0x78ec, 0xa084,
-	0x0003, 0x0110, 0x782b, 0x3009, 0x789b, 0x0060, 0x78ab, 0x0000,
-	0xa684, 0xfffb, 0x785a, 0x7d9a, 0x79e4, 0xd1ac, 0x0120, 0x78ec,
-	0xa084, 0x0003, 0x1120, 0x2001, 0x0014, 0x0804, 0x2daa, 0xa184,
-	0x0007, 0x04c2, 0x7a90, 0xa294, 0x0007, 0x789b, 0x0060, 0x79a8,
-	0x81ff, 0x0568, 0x789b, 0x0080, 0x7ba8, 0xa384, 0x0001, 0x11d0,
-	0x7ba8, 0x7ba8, 0xa386, 0x0004, 0x1118, 0x2009, 0xffdf, 0x0058,
-	0xa386, 0x0001, 0x1118, 0x2009, 0xfff7, 0x0028, 0xa386, 0x0003,
-	0x1148, 0x2009, 0xffef, 0x00c6, 0x7058, 0x2060, 0x6004, 0xa104,
-	0x6006, 0x00ce, 0x789b, 0x0060, 0x78ab, 0x0000, 0xa684, 0xfffb,
-	0x785a, 0x782b, 0x3009, 0x6920, 0xa18c, 0xecff, 0x6922, 0x7d9a,
-	0x0804, 0x3a3f, 0x2a9f, 0x2aa8, 0x3214, 0x321a, 0x3212, 0x3212,
-	0x3a3f, 0x3a3f, 0x080c, 0x243b, 0x6920, 0xa18c, 0xfcff, 0x6922,
-	0x0804, 0x3a45, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0804, 0x3a3f,
-	0x79e4, 0xa184, 0x0030, 0x0120, 0x78ec, 0xa084, 0x0003, 0x1558,
-	0x7000, 0xa086, 0x0004, 0x1190, 0x7064, 0xa086, 0x0002, 0x1130,
-	0x2011, 0x0002, 0x2019, 0x0000, 0x0804, 0x295c, 0x7064, 0xa086,
-	0x0006, 0x0db0, 0x7064, 0xa086, 0x0004, 0x0d90, 0x7000, 0xa086,
-	0x0000, 0x0904, 0x248c, 0x6920, 0xa184, 0x0420, 0x0128, 0xc1d4,
-	0x6922, 0x6818, 0x0804, 0x2daa, 0x6818, 0xc0fd, 0x681a, 0x2001,
-	0x0014, 0x0804, 0x2daa, 0xa184, 0x0007, 0x0002, 0x3a3f, 0x3a3f,
-	0x325e, 0x3a3f, 0x3a83, 0x3a83, 0x3a3f, 0x3a3f, 0xd6bc, 0x0570,
-	0x7184, 0x81ff, 0x0558, 0xa182, 0x000d, 0x1318, 0x7087, 0x0000,
-	0x0028, 0xa182, 0x000c, 0x7086, 0x2009, 0x000c, 0x789b, 0x0061,
-	0x79aa, 0x0156, 0x0136, 0x0146, 0x7088, 0x8114, 0xa210, 0x728a,
-	0xa080, 0x000b, 0xad00, 0x2098, 0xb284, 0x0600, 0x0118, 0x20a1,
-	0x022b, 0x0010, 0x20a1, 0x012b, 0x789b, 0x0000, 0x8108, 0x81ac,
-	0x53a6, 0x014e, 0x013e, 0x015e, 0x0804, 0x3a45, 0xd6d4, 0x1904,
-	0x32d1, 0x6820, 0xd084, 0x0904, 0x3a45, 0xa68c, 0x0060, 0xa684,
-	0x0060, 0x0120, 0xa086, 0x0060, 0x1108, 0xc1f5, 0xc194, 0x795a,
-	0x69b6, 0x789b, 0x0060, 0x78ab, 0x0000, 0x789b, 0x0061, 0x6818,
-	0xc0fd, 0x681a, 0x78aa, 0x8008, 0x810c, 0x0904, 0x35da, 0xa18c,
-	0x00f8, 0x1904, 0x35da, 0x0156, 0x0136, 0x0146, 0x0016, 0x20a1,
-	0x012b, 0x3208, 0xa18c, 0x0600, 0x0110, 0x20a1, 0x022b, 0x001e,
-	0x789b, 0x0000, 0x8000, 0x80ac, 0xad80, 0x000b, 0x2098, 0x53a6,
-	0x014e, 0x013e, 0x015e, 0x6814, 0xc0fc, 0x8007, 0x7882, 0x0804,
-	0x3a45, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x0008, 0x080c, 0x3837,
-	0x781b, 0x00ed, 0x0005, 0x2300, 0x0002, 0x32e2, 0x3398, 0x32e0,
-	0x080c, 0x243b, 0x7cd8, 0x7ddc, 0x7fd0, 0x82ff, 0x11f0, 0x7200,
-	0xa286, 0x0003, 0x0904, 0x2d7f, 0x71d4, 0xd1b4, 0x00c0, 0x00d6,
-	0x783b, 0x8800, 0x781b, 0x0059, 0x70bc, 0xa06d, 0x68b4, 0xc0a5,
-	0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0xc1b4,
-	0x71d6, 0x7003, 0x0030, 0x00de, 0x0030, 0x7200, 0x0020, 0x783b,
-	0x1800, 0x781b, 0x0057, 0xa284, 0x000f, 0x0002, 0x3383, 0x3344,
-	0x3318, 0x2da7, 0x3316, 0x3383, 0x3316, 0x3316, 0x080c, 0x243b,
-	0x681c, 0xd0ec, 0x0118, 0x6008, 0xc08d, 0x600a, 0x6920, 0xc185,
-	0x6922, 0x6800, 0x6006, 0xa005, 0x1108, 0x6002, 0x6008, 0xc0d4,
-	0x600a, 0x681c, 0xa084, 0x000e, 0x1148, 0xb284, 0x0600, 0x0118,
-	0x2009, 0x89c0, 0x0040, 0x2009, 0x8ad0, 0x0028, 0x7030, 0x68ba,
-	0x7140, 0x70cc, 0xa108, 0x2104, 0x6802, 0x2d0a, 0x715e, 0xd6dc,
-	0x1118, 0xc6fc, 0x6eb6, 0x04f8, 0x6eb6, 0xa684, 0x0060, 0x05d8,
+	0xa084, 0x00ff, 0xa205, 0x6822, 0x080c, 0x1d89, 0x2021, 0x4502,
+	0x241c, 0x8319, 0x2322, 0x6010, 0x8001, 0x6012, 0x1128, 0x2021,
+	0x4504, 0x2404, 0xc0a5, 0x2022, 0x6008, 0xa084, 0xf9ef, 0x600a,
+	0x080c, 0x267d, 0x080c, 0x3786, 0x0005, 0xa085, 0x0001, 0x0ce0,
+	0x2300, 0x0002, 0x2b47, 0x2b45, 0x2bad, 0x080c, 0x252b, 0x78e4,
+	0xa005, 0x1708, 0x3208, 0xa18c, 0x0800, 0x0118, 0x0104, 0x257c,
+	0x0010, 0x0304, 0x257c, 0x2008, 0xa084, 0x0030, 0x1110, 0x0804,
+	0x31c5, 0x78ec, 0xa084, 0x0003, 0x0dd0, 0x2100, 0xa084, 0x0007,
+	0x0002, 0x2b90, 0x2b99, 0x2b86, 0x2b69, 0x3bef, 0x3bef, 0x2b69,
+	0x2ba3, 0x080c, 0x252b, 0x7000, 0xa086, 0x0004, 0x1190, 0x7060,
+	0xa086, 0x0002, 0x1130, 0x2011, 0x0002, 0x2019, 0x0000, 0x0804,
+	0x2a4d, 0x7060, 0xa086, 0x0006, 0x0db0, 0x7060, 0xa086, 0x0004,
+	0x0d90, 0x79e4, 0x2001, 0x0003, 0x0804, 0x2ea4, 0x6818, 0xd0fc,
+	0x0110, 0x681b, 0x001d, 0x080c, 0x39ff, 0x781b, 0x006e, 0x0005,
+	0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d, 0x080c, 0x39ff, 0x0804,
+	0x3bcd, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d, 0x080c, 0x39ff,
+	0x781b, 0x00fa, 0x0005, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d,
+	0x080c, 0x39ff, 0x781b, 0x00cb, 0x0005, 0xa584, 0x000f, 0x11c0,
+	0x7000, 0x0002, 0x257f, 0x2bba, 0x2bbc, 0x3725, 0x3725, 0x3725,
+	0x2bba, 0x2bba, 0x080c, 0x252b, 0x080c, 0x3786, 0x6008, 0xa084,
+	0xfbef, 0x600a, 0x080c, 0x3717, 0x0904, 0x3725, 0x0804, 0x257f,
+	0x78e4, 0xa005, 0x1b04, 0x2b6b, 0x3208, 0xa18c, 0x0800, 0x0118,
+	0x0104, 0x2b6b, 0x0010, 0x0304, 0x2b6b, 0x2008, 0xa084, 0x0030,
+	0x1118, 0x781b, 0x0068, 0x0005, 0x78ec, 0xa084, 0x0003, 0x0dc8,
+	0x2100, 0xa184, 0x0007, 0x0002, 0x2bf3, 0x2bf7, 0x2bee, 0x2bec,
+	0x3bef, 0x3bef, 0x2bec, 0x3be9, 0x080c, 0x252b, 0x080c, 0x3a05,
+	0x781b, 0x006e, 0x0005, 0x080c, 0x3a05, 0x0804, 0x3bcd, 0x080c,
+	0x3a05, 0x781b, 0x00fa, 0x0005, 0x080c, 0x3a05, 0x781b, 0x00cb,
+	0x0005, 0x2300, 0x0002, 0x2c08, 0x2c06, 0x2c0a, 0x080c, 0x252b,
+	0x0804, 0x3361, 0x681b, 0x0016, 0x78a3, 0x0000, 0x79e4, 0xa184,
+	0x0030, 0x0904, 0x3361, 0x78ec, 0xa084, 0x0003, 0x0904, 0x3361,
+	0xa184, 0x0100, 0x0d98, 0xa184, 0x0007, 0x0002, 0x2c26, 0x2bf7,
+	0x2b86, 0x3bab, 0x3bef, 0x3bef, 0x3bab, 0x3be9, 0x080c, 0x3bb7,
+	0x0005, 0xa282, 0x0005, 0x0310, 0x080c, 0x252b, 0x7898, 0x2040,
+	0x2300, 0x0002, 0x2c35, 0x2e34, 0x2e3e, 0x2200, 0x0002, 0x2c51,
+	0x2c3e, 0x2c51, 0x2c3c, 0x2e16, 0x080c, 0x252b, 0x789b, 0x0018,
+	0x78a8, 0x2010, 0xa084, 0x00ff, 0xa082, 0x0020, 0x0a04, 0x39d0,
+	0xa08a, 0x0004, 0x1a04, 0x39d0, 0x0002, 0x39d0, 0x39d0, 0x39d0,
+	0x3986, 0x789b, 0x0018, 0x79a8, 0xa184, 0x0080, 0x0148, 0x0804,
+	0x39d0, 0x7000, 0xa005, 0x1dd8, 0x2011, 0x0004, 0x0804, 0x3502,
+	0xa184, 0x00ff, 0xa08a, 0x0010, 0x1a04, 0x39d0, 0x0002, 0x2c79,
+	0x2c77, 0x2c8b, 0x2c8f, 0x2d2d, 0x39d0, 0x39d0, 0x2d2f, 0x39d0,
+	0x39d0, 0x2e12, 0x2e12, 0x39d0, 0x39d0, 0x39d0, 0x2e14, 0x080c,
+	0x252b, 0xd6e4, 0x0140, 0x2001, 0x0300, 0x8000, 0x8000, 0x783a,
+	0x781b, 0x00c7, 0x0005, 0x6818, 0xd0fc, 0x0118, 0x681b, 0x001d,
+	0x0c90, 0x0804, 0x3bab, 0x681b, 0x001d, 0x0804, 0x39f9, 0x6920,
+	0x6922, 0xa684, 0x1800, 0x15e0, 0x6820, 0xd084, 0x1904, 0x2cd8,
+	0x6818, 0xa086, 0x0008, 0x1110, 0x681b, 0x0000, 0xd6d4, 0x0568,
+	0xd6bc, 0x0558, 0x7083, 0x0000, 0x6818, 0xa084, 0x003f, 0xa08a,
+	0x000d, 0x0718, 0xa08a, 0x000c, 0x7182, 0x2001, 0x000c, 0x800c,
+	0x7186, 0x789b, 0x0061, 0x78aa, 0x0156, 0x0136, 0x0146, 0x0016,
+	0x3208, 0xa18c, 0x0600, 0x0118, 0x20a1, 0x022b, 0x0010, 0x20a1,
+	0x012b, 0x001e, 0x789b, 0x0000, 0x8000, 0x80ac, 0xad80, 0x000b,
+	0x2098, 0x53a6, 0x014e, 0x013e, 0x015e, 0x781b, 0x0071, 0x0005,
+	0xd6e4, 0x0130, 0x781b, 0x0083, 0x0005, 0x781b, 0x0083, 0x0005,
+	0xa684, 0x0060, 0x0dd0, 0xd6dc, 0x0dc0, 0xd6fc, 0x01a0, 0xc6fc,
+	0x7e5a, 0x6eb6, 0x7adc, 0x79d8, 0x78d0, 0x8007, 0xa084, 0x007f,
+	0xa108, 0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94,
+	0x2200, 0xa303, 0x68ae, 0xd6f4, 0x0118, 0xc6f4, 0x7e5a, 0x6eb6,
+	0x7000, 0xa086, 0x0003, 0x1148, 0x0006, 0x080c, 0x3ed9, 0x080c,
+	0x4180, 0x000e, 0x781b, 0x0080, 0x0005, 0xa006, 0x080c, 0x425d,
+	0x6ab0, 0x69ac, 0x6c98, 0x6b94, 0x2200, 0xa105, 0x0120, 0x2200,
+	0xa422, 0x2100, 0xa31b, 0x6caa, 0x7cd2, 0x7cda, 0x6ba6, 0x7bd6,
+	0x7bde, 0x2300, 0xa405, 0x1130, 0xc6f5, 0x7e5a, 0x6eb6, 0x781b,
+	0x0080, 0x0005, 0x781b, 0x0080, 0x2200, 0xa115, 0x1118, 0x080c,
+	0x4180, 0x0005, 0x080c, 0x41ad, 0x0005, 0x080c, 0x252b, 0x0804,
+	0x2dae, 0x00c6, 0x7054, 0x2060, 0x7aa8, 0xa294, 0x00ff, 0xa286,
+	0x0004, 0x11d8, 0x6920, 0xd1e4, 0x1170, 0x2039, 0x0000, 0x2041,
+	0x0000, 0x2031, 0x0000, 0xa006, 0x2010, 0x080c, 0x38bd, 0x080c,
+	0x3961, 0x0804, 0x2da2, 0xa18c, 0xecff, 0x6922, 0x6104, 0xa18c,
+	0xffdd, 0x6106, 0x6000, 0xc0ac, 0x6002, 0xa286, 0x0003, 0x01d0,
+	0x6104, 0xa184, 0x0010, 0x0548, 0x080c, 0x3b31, 0x080c, 0x393d,
+	0x88ff, 0x0518, 0x00ce, 0x789b, 0x0060, 0x2800, 0x78aa, 0x7e58,
+	0xc695, 0x7e5a, 0xd6d4, 0x1118, 0x781b, 0x006e, 0x0005, 0x781b,
+	0x0082, 0x0005, 0x6920, 0xd1cc, 0x0130, 0xa18c, 0xfdff, 0x6922,
+	0x6000, 0xc0ec, 0x6002, 0x2039, 0x0000, 0x2041, 0x0000, 0x2031,
+	0x0000, 0xa006, 0x2010, 0x080c, 0x3961, 0xa286, 0x0001, 0x0158,
+	0x6104, 0xa184, 0x0008, 0x01b0, 0x080c, 0x3b31, 0x080c, 0x385d,
+	0x88ff, 0x1980, 0x0078, 0x6920, 0xd1c4, 0x0130, 0xa18c, 0xfeff,
+	0x6922, 0x6000, 0xc0e4, 0x6002, 0x2031, 0x0000, 0xa006, 0x2010,
+	0x080c, 0x38bd, 0x00ce, 0x7e58, 0xd6d4, 0x1118, 0x781b, 0x0071,
+	0x0005, 0x781b, 0x0083, 0x0005, 0x0804, 0x39f5, 0x2808, 0x789b,
+	0x0080, 0x2019, 0x0080, 0x78a8, 0xa094, 0x00ff, 0xa286, 0x0001,
+	0x1188, 0x7ca8, 0xa4a4, 0x00ff, 0xa480, 0x0002, 0xa300, 0x2018,
+	0xa102, 0x0a04, 0x2d31, 0x0904, 0x2d31, 0x24a8, 0x7aa8, 0x1f04,
+	0x2dc6, 0x0c48, 0xa284, 0x00f0, 0xa082, 0x0020, 0x06b8, 0x2200,
+	0xa082, 0x0021, 0x1698, 0x7aa8, 0x8318, 0x8318, 0x2100, 0xa302,
+	0x0ad0, 0xa286, 0x0023, 0x0980, 0x681c, 0xa084, 0xfff1, 0x681e,
+	0x7e58, 0xa684, 0xfff1, 0xc0a5, 0x2030, 0x7e5a, 0x6008, 0xc0a5,
+	0x600a, 0x78a0, 0x8001, 0x0904, 0x2da2, 0x20a8, 0x7998, 0x789b,
+	0x0060, 0x78aa, 0x2011, 0x0080, 0x799a, 0x78a8, 0x7998, 0x7a9a,
+	0x78aa, 0x7a98, 0x1f04, 0x2df4, 0xc695, 0x7e5a, 0xd6d4, 0x1118,
+	0x781b, 0x006e, 0x0005, 0x781b, 0x0082, 0x0005, 0x8318, 0x2100,
+	0xa302, 0x0a04, 0x2db3, 0xa284, 0x0080, 0x1904, 0x39f9, 0x78a0,
+	0xa005, 0x08c8, 0x0804, 0x39f9, 0x0804, 0x39d0, 0x7054, 0xa04d,
+	0x789b, 0x0018, 0x78a8, 0xa084, 0x00ff, 0xa08e, 0x0001, 0x0110,
+	0x080c, 0x252b, 0x7aa8, 0xa294, 0x00ff, 0x784b, 0x0008, 0x78a8,
+	0xa084, 0x00ff, 0xa08a, 0x0005, 0x1a04, 0x39d0, 0x0002, 0x39d0,
+	0x37d4, 0x39d0, 0x38ed, 0x3cef, 0xa282, 0x0000, 0x1110, 0x080c,
+	0x252b, 0x080c, 0x39ff, 0x781b, 0x0082, 0x0005, 0xa282, 0x0003,
+	0x1110, 0x080c, 0x252b, 0xd4fc, 0x11d0, 0x7060, 0xa005, 0x0110,
+	0x080c, 0x252b, 0x6f14, 0x7772, 0xa7bc, 0x8f00, 0x080c, 0x3b35,
+	0x6008, 0xa085, 0x0021, 0x600a, 0x8738, 0xa784, 0x001f, 0x1db0,
+	0x080c, 0x3a02, 0x7063, 0x0002, 0x701f, 0x0009, 0x0010, 0x080c,
+	0x3a0e, 0x781b, 0x0082, 0x0005, 0xa282, 0x0004, 0x0310, 0x080c,
+	0x252b, 0x2300, 0x0002, 0x2e6e, 0x3004, 0x3040, 0xa286, 0x0003,
+	0x0598, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0, 0x71d0, 0xd1bc, 0x1528,
+	0xd1b4, 0x0518, 0x2001, 0x4501, 0x2004, 0xd0c4, 0x11f0, 0x7868,
+	0xa084, 0x00ff, 0x11d0, 0xa282, 0x0002, 0x12b8, 0x00d6, 0x783b,
+	0x8300, 0x781b, 0x0059, 0x70b8, 0xa06d, 0x68b4, 0x785a, 0x6894,
+	0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d2, 0x7003,
+	0x0030, 0x00de, 0x2001, 0x0000, 0x0058, 0x783b, 0x1300, 0x781b,
+	0x0057, 0x2001, 0x0000, 0x0020, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0,
+	0x7046, 0x68a0, 0xd0ec, 0x0118, 0x6008, 0xc08d, 0x600a, 0xa284,
+	0x000f, 0x0002, 0x2fe5, 0x2ebf, 0x2ebc, 0x3117, 0x31aa, 0x257f,
+	0x2eba, 0x2eba, 0x080c, 0x252b, 0x6008, 0xc0d4, 0x600a, 0xd6e4,
+	0x0120, 0x7044, 0xa086, 0x0014, 0x11e8, 0x080c, 0x3ed9, 0x2009,
+	0x0000, 0x6818, 0xd0fc, 0x0108, 0x7044, 0xa086, 0x0014, 0x0168,
+	0x6818, 0xa086, 0x0008, 0x1904, 0x2fa7, 0x7858, 0xd09c, 0x0904,
+	0x2fa7, 0x6820, 0xd0ac, 0x0904, 0x2fa7, 0x681b, 0x0014, 0x2009,
+	0x0002, 0x04a8, 0x7868, 0xa08c, 0x00ff, 0x0588, 0xa186, 0x0008,
+	0x1158, 0x6008, 0xc0a4, 0x600a, 0x080c, 0x3717, 0x0540, 0x080c,
+	0x3786, 0x080c, 0x3ed9, 0x0060, 0xa186, 0x0028, 0x1500, 0x6018,
+	0xa005, 0x0d78, 0x8001, 0x0d68, 0x8001, 0x0d58, 0x601e, 0x0c48,
+	0x6820, 0xd084, 0x0904, 0x257f, 0xc084, 0x6822, 0x080c, 0x2672,
+	0x7058, 0x00c6, 0x2060, 0x6800, 0x6002, 0x00ce, 0x6004, 0x6802,
+	0xa005, 0x2d00, 0x1108, 0x6002, 0x6006, 0x0804, 0x257f, 0x0016,
+	0x81ff, 0x15f0, 0x7000, 0xa086, 0x0030, 0x05d0, 0x71d0, 0xd1bc,
+	0x15b8, 0xd1b4, 0x11e8, 0x705c, 0xa005, 0x1590, 0x70a0, 0xa086,
+	0x0001, 0x0570, 0x7003, 0x0000, 0x0046, 0x0056, 0x0076, 0x0066,
+	0x00c6, 0x00d6, 0x080c, 0x25a4, 0x00de, 0x00ce, 0x006e, 0x007e,
+	0x005e, 0x004e, 0x71d0, 0xd1b4, 0x11d8, 0x7003, 0x0040, 0x00c0,
+	0x080c, 0x3bf9, 0x11a8, 0x781b, 0x0068, 0x00d6, 0x70b8, 0xa06d,
+	0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da,
+	0xc1b4, 0x71d2, 0x7003, 0x0030, 0x7808, 0xc08d, 0x780a, 0x00de,
+	0x080c, 0x3068, 0x001e, 0x81ff, 0x0904, 0x2fa7, 0xa684, 0xdf00,
+	0x681e, 0x682b, 0x0000, 0x6f14, 0xa186, 0x0002, 0x1904, 0x2fa8,
+	0x6818, 0xa086, 0x0014, 0x1130, 0x2008, 0xd6e4, 0x0118, 0x7868,
+	0xa08c, 0x00ff, 0x080c, 0x3a18, 0x080c, 0x267d, 0x6820, 0xd0dc,
+	0x1578, 0x8717, 0xa294, 0x000f, 0x8213, 0x8213, 0x8213, 0xb284,
+	0x0600, 0x0118, 0xa290, 0x49c0, 0x0010, 0xa290, 0x4a40, 0xa290,
+	0x0000, 0x221c, 0xd3c4, 0x0170, 0x6820, 0xd0e4, 0x0128, 0xa084,
+	0xefff, 0x6822, 0xc3ac, 0x2312, 0x8210, 0x2204, 0xa085, 0x0038,
+	0x2012, 0x8211, 0xd3d4, 0x0138, 0x68a0, 0xd0c4, 0x1120, 0x080c,
+	0x30d0, 0x0804, 0x257f, 0x6008, 0xc08d, 0x600a, 0x0008, 0x692a,
+	0x6916, 0x6818, 0xd0fc, 0x0110, 0x7044, 0x681a, 0xa68c, 0xdf00,
+	0x691e, 0x6410, 0x84ff, 0x0168, 0x2009, 0x4502, 0x2104, 0x8001,
+	0x200a, 0x8421, 0x6412, 0x1128, 0x2021, 0x4504, 0x2404, 0xc0a5,
+	0x2022, 0x6018, 0xa005, 0x0118, 0x8001, 0x601a, 0x1118, 0x6008,
+	0xc0a4, 0x600a, 0x6820, 0xd084, 0x1130, 0x6800, 0xa005, 0x1108,
+	0x6002, 0x6006, 0x0020, 0x7058, 0x2060, 0x6800, 0x6002, 0x2061,
+	0x4500, 0x6887, 0x0103, 0x2d08, 0x206b, 0x0000, 0x6068, 0xa005,
+	0x616a, 0x0110, 0x2d02, 0x0008, 0x616e, 0x7200, 0xa286, 0x0030,
+	0x0158, 0xa286, 0x0040, 0x1904, 0x257f, 0x7003, 0x0002, 0x7048,
+	0x2068, 0x68c4, 0x2060, 0x0005, 0x7003, 0x0002, 0x70b8, 0xa06d,
+	0x68bc, 0x703e, 0x70b4, 0xa065, 0x68c0, 0x7056, 0x2d00, 0x704a,
+	0xad80, 0x0009, 0x7042, 0x0005, 0xa282, 0x0004, 0x0210, 0x080c,
+	0x252b, 0x2200, 0x0002, 0x300f, 0x301e, 0x302a, 0x301e, 0xa586,
+	0x1300, 0x0160, 0xa586, 0x8300, 0x1d90, 0x7003, 0x0000, 0x6018,
+	0x8001, 0x601a, 0x6008, 0xa084, 0xfbef, 0x600a, 0x7000, 0xa086,
+	0x0005, 0x0128, 0x080c, 0x39ff, 0x781b, 0x0082, 0x0005, 0x781b,
+	0x0083, 0x0005, 0x7890, 0x8007, 0x8001, 0xa084, 0x0007, 0xa080,
+	0x0018, 0x789a, 0x79a8, 0xa18c, 0x00ff, 0xa186, 0x0003, 0x0128,
+	0xa186, 0x0000, 0x0110, 0x0804, 0x39d0, 0x781b, 0x0083, 0x0005,
+	0x6820, 0xc095, 0x6822, 0x82ff, 0x1118, 0x080c, 0x39ff, 0x0030,
+	0x8211, 0x0110, 0x080c, 0x252b, 0x080c, 0x3a0e, 0x781b, 0x0082,
+	0x0005, 0x080c, 0x3c0c, 0x7830, 0xa084, 0x00c0, 0x1170, 0x0016,
+	0x3208, 0xa18c, 0x0800, 0x001e, 0x0118, 0x0104, 0x3065, 0x0010,
+	0x0304, 0x3065, 0x791a, 0xa006, 0x0005, 0xa085, 0x0001, 0x0005,
+	0xa684, 0x0060, 0x1130, 0x682f, 0x0000, 0x6833, 0x0000, 0x0804,
+	0x30cf, 0xd6dc, 0x1198, 0x68b4, 0xd0dc, 0x1180, 0x6998, 0x6a94,
+	0x692e, 0x6a32, 0x7044, 0xa005, 0x1130, 0x2200, 0xa105, 0x0904,
+	0x3ed9, 0x7047, 0x0015, 0x0804, 0x3ed9, 0x0005, 0xd6ac, 0x01f0,
+	0xd6f4, 0x0130, 0x682f, 0x0000, 0x6833, 0x0000, 0x0804, 0x3ed9,
+	0x68b4, 0xa084, 0x4000, 0xa635, 0xd6f4, 0x1da0, 0x7044, 0xa005,
+	0x1110, 0x7047, 0x0015, 0xd6dc, 0x1128, 0x68b4, 0xd0dc, 0x0110,
+	0x6ca8, 0x6da4, 0x6c2e, 0x6d32, 0x0804, 0x3ed9, 0xd6f4, 0x0130,
+	0x682f, 0x0000, 0x6833, 0x0000, 0x0804, 0x3ed9, 0x68b4, 0xa084,
+	0x4800, 0xa635, 0xd6f4, 0x1da0, 0x7044, 0xa005, 0x1110, 0x7047,
+	0x0015, 0x2408, 0x2510, 0x2700, 0x8007, 0xa084, 0x007f, 0xa108,
+	0xa291, 0x0000, 0x692e, 0x6a32, 0x2100, 0xa205, 0x1110, 0x0804,
+	0x3ed9, 0x7000, 0xa086, 0x0006, 0x0110, 0x0804, 0x3ed9, 0x0005,
+	0x6946, 0x6008, 0xc0cd, 0xd3cc, 0x0108, 0xc08d, 0x600a, 0x6818,
+	0x683a, 0x681b, 0x0006, 0x688f, 0x0000, 0x6893, 0x0000, 0x6a30,
+	0x692c, 0x6a3e, 0x6942, 0x682f, 0x0003, 0x6833, 0x0000, 0x6837,
+	0x0020, 0x6897, 0x0000, 0x689b, 0x0020, 0x7000, 0x0002, 0x257f,
+	0x30ff, 0x30f9, 0x30f7, 0x30f7, 0x30f7, 0x30f7, 0x30f7, 0x080c,
+	0x252b, 0x6820, 0xd084, 0x1118, 0x080c, 0x376c, 0x0030, 0x7058,
+	0x2c50, 0x2060, 0x6800, 0x6002, 0x2a60, 0x3208, 0xa18c, 0x0600,
+	0x0118, 0x2021, 0x4557, 0x0010, 0x2021, 0x4597, 0x2404, 0xa005,
+	0x0110, 0x2020, 0x0cd8, 0x2d22, 0x206b, 0x0000, 0x0005, 0x080c,
+	0x3772, 0x080c, 0x3786, 0x6008, 0xc0cc, 0x600a, 0x682b, 0x0000,
+	0x789b, 0x000e, 0x6f14, 0x6938, 0x691a, 0x6944, 0x6916, 0x3208,
+	0xa18c, 0x0600, 0x0118, 0x2009, 0x0000, 0x0010, 0x2009, 0x0001,
+	0x080c, 0x428b, 0xd6dc, 0x01c8, 0x691c, 0xc1ed, 0x691e, 0x6828,
+	0xa082, 0x000e, 0x0290, 0x6848, 0xa084, 0x000f, 0xa086, 0x000b,
+	0x1160, 0x685c, 0xa086, 0x0047, 0x1140, 0x2001, 0x4501, 0x2004,
+	0xd0ac, 0x1118, 0x2700, 0x080c, 0x2454, 0x6818, 0xd0fc, 0x0140,
+	0x681b, 0x0000, 0x7868, 0xa08c, 0x00ff, 0x0110, 0x681b, 0x001e,
+	0xb284, 0x0600, 0x1118, 0x2021, 0x4597, 0x0010, 0x2021, 0x4557,
+	0x6800, 0x2022, 0x6a3c, 0x6940, 0x6a32, 0x692e, 0x68c0, 0x2060,
+	0x6000, 0xd0a4, 0x0580, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051,
+	0x0020, 0x00d6, 0x00f6, 0x0156, 0x0146, 0x2079, 0x4500, 0x080c,
+	0x1b77, 0x014e, 0x015e, 0x00fe, 0x70c8, 0x2010, 0x2009, 0x0101,
+	0x0026, 0x2204, 0xa06d, 0x0140, 0x6814, 0xa706, 0x0110, 0x6800,
+	0x0cc8, 0x6820, 0xc0d5, 0x6822, 0x002e, 0x8210, 0x8109, 0x1d80,
+	0x00de, 0x7063, 0x0003, 0x707b, 0x0000, 0x7772, 0x707f, 0x000f,
+	0x71d0, 0xc1c4, 0x71d2, 0x6818, 0xa086, 0x0002, 0x1138, 0x6817,
+	0x0000, 0x682b, 0x0000, 0x681c, 0xc0ec, 0x681e, 0x080c, 0x1d89,
+	0x0804, 0x257f, 0x7cd8, 0x7ddc, 0x7fd0, 0x080c, 0x3068, 0x682b,
+	0x0000, 0x789b, 0x000e, 0x6f14, 0x080c, 0x3c10, 0xa08c, 0x00ff,
+	0x6916, 0x6818, 0xd0fc, 0x0110, 0x7044, 0x681a, 0xa68c, 0xdf00,
+	0x691e, 0x7063, 0x0000, 0x0804, 0x257f, 0x7000, 0xa005, 0x1110,
+	0x0804, 0x257f, 0xa006, 0x080c, 0x3ed9, 0x6920, 0xd1ac, 0x1110,
+	0x681b, 0x0014, 0xa68c, 0xdf00, 0x691e, 0x682b, 0x0000, 0x6820,
+	0xa084, 0x00ff, 0x6822, 0x7000, 0x0002, 0x257f, 0x31e7, 0x31e7,
+	0x31ea, 0x31ea, 0x31ea, 0x31e5, 0x31e5, 0x080c, 0x252b, 0x6818,
+	0x0804, 0x2ea4, 0x6008, 0xc0a4, 0x600a, 0x6817, 0x0000, 0x0804,
+	0x373a, 0x2300, 0x0002, 0x31f6, 0x31f8, 0x3241, 0x080c, 0x252b,
+	0xd6fc, 0x1904, 0x2cdf, 0x7000, 0xa00d, 0x0002, 0x257f, 0x3208,
+	0x3208, 0x3231, 0x3208, 0x323e, 0x3206, 0x3206, 0x080c, 0x252b,
+	0xa684, 0x0060, 0x0530, 0xa086, 0x0060, 0x1508, 0xc6ac, 0xc6f4,
+	0xc6ed, 0x7e5a, 0x681c, 0xc0ac, 0x681e, 0xa186, 0x0002, 0x0148,
+	0x080c, 0x3ed9, 0x69ac, 0x68b0, 0xa115, 0x0118, 0x080c, 0x41ad,
+	0x0010, 0x080c, 0x4180, 0x781b, 0x0083, 0x71d0, 0xd1b4, 0x1904,
+	0x257c, 0x70a0, 0xa086, 0x0001, 0x1904, 0x25c0, 0x0005, 0xd6ec,
+	0x09f8, 0x6818, 0xd0fc, 0x0150, 0xd6f4, 0x1130, 0x681b, 0x0015,
+	0x781b, 0x0083, 0x0804, 0x257c, 0x681b, 0x0007, 0x080c, 0x3bb7,
+	0x0005, 0x080c, 0x252b, 0x2300, 0x0002, 0x324a, 0x326c, 0x32c3,
+	0x080c, 0x252b, 0x7000, 0x0002, 0x3254, 0x3256, 0x325d, 0x3254,
+	0x3254, 0x3254, 0x3254, 0x3254, 0x080c, 0x252b, 0x69ac, 0x68b0,
+	0xa115, 0x0118, 0x080c, 0x41ad, 0x0010, 0x080c, 0x4180, 0x681c,
+	0xc0b4, 0x681e, 0x70d0, 0xd0b4, 0x1904, 0x257c, 0x70a0, 0xa086,
+	0x0001, 0x1904, 0x25c0, 0x0005, 0xd6fc, 0x1904, 0x32b3, 0x7000,
+	0xa00d, 0x0002, 0x257f, 0x3282, 0x327c, 0x32ab, 0x3282, 0x32b0,
+	0x327a, 0x327a, 0x080c, 0x252b, 0x6894, 0x78d6, 0x78de, 0x6898,
+	0x78d2, 0x78da, 0xa684, 0x0060, 0x0530, 0xa086, 0x0060, 0x1508,
+	0xa6b4, 0xbfbf, 0xc6ed, 0x7e5a, 0xa186, 0x0002, 0x0148, 0x080c,
+	0x3ed9, 0x69ac, 0x68b0, 0xa115, 0x0118, 0x080c, 0x41ad, 0x0010,
+	0x080c, 0x4180, 0x781b, 0x0083, 0x681c, 0xc0b4, 0x681e, 0x71d0,
+	0xd1b4, 0x1904, 0x257c, 0x70a0, 0xa086, 0x0001, 0x1904, 0x25c0,
+	0x0005, 0xd6ec, 0x09f8, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x0007,
+	0x781b, 0x00fb, 0x0005, 0xc6fc, 0x7e5a, 0x7adc, 0x79d8, 0x6b98,
+	0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae, 0x79d2,
+	0x781b, 0x0083, 0x0005, 0xd6dc, 0x0130, 0x782b, 0x3009, 0x781b,
+	0x0083, 0x0804, 0x257c, 0x7884, 0xc0ac, 0x7886, 0x78e4, 0xa084,
+	0x0008, 0x1150, 0xa484, 0x0200, 0x0108, 0xc6f5, 0xc6dd, 0x7e5a,
+	0x781b, 0x0083, 0x0804, 0x257c, 0x6820, 0xc095, 0x6822, 0x080c,
+	0x3ba2, 0xc6dd, 0x080c, 0x39ff, 0x781b, 0x0082, 0x0804, 0x257c,
+	0x2300, 0x0002, 0x32ed, 0x32ef, 0x32f1, 0x080c, 0x252b, 0x0804,
+	0x39f9, 0x7d98, 0xd6d4, 0x11f8, 0x79e4, 0xd1ac, 0x0130, 0x78ec,
+	0xa084, 0x0003, 0x0110, 0x782b, 0x3009, 0x789b, 0x0060, 0x78ab,
+	0x0000, 0xa684, 0xfffb, 0x785a, 0x7d9a, 0x79e4, 0xd1ac, 0x0120,
+	0x78ec, 0xa084, 0x0003, 0x1120, 0x2001, 0x0014, 0x0804, 0x2ea4,
+	0xa184, 0x0007, 0x04c2, 0x7a90, 0xa294, 0x0007, 0x789b, 0x0060,
+	0x79a8, 0x81ff, 0x0568, 0x789b, 0x0080, 0x7ba8, 0xa384, 0x0001,
+	0x11d0, 0x7ba8, 0x7ba8, 0xa386, 0x0004, 0x1118, 0x2009, 0xffdf,
+	0x0058, 0xa386, 0x0001, 0x1118, 0x2009, 0xfff7, 0x0028, 0xa386,
+	0x0003, 0x1148, 0x2009, 0xffef, 0x00c6, 0x7054, 0x2060, 0x6004,
+	0xa104, 0x6006, 0x00ce, 0x789b, 0x0060, 0x78ab, 0x0000, 0xa684,
+	0xfffb, 0x785a, 0x782b, 0x3009, 0x6920, 0xa18c, 0xecff, 0x6922,
+	0x7d9a, 0x0804, 0x3bab, 0x2b90, 0x2b99, 0x3355, 0x335b, 0x3353,
+	0x3353, 0x3bab, 0x3bab, 0x080c, 0x252b, 0x6920, 0xa18c, 0xfcff,
+	0x6922, 0x0804, 0x3bb1, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0804,
+	0x3bab, 0x79e4, 0xa184, 0x0030, 0x0120, 0x78ec, 0xa084, 0x0003,
+	0x1570, 0x7000, 0xa086, 0x0004, 0x1190, 0x7060, 0xa086, 0x0002,
+	0x1130, 0x2011, 0x0002, 0x2019, 0x0000, 0x0804, 0x2a4d, 0x7060,
+	0xa086, 0x0006, 0x0db0, 0x7060, 0xa086, 0x0004, 0x0d90, 0x7000,
+	0xa086, 0x0000, 0x0904, 0x257c, 0x6920, 0xa184, 0x0420, 0x0128,
+	0xc1d4, 0x6922, 0x6818, 0x0804, 0x2ea4, 0x6818, 0xa08e, 0x0002,
+	0x0120, 0xc0fd, 0x681a, 0x2001, 0x0014, 0x0804, 0x2ea4, 0xa184,
+	0x0007, 0x0002, 0x3bab, 0x3bab, 0x33a2, 0x3bab, 0x3bef, 0x3bef,
+	0x3bab, 0x3bab, 0xd6bc, 0x0570, 0x7180, 0x81ff, 0x0558, 0xa182,
+	0x000d, 0x1318, 0x7083, 0x0000, 0x0028, 0xa182, 0x000c, 0x7082,
+	0x2009, 0x000c, 0x789b, 0x0061, 0x79aa, 0x0156, 0x0136, 0x0146,
+	0x7084, 0x8114, 0xa210, 0x7286, 0xa080, 0x000b, 0xad00, 0x2098,
+	0xb284, 0x0600, 0x0118, 0x20a1, 0x022b, 0x0010, 0x20a1, 0x012b,
+	0x789b, 0x0000, 0x8108, 0x81ac, 0x53a6, 0x014e, 0x013e, 0x015e,
+	0x0804, 0x3bb1, 0xd6d4, 0x1904, 0x3415, 0x6820, 0xd084, 0x0904,
+	0x3bb1, 0xa68c, 0x0060, 0xa684, 0x0060, 0x0120, 0xa086, 0x0060,
+	0x1108, 0xc1f5, 0xc194, 0x795a, 0x69b6, 0x789b, 0x0060, 0x78ab,
+	0x0000, 0x789b, 0x0061, 0x6818, 0xc0fd, 0x681a, 0x78aa, 0x8008,
+	0x810c, 0x0904, 0x379b, 0xa18c, 0x00f8, 0x1904, 0x379b, 0x0156,
+	0x0136, 0x0146, 0x0016, 0x20a1, 0x012b, 0x3208, 0xa18c, 0x0600,
+	0x0110, 0x20a1, 0x022b, 0x001e, 0x789b, 0x0000, 0x8000, 0x80ac,
+	0xad80, 0x000b, 0x2098, 0x53a6, 0x014e, 0x013e, 0x015e, 0x6814,
+	0xc0fc, 0x8007, 0x7882, 0x0804, 0x3bb1, 0x6818, 0xd0fc, 0x0110,
+	0x681b, 0x0008, 0x080c, 0x39ff, 0x781b, 0x00ed, 0x0005, 0x2300,
+	0x0002, 0x3426, 0x34e8, 0x3424, 0x080c, 0x252b, 0x7cd8, 0x7ddc,
+	0x7fd0, 0x82ff, 0x1528, 0x7200, 0xa286, 0x0003, 0x0904, 0x2e72,
+	0x71d0, 0xd1bc, 0x11f8, 0xd1b4, 0x01e8, 0x2001, 0x4501, 0x2004,
+	0xd0c4, 0x11c0, 0x00d6, 0x783b, 0x8800, 0x781b, 0x0059, 0x70b8,
+	0xa06d, 0x68b4, 0xc0a5, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898,
+	0x78d2, 0x78da, 0xc1b4, 0x71d2, 0x7003, 0x0030, 0x00de, 0x0030,
+	0x7200, 0x0020, 0x783b, 0x1800, 0x781b, 0x0057, 0xa284, 0x000f,
+	0x0002, 0x34d3, 0x3490, 0x3463, 0x2ea1, 0x3461, 0x34d3, 0x3461,
+	0x3461, 0x080c, 0x252b, 0x681c, 0xd0ec, 0x0118, 0x6008, 0xc08d,
+	0x600a, 0x6920, 0xc185, 0x6922, 0x6800, 0x6006, 0xa005, 0x1108,
+	0x6002, 0x6008, 0xc0d4, 0x600a, 0x681c, 0xa084, 0x000e, 0x1148,
+	0xb284, 0x0600, 0x0118, 0x2009, 0x8bc0, 0x0040, 0x2009, 0x8cd0,
+	0x0028, 0x7030, 0x68ba, 0x713c, 0x70c8, 0xa108, 0x2104, 0x6802,
+	0x2d0a, 0x715a, 0xd6dc, 0x1120, 0xc6fc, 0x6eb6, 0x0804, 0x34d3,
+	0x6eb6, 0xa684, 0x0060, 0x1120, 0xa684, 0x7fff, 0x68b6, 0x04d8,
 	0xd6dc, 0x1150, 0xa684, 0x7fff, 0x68b6, 0x6894, 0x68a6, 0x6898,
-	0x68aa, 0x080c, 0x3d52, 0x0478, 0xd6ac, 0x0140, 0xa006, 0x080c,
-	0x3d52, 0x2408, 0x2510, 0x69aa, 0x6aa6, 0x0068, 0x2408, 0x2510,
+	0x68aa, 0x080c, 0x3ed9, 0x0478, 0xd6ac, 0x0140, 0xa006, 0x080c,
+	0x3ed9, 0x2408, 0x2510, 0x69aa, 0x6aa6, 0x0068, 0x2408, 0x2510,
 	0x2700, 0x8007, 0xa084, 0x007f, 0xa108, 0xa291, 0x0000, 0x69aa,
-	0x6aa6, 0x080c, 0x3d52, 0xd6fc, 0x01b0, 0xa684, 0x7fff, 0x68b6,
+	0x6aa6, 0x080c, 0x3ed9, 0xd6fc, 0x01b0, 0xa684, 0x7fff, 0x68b6,
 	0x2510, 0x2408, 0xd6ac, 0x1138, 0x2700, 0x8007, 0xa084, 0x007f,
 	0xa108, 0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94,
-	0x2200, 0xa303, 0x68ae, 0x7000, 0xa086, 0x0030, 0x1904, 0x248f,
-	0x7003, 0x0002, 0x70bc, 0xa06d, 0x68bc, 0x7042, 0x70b8, 0xa065,
-	0x68c0, 0x705a, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x0005,
+	0x2200, 0xa303, 0x68ae, 0x7000, 0xa086, 0x0030, 0x1904, 0x257f,
+	0x7003, 0x0002, 0x70b8, 0xa06d, 0x68bc, 0x703e, 0x70b4, 0xa065,
+	0x68c0, 0x7056, 0x2d00, 0x704a, 0xad80, 0x0009, 0x7042, 0x0005,
 	0xa586, 0x8800, 0x1148, 0x7003, 0x0000, 0x6018, 0x8001, 0x601a,
-	0x6008, 0xa084, 0xfbef, 0x600a, 0x0804, 0x3831, 0x7047, 0x0000,
-	0xa282, 0x0006, 0x0310, 0x080c, 0x243b, 0x2300, 0x0002, 0x33b2,
-	0x33e4, 0x340f, 0x2200, 0x0002, 0x33ba, 0x3831, 0x33bc, 0x33ba,
-	0x343f, 0x349d, 0x080c, 0x243b, 0x7003, 0x0005, 0xb284, 0x0600,
-	0x0118, 0x2001, 0x8ae0, 0x0010, 0x2001, 0x8b12, 0x2068, 0x704e,
-	0x0156, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000, 0x1f04, 0x33cb,
+	0x6008, 0xa084, 0xfbef, 0x600a, 0x0804, 0x39f9, 0x7043, 0x0000,
+	0xa282, 0x0006, 0x0310, 0x080c, 0x252b, 0x2300, 0x0002, 0x3502,
+	0x3534, 0x355f, 0x2200, 0x0002, 0x350a, 0x39f9, 0x350c, 0x350a,
+	0x358f, 0x35f9, 0x080c, 0x252b, 0x7003, 0x0005, 0xb284, 0x0600,
+	0x0118, 0x2001, 0x8ce0, 0x0010, 0x2001, 0x8d12, 0x2068, 0x704a,
+	0x0156, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000, 0x1f04, 0x351b,
 	0x015e, 0xb284, 0x0600, 0x0118, 0x6817, 0x0000, 0x0010, 0x6817,
-	0x8000, 0xad80, 0x0009, 0x7046, 0x68b7, 0x0700, 0x6823, 0x0800,
-	0x6827, 0x0003, 0x0804, 0x3809, 0x7000, 0xa086, 0x0002, 0x1150,
-	0x080c, 0x35c5, 0x0010, 0x080c, 0x3d52, 0x6008, 0xa084, 0xfbef,
+	0x8000, 0xad80, 0x0009, 0x7042, 0x68b7, 0x0700, 0x6823, 0x0800,
+	0x6827, 0x0003, 0x0804, 0x39d0, 0x7000, 0xa086, 0x0002, 0x1150,
+	0x080c, 0x3786, 0x0010, 0x080c, 0x3ed9, 0x6008, 0xa084, 0xfbef,
 	0x600a, 0x0020, 0x7000, 0xa086, 0x0003, 0x0da8, 0x7003, 0x0005,
-	0xb284, 0x0600, 0x0118, 0x2001, 0x8ae0, 0x0010, 0x2001, 0x8b12,
-	0x2068, 0x704e, 0xad80, 0x0009, 0x7046, 0x2200, 0x0002, 0x3831,
-	0x340d, 0x340d, 0x343f, 0x340d, 0x3831, 0x080c, 0x243b, 0x7000,
-	0xa086, 0x0002, 0x1150, 0x080c, 0x35c5, 0x0010, 0x080c, 0x3d52,
+	0xb284, 0x0600, 0x0118, 0x2001, 0x8ce0, 0x0010, 0x2001, 0x8d12,
+	0x2068, 0x704a, 0xad80, 0x0009, 0x7042, 0x2200, 0x0002, 0x39f9,
+	0x355d, 0x355d, 0x358f, 0x355d, 0x39f9, 0x080c, 0x252b, 0x7000,
+	0xa086, 0x0002, 0x1150, 0x080c, 0x3786, 0x0010, 0x080c, 0x3ed9,
 	0x6008, 0xa084, 0xfbef, 0x600a, 0x0020, 0x7000, 0xa086, 0x0003,
-	0x0da8, 0x7003, 0x0005, 0xb284, 0x0600, 0x0118, 0x2001, 0x8ae0,
-	0x0010, 0x2001, 0x8b12, 0x2068, 0x704e, 0xad80, 0x0009, 0x7046,
-	0x2200, 0x0002, 0x343a, 0x3438, 0x3438, 0x343a, 0x3438, 0x343a,
-	0x080c, 0x243b, 0x080c, 0x3846, 0x781b, 0x0082, 0x0005, 0x7000,
-	0xa086, 0x0002, 0x1158, 0x70d4, 0xc0b5, 0x70d6, 0x2c00, 0x70ba,
-	0x2d00, 0x70be, 0x0038, 0x080c, 0x3d52, 0x0020, 0x7000, 0xa086,
+	0x0da8, 0x7003, 0x0005, 0xb284, 0x0600, 0x0118, 0x2001, 0x8ce0,
+	0x0010, 0x2001, 0x8d12, 0x2068, 0x704a, 0xad80, 0x0009, 0x7042,
+	0x2200, 0x0002, 0x358a, 0x3588, 0x3588, 0x358a, 0x3588, 0x358a,
+	0x080c, 0x252b, 0x080c, 0x3a0e, 0x781b, 0x0082, 0x0005, 0x7000,
+	0xa086, 0x0002, 0x1158, 0x70d0, 0xc0b5, 0x70d2, 0x2c00, 0x70b6,
+	0x2d00, 0x70ba, 0x0038, 0x080c, 0x3ed9, 0x0020, 0x7000, 0xa086,
 	0x0003, 0x0dc8, 0x7003, 0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b,
-	0x0018, 0x7ca8, 0xa484, 0x001f, 0xa215, 0x2069, 0x89c0, 0xb284,
-	0x0600, 0x1118, 0xc2fd, 0x2069, 0x8ad0, 0x2d04, 0x2d08, 0x715e,
+	0x0018, 0x7ca8, 0xa484, 0x001f, 0xa215, 0x2069, 0x8bc0, 0xb284,
+	0x0600, 0x1118, 0xc2fd, 0x2069, 0x8cd0, 0x2d04, 0x2d08, 0x715a,
 	0xa06d, 0x0128, 0x6814, 0xa206, 0x0500, 0x6800, 0x0cb8, 0x7003,
-	0x0005, 0xd2fc, 0x1118, 0x2001, 0x8ae0, 0x0010, 0x2001, 0x8b12,
-	0x2068, 0x704e, 0x0156, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000,
-	0x1f04, 0x347d, 0x015e, 0xad80, 0x0009, 0x7046, 0x6a16, 0x68b7,
+	0x0005, 0xd2fc, 0x1118, 0x2001, 0x8ce0, 0x0010, 0x2001, 0x8d12,
+	0x2068, 0x704a, 0x0156, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000,
+	0x1f04, 0x35cd, 0x015e, 0xad80, 0x0009, 0x7042, 0x6a16, 0x68b7,
 	0x0700, 0x6823, 0x0800, 0x6827, 0x0003, 0x6eb4, 0x7e5a, 0x6920,
-	0xa184, 0x0c00, 0x0904, 0x3507, 0x681b, 0x0005, 0xc1ad, 0xc1d4,
-	0x6922, 0x080c, 0x383d, 0x0804, 0x3507, 0x7200, 0xa286, 0x0002,
-	0x1158, 0x70d4, 0xc0b5, 0x70d6, 0x2c00, 0x70ba, 0x2d00, 0x70be,
-	0x0030, 0x080c, 0x3d52, 0x0018, 0xa286, 0x0003, 0x0dd0, 0x7003,
-	0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b, 0x0018, 0x7ca8, 0xa484,
-	0x001f, 0xa215, 0xb284, 0x0600, 0x1108, 0xc2fd, 0x79a8, 0x79a8,
-	0xa18c, 0x00ff, 0x70cc, 0xa168, 0x2d04, 0x2d08, 0x715e, 0xa06d,
-	0x0128, 0x6814, 0xa206, 0x0538, 0x6800, 0x0cb8, 0x7003, 0x0005,
-	0xb284, 0x0600, 0x0118, 0x2001, 0x8ae0, 0x0010, 0x2001, 0x8b12,
-	0x2068, 0x704e, 0x0156, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000,
-	0x1f04, 0x34dd, 0x015e, 0xb284, 0x0600, 0x0110, 0xc2fc, 0x0008,
-	0xc2fd, 0x6a16, 0xad80, 0x0009, 0x7046, 0x68b7, 0x0700, 0x6823,
-	0x0800, 0x6827, 0x0003, 0x6eb4, 0x6920, 0xa184, 0x0c00, 0x0178,
-	0xd0dc, 0x0118, 0x080c, 0x3843, 0x0050, 0x681b, 0x0005, 0xc1ad,
-	0xc1d4, 0x6922, 0x080c, 0x383d, 0x707f, 0x0000, 0x0000, 0xa6ac,
-	0x0060, 0x05c8, 0x6b98, 0x6c94, 0x69ac, 0x68b0, 0xa105, 0x11c0,
-	0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0xa6b4, 0xb7ff, 0xa586, 0x0060,
-	0x0550, 0xc6ed, 0x7e5a, 0x2009, 0x0083, 0xd69c, 0x0128, 0x2009,
-	0x0082, 0x2019, 0x0000, 0x2320, 0x791a, 0x080c, 0x3fb8, 0x0418,
-	0x68b0, 0xa31a, 0x2100, 0xa423, 0x2400, 0xa305, 0x01a0, 0x7bd2,
-	0x7bda, 0x7cd6, 0x7cde, 0x68b0, 0xc6f4, 0x7e5a, 0x2011, 0x0083,
-	0xd69c, 0x0128, 0x2011, 0x0082, 0x2019, 0x0000, 0x2320, 0x7a1a,
-	0x080c, 0x3fe5, 0x0040, 0x7e5a, 0x2009, 0x0083, 0xd69c, 0x0110,
-	0x2009, 0x0082, 0x791a, 0x68c0, 0x705a, 0x2d00, 0x704e, 0x68c4,
-	0x2060, 0x71d4, 0xd1b4, 0x1904, 0x248c, 0x2300, 0xa405, 0x0904,
-	0x248c, 0x70a4, 0xa086, 0x0001, 0x1904, 0x24ce, 0x0005, 0x6020,
+	0xa184, 0x0c00, 0x0904, 0x3670, 0x7060, 0xa086, 0x0006, 0x1128,
+	0x7070, 0xa206, 0x1110, 0x7062, 0x707a, 0x681b, 0x0005, 0xc1ad,
+	0x681b, 0x0005, 0xc1ad, 0xc1d4, 0x6922, 0x080c, 0x3a05, 0x0804,
+	0x3670, 0x7200, 0xa286, 0x0002, 0x1158, 0x70d0, 0xc0b5, 0x70d2,
+	0x2c00, 0x70b6, 0x2d00, 0x70ba, 0x0030, 0x080c, 0x3ed9, 0x0018,
+	0xa286, 0x0003, 0x0dd0, 0x7003, 0x0001, 0x7a80, 0xa294, 0x0f00,
+	0x789b, 0x0018, 0x7ca8, 0xa484, 0x001f, 0xa215, 0xb284, 0x0600,
+	0x1108, 0xc2fd, 0x79a8, 0x79a8, 0xa18c, 0x00ff, 0x2118, 0x70c8,
+	0xa168, 0x2d04, 0x2d08, 0x715a, 0xa06d, 0x0128, 0x6814, 0xa206,
+	0x0538, 0x6800, 0x0cb8, 0x7003, 0x0005, 0xb284, 0x0600, 0x0118,
+	0x2001, 0x8ce0, 0x0010, 0x2001, 0x8d12, 0x2068, 0x704a, 0x0156,
+	0x20a9, 0x0032, 0x2003, 0x0000, 0x8000, 0x1f04, 0x363a, 0x015e,
+	0xb284, 0x0600, 0x0110, 0xc2fc, 0x0008, 0xc2fd, 0x6a16, 0xad80,
+	0x0009, 0x7042, 0x68b7, 0x0700, 0x6823, 0x0800, 0x6827, 0x0003,
+	0x6eb4, 0x6920, 0xa184, 0x0c00, 0x01d8, 0xd0dc, 0x0178, 0x7060,
+	0xa086, 0x0004, 0x1140, 0x7070, 0xa206, 0x1128, 0x7074, 0xa306,
+	0x1110, 0x7062, 0x707a, 0x080c, 0x3a0b, 0x0050, 0x681b, 0x0005,
+	0xc1ad, 0xc1d4, 0x6922, 0x080c, 0x3a05, 0x707b, 0x0000, 0x0000,
+	0xc6ec, 0xa6ac, 0x0060, 0x0904, 0x36b7, 0x6b98, 0x6c94, 0x69ac,
+	0x68b0, 0xa105, 0x11e0, 0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0xa586,
+	0x0060, 0x05c8, 0xd6f4, 0x1108, 0xc6ed, 0xa6b4, 0xb7ff, 0x7e5a,
+	0x2009, 0x0083, 0xd69c, 0x0128, 0x2009, 0x0082, 0x2019, 0x0000,
+	0x2320, 0x791a, 0xd6ec, 0x0588, 0x080c, 0x4180, 0x0470, 0x68b0,
+	0xa31a, 0x2100, 0xa423, 0x2400, 0xa305, 0x01f8, 0x7bd2, 0x7bda,
+	0x7cd6, 0x7cde, 0x68b0, 0xd6f4, 0x1108, 0xc6ed, 0xc6f4, 0x7e5a,
+	0x2011, 0x0083, 0xd69c, 0x0128, 0x2011, 0x0082, 0x2019, 0x0000,
+	0x2320, 0x7a1a, 0xd6ec, 0x0188, 0x080c, 0x41ad, 0x0070, 0x2019,
+	0x0000, 0x2320, 0x0010, 0xa6b4, 0xb7ff, 0x7e5a, 0x2009, 0x0083,
+	0xd69c, 0x0110, 0x2009, 0x0082, 0x791a, 0x68c0, 0x7056, 0x2d00,
+	0x704a, 0x68c4, 0x2060, 0x71d0, 0x2001, 0x4501, 0x2004, 0xd0c4,
+	0x15c8, 0x70d4, 0xa02d, 0x01b8, 0xd1bc, 0x0548, 0x7a80, 0xa294,
+	0x0f00, 0x70d8, 0xa206, 0x0118, 0x78e0, 0xa504, 0x1558, 0x70d6,
+	0xc1bc, 0x71d2, 0x0438, 0x2031, 0x0001, 0x852c, 0x0218, 0x8633,
+	0x8210, 0x0cd8, 0x0005, 0x7de0, 0xa594, 0xff00, 0x0130, 0x2011,
+	0x0008, 0x852f, 0x0c81, 0x8637, 0x0008, 0x0c69, 0x8217, 0x7880,
+	0xa084, 0x0f00, 0xa206, 0x0170, 0x72da, 0x76d6, 0x0058, 0x7a80,
+	0xa294, 0x0f00, 0x70d8, 0xa236, 0x0dc0, 0x78e0, 0xa534, 0x0da8,
+	0xc1bd, 0x71d2, 0xd1b4, 0x1904, 0x257c, 0x2300, 0xa405, 0x0904,
+	0x257c, 0x70a0, 0xa086, 0x0001, 0x1904, 0x25c0, 0x0005, 0x6020,
 	0xa005, 0x0150, 0x8001, 0x6022, 0x6008, 0xa085, 0x0008, 0x600a,
-	0x700f, 0x0100, 0x702c, 0x6026, 0x0005, 0xa006, 0x080c, 0x3d52,
+	0x700f, 0x0100, 0x702c, 0x6026, 0x0005, 0xa006, 0x080c, 0x3ed9,
+	0x7000, 0xa086, 0x0002, 0x0120, 0x7060, 0xa086, 0x0005, 0x1150,
 	0x682b, 0x0000, 0x6817, 0x0000, 0x681b, 0x0001, 0x6823, 0x0040,
-	0x681f, 0x0100, 0x7000, 0xa084, 0x000f, 0x0002, 0x248f, 0x358b,
-	0x3588, 0x35a7, 0x3594, 0x248f, 0x3586, 0x3586, 0x080c, 0x243b,
-	0x0441, 0x0409, 0x0028, 0x0429, 0x705c, 0x2060, 0x6800, 0x6002,
-	0x080c, 0x1d3d, 0x0804, 0x248f, 0x7064, 0x7067, 0x0000, 0x7083,
-	0x0000, 0x0002, 0x35a3, 0x35a3, 0x35a2, 0x35a2, 0x35a2, 0x35a3,
-	0x35a2, 0x35a3, 0x2971, 0x7067, 0x0000, 0x0804, 0x248f, 0x681b,
-	0x0000, 0x0804, 0x3012, 0x6800, 0xa005, 0x1108, 0x6002, 0x6006,
-	0x0005, 0x6410, 0x84ff, 0x0168, 0x2009, 0x4302, 0x2104, 0x8001,
-	0x200a, 0x8421, 0x6412, 0x1128, 0x2021, 0x4304, 0x2404, 0xc0a5,
-	0x2022, 0x6008, 0xc0a4, 0x600a, 0x0005, 0x6018, 0xa005, 0x0110,
-	0x8001, 0x601a, 0x0005, 0x080c, 0x3aa0, 0x681b, 0x0018, 0x04a0,
-	0x080c, 0x3aa0, 0x681b, 0x0019, 0x0478, 0x080c, 0x3aa0, 0x681b,
-	0x001a, 0x0450, 0x080c, 0x3aa0, 0x681b, 0x0003, 0x0428, 0x7774,
-	0x080c, 0x396d, 0x7178, 0xa18c, 0x00ff, 0x3210, 0xa294, 0x0600,
-	0x0118, 0xa1e8, 0x88c0, 0x0010, 0xa1e8, 0x89d0, 0x2d04, 0x2d08,
-	0x2068, 0xa005, 0x1118, 0x707e, 0x0804, 0x248f, 0x6814, 0xc0fc,
-	0x7274, 0xc2fc, 0xa206, 0x0110, 0x6800, 0x0c88, 0x6800, 0x200a,
-	0x681b, 0x0005, 0x707f, 0x0000, 0x080c, 0x35b1, 0x6820, 0xd084,
-	0x1110, 0x080c, 0x35ab, 0x080c, 0x35c5, 0x681f, 0x0000, 0x6823,
-	0x0020, 0x080c, 0x1d3d, 0x0804, 0x248f, 0xa282, 0x0003, 0x1904,
-	0x380d, 0x7da8, 0xa5ac, 0x00ff, 0x7ea8, 0xa6b4, 0x00ff, 0x6920,
-	0xc1bd, 0x6922, 0xd1c4, 0x0590, 0xc1c4, 0x6922, 0xa6b4, 0x00ff,
-	0x0510, 0xa682, 0x001c, 0x0218, 0x0110, 0x2031, 0x001c, 0x852b,
-	0x852b, 0x2041, 0x0000, 0x080c, 0x38c6, 0x0118, 0x080c, 0x36f6,
-	0x00a0, 0x080c, 0x3892, 0x080c, 0x36f3, 0x6920, 0xc1c5, 0x6922,
+	0x681f, 0x0100, 0x7000, 0xa084, 0x000f, 0x0002, 0x257f, 0x374b,
+	0x3748, 0x3768, 0x3754, 0x257f, 0x3746, 0x3746, 0x080c, 0x252b,
+	0x0449, 0x0411, 0x0028, 0x0431, 0x7058, 0x2060, 0x6800, 0x6002,
+	0x080c, 0x1d89, 0x0804, 0x257f, 0x7060, 0x7063, 0x0000, 0x707f,
+	0x0000, 0x0002, 0x3764, 0x3764, 0x3762, 0x3762, 0x3762, 0x3764,
+	0x3762, 0x3764, 0x0804, 0x2a62, 0x7063, 0x0000, 0x0804, 0x257f,
+	0x681b, 0x0000, 0x0804, 0x3117, 0x6800, 0xa005, 0x1108, 0x6002,
+	0x6006, 0x0005, 0x6410, 0x84ff, 0x0168, 0x2009, 0x4502, 0x2104,
+	0x8001, 0x200a, 0x8421, 0x6412, 0x1128, 0x2021, 0x4504, 0x2404,
+	0xc0a5, 0x2022, 0x6008, 0xc0a4, 0x600a, 0x0005, 0x6018, 0xa005,
+	0x0110, 0x8001, 0x601a, 0x0005, 0x080c, 0x3c0c, 0x681b, 0x0018,
+	0x0490, 0x080c, 0x3c0c, 0x681b, 0x0019, 0x0468, 0x080c, 0x3c0c,
+	0x681b, 0x001a, 0x0440, 0x080c, 0x3c0c, 0x681b, 0x0003, 0x0418,
+	0x7770, 0x080c, 0x3b35, 0x7174, 0xa18c, 0x00ff, 0x3210, 0xa294,
+	0x0600, 0x0118, 0xa1e8, 0x8ac0, 0x0010, 0xa1e8, 0x8bd0, 0x2d04,
+	0x2d08, 0x2068, 0xa005, 0x1118, 0x707a, 0x0804, 0x257f, 0x6814,
+	0x7270, 0xa206, 0x0110, 0x6800, 0x0c98, 0x6800, 0x200a, 0x681b,
+	0x0005, 0x707b, 0x0000, 0x080c, 0x3772, 0x6820, 0xd084, 0x1110,
+	0x080c, 0x376c, 0x080c, 0x3786, 0x681f, 0x0000, 0x6823, 0x0020,
+	0x080c, 0x1d89, 0x0804, 0x257f, 0xa282, 0x0003, 0x1904, 0x39d5,
+	0x7da8, 0xa5ac, 0x00ff, 0x7ea8, 0xa6b4, 0x00ff, 0x6920, 0xc1bd,
+	0x6922, 0xd1c4, 0x05b0, 0xc1c4, 0x6922, 0xa6b4, 0x00ff, 0x0530,
+	0xa682, 0x001c, 0x0218, 0x0110, 0x2031, 0x001c, 0xa686, 0x0010,
+	0x1108, 0x8630, 0x852b, 0x852b, 0x2041, 0x0000, 0x080c, 0x3a8e,
+	0x0118, 0x080c, 0x38bd, 0x00a0, 0x080c, 0x3a5a, 0x080c, 0x38ba,
+	0x6920, 0xc1c5, 0x6922, 0x7e58, 0xc695, 0x7e5a, 0xd6d4, 0x1118,
+	0x781b, 0x006e, 0x0005, 0x781b, 0x0082, 0x0005, 0x080c, 0x38ba,
+	0x7e58, 0xd6d4, 0x1118, 0x781b, 0x0071, 0x0005, 0x781b, 0x0083,
+	0x0005, 0x00c6, 0x7054, 0x2060, 0x6100, 0xd1e4, 0x0598, 0x6208,
+	0x8217, 0xa294, 0x00ff, 0xa282, 0x001c, 0x0218, 0x0110, 0x2011,
+	0x001c, 0x2600, 0xa202, 0x1208, 0x2230, 0xa686, 0x0010, 0x1108,
+	0x8630, 0x6208, 0xa294, 0x00ff, 0x78ec, 0xd0e4, 0x0130, 0xa282,
+	0x000a, 0x1240, 0x2011, 0x000a, 0x0028, 0xa282, 0x000c, 0x1210,
+	0x2011, 0x000c, 0x2200, 0xa502, 0x1208, 0x2228, 0x080c, 0x3a5e,
+	0x852b, 0x852b, 0x2041, 0x0000, 0x080c, 0x3a8e, 0x0118, 0x080c,
+	0x38bd, 0x0020, 0x080c, 0x3a5a, 0x080c, 0x38ba, 0x7858, 0xc095,
+	0x785a, 0x00ce, 0x781b, 0x0082, 0x0005, 0x00c6, 0x2960, 0x6000,
+	0xd0e4, 0x1178, 0x6010, 0xa084, 0x000f, 0x1130, 0x6104, 0xa18c,
+	0xfff5, 0x6106, 0x00ce, 0x0005, 0x2011, 0x0032, 0x2019, 0x0000,
+	0x00f0, 0x68a0, 0xd0cc, 0x1dc0, 0x6208, 0xa294, 0x00ff, 0x78ec,
+	0xd0e4, 0x0130, 0xa282, 0x000b, 0x1218, 0x2011, 0x000a, 0x0028,
+	0xa282, 0x000c, 0x1210, 0x2011, 0x000c, 0x6308, 0x831f, 0xa39c,
+	0x00ff, 0xa382, 0x001c, 0x0218, 0x0110, 0x2019, 0x001c, 0x78ab,
+	0x0001, 0x78ab, 0x0003, 0x78ab, 0x0001, 0x7aaa, 0x7baa, 0xa8c0,
+	0x0005, 0x6820, 0xc0c5, 0x6822, 0x080c, 0x3a18, 0x00ce, 0x0005,
+	0x00c6, 0x2960, 0x6104, 0xa18c, 0xfff5, 0x6106, 0x2011, 0x0032,
+	0x2019, 0x0000, 0x0000, 0x78ab, 0x0001, 0x78ab, 0x0003, 0x78ab,
+	0x0001, 0x7aaa, 0x7baa, 0xa8c0, 0x0005, 0x6820, 0xc0c5, 0x6822,
+	0x00ce, 0x0005, 0xa006, 0x2030, 0x2010, 0x00c6, 0x7154, 0x2160,
+	0x2018, 0x2008, 0xa084, 0xffe0, 0xa635, 0x7e86, 0x6018, 0x789a,
+	0x7eae, 0x6612, 0x78a4, 0xa084, 0x7770, 0xa18c, 0x000f, 0xa105,
+	0x2029, 0x4505, 0x252c, 0xd5cc, 0x0140, 0xd3a4, 0x0110, 0xa085,
+	0x0800, 0xd3fc, 0x0110, 0xa085, 0x8080, 0x78a6, 0x6016, 0x788a,
+	0xa6b4, 0x001f, 0x8637, 0x8204, 0x8004, 0xa605, 0x600e, 0x6004,
+	0xa084, 0xffd5, 0x6006, 0x00ce, 0x0005, 0xa282, 0x0002, 0x1904,
+	0x39de, 0x7aa8, 0x6920, 0xc1bd, 0x6922, 0xd1cc, 0x0568, 0xc1cc,
+	0x6922, 0xa294, 0x00ff, 0xa282, 0x0002, 0x1a04, 0x39d0, 0x080c,
+	0x3963, 0x080c, 0x38ba, 0xa980, 0x0001, 0x200c, 0x080c, 0x3b31,
+	0x080c, 0x385d, 0x88ff, 0x0178, 0x789b, 0x0060, 0x2800, 0x78aa,
 	0x7e58, 0xc695, 0x7e5a, 0xd6d4, 0x1118, 0x781b, 0x006e, 0x0005,
-	0x781b, 0x0082, 0x0005, 0x080c, 0x36f3, 0x7e58, 0xd6d4, 0x1118,
-	0x781b, 0x0071, 0x0005, 0x781b, 0x0083, 0x0005, 0x00c6, 0x7058,
-	0x2060, 0x6100, 0xd1e4, 0x0578, 0x6208, 0x8217, 0xa294, 0x00ff,
-	0xa282, 0x001c, 0x0218, 0x0110, 0x2011, 0x001c, 0x2600, 0xa202,
-	0x1208, 0x2230, 0x6208, 0xa294, 0x00ff, 0x78ec, 0xd0e4, 0x0130,
-	0xa282, 0x000a, 0x1240, 0x2011, 0x000a, 0x0028, 0xa282, 0x000c,
-	0x1210, 0x2011, 0x000c, 0x2200, 0xa502, 0x1208, 0x2228, 0x080c,
-	0x3896, 0x852b, 0x852b, 0x2041, 0x0000, 0x080c, 0x38c6, 0x0118,
-	0x080c, 0x36f6, 0x0020, 0x080c, 0x3892, 0x080c, 0x36f3, 0x7858,
-	0xc095, 0x785a, 0x00ce, 0x781b, 0x0082, 0x0005, 0x00c6, 0x2960,
-	0x6000, 0xd0e4, 0x1178, 0x6010, 0xa084, 0x000f, 0x1130, 0x6104,
-	0xa18c, 0xfff5, 0x6106, 0x00ce, 0x0005, 0x2011, 0x0032, 0x2019,
-	0x0000, 0x00f0, 0x68a0, 0xd0cc, 0x1dc0, 0x6208, 0xa294, 0x00ff,
-	0x78ec, 0xd0e4, 0x0130, 0xa282, 0x000b, 0x1218, 0x2011, 0x000a,
-	0x0028, 0xa282, 0x000c, 0x1210, 0x2011, 0x000c, 0x6308, 0x831f,
-	0xa39c, 0x00ff, 0xa382, 0x001c, 0x0218, 0x0110, 0x2019, 0x001c,
-	0x78ab, 0x0001, 0x78ab, 0x0003, 0x78ab, 0x0001, 0x7aaa, 0x7baa,
-	0xa8c0, 0x0005, 0x6820, 0xc0c5, 0x6822, 0x080c, 0x3850, 0x00ce,
-	0x0005, 0x00c6, 0x2960, 0x6104, 0xa18c, 0xfff5, 0x6106, 0x2011,
-	0x0032, 0x2019, 0x0000, 0x0000, 0x78ab, 0x0001, 0x78ab, 0x0003,
-	0x78ab, 0x0001, 0x7aaa, 0x7baa, 0xa8c0, 0x0005, 0x6820, 0xc0c5,
-	0x6822, 0x00ce, 0x0005, 0xa006, 0x2030, 0x2010, 0x00c6, 0x7158,
-	0x2160, 0x2018, 0x2008, 0xa084, 0xffe0, 0xa635, 0x7e86, 0x6018,
-	0x789a, 0x7eae, 0x6612, 0x78a4, 0xa084, 0x7770, 0xa18c, 0x000f,
-	0xa105, 0x2029, 0x4305, 0x252c, 0xd5cc, 0x0140, 0xd3a4, 0x0110,
-	0xa085, 0x0800, 0xd3fc, 0x0110, 0xa085, 0x8080, 0x78a6, 0x6016,
-	0x788a, 0xa6b4, 0x001f, 0x8637, 0x8204, 0x8004, 0xa605, 0x600e,
-	0x6004, 0xa084, 0xffd5, 0x6006, 0x00ce, 0x0005, 0xa282, 0x0002,
-	0x1904, 0x3816, 0x7aa8, 0x6920, 0xc1bd, 0x6922, 0xd1cc, 0x0568,
-	0xc1cc, 0x6922, 0xa294, 0x00ff, 0xa282, 0x0002, 0x1a04, 0x3809,
-	0x080c, 0x379c, 0x080c, 0x36f3, 0xa980, 0x0001, 0x200c, 0x080c,
-	0x3969, 0x080c, 0x3696, 0x88ff, 0x0178, 0x789b, 0x0060, 0x2800,
-	0x78aa, 0x7e58, 0xc695, 0x7e5a, 0xd6d4, 0x1118, 0x781b, 0x006e,
-	0x0005, 0x781b, 0x0082, 0x0005, 0x7e58, 0xd6d4, 0x1118, 0x781b,
-	0x0071, 0x0005, 0x781b, 0x0083, 0x0005, 0xa282, 0x0002, 0x1218,
-	0xa284, 0x0001, 0x0140, 0x7158, 0xa188, 0x0000, 0x210c, 0xd1ec,
-	0x1110, 0x2011, 0x0000, 0x080c, 0x3883, 0x0471, 0x080c, 0x36f3,
-	0x7858, 0xc095, 0x785a, 0x781b, 0x0082, 0x0005, 0x00c6, 0x0026,
-	0x2960, 0x6000, 0x2011, 0x0001, 0xd0ec, 0x1150, 0x6014, 0xa084,
-	0x0040, 0x1120, 0xc1a4, 0x6106, 0xa006, 0x0088, 0x2011, 0x0000,
-	0x78ab, 0x0001, 0x78ab, 0x0002, 0x78ab, 0x0003, 0x7aaa, 0xa8c0,
-	0x0004, 0x080c, 0x3850, 0x6820, 0xa085, 0x0200, 0x6822, 0x002e,
-	0x00ce, 0x0005, 0x8807, 0xa715, 0x00c6, 0x2009, 0x0000, 0x7058,
-	0x2060, 0x82ff, 0x0110, 0x2009, 0x0040, 0x6018, 0xa080, 0x0002,
-	0x789a, 0x78a4, 0xa084, 0xff9f, 0xa105, 0xc0ec, 0xd0b4, 0x1108,
-	0xc0ed, 0x6100, 0xd1f4, 0x0110, 0xa085, 0x0020, 0x78a6, 0x6016,
-	0x788a, 0x6004, 0xa084, 0xffef, 0x6006, 0x00ce, 0x0005, 0x0006,
-	0x7000, 0xa086, 0x0003, 0x0110, 0x000e, 0x0010, 0x000e, 0x0488,
-	0xd6ac, 0x0578, 0x7888, 0xa084, 0x0040, 0x0558, 0x7bb8, 0x8307,
-	0xa084, 0x007f, 0x1508, 0x8207, 0xa084, 0x00ff, 0xa09e, 0x0001,
-	0x1904, 0x382d, 0xd6f4, 0x11d0, 0x79d8, 0x7adc, 0xa108, 0xa291,
-	0x0000, 0x79d2, 0x79da, 0x7ad6, 0x7ade, 0x080c, 0x4083, 0x781b,
-	0x0080, 0xb284, 0x0600, 0x0118, 0x2001, 0x0000, 0x0010, 0x2001,
-	0x0001, 0x080c, 0x3f50, 0x0005, 0x080c, 0x243b, 0x781b, 0x0080,
-	0x0005, 0x781b, 0x0083, 0x0005, 0x2039, 0x0000, 0x2041, 0x0000,
-	0x2031, 0x0000, 0xa006, 0x2010, 0x080c, 0x36f6, 0x080c, 0x379a,
-	0x7e58, 0x04f9, 0x781b, 0x0082, 0x0005, 0x0cd9, 0x6820, 0xc0c4,
-	0x6822, 0x00c6, 0x7058, 0x2060, 0x0804, 0x3720, 0x0c91, 0x6820,
-	0xc0cc, 0x6822, 0x00c6, 0x7058, 0x2060, 0x0804, 0x37b9, 0x0c49,
-	0x6820, 0xa084, 0xecff, 0x6822, 0x00c6, 0x7058, 0x2060, 0x6004,
+	0x781b, 0x0082, 0x0005, 0x7e58, 0xd6d4, 0x1118, 0x781b, 0x0071,
+	0x0005, 0x781b, 0x0083, 0x0005, 0xa282, 0x0002, 0x1218, 0xa284,
+	0x0001, 0x0140, 0x7154, 0xa188, 0x0000, 0x210c, 0xd1ec, 0x1110,
+	0x2011, 0x0000, 0x080c, 0x3a4b, 0x0471, 0x080c, 0x38ba, 0x7858,
+	0xc095, 0x785a, 0x781b, 0x0082, 0x0005, 0x00c6, 0x0026, 0x2960,
+	0x6000, 0x2011, 0x0001, 0xd0ec, 0x1150, 0x6014, 0xa084, 0x0040,
+	0x1120, 0xc1a4, 0x6106, 0xa006, 0x0088, 0x2011, 0x0000, 0x78ab,
+	0x0001, 0x78ab, 0x0002, 0x78ab, 0x0003, 0x7aaa, 0xa8c0, 0x0004,
+	0x080c, 0x3a18, 0x6820, 0xa085, 0x0200, 0x6822, 0x002e, 0x00ce,
+	0x0005, 0x8807, 0xa715, 0x00c6, 0x2009, 0x0000, 0x7054, 0x2060,
+	0x82ff, 0x0110, 0x2009, 0x0040, 0x6018, 0xa080, 0x0002, 0x789a,
+	0x78a4, 0xa084, 0xff9f, 0xa105, 0xc0ec, 0xd0b4, 0x1108, 0xc0ed,
+	0x6100, 0xd1f4, 0x0110, 0xa085, 0x0020, 0x78a6, 0x6016, 0x788a,
+	0x6004, 0xa084, 0xffef, 0x6006, 0x00ce, 0x0005, 0x0006, 0x7000,
+	0xa086, 0x0003, 0x0110, 0x000e, 0x0010, 0x000e, 0x0488, 0xd6ac,
+	0x0578, 0x7888, 0xa084, 0x0040, 0x0558, 0x7bb8, 0x8307, 0xa084,
+	0x007f, 0x1508, 0x8207, 0xa084, 0x00ff, 0xa09e, 0x0001, 0x1904,
+	0x39f5, 0xd6f4, 0x11d0, 0x79d8, 0x7adc, 0xa108, 0xa291, 0x0000,
+	0x79d2, 0x79da, 0x7ad6, 0x7ade, 0x080c, 0x425d, 0x781b, 0x0080,
+	0xb284, 0x0600, 0x0118, 0x2001, 0x0000, 0x0010, 0x2001, 0x0001,
+	0x080c, 0x4118, 0x0005, 0x080c, 0x252b, 0x781b, 0x0080, 0x0005,
+	0x781b, 0x0083, 0x0005, 0x2039, 0x0000, 0x2041, 0x0000, 0x2031,
+	0x0000, 0xa006, 0x2010, 0x080c, 0x38bd, 0x080c, 0x3961, 0x7e58,
+	0x080c, 0x3a11, 0x781b, 0x0082, 0x0005, 0x0cd1, 0x6820, 0xc0c4,
+	0x6822, 0x00c6, 0x7054, 0x2060, 0x0804, 0x38e7, 0x0c89, 0x6820,
+	0xc0cc, 0x6822, 0x00c6, 0x7054, 0x2060, 0x0804, 0x3980, 0x0c41,
+	0x6820, 0xa084, 0xecff, 0x6822, 0x00c6, 0x7054, 0x2060, 0x6004,
 	0xa084, 0xffc5, 0x6006, 0x00ce, 0x0005, 0x0049, 0x781b, 0x0082,
 	0x0005, 0x6827, 0x0002, 0x0049, 0x781b, 0x0082, 0x0005, 0x2001,
 	0x0005, 0x0088, 0x2001, 0x000c, 0x0070, 0x6820, 0xc0d5, 0x6822,
 	0x2001, 0x0006, 0x0040, 0x2001, 0x000d, 0x0028, 0x2001, 0x0009,
 	0x0010, 0x2001, 0x0007, 0x789b, 0x007e, 0x78aa, 0xc69d, 0x7e5a,
-	0x70d4, 0xd0b4, 0x0168, 0xc0b4, 0x70d6, 0x00c6, 0x70b8, 0xa065,
+	0x70d0, 0xd0b4, 0x0168, 0xc0b4, 0x70d2, 0x00c6, 0x70b4, 0xa065,
 	0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x00ce,
 	0x0005, 0x0076, 0x873f, 0xa7bc, 0x000f, 0x873b, 0x873b, 0x8703,
-	0xb28c, 0x0600, 0x0118, 0xa0e0, 0x47c0, 0x0010, 0xa0e0, 0x4840,
+	0xb28c, 0x0600, 0x0118, 0xa0e0, 0x49c0, 0x0010, 0xa0e0, 0x4a40,
 	0xa7b8, 0x0020, 0x7f9a, 0x79a4, 0xa184, 0x7fe0, 0x78ae, 0x6012,
 	0x79a4, 0xa184, 0x773f, 0x78a6, 0x6016, 0x6004, 0xa085, 0x0038,
 	0x6006, 0x007e, 0x0005, 0x789b, 0x0080, 0x78ab, 0x0001, 0x78ab,
 	0x0002, 0x78ab, 0x0003, 0x7aaa, 0x789b, 0x0060, 0x78ab, 0x0004,
-	0x0804, 0x3850, 0x2031, 0x0000, 0x2029, 0x0032, 0x789b, 0x0080,
+	0x0804, 0x3a18, 0x2031, 0x0000, 0x2029, 0x0032, 0x789b, 0x0080,
 	0x78ab, 0x0001, 0x78ab, 0x0003, 0x78ab, 0x0001, 0x7daa, 0x7eaa,
-	0x789b, 0x0060, 0x78ab, 0x0005, 0x0804, 0x3850, 0x0156, 0x8007,
+	0x789b, 0x0060, 0x78ab, 0x0005, 0x0804, 0x3a18, 0x0156, 0x8007,
 	0xa084, 0x00ff, 0x8003, 0x8003, 0xa080, 0x0020, 0x789a, 0x79a4,
-	0xa18c, 0xffe0, 0x2021, 0x3952, 0x2019, 0x0011, 0x20a9, 0x000e,
+	0xa18c, 0xffe0, 0x2021, 0x3b1a, 0x2019, 0x0011, 0x20a9, 0x000e,
 	0x2011, 0x0032, 0x2404, 0xa084, 0xffe0, 0xa106, 0x0128, 0x8420,
-	0x2300, 0xa210, 0x1f04, 0x38ba, 0x015e, 0x0005, 0x0156, 0x0804,
-	0x3908, 0x2021, 0x3960, 0x20a9, 0x0009, 0x2011, 0x0029, 0xa582,
+	0x2300, 0xa210, 0x1f04, 0x3a82, 0x015e, 0x0005, 0x0156, 0x0804,
+	0x3ad0, 0x2021, 0x3b28, 0x20a9, 0x0009, 0x2011, 0x0029, 0xa582,
 	0x0028, 0x0550, 0x8420, 0x95a9, 0x2011, 0x0033, 0xa582, 0x0033,
 	0x0618, 0x8420, 0x95a9, 0x2019, 0x000a, 0x2011, 0x0065, 0x2200,
-	0xa502, 0x02d0, 0x8420, 0x2300, 0xa210, 0x1f04, 0x38df, 0x015e,
-	0x0088, 0x2021, 0x3952, 0x2019, 0x0011, 0x20a9, 0x000e, 0x2011,
+	0xa502, 0x02d0, 0x8420, 0x2300, 0xa210, 0x1f04, 0x3aa7, 0x015e,
+	0x0088, 0x2021, 0x3b1a, 0x2019, 0x0011, 0x20a9, 0x000e, 0x2011,
 	0x0033, 0x2200, 0xa502, 0x0240, 0x8420, 0x2300, 0xa210, 0x1f04,
-	0x38f1, 0x015e, 0xa006, 0x0005, 0x8211, 0x015e, 0xa582, 0x0064,
+	0x3ab9, 0x015e, 0xa006, 0x0005, 0x8211, 0x015e, 0xa582, 0x0064,
 	0x1220, 0x7808, 0xa085, 0x0070, 0x780a, 0x2404, 0xa005, 0x0005,
-	0xa886, 0x0002, 0x01e8, 0x2021, 0x393e, 0x20a9, 0x000d, 0x2011,
+	0xa886, 0x0002, 0x01e8, 0x2021, 0x3b06, 0x20a9, 0x000d, 0x2011,
 	0x0028, 0xa582, 0x0028, 0x0d48, 0x8420, 0x2019, 0x0019, 0x2011,
 	0x0033, 0x2200, 0xa502, 0x0e00, 0x8420, 0x2300, 0xa210, 0x1f04,
-	0x3919, 0x015e, 0x2011, 0x0184, 0xa582, 0x0185, 0x0ab0, 0x0890,
-	0x2021, 0x394d, 0x20a9, 0x0003, 0x2011, 0x0024, 0xa586, 0x0024,
+	0x3ae1, 0x015e, 0x2011, 0x0184, 0xa582, 0x0185, 0x0ab0, 0x0890,
+	0x2021, 0x3b15, 0x20a9, 0x0003, 0x2011, 0x0024, 0xa586, 0x0024,
 	0x0960, 0x8420, 0x2011, 0x0028, 0xa586, 0x0028, 0x0930, 0x8420,
-	0x2019, 0x0019, 0x2011, 0x0033, 0x0804, 0x38f1, 0x1021, 0x2202,
+	0x2019, 0x0019, 0x2011, 0x0033, 0x0804, 0x3ab9, 0x1021, 0x2202,
 	0x3403, 0x4604, 0x5805, 0x6a06, 0x7c07, 0x4610, 0x4612, 0x5812,
 	0x5a12, 0x6a14, 0x6c14, 0x6e14, 0x7e17, 0x9021, 0xb002, 0xe204,
 	0xe210, 0xe210, 0x1209, 0x3002, 0x3202, 0x4203, 0x4403, 0x5404,
@@ -1391,314 +1485,319 @@
 	0x10e1, 0x330a, 0x5805, 0x5a05, 0x6a06, 0x6c06, 0x7c07, 0x7e07,
 	0x0e00, 0x789b, 0x0080, 0xa046, 0x0005, 0xa784, 0x0f00, 0x800b,
 	0xa784, 0x001f, 0x8003, 0x8003, 0x8003, 0x8003, 0xa105, 0xd7fc,
-	0x0118, 0xa0e0, 0x68c0, 0x0010, 0xa0e0, 0x48c0, 0x0005, 0x00e6,
-	0x00f6, 0xd084, 0x0138, 0x2079, 0x0100, 0x2009, 0x4380, 0x2071,
-	0x4380, 0x0030, 0x2009, 0x4340, 0x2079, 0x0200, 0x2071, 0x4340,
-	0x2091, 0x8000, 0x2104, 0xa084, 0x000f, 0x0002, 0x39c5, 0x39a0,
-	0x39a0, 0x39a0, 0x39a0, 0x39a0, 0x399e, 0x399e, 0x080c, 0x243b,
-	0x784b, 0x0004, 0x7848, 0xa084, 0x0004, 0x1de0, 0x784b, 0x0008,
-	0x7848, 0xa084, 0x0008, 0x1de0, 0x68b4, 0xc0f5, 0x68b6, 0x7858,
-	0xc0f5, 0x785a, 0x7830, 0xd0bc, 0x1180, 0xb284, 0x0800, 0x0118,
-	0x0104, 0x39c5, 0x0010, 0x0304, 0x39c5, 0x681c, 0xd0ac, 0x1118,
-	0x080c, 0x3a4b, 0x0010, 0x781b, 0x00fb, 0x2091, 0x8001, 0x00fe,
-	0x00ee, 0x0005, 0x00c6, 0x2001, 0x4301, 0x2004, 0xd0ac, 0x1904,
-	0x3a3d, 0x6814, 0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003,
-	0xb28c, 0x0600, 0x0118, 0xa0e0, 0x47c0, 0x0010, 0xa0e0, 0x4840,
-	0x6004, 0xa084, 0x000a, 0x1904, 0x3a3d, 0x6108, 0xa194, 0xff00,
-	0x0904, 0x3a3d, 0xa18c, 0x00ff, 0x601c, 0xa084, 0xff00, 0x0180,
-	0x2001, 0x0009, 0xa102, 0x16b8, 0x2001, 0x000a, 0xa102, 0x16b0,
-	0x2001, 0x000c, 0xa102, 0x16a8, 0x601c, 0xa084, 0x00ff, 0x601e,
-	0x2001, 0x000a, 0xa106, 0x01a8, 0x2001, 0x000c, 0xa106, 0x01a0,
-	0x2001, 0x0012, 0xa106, 0x0198, 0x2001, 0x0014, 0xa106, 0x0190,
-	0x2001, 0x0019, 0xa106, 0x0188, 0x2001, 0x0032, 0xa106, 0x0180,
-	0x00d8, 0x2009, 0x000c, 0x00d0, 0x2009, 0x0012, 0x00b8, 0x2009,
-	0x0014, 0x00a0, 0x2009, 0x0019, 0x0088, 0x2009, 0x0020, 0x0070,
-	0x2009, 0x003f, 0x0058, 0x2009, 0x000a, 0x0040, 0x2009, 0x000c,
-	0x0028, 0x2009, 0x0019, 0x0010, 0x2011, 0x0000, 0x2100, 0xa205,
-	0x600a, 0x6004, 0xa085, 0x0002, 0x6006, 0x00ce, 0x0005, 0x781b,
-	0x0083, 0x0005, 0x781b, 0x0082, 0x0005, 0x781b, 0x0071, 0x0005,
-	0x781b, 0x006e, 0x0005, 0x2009, 0x4319, 0x210c, 0xa186, 0x0000,
-	0x0150, 0xa186, 0x0001, 0x0150, 0x701f, 0x000b, 0x7067, 0x0001,
-	0x781b, 0x0054, 0x0005, 0x781b, 0x00f3, 0x0005, 0x701f, 0x000a,
-	0x0005, 0x2009, 0x4319, 0x210c, 0xa186, 0x0000, 0x0168, 0xa186,
-	0x0001, 0x0138, 0x701f, 0x000b, 0x7067, 0x0001, 0x781b, 0x0054,
-	0x0005, 0x701f, 0x000a, 0x0005, 0x781b, 0x00f2, 0x0005, 0x781b,
-	0x00fb, 0x0005, 0x781b, 0x00fa, 0x0005, 0x781b, 0x00cc, 0x0005,
-	0x781b, 0x00cb, 0x0005, 0x6818, 0xd0fc, 0x0110, 0x681b, 0x001d,
-	0x7067, 0x0001, 0x781b, 0x0054, 0x0005, 0x7830, 0xa084, 0x00c0,
-	0x1170, 0x7808, 0xc08c, 0x780a, 0xe000, 0xe000, 0xe000, 0xe000,
-	0x78ec, 0xa084, 0x0021, 0x0118, 0x7808, 0xc08d, 0x780a, 0x0005,
-	0x7808, 0xc08d, 0x780a, 0x0005, 0x7830, 0xa084, 0x0040, 0x1de0,
-	0xb284, 0x0800, 0x0118, 0x1104, 0x3ab2, 0x0010, 0x1304, 0x3ab2,
-	0x78ac, 0x0005, 0x7808, 0xa084, 0xfffd, 0x780a, 0xe000, 0xe000,
-	0xe000, 0xe000, 0x78ec, 0xa084, 0x0021, 0x0140, 0xb284, 0x0800,
-	0x0118, 0x1104, 0x3ac1, 0x0010, 0x1304, 0x3ac4, 0x78ac, 0x0006,
-	0x7808, 0xa085, 0x0002, 0x780a, 0x000e, 0x0005, 0xa784, 0x0001,
-	0x1904, 0x30a0, 0xa784, 0x0070, 0x0140, 0x00c6, 0x2d60, 0x2f68,
-	0x080c, 0x23e1, 0x2d78, 0x2c68, 0x00ce, 0xa784, 0x0008, 0x0148,
-	0x784b, 0x0008, 0x78ec, 0xa084, 0x0003, 0x0904, 0x248f, 0x0804,
-	0x3a3f, 0xa784, 0x0004, 0x01c8, 0x78b8, 0xa084, 0x8000, 0x01a8,
-	0x784b, 0x0008, 0x78ec, 0xa084, 0x0003, 0x0904, 0x248f, 0x78e4,
-	0xa084, 0x0007, 0xa086, 0x0001, 0x1140, 0x78c0, 0xa685, 0x4800,
-	0x2030, 0x7e5a, 0x781b, 0x00fb, 0x0005, 0xa784, 0x0080, 0x0140,
-	0x7884, 0xd0fc, 0x0128, 0x080c, 0x382d, 0x681b, 0x0022, 0x0005,
-	0x681b, 0x0003, 0x7858, 0xa084, 0x3f00, 0x681e, 0x682f, 0x0000,
-	0x6833, 0x0000, 0x784b, 0x0008, 0x78ec, 0xa084, 0x0003, 0x0904,
-	0x2a7a, 0xb284, 0x0800, 0x0110, 0x0104, 0x248c, 0x0304, 0x248c,
-	0x6b14, 0x8307, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xd3fc,
-	0x0118, 0xa080, 0x4840, 0x0010, 0xa080, 0x47c0, 0x2060, 0x2048,
-	0x705a, 0x2a60, 0x0005, 0x00c6, 0x2960, 0x6000, 0xd0ac, 0x0904,
-	0x3b81, 0xd1ac, 0x05e0, 0x6108, 0x8117, 0xa18c, 0x00ff, 0x631c,
-	0x832f, 0x68a0, 0xd0cc, 0x11c8, 0xa584, 0x00ff, 0x0138, 0x78ec,
-	0xd0e4, 0x0110, 0x8213, 0x00b8, 0x2029, 0x0000, 0xa182, 0x000c,
-	0x1290, 0x78ec, 0xd0e4, 0x1118, 0x2009, 0x000c, 0x0060, 0xa182,
-	0x000b, 0x1248, 0x2009, 0x000a, 0x0030, 0x2009, 0x0032, 0x2011,
-	0x0000, 0x2029, 0x0000, 0x78ab, 0x0001, 0x78ab, 0x0006, 0x78ab,
-	0x0004, 0x79aa, 0x78ab, 0x0000, 0x7aaa, 0x7baa, 0x7daa, 0xa8c0,
-	0x0008, 0x6820, 0xa085, 0x1000, 0x6822, 0x080c, 0x3850, 0xa085,
-	0x0001, 0x00ce, 0x0005, 0xa282, 0x0006, 0x1904, 0x381f, 0x7da8,
-	0x7eac, 0x8637, 0xa5ac, 0x00ff, 0xa6b4, 0x00ff, 0x7fac, 0x8747,
-	0xa7bc, 0x00ff, 0xa8c4, 0x00ff, 0x6920, 0xc1bd, 0x6922, 0xd1e4,
-	0x05c8, 0xa18c, 0xecff, 0x6922, 0xa782, 0x0002, 0x1a04, 0x37fc,
-	0xa6b4, 0x00ff, 0x0560, 0xa682, 0x0039, 0x1a04, 0x37fc, 0xa582,
-	0x0009, 0x0a04, 0x37fc, 0xa882, 0x0003, 0x1a04, 0x37fc, 0xa886,
-	0x0002, 0x0128, 0xa886, 0x0000, 0x0138, 0x0804, 0x37fc, 0xa786,
-	0x0000, 0x0904, 0x37fc, 0x8634, 0x852b, 0x852b, 0x080c, 0x38c6,
-	0x0904, 0x37fc, 0x080c, 0x36f6, 0x080c, 0x379a, 0x7e58, 0xd6d4,
-	0x1118, 0x781b, 0x0071, 0x0005, 0x781b, 0x0083, 0x0005, 0x080c,
-	0x36f3, 0x0c90, 0xa886, 0x0002, 0x1108, 0x8634, 0x7158, 0xa188,
-	0x0000, 0x210c, 0xd1ac, 0x0904, 0x37fc, 0xd1ec, 0x1120, 0x2039,
-	0x0000, 0x2041, 0x0000, 0xd1e4, 0x1120, 0x2031, 0x0000, 0x2041,
-	0x0000, 0xa782, 0x0002, 0x12c8, 0x621c, 0xa284, 0x00ff, 0xa706,
-	0x0110, 0x2039, 0x0000, 0xa605, 0x0190, 0x6108, 0x811f, 0xa39c,
-	0x00ff, 0x0168, 0xa302, 0x1208, 0x2330, 0x8807, 0xa705, 0xa086,
-	0x0201, 0x0160, 0xa886, 0x0000, 0x0168, 0x2039, 0x0000, 0x2041,
-	0x0000, 0x2031, 0x0000, 0xa006, 0x2010, 0x0070, 0xa284, 0xff00,
-	0x1108, 0x2040, 0xa184, 0x00ff, 0xa502, 0x0108, 0x2128, 0x852b,
-	0x852b, 0x080c, 0x38c6, 0x0d58, 0x080c, 0x36f6, 0x080c, 0x379a,
-	0x789b, 0x0080, 0x78ab, 0x0001, 0x78ab, 0x0006, 0x78ab, 0x0004,
-	0x78ab, 0x0000, 0x7daa, 0x7eaa, 0x7faa, 0x2800, 0x78aa, 0x789b,
-	0x0060, 0x78ab, 0x0005, 0x080c, 0x3850, 0x7858, 0xc095, 0x785a,
-	0x781b, 0x0082, 0x0005, 0x0020, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0062, 0x0009, 0x0014,
-	0x0014, 0x9855, 0x984d, 0x0014, 0x9911, 0x98ff, 0x0014, 0x0014,
-	0x0090, 0x00e7, 0x0100, 0x0402, 0x2008, 0xf880, 0x0018, 0x0017,
-	0x840f, 0xd8c1, 0x0014, 0x0016, 0xa20a, 0x0014, 0x300b, 0xa20c,
-	0x0014, 0x2500, 0x0013, 0x2500, 0x0010, 0x0010, 0x0010, 0x0010,
+	0x0118, 0xa0e0, 0x6ac0, 0x0010, 0xa0e0, 0x4ac0, 0x0005, 0x00e6,
+	0x00f6, 0xd084, 0x0138, 0x2079, 0x0100, 0x2009, 0x4580, 0x2071,
+	0x4580, 0x0030, 0x2009, 0x4540, 0x2079, 0x0200, 0x2071, 0x4540,
+	0x2091, 0x8000, 0x2104, 0xa084, 0x000f, 0x0002, 0x3b68, 0x3b68,
+	0x3b68, 0x3b68, 0x3b68, 0x3b68, 0x3b66, 0x3b66, 0x080c, 0x252b,
+	0x69b4, 0xc1f5, 0xa18c, 0xff9f, 0x69b6, 0xa005, 0x0580, 0x7858,
+	0xa084, 0xff9f, 0xa085, 0x6000, 0x785a, 0x7828, 0xa086, 0x1814,
+	0x1530, 0x784b, 0x0004, 0x7848, 0xa084, 0x0004, 0x1de0, 0x784b,
+	0x0008, 0x7848, 0xa084, 0x0008, 0x1de0, 0x7830, 0xd0bc, 0x11b8,
+	0xb284, 0x0800, 0x0118, 0x0104, 0x3b9f, 0x0010, 0x0304, 0x3b9f,
+	0x79e4, 0xa184, 0x0030, 0x0158, 0x78ec, 0xa084, 0x0003, 0x0138,
+	0x681c, 0xd0ac, 0x1110, 0x00d9, 0x0010, 0x781b, 0x00fb, 0x00fe,
+	0x00ee, 0x0005, 0x2001, 0x4501, 0x2004, 0xd0ac, 0x1118, 0x6814,
+	0x080c, 0x2454, 0x0005, 0x781b, 0x0083, 0x0005, 0x781b, 0x0082,
+	0x0005, 0x781b, 0x0071, 0x0005, 0x781b, 0x006e, 0x0005, 0x2009,
+	0x4519, 0x210c, 0xa186, 0x0000, 0x0150, 0xa186, 0x0001, 0x0150,
+	0x701f, 0x000b, 0x7063, 0x0001, 0x781b, 0x0054, 0x0005, 0x781b,
+	0x00f3, 0x0005, 0x701f, 0x000a, 0x0005, 0x2009, 0x4519, 0x210c,
+	0xa186, 0x0000, 0x0168, 0xa186, 0x0001, 0x0138, 0x701f, 0x000b,
+	0x7063, 0x0001, 0x781b, 0x0054, 0x0005, 0x701f, 0x000a, 0x0005,
+	0x781b, 0x00f2, 0x0005, 0x781b, 0x00fb, 0x0005, 0x781b, 0x00fa,
+	0x0005, 0x781b, 0x00cc, 0x0005, 0x781b, 0x00cb, 0x0005, 0x6818,
+	0xd0fc, 0x0110, 0x681b, 0x001d, 0x7063, 0x0001, 0x781b, 0x0054,
+	0x0005, 0x7830, 0xa084, 0x00c0, 0x1170, 0x7808, 0xc08c, 0x780a,
+	0xe000, 0xe000, 0xe000, 0xe000, 0x78ec, 0xa084, 0x0021, 0x0118,
+	0x7808, 0xc08d, 0x780a, 0x0005, 0x7808, 0xc08d, 0x780a, 0x0005,
+	0x7830, 0xa084, 0x0040, 0x1de0, 0xb284, 0x0800, 0x0118, 0x1104,
+	0x3c1e, 0x0010, 0x1304, 0x3c1e, 0x78ac, 0x0005, 0x7808, 0xa084,
+	0xfffd, 0x780a, 0xe000, 0xe000, 0xe000, 0xe000, 0x78ec, 0xa084,
+	0x0021, 0x0140, 0xb284, 0x0800, 0x0118, 0x1104, 0x3c2d, 0x0010,
+	0x1304, 0x3c30, 0x78ac, 0x0006, 0x7808, 0xa085, 0x0002, 0x780a,
+	0x000e, 0x0005, 0xa784, 0x0001, 0x1904, 0x31c5, 0xa784, 0x0070,
+	0x0140, 0x00c6, 0x2d60, 0x2f68, 0x080c, 0x2446, 0x2d78, 0x2c68,
+	0x00ce, 0xa784, 0x0008, 0x0148, 0x784b, 0x0008, 0x78ec, 0xa084,
+	0x0003, 0x0904, 0x31c5, 0x0804, 0x3bab, 0xa784, 0x0004, 0x01c8,
+	0x78b8, 0xa084, 0x8000, 0x01a8, 0x784b, 0x0008, 0x78ec, 0xa084,
+	0x0003, 0x0904, 0x31c5, 0x78e4, 0xa084, 0x0007, 0xa086, 0x0001,
+	0x1140, 0x78c0, 0xa685, 0x4800, 0x2030, 0x7e5a, 0x781b, 0x00fb,
+	0x0005, 0xa784, 0x0080, 0x0140, 0x7884, 0xd0fc, 0x0128, 0x080c,
+	0x39f5, 0x681b, 0x0022, 0x0005, 0x681b, 0x0003, 0x7858, 0xa084,
+	0x5f00, 0x681e, 0x682f, 0x0000, 0x6833, 0x0000, 0x784b, 0x0008,
+	0x78ec, 0xa084, 0x0003, 0x0904, 0x2b6b, 0xb284, 0x0800, 0x0110,
+	0x0104, 0x257c, 0x0304, 0x257c, 0x6b14, 0x8307, 0xa084, 0x000f,
+	0x8003, 0x8003, 0x8003, 0xd3fc, 0x0118, 0xa080, 0x4a40, 0x0010,
+	0xa080, 0x49c0, 0x2060, 0x2048, 0x7056, 0x2a60, 0x0005, 0x00c6,
+	0x2960, 0x6000, 0xd0ac, 0x0904, 0x3ced, 0xd1ac, 0x05e0, 0x6108,
+	0x8117, 0xa18c, 0x00ff, 0x631c, 0x832f, 0x68a0, 0xd0cc, 0x11c8,
+	0xa584, 0x00ff, 0x0138, 0x78ec, 0xd0e4, 0x0110, 0x8213, 0x00b8,
+	0x2029, 0x0000, 0xa182, 0x000c, 0x1290, 0x78ec, 0xd0e4, 0x1118,
+	0x2009, 0x000c, 0x0060, 0xa182, 0x000b, 0x1248, 0x2009, 0x000a,
+	0x0030, 0x2009, 0x0032, 0x2011, 0x0000, 0x2029, 0x0000, 0x78ab,
+	0x0001, 0x78ab, 0x0006, 0x78ab, 0x0004, 0x79aa, 0x78ab, 0x0000,
+	0x7aaa, 0x7baa, 0x7daa, 0xa8c0, 0x0008, 0x6820, 0xa085, 0x1000,
+	0x6822, 0x080c, 0x3a18, 0xa085, 0x0001, 0x00ce, 0x0005, 0xa282,
+	0x0006, 0x1904, 0x39e7, 0x7da8, 0x7eac, 0x8637, 0xa5ac, 0x00ff,
+	0xa6b4, 0x00ff, 0x7fac, 0x8747, 0xa7bc, 0x00ff, 0xa8c4, 0x00ff,
+	0x6920, 0xc1bd, 0x6922, 0xd1e4, 0x0904, 0x3d59, 0xa18c, 0xecff,
+	0x6922, 0xa782, 0x0002, 0x1a04, 0x39c3, 0xa6b4, 0x00ff, 0x0904,
+	0x3d56, 0xa682, 0x0039, 0x1a04, 0x39c3, 0xa582, 0x0009, 0x0a04,
+	0x39c3, 0xa882, 0x0003, 0x1a04, 0x39c3, 0xa886, 0x0002, 0x01d0,
+	0xa886, 0x0000, 0x1904, 0x39c3, 0x2001, 0x000c, 0x79ec, 0xd1e4,
+	0x0110, 0x2001, 0x000a, 0xa502, 0x1290, 0x080c, 0x39c3, 0x00c6,
+	0x2960, 0x6004, 0xa085, 0x001a, 0x6006, 0x6000, 0xc0ac, 0x6002,
+	0x00ce, 0x0005, 0xa786, 0x0000, 0x0904, 0x39c3, 0x8634, 0xa686,
+	0x0010, 0x1108, 0x8630, 0x852b, 0x852b, 0x080c, 0x3a8e, 0x0904,
+	0x39c3, 0x080c, 0x38bd, 0x080c, 0x3961, 0x7e58, 0xd6d4, 0x1118,
+	0x781b, 0x0071, 0x0005, 0x781b, 0x0083, 0x0005, 0x080c, 0x38ba,
+	0x0c90, 0xa886, 0x0002, 0x1108, 0x8634, 0x7154, 0xa188, 0x0000,
+	0x210c, 0xd1ac, 0x0904, 0x39c3, 0xd1ec, 0x1120, 0x2039, 0x0000,
+	0x2041, 0x0000, 0xd1e4, 0x1120, 0x2031, 0x0000, 0x2041, 0x0000,
+	0xa782, 0x0002, 0x12c8, 0x621c, 0xa284, 0x00ff, 0xa706, 0x0110,
+	0x2039, 0x0000, 0xa605, 0x0190, 0x6108, 0x811f, 0xa39c, 0x00ff,
+	0x0168, 0xa302, 0x1208, 0x2330, 0x8807, 0xa705, 0xa086, 0x0201,
+	0x0160, 0xa886, 0x0000, 0x0168, 0x2039, 0x0000, 0x2041, 0x0000,
+	0x2031, 0x0000, 0xa006, 0x2010, 0x0070, 0xa284, 0xff00, 0x1108,
+	0x2040, 0xa184, 0x00ff, 0xa502, 0x0108, 0x2128, 0x852b, 0x852b,
+	0x080c, 0x3a8e, 0x0d58, 0x080c, 0x38bd, 0x080c, 0x3961, 0x789b,
+	0x0080, 0x78ab, 0x0001, 0x78ab, 0x0006, 0x78ab, 0x0004, 0x78ab,
+	0x0000, 0x7daa, 0x7eaa, 0x7faa, 0x2800, 0x78aa, 0x789b, 0x0060,
+	0x78ab, 0x0005, 0x080c, 0x3a18, 0x7858, 0xc095, 0x785a, 0x781b,
+	0x0082, 0x0005, 0x0020, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0062, 0x0009, 0x0014, 0x0014,
+	0x9855, 0x984d, 0x0014, 0x9911, 0x98ff, 0x0014, 0x0014, 0x0090,
+	0x00e7, 0x0100, 0x0402, 0x2008, 0xf880, 0x0018, 0x0017, 0x840f,
+	0xd8c1, 0x0014, 0x0016, 0xa20a, 0x0014, 0x300b, 0xa20c, 0x0014,
+	0x2500, 0x0013, 0x2500, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010,
 	0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010,
-	0x0010, 0x0010, 0xa200, 0x3806, 0x8839, 0x20c4, 0x0864, 0xa84f,
-	0x3008, 0x28c1, 0x9d18, 0xa201, 0x300c, 0x2847, 0x8161, 0x846a,
-	0x8000, 0x84a4, 0x1856, 0x883a, 0xa808, 0x28e2, 0x9cce, 0xa8f3,
-	0x0864, 0xa83d, 0x300c, 0xa801, 0x3008, 0x28e1, 0x9cce, 0x2021,
-	0xa818, 0xa205, 0x870c, 0xd8de, 0x64a0, 0x6de0, 0x6fc0, 0x67a4,
-	0x6c80, 0x0212, 0xa205, 0x883d, 0x882b, 0x1814, 0x883b, 0x7027,
-	0x85f2, 0xa737, 0xa532, 0xf003, 0x8576, 0x8677, 0xa814, 0x883e,
-	0xa812, 0x280a, 0xa204, 0x64c0, 0x6de0, 0x67a0, 0x6fc0, 0x1814,
-	0x883b, 0x7027, 0x8576, 0x8677, 0xa806, 0x796d, 0xa8da, 0x796b,
-	0xa8f1, 0x7861, 0x883e, 0x206b, 0x28c1, 0x9d18, 0x2044, 0x2103,
-	0x20b4, 0x2095, 0xa8ca, 0xa207, 0x2901, 0xa80a, 0x0014, 0xa203,
+	0x0010, 0xa200, 0x3806, 0x8839, 0x20c4, 0x0864, 0xa850, 0x3008,
+	0x28c1, 0x9d18, 0xa201, 0x300c, 0x2847, 0x8161, 0x846a, 0x8000,
+	0x84a4, 0x1856, 0x883a, 0xa808, 0x28e2, 0x9cce, 0xa8f3, 0x0864,
+	0xa83e, 0x300c, 0xa801, 0x3008, 0x28e1, 0x9cce, 0x28a1, 0x7162,
+	0x2021, 0xa818, 0xa205, 0x870c, 0xd8de, 0x64a0, 0x6de0, 0x6fc0,
+	0x67a4, 0x6c80, 0x0212, 0xa205, 0x883d, 0x882b, 0x1814, 0x883b,
+	0x7027, 0x85f2, 0xa737, 0xa532, 0xf003, 0x8576, 0x8677, 0xa812,
+	0x883e, 0xa810, 0x2881, 0x7161, 0x280a, 0xa204, 0x64c0, 0x6de0,
+	0x67a0, 0x6fc0, 0x1814, 0x883b, 0x7023, 0x8576, 0x8677, 0xa802,
+	0x7861, 0x883e, 0x206c, 0x28c1, 0x9d18, 0x2044, 0x2103, 0x20a2,
+	0x2081, 0xa8ca, 0x2902, 0xa20e, 0xa80b, 0xa207, 0x0014, 0xa203,
 	0x8000, 0x85a4, 0x1872, 0x879a, 0x883c, 0x1fe2, 0xf601, 0xa208,
-	0x856e, 0x866f, 0x7121, 0x0014, 0x0704, 0x3008, 0x9cce, 0x0014,
-	0xa202, 0x8000, 0x85a4, 0x3009, 0x84a8, 0x19e2, 0xf844, 0x856e,
-	0x883f, 0x08e6, 0xa8f5, 0xf861, 0xa8ea, 0xf801, 0x0014, 0xf881,
-	0x0016, 0x85b2, 0x80f0, 0x9532, 0xfaa2, 0x1de2, 0x0014, 0x8532,
-	0xf221, 0x0014, 0x1de2, 0x84a8, 0xd6e0, 0x1fe6, 0x0014, 0x3008,
-	0x8000, 0x2849, 0x1011, 0xa8fc, 0x3008, 0x8000, 0xa000, 0x2081,
-	0x2802, 0x1011, 0xa8fc, 0xa889, 0x3008, 0x20a1, 0x283c, 0x1011,
-	0xa8fc, 0xa209, 0x0017, 0x300c, 0x8000, 0x85a4, 0x1de2, 0xdac1,
-	0x0014, 0x0210, 0xa801, 0x0014, 0x26e0, 0x873a, 0xfaa3, 0x19f2,
-	0x26e0, 0x18f2, 0x0014, 0xa20b, 0x0014, 0xa20d, 0x3806, 0x0210,
-	0x9d22, 0x0704, 0xa206, 0x6865, 0x817e, 0x842a, 0x1dc1, 0x8823,
-	0x0016, 0x6042, 0x8008, 0xa8fa, 0x8160, 0x842a, 0x8180, 0xf021,
-	0x3008, 0x84a8, 0x11d7, 0x7042, 0x20dd, 0x0011, 0x20d5, 0x8822,
-	0x0016, 0x0000, 0x0126, 0x70d4, 0xa084, 0x4c00, 0x8004, 0x2090,
-	0x7204, 0x7008, 0xc09c, 0xa205, 0x1178, 0x720c, 0x82ff, 0x0128,
-	0x8aff, 0x1150, 0x7200, 0xd284, 0x1138, 0x7007, 0x0004, 0x7003,
-	0x0008, 0x012e, 0x2000, 0x0005, 0x7000, 0xa084, 0x0003, 0x7002,
-	0xc69c, 0xd084, 0x05b8, 0x2001, 0x4301, 0x2004, 0xd0b4, 0x0904,
-	0x3dcf, 0x7108, 0xe000, 0x7008, 0xa106, 0x1dd8, 0xa184, 0x0003,
-	0x0904, 0x3dcf, 0xa184, 0x01e0, 0x1904, 0x3dcf, 0xd1f4, 0x1d88,
-	0xa184, 0x3000, 0xa086, 0x1000, 0x0d60, 0x2011, 0x0180, 0x710c,
-	0x8211, 0x0130, 0x7008, 0xd0f4, 0x1d20, 0x700c, 0xa106, 0x0dc0,
-	0x7007, 0x0012, 0x7108, 0xe000, 0x7008, 0xa106, 0x1dd8, 0xa184,
-	0x0003, 0x0568, 0xd194, 0x0db0, 0xd1f4, 0x0548, 0x7007, 0x0002,
-	0x0880, 0x0428, 0x7108, 0xd1fc, 0x0130, 0x080c, 0x3e9e, 0x8aff,
-	0x0904, 0x3d58, 0x0cb8, 0x700c, 0xa08c, 0x07ff, 0x01e8, 0x7004,
-	0xd084, 0x0178, 0x7014, 0xa005, 0x1148, 0x7010, 0x7310, 0xa306,
-	0x1de0, 0x2300, 0xa005, 0x0128, 0xa102, 0x1e20, 0x7007, 0x0010,
-	0x0030, 0x8aff, 0x0148, 0x080c, 0x4046, 0x1de8, 0x09d8, 0x080c,
-	0x3e58, 0x012e, 0x2000, 0x0005, 0x7204, 0x7108, 0xc19c, 0x8103,
-	0x1218, 0x080c, 0x3e9e, 0x0cc0, 0xa205, 0x1d88, 0x7007, 0x0004,
-	0x7003, 0x0008, 0x012e, 0x2000, 0x0005, 0x6428, 0x84ff, 0x0508,
-	0x2c70, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x3e19, 0x273c, 0x87fb,
-	0x1148, 0x0210, 0x080c, 0x243b, 0x609c, 0xa075, 0x0190, 0x0c88,
-	0x2039, 0x3e0e, 0x2704, 0xae68, 0x6808, 0xa630, 0x680c, 0xa529,
-	0x8421, 0x0138, 0x8738, 0x2704, 0xa005, 0x1da8, 0x709c, 0xa075,
-	0x1d00, 0x0005, 0x0000, 0x0005, 0x0009, 0x000d, 0x0011, 0x0015,
-	0x0019, 0x001d, 0x0000, 0x0003, 0x0009, 0x000f, 0x0015, 0x001b,
-	0x0000, 0x0000, 0x3e0e, 0x3e0b, 0x0000, 0x0000, 0x8000, 0x0000,
-	0x3e0e, 0x0000, 0x3e16, 0x3e13, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x3e16, 0x0000, 0x3e11, 0x3e11, 0x0000, 0x0000, 0x8000, 0x0000,
-	0x3e11, 0x0000, 0x3e17, 0x3e17, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x3e17, 0x2079, 0x4300, 0x2071, 0x0010, 0x7007, 0x000a, 0x7007,
-	0x0002, 0x7003, 0x0001, 0x2009, 0x0002, 0x2071, 0x0050, 0x7007,
-	0x000a, 0x7007, 0x0002, 0x7003, 0x0000, 0x2001, 0x01ff, 0x2004,
-	0xd0fc, 0x1128, 0x8109, 0x0118, 0x2071, 0x0020, 0x0c80, 0x0005,
-	0x7004, 0x8004, 0x1690, 0x7007, 0x0012, 0x2019, 0x0000, 0x7108,
-	0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0110, 0x080c, 0x243b,
-	0xa19c, 0x300c, 0xa386, 0x2004, 0x0130, 0xa386, 0x0008, 0x0160,
-	0xa386, 0x200c, 0x1d60, 0x7200, 0x8204, 0x0230, 0x730c, 0xa384,
-	0x07ff, 0x0110, 0x080c, 0x243b, 0x7007, 0x0012, 0x7000, 0xd084,
-	0x1160, 0x7008, 0xa084, 0x01e0, 0x1140, 0x7310, 0x7014, 0xa305,
-	0x0120, 0x710c, 0xa184, 0x07ff, 0x1958, 0x7007, 0x0012, 0x7007,
-	0x0008, 0x7004, 0xd09c, 0x1de8, 0x7007, 0x0012, 0x7108, 0x8103,
-	0x0ed8, 0x7003, 0x0008, 0x0005, 0x7108, 0x0000, 0xa184, 0x01e0,
-	0x1550, 0x7108, 0xa184, 0x01e0, 0x1530, 0xa184, 0x0007, 0x0002,
-	0x3eb2, 0x3ec0, 0x3eb0, 0x3ec0, 0x3eb0, 0x3f06, 0x3eb0, 0x3f05,
-	0x080c, 0x243b, 0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff,
-	0x1118, 0x2049, 0x0000, 0x0005, 0x080c, 0x4046, 0x1de8, 0x0005,
-	0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, 0x0118, 0x080c,
-	0x4046, 0x1de8, 0x0005, 0x7007, 0x0012, 0x7108, 0x1d04, 0x3ece,
-	0x2091, 0x6000, 0x1d04, 0x3ed2, 0x2091, 0x6000, 0x7007, 0x0012,
+	0x856e, 0x7121, 0x0014, 0x0704, 0x3008, 0x9cce, 0x0014, 0xa202,
+	0x8000, 0x85a4, 0x3009, 0x84a8, 0x19e2, 0xf844, 0x856e, 0x883f,
+	0x08e6, 0xa8f5, 0xf861, 0xa8eb, 0xf801, 0x0014, 0xf881, 0x0016,
+	0x85b2, 0x80f0, 0x9532, 0xfaa2, 0x1de2, 0x0014, 0x8532, 0xf221,
+	0x0014, 0x1de2, 0x84a8, 0xd6e0, 0x1fe6, 0x0014, 0x3008, 0x8000,
+	0x2849, 0x1011, 0xa8fc, 0x3008, 0x8000, 0xa000, 0x2081, 0x2802,
+	0x1011, 0xa8fc, 0xa889, 0x3008, 0x20a1, 0x283c, 0x1011, 0xa8fc,
+	0xa209, 0x0017, 0x300c, 0x8000, 0x85a4, 0x1de2, 0xdac1, 0x0014,
+	0x0210, 0xa801, 0x0014, 0x26e0, 0x873a, 0xfaa3, 0x19f2, 0x26e0,
+	0x18f2, 0x0014, 0xa20b, 0x0014, 0xa20d, 0x3806, 0x0210, 0x9d22,
+	0x0704, 0xa206, 0x6865, 0x817e, 0x842a, 0x1dc1, 0x8823, 0x0016,
+	0x6042, 0x8008, 0xa8fa, 0x8160, 0x842a, 0x8180, 0xf021, 0x3008,
+	0x84a8, 0x11d7, 0x7042, 0x20dd, 0x0011, 0x20d5, 0x8822, 0x0016,
+	0x0000, 0x0126, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x7204,
+	0x7008, 0xc09c, 0xa205, 0x1178, 0x720c, 0x82ff, 0x0128, 0x8aff,
+	0x1150, 0x7200, 0xd284, 0x1138, 0x7007, 0x0004, 0x7003, 0x0008,
+	0x012e, 0x2000, 0x0005, 0x7000, 0xa084, 0x0003, 0x7002, 0xc69c,
+	0xd084, 0x0588, 0x7108, 0xe000, 0x7008, 0xa106, 0x1dd8, 0xa184,
+	0x0003, 0x0904, 0x3f50, 0xa184, 0x01e0, 0x1904, 0x3f50, 0xd1f4,
+	0x1d88, 0xa184, 0x3000, 0xa086, 0x1000, 0x0d60, 0x2011, 0x0180,
+	0x710c, 0x8211, 0x0130, 0x7008, 0xd0f4, 0x1d20, 0x700c, 0xa106,
+	0x0dc0, 0x7007, 0x0012, 0x7108, 0xe000, 0x7008, 0xa106, 0x1dd8,
+	0xa184, 0x0003, 0x0568, 0xd194, 0x0db0, 0xd1f4, 0x0548, 0x7007,
+	0x0002, 0x0880, 0x0428, 0x7108, 0xd1fc, 0x0130, 0x080c, 0x4053,
+	0x8aff, 0x0904, 0x3edf, 0x0cb8, 0x700c, 0xa08c, 0x07ff, 0x01e8,
+	0x7004, 0xd084, 0x0178, 0x7014, 0xa005, 0x1148, 0x7010, 0x7310,
+	0xa306, 0x1de0, 0x2300, 0xa005, 0x0128, 0xa102, 0x1e20, 0x7007,
+	0x0010, 0x0030, 0x8aff, 0x0148, 0x080c, 0x4212, 0x1de8, 0x09d8,
+	0x080c, 0x3fd9, 0x012e, 0x2000, 0x0005, 0x7204, 0x7108, 0xc19c,
+	0x8103, 0x1218, 0x7007, 0x0002, 0x0cc0, 0xa205, 0x1d88, 0x7007,
+	0x0004, 0x7003, 0x0008, 0x012e, 0x2000, 0x0005, 0x6428, 0x84ff,
+	0x0508, 0x2c70, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x3f9a, 0x273c,
+	0x87fb, 0x1148, 0x0210, 0x080c, 0x252b, 0x609c, 0xa075, 0x0190,
+	0x0c88, 0x2039, 0x3f8f, 0x2704, 0xae68, 0x6808, 0xa630, 0x680c,
+	0xa529, 0x8421, 0x0138, 0x8738, 0x2704, 0xa005, 0x1da8, 0x709c,
+	0xa075, 0x1d00, 0x0005, 0x0000, 0x0005, 0x0009, 0x000d, 0x0011,
+	0x0015, 0x0019, 0x001d, 0x0000, 0x0003, 0x0009, 0x000f, 0x0015,
+	0x001b, 0x0000, 0x0000, 0x3f8f, 0x3f8c, 0x0000, 0x0000, 0x8000,
+	0x0000, 0x3f8f, 0x0000, 0x3f97, 0x3f94, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x3f97, 0x0000, 0x3f92, 0x3f92, 0x0000, 0x0000, 0x8000,
+	0x0000, 0x3f92, 0x0000, 0x3f98, 0x3f98, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x3f98, 0x2079, 0x4500, 0x2071, 0x0010, 0x7007, 0x000a,
+	0x7007, 0x0002, 0x7003, 0x0001, 0x2009, 0x0002, 0x2071, 0x0050,
+	0x7007, 0x000a, 0x7007, 0x0002, 0x7003, 0x0000, 0x2001, 0x01ff,
+	0x2004, 0xd0fc, 0x1128, 0x8109, 0x0118, 0x2071, 0x0020, 0x0c80,
+	0x0005, 0x7004, 0x8004, 0x1a04, 0x402f, 0x7108, 0x7008, 0xa106,
+	0x1de0, 0xa184, 0x01e0, 0x0120, 0x080c, 0x408b, 0x0804, 0x404f,
+	0x7007, 0x0012, 0x2019, 0x0000, 0x7108, 0x7008, 0xa106, 0x1de0,
+	0xa184, 0x01e0, 0x0120, 0x080c, 0x408b, 0x0804, 0x404f, 0xa19c,
+	0x300c, 0xa386, 0x2004, 0x0190, 0xa386, 0x0008, 0x01c0, 0x7004,
+	0xd084, 0x1148, 0x7108, 0x7008, 0xa106, 0x1de0, 0xa184, 0x0003,
+	0x0110, 0x0804, 0x408b, 0xa386, 0x200c, 0x19f0, 0x7200, 0x8204,
+	0x0230, 0x730c, 0xa384, 0x07ff, 0x0110, 0x080c, 0x252b, 0x7108,
+	0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0118, 0x080c, 0x408b,
+	0x0470, 0x7007, 0x0012, 0x7000, 0xd084, 0x1148, 0x7310, 0x7014,
+	0xa305, 0x0128, 0x710c, 0xa184, 0x07ff, 0x1904, 0x3fd9, 0x7108,
+	0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0118, 0x080c, 0x408b,
+	0x00b0, 0x7007, 0x0012, 0x7007, 0x0008, 0x7004, 0xd09c, 0x1de8,
+	0x7108, 0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0118, 0x080c,
+	0x408b, 0x0028, 0x7007, 0x0012, 0x7108, 0x8103, 0x0e88, 0x7003,
+	0x0008, 0x0005, 0x7108, 0xa184, 0x01e0, 0x15a8, 0x7108, 0xa184,
+	0x01e0, 0x1588, 0xa184, 0x0007, 0x0002, 0x4067, 0x4075, 0x4065,
+	0x4075, 0x4065, 0x40c5, 0x4065, 0x40c3, 0x080c, 0x252b, 0x7004,
+	0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, 0x1118, 0x2049, 0x0000,
+	0x0005, 0x080c, 0x4212, 0x1de8, 0x0005, 0x7004, 0xa084, 0x0010,
+	0xc08d, 0x7006, 0x7004, 0xd084, 0x1140, 0x7108, 0x7008, 0xa106,
+	0x1de0, 0xa184, 0x0003, 0x0108, 0x0030, 0x8aff, 0x0118, 0x080c,
+	0x4212, 0x1de8, 0x0005, 0x7007, 0x0012, 0x7108, 0x1d04, 0x408e,
+	0x2091, 0x6000, 0x1d04, 0x4092, 0x2091, 0x6000, 0x7007, 0x0012,
 	0x7007, 0x0008, 0x7004, 0xd09c, 0x1de8, 0x7007, 0x0012, 0x7108,
 	0xd1fc, 0x1dd8, 0x7003, 0x0000, 0x7000, 0xa005, 0x1130, 0x7004,
 	0xa005, 0x1118, 0x700c, 0xa005, 0x0108, 0x0c40, 0x2049, 0x0000,
 	0xb284, 0x0200, 0x0118, 0x2001, 0x0000, 0x0010, 0x2001, 0x0001,
-	0x080c, 0x397f, 0x6818, 0xa084, 0x8000, 0x0110, 0x681b, 0x0002,
-	0x0005, 0x080c, 0x243b, 0x080c, 0x243b, 0x04b9, 0x7210, 0x7114,
-	0x700c, 0xa09c, 0x07ff, 0x2800, 0xa300, 0xa211, 0xa189, 0x0000,
-	0x0461, 0x2704, 0x2c58, 0xac60, 0x6308, 0x2200, 0xa322, 0x630c,
-	0x2100, 0xa31b, 0x2400, 0xa305, 0x0140, 0x1238, 0x8412, 0x8210,
-	0x830a, 0xa189, 0x0000, 0x2b60, 0x0c58, 0x2b60, 0x8a07, 0x0006,
-	0x6004, 0xa084, 0x0008, 0x0118, 0xa7ba, 0x3e13, 0x0010, 0xa7ba,
-	0x3e0b, 0x000e, 0xa73d, 0x2c00, 0x6886, 0x6f8a, 0x6c92, 0x6b8e,
-	0x7007, 0x0012, 0x080c, 0x3e58, 0x0005, 0x8a50, 0x8739, 0x2704,
+	0x080c, 0x3b47, 0x681b, 0x0002, 0x2051, 0x0000, 0x0005, 0x080c,
+	0x252b, 0x080c, 0x252b, 0x080c, 0x4105, 0x7210, 0x7114, 0x700c,
+	0xa09c, 0x07ff, 0x2800, 0xa300, 0xa211, 0xa189, 0x0000, 0x04a9,
+	0x2704, 0x2c58, 0xac60, 0x6308, 0x2200, 0xa322, 0x630c, 0x2100,
+	0xa31b, 0x2400, 0xa305, 0x0140, 0x1238, 0x8412, 0x8210, 0x830a,
+	0xa189, 0x0000, 0x2b60, 0x0c58, 0x2b60, 0x8a07, 0x0006, 0x6004,
+	0xa084, 0x0008, 0x0118, 0xa7ba, 0x3f94, 0x0010, 0xa7ba, 0x3f8c,
+	0x000e, 0xa73d, 0x2c00, 0x6886, 0x6f8a, 0x6c92, 0x6b8e, 0x7108,
+	0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0110, 0x080c, 0x408b,
+	0x7007, 0x0012, 0x080c, 0x3fd9, 0x0005, 0x8a50, 0x8739, 0x2704,
 	0xa004, 0x1168, 0x6000, 0xa064, 0x1108, 0x2d60, 0x6004, 0xa084,
-	0x000f, 0xa080, 0x3e29, 0x203c, 0x87fb, 0x090c, 0x243b, 0x0005,
-	0x0126, 0x00d6, 0x70d4, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de,
+	0x000f, 0xa080, 0x3faa, 0x203c, 0x87fb, 0x090c, 0x252b, 0x0005,
+	0x0126, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de,
 	0x6884, 0x2060, 0x6888, 0x6b8c, 0x6c90, 0x8057, 0xaad4, 0x00ff,
 	0xa084, 0x00ff, 0x0006, 0x6804, 0xa084, 0x0008, 0x000e, 0x0118,
-	0xa0b8, 0x3e13, 0x0010, 0xa0b8, 0x3e0b, 0xb284, 0x0200, 0x0110,
+	0xa0b8, 0x3f94, 0x0010, 0xa0b8, 0x3f8c, 0xb284, 0x0200, 0x0110,
 	0x7e20, 0x0008, 0x7e24, 0xa6b5, 0x000c, 0x681c, 0xd0b4, 0x0108,
 	0xc685, 0x2400, 0xa305, 0x0520, 0x2c58, 0x2704, 0x6104, 0xac60,
 	0x6000, 0xa400, 0x701a, 0x6004, 0xa301, 0x701e, 0xa184, 0x0008,
 	0x0140, 0x6010, 0xa081, 0x0000, 0x7022, 0x6014, 0xa081, 0x0000,
 	0x7026, 0x6208, 0x2400, 0xa202, 0x7012, 0x620c, 0x2300, 0xa203,
-	0x7016, 0x7602, 0x7007, 0x0001, 0x2b60, 0x080c, 0x4067, 0x0010,
-	0x080c, 0x4046, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x00d6,
-	0x70d4, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x7007, 0x0004,
+	0x7016, 0x7602, 0x7007, 0x0001, 0x2b60, 0x080c, 0x423a, 0x0010,
+	0x080c, 0x4212, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x00d6,
+	0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x7007, 0x0004,
 	0x7004, 0xd094, 0x1de8, 0x7003, 0x0008, 0x012e, 0x2000, 0x0005,
-	0x0126, 0x00d6, 0x70d4, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de,
+	0x0126, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de,
 	0x7e20, 0xb284, 0x0200, 0x1108, 0x7e24, 0xa6b5, 0x000c, 0x681c,
 	0xd0ac, 0x1118, 0xc685, 0x7003, 0x0000, 0x6828, 0x2050, 0x2d60,
-	0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x3e19, 0x273c, 0x87fb, 0x1138,
-	0x0210, 0x080c, 0x243b, 0x689c, 0xa065, 0x0120, 0x0c88, 0x080c,
-	0x4046, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x0006, 0x0016,
-	0x00d6, 0x70d4, 0xa084, 0x4c00, 0x8004, 0x2090, 0x7e20, 0xb284,
+	0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x3f9a, 0x273c, 0x87fb, 0x1138,
+	0x0210, 0x080c, 0x252b, 0x689c, 0xa065, 0x0120, 0x0c88, 0x080c,
+	0x4212, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x0006, 0x0016,
+	0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x7e20, 0xb284,
 	0x0200, 0x1108, 0x7e24, 0x00de, 0x003e, 0x004e, 0xa6b5, 0x000c,
 	0x681c, 0xd0b4, 0x0128, 0xc685, 0x7003, 0x0000, 0x7007, 0x0004,
-	0x2049, 0x3fe5, 0x6828, 0xa055, 0x05f0, 0x2d70, 0x2e60, 0x7004,
-	0xa0bc, 0x000f, 0xa7b8, 0x3e19, 0x273c, 0x87fb, 0x1140, 0x0210,
-	0x080c, 0x243b, 0x709c, 0xa075, 0x2060, 0x0568, 0x0c80, 0x2704,
-	0xae68, 0x6808, 0xa422, 0x680c, 0xa31b, 0x0268, 0x8a51, 0x1110,
-	0x080c, 0x243b, 0x8738, 0x2704, 0xa005, 0x1d90, 0x709c, 0xa075,
-	0x2060, 0x01c8, 0x08e0, 0x8422, 0x8420, 0x831a, 0xa399, 0x0000,
-	0x6908, 0x2400, 0xa122, 0x690c, 0x2300, 0xa11b, 0x1210, 0x080c,
-	0x243b, 0xb284, 0x0200, 0x0118, 0x2071, 0x0050, 0x0010, 0x2071,
-	0x0020, 0x0804, 0x3f79, 0x012e, 0x2000, 0x0005, 0x7008, 0xa084,
-	0x0003, 0xa086, 0x0003, 0x1108, 0x0005, 0x2704, 0xac78, 0x7800,
-	0x701a, 0x7804, 0x701e, 0x7808, 0x7012, 0x780c, 0x7016, 0x6004,
-	0xa084, 0x0008, 0x0120, 0x7810, 0x7022, 0x7814, 0x7026, 0x7602,
-	0x7004, 0xa084, 0x0010, 0xc085, 0x7006, 0x2079, 0x4300, 0x8a51,
-	0x01b0, 0x8738, 0x2704, 0xa005, 0x1168, 0x609c, 0xa005, 0x0180,
-	0x2060, 0x6004, 0xa084, 0x000f, 0xa080, 0x3e19, 0x203c, 0x87fb,
-	0x090c, 0x243b, 0x7008, 0xa084, 0x0003, 0xa086, 0x0003, 0x0005,
-	0x2051, 0x0000, 0x0005, 0x0126, 0x0006, 0x00d6, 0x70d4, 0xa084,
-	0x4c00, 0x8004, 0x2090, 0x00de, 0x008e, 0x7108, 0xa184, 0x0003,
-	0x1128, 0x6828, 0xa005, 0x0178, 0x0804, 0x3d6c, 0x7108, 0xd1fc,
-	0x0118, 0x080c, 0x3e9e, 0x0c88, 0x7007, 0x0010, 0x7108, 0xd1fc,
-	0x0de8, 0x080c, 0x3e9e, 0x7008, 0xa086, 0x0008, 0x1d30, 0x7000,
-	0xa005, 0x1d18, 0x7003, 0x0000, 0x2049, 0x0000, 0x012e, 0x2000,
-	0x0005, 0x0126, 0x0146, 0x0136, 0x0156, 0x00c6, 0x00d6, 0x70d4,
-	0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x2049, 0x40b1, 0xad80,
-	0x0011, 0x20a0, 0xb284, 0x0200, 0x0118, 0x2099, 0x0032, 0x0010,
-	0x2099, 0x0031, 0x700c, 0xa084, 0x07ff, 0x682a, 0x7007, 0x0008,
-	0x7007, 0x0002, 0x7003, 0x0001, 0x0118, 0x8000, 0x80ac, 0x53a5,
-	0x700c, 0xa084, 0x07ff, 0x0130, 0x7007, 0x0004, 0x7004, 0xa084,
-	0x0004, 0x1de0, 0x00ce, 0x2049, 0x0000, 0x7003, 0x0000, 0x015e,
-	0x013e, 0x014e, 0x012e, 0x2000, 0x0005, 0x2091, 0x8000, 0x2091,
-	0x6000, 0x78ac, 0xa005, 0x1168, 0x7974, 0x70d0, 0xa106, 0x1148,
-	0x781c, 0xa005, 0x0130, 0x781f, 0x0000, 0x0e04, 0x4101, 0x2091,
-	0x4080, 0x7830, 0x8001, 0x7832, 0x1904, 0x416b, 0x7834, 0x7832,
-	0x2061, 0x68c0, 0x2069, 0x4380, 0xc7fd, 0x68d0, 0xa005, 0x0128,
-	0x8001, 0x68d2, 0x1110, 0x080c, 0x42c4, 0x6800, 0xa084, 0x000f,
-	0x0168, 0xa086, 0x0001, 0x0150, 0x6844, 0xa00d, 0x0138, 0x2104,
-	0xa005, 0x0120, 0x8001, 0x200a, 0x0904, 0x425f, 0x6814, 0xa005,
-	0x01a8, 0x8001, 0x6816, 0x1190, 0x68a7, 0x0001, 0x00f6, 0xd7fc,
-	0x1118, 0x2079, 0x0200, 0x0010, 0x2079, 0x0100, 0x080c, 0x3aa0,
-	0x00fe, 0x6864, 0xa005, 0x0110, 0x080c, 0x2233, 0x6880, 0xa005,
-	0x0140, 0x8001, 0x6882, 0x1128, 0x6867, 0x0000, 0x68d4, 0xc0c5,
-	0x68d6, 0x68d4, 0xd0fc, 0x01b0, 0xc0fc, 0x68d6, 0x20a9, 0x0200,
-	0x6034, 0xa005, 0x0158, 0x8001, 0x6036, 0x68d4, 0xc0fd, 0x68d6,
-	0x1128, 0x6010, 0xa005, 0x0110, 0x080c, 0x2233, 0xace0, 0x0010,
-	0x1f04, 0x4150, 0xd7fc, 0x0138, 0x2061, 0x48c0, 0x2069, 0x4340,
-	0xc7fc, 0x0804, 0x410d, 0x0459, 0x7838, 0x8001, 0x783a, 0x11a0,
-	0x783c, 0x783a, 0x2061, 0x48c0, 0x2069, 0x4340, 0xc7fc, 0x680c,
-	0xa005, 0x0110, 0x080c, 0x41c9, 0xd7fc, 0x1130, 0x2061, 0x68c0,
-	0x2069, 0x4380, 0xc7fd, 0x0c98, 0x7810, 0xd0cc, 0x0168, 0xd0ac,
-	0x1120, 0xd0a4, 0x0148, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0e04,
-	0x4193, 0x080c, 0x1ffe, 0x0005, 0x2091, 0x8001, 0x0005, 0x7840,
-	0x8001, 0x7842, 0x1568, 0x7844, 0x7842, 0x2091, 0x8000, 0x2061,
-	0x48c0, 0x2069, 0x4340, 0xc7fc, 0x6810, 0xa005, 0x1110, 0x2001,
-	0x0101, 0x8001, 0x6812, 0xd7fc, 0x0118, 0xa080, 0x89d0, 0x0010,
-	0xa080, 0x88c0, 0x2040, 0x2004, 0xa065, 0x0150, 0x6024, 0xa005,
-	0x0120, 0x8001, 0x6026, 0x0904, 0x4207, 0x6000, 0x2c40, 0x0ca0,
-	0xd7fc, 0x1130, 0x2061, 0x68c0, 0x2069, 0x4380, 0xc7fd, 0x08e0,
-	0x0005, 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0540,
-	0x6024, 0xa005, 0x0118, 0x8001, 0x6026, 0x0400, 0x6008, 0xc09c,
-	0xd084, 0x1110, 0xd0ac, 0x01a8, 0x600a, 0x6004, 0xa06d, 0x01c0,
-	0x00c6, 0x0016, 0x6010, 0x8001, 0x6012, 0x080c, 0x35ab, 0x2d00,
-	0x2c68, 0x2060, 0x080c, 0x1b85, 0x080c, 0x1d30, 0x001e, 0x00ce,
-	0x0038, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0010, 0xa18d, 0x0100,
-	0xace0, 0x0010, 0x1f04, 0x41cd, 0xa184, 0x0001, 0x0130, 0xa18c,
-	0xfffe, 0x690e, 0x080c, 0x2233, 0x0008, 0x690e, 0x0005, 0x6800,
-	0xa005, 0x0120, 0x684c, 0xac06, 0x0904, 0x425f, 0x6864, 0xa005,
-	0x0120, 0x6027, 0x0001, 0x0804, 0x425c, 0x2c00, 0x687e, 0x6714,
-	0x6f76, 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, 0x60b4,
-	0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060,
-	0x6022, 0x6000, 0x2042, 0x080c, 0x1b1d, 0x6818, 0xa005, 0x0110,
-	0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109,
-	0x790a, 0x8001, 0x1310, 0x080c, 0x243b, 0x6812, 0x1118, 0x7910,
-	0xc1a5, 0x7912, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x080c,
-	0x1d3d, 0xd7fc, 0x1118, 0x2069, 0x4340, 0x0010, 0x2069, 0x4380,
-	0x6910, 0xa184, 0x0100, 0x2001, 0x0006, 0x1118, 0x697a, 0x2001,
-	0x0004, 0x2708, 0x080c, 0x2228, 0x2091, 0x8001, 0x0005, 0x00d6,
-	0x694c, 0x2160, 0xd7fc, 0x1118, 0x2069, 0x0200, 0x0010, 0x2069,
-	0x0100, 0x080c, 0x23e1, 0x601b, 0x0006, 0x6858, 0xa084, 0x3f00,
-	0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f,
-	0x0000, 0x6033, 0x0000, 0x6830, 0xd0b4, 0x01b0, 0x684b, 0x0004,
-	0x20a9, 0x0014, 0x6848, 0xd094, 0x0110, 0x1f04, 0x4282, 0x684b,
-	0x0009, 0x20a9, 0x0014, 0x6848, 0xd084, 0x0110, 0x1f04, 0x428b,
-	0x20a9, 0x00fa, 0x1f04, 0x4292, 0x6808, 0xa084, 0xfffd, 0x680a,
-	0x681b, 0x0054, 0x00de, 0x6867, 0x0007, 0x2091, 0x8001, 0x0005,
-	0x2079, 0x4300, 0x00e1, 0x0089, 0x00a9, 0x2009, 0x0002, 0x2069,
-	0x4380, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, 0x0000, 0x8109,
-	0x0118, 0x2069, 0x4340, 0x0ca8, 0x0005, 0x2019, 0x00a3, 0x7b3a,
-	0x7b3e, 0x0005, 0x2019, 0x0033, 0x7b42, 0x7b46, 0x0005, 0x2019,
-	0x32dd, 0x7b32, 0x7b36, 0x0005, 0x6950, 0xa185, 0x0000, 0x0178,
-	0x00c6, 0x6ac0, 0x2264, 0x602b, 0x0000, 0x602f, 0x0000, 0x6008,
-	0xc0b5, 0x600a, 0x8210, 0x8109, 0x1da8, 0x6952, 0x00ce, 0x0005,
-	0x70ec, 0xd0dc, 0x1118, 0xd0d4, 0x0180, 0x0088, 0xae8e, 0x0100,
-	0x0130, 0x7814, 0xc0f5, 0x7816, 0xd0d4, 0x1170, 0x0050, 0x7814,
-	0xc0fd, 0x7816, 0xd0d4, 0x1140, 0x0020, 0xd0e4, 0x0138, 0x70a0,
-	0x70a2, 0x7804, 0xd08c, 0x0110, 0x681f, 0x000c, 0x0005, 0xaf67
+	0x2049, 0x41ad, 0x6828, 0xa055, 0x00d6, 0x0904, 0x420e, 0x2d70,
+	0x2e60, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x3f9a, 0x273c, 0x87fb,
+	0x1140, 0x0210, 0x080c, 0x252b, 0x709c, 0xa075, 0x2060, 0x0570,
+	0x0c80, 0x2704, 0xae68, 0x6808, 0xa422, 0x680c, 0xa31b, 0x0268,
+	0x8a51, 0x1110, 0x080c, 0x252b, 0x8738, 0x2704, 0xa005, 0x1d90,
+	0x709c, 0xa075, 0x2060, 0x01d0, 0x08e0, 0x8422, 0x8420, 0x831a,
+	0xa399, 0x0000, 0x6908, 0x2400, 0xa122, 0x690c, 0x2300, 0xa11b,
+	0x1210, 0x080c, 0x252b, 0xb284, 0x0200, 0x0118, 0x2071, 0x0050,
+	0x0010, 0x2071, 0x0020, 0x00de, 0x0804, 0x4141, 0x00de, 0x012e,
+	0x2000, 0x0005, 0x7008, 0x0006, 0xa084, 0x01e0, 0x000e, 0x0110,
+	0xa006, 0x0005, 0xa084, 0x0003, 0xa086, 0x0003, 0x1108, 0x0005,
+	0x2704, 0xac78, 0x7800, 0x701a, 0x7804, 0x701e, 0x7808, 0x7012,
+	0x780c, 0x7016, 0x6004, 0xa084, 0x0008, 0x0120, 0x7810, 0x7022,
+	0x7814, 0x7026, 0x7602, 0x7004, 0xa084, 0x0010, 0xc085, 0x7006,
+	0x2079, 0x4500, 0x8a51, 0x01e8, 0x8738, 0x2704, 0xa005, 0x1168,
+	0x609c, 0xa005, 0x01b8, 0x2060, 0x6004, 0xa084, 0x000f, 0xa080,
+	0x3f9a, 0x203c, 0x87fb, 0x090c, 0x252b, 0x7008, 0x0006, 0xa084,
+	0x01e0, 0x000e, 0x0110, 0xa006, 0x0028, 0xa084, 0x0003, 0xa086,
+	0x0003, 0x0005, 0x2051, 0x0000, 0x0005, 0x0126, 0x0006, 0x00d6,
+	0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x008e, 0x7108,
+	0xa184, 0x0003, 0x1128, 0x6828, 0xa005, 0x0178, 0x0804, 0x3ef3,
+	0x7108, 0xd1fc, 0x0118, 0x080c, 0x4053, 0x0c88, 0x7007, 0x0010,
+	0x7108, 0xd1fc, 0x0de8, 0x080c, 0x4053, 0x7008, 0xa086, 0x0008,
+	0x1d30, 0x7000, 0xa005, 0x1d18, 0x7003, 0x0000, 0x2049, 0x0000,
+	0x012e, 0x2000, 0x0005, 0x0126, 0x0146, 0x0136, 0x0156, 0x00c6,
+	0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x2049,
+	0x428b, 0xad80, 0x0011, 0x20a0, 0xb284, 0x0200, 0x0118, 0x2099,
+	0x0032, 0x0010, 0x2099, 0x0031, 0x700c, 0xa084, 0x07ff, 0x682a,
+	0x7007, 0x0008, 0x7007, 0x0002, 0x7003, 0x0001, 0x0118, 0x8000,
+	0x80ac, 0x53a5, 0x700c, 0xa084, 0x07ff, 0x0130, 0x7007, 0x0004,
+	0x7004, 0xa084, 0x0004, 0x1de0, 0x00ce, 0x2049, 0x0000, 0x7003,
+	0x0000, 0x015e, 0x013e, 0x014e, 0x012e, 0x2000, 0x0005, 0x2091,
+	0x8000, 0x2091, 0x6000, 0x78ac, 0xa005, 0x1168, 0x7974, 0x70d0,
+	0xa106, 0x1148, 0x781c, 0xa005, 0x0130, 0x781f, 0x0000, 0x0e04,
+	0x42db, 0x2091, 0x4080, 0x7830, 0x8001, 0x7832, 0x1904, 0x4345,
+	0x7834, 0x7832, 0x2061, 0x6ac0, 0x2069, 0x4580, 0xc7fd, 0x68cc,
+	0xa005, 0x0128, 0x8001, 0x68ce, 0x1110, 0x080c, 0x44ad, 0x6800,
+	0xa084, 0x000f, 0x0168, 0xa086, 0x0001, 0x0150, 0x6840, 0xa00d,
+	0x0138, 0x2104, 0xa005, 0x0120, 0x8001, 0x200a, 0x0904, 0x444a,
+	0x6814, 0xa005, 0x01a8, 0x8001, 0x6816, 0x1190, 0x68a3, 0x0001,
+	0x00f6, 0xd7fc, 0x1118, 0x2079, 0x0200, 0x0010, 0x2079, 0x0100,
+	0x080c, 0x3c0c, 0x00fe, 0x6860, 0xa005, 0x0110, 0x080c, 0x2296,
+	0x687c, 0xa005, 0x0140, 0x8001, 0x687e, 0x1128, 0x6863, 0x0000,
+	0x68d0, 0xc0c5, 0x68d2, 0x68d0, 0xd0fc, 0x01b0, 0xc0fc, 0x68d2,
+	0x20a9, 0x0200, 0x6034, 0xa005, 0x0158, 0x8001, 0x6036, 0x68d0,
+	0xc0fd, 0x68d2, 0x1128, 0x6010, 0xa005, 0x0110, 0x080c, 0x2296,
+	0xace0, 0x0010, 0x1f04, 0x432a, 0xd7fc, 0x0138, 0x2061, 0x4ac0,
+	0x2069, 0x4540, 0xc7fc, 0x0804, 0x42e7, 0x0459, 0x7838, 0x8001,
+	0x783a, 0x11a0, 0x783c, 0x783a, 0x2061, 0x4ac0, 0x2069, 0x4540,
+	0xc7fc, 0x680c, 0xa005, 0x0110, 0x080c, 0x43c1, 0xd7fc, 0x1130,
+	0x2061, 0x6ac0, 0x2069, 0x4580, 0xc7fd, 0x0c98, 0x7810, 0xd0cc,
+	0x0168, 0xd0ac, 0x1120, 0xd0a4, 0x0148, 0xc0ad, 0x7812, 0x2091,
+	0x8001, 0x0e04, 0x436d, 0x080c, 0x2061, 0x0005, 0x2091, 0x8001,
+	0x0005, 0x7840, 0x8001, 0x7842, 0x1904, 0x43c0, 0x7844, 0x7842,
+	0x2069, 0x4540, 0xc7fc, 0x2079, 0x0200, 0x68d4, 0xa005, 0x0138,
+	0x7de0, 0xa504, 0x1120, 0x68d6, 0x68d0, 0xc0bc, 0x68d2, 0x2079,
+	0x4500, 0x6810, 0xa005, 0x1110, 0x2001, 0x0101, 0x8001, 0x6812,
+	0xd7fc, 0x0118, 0xa080, 0x8bd0, 0x0010, 0xa080, 0x8ac0, 0x2040,
+	0x2004, 0xa065, 0x01e0, 0x6024, 0xa005, 0x01b0, 0x8001, 0x6026,
+	0x1198, 0x6800, 0xa005, 0x0130, 0x6848, 0xac06, 0x1118, 0x080c,
+	0x444a, 0x0068, 0x6860, 0xa005, 0x0118, 0x6027, 0x0001, 0x0020,
+	0x080c, 0x4402, 0x2804, 0x0c28, 0x6000, 0x2c40, 0x0c10, 0xd7fc,
+	0x1138, 0x2069, 0x4580, 0xc7fd, 0x2079, 0x0100, 0x0804, 0x437d,
+	0x0005, 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0558,
+	0x6024, 0xa005, 0x0118, 0x8001, 0x6026, 0x0418, 0x6008, 0xc09c,
+	0xd084, 0x1110, 0xd0ac, 0x01c0, 0x600a, 0x6004, 0xa005, 0x01d8,
+	0x00d6, 0x00c6, 0x0016, 0x2068, 0x6010, 0x8001, 0x6012, 0x080c,
+	0x376c, 0x2d00, 0x2c68, 0x2060, 0x080c, 0x1bc7, 0x080c, 0x1d7c,
+	0x001e, 0x00ce, 0x00de, 0x0038, 0xc0bd, 0x600a, 0xa18d, 0x0001,
+	0x0010, 0xa18d, 0x0100, 0xace0, 0x0010, 0x1f04, 0x43c5, 0xa184,
+	0x0001, 0x0130, 0xa18c, 0xfffe, 0x690e, 0x080c, 0x2296, 0x0008,
+	0x690e, 0x0005, 0x2c00, 0x687a, 0x6714, 0x6f72, 0x6017, 0x0000,
+	0x602b, 0x0000, 0x601b, 0x0006, 0x60b4, 0xa084, 0x5f00, 0x601e,
+	0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042,
+	0x080c, 0x1b5f, 0x6818, 0xa005, 0x0110, 0x8001, 0x681a, 0x6808,
+	0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x1310,
+	0x080c, 0x252b, 0x6812, 0x1118, 0x7910, 0xc1a5, 0x7912, 0x602f,
+	0x0000, 0x6033, 0x0000, 0x2c68, 0x080c, 0x1d89, 0xd7fc, 0x1118,
+	0x2069, 0x4540, 0x0010, 0x2069, 0x4580, 0x6910, 0xa184, 0x0100,
+	0x2001, 0x0006, 0x1118, 0x6976, 0x2001, 0x0004, 0x2708, 0x080c,
+	0x228b, 0x0005, 0x00d6, 0x6948, 0x2160, 0xd7fc, 0x1118, 0x2069,
+	0x0200, 0x0010, 0x2069, 0x0100, 0x080c, 0x2446, 0x601b, 0x0006,
+	0x6858, 0xa084, 0x5f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085,
+	0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6808, 0xa084,
+	0xfffd, 0x680a, 0x6830, 0xd0b4, 0x01b0, 0x684b, 0x0004, 0x20a9,
+	0x0014, 0x6848, 0xd094, 0x0110, 0x1f04, 0x4471, 0x684b, 0x0009,
+	0x20a9, 0x0014, 0x6848, 0xd084, 0x0110, 0x1f04, 0x447a, 0x20a9,
+	0x00fa, 0x1f04, 0x4481, 0x681b, 0x0054, 0x00de, 0x6863, 0x0007,
+	0x0005, 0x2079, 0x4500, 0x00e1, 0x0089, 0x00a9, 0x2009, 0x0002,
+	0x2069, 0x4580, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, 0x0000,
+	0x8109, 0x0118, 0x2069, 0x4540, 0x0ca8, 0x0005, 0x2019, 0x00a3,
+	0x7b3a, 0x7b3e, 0x0005, 0x2019, 0x0033, 0x7b42, 0x7b46, 0x0005,
+	0x2019, 0x32dd, 0x7b32, 0x7b36, 0x0005, 0x694c, 0xa185, 0x0000,
+	0x0158, 0x00c6, 0x6abc, 0x2264, 0x6008, 0xc0b5, 0x600a, 0x8210,
+	0x8109, 0x1dc8, 0x694e, 0x00ce, 0x0005, 0x70ec, 0xd0dc, 0x1118,
+	0xd0d4, 0x0190, 0x0098, 0xae8e, 0x0100, 0x0138, 0x7814, 0xc0f5,
+	0xc0c5, 0x7816, 0xd0d4, 0x11a8, 0x0088, 0x7814, 0xc0fd, 0xc0c5,
+	0x7816, 0xd0d4, 0x1170, 0x0050, 0xd0e4, 0x0168, 0x70e4, 0xa084,
+	0x01ff, 0xa086, 0x01ff, 0x0d38, 0x70a0, 0x70a2, 0x7804, 0xd08c,
+	0x0110, 0x681f, 0x000c, 0x0005, 0x69ca
 };
 #ifdef UNIQUE_FW_NAME
-unsigned short   fw12160i_length01 = 0x32f8;
+unsigned short   fw12160i_length01 = 0x34e5;
 #else
-unsigned short   risc_code_length01 = 0x32f8;
+unsigned short   risc_code_length01 = 0x34e5;
 #endif
 
diff -urN linux-2.4.16/drivers/scsi/ql1280_fw.h lia64-2.4/drivers/scsi/ql1280_fw.h
--- linux-2.4.16/drivers/scsi/ql1280_fw.h	Mon Feb  7 19:45:28 2000
+++ lia64-2.4/drivers/scsi/ql1280_fw.h	Mon Oct 30 22:17:11 2000
@@ -1,59 +1,117 @@
 /************************************************************************
+
  *									*
+
  * 	         --- ISP1240/1080/1280 Initiator Firmware ---           *
+
  *			      32 LUN Support				*
+
  *									*
+
  ************************************************************************
- * Copyright (C) 1999,2000 Qlogic, Corporation.
+
+ *									*
+
+ * Copyright (C) 1999,2000 Qlogic, Corporation
+
  * All rights reserved.
+
  *
+
  * Redistribution and use in source and binary forms are permitted provided
+
  * that the following conditions are met:
+
  * 1. Redistribution of source code must retain the above copyright
+
  *    notice, this list of conditions and the following disclaimer.
- * 2. The name of the author may not be used to endorse or promote products
+
+ * 2. Redistribution in binary form must reproduce the above copyright
+
+ *    notice, this list of conditions and the following disclaimer in the
+
+ *    documentation and/or other materials provided with the distribution.
+
+ * 3. The name of the author may not be used to endorse or promote products
+
  *    derived from this software without specific prior written permission
+
  *
+
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
  *									*
+
  ************************************************************************
+
  */
 
 
 /*
- *	Firmware Version 8.09.00 (18:29 Apr 16, 1999)
+ *	Firmware Version 8.13.08 (10:53 Jan 14, 2000)
  */
 
-unsigned short fw1280ei_version = 8*1024+9;
+#ifdef UNIQUE_FW_NAME
+unsigned short fw1280ei_version = 8*1024+13;
+#else
+unsigned short risc_code_version = 8*1024+13;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned char fw1280ei_version_str[] = {8,13,8};
+#else
+unsigned char firmware_version[] = {8,13,8};
+#endif
 
-unsigned char fw1280ei_version_str[] = {8,9,0};
+#ifdef UNIQUE_FW_NAME
+#define fw1280ei_VERSION_STRING "8.13.8"
+#else
+#define FW_VERSION_STRING "8.13.8"
+#endif
 
+#ifdef UNIQUE_FW_NAME
 unsigned short fw1280ei_addr01 = 0x1000 ;
+#else
+unsigned short risc_code_addr01 = 0x1000 ;
+#endif
 
+#ifdef UNIQUE_FW_NAME
 unsigned short fw1280ei_code01[] = { 
-	0x0078, 0x1041, 0x0000, 0x39e3, 0x0000, 0x2043, 0x4f50, 0x5952,
+#else
+unsigned short risc_code01[] = { 
+#endif
+	0x0078, 0x1041, 0x0000, 0x3c71, 0x0000, 0x2043, 0x4f50, 0x5952,
 	0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31,
 	0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320,
 	0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350,
 	0x3132, 0x3430, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056,
-	0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3039, 0x2020, 0x2043,
+	0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3133, 0x2020, 0x2043,
 	0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050,
 	0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020,
-	0x2400, 0x20c9, 0x93ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080,
+	0x2400, 0x20c9, 0x96ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080,
 	0x00c0, 0x1054, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010,
-	0x2089, 0x136a, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086,
+	0x2089, 0x1374, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086,
 	0x1280, 0x00c0, 0x1069, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2071,
-	0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13ea, 0x0078,
-	0x106d, 0x20c1, 0x0020, 0x2089, 0x1312, 0x2071, 0x0010, 0x70c3,
+	0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13f8, 0x0078,
+	0x106d, 0x20c1, 0x0020, 0x2089, 0x131c, 0x2071, 0x0010, 0x70c3,
 	0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3,
 	0x0008, 0x2001, 0x04fe, 0x70d6, 0x20c1, 0x0021, 0x2019, 0x0000,
 	0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, 0x7fff, 0x2d64,
@@ -61,1838 +119,1924 @@
 	0xa286, 0xa5a5, 0x0040, 0x10a4, 0xa386, 0x000f, 0x0040, 0x10a0,
 	0x2c6a, 0x2a5a, 0x20c1, 0x0020, 0x2019, 0x000f, 0x0078, 0x1080,
 	0x2c6a, 0x2a5a, 0x0078, 0x10a2, 0x2c6a, 0x2a5a, 0x2130, 0x2128,
-	0xa1a2, 0x4a00, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424,
-	0xa192, 0x9400, 0x2009, 0x0000, 0x2001, 0x0032, 0x1078, 0x2078,
-	0x2218, 0x2079, 0x4a00, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9,
-	0x0040, 0x42a4, 0x8109, 0x00c0, 0x10bf, 0x2001, 0x04fc, 0x2004,
-	0xa086, 0x1080, 0x00c0, 0x10db, 0x2071, 0x0100, 0x0d7e, 0x2069,
-	0x4a40, 0x1078, 0x49ae, 0x0d7f, 0x7810, 0xc0ed, 0x7812, 0x781b,
-	0x0064, 0x0078, 0x1100, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1280,
-	0x00c0, 0x10fb, 0x7814, 0xc0ed, 0xc0d5, 0x7816, 0x781b, 0x0064,
-	0x2071, 0x0200, 0x0d7e, 0x2069, 0x4a40, 0x1078, 0x49ae, 0x2069,
-	0x4a80, 0x2071, 0x0100, 0x1078, 0x49ae, 0x7814, 0xc0d4, 0x7816,
-	0x0d7f, 0x0078, 0x1100, 0x7814, 0xc0e5, 0x7816, 0x781b, 0x003c,
-	0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802,
-	0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002,
-	0x2009, 0x0002, 0x2069, 0x4a40, 0x681b, 0x0003, 0x6823, 0x0007,
-	0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0000,
-	0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000, 0x8109, 0x0040,
-	0x1154, 0x68d3, 0x000a, 0x68c3, 0x4ac0, 0x2079, 0x4a00, 0x7814,
-	0xd0e4, 0x00c0, 0x113a, 0xd0ec, 0x00c0, 0x113e, 0x68d7, 0x7329,
-	0x0078, 0x1140, 0x68d7, 0x730d, 0x0078, 0x1140, 0x68d7, 0x7329,
-	0x68c7, 0x4fc0, 0x68cb, 0x4ec0, 0x68cf, 0x8fc0, 0x68ab, 0x9244,
-	0x68af, 0x9249, 0x68b3, 0x9244, 0x68b7, 0x9244, 0x68a7, 0x0001,
-	0x2069, 0x4a80, 0x0078, 0x1114, 0x68d3, 0x000a, 0x68c3, 0x4cc0,
-	0x7814, 0xd0e4, 0x00c0, 0x1160, 0x68d7, 0x7439, 0x0078, 0x1162,
-	0x68d7, 0x7419, 0x68c7, 0x6fc0, 0x68cb, 0x4f40, 0x68cf, 0x90d0,
-	0x68ab, 0x9249, 0x68af, 0x924e, 0x68b3, 0x9249, 0x68b7, 0x9249,
-	0x68a7, 0x0001, 0x7810, 0xd0ec, 0x00c0, 0x11b8, 0x7814, 0xd0e4,
-	0x00c0, 0x11aa, 0x0e7e, 0x2069, 0x4ec0, 0x2071, 0x0200, 0x70ec,
-	0xd0e4, 0x00c0, 0x118b, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078,
-	0x2007, 0x0078, 0x1191, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078,
-	0x2007, 0x2069, 0x4f40, 0x2071, 0x0100, 0x70ec, 0xd0e4, 0x00c0,
-	0x11a1, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, 0x2007, 0x0078,
-	0x11a7, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, 0x2007, 0x0e7f,
-	0x0078, 0x11d1, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x2069, 0x4ec0,
-	0x1078, 0x2007, 0x2069, 0x4f40, 0x1078, 0x2007, 0x0078, 0x11d1,
-	0x2069, 0x4ec0, 0x0e7e, 0x2071, 0x0100, 0x70ec, 0xd0e4, 0x00c0,
-	0x11ca, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, 0x2007, 0x0e7f,
-	0x0078, 0x11d1, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, 0x2007,
-	0x0e7f, 0x2011, 0x0002, 0x2069, 0x4fc0, 0x2009, 0x0002, 0x20a9,
-	0x0100, 0x683f, 0x0000, 0x680b, 0x0040, 0x7bc8, 0xa386, 0xfeff,
-	0x00c0, 0x11e8, 0x6817, 0x0100, 0x681f, 0x0064, 0x0078, 0x11ec,
-	0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, 0x00f0, 0x11d9,
-	0x8109, 0x00c0, 0x11d7, 0x8211, 0x0040, 0x11fa, 0x2069, 0x6fc0,
-	0x0078, 0x11d5, 0x1078, 0x2611, 0x1078, 0x441d, 0x1078, 0x1df2,
-	0x1078, 0x4957, 0x2091, 0x2100, 0x2079, 0x4a00, 0x7810, 0xd0ec,
-	0x0040, 0x120e, 0x2071, 0x0020, 0x0078, 0x1210, 0x2071, 0x0050,
-	0x2091, 0x2200, 0x2079, 0x4a00, 0x2071, 0x0020, 0x2091, 0x2300,
-	0x2079, 0x4a00, 0x7810, 0xd0ec, 0x0040, 0x1222, 0x2079, 0x0100,
-	0x0078, 0x1224, 0x2079, 0x0200, 0x2071, 0x4a40, 0x2091, 0x2400,
-	0x2079, 0x0100, 0x2071, 0x4a80, 0x2091, 0x2000, 0x2079, 0x4a00,
-	0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, 0x2071, 0x0010,
-	0x70c3, 0x0000, 0x0090, 0x1243, 0x70c0, 0xa086, 0x0002, 0x00c0,
-	0x1243, 0x1078, 0x159d, 0x2039, 0x0000, 0x7810, 0xd0ec, 0x00c0,
-	0x12c5, 0x1078, 0x1472, 0x78ac, 0xa005, 0x00c0, 0x1261, 0x0068,
-	0x1257, 0x786c, 0xa065, 0x0040, 0x1257, 0x1078, 0x2368, 0x1078,
-	0x209f, 0x0068, 0x126e, 0x786c, 0xa065, 0x0040, 0x1261, 0x1078,
-	0x2368, 0x0068, 0x126e, 0x2009, 0x4a47, 0x2011, 0x4a87, 0x2104,
-	0x220c, 0xa105, 0x0040, 0x126e, 0x1078, 0x1f1e, 0x2071, 0x4a40,
-	0x70a4, 0xa005, 0x0040, 0x1293, 0x7450, 0xa485, 0x0000, 0x0040,
-	0x1293, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4, 0xa28c, 0x303d,
-	0x2190, 0x1078, 0x2a9c, 0x2091, 0x8000, 0x2091, 0x303d, 0x0068,
-	0x1293, 0x2079, 0x4a00, 0x786c, 0xa065, 0x0040, 0x1293, 0x2071,
-	0x0010, 0x1078, 0x2368, 0x00e0, 0x129b, 0x2079, 0x4a00, 0x2071,
-	0x0010, 0x1078, 0x4765, 0x2071, 0x4a80, 0x70a4, 0xa005, 0x0040,
-	0x12b3, 0x7050, 0xa025, 0x0040, 0x12b3, 0x2079, 0x0100, 0x2091,
-	0x8000, 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, 0x2a9c, 0x2091,
-	0x8000, 0x2091, 0x303d, 0x2079, 0x4a00, 0x2071, 0x0010, 0x0068,
-	0x12bf, 0x786c, 0xa065, 0x0040, 0x12bf, 0x1078, 0x2368, 0x00e0,
-	0x1249, 0x1078, 0x4765, 0x0078, 0x1249, 0x1078, 0x1472, 0x78ac,
-	0xa005, 0x00c0, 0x12dd, 0x0068, 0x12d3, 0x786c, 0xa065, 0x0040,
-	0x12d3, 0x1078, 0x2368, 0x1078, 0x209f, 0x0068, 0x12e7, 0x786c,
-	0xa065, 0x0040, 0x12dd, 0x1078, 0x2368, 0x0068, 0x12e7, 0x2009,
-	0x4a47, 0x2104, 0xa005, 0x0040, 0x12e7, 0x1078, 0x1f1e, 0x2071,
-	0x4a40, 0x70a4, 0xa005, 0x0040, 0x1302, 0x7450, 0xa485, 0x0000,
-	0x0040, 0x1302, 0x2079, 0x0100, 0x2091, 0x8000, 0x72d4, 0xa28c,
-	0x303d, 0x2190, 0x1078, 0x2a9c, 0x2091, 0x8000, 0x2091, 0x303d,
-	0x2079, 0x4a00, 0x2071, 0x0010, 0x0068, 0x130c, 0x786c, 0xa065,
-	0x0040, 0x130c, 0x1078, 0x2368, 0x00e0, 0x12c5, 0x1078, 0x4765,
-	0x0078, 0x12c5, 0x1332, 0x1332, 0x1334, 0x1334, 0x1341, 0x1341,
-	0x1341, 0x1341, 0x134c, 0x134c, 0x1359, 0x1359, 0x1341, 0x1341,
-	0x1341, 0x1341, 0x1332, 0x1332, 0x1334, 0x1334, 0x1341, 0x1341,
-	0x1341, 0x1341, 0x134c, 0x134c, 0x1359, 0x1359, 0x1341, 0x1341,
-	0x1341, 0x1341, 0x0078, 0x1332, 0x007e, 0x107e, 0x127e, 0x2091,
-	0x2400, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001,
-	0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13ba, 0x127f, 0x107f,
-	0x007f, 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x2091,
-	0x2300, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001,
-	0x007c, 0x007e, 0x107e, 0x127e, 0x2091, 0x2300, 0x1078, 0x290b,
-	0x2091, 0x2400, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091,
-	0x8001, 0x007c, 0x138a, 0x138a, 0x138c, 0x138c, 0x1399, 0x1399,
-	0x1399, 0x1399, 0x13a4, 0x13a4, 0x138c, 0x138c, 0x1399, 0x1399,
-	0x1399, 0x1399, 0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5,
-	0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5, 0x13a5,
-	0x13a5, 0x13a5, 0x0078, 0x138a, 0x007e, 0x107e, 0x127e, 0x2091,
-	0x2300, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001,
-	0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13c7, 0x127f, 0x107f,
-	0x007f, 0x2091, 0x8001, 0x007c, 0x007c, 0x107e, 0x127e, 0x0d7e,
-	0x0e7e, 0x0f7e, 0x007e, 0x2071, 0x0100, 0x2069, 0x4a40, 0x2079,
-	0x4a00, 0x1078, 0x49ae, 0x007f, 0x0f7f, 0x0e7f, 0x0d7f, 0x127f,
-	0x107f, 0x007c, 0x3c00, 0xa084, 0x0007, 0x0079, 0x13bf, 0x13d0,
-	0x13d0, 0x13d2, 0x13d2, 0x13d7, 0x13d7, 0x13dc, 0x13dc, 0x3c00,
-	0xa084, 0x0003, 0x0079, 0x13cc, 0x13d0, 0x13d0, 0x13e5, 0x13e5,
-	0x1078, 0x28ec, 0x2091, 0x2200, 0x1078, 0x44b7, 0x007c, 0x2091,
-	0x2100, 0x1078, 0x44b7, 0x007c, 0x2091, 0x2100, 0x1078, 0x44b7,
-	0x2091, 0x2200, 0x1078, 0x44b7, 0x007c, 0x2091, 0x2100, 0x1078,
-	0x44b7, 0x007c, 0x140a, 0x140a, 0x140c, 0x140c, 0x1419, 0x1419,
-	0x1419, 0x1419, 0x1424, 0x1424, 0x1431, 0x1431, 0x1419, 0x1419,
-	0x1419, 0x1419, 0x1442, 0x1442, 0x1442, 0x1442, 0x1442, 0x1442,
-	0x1442, 0x1442, 0x1442, 0x1442, 0x1442, 0x1442, 0x1442, 0x1442,
-	0x1442, 0x1442, 0x0078, 0x140a, 0x007e, 0x107e, 0x127e, 0x2091,
-	0x2400, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001,
-	0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13ba, 0x127f, 0x107f,
-	0x007f, 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x2091,
-	0x2300, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001,
-	0x007c, 0x007e, 0x107e, 0x127e, 0x2091, 0x2300, 0x1078, 0x290b,
-	0x2091, 0x2400, 0x1078, 0x290b, 0x127f, 0x107f, 0x007f, 0x2091,
-	0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x0d7e, 0x0e7e, 0x0f7e,
-	0x2079, 0x4a00, 0x2071, 0x0200, 0x2069, 0x4a40, 0x3d00, 0xd08c,
-	0x00c0, 0x1456, 0x2069, 0x4a80, 0x2071, 0x0100, 0x1078, 0x49ae,
-	0x0f7f, 0x0e7f, 0x0d7f, 0x127f, 0x107f, 0x007f, 0x007c, 0x7008,
-	0x800b, 0x00c8, 0x146d, 0x7007, 0x0002, 0xa08c, 0x01e0, 0x00c0,
-	0x146e, 0xd09c, 0x0040, 0x146d, 0x087a, 0x097a, 0x70c3, 0x4002,
-	0x0078, 0x15a0, 0x0068, 0x14f7, 0x2061, 0x0000, 0x6018, 0xd084,
-	0x00c0, 0x14f7, 0x7828, 0xa005, 0x00c0, 0x1482, 0x0010, 0x14f8,
-	0x0078, 0x14f7, 0x7910, 0xd1f4, 0x0040, 0x148a, 0x2001, 0x4007,
-	0x0078, 0x159f, 0x7914, 0xd1ec, 0x0040, 0x14a5, 0xd0fc, 0x0040,
-	0x149b, 0x007e, 0x1078, 0x1d82, 0x007f, 0x0040, 0x14a5, 0x2001,
-	0x4007, 0x0078, 0x159f, 0x007e, 0x1078, 0x1d72, 0x007f, 0x0040,
-	0x14a5, 0x2001, 0x4007, 0x0078, 0x159f, 0x7910, 0xd0fc, 0x00c0,
-	0x14af, 0x2061, 0x4a40, 0xc19c, 0xc7fc, 0x0078, 0x14b3, 0x2061,
-	0x4a80, 0xc19d, 0xc7fd, 0x6064, 0xa005, 0x00c0, 0x14f7, 0x7912,
-	0x6083, 0x0000, 0x7828, 0xc0fc, 0xa086, 0x0018, 0x00c0, 0x14c4,
-	0x0c7e, 0x1078, 0x1b13, 0x0c7f, 0x782b, 0x0000, 0x607c, 0xa065,
-	0x0040, 0x14dd, 0x0c7e, 0x609c, 0x1078, 0x1e5d, 0x0c7f, 0x609f,
-	0x0000, 0x1078, 0x1c3f, 0x2009, 0x0018, 0x6087, 0x0103, 0x1078,
-	0x1d92, 0x00c0, 0x14f1, 0x1078, 0x1de4, 0x7810, 0xd09c, 0x00c0,
-	0x14e5, 0x2061, 0x4a40, 0x0078, 0x14e9, 0x2061, 0x4a80, 0xc09c,
-	0x7812, 0x607f, 0x0000, 0x60d4, 0xd0dc, 0x0040, 0x14f5, 0xc0dc,
-	0x60d6, 0x2001, 0x4005, 0x0078, 0x159f, 0x0078, 0x159d, 0x007c,
-	0x7810, 0xd0f4, 0x0040, 0x1500, 0x2001, 0x4007, 0x0078, 0x159f,
-	0xa006, 0x70c2, 0x70c6, 0x70ca, 0x70ce, 0x70da, 0x70c0, 0xa08a,
-	0x0040, 0x00c8, 0x150d, 0x0079, 0x1514, 0x2100, 0xa08a, 0x0040,
-	0x00c8, 0x15ab, 0x0079, 0x1554, 0x159d, 0x15f3, 0x15bc, 0x162b,
-	0x1663, 0x1663, 0x15b3, 0x1c57, 0x166e, 0x15ab, 0x15c0, 0x15c2,
-	0x15c4, 0x15c6, 0x1c5c, 0x15ab, 0x167c, 0x16d4, 0x1b35, 0x1c51,
-	0x15c8, 0x19a7, 0x19e9, 0x1a1f, 0x1a6b, 0x1962, 0x196f, 0x1983,
-	0x1996, 0x17a4, 0x1cdc, 0x1706, 0x1713, 0x171f, 0x172b, 0x1741,
-	0x174d, 0x1750, 0x175c, 0x1768, 0x1770, 0x178c, 0x1798, 0x15ab,
-	0x15ab, 0x15ab, 0x15ab, 0x17b1, 0x17c3, 0x17df, 0x1815, 0x183d,
-	0x184d, 0x1850, 0x1881, 0x18b2, 0x18c4, 0x1931, 0x1941, 0x1d32,
-	0x15ab, 0x15ab, 0x15ab, 0x1951, 0x15ab, 0x15ab, 0x15ab, 0x15ab,
-	0x15ab, 0x1c81, 0x1c87, 0x15ab, 0x15ab, 0x15ab, 0x1c8b, 0x1cd8,
-	0x15ab, 0x15ab, 0x1ce8, 0x1cf7, 0x15ed, 0x165d, 0x1676, 0x16ce,
-	0x1b2f, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x1d39, 0x1c73, 0x1c7d,
-	0x15ab, 0x15ab, 0x1d02, 0x1d1b, 0x15ab, 0x15ab, 0x15ab, 0x15ab,
-	0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab,
-	0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab,
-	0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x15ab,
-	0x15ab, 0x15ab, 0x15ab, 0x15ab, 0x72ca, 0x71c6, 0x2001, 0x4006,
-	0x0078, 0x159f, 0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2,
-	0x0068, 0x15a0, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000,
-	0x2091, 0x4080, 0x007c, 0x70c3, 0x4001, 0x0078, 0x15a0, 0x70c3,
-	0x4006, 0x0078, 0x15a0, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9,
-	0x0005, 0x53a3, 0x0078, 0x159d, 0x70c4, 0x70c3, 0x0004, 0x007a,
-	0x0078, 0x159d, 0x0078, 0x159d, 0x0078, 0x159d, 0x0078, 0x159d,
-	0x2091, 0x8000, 0x70c3, 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020,
-	0x70cf, 0x2020, 0x70d3, 0x0008, 0x2001, 0x0009, 0x70d6, 0x2079,
-	0x0000, 0x781b, 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029,
-	0x041a, 0x2051, 0x0445, 0x2061, 0x0447, 0x20c1, 0x0020, 0x2091,
-	0x5000, 0x2091, 0x4080, 0x0078, 0x0418, 0x75d8, 0x74dc, 0x75da,
-	0x74de, 0x0078, 0x15f6, 0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8,
-	0x73cc, 0x70c4, 0x20a0, 0x2099, 0x0030, 0x7003, 0x0001, 0x7007,
-	0x0006, 0x731a, 0x721e, 0x7422, 0x7526, 0x2021, 0x0040, 0x81ff,
-	0x0040, 0x159d, 0xa182, 0x0040, 0x00c8, 0x1610, 0x2120, 0xa006,
-	0x2008, 0x8403, 0x7012, 0x7007, 0x0004, 0x7007, 0x0001, 0x7008,
-	0xd0fc, 0x0040, 0x1617, 0x7007, 0x0002, 0xa084, 0x01e0, 0x0040,
-	0x1625, 0x70c3, 0x4002, 0x0078, 0x15a0, 0x24a8, 0x53a5, 0x0078,
-	0x1607, 0x0078, 0x159d, 0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8,
-	0x73cc, 0x70c4, 0x2098, 0x20a1, 0x0030, 0x7003, 0x0000, 0x7007,
-	0x0006, 0x731a, 0x721e, 0x7422, 0x7526, 0x2021, 0x0040, 0x7007,
-	0x0006, 0x81ff, 0x0040, 0x159d, 0xa182, 0x0040, 0x00c8, 0x164a,
-	0x2120, 0xa006, 0x2008, 0x8403, 0x7012, 0x24a8, 0x53a6, 0x7007,
-	0x0001, 0x7008, 0xd0fc, 0x0040, 0x1651, 0xa084, 0x01e0, 0x0040,
-	0x163f, 0x70c3, 0x4002, 0x0078, 0x15a0, 0x75d8, 0x74dc, 0x75da,
-	0x74de, 0x0078, 0x162e, 0x71c4, 0x70c8, 0x2114, 0xa79e, 0x0004,
-	0x00c0, 0x166b, 0x200a, 0x72ca, 0x0078, 0x159c, 0x70c7, 0x0008,
-	0x70cb, 0x0009, 0x70cf, 0x0000, 0x0078, 0x159d, 0x75d8, 0x76dc,
-	0x75da, 0x76de, 0x0078, 0x167f, 0x2029, 0x0000, 0x2530, 0x70c4,
-	0x72c8, 0x73cc, 0x74d0, 0x70c6, 0x72ca, 0x73ce, 0x74d2, 0xa005,
-	0x0040, 0x16c9, 0x8001, 0x7872, 0xa084, 0xfc00, 0x0040, 0x1697,
-	0x78ac, 0xc085, 0x78ae, 0x2001, 0x4005, 0x0078, 0x159f, 0x7b7e,
-	0x7a7a, 0x7e86, 0x7d82, 0x7c76, 0xa48c, 0xff00, 0x0040, 0x16af,
-	0x8407, 0x8004, 0x8004, 0x810c, 0x810c, 0x810f, 0xa118, 0xa291,
-	0x0000, 0xa6b1, 0x0000, 0xa581, 0x0000, 0x0078, 0x16b9, 0x8407,
-	0x8004, 0x8004, 0xa318, 0xa291, 0x0000, 0xa6b1, 0x0000, 0xa581,
-	0x0000, 0x731a, 0x721e, 0x7622, 0x7026, 0xa605, 0x0040, 0x16c3,
-	0x7a10, 0xc2c5, 0x7a12, 0x78ac, 0xa084, 0xfffc, 0x78ae, 0x0078,
-	0x16cc, 0x78ac, 0xc085, 0x78ae, 0x0078, 0x159d, 0x75d8, 0x76dc,
-	0x75da, 0x76de, 0x0078, 0x16d7, 0x2029, 0x0000, 0x2530, 0x70c4,
-	0x72c8, 0x73cc, 0x74d4, 0x70c6, 0x72ca, 0x73ce, 0x74d6, 0xa005,
-	0x0040, 0x1701, 0x8001, 0x7892, 0xa084, 0xfc00, 0x0040, 0x16ef,
-	0x78ac, 0xc0c5, 0x78ae, 0x2001, 0x4005, 0x0078, 0x159f, 0x7a9a,
-	0x7b9e, 0x7da2, 0x7ea6, 0x2600, 0xa505, 0x0040, 0x16fa, 0x7a10,
-	0xc2c5, 0x7a12, 0x7c96, 0x78ac, 0xa084, 0xfcff, 0x78ae, 0x0078,
-	0x1704, 0x78ac, 0xc0c5, 0x78ae, 0x0078, 0x159d, 0x2009, 0x0000,
-	0x786c, 0xa065, 0x0040, 0x1710, 0x8108, 0x6000, 0x0078, 0x1709,
-	0x7ac4, 0x0078, 0x159b, 0x2009, 0x4a48, 0x210c, 0x7810, 0xd0ec,
-	0x00c0, 0x159c, 0x2011, 0x4a88, 0x2214, 0x0078, 0x159b, 0x2009,
-	0x4a49, 0x210c, 0x7810, 0xd0ec, 0x00c0, 0x159c, 0x2011, 0x4a89,
-	0x2214, 0x0078, 0x159b, 0x2061, 0x4a40, 0x6128, 0x622c, 0x8214,
-	0x8214, 0x8214, 0x7810, 0xd0ec, 0x00c0, 0x173f, 0x2061, 0x4a80,
-	0x6328, 0x73da, 0x632c, 0x831c, 0x831c, 0x831c, 0x73de, 0x0078,
-	0x159b, 0x2009, 0x4a4c, 0x210c, 0x7810, 0xd0ec, 0x00c0, 0x159c,
-	0x2011, 0x4a8c, 0x2214, 0x0078, 0x159b, 0x7918, 0x0078, 0x159c,
-	0x2009, 0x4a4d, 0x210c, 0x7810, 0xd0ec, 0x00c0, 0x159c, 0x2011,
-	0x4a8d, 0x2214, 0x0078, 0x159b, 0x2009, 0x4a4e, 0x210c, 0x7810,
-	0xd0ec, 0x00c0, 0x159c, 0x2011, 0x4a8e, 0x2214, 0x0078, 0x159b,
-	0x7920, 0x7810, 0xd0ec, 0x00c0, 0x159c, 0x7a24, 0x0078, 0x159b,
-	0x71c4, 0xd1fc, 0x00c0, 0x1778, 0x2011, 0x4ec0, 0x0078, 0x177a,
-	0x2011, 0x4f40, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003,
-	0xa268, 0x6a00, 0x6804, 0xd09c, 0x0040, 0x1789, 0x6b08, 0x0078,
-	0x178a, 0x6b0c, 0x0078, 0x159a, 0x77c4, 0x1078, 0x1e02, 0x2091,
-	0x8000, 0x6b1c, 0x6a14, 0x2091, 0x8001, 0x2708, 0x0078, 0x159a,
-	0x2061, 0x4a40, 0x6118, 0x7810, 0xd0ec, 0x00c0, 0x159c, 0x2061,
-	0x4a80, 0x6218, 0x0078, 0x159b, 0x77c4, 0x1078, 0x1e02, 0x2091,
-	0x8000, 0x6908, 0x6a18, 0x6b10, 0x77da, 0x2091, 0x8001, 0x0078,
-	0x159a, 0x71c4, 0x2110, 0xa294, 0x000f, 0xa282, 0x0010, 0x00c8,
-	0x1595, 0x1078, 0x2729, 0xa384, 0x4000, 0x0040, 0x17c1, 0xa295,
-	0x0020, 0x0078, 0x159a, 0x71c4, 0x2100, 0xc0bc, 0xa082, 0x0010,
-	0x00c8, 0x1595, 0xd1bc, 0x00c0, 0x17d2, 0x2011, 0x4a48, 0x2204,
-	0x0078, 0x17d6, 0x2011, 0x4a88, 0x2204, 0xc0bd, 0x007e, 0x2100,
-	0xc0bc, 0x2012, 0x1078, 0x2686, 0x017f, 0x0078, 0x159c, 0x71c4,
-	0x2021, 0x4a49, 0x2404, 0x70c6, 0x2019, 0x0000, 0x0078, 0x17ee,
-	0x71c8, 0x2021, 0x4a89, 0x2404, 0x70ca, 0xc3fd, 0x2011, 0x180d,
-	0x20a9, 0x0008, 0x2204, 0xa106, 0x0040, 0x17fd, 0x8210, 0x00f0,
-	0x17f2, 0x71c4, 0x72c8, 0x0078, 0x1594, 0xa292, 0x180d, 0x027e,
-	0x2122, 0x017f, 0x1078, 0x26a7, 0x7810, 0xd0ec, 0x00c0, 0x180b,
-	0xd3fc, 0x0040, 0x17e8, 0x0078, 0x159d, 0x03e8, 0x00fa, 0x01f4,
-	0x02ee, 0x0064, 0x0019, 0x0032, 0x004b, 0x2061, 0x4a40, 0x6128,
-	0x622c, 0x8214, 0x8214, 0x8214, 0x70c4, 0x602a, 0x70c8, 0x8003,
-	0x8003, 0x8003, 0x602e, 0x7810, 0xd0ec, 0x00c0, 0x183b, 0x027e,
-	0x017e, 0x2061, 0x4a80, 0x6128, 0x622c, 0x8214, 0x8214, 0x8214,
-	0x70d8, 0x602a, 0x70dc, 0x8003, 0x8003, 0x8003, 0x602e, 0x71da,
-	0x72de, 0x017f, 0x027f, 0x0078, 0x159b, 0x2061, 0x4a40, 0x6130,
-	0x70c4, 0x6032, 0x7810, 0xd0ec, 0x00c0, 0x159c, 0x2061, 0x4a80,
-	0x6230, 0x70c8, 0x6032, 0x0078, 0x159b, 0x7918, 0x0078, 0x159c,
-	0x71c4, 0xa184, 0xffcf, 0x0040, 0x185c, 0x7810, 0xd0ec, 0x00c0,
-	0x1595, 0x72c8, 0x0078, 0x1594, 0x2011, 0x4a4d, 0x2204, 0x2112,
-	0x007e, 0x2019, 0x0000, 0x1078, 0x270e, 0x7810, 0xd0ec, 0x0040,
-	0x186c, 0x017f, 0x0078, 0x159c, 0x71c8, 0xa184, 0xffcf, 0x0040,
-	0x1875, 0x2110, 0x71c4, 0x0078, 0x1594, 0x2011, 0x4a8d, 0x2204,
-	0x2112, 0x007e, 0xc3fd, 0x1078, 0x270e, 0x027f, 0x017f, 0x0078,
-	0x159b, 0x71c4, 0xa182, 0x0010, 0x0048, 0x188d, 0x7810, 0xd0ec,
-	0x00c0, 0x1595, 0x72c8, 0x0078, 0x1594, 0x2011, 0x4a4e, 0x2204,
-	0x007e, 0x2112, 0x2019, 0x0000, 0x1078, 0x26ec, 0x7810, 0xd0ec,
-	0x0040, 0x189d, 0x017f, 0x0078, 0x159c, 0x71c8, 0xa182, 0x0010,
-	0x0048, 0x18a6, 0x2110, 0x71c4, 0x0078, 0x1594, 0x2011, 0x4a8e,
-	0x2204, 0x007e, 0x2112, 0xc3fd, 0x1078, 0x26ec, 0x027f, 0x017f,
-	0x0078, 0x159b, 0x71c4, 0x72c8, 0xa184, 0xfffd, 0x00c0, 0x1594,
-	0xa284, 0xfffd, 0x00c0, 0x1594, 0x2100, 0x7920, 0x7822, 0x2200,
-	0x7a24, 0x7826, 0x0078, 0x159b, 0x71c4, 0xd1fc, 0x00c0, 0x18cc,
-	0x2011, 0x4ec0, 0x0078, 0x18ce, 0x2011, 0x4f40, 0x8107, 0xa084,
-	0x000f, 0x8003, 0x8003, 0x8003, 0xa268, 0x2019, 0x0000, 0x72c8,
-	0xa284, 0x0080, 0x0040, 0x18e2, 0x6c14, 0x84ff, 0x00c0, 0x18e2,
-	0x6817, 0x0040, 0xa284, 0x0040, 0x0040, 0x18ec, 0x6c10, 0x84ff,
-	0x00c0, 0x18ec, 0x6813, 0x0001, 0x6800, 0x007e, 0xa226, 0x0040,
-	0x1909, 0x6a02, 0xd4ec, 0x0040, 0x18f6, 0xc3a5, 0xd4e4, 0x0040,
-	0x18fa, 0xc39d, 0xd4f4, 0x0040, 0x1909, 0x810f, 0xd2f4, 0x0040,
-	0x1905, 0x1078, 0x276b, 0x0078, 0x1909, 0x1078, 0x2749, 0x0078,
-	0x1909, 0x72cc, 0x6808, 0xa206, 0x0040, 0x1929, 0xa2a4, 0x00ff,
-	0x7814, 0xd0e4, 0x00c0, 0x191c, 0xa482, 0x0028, 0x0048, 0x1926,
-	0x0040, 0x1926, 0x0078, 0x1920, 0xa482, 0x0043, 0x0048, 0x1926,
-	0x71c4, 0x71c6, 0x027f, 0x72ca, 0x0078, 0x1596, 0x6a0a, 0xa39d,
-	0x000a, 0x6804, 0xa305, 0x6806, 0x027f, 0x6b0c, 0x71c4, 0x0078,
-	0x159a, 0x77c4, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6a14, 0x6b1c,
-	0x2091, 0x8001, 0x70c8, 0x6816, 0x70cc, 0x681e, 0x2708, 0x0078,
-	0x159a, 0x70c4, 0x2061, 0x4a40, 0x6118, 0x601a, 0x7810, 0xd0ec,
-	0x00c0, 0x159c, 0x70c8, 0x2061, 0x4a80, 0x6218, 0x601a, 0x0078,
-	0x159b, 0x71c4, 0x72c8, 0x73cc, 0xa182, 0x0010, 0x00c8, 0x1595,
-	0x1078, 0x278d, 0xa384, 0x4000, 0x0040, 0x1960, 0xa295, 0x0020,
-	0x0078, 0x159a, 0x77c4, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6a08,
-	0xc28d, 0x6a0a, 0x2091, 0x8001, 0x2708, 0x0078, 0x159b, 0x77c4,
-	0x1078, 0x1e02, 0x2091, 0x8000, 0x6a08, 0xa294, 0xfff9, 0x6a0a,
-	0x6804, 0xa005, 0x0040, 0x197e, 0x1078, 0x25de, 0x2091, 0x8001,
-	0x2708, 0x0078, 0x159b, 0x77c4, 0x1078, 0x1e02, 0x2091, 0x8000,
-	0x6a08, 0xc295, 0x6a0a, 0x6804, 0xa005, 0x0040, 0x1991, 0x1078,
-	0x25de, 0x2091, 0x8001, 0x2708, 0x0078, 0x159b, 0x77c4, 0x2041,
-	0x0001, 0x2049, 0x0005, 0x2051, 0x0020, 0x2091, 0x8000, 0x1078,
-	0x1e1d, 0x2091, 0x8001, 0x2708, 0x6a08, 0x0078, 0x159b, 0x77c4,
-	0x7814, 0xd0e4, 0x00c0, 0x19bb, 0xd7fc, 0x0040, 0x19b5, 0x1078,
-	0x1d82, 0x0040, 0x19bb, 0x0078, 0x159f, 0x1078, 0x1d72, 0x0040,
-	0x19bb, 0x0078, 0x159f, 0x73c8, 0x72cc, 0x77c6, 0x73ca, 0x72ce,
-	0x1078, 0x1e9a, 0x00c0, 0x19e5, 0x6818, 0xa005, 0x0040, 0x19df,
-	0x2708, 0x077e, 0x1078, 0x27bd, 0x077f, 0x00c0, 0x19df, 0x2001,
-	0x0015, 0xd7fc, 0x00c0, 0x19d8, 0x2061, 0x4a40, 0x0078, 0x19db,
-	0xc0fd, 0x2061, 0x4a80, 0x782a, 0x2091, 0x8001, 0x007c, 0x2091,
-	0x8001, 0x2001, 0x4005, 0x0078, 0x159f, 0x2091, 0x8001, 0x0078,
-	0x159d, 0x77c4, 0x7814, 0xd0e4, 0x00c0, 0x19fd, 0xd7fc, 0x0040,
-	0x19f7, 0x1078, 0x1d82, 0x0040, 0x19fd, 0x0078, 0x159f, 0x1078,
-	0x1d72, 0x0040, 0x19fd, 0x0078, 0x159f, 0x77c6, 0x2041, 0x0021,
-	0x2049, 0x0005, 0x2051, 0x0020, 0x2091, 0x8000, 0x1078, 0x1e1d,
-	0x2009, 0x0016, 0xd7fc, 0x00c0, 0x1a11, 0x2061, 0x4a40, 0x0078,
-	0x1a14, 0x2061, 0x4a80, 0xc1fd, 0x6067, 0x0003, 0x6776, 0x6083,
-	0x000f, 0x792a, 0x1078, 0x25de, 0x2091, 0x8001, 0x007c, 0x77c8,
-	0x77ca, 0x77c4, 0x77c6, 0x7814, 0xd0e4, 0x00c0, 0x1a36, 0xd7fc,
-	0x0040, 0x1a30, 0x1078, 0x1d82, 0x0040, 0x1a36, 0x0078, 0x159f,
-	0x1078, 0x1d72, 0x0040, 0x1a36, 0x0078, 0x159f, 0xa7bc, 0xff00,
-	0x2091, 0x8000, 0x2009, 0x0017, 0xd7fc, 0x00c0, 0x1a43, 0x2061,
-	0x4a40, 0x0078, 0x1a46, 0x2061, 0x4a80, 0xc1fd, 0x6067, 0x0002,
-	0x6776, 0x6083, 0x000f, 0x792a, 0x1078, 0x25de, 0x2091, 0x8001,
-	0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0010, 0x2091, 0x8000,
-	0x70c8, 0xa005, 0x0040, 0x1a5f, 0x60d4, 0xc0fd, 0x60d6, 0x1078,
-	0x1e1d, 0x70c8, 0x683e, 0x8738, 0xa784, 0x001f, 0x00c0, 0x1a5f,
-	0x2091, 0x8001, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x1a7f, 0x72c8,
-	0xd284, 0x0040, 0x1a79, 0x1078, 0x1d82, 0x0040, 0x1a7f, 0x0078,
-	0x159f, 0x1078, 0x1d72, 0x0040, 0x1a7f, 0x0078, 0x159f, 0x72c8,
-	0x72ca, 0x78ac, 0xa084, 0x0003, 0x00c0, 0x1aaa, 0x2039, 0x0000,
-	0xd284, 0x0040, 0x1a8c, 0xc7fd, 0x2041, 0x0021, 0x2049, 0x0004,
-	0x2051, 0x0008, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6808, 0xc0d4,
-	0xa80d, 0x690a, 0x2091, 0x8001, 0x8738, 0xa784, 0x001f, 0x00c0,
-	0x1a92, 0xa7bc, 0xff00, 0x873f, 0x8738, 0x873f, 0xa784, 0x0f00,
-	0x00c0, 0x1a92, 0x2091, 0x8000, 0x72c8, 0xd284, 0x00c0, 0x1abc,
-	0x7810, 0xd0ec, 0x0040, 0x1ab8, 0x2069, 0x0100, 0x0078, 0x1abe,
-	0x2069, 0x0200, 0x0078, 0x1abe, 0x2069, 0x0100, 0x6830, 0xd0b4,
-	0x0040, 0x1ada, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094,
-	0x0040, 0x1acc, 0x00f0, 0x1ac6, 0x684b, 0x0009, 0x20a9, 0x0014,
-	0x6848, 0xd084, 0x0040, 0x1ad6, 0x00f0, 0x1ad0, 0x20a9, 0x00fa,
-	0x00f0, 0x1ad8, 0x2079, 0x4a00, 0x2009, 0x0018, 0x72c8, 0xd284,
-	0x00c0, 0x1ae6, 0x2061, 0x4a40, 0x0078, 0x1ae9, 0x2061, 0x4a80,
-	0xc1fd, 0x792a, 0x6067, 0x0001, 0x6083, 0x000f, 0x60a7, 0x0000,
-	0x60a8, 0x60b2, 0x60b6, 0x60d4, 0xd0b4, 0x0040, 0x1b03, 0xc0b4,
-	0x60d6, 0x0c7e, 0x60b8, 0xa065, 0x6008, 0xc0d4, 0x600a, 0x6018,
-	0x8001, 0x601a, 0x0c7f, 0x60d4, 0xa084, 0x77ff, 0x60d6, 0x78ac,
-	0xc08d, 0x78ae, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b, 0x0047,
-	0x2091, 0x8001, 0x007c, 0xd7fc, 0x00c0, 0x1b1a, 0x2069, 0x4a40,
-	0x0078, 0x1b1c, 0x2069, 0x4a80, 0x78ac, 0xc08c, 0x78ae, 0xd084,
-	0x00c0, 0x1b26, 0x0d7e, 0x1078, 0x1efa, 0x0d7f, 0x71c4, 0x71c6,
-	0x6916, 0x81ff, 0x00c0, 0x1b2e, 0x68a7, 0x0001, 0x007c, 0x75d8,
-	0x74dc, 0x75da, 0x74de, 0x0078, 0x1b38, 0x2029, 0x0000, 0x2520,
-	0x71c4, 0x73c8, 0x72cc, 0x71c6, 0x73ca, 0x72ce, 0x2079, 0x4a00,
-	0x7dde, 0x7cda, 0x7bd6, 0x7ad2, 0x1078, 0x1ddb, 0x0040, 0x1c3b,
-	0x20a9, 0x0005, 0x20a1, 0x4a14, 0x2091, 0x8000, 0x41a1, 0x2091,
-	0x8001, 0x2009, 0x0040, 0x1078, 0x1fcf, 0x0040, 0x1b5b, 0x1078,
-	0x1de4, 0x0078, 0x1c3b, 0x6004, 0xa08c, 0x00ff, 0xa18e, 0x0009,
-	0x00c0, 0x1b66, 0x007e, 0x1078, 0x234b, 0x007f, 0xa084, 0xff00,
-	0x8007, 0x8009, 0x0040, 0x1bda, 0x0c7e, 0x2c68, 0x1078, 0x1ddb,
-	0x0040, 0x1bac, 0x2c00, 0x689e, 0x8109, 0x00c0, 0x1b6d, 0x609f,
-	0x0000, 0x0c7f, 0x0c7e, 0x7ddc, 0x7cd8, 0x7bd4, 0x7ad0, 0xa290,
-	0x0040, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x7dde,
-	0x7cda, 0x7bd6, 0x7ad2, 0x2c68, 0x689c, 0xa065, 0x0040, 0x1bd9,
-	0x2009, 0x0040, 0x1078, 0x1fcf, 0x00c0, 0x1bc3, 0x6004, 0xa084,
-	0x00ff, 0xa086, 0x0002, 0x00c0, 0x1bac, 0x6004, 0xa084, 0x00ff,
-	0xa086, 0x000a, 0x00c0, 0x1ba8, 0x017e, 0x1078, 0x2347, 0x017f,
-	0x2d00, 0x6002, 0x0078, 0x1b7b, 0x0c7f, 0x0c7e, 0x609c, 0x1078,
-	0x1e5d, 0x0c7f, 0x609f, 0x0000, 0x1078, 0x1c3f, 0x2009, 0x0018,
-	0x6008, 0xc0cd, 0x600a, 0x6004, 0x6086, 0x1078, 0x1d92, 0x1078,
-	0x1de4, 0x0078, 0x1c3b, 0x0c7f, 0x0c7e, 0x609c, 0x1078, 0x1e5d,
-	0x0c7f, 0x609f, 0x0000, 0x1078, 0x1c3f, 0x2009, 0x0018, 0x6087,
-	0x0103, 0x601b, 0x0003, 0x1078, 0x1d92, 0x1078, 0x1de4, 0x0078,
-	0x1c3b, 0x0c7f, 0x7814, 0xd0e4, 0x00c0, 0x1bff, 0x6114, 0xd1fc,
-	0x0040, 0x1be8, 0x1078, 0x1d82, 0x0040, 0x1bff, 0x0078, 0x1bec,
-	0x1078, 0x1d72, 0x0040, 0x1bff, 0x2029, 0x0000, 0x2520, 0x2009,
-	0x0018, 0x73c8, 0x72cc, 0x6087, 0x0103, 0x601b, 0x0021, 0x1078,
-	0x1d92, 0x1078, 0x1de4, 0x2001, 0x4007, 0x0078, 0x159f, 0x74c4,
-	0x73c8, 0x72cc, 0x6014, 0x2091, 0x8000, 0x0e7e, 0x2009, 0x0012,
-	0xd0fc, 0x00c0, 0x1c0f, 0x2071, 0x4a40, 0x0078, 0x1c12, 0x2071,
-	0x4a80, 0xc1fd, 0x792a, 0x7067, 0x0005, 0x71d4, 0xa18c, 0xf77f,
-	0x71d6, 0x736a, 0x726e, 0x7472, 0x7076, 0x707b, 0x0000, 0x2c00,
-	0x707e, 0xa02e, 0x2530, 0x611c, 0xa184, 0x0060, 0x0040, 0x1c2a,
-	0x1078, 0x43c1, 0x0e7f, 0x6596, 0x65a6, 0x669a, 0x66aa, 0x60af,
-	0x0000, 0x60b3, 0x0000, 0x6714, 0x6023, 0x0000, 0x1078, 0x25de,
-	0x2091, 0x8001, 0x007c, 0x70c3, 0x4005, 0x0078, 0x15a0, 0x20a9,
-	0x0005, 0x2099, 0x4a14, 0x2091, 0x8000, 0x530a, 0x2091, 0x8001,
-	0x2100, 0xa210, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000,
-	0x007c, 0x71c4, 0x70c7, 0x0000, 0x791e, 0x0078, 0x159d, 0x71c4,
-	0x71c6, 0x2168, 0x0078, 0x1c5e, 0x2069, 0x1000, 0x690c, 0xa016,
-	0x2d04, 0xa210, 0x8d68, 0x8109, 0x00c0, 0x1c60, 0xa285, 0x0000,
-	0x00c0, 0x1c6e, 0x70c3, 0x4000, 0x0078, 0x1c70, 0x70c3, 0x4003,
-	0x70ca, 0x0078, 0x15a0, 0x7964, 0x71c6, 0x71c4, 0xa182, 0x0003,
-	0x00c8, 0x1595, 0x7966, 0x0078, 0x159d, 0x7964, 0x71c6, 0x0078,
-	0x159d, 0x7900, 0x71c6, 0x71c4, 0x7902, 0x0078, 0x159d, 0x7900,
-	0x71c6, 0x0078, 0x159d, 0x70c4, 0xd08c, 0x0040, 0x1c94, 0x7a10,
-	0xd2ec, 0x00c0, 0x1c94, 0xc08c, 0x2011, 0x0000, 0xa08c, 0x000d,
-	0x0040, 0x1ca8, 0x810c, 0x0048, 0x1ca4, 0x8210, 0x810c, 0x810c,
-	0x0048, 0x1ca4, 0x8210, 0x810c, 0x81ff, 0x00c0, 0x1596, 0x8210,
-	0x7a0e, 0xd28c, 0x0040, 0x1cd4, 0x7910, 0xc1cd, 0x7912, 0x2009,
-	0x0021, 0x2019, 0x0003, 0xd284, 0x0040, 0x1cce, 0x8108, 0x2019,
-	0x0041, 0x2011, 0x924e, 0x2312, 0x2019, 0x0042, 0x8210, 0x2312,
-	0x2019, 0x0043, 0x8210, 0x2312, 0x2019, 0x0046, 0x8210, 0x2312,
-	0x2019, 0x0047, 0x8210, 0x2312, 0x2019, 0x0006, 0x2011, 0x9253,
-	0x2112, 0x2011, 0x9273, 0x2312, 0x7904, 0x7806, 0x0078, 0x159c,
-	0x7804, 0x70c6, 0x0078, 0x159d, 0x2091, 0x8000, 0x2019, 0x0000,
-	0x2011, 0x0000, 0x2009, 0x0000, 0x2091, 0x8001, 0x0078, 0x159a,
-	0x77c4, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6830, 0xa084, 0xff00,
-	0x8007, 0x2010, 0x2091, 0x8001, 0x2708, 0x0078, 0x159b, 0x77c4,
-	0x1078, 0x1e02, 0x2091, 0x8000, 0x6a34, 0x2091, 0x8001, 0x2708,
-	0x0078, 0x159b, 0x77c4, 0x077e, 0xa7bc, 0xff00, 0x20a9, 0x0008,
-	0x72c8, 0x8217, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6c30, 0x6a32,
-	0x2091, 0x8001, 0x8738, 0x00f0, 0x1d0a, 0x077f, 0x2708, 0x8427,
-	0x2410, 0x0078, 0x159b, 0x77c4, 0x077e, 0xa7bc, 0xff00, 0x20a9,
-	0x0008, 0x72c8, 0x1078, 0x1e02, 0x2091, 0x8000, 0x6c34, 0x6a36,
-	0x2091, 0x8001, 0x8738, 0x00f0, 0x1d22, 0x077f, 0x2708, 0x2410,
-	0x0078, 0x159b, 0x2011, 0x4a3c, 0x220c, 0x70c4, 0x2012, 0x0078,
-	0x159c, 0x71c4, 0xd1fc, 0x00c0, 0x1d41, 0x2011, 0x4ec0, 0x0078,
-	0x1d43, 0x2011, 0x4f40, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003,
-	0x8003, 0xa268, 0x6a14, 0xd2b4, 0x0040, 0x1d52, 0x2011, 0x0001,
-	0x0078, 0x1d54, 0x2011, 0x0000, 0x6b0c, 0x0078, 0x159a, 0x017e,
-	0x7814, 0xd0f4, 0x0040, 0x1d64, 0x2001, 0x4007, 0x70db, 0x0000,
-	0xa18d, 0x0001, 0x0078, 0x1d70, 0xd0fc, 0x0040, 0x1d6f, 0x2001,
-	0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0078, 0x1d70, 0xa006,
-	0x017f, 0x007c, 0x017e, 0x7814, 0xd0f4, 0x0040, 0x1d7f, 0x2001,
-	0x4007, 0x70db, 0x0000, 0xa18d, 0x0001, 0x0078, 0x1d80, 0xa006,
-	0x017f, 0x007c, 0x017e, 0x7814, 0xd0fc, 0x0040, 0x1d8f, 0x2001,
-	0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0078, 0x1d90, 0xa006,
-	0x017f, 0x007c, 0x7112, 0x721a, 0x731e, 0x7810, 0xd0c4, 0x0040,
-	0x1d9b, 0x7422, 0x7526, 0xac80, 0x0001, 0x8108, 0x810c, 0x81a9,
-	0x8098, 0x20a1, 0x0030, 0x7003, 0x0000, 0x6084, 0x20a2, 0x53a6,
-	0x7007, 0x0001, 0x7974, 0xa184, 0xff00, 0x0040, 0x1db8, 0x810f,
-	0x810c, 0x810c, 0x8004, 0x8004, 0x8007, 0xa100, 0x0078, 0x1dbb,
-	0x8107, 0x8004, 0x8004, 0x797c, 0xa108, 0x7a78, 0xa006, 0xa211,
-	0x7d10, 0xd5c4, 0x0040, 0x1dc8, 0x7b84, 0xa319, 0x7c80, 0xa421,
-	0x7008, 0xd0fc, 0x0040, 0x1dc8, 0x7003, 0x0001, 0x7007, 0x0006,
-	0x711a, 0x721e, 0x7d10, 0xd5c4, 0x0040, 0x1dd8, 0x7322, 0x7426,
-	0xa084, 0x01e0, 0x007c, 0x7848, 0xa065, 0x0040, 0x1de3, 0x2c04,
-	0x784a, 0x2063, 0x0000, 0x007c, 0x0f7e, 0x2079, 0x4a00, 0x7848,
-	0x2062, 0x2c00, 0xa005, 0x00c0, 0x1def, 0x1078, 0x28ec, 0x784a,
-	0x0f7f, 0x007c, 0x2011, 0x9400, 0x7a4a, 0x7bc4, 0x8319, 0x0040,
-	0x1dff, 0xa280, 0x0032, 0x2012, 0x2010, 0x0078, 0x1df6, 0x2013,
-	0x0000, 0x007c, 0x017e, 0x027e, 0xd7fc, 0x00c0, 0x1e0b, 0x2011,
-	0x4fc0, 0x0078, 0x1e0d, 0x2011, 0x6fc0, 0xa784, 0x0f00, 0x800b,
-	0xa784, 0x001f, 0x0040, 0x1e18, 0x8003, 0x8003, 0x8003, 0x8003,
-	0xa105, 0xa268, 0x027f, 0x017f, 0x007c, 0x1078, 0x1e02, 0x2900,
-	0x682a, 0x2a00, 0x682e, 0x6808, 0xa084, 0xf9ef, 0xa80d, 0x690a,
-	0xd7fc, 0x00c0, 0x1e2f, 0x2009, 0x4a53, 0x0078, 0x1e31, 0x2009,
-	0x4a93, 0x210c, 0x6804, 0xa005, 0x0040, 0x1e41, 0xa116, 0x00c0,
-	0x1e41, 0x2060, 0x6000, 0x6806, 0x017e, 0x200b, 0x0000, 0x0078,
-	0x1e44, 0x2009, 0x0000, 0x017e, 0x6804, 0xa065, 0x0040, 0x1e59,
-	0x6000, 0x6806, 0x1078, 0x1e6f, 0x1078, 0x201b, 0x6810, 0x7908,
-	0x8109, 0x790a, 0x8001, 0x6812, 0x00c0, 0x1e44, 0x7910, 0xc1a5,
-	0x7912, 0x017f, 0x6902, 0x6906, 0x007c, 0xa065, 0x0040, 0x1e6e,
-	0x2008, 0x609c, 0xa005, 0x0040, 0x1e6b, 0x2062, 0x609f, 0x0000,
-	0xa065, 0x0078, 0x1e61, 0x7848, 0x794a, 0x2062, 0x007c, 0x6007,
-	0x0103, 0x608f, 0x0000, 0x20a9, 0x001c, 0xac80, 0x0005, 0x20a0,
-	0x2001, 0x0000, 0x40a4, 0x6828, 0x601a, 0x682c, 0x6022, 0x007c,
-	0x0e7e, 0xd7fc, 0x00c0, 0x1e8a, 0x2071, 0x4a40, 0x2031, 0x4ac0,
-	0x0078, 0x1e8e, 0x2071, 0x4a80, 0x2031, 0x4cc0, 0x7050, 0xa08c,
-	0x0200, 0x00c0, 0x1e98, 0xa608, 0x2d0a, 0x8000, 0x7052, 0xa006,
-	0x0e7f, 0x007c, 0x0f7e, 0xd7fc, 0x00c0, 0x1ea2, 0x2079, 0x4a40,
-	0x0078, 0x1ea4, 0x2079, 0x4a80, 0x1078, 0x1e02, 0x2091, 0x8000,
-	0x6804, 0x780a, 0xa065, 0x0040, 0x1ef8, 0x0078, 0x1eb6, 0x2c00,
-	0x780a, 0x2060, 0x6000, 0xa065, 0x0040, 0x1ef8, 0x6010, 0xa306,
-	0x00c0, 0x1eaf, 0x600c, 0xa206, 0x00c0, 0x1eaf, 0x2c28, 0x784c,
-	0xac06, 0x00c0, 0x1ec5, 0x0078, 0x1ef5, 0x6804, 0xac06, 0x00c0,
-	0x1ed3, 0x6000, 0x2060, 0x6806, 0xa005, 0x00c0, 0x1ed3, 0x6803,
-	0x0000, 0x0078, 0x1edd, 0x6400, 0x7808, 0x2060, 0x6402, 0xa486,
-	0x0000, 0x00c0, 0x1edd, 0x2c00, 0x6802, 0x2560, 0x0f7f, 0x1078,
-	0x1e6f, 0x0f7e, 0x601b, 0x0005, 0x6023, 0x0020, 0x0f7f, 0x1078,
-	0x201b, 0x0f7e, 0x7908, 0x8109, 0x790a, 0x6810, 0x8001, 0x6812,
-	0x00c0, 0x1ef5, 0x7810, 0xc0a5, 0x7812, 0x2001, 0xffff, 0xa005,
-	0x0f7f, 0x007c, 0x077e, 0x2700, 0x2039, 0x0000, 0xd0fc, 0x0040,
-	0x1f02, 0xc7fd, 0x2041, 0x0021, 0x2049, 0x0004, 0x2051, 0x0008,
-	0x2091, 0x8000, 0x1078, 0x1e1d, 0x8738, 0xa784, 0x001f, 0x00c0,
-	0x1f0a, 0xa7bc, 0xff00, 0x873f, 0x8738, 0x873f, 0xa784, 0x0f00,
-	0x00c0, 0x1f0a, 0x2091, 0x8001, 0x077f, 0x007c, 0x2061, 0x0000,
-	0x6018, 0xd084, 0x00c0, 0x1f3e, 0x7810, 0xd08c, 0x0040, 0x1f2f,
-	0xc08c, 0x7812, 0xc7fc, 0x2069, 0x4a40, 0x0078, 0x1f34, 0xc08d,
-	0x7812, 0x2069, 0x4a80, 0xc7fd, 0x2091, 0x8000, 0x681c, 0x681f,
-	0x0000, 0x2091, 0x8001, 0xa005, 0x00c0, 0x1f3f, 0x007c, 0xa08c,
-	0xfff0, 0x0040, 0x1f45, 0x1078, 0x28ec, 0x0079, 0x1f47, 0x1f57,
-	0x1f5a, 0x1f60, 0x1f64, 0x1f58, 0x1f68, 0x1f58, 0x1f58, 0x1f58,
-	0x1f6e, 0x1f9f, 0x1fa3, 0x1fa9, 0x1f58, 0x1f58, 0x1f58, 0x007c,
-	0x1078, 0x28ec, 0x1078, 0x1efa, 0x2001, 0x8001, 0x0078, 0x1fbe,
-	0x2001, 0x8003, 0x0078, 0x1fbe, 0x2001, 0x8004, 0x0078, 0x1fbe,
-	0x1078, 0x1efa, 0x2001, 0x8006, 0x0078, 0x1fbe, 0x2091, 0x8000,
-	0x077e, 0xd7fc, 0x00c0, 0x1f7a, 0x2069, 0x4a40, 0x2039, 0x0009,
-	0x0078, 0x1f7e, 0x2069, 0x4a80, 0x2039, 0x0009, 0x6800, 0xa086,
-	0x0000, 0x0040, 0x1f88, 0x007f, 0x6f1e, 0x2091, 0x8001, 0x007c,
-	0x6874, 0x077f, 0xa0bc, 0xff00, 0x2041, 0x0021, 0x2049, 0x0004,
-	0x2051, 0x0010, 0x1078, 0x1e1d, 0x8738, 0xa784, 0x001f, 0x00c0,
-	0x1f92, 0x2091, 0x8001, 0x2001, 0x800a, 0x0078, 0x1fbe, 0x2001,
-	0x800c, 0x0078, 0x1fbe, 0x1078, 0x1efa, 0x2001, 0x800d, 0x0078,
-	0x1fbe, 0x7814, 0xd0e4, 0x00c0, 0x1fbc, 0xd0ec, 0x0040, 0x1fb6,
-	0xd7fc, 0x0040, 0x1fb6, 0x78ec, 0x0078, 0x1fb7, 0x78e4, 0x70c6,
-	0x2001, 0x800e, 0x0078, 0x1fbe, 0x0078, 0x1f58, 0x70c2, 0xd7fc,
-	0x00c0, 0x1fc6, 0x70db, 0x0000, 0x0078, 0x1fc8, 0x70db, 0x0001,
-	0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x4080, 0x007c, 0xac80,
-	0x0001, 0x81ff, 0x0040, 0x1ffa, 0x2099, 0x0030, 0x20a0, 0x700c,
-	0xa084, 0x03ff, 0x0040, 0x1fdc, 0x7018, 0x007e, 0x701c, 0x007e,
-	0x7020, 0x007e, 0x7024, 0x007e, 0x7112, 0x81ac, 0x721a, 0x731e,
-	0x7422, 0x7526, 0x7003, 0x0001, 0x7007, 0x0001, 0x7008, 0x800b,
-	0x00c8, 0x1fee, 0x7007, 0x0002, 0xa08c, 0x01e0, 0x00c0, 0x1ffa,
-	0x53a5, 0xa006, 0x7003, 0x0000, 0x7007, 0x0004, 0x007f, 0x7026,
-	0x007f, 0x7022, 0x007f, 0x701e, 0x007f, 0x701a, 0x007c, 0x2011,
-	0x0020, 0x2009, 0x0010, 0x6b0a, 0x6c0e, 0x6803, 0xfd00, 0x6807,
-	0x0018, 0x6a1a, 0x2d00, 0xa0e8, 0x0008, 0xa290, 0x0004, 0x8109,
-	0x00c0, 0x200b, 0x007c, 0x6004, 0x6086, 0x2c08, 0x2063, 0x0000,
-	0x7868, 0xa005, 0x796a, 0x0040, 0x2028, 0x2c02, 0x0078, 0x2029,
-	0x796e, 0x007c, 0x0c7e, 0x2061, 0x4a00, 0x6887, 0x0103, 0x2d08,
-	0x206b, 0x0000, 0x6068, 0xa005, 0x616a, 0x0040, 0x203a, 0x2d02,
-	0x0078, 0x203b, 0x616e, 0x0c7f, 0x007c, 0x2091, 0x8000, 0x2c04,
-	0x786e, 0xa005, 0x00c0, 0x2045, 0x786a, 0x2091, 0x8001, 0x609c,
-	0xa005, 0x0040, 0x205e, 0x0c7e, 0x2060, 0x2008, 0x609c, 0xa005,
-	0x0040, 0x205a, 0x2062, 0x609f, 0x0000, 0xa065, 0x609c, 0xa005,
-	0x00c0, 0x2052, 0x7848, 0x794a, 0x2062, 0x0c7f, 0x7848, 0x2062,
-	0x609f, 0x0000, 0xac85, 0x0000, 0x00c0, 0x2068, 0x1078, 0x28ec,
-	0x784a, 0x007c, 0x20a9, 0x0010, 0xa006, 0x8004, 0x8086, 0x818e,
-	0x00c8, 0x2073, 0xa200, 0x00f0, 0x206e, 0x8086, 0x818e, 0x007c,
-	0x157e, 0x20a9, 0x0010, 0xa005, 0x0040, 0x2099, 0xa11a, 0x00c8,
-	0x2099, 0x8213, 0x818d, 0x0048, 0x208c, 0xa11a, 0x00c8, 0x208d,
-	0x00f0, 0x2081, 0x0078, 0x2091, 0xa11a, 0x2308, 0x8210, 0x00f0,
-	0x2081, 0x007e, 0x3200, 0xa084, 0xf7ff, 0x2080, 0x007f, 0x157f,
-	0x007c, 0x007e, 0x3200, 0xa085, 0x0800, 0x0078, 0x2095, 0x7d74,
-	0x70d0, 0xa506, 0x0040, 0x2185, 0x7810, 0x2050, 0x7800, 0xd08c,
-	0x0040, 0x20c1, 0xdaec, 0x0040, 0x20c1, 0x0e7e, 0x2091, 0x8000,
-	0x2071, 0x0020, 0x7004, 0xa005, 0x00c0, 0x20be, 0x7008, 0x0e7f,
-	0xa086, 0x0008, 0x0040, 0x20c1, 0x0078, 0x2185, 0x0e7f, 0x0078,
-	0x2185, 0x1078, 0x1ddb, 0x0040, 0x2185, 0xa046, 0x7970, 0x2500,
-	0x8000, 0xa112, 0x2009, 0x0040, 0x00c8, 0x20d0, 0x0078, 0x20d7,
-	0x72d0, 0xa206, 0x0040, 0x20d7, 0x8840, 0x2009, 0x0080, 0x0c7e,
-	0x7112, 0x7007, 0x0001, 0x2099, 0x0030, 0x20a9, 0x0020, 0xac80,
-	0x0001, 0x20a0, 0x2061, 0x0000, 0x88ff, 0x0040, 0x20e9, 0x1078,
-	0x1ddb, 0x7008, 0xd0fc, 0x0040, 0x20e9, 0x7007, 0x0002, 0x2091,
-	0x8001, 0xa08c, 0x01e0, 0x00c0, 0x2120, 0x53a5, 0x8cff, 0x00c0,
-	0x20fe, 0x88ff, 0x0040, 0x216f, 0x0078, 0x2108, 0x2c00, 0x788e,
-	0x20a9, 0x0020, 0xac80, 0x0001, 0x20a0, 0x53a5, 0x0078, 0x216f,
-	0xa046, 0x7218, 0x731c, 0xdac4, 0x0040, 0x2110, 0x7420, 0x7524,
-	0xa292, 0x0040, 0xa39b, 0x0000, 0xa4a3, 0x0000, 0xa5ab, 0x0000,
-	0x721a, 0x731e, 0xdac4, 0x0040, 0x2120, 0x7422, 0x7526, 0xa006,
-	0x7007, 0x0004, 0x0040, 0x216f, 0x8cff, 0x0040, 0x2129, 0x1078,
-	0x1de4, 0x0c7f, 0x1078, 0x1de4, 0xa046, 0x7888, 0x8000, 0x788a,
-	0xa086, 0x0002, 0x0040, 0x214f, 0x7a7c, 0x7b78, 0xdac4, 0x0040,
-	0x213b, 0x7c84, 0x7d80, 0x7974, 0x8107, 0x8004, 0x8004, 0xa210,
-	0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x721a, 0x731e,
-	0xdac4, 0x0040, 0x2185, 0x7422, 0x7526, 0x0078, 0x2185, 0x6014,
-	0xd0fc, 0x00c0, 0x2157, 0x2069, 0x4a40, 0x0078, 0x2159, 0x2069,
-	0x4a80, 0x2091, 0x8000, 0x681f, 0x0002, 0x88ff, 0x0040, 0x2165,
-	0xa046, 0x788c, 0x2060, 0x0078, 0x214f, 0x788b, 0x0000, 0x78ac,
-	0xa085, 0x0003, 0x78ae, 0x2091, 0x8001, 0x0078, 0x2185, 0x0c7f,
-	0x788b, 0x0000, 0x1078, 0x2319, 0x6004, 0xa084, 0x000f, 0x1078,
-	0x2186, 0x88ff, 0x0040, 0x2183, 0x788c, 0x2060, 0x6004, 0xa084,
-	0x000f, 0x1078, 0x2186, 0x0078, 0x209f, 0x007c, 0x0079, 0x2188,
-	0x2198, 0x21b6, 0x21d4, 0x2198, 0x21e5, 0x21a9, 0x2198, 0x2198,
-	0x2198, 0x21b4, 0x21d2, 0x2198, 0x2198, 0x2198, 0x2198, 0x2198,
-	0x2039, 0x0400, 0x78bc, 0xa705, 0x78be, 0x6008, 0xa705, 0x600a,
-	0x1078, 0x2228, 0x609c, 0x78ba, 0x609f, 0x0000, 0x1078, 0x2303,
-	0x007c, 0x78bc, 0xd0c4, 0x0040, 0x21af, 0x0078, 0x2198, 0x601c,
-	0xc0bd, 0x601e, 0x0078, 0x21bc, 0x1078, 0x234b, 0x78bc, 0xd0c4,
-	0x0040, 0x21bc, 0x0078, 0x2198, 0x78bf, 0x0000, 0x6004, 0x8007,
-	0xa084, 0x00ff, 0x78b2, 0x8001, 0x0040, 0x21cf, 0x1078, 0x2228,
-	0x0040, 0x21cf, 0x78bc, 0xc0c5, 0x78be, 0x0078, 0x21d1, 0x0078,
-	0x2247, 0x007c, 0x1078, 0x2347, 0x78bc, 0xa08c, 0x0e00, 0x00c0,
-	0x21dc, 0xd0c4, 0x00c0, 0x21de, 0x0078, 0x2198, 0x1078, 0x2228,
-	0x00c0, 0x21e4, 0x0078, 0x2247, 0x007c, 0x78bc, 0xd0c4, 0x0040,
-	0x21eb, 0x0078, 0x2198, 0x78bf, 0x0000, 0x6714, 0x2011, 0x0001,
-	0x22a8, 0x6018, 0xa084, 0x00ff, 0xa005, 0x0040, 0x220b, 0xa7bc,
-	0xff00, 0x20a9, 0x0020, 0xa08e, 0x0001, 0x0040, 0x220b, 0xa7bc,
-	0x8000, 0x2011, 0x0002, 0x20a9, 0x0100, 0xa08e, 0x0002, 0x0040,
-	0x220b, 0x0078, 0x2225, 0x1078, 0x1e02, 0x2d00, 0x2091, 0x8000,
-	0x682b, 0x0000, 0x682f, 0x0000, 0x6808, 0xa084, 0xffde, 0x680a,
-	0xade8, 0x0010, 0x2091, 0x8001, 0x00f0, 0x220e, 0x8211, 0x0040,
-	0x2225, 0x20a9, 0x0100, 0x0078, 0x220e, 0x1078, 0x1de4, 0x007c,
-	0x609f, 0x0000, 0x78b4, 0xa06d, 0x2c00, 0x78b6, 0x00c0, 0x2233,
-	0x78ba, 0x0078, 0x223b, 0x689e, 0x2d00, 0x6002, 0x78b8, 0xad06,
-	0x00c0, 0x223b, 0x6002, 0x78b0, 0x8001, 0x78b2, 0x00c0, 0x2246,
-	0x78bc, 0xc0c4, 0x78be, 0x78b8, 0x2060, 0xa006, 0x007c, 0x0e7e,
-	0xa02e, 0x2530, 0x7dba, 0x7db6, 0x65ae, 0x65b2, 0x601c, 0x60a2,
-	0x2048, 0xa984, 0xe1ff, 0x601e, 0xa984, 0x0060, 0x0040, 0x225a,
-	0x1078, 0x43c1, 0x6596, 0x65a6, 0x669a, 0x66aa, 0x6714, 0x2071,
-	0x4a80, 0xd7fc, 0x00c0, 0x2266, 0x2071, 0x4a40, 0xa784, 0x0f00,
-	0x800b, 0xa784, 0x001f, 0x0040, 0x2271, 0x8003, 0x8003, 0x8003,
-	0x8003, 0xa105, 0x71c4, 0xa168, 0x2700, 0x8007, 0xa084, 0x000f,
-	0x8003, 0x8003, 0x8003, 0x71c8, 0xa100, 0x60c2, 0x2091, 0x8000,
-	0x7810, 0xd0f4, 0x00c0, 0x228b, 0x6e08, 0xd684, 0x0040, 0x22a1,
-	0xd9fc, 0x00c0, 0x22a1, 0x2091, 0x8001, 0x1078, 0x1e6f, 0x2091,
-	0x8000, 0x1078, 0x201b, 0x2091, 0x8001, 0x7814, 0xd0e4, 0x00c0,
-	0x2301, 0x7810, 0xd0f4, 0x0040, 0x2301, 0x601b, 0x0021, 0x0078,
-	0x2301, 0x6024, 0xa096, 0x0001, 0x00c0, 0x22a8, 0x8000, 0x6026,
-	0x6a10, 0x6814, 0xa202, 0x0048, 0x22bb, 0x0040, 0x22bb, 0x2091,
-	0x8001, 0x2039, 0x0200, 0x609c, 0x78ba, 0x609f, 0x0000, 0x1078,
-	0x2303, 0x0078, 0x2301, 0x2c08, 0xd9fc, 0x0040, 0x22de, 0x6800,
-	0xa065, 0x0040, 0x22de, 0x6a04, 0x7000, 0xa084, 0x0002, 0x0040,
-	0x22d9, 0x704c, 0xa206, 0x00c0, 0x22d9, 0x6b04, 0x2160, 0x2304,
-	0x6002, 0xa005, 0x00c0, 0x22d5, 0x6902, 0x2260, 0x6102, 0x0078,
-	0x22ea, 0x2160, 0x6202, 0x6906, 0x0078, 0x22ea, 0x6800, 0x6902,
-	0xa065, 0x0040, 0x22e6, 0x6102, 0x0078, 0x22e7, 0x6906, 0x2160,
-	0x6003, 0x0000, 0x2160, 0xd9fc, 0x0040, 0x22f1, 0xa6b4, 0xfffc,
-	0x6e0a, 0x6810, 0x7d08, 0x8528, 0x7d0a, 0x8000, 0x6812, 0x2091,
-	0x8001, 0xd6b4, 0x0040, 0x2301, 0xa6b6, 0x0040, 0x6e0a, 0x1078,
-	0x1e80, 0x0e7f, 0x007c, 0x6008, 0xa705, 0x600a, 0x2091, 0x8000,
-	0x1078, 0x201b, 0x2091, 0x8001, 0x78b8, 0xa065, 0x0040, 0x2316,
-	0x609c, 0x78ba, 0x609f, 0x0000, 0x0078, 0x2303, 0x78b6, 0x78ba,
-	0x007c, 0x7970, 0x7874, 0x2818, 0xd384, 0x0040, 0x2323, 0x8000,
-	0xa112, 0x0048, 0x2328, 0x8000, 0xa112, 0x00c8, 0x2338, 0xc384,
-	0x7a7c, 0x721a, 0x7a78, 0x721e, 0xdac4, 0x0040, 0x2333, 0x7a84,
-	0x7222, 0x7a80, 0x7226, 0xa006, 0xd384, 0x0040, 0x2338, 0x8000,
-	0x7876, 0x70d2, 0x781c, 0xa005, 0x0040, 0x2346, 0x8001, 0x781e,
-	0x00c0, 0x2346, 0x0068, 0x2346, 0x2091, 0x4080, 0x007c, 0x2039,
-	0x235f, 0x0078, 0x234d, 0x2039, 0x2365, 0x2704, 0xa005, 0x0040,
-	0x235e, 0xac00, 0x2068, 0x6908, 0x6810, 0x6912, 0x680a, 0x690c,
-	0x6814, 0x6916, 0x680e, 0x8738, 0x0078, 0x234d, 0x007c, 0x0003,
-	0x0009, 0x000f, 0x0015, 0x001b, 0x0000, 0x0015, 0x001b, 0x0000,
-	0x2041, 0x0000, 0x780c, 0x0079, 0x236d, 0x2535, 0x2508, 0x2371,
-	0x23e5, 0x2039, 0x9274, 0x2734, 0x7d10, 0x0078, 0x238c, 0x6084,
-	0xa086, 0x0103, 0x00c0, 0x23ce, 0x6114, 0x6018, 0xa105, 0x00c0,
-	0x23ce, 0x8603, 0xa080, 0x9255, 0x620c, 0x2202, 0x8000, 0x6210,
-	0x2202, 0x1078, 0x203d, 0x8630, 0xa68e, 0x000f, 0x0040, 0x2454,
-	0x786c, 0xa065, 0x00c0, 0x2377, 0x7808, 0xa602, 0x00c8, 0x239d,
-	0xd5ac, 0x00c0, 0x239d, 0x263a, 0x007c, 0xa682, 0x0003, 0x00c8,
-	0x2454, 0x2091, 0x8000, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0,
-	0x23c9, 0x2011, 0x9255, 0x2204, 0x70c6, 0x8210, 0x2204, 0x70ca,
-	0xd684, 0x00c0, 0x23b9, 0x8210, 0x2204, 0x70da, 0x8210, 0x2204,
-	0x70de, 0xa685, 0x8020, 0x70c2, 0x681b, 0x0001, 0x2091, 0x4080,
-	0x7810, 0xa084, 0xffcf, 0x7812, 0x2091, 0x8001, 0x203b, 0x0000,
-	0x007c, 0x7810, 0xc0ad, 0x7812, 0x0078, 0x2454, 0x263a, 0x1078,
-	0x253f, 0x00c0, 0x254e, 0x786c, 0xa065, 0x00c0, 0x2377, 0x2091,
-	0x8000, 0x7810, 0xa084, 0xffcf, 0x86ff, 0x0040, 0x23e0, 0xc0ad,
-	0x7812, 0x2091, 0x8001, 0x0078, 0x254e, 0x2039, 0x9274, 0x2734,
-	0x7d10, 0x0078, 0x23fc, 0x6084, 0xa086, 0x0103, 0x00c0, 0x243d,
-	0x6114, 0x6018, 0xa105, 0x00c0, 0x243d, 0xa680, 0x9255, 0x620c,
-	0x2202, 0x1078, 0x203d, 0x8630, 0xa68e, 0x001e, 0x0040, 0x2454,
-	0x786c, 0xa065, 0x00c0, 0x23eb, 0x7808, 0xa602, 0x00c8, 0x240d,
-	0xd5ac, 0x00c0, 0x240d, 0x263a, 0x007c, 0xa682, 0x0006, 0x00c8,
-	0x2454, 0x2091, 0x8000, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0,
-	0x2438, 0x2011, 0x9255, 0x2009, 0x924e, 0x26a8, 0x211c, 0x2204,
-	0x201a, 0x8108, 0x8210, 0x00f0, 0x241e, 0xa685, 0x8030, 0x70c2,
+	0xa1a2, 0x4d00, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424,
+	0xa192, 0x9700, 0x2009, 0x0000, 0x2001, 0x0032, 0x1078, 0x2061,
+	0x2218, 0x2079, 0x4d00, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9,
+	0x0040, 0x42a4, 0x8109, 0x00c0, 0x10bf, 0x2009, 0xff00, 0x3400,
+	0xa102, 0x0048, 0x10cf, 0x0040, 0x10cf, 0x20a8, 0x42a4, 0x2001,
+	0x04fc, 0x2004, 0xa086, 0x1080, 0x00c0, 0x10e5, 0x2071, 0x0100,
+	0x0d7e, 0x2069, 0x4d40, 0x1078, 0x4c38, 0x0d7f, 0x7810, 0xc0ed,
+	0x7812, 0x781b, 0x0064, 0x0078, 0x110a, 0x2001, 0x04fc, 0x2004,
+	0xa086, 0x1280, 0x00c0, 0x1105, 0x7814, 0xc0ed, 0xc0d5, 0x7816,
+	0x781b, 0x0064, 0x2071, 0x0200, 0x0d7e, 0x2069, 0x4d40, 0x1078,
+	0x4c38, 0x2069, 0x4d80, 0x2071, 0x0100, 0x1078, 0x4c38, 0x7814,
+	0xc0d4, 0x7816, 0x0d7f, 0x0078, 0x110a, 0x7814, 0xc0e5, 0x7816,
+	0x781b, 0x003c, 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800,
+	0xc08d, 0x7802, 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002,
+	0x7827, 0x0002, 0x2009, 0x0002, 0x2069, 0x4d40, 0x681b, 0x0003,
+	0x6823, 0x0007, 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028,
+	0x6837, 0x0000, 0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000,
+	0x8109, 0x0040, 0x115e, 0x68d3, 0x000a, 0x68c3, 0x4dc0, 0x2079,
+	0x4d00, 0x7814, 0xd0e4, 0x00c0, 0x1144, 0xd0ec, 0x00c0, 0x1148,
+	0x68d7, 0x7329, 0x0078, 0x114a, 0x68d7, 0x730d, 0x0078, 0x114a,
+	0x68d7, 0x732d, 0x68c7, 0x52c0, 0x68cb, 0x51c0, 0x68cf, 0x92c0,
+	0x68ab, 0x9544, 0x68af, 0x9549, 0x68b3, 0x9544, 0x68b7, 0x9544,
+	0x68a7, 0x0001, 0x2069, 0x4d80, 0x0078, 0x111e, 0x68d3, 0x000a,
+	0x68c3, 0x4fc0, 0x7814, 0xd0e4, 0x00c0, 0x116a, 0x68d7, 0x7439,
+	0x0078, 0x116c, 0x68d7, 0x7419, 0x68c7, 0x72c0, 0x68cb, 0x5240,
+	0x68cf, 0x93d0, 0x68ab, 0x9549, 0x68af, 0x954e, 0x68b3, 0x9549,
+	0x68b7, 0x9549, 0x68a7, 0x0001, 0x7810, 0xd0ec, 0x00c0, 0x11c2,
+	0x7814, 0xd0e4, 0x00c0, 0x11b4, 0x0e7e, 0x2069, 0x51c0, 0x2071,
+	0x0200, 0x70ec, 0xd0e4, 0x00c0, 0x1195, 0x2019, 0x0c0c, 0x2021,
+	0x000c, 0x1078, 0x1ff0, 0x0078, 0x119b, 0x2019, 0x0c0a, 0x2021,
+	0x000a, 0x1078, 0x1ff0, 0x2069, 0x5240, 0x2071, 0x0100, 0x70ec,
+	0xd0e4, 0x00c0, 0x11ab, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078,
+	0x1ff0, 0x0078, 0x11b1, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078,
+	0x1ff0, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0c, 0x2021, 0x000c,
+	0x2069, 0x51c0, 0x1078, 0x1ff0, 0x2069, 0x5240, 0x1078, 0x1ff0,
+	0x0078, 0x11db, 0x2069, 0x51c0, 0x0e7e, 0x2071, 0x0100, 0x70ec,
+	0xd0e4, 0x00c0, 0x11d4, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078,
+	0x1ff0, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0a, 0x2021, 0x000a,
+	0x1078, 0x1ff0, 0x0e7f, 0x2011, 0x0002, 0x2069, 0x52c0, 0x2009,
+	0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, 0x7bc8,
+	0xa386, 0xfeff, 0x00c0, 0x11f2, 0x6817, 0x0100, 0x681f, 0x0064,
+	0x0078, 0x11f6, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010,
+	0x00f0, 0x11e3, 0x8109, 0x00c0, 0x11e1, 0x8211, 0x0040, 0x1204,
+	0x2069, 0x72c0, 0x0078, 0x11df, 0x1078, 0x261d, 0x1078, 0x4603,
+	0x1078, 0x1dbb, 0x1078, 0x4be1, 0x2091, 0x2100, 0x2079, 0x4d00,
+	0x7810, 0xd0ec, 0x0040, 0x1218, 0x2071, 0x0020, 0x0078, 0x121a,
+	0x2071, 0x0050, 0x2091, 0x2200, 0x2079, 0x4d00, 0x2071, 0x0020,
+	0x2091, 0x2300, 0x2079, 0x4d00, 0x7810, 0xd0ec, 0x0040, 0x122c,
+	0x2079, 0x0100, 0x0078, 0x122e, 0x2079, 0x0200, 0x2071, 0x4d40,
+	0x2091, 0x2400, 0x2079, 0x0100, 0x2071, 0x4d80, 0x2091, 0x2000,
+	0x2079, 0x4d00, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090,
+	0x2071, 0x0010, 0x70c3, 0x0000, 0x0090, 0x124d, 0x70c0, 0xa086,
+	0x0002, 0x00c0, 0x124d, 0x1078, 0x15ba, 0x2039, 0x0000, 0x7810,
+	0xd0ec, 0x00c0, 0x12cf, 0x1078, 0x148e, 0x78ac, 0xa005, 0x00c0,
+	0x126b, 0x0068, 0x1261, 0x786c, 0xa065, 0x0040, 0x1261, 0x1078,
+	0x2356, 0x1078, 0x2088, 0x0068, 0x1278, 0x786c, 0xa065, 0x0040,
+	0x126b, 0x1078, 0x2356, 0x0068, 0x1278, 0x2009, 0x4d47, 0x2011,
+	0x4d87, 0x2104, 0x220c, 0xa105, 0x0040, 0x1278, 0x1078, 0x1ef1,
+	0x2071, 0x4d40, 0x70a4, 0xa005, 0x0040, 0x129d, 0x7450, 0xa485,
+	0x0000, 0x0040, 0x129d, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4,
+	0xa28c, 0x303d, 0x2190, 0x1078, 0x2b0b, 0x2091, 0x8000, 0x2091,
+	0x303d, 0x0068, 0x129d, 0x2079, 0x4d00, 0x786c, 0xa065, 0x0040,
+	0x129d, 0x2071, 0x0010, 0x1078, 0x2356, 0x00e0, 0x12a5, 0x2079,
+	0x4d00, 0x2071, 0x0010, 0x1078, 0x49ba, 0x2071, 0x4d80, 0x70a4,
+	0xa005, 0x0040, 0x12bd, 0x7050, 0xa025, 0x0040, 0x12bd, 0x2079,
+	0x0100, 0x2091, 0x8000, 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078,
+	0x2b0b, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079, 0x4d00, 0x2071,
+	0x0010, 0x0068, 0x12c9, 0x786c, 0xa065, 0x0040, 0x12c9, 0x1078,
+	0x2356, 0x00e0, 0x1253, 0x1078, 0x49ba, 0x0078, 0x1253, 0x1078,
+	0x148e, 0x78ac, 0xa005, 0x00c0, 0x12e7, 0x0068, 0x12dd, 0x786c,
+	0xa065, 0x0040, 0x12dd, 0x1078, 0x2356, 0x1078, 0x2088, 0x0068,
+	0x12f1, 0x786c, 0xa065, 0x0040, 0x12e7, 0x1078, 0x2356, 0x0068,
+	0x12f1, 0x2009, 0x4d47, 0x2104, 0xa005, 0x0040, 0x12f1, 0x1078,
+	0x1ef1, 0x2071, 0x4d40, 0x70a4, 0xa005, 0x0040, 0x130c, 0x7450,
+	0xa485, 0x0000, 0x0040, 0x130c, 0x2079, 0x0100, 0x2091, 0x8000,
+	0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, 0x2b0b, 0x2091, 0x8000,
+	0x2091, 0x303d, 0x2079, 0x4d00, 0x2071, 0x0010, 0x0068, 0x1316,
+	0x786c, 0xa065, 0x0040, 0x1316, 0x1078, 0x2356, 0x00e0, 0x12cf,
+	0x1078, 0x49ba, 0x0078, 0x12cf, 0x133c, 0x133c, 0x133e, 0x133e,
+	0x134b, 0x134b, 0x134b, 0x134b, 0x1356, 0x1356, 0x1363, 0x1363,
+	0x134b, 0x134b, 0x134b, 0x134b, 0x133c, 0x133c, 0x133e, 0x133e,
+	0x134b, 0x134b, 0x134b, 0x134b, 0x1356, 0x1356, 0x1363, 0x1363,
+	0x134b, 0x134b, 0x134b, 0x134b, 0x0078, 0x133c, 0x007e, 0x107e,
+	0x127e, 0x2091, 0x2400, 0x1078, 0x292b, 0x127f, 0x107f, 0x007f,
+	0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13c8,
+	0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c, 0x007e, 0x107e,
+	0x127e, 0x2091, 0x2300, 0x1078, 0x292b, 0x127f, 0x107f, 0x007f,
+	0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x2091, 0x2300,
+	0x1078, 0x292b, 0x2091, 0x2400, 0x1078, 0x292b, 0x127f, 0x107f,
+	0x007f, 0x2091, 0x8001, 0x007c, 0x1394, 0x1394, 0x1396, 0x1396,
+	0x13a3, 0x13a3, 0x13a3, 0x13a3, 0x13ae, 0x13ae, 0x1396, 0x1396,
+	0x13a3, 0x13a3, 0x13a3, 0x13a3, 0x13af, 0x13af, 0x13af, 0x13af,
+	0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af,
+	0x13af, 0x13af, 0x13af, 0x13af, 0x0078, 0x1394, 0x007e, 0x107e,
+	0x127e, 0x2091, 0x2300, 0x1078, 0x292b, 0x127f, 0x107f, 0x007f,
+	0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13d5,
+	0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c, 0x007c, 0x107e,
+	0x127e, 0x0d7e, 0x0e7e, 0x0f7e, 0x007e, 0x2071, 0x0100, 0x2069,
+	0x4d40, 0x2079, 0x4d00, 0x70ec, 0xa084, 0x1c00, 0x78e2, 0x1078,
+	0x4c38, 0x007f, 0x0f7f, 0x0e7f, 0x0d7f, 0x127f, 0x107f, 0x007c,
+	0x3c00, 0xa084, 0x0007, 0x0079, 0x13cd, 0x13de, 0x13de, 0x13e0,
+	0x13e0, 0x13e5, 0x13e5, 0x13ea, 0x13ea, 0x3c00, 0xa084, 0x0003,
+	0x0079, 0x13da, 0x13de, 0x13de, 0x13f3, 0x13f3, 0x1078, 0x290c,
+	0x2091, 0x2200, 0x1078, 0x46dd, 0x007c, 0x2091, 0x2100, 0x1078,
+	0x46dd, 0x007c, 0x2091, 0x2100, 0x1078, 0x46dd, 0x2091, 0x2200,
+	0x1078, 0x46dd, 0x007c, 0x2091, 0x2100, 0x1078, 0x46dd, 0x007c,
+	0x1418, 0x1418, 0x141a, 0x141a, 0x1427, 0x1427, 0x1427, 0x1427,
+	0x1432, 0x1432, 0x143f, 0x143f, 0x1427, 0x1427, 0x1427, 0x1427,
+	0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450,
+	0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450, 0x1450,
+	0x0078, 0x1418, 0x007e, 0x107e, 0x127e, 0x2091, 0x2400, 0x1078,
+	0x292b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c, 0x007e,
+	0x107e, 0x127e, 0x1078, 0x13c8, 0x127f, 0x107f, 0x007f, 0x2091,
+	0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x2091, 0x2300, 0x1078,
+	0x292b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c, 0x007e,
+	0x107e, 0x127e, 0x2091, 0x2300, 0x1078, 0x292b, 0x2091, 0x2400,
+	0x1078, 0x292b, 0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c,
+	0x007e, 0x107e, 0x127e, 0x0d7e, 0x0e7e, 0x0f7e, 0x2079, 0x4d00,
+	0x2071, 0x0200, 0x2069, 0x4d40, 0x3d00, 0xd08c, 0x0040, 0x1466,
+	0x70ec, 0xa084, 0x1c00, 0x78e2, 0x1078, 0x4c38, 0x3d00, 0xd084,
+	0x0040, 0x1474, 0x2069, 0x4d80, 0x2071, 0x0100, 0x70ec, 0xa084,
+	0x1c00, 0x78e6, 0x1078, 0x4c38, 0x0f7f, 0x0e7f, 0x0d7f, 0x127f,
+	0x107f, 0x007f, 0x007c, 0x7008, 0x800b, 0x00c8, 0x1489, 0x7007,
+	0x0002, 0xa08c, 0x01e0, 0x00c0, 0x148a, 0xd09c, 0x0040, 0x1489,
+	0x087a, 0x097a, 0x70c3, 0x4002, 0x0078, 0x15bd, 0x0068, 0x1513,
+	0x2061, 0x0000, 0x6018, 0xd084, 0x00c0, 0x1513, 0x7828, 0xa005,
+	0x00c0, 0x149e, 0x0010, 0x1514, 0x0078, 0x1513, 0x7910, 0xd1f4,
+	0x0040, 0x14a6, 0x2001, 0x4007, 0x0078, 0x15bc, 0x7914, 0xd1ec,
+	0x0040, 0x14c1, 0xd0fc, 0x0040, 0x14b7, 0x007e, 0x1078, 0x1d4b,
+	0x007f, 0x0040, 0x14c1, 0x2001, 0x4007, 0x0078, 0x15bc, 0x007e,
+	0x1078, 0x1d3b, 0x007f, 0x0040, 0x14c1, 0x2001, 0x4007, 0x0078,
+	0x15bc, 0x7910, 0xd0fc, 0x00c0, 0x14cb, 0x2061, 0x4d40, 0xc19c,
+	0xc7fc, 0x0078, 0x14cf, 0x2061, 0x4d80, 0xc19d, 0xc7fd, 0x6064,
+	0xa005, 0x00c0, 0x1513, 0x7912, 0x6083, 0x0000, 0x7828, 0xc0fc,
+	0xa086, 0x0018, 0x00c0, 0x14e0, 0x0c7e, 0x1078, 0x1b44, 0x0c7f,
+	0x782b, 0x0000, 0x607c, 0xa065, 0x0040, 0x14f9, 0x0c7e, 0x609c,
+	0x1078, 0x1e30, 0x0c7f, 0x609f, 0x0000, 0x1078, 0x1c6d, 0x2009,
+	0x0018, 0x6087, 0x0103, 0x1078, 0x1d5b, 0x00c0, 0x150d, 0x1078,
+	0x1dad, 0x7810, 0xd09c, 0x00c0, 0x1501, 0x2061, 0x4d40, 0x0078,
+	0x1505, 0x2061, 0x4d80, 0xc09c, 0x7812, 0x607f, 0x0000, 0x60d4,
+	0xd0dc, 0x0040, 0x1511, 0xc0dc, 0x60d6, 0x2001, 0x4005, 0x0078,
+	0x15bc, 0x0078, 0x15ba, 0x007c, 0x7810, 0xd0f4, 0x0040, 0x151c,
+	0x2001, 0x4007, 0x0078, 0x15bc, 0xa006, 0x70c2, 0x70c6, 0x70ca,
+	0x70ce, 0x70da, 0x70c0, 0xa03d, 0xa08a, 0x0040, 0x00c8, 0x152a,
+	0x0079, 0x1531, 0x2100, 0xa08a, 0x0040, 0x00c8, 0x15c8, 0x0079,
+	0x1571, 0x15ba, 0x1610, 0x15d9, 0x1648, 0x1680, 0x1680, 0x15d0,
+	0x1c85, 0x168b, 0x15c8, 0x15dd, 0x15df, 0x15e1, 0x15e3, 0x1c8a,
+	0x15c8, 0x1699, 0x16f6, 0x1b64, 0x1c7f, 0x15e5, 0x19d4, 0x1a16,
+	0x1a4e, 0x1a9c, 0x198f, 0x199c, 0x19b0, 0x19c3, 0x17cb, 0x15c8,
+	0x172d, 0x173a, 0x1746, 0x1752, 0x1768, 0x1774, 0x1777, 0x1783,
+	0x178f, 0x1797, 0x17b3, 0x17bf, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x17d8, 0x17ea, 0x1806, 0x183c, 0x1864, 0x1874, 0x1877, 0x18a8,
+	0x18d9, 0x18eb, 0x195e, 0x196e, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x197e, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x1caf, 0x1cb5,
+	0x15c8, 0x15c8, 0x15c8, 0x1cb9, 0x1cfe, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x160a, 0x167a, 0x1693, 0x16f0, 0x1b5e, 0x15c8, 0x15c8,
+	0x15c8, 0x15c8, 0x1d02, 0x1ca1, 0x1cab, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8, 0x15c8,
+	0x15c8, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0078, 0x15bc, 0x73ce,
+	0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0068, 0x15bd, 0x2061,
+	0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x007c,
+	0x70c3, 0x4001, 0x0078, 0x15bd, 0x70c3, 0x4006, 0x0078, 0x15bd,
+	0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, 0x53a3, 0x0078,
+	0x15ba, 0x70c4, 0x70c3, 0x0004, 0x007a, 0x0078, 0x15ba, 0x0078,
+	0x15ba, 0x0078, 0x15ba, 0x0078, 0x15ba, 0x2091, 0x8000, 0x70c3,
+	0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3,
+	0x0008, 0x2001, 0x000d, 0x70d6, 0x2079, 0x0000, 0x781b, 0x0001,
+	0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x041a, 0x2051, 0x0445,
+	0x2061, 0x0447, 0x20c1, 0x0020, 0x2091, 0x5000, 0x2091, 0x4080,
+	0x0078, 0x0418, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0078, 0x1613,
+	0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8, 0x73cc, 0x70c4, 0x20a0,
+	0x2099, 0x0030, 0x7003, 0x0001, 0x7007, 0x0006, 0x731a, 0x721e,
+	0x7422, 0x7526, 0x2021, 0x0040, 0x81ff, 0x0040, 0x15ba, 0xa182,
+	0x0040, 0x00c8, 0x162d, 0x2120, 0xa006, 0x2008, 0x8403, 0x7012,
+	0x7007, 0x0004, 0x7007, 0x0001, 0x7008, 0xd0fc, 0x0040, 0x1634,
+	0x7007, 0x0002, 0xa084, 0x01e0, 0x0040, 0x1642, 0x70c3, 0x4002,
+	0x0078, 0x15bd, 0x24a8, 0x53a5, 0x0078, 0x1624, 0x0078, 0x15ba,
+	0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8, 0x73cc, 0x70c4, 0x2098,
+	0x20a1, 0x0030, 0x7003, 0x0000, 0x7007, 0x0006, 0x731a, 0x721e,
+	0x7422, 0x7526, 0x2021, 0x0040, 0x7007, 0x0006, 0x81ff, 0x0040,
+	0x15ba, 0xa182, 0x0040, 0x00c8, 0x1667, 0x2120, 0xa006, 0x2008,
+	0x8403, 0x7012, 0x24a8, 0x53a6, 0x7007, 0x0001, 0x7008, 0xd0fc,
+	0x0040, 0x166e, 0xa084, 0x01e0, 0x0040, 0x165c, 0x70c3, 0x4002,
+	0x0078, 0x15bd, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0078, 0x164b,
+	0x71c4, 0x70c8, 0x2114, 0xa79e, 0x0004, 0x00c0, 0x1688, 0x200a,
+	0x72ca, 0x0078, 0x15b9, 0x70c7, 0x0008, 0x70cb, 0x000d, 0x70cf,
+	0x0008, 0x0078, 0x15ba, 0x75d8, 0x76dc, 0x75da, 0x76de, 0x0078,
+	0x169c, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d0,
+	0x70c6, 0x72ca, 0x73ce, 0x74d2, 0xa005, 0x0040, 0x16eb, 0xa40a,
+	0x0040, 0x16ac, 0x00c8, 0x15bc, 0x8001, 0x7872, 0xa084, 0xfc00,
+	0x0040, 0x16b9, 0x78ac, 0xc085, 0x78ae, 0x2001, 0x4005, 0x0078,
+	0x15bc, 0x7b7e, 0x7a7a, 0x7e86, 0x7d82, 0x7c76, 0xa48c, 0xff00,
+	0x0040, 0x16d1, 0x8407, 0x8004, 0x8004, 0x810c, 0x810c, 0x810f,
+	0xa118, 0xa291, 0x0000, 0xa6b1, 0x0000, 0xa581, 0x0000, 0x0078,
+	0x16db, 0x8407, 0x8004, 0x8004, 0xa318, 0xa291, 0x0000, 0xa6b1,
+	0x0000, 0xa581, 0x0000, 0x731a, 0x721e, 0x7622, 0x7026, 0xa605,
+	0x0040, 0x16e5, 0x7a10, 0xc2c5, 0x7a12, 0x78ac, 0xa084, 0xfffc,
+	0x78ae, 0x0078, 0x16ee, 0x78ac, 0xc085, 0x78ae, 0x0078, 0x15ba,
+	0x75d8, 0x76dc, 0x75da, 0x76de, 0x0078, 0x16f9, 0x2029, 0x0000,
+	0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d4, 0x70c6, 0x72ca, 0x73ce,
+	0x74d6, 0xa005, 0x0040, 0x1728, 0xa40a, 0x0040, 0x1709, 0x00c8,
+	0x15bc, 0x8001, 0x7892, 0xa084, 0xfc00, 0x0040, 0x1716, 0x78ac,
+	0xc0c5, 0x78ae, 0x2001, 0x4005, 0x0078, 0x15bc, 0x7a9a, 0x7b9e,
+	0x7da2, 0x7ea6, 0x2600, 0xa505, 0x0040, 0x1721, 0x7a10, 0xc2c5,
+	0x7a12, 0x7c96, 0x78ac, 0xa084, 0xfcff, 0x78ae, 0x0078, 0x172b,
+	0x78ac, 0xc0c5, 0x78ae, 0x0078, 0x15ba, 0x2009, 0x0000, 0x786c,
+	0xa065, 0x0040, 0x1737, 0x8108, 0x6000, 0x0078, 0x1730, 0x7ac4,
+	0x0078, 0x15b8, 0x2009, 0x4d48, 0x210c, 0x7810, 0xd0ec, 0x00c0,
+	0x15b9, 0x2011, 0x4d88, 0x2214, 0x0078, 0x15b8, 0x2009, 0x4d49,
+	0x210c, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x2011, 0x4d89, 0x2214,
+	0x0078, 0x15b8, 0x2061, 0x4d40, 0x6128, 0x622c, 0x8214, 0x8214,
+	0x8214, 0x7810, 0xd0ec, 0x00c0, 0x1766, 0x2061, 0x4d80, 0x6328,
+	0x73da, 0x632c, 0x831c, 0x831c, 0x831c, 0x73de, 0x0078, 0x15b8,
+	0x2009, 0x4d4c, 0x210c, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x2011,
+	0x4d8c, 0x2214, 0x0078, 0x15b8, 0x7918, 0x0078, 0x15b9, 0x2009,
+	0x4d4d, 0x210c, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x2011, 0x4d8d,
+	0x2214, 0x0078, 0x15b8, 0x2009, 0x4d4e, 0x210c, 0x7810, 0xd0ec,
+	0x00c0, 0x15b9, 0x2011, 0x4d8e, 0x2214, 0x0078, 0x15b8, 0x7920,
+	0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x7a24, 0x0078, 0x15b8, 0x71c4,
+	0xd1fc, 0x00c0, 0x179f, 0x2011, 0x51c0, 0x0078, 0x17a1, 0x2011,
+	0x5240, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xa268,
+	0x6a00, 0x6804, 0xd09c, 0x0040, 0x17b0, 0x6b08, 0x0078, 0x17b1,
+	0x6b0c, 0x0078, 0x15b7, 0x77c4, 0x1078, 0x1dcb, 0x2091, 0x8000,
+	0x6b1c, 0x6a14, 0x2091, 0x8001, 0x2708, 0x0078, 0x15b7, 0x2061,
+	0x4d40, 0x6118, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x2061, 0x4d80,
+	0x6218, 0x0078, 0x15b8, 0x77c4, 0x1078, 0x1dcb, 0x2091, 0x8000,
+	0x6908, 0x6a18, 0x6b10, 0x77da, 0x2091, 0x8001, 0x0078, 0x15b7,
+	0x71c4, 0x2110, 0xa294, 0x000f, 0xa282, 0x0010, 0x00c8, 0x15b2,
+	0x1078, 0x2735, 0xa384, 0x4000, 0x0040, 0x17e8, 0xa295, 0x0020,
+	0x0078, 0x15b7, 0x71c4, 0x2100, 0xc0bc, 0xa082, 0x0010, 0x00c8,
+	0x15b2, 0xd1bc, 0x00c0, 0x17f9, 0x2011, 0x4d48, 0x2204, 0x0078,
+	0x17fd, 0x2011, 0x4d88, 0x2204, 0xc0bd, 0x007e, 0x2100, 0xc0bc,
+	0x2012, 0x1078, 0x2692, 0x017f, 0x0078, 0x15b9, 0x71c4, 0x2021,
+	0x4d49, 0x2404, 0x70c6, 0x2019, 0x0000, 0x0078, 0x1815, 0x71c8,
+	0x2021, 0x4d89, 0x2404, 0x70ca, 0xc3fd, 0x2011, 0x1834, 0x20a9,
+	0x0008, 0x2204, 0xa106, 0x0040, 0x1824, 0x8210, 0x00f0, 0x1819,
+	0x71c4, 0x72c8, 0x0078, 0x15b1, 0xa292, 0x1834, 0x027e, 0x2122,
+	0x017f, 0x1078, 0x26b3, 0x7810, 0xd0ec, 0x00c0, 0x1832, 0xd3fc,
+	0x0040, 0x180f, 0x0078, 0x15ba, 0x03e8, 0x00fa, 0x01f4, 0x02ee,
+	0x0064, 0x0019, 0x0032, 0x004b, 0x2061, 0x4d40, 0x6128, 0x622c,
+	0x8214, 0x8214, 0x8214, 0x70c4, 0x602a, 0x70c8, 0x8003, 0x8003,
+	0x8003, 0x602e, 0x7810, 0xd0ec, 0x00c0, 0x1862, 0x027e, 0x017e,
+	0x2061, 0x4d80, 0x6128, 0x622c, 0x8214, 0x8214, 0x8214, 0x70d8,
+	0x602a, 0x70dc, 0x8003, 0x8003, 0x8003, 0x602e, 0x71da, 0x72de,
+	0x017f, 0x027f, 0x0078, 0x15b8, 0x2061, 0x4d40, 0x6130, 0x70c4,
+	0x6032, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x2061, 0x4d80, 0x6230,
+	0x70c8, 0x6032, 0x0078, 0x15b8, 0x7918, 0x0078, 0x15b9, 0x71c4,
+	0xa184, 0xffcf, 0x0040, 0x1883, 0x7810, 0xd0ec, 0x00c0, 0x15b2,
+	0x72c8, 0x0078, 0x15b1, 0x2011, 0x4d4d, 0x2204, 0x2112, 0x007e,
+	0x2019, 0x0000, 0x1078, 0x271a, 0x7810, 0xd0ec, 0x0040, 0x1893,
+	0x017f, 0x0078, 0x15b9, 0x71c8, 0xa184, 0xffcf, 0x0040, 0x189c,
+	0x2110, 0x71c4, 0x0078, 0x15b1, 0x2011, 0x4d8d, 0x2204, 0x2112,
+	0x007e, 0xc3fd, 0x1078, 0x271a, 0x027f, 0x017f, 0x0078, 0x15b8,
+	0x71c4, 0xa182, 0x0010, 0x0048, 0x18b4, 0x7810, 0xd0ec, 0x00c0,
+	0x15b2, 0x72c8, 0x0078, 0x15b1, 0x2011, 0x4d4e, 0x2204, 0x007e,
+	0x2112, 0x2019, 0x0000, 0x1078, 0x26f8, 0x7810, 0xd0ec, 0x0040,
+	0x18c4, 0x017f, 0x0078, 0x15b9, 0x71c8, 0xa182, 0x0010, 0x0048,
+	0x18cd, 0x2110, 0x71c4, 0x0078, 0x15b1, 0x2011, 0x4d8e, 0x2204,
+	0x007e, 0x2112, 0xc3fd, 0x1078, 0x26f8, 0x027f, 0x017f, 0x0078,
+	0x15b8, 0x71c4, 0x72c8, 0xa184, 0xfffd, 0x00c0, 0x15b1, 0xa284,
+	0xfffd, 0x00c0, 0x15b1, 0x2100, 0x7920, 0x7822, 0x2200, 0x7a24,
+	0x7826, 0x0078, 0x15b8, 0x71c4, 0xd1fc, 0x00c0, 0x18f3, 0x2011,
+	0x51c0, 0x0078, 0x18f5, 0x2011, 0x5240, 0x8107, 0xa084, 0x000f,
+	0x8003, 0x8003, 0x8003, 0xa268, 0x2019, 0x0000, 0x72c8, 0x2091,
+	0x8000, 0xa284, 0x0080, 0x0040, 0x190b, 0x6c14, 0x84ff, 0x00c0,
+	0x190b, 0x6817, 0x0040, 0xa284, 0x0040, 0x0040, 0x1915, 0x6c10,
+	0x84ff, 0x00c0, 0x1915, 0x6813, 0x0001, 0x6800, 0x007e, 0xa226,
+	0x0040, 0x1932, 0x6a02, 0xd4ec, 0x0040, 0x191f, 0xc3a5, 0xd4e4,
+	0x0040, 0x1923, 0xc39d, 0xd4f4, 0x0040, 0x1932, 0x810f, 0xd2f4,
+	0x0040, 0x192e, 0x1078, 0x2777, 0x0078, 0x1932, 0x1078, 0x2755,
+	0x0078, 0x1932, 0x72cc, 0x6808, 0xa206, 0x0040, 0x1954, 0xa2a4,
+	0x00ff, 0x7814, 0xd0e4, 0x00c0, 0x1945, 0xa482, 0x0028, 0x0048,
+	0x1951, 0x0040, 0x1951, 0x0078, 0x1949, 0xa482, 0x0043, 0x0048,
+	0x1951, 0x71c4, 0x71c6, 0x027f, 0x72ca, 0x2091, 0x8001, 0x0078,
+	0x15b3, 0x6a0a, 0xa39d, 0x000a, 0x6804, 0xa305, 0x6806, 0x027f,
+	0x6b0c, 0x71c4, 0x2091, 0x8001, 0x0078, 0x15b7, 0x77c4, 0x1078,
+	0x1dcb, 0x2091, 0x8000, 0x6a14, 0x6b1c, 0x2091, 0x8001, 0x70c8,
+	0x6816, 0x70cc, 0x681e, 0x2708, 0x0078, 0x15b7, 0x70c4, 0x2061,
+	0x4d40, 0x6118, 0x601a, 0x7810, 0xd0ec, 0x00c0, 0x15b9, 0x70c8,
+	0x2061, 0x4d80, 0x6218, 0x601a, 0x0078, 0x15b8, 0x71c4, 0x72c8,
+	0x73cc, 0xa182, 0x0010, 0x00c8, 0x15b2, 0x1078, 0x2799, 0xa384,
+	0x4000, 0x0040, 0x198d, 0xa295, 0x0020, 0x0078, 0x15b7, 0x77c4,
+	0x1078, 0x1dcb, 0x2091, 0x8000, 0x6a08, 0xc28d, 0x6a0a, 0x2091,
+	0x8001, 0x2708, 0x0078, 0x15b8, 0x77c4, 0x1078, 0x1dcb, 0x2091,
+	0x8000, 0x6a08, 0xa294, 0xfff9, 0x6a0a, 0x6804, 0xa005, 0x0040,
+	0x19ab, 0x1078, 0x25ea, 0x2091, 0x8001, 0x2708, 0x0078, 0x15b8,
+	0x77c4, 0x1078, 0x1dcb, 0x2091, 0x8000, 0x6a08, 0xc295, 0x6a0a,
+	0x6804, 0xa005, 0x0040, 0x19be, 0x1078, 0x25ea, 0x2091, 0x8001,
+	0x2708, 0x0078, 0x15b8, 0x77c4, 0x2041, 0x0001, 0x2049, 0x0005,
+	0x2051, 0x0020, 0x2091, 0x8000, 0x1078, 0x1de6, 0x2091, 0x8001,
+	0x2708, 0x6a08, 0x0078, 0x15b8, 0x77c4, 0x7814, 0xd0e4, 0x00c0,
+	0x19e8, 0xd7fc, 0x0040, 0x19e2, 0x1078, 0x1d4b, 0x0040, 0x19e8,
+	0x0078, 0x15bc, 0x1078, 0x1d3b, 0x0040, 0x19e8, 0x0078, 0x15bc,
+	0x73c8, 0x72cc, 0x77c6, 0x73ca, 0x72ce, 0x1078, 0x1e6d, 0x00c0,
+	0x1a12, 0x6818, 0xa005, 0x0040, 0x1a0c, 0x2708, 0x077e, 0x1078,
+	0x27c9, 0x077f, 0x00c0, 0x1a0c, 0x2001, 0x0015, 0xd7fc, 0x00c0,
+	0x1a05, 0x2061, 0x4d40, 0x0078, 0x1a08, 0xc0fd, 0x2061, 0x4d80,
+	0x782a, 0x2091, 0x8001, 0x007c, 0x2091, 0x8001, 0x2001, 0x4005,
+	0x0078, 0x15bc, 0x2091, 0x8001, 0x0078, 0x15ba, 0x77c4, 0x7814,
+	0xd0e4, 0x00c0, 0x1a2a, 0xd7fc, 0x0040, 0x1a24, 0x1078, 0x1d4b,
+	0x0040, 0x1a2a, 0x0078, 0x15bc, 0x1078, 0x1d3b, 0x0040, 0x1a2a,
+	0x0078, 0x15bc, 0x77c6, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051,
+	0x0020, 0x2091, 0x8000, 0x1078, 0x1de6, 0x2009, 0x0016, 0xd7fc,
+	0x00c0, 0x1a3e, 0x2061, 0x4d40, 0x0078, 0x1a41, 0x2061, 0x4d80,
+	0xc1fd, 0x6067, 0x0003, 0x607f, 0x0000, 0x6776, 0x6083, 0x000f,
+	0x792a, 0x1078, 0x25ea, 0x2091, 0x8001, 0x007c, 0x77c8, 0x77ca,
+	0x77c4, 0x77c6, 0x7814, 0xd0e4, 0x00c0, 0x1a65, 0xd7fc, 0x0040,
+	0x1a5f, 0x1078, 0x1d4b, 0x0040, 0x1a65, 0x0078, 0x15bc, 0x1078,
+	0x1d3b, 0x0040, 0x1a65, 0x0078, 0x15bc, 0xa7bc, 0xff00, 0x2091,
+	0x8000, 0x2009, 0x0017, 0xd7fc, 0x00c0, 0x1a72, 0x2061, 0x4d40,
+	0x0078, 0x1a75, 0x2061, 0x4d80, 0xc1fd, 0x607f, 0x0000, 0x6067,
+	0x0002, 0x6776, 0x6083, 0x000f, 0x792a, 0x1078, 0x25ea, 0x2091,
+	0x8001, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0010, 0x2091,
+	0x8000, 0x70c8, 0xa005, 0x0040, 0x1a90, 0x60d4, 0xc0fd, 0x60d6,
+	0x1078, 0x1de6, 0x70c8, 0x6836, 0x8738, 0xa784, 0x001f, 0x00c0,
+	0x1a90, 0x2091, 0x8001, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x1ab0,
+	0x72c8, 0xd284, 0x0040, 0x1aaa, 0x1078, 0x1d4b, 0x0040, 0x1ab0,
+	0x0078, 0x15bc, 0x1078, 0x1d3b, 0x0040, 0x1ab0, 0x0078, 0x15bc,
+	0x72c8, 0x72ca, 0x78ac, 0xa084, 0x0003, 0x00c0, 0x1adb, 0x2039,
+	0x0000, 0xd284, 0x0040, 0x1abd, 0xc7fd, 0x2041, 0x0021, 0x2049,
+	0x0004, 0x2051, 0x0008, 0x1078, 0x1dcb, 0x2091, 0x8000, 0x6808,
+	0xc0d4, 0xa80d, 0x690a, 0x2091, 0x8001, 0x8738, 0xa784, 0x001f,
+	0x00c0, 0x1ac3, 0xa7bc, 0xff00, 0x873f, 0x8738, 0x873f, 0xa784,
+	0x0f00, 0x00c0, 0x1ac3, 0x2091, 0x8000, 0x72c8, 0xd284, 0x00c0,
+	0x1aed, 0x7810, 0xd0ec, 0x0040, 0x1ae9, 0x2069, 0x0100, 0x0078,
+	0x1aef, 0x2069, 0x0200, 0x0078, 0x1aef, 0x2069, 0x0100, 0x6808,
+	0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4, 0x0040, 0x1b0f, 0x684b,
+	0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0040, 0x1b01, 0x00f0,
+	0x1afb, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xd084, 0x0040,
+	0x1b0b, 0x00f0, 0x1b05, 0x20a9, 0x00fa, 0x00f0, 0x1b0d, 0x2079,
+	0x4d00, 0x2009, 0x0018, 0x72c8, 0xd284, 0x00c0, 0x1b1b, 0x2061,
+	0x4d40, 0x0078, 0x1b1e, 0x2061, 0x4d80, 0xc1fd, 0x792a, 0x6067,
+	0x0001, 0x6083, 0x000f, 0x60a7, 0x0000, 0x60a8, 0x60b2, 0x60b6,
+	0x60d4, 0xd0b4, 0x0040, 0x1b38, 0xc0b4, 0x60d6, 0x0c7e, 0x60b8,
+	0xa065, 0x6008, 0xc0d4, 0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f,
+	0x60d4, 0xa084, 0x77ff, 0x60d6, 0x78ac, 0xc08d, 0x78ae, 0x681b,
+	0x0047, 0x2091, 0x8001, 0x007c, 0xd7fc, 0x00c0, 0x1b4b, 0x2069,
+	0x4d40, 0x0078, 0x1b4d, 0x2069, 0x4d80, 0x71c4, 0x71c6, 0x6916,
+	0x81ff, 0x00c0, 0x1b55, 0x68a7, 0x0001, 0x78ac, 0xc08c, 0x78ae,
+	0xd084, 0x00c0, 0x1b5d, 0x1078, 0x1ecd, 0x007c, 0x75d8, 0x74dc,
+	0x75da, 0x74de, 0x0078, 0x1b67, 0x2029, 0x0000, 0x2520, 0x71c4,
+	0x73c8, 0x72cc, 0x71c6, 0x73ca, 0x72ce, 0x2079, 0x4d00, 0x7dde,
+	0x7cda, 0x7bd6, 0x7ad2, 0x1078, 0x1da4, 0x0040, 0x1c69, 0x20a9,
+	0x0005, 0x20a1, 0x4d14, 0x2091, 0x8000, 0x41a1, 0x2091, 0x8001,
+	0x2009, 0x0040, 0x1078, 0x1fb8, 0x0040, 0x1b8a, 0x1078, 0x1dad,
+	0x0078, 0x1c69, 0x6004, 0xa08c, 0x00ff, 0xa18e, 0x0009, 0x00c0,
+	0x1b95, 0x007e, 0x1078, 0x2339, 0x007f, 0xa084, 0xff00, 0x8007,
+	0x8009, 0x0040, 0x1c09, 0x0c7e, 0x2c68, 0x1078, 0x1da4, 0x0040,
+	0x1bdb, 0x2c00, 0x689e, 0x8109, 0x00c0, 0x1b9c, 0x609f, 0x0000,
+	0x0c7f, 0x0c7e, 0x7ddc, 0x7cd8, 0x7bd4, 0x7ad0, 0xa290, 0x0040,
+	0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x7dde, 0x7cda,
+	0x7bd6, 0x7ad2, 0x2c68, 0x689c, 0xa065, 0x0040, 0x1c08, 0x2009,
+	0x0040, 0x1078, 0x1fb8, 0x00c0, 0x1bf2, 0x6004, 0xa084, 0x00ff,
+	0xa086, 0x0002, 0x00c0, 0x1bdb, 0x6004, 0xa084, 0x00ff, 0xa086,
+	0x000a, 0x00c0, 0x1bd7, 0x017e, 0x1078, 0x2335, 0x017f, 0x2d00,
+	0x6002, 0x0078, 0x1baa, 0x0c7f, 0x0c7e, 0x609c, 0x1078, 0x1e30,
+	0x0c7f, 0x609f, 0x0000, 0x1078, 0x1c6d, 0x2009, 0x0018, 0x6008,
+	0xc0cd, 0x600a, 0x6004, 0x6086, 0x1078, 0x1d5b, 0x1078, 0x1dad,
+	0x0078, 0x1c69, 0x0c7f, 0x0c7e, 0x609c, 0x1078, 0x1e30, 0x0c7f,
+	0x609f, 0x0000, 0x1078, 0x1c6d, 0x2009, 0x0018, 0x6087, 0x0103,
+	0x601b, 0x0003, 0x1078, 0x1d5b, 0x1078, 0x1dad, 0x0078, 0x1c69,
+	0x0c7f, 0x7814, 0xd0e4, 0x00c0, 0x1c2e, 0x6114, 0xd1fc, 0x0040,
+	0x1c17, 0x1078, 0x1d4b, 0x0040, 0x1c2e, 0x0078, 0x1c1b, 0x1078,
+	0x1d3b, 0x0040, 0x1c2e, 0x2029, 0x0000, 0x2520, 0x2009, 0x0018,
+	0x73c8, 0x72cc, 0x6087, 0x0103, 0x601b, 0x0021, 0x1078, 0x1d5b,
+	0x1078, 0x1dad, 0x2001, 0x4007, 0x0078, 0x15bc, 0x74c4, 0x73c8,
+	0x72cc, 0x6014, 0x2091, 0x8000, 0x0e7e, 0x2009, 0x0012, 0xd0fc,
+	0x00c0, 0x1c3e, 0x2071, 0x4d40, 0x0078, 0x1c41, 0x2071, 0x4d80,
+	0xc1fd, 0x792a, 0x7067, 0x0005, 0x71d4, 0xc1dc, 0x71d6, 0x736a,
+	0x726e, 0x7472, 0x7076, 0x707b, 0x0000, 0x2c00, 0x707e, 0xa02e,
+	0x2530, 0x611c, 0xa184, 0x0060, 0x0040, 0x1c58, 0x1078, 0x45a7,
+	0x0e7f, 0x6596, 0x65a6, 0x669a, 0x66aa, 0x60af, 0x0000, 0x60b3,
+	0x0000, 0x6714, 0x6023, 0x0000, 0x1078, 0x25ea, 0x2091, 0x8001,
+	0x007c, 0x70c3, 0x4005, 0x0078, 0x15bd, 0x20a9, 0x0005, 0x2099,
+	0x4d14, 0x2091, 0x8000, 0x530a, 0x2091, 0x8001, 0x2100, 0xa210,
+	0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x007c, 0x71c4,
+	0x70c7, 0x0000, 0x791e, 0x0078, 0x15ba, 0x71c4, 0x71c6, 0x2168,
+	0x0078, 0x1c8c, 0x2069, 0x1000, 0x690c, 0xa016, 0x2d04, 0xa210,
+	0x8d68, 0x8109, 0x00c0, 0x1c8e, 0xa285, 0x0000, 0x00c0, 0x1c9c,
+	0x70c3, 0x4000, 0x0078, 0x1c9e, 0x70c3, 0x4003, 0x70ca, 0x0078,
+	0x15bd, 0x7964, 0x71c6, 0x71c4, 0xa182, 0x0003, 0x00c8, 0x15b2,
+	0x7966, 0x0078, 0x15ba, 0x7964, 0x71c6, 0x0078, 0x15ba, 0x7900,
+	0x71c6, 0x71c4, 0x7902, 0x0078, 0x15ba, 0x7900, 0x71c6, 0x0078,
+	0x15ba, 0x70c4, 0x2011, 0x0000, 0xa08c, 0x000d, 0x0040, 0x1cce,
+	0x810c, 0x0048, 0x1cca, 0x8210, 0x810c, 0x810c, 0x0048, 0x1cca,
+	0x8210, 0x810c, 0x81ff, 0x00c0, 0x15b3, 0x8210, 0x7a0e, 0xd28c,
+	0x0040, 0x1cfa, 0x7910, 0xc1cd, 0x7912, 0x2009, 0x0021, 0x2019,
+	0x0003, 0xd284, 0x0040, 0x1cf4, 0x8108, 0x2019, 0x0041, 0x2011,
+	0x954e, 0x2312, 0x2019, 0x0042, 0x8210, 0x2312, 0x2019, 0x0043,
+	0x8210, 0x2312, 0x2019, 0x0046, 0x8210, 0x2312, 0x2019, 0x0047,
+	0x8210, 0x2312, 0x2019, 0x0006, 0x2011, 0x9553, 0x2112, 0x2011,
+	0x9573, 0x2312, 0x7904, 0x7806, 0x0078, 0x15b9, 0x7804, 0x70c6,
+	0x0078, 0x15ba, 0x71c4, 0xd1fc, 0x00c0, 0x1d0a, 0x2011, 0x51c0,
+	0x0078, 0x1d0c, 0x2011, 0x5240, 0x8107, 0xa084, 0x000f, 0x8003,
+	0x8003, 0x8003, 0xa268, 0x6a14, 0xd2b4, 0x0040, 0x1d1b, 0x2011,
+	0x0001, 0x0078, 0x1d1d, 0x2011, 0x0000, 0x6b0c, 0x0078, 0x15b7,
+	0x017e, 0x7814, 0xd0f4, 0x0040, 0x1d2d, 0x2001, 0x4007, 0x70db,
+	0x0000, 0xa18d, 0x0001, 0x0078, 0x1d39, 0xd0fc, 0x0040, 0x1d38,
+	0x2001, 0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0078, 0x1d39,
+	0xa006, 0x017f, 0x007c, 0x017e, 0x7814, 0xd0f4, 0x0040, 0x1d48,
+	0x2001, 0x4007, 0x70db, 0x0000, 0xa18d, 0x0001, 0x0078, 0x1d49,
+	0xa006, 0x017f, 0x007c, 0x017e, 0x7814, 0xd0fc, 0x0040, 0x1d58,
+	0x2001, 0x4007, 0x70db, 0x0001, 0xa18d, 0x0001, 0x0078, 0x1d59,
+	0xa006, 0x017f, 0x007c, 0x7112, 0x721a, 0x731e, 0x7810, 0xd0c4,
+	0x0040, 0x1d64, 0x7422, 0x7526, 0xac80, 0x0001, 0x8108, 0x810c,
+	0x81a9, 0x8098, 0x20a1, 0x0030, 0x7003, 0x0000, 0x6084, 0x20a2,
+	0x53a6, 0x7007, 0x0001, 0x7974, 0xa184, 0xff00, 0x0040, 0x1d81,
+	0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007, 0xa100, 0x0078,
+	0x1d84, 0x8107, 0x8004, 0x8004, 0x797c, 0xa108, 0x7a78, 0xa006,
+	0xa211, 0x7d10, 0xd5c4, 0x0040, 0x1d91, 0x7b84, 0xa319, 0x7c80,
+	0xa421, 0x7008, 0xd0fc, 0x0040, 0x1d91, 0x7003, 0x0001, 0x7007,
+	0x0006, 0x711a, 0x721e, 0x7d10, 0xd5c4, 0x0040, 0x1da1, 0x7322,
+	0x7426, 0xa084, 0x01e0, 0x007c, 0x7848, 0xa065, 0x0040, 0x1dac,
+	0x2c04, 0x784a, 0x2063, 0x0000, 0x007c, 0x0f7e, 0x2079, 0x4d00,
+	0x7848, 0x2062, 0x2c00, 0xa005, 0x00c0, 0x1db8, 0x1078, 0x290c,
+	0x784a, 0x0f7f, 0x007c, 0x2011, 0x9700, 0x7a4a, 0x7bc4, 0x8319,
+	0x0040, 0x1dc8, 0xa280, 0x0032, 0x2012, 0x2010, 0x0078, 0x1dbf,
+	0x2013, 0x0000, 0x007c, 0x017e, 0x027e, 0xd7fc, 0x00c0, 0x1dd4,
+	0x2011, 0x52c0, 0x0078, 0x1dd6, 0x2011, 0x72c0, 0xa784, 0x0f00,
+	0x800b, 0xa784, 0x001f, 0x0040, 0x1de1, 0x8003, 0x8003, 0x8003,
+	0x8003, 0xa105, 0xa268, 0x027f, 0x017f, 0x007c, 0x1078, 0x1dcb,
+	0x2900, 0x682a, 0x2a00, 0x682e, 0x6808, 0xa084, 0xf9ef, 0xa80d,
+	0x690a, 0x0e7e, 0xd7fc, 0x00c0, 0x1dfb, 0x2009, 0x4d53, 0x2071,
+	0x4d40, 0x0078, 0x1dff, 0x2009, 0x4d93, 0x2071, 0x4d80, 0x210c,
+	0x6804, 0xa005, 0x0040, 0x1e0f, 0xa116, 0x00c0, 0x1e0f, 0x2060,
+	0x6000, 0x6806, 0x017e, 0x200b, 0x0000, 0x0078, 0x1e12, 0x2009,
+	0x0000, 0x017e, 0x6804, 0xa065, 0x0040, 0x1e27, 0x6000, 0x6806,
+	0x1078, 0x1e42, 0x1078, 0x2004, 0x6810, 0x7908, 0x8109, 0x790a,
+	0x8001, 0x6812, 0x00c0, 0x1e12, 0x7910, 0xc1a5, 0x7912, 0x017f,
+	0x6902, 0x6906, 0x2d00, 0x2060, 0x1078, 0x2a6d, 0x0e7f, 0x007c,
+	0xa065, 0x0040, 0x1e41, 0x2008, 0x609c, 0xa005, 0x0040, 0x1e3e,
+	0x2062, 0x609f, 0x0000, 0xa065, 0x0078, 0x1e34, 0x7848, 0x794a,
+	0x2062, 0x007c, 0x6007, 0x0103, 0x608f, 0x0000, 0x20a9, 0x001c,
+	0xac80, 0x0005, 0x20a0, 0x2001, 0x0000, 0x40a4, 0x6828, 0x601a,
+	0x682c, 0x6022, 0x007c, 0x0e7e, 0xd7fc, 0x00c0, 0x1e5d, 0x2071,
+	0x4d40, 0x2031, 0x4dc0, 0x0078, 0x1e61, 0x2071, 0x4d80, 0x2031,
+	0x4fc0, 0x7050, 0xa08c, 0x0200, 0x00c0, 0x1e6b, 0xa608, 0x2d0a,
+	0x8000, 0x7052, 0xa006, 0x0e7f, 0x007c, 0x0f7e, 0xd7fc, 0x00c0,
+	0x1e75, 0x2079, 0x4d40, 0x0078, 0x1e77, 0x2079, 0x4d80, 0x1078,
+	0x1dcb, 0x2091, 0x8000, 0x6804, 0x780a, 0xa065, 0x0040, 0x1ecb,
+	0x0078, 0x1e89, 0x2c00, 0x780a, 0x2060, 0x6000, 0xa065, 0x0040,
+	0x1ecb, 0x6010, 0xa306, 0x00c0, 0x1e82, 0x600c, 0xa206, 0x00c0,
+	0x1e82, 0x2c28, 0x784c, 0xac06, 0x00c0, 0x1e98, 0x0078, 0x1ec8,
+	0x6804, 0xac06, 0x00c0, 0x1ea6, 0x6000, 0x2060, 0x6806, 0xa005,
+	0x00c0, 0x1ea6, 0x6803, 0x0000, 0x0078, 0x1eb0, 0x6400, 0x7808,
+	0x2060, 0x6402, 0xa486, 0x0000, 0x00c0, 0x1eb0, 0x2c00, 0x6802,
+	0x2560, 0x0f7f, 0x1078, 0x1e42, 0x0f7e, 0x601b, 0x0005, 0x6023,
+	0x0020, 0x0f7f, 0x1078, 0x2004, 0x0f7e, 0x7908, 0x8109, 0x790a,
+	0x6810, 0x8001, 0x6812, 0x00c0, 0x1ec8, 0x7810, 0xc0a5, 0x7812,
+	0x2001, 0xffff, 0xa005, 0x0f7f, 0x007c, 0x077e, 0x2700, 0x2039,
+	0x0000, 0xd0fc, 0x0040, 0x1ed5, 0xc7fd, 0x2041, 0x0021, 0x2049,
+	0x0004, 0x2051, 0x0008, 0x2091, 0x8000, 0x1078, 0x1de6, 0x8738,
+	0xa784, 0x001f, 0x00c0, 0x1edd, 0xa7bc, 0xff00, 0x873f, 0x8738,
+	0x873f, 0xa784, 0x0f00, 0x00c0, 0x1edd, 0x2091, 0x8001, 0x077f,
+	0x007c, 0x786c, 0x2009, 0x9574, 0x210c, 0xa10d, 0x0040, 0x1efb,
+	0xa065, 0x0078, 0x2356, 0x2061, 0x0000, 0x6018, 0xd084, 0x00c0,
+	0x1f1b, 0x7810, 0xd08c, 0x0040, 0x1f0c, 0xc08c, 0x7812, 0xc7fc,
+	0x2069, 0x4d40, 0x0078, 0x1f11, 0xc08d, 0x7812, 0x2069, 0x4d80,
+	0xc7fd, 0x2091, 0x8000, 0x681c, 0x681f, 0x0000, 0x2091, 0x8001,
+	0xa005, 0x00c0, 0x1f1c, 0x007c, 0xa08c, 0xfff0, 0x0040, 0x1f22,
+	0x1078, 0x290c, 0x0079, 0x1f24, 0x1f34, 0x1f37, 0x1f3d, 0x1f41,
+	0x1f35, 0x1f45, 0x1f35, 0x1f35, 0x1f35, 0x1f4b, 0x1f7c, 0x1f80,
+	0x1f86, 0x1f9b, 0x1f35, 0x1f35, 0x007c, 0x1078, 0x290c, 0x1078,
+	0x1ecd, 0x2001, 0x8001, 0x0078, 0x1fa7, 0x2001, 0x8003, 0x0078,
+	0x1fa7, 0x2001, 0x8004, 0x0078, 0x1fa7, 0x1078, 0x1ecd, 0x2001,
+	0x8006, 0x0078, 0x1fa7, 0x2091, 0x8000, 0x077e, 0xd7fc, 0x00c0,
+	0x1f57, 0x2069, 0x4d40, 0x2039, 0x0009, 0x0078, 0x1f5b, 0x2069,
+	0x4d80, 0x2039, 0x0009, 0x6800, 0xa086, 0x0000, 0x0040, 0x1f65,
+	0x007f, 0x6f1e, 0x2091, 0x8001, 0x007c, 0x6874, 0x077f, 0xa0bc,
+	0xff00, 0x2041, 0x0021, 0x2049, 0x0004, 0x2051, 0x0010, 0x1078,
+	0x1de6, 0x8738, 0xa784, 0x001f, 0x00c0, 0x1f6f, 0x2091, 0x8001,
+	0x2001, 0x800a, 0x0078, 0x1fa7, 0x2001, 0x800c, 0x0078, 0x1fa7,
+	0x1078, 0x1ecd, 0x2001, 0x800d, 0x0078, 0x1fa7, 0x7814, 0xd0e4,
+	0x00c0, 0x1f99, 0xd0ec, 0x0040, 0x1f93, 0xd7fc, 0x0040, 0x1f93,
+	0x78e4, 0x0078, 0x1f94, 0x78e0, 0x70c6, 0x2001, 0x800e, 0x0078,
+	0x1fa7, 0x0078, 0x1f35, 0xd7fc, 0x0040, 0x1fa1, 0x78ec, 0x0078,
+	0x1fa2, 0x78e8, 0x70c6, 0x2001, 0x000d, 0x0078, 0x1fa7, 0x70c2,
+	0xd7fc, 0x00c0, 0x1faf, 0x70db, 0x0000, 0x0078, 0x1fb1, 0x70db,
+	0x0001, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x4080, 0x007c,
+	0xac80, 0x0001, 0x81ff, 0x0040, 0x1fe3, 0x2099, 0x0030, 0x20a0,
+	0x700c, 0xa084, 0x03ff, 0x0040, 0x1fc5, 0x7018, 0x007e, 0x701c,
+	0x007e, 0x7020, 0x007e, 0x7024, 0x007e, 0x7112, 0x81ac, 0x721a,
+	0x731e, 0x7422, 0x7526, 0x7003, 0x0001, 0x7007, 0x0001, 0x7008,
+	0x800b, 0x00c8, 0x1fd7, 0x7007, 0x0002, 0xa08c, 0x01e0, 0x00c0,
+	0x1fe3, 0x53a5, 0xa006, 0x7003, 0x0000, 0x7007, 0x0004, 0x007f,
+	0x7026, 0x007f, 0x7022, 0x007f, 0x701e, 0x007f, 0x701a, 0x007c,
+	0x2011, 0x0020, 0x2009, 0x0010, 0x6b0a, 0x6c0e, 0x6803, 0xfd00,
+	0x6807, 0x0018, 0x6a1a, 0x2d00, 0xa0e8, 0x0008, 0xa290, 0x0004,
+	0x8109, 0x00c0, 0x1ff4, 0x007c, 0x6004, 0x6086, 0x2c08, 0x2063,
+	0x0000, 0x7868, 0xa005, 0x796a, 0x0040, 0x2011, 0x2c02, 0x0078,
+	0x2012, 0x796e, 0x007c, 0x0c7e, 0x2061, 0x4d00, 0x6887, 0x0103,
+	0x2d08, 0x206b, 0x0000, 0x6068, 0xa005, 0x616a, 0x0040, 0x2023,
+	0x2d02, 0x0078, 0x2024, 0x616e, 0x0c7f, 0x007c, 0x2091, 0x8000,
+	0x2c04, 0x786e, 0xa005, 0x00c0, 0x202e, 0x786a, 0x2091, 0x8001,
+	0x609c, 0xa005, 0x0040, 0x2047, 0x0c7e, 0x2060, 0x2008, 0x609c,
+	0xa005, 0x0040, 0x2043, 0x2062, 0x609f, 0x0000, 0xa065, 0x609c,
+	0xa005, 0x00c0, 0x203b, 0x7848, 0x794a, 0x2062, 0x0c7f, 0x7848,
+	0x2062, 0x609f, 0x0000, 0xac85, 0x0000, 0x00c0, 0x2051, 0x1078,
+	0x290c, 0x784a, 0x007c, 0x20a9, 0x0010, 0xa006, 0x8004, 0x8086,
+	0x818e, 0x00c8, 0x205c, 0xa200, 0x00f0, 0x2057, 0x8086, 0x818e,
+	0x007c, 0x157e, 0x20a9, 0x0010, 0xa005, 0x0040, 0x2082, 0xa11a,
+	0x00c8, 0x2082, 0x8213, 0x818d, 0x0048, 0x2075, 0xa11a, 0x00c8,
+	0x2076, 0x00f0, 0x206a, 0x0078, 0x207a, 0xa11a, 0x2308, 0x8210,
+	0x00f0, 0x206a, 0x007e, 0x3200, 0xa084, 0xf7ff, 0x2080, 0x007f,
+	0x157f, 0x007c, 0x007e, 0x3200, 0xa085, 0x0800, 0x0078, 0x207e,
+	0x7d74, 0x70d0, 0xa506, 0x0040, 0x216e, 0x7810, 0x2050, 0x7800,
+	0xd08c, 0x0040, 0x20aa, 0xdaec, 0x0040, 0x20aa, 0x0e7e, 0x2091,
+	0x8000, 0x2071, 0x0020, 0x7004, 0xa005, 0x00c0, 0x20a7, 0x7008,
+	0x0e7f, 0xa086, 0x0008, 0x0040, 0x20aa, 0x0078, 0x216e, 0x0e7f,
+	0x0078, 0x216e, 0x1078, 0x1da4, 0x0040, 0x216e, 0xa046, 0x7970,
+	0x2500, 0x8000, 0xa112, 0x2009, 0x0040, 0x00c8, 0x20b9, 0x0078,
+	0x20c0, 0x72d0, 0xa206, 0x0040, 0x20c0, 0x8840, 0x2009, 0x0080,
+	0x0c7e, 0x7112, 0x7007, 0x0001, 0x2099, 0x0030, 0x20a9, 0x0020,
+	0xac80, 0x0001, 0x20a0, 0x2061, 0x0000, 0x88ff, 0x0040, 0x20d2,
+	0x1078, 0x1da4, 0x7008, 0xd0fc, 0x0040, 0x20d2, 0x7007, 0x0002,
+	0x2091, 0x8001, 0xa08c, 0x01e0, 0x00c0, 0x2109, 0x53a5, 0x8cff,
+	0x00c0, 0x20e7, 0x88ff, 0x0040, 0x2158, 0x0078, 0x20f1, 0x2c00,
+	0x788e, 0x20a9, 0x0020, 0xac80, 0x0001, 0x20a0, 0x53a5, 0x0078,
+	0x2158, 0xa046, 0x7218, 0x731c, 0xdac4, 0x0040, 0x20f9, 0x7420,
+	0x7524, 0xa292, 0x0040, 0xa39b, 0x0000, 0xa4a3, 0x0000, 0xa5ab,
+	0x0000, 0x721a, 0x731e, 0xdac4, 0x0040, 0x2109, 0x7422, 0x7526,
+	0xa006, 0x7007, 0x0004, 0x0040, 0x2158, 0x8cff, 0x0040, 0x2112,
+	0x1078, 0x1dad, 0x0c7f, 0x1078, 0x1dad, 0xa046, 0x7888, 0x8000,
+	0x788a, 0xa086, 0x0002, 0x0040, 0x2138, 0x7a7c, 0x7b78, 0xdac4,
+	0x0040, 0x2124, 0x7c84, 0x7d80, 0x7974, 0x8107, 0x8004, 0x8004,
+	0xa210, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x721a,
+	0x731e, 0xdac4, 0x0040, 0x216e, 0x7422, 0x7526, 0x0078, 0x216e,
+	0x6014, 0xd0fc, 0x00c0, 0x2140, 0x2069, 0x4d40, 0x0078, 0x2142,
+	0x2069, 0x4d80, 0x2091, 0x8000, 0x681f, 0x0002, 0x88ff, 0x0040,
+	0x214e, 0xa046, 0x788c, 0x2060, 0x0078, 0x2138, 0x788b, 0x0000,
+	0x78ac, 0xa085, 0x0003, 0x78ae, 0x2091, 0x8001, 0x0078, 0x216e,
+	0x0c7f, 0x788b, 0x0000, 0x1078, 0x2307, 0x6004, 0xa084, 0x000f,
+	0x1078, 0x216f, 0x88ff, 0x0040, 0x216c, 0x788c, 0x2060, 0x6004,
+	0xa084, 0x000f, 0x1078, 0x216f, 0x0078, 0x2088, 0x007c, 0x0079,
+	0x2171, 0x2181, 0x219f, 0x21bd, 0x2181, 0x21ce, 0x2192, 0x2181,
+	0x2181, 0x2181, 0x219d, 0x21bb, 0x2181, 0x2181, 0x2181, 0x2181,
+	0x2181, 0x2039, 0x0400, 0x78bc, 0xa705, 0x78be, 0x6008, 0xa705,
+	0x600a, 0x1078, 0x2211, 0x609c, 0x78ba, 0x609f, 0x0000, 0x1078,
+	0x22f1, 0x007c, 0x78bc, 0xd0c4, 0x0040, 0x2198, 0x0078, 0x2181,
+	0x601c, 0xc0bd, 0x601e, 0x0078, 0x21a5, 0x1078, 0x2339, 0x78bc,
+	0xd0c4, 0x0040, 0x21a5, 0x0078, 0x2181, 0x78bf, 0x0000, 0x6004,
+	0x8007, 0xa084, 0x00ff, 0x78b2, 0x8001, 0x0040, 0x21b8, 0x1078,
+	0x2211, 0x0040, 0x21b8, 0x78bc, 0xc0c5, 0x78be, 0x0078, 0x21ba,
+	0x0078, 0x2230, 0x007c, 0x1078, 0x2335, 0x78bc, 0xa08c, 0x0e00,
+	0x00c0, 0x21c5, 0xd0c4, 0x00c0, 0x21c7, 0x0078, 0x2181, 0x1078,
+	0x2211, 0x00c0, 0x21cd, 0x0078, 0x2230, 0x007c, 0x78bc, 0xd0c4,
+	0x0040, 0x21d4, 0x0078, 0x2181, 0x78bf, 0x0000, 0x6714, 0x2011,
+	0x0001, 0x22a8, 0x6018, 0xa084, 0x00ff, 0xa005, 0x0040, 0x21f4,
+	0xa7bc, 0xff00, 0x20a9, 0x0020, 0xa08e, 0x0001, 0x0040, 0x21f4,
+	0xa7bc, 0x8000, 0x2011, 0x0002, 0x20a9, 0x0100, 0xa08e, 0x0002,
+	0x0040, 0x21f4, 0x0078, 0x220e, 0x1078, 0x1dcb, 0x2d00, 0x2091,
+	0x8000, 0x682b, 0x0000, 0x682f, 0x0000, 0x6808, 0xa084, 0xffde,
+	0x680a, 0xade8, 0x0010, 0x2091, 0x8001, 0x00f0, 0x21f7, 0x8211,
+	0x0040, 0x220e, 0x20a9, 0x0100, 0x0078, 0x21f7, 0x1078, 0x1dad,
+	0x007c, 0x609f, 0x0000, 0x78b4, 0xa06d, 0x2c00, 0x78b6, 0x00c0,
+	0x221c, 0x78ba, 0x0078, 0x2224, 0x689e, 0x2d00, 0x6002, 0x78b8,
+	0xad06, 0x00c0, 0x2224, 0x6002, 0x78b0, 0x8001, 0x78b2, 0x00c0,
+	0x222f, 0x78bc, 0xc0c4, 0x78be, 0x78b8, 0x2060, 0xa006, 0x007c,
+	0x0e7e, 0xa02e, 0x2530, 0x7dba, 0x7db6, 0x65ae, 0x65b2, 0x601c,
+	0x60a2, 0x2048, 0xa984, 0xe1ff, 0x601e, 0xa984, 0x0060, 0x0040,
+	0x2243, 0x1078, 0x45a7, 0x6596, 0x65a6, 0x669a, 0x66aa, 0x6714,
+	0x2071, 0x4d80, 0xd7fc, 0x00c0, 0x224f, 0x2071, 0x4d40, 0xa784,
+	0x0f00, 0x800b, 0xa784, 0x001f, 0x0040, 0x225a, 0x8003, 0x8003,
+	0x8003, 0x8003, 0xa105, 0x71c4, 0xa168, 0x2700, 0x8007, 0xa084,
+	0x000f, 0x8003, 0x8003, 0x8003, 0x71c8, 0xa100, 0x60c2, 0x2091,
+	0x8000, 0x7810, 0xd0f4, 0x00c0, 0x2274, 0x6e08, 0xd684, 0x0040,
+	0x228a, 0xd9fc, 0x00c0, 0x228a, 0x2091, 0x8001, 0x1078, 0x1e42,
+	0x2091, 0x8000, 0x1078, 0x2004, 0x2091, 0x8001, 0x7814, 0xd0e4,
+	0x00c0, 0x22ef, 0x7810, 0xd0f4, 0x0040, 0x22ef, 0x601b, 0x0021,
+	0x0078, 0x22ef, 0x6024, 0xa096, 0x0001, 0x00c0, 0x2291, 0x8000,
+	0x6026, 0x6a10, 0x6814, 0xa202, 0x0048, 0x22a4, 0x0040, 0x22a4,
+	0x2091, 0x8001, 0x2039, 0x0200, 0x609c, 0x78ba, 0x609f, 0x0000,
+	0x1078, 0x22f1, 0x0078, 0x22ef, 0x2c08, 0xd9fc, 0x0040, 0x22cc,
+	0x6800, 0xa065, 0x0040, 0x22cc, 0x6a04, 0x7000, 0xa084, 0x0002,
+	0x0040, 0x22c2, 0x704c, 0xa206, 0x00c0, 0x22c2, 0x6b04, 0x2160,
+	0x2304, 0x6002, 0xa005, 0x00c0, 0x22be, 0x6902, 0x2260, 0x6102,
+	0x0078, 0x22d8, 0x2d00, 0x2060, 0x1078, 0x2a6d, 0x6e08, 0x2160,
+	0x6202, 0x6906, 0x0078, 0x22d8, 0x6800, 0x6902, 0xa065, 0x0040,
+	0x22d4, 0x6102, 0x0078, 0x22d5, 0x6906, 0x2160, 0x6003, 0x0000,
+	0x2160, 0xd9fc, 0x0040, 0x22df, 0xa6b4, 0xfffc, 0x6e0a, 0x6810,
+	0x7d08, 0x8528, 0x7d0a, 0x8000, 0x6812, 0x2091, 0x8001, 0xd6b4,
+	0x0040, 0x22ef, 0xa6b6, 0x0040, 0x6e0a, 0x1078, 0x1e53, 0x0e7f,
+	0x007c, 0x6008, 0xa705, 0x600a, 0x2091, 0x8000, 0x1078, 0x2004,
+	0x2091, 0x8001, 0x78b8, 0xa065, 0x0040, 0x2304, 0x609c, 0x78ba,
+	0x609f, 0x0000, 0x0078, 0x22f1, 0x78b6, 0x78ba, 0x007c, 0x7970,
+	0x7874, 0x2818, 0xd384, 0x0040, 0x2311, 0x8000, 0xa112, 0x0048,
+	0x2316, 0x8000, 0xa112, 0x00c8, 0x2326, 0xc384, 0x7a7c, 0x721a,
+	0x7a78, 0x721e, 0xdac4, 0x0040, 0x2321, 0x7a84, 0x7222, 0x7a80,
+	0x7226, 0xa006, 0xd384, 0x0040, 0x2326, 0x8000, 0x7876, 0x70d2,
+	0x781c, 0xa005, 0x0040, 0x2334, 0x8001, 0x781e, 0x00c0, 0x2334,
+	0x0068, 0x2334, 0x2091, 0x4080, 0x007c, 0x2039, 0x234d, 0x0078,
+	0x233b, 0x2039, 0x2353, 0x2704, 0xa005, 0x0040, 0x234c, 0xac00,
+	0x2068, 0x6908, 0x6810, 0x6912, 0x680a, 0x690c, 0x6814, 0x6916,
+	0x680e, 0x8738, 0x0078, 0x233b, 0x007c, 0x0003, 0x0009, 0x000f,
+	0x0015, 0x001b, 0x0000, 0x0015, 0x001b, 0x0000, 0x2041, 0x0000,
+	0x780c, 0x0079, 0x235b, 0x252d, 0x2500, 0x235f, 0x23d8, 0x2039,
+	0x9574, 0x2734, 0x7d10, 0x0078, 0x237f, 0x6084, 0xa086, 0x0103,
+	0x00c0, 0x23c1, 0x6114, 0x6018, 0xa105, 0x0040, 0x2374, 0x86ff,
+	0x00c0, 0x2390, 0x0078, 0x23c1, 0x8603, 0xa080, 0x9555, 0x620c,
+	0x2202, 0x8000, 0x6210, 0x2202, 0x1078, 0x2026, 0x8630, 0xa68e,
+	0x000f, 0x0040, 0x244c, 0x786c, 0xa065, 0x00c0, 0x2365, 0x7808,
+	0xa602, 0x00c8, 0x2390, 0xd5ac, 0x00c0, 0x2390, 0x263a, 0x007c,
+	0xa682, 0x0003, 0x00c8, 0x244c, 0x2091, 0x8000, 0x2069, 0x0000,
+	0x6818, 0xd084, 0x00c0, 0x23bc, 0x2011, 0x9555, 0x2204, 0x70c6,
+	0x8210, 0x2204, 0x70ca, 0xd684, 0x00c0, 0x23ac, 0x8210, 0x2204,
+	0x70da, 0x8210, 0x2204, 0x70de, 0xa685, 0x8020, 0x70c2, 0x681b,
+	0x0001, 0x2091, 0x4080, 0x7810, 0xa084, 0xffcf, 0x7812, 0x2091,
+	0x8001, 0x203b, 0x0000, 0x007c, 0x7810, 0xc0ad, 0x7812, 0x0078,
+	0x244c, 0x263a, 0x1078, 0x2537, 0x00c0, 0x255a, 0x786c, 0xa065,
+	0x00c0, 0x2365, 0x2091, 0x8000, 0x7810, 0xa084, 0xffcf, 0x86ff,
+	0x0040, 0x23d3, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0078, 0x255a,
+	0x2039, 0x9574, 0x2734, 0x7d10, 0x0078, 0x23f4, 0x6084, 0xa086,
+	0x0103, 0x00c0, 0x2435, 0x6114, 0x6018, 0xa105, 0x0040, 0x23ed,
+	0x86ff, 0x00c0, 0x2405, 0x0078, 0x2435, 0xa680, 0x9555, 0x620c,
+	0x2202, 0x1078, 0x2026, 0x8630, 0xa68e, 0x001e, 0x0040, 0x244c,
+	0x786c, 0xa065, 0x00c0, 0x23de, 0x7808, 0xa602, 0x00c8, 0x2405,
+	0xd5ac, 0x00c0, 0x2405, 0x263a, 0x007c, 0xa682, 0x0006, 0x00c8,
+	0x244c, 0x2091, 0x8000, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0,
+	0x2430, 0x2011, 0x9555, 0x2009, 0x954e, 0x26a8, 0x211c, 0x2204,
+	0x201a, 0x8108, 0x8210, 0x00f0, 0x2416, 0xa685, 0x8030, 0x70c2,
 	0x681b, 0x0001, 0x2091, 0x4080, 0x7810, 0xa084, 0xffcf, 0x7812,
-	0x2091, 0x8001, 0xa006, 0x2009, 0x9275, 0x200a, 0x203a, 0x007c,
-	0x7810, 0xc0ad, 0x7812, 0x0078, 0x2454, 0x263a, 0x1078, 0x253f,
-	0x00c0, 0x254e, 0x786c, 0xa065, 0x00c0, 0x23eb, 0x2091, 0x8000,
-	0x7810, 0xa084, 0xffcf, 0x86ff, 0x0040, 0x244f, 0xc0ad, 0x7812,
-	0x2091, 0x8001, 0x0078, 0x254e, 0x2091, 0x8000, 0x7007, 0x0004,
-	0x7994, 0x70d4, 0xa102, 0x0048, 0x2465, 0x0040, 0x246f, 0x7b90,
-	0xa302, 0x00c0, 0x246f, 0x0078, 0x2468, 0x8002, 0x00c0, 0x246f,
+	0x2091, 0x8001, 0xa006, 0x2009, 0x9575, 0x200a, 0x203a, 0x007c,
+	0x7810, 0xc0ad, 0x7812, 0x0078, 0x244c, 0x263a, 0x1078, 0x2537,
+	0x00c0, 0x255a, 0x786c, 0xa065, 0x00c0, 0x23de, 0x2091, 0x8000,
+	0x7810, 0xa084, 0xffcf, 0x86ff, 0x0040, 0x2447, 0xc0ad, 0x7812,
+	0x2091, 0x8001, 0x0078, 0x255a, 0x2091, 0x8000, 0x7007, 0x0004,
+	0x7994, 0x70d4, 0xa102, 0x0048, 0x245d, 0x0040, 0x2467, 0x7b90,
+	0xa302, 0x00c0, 0x2467, 0x0078, 0x2460, 0x8002, 0x00c0, 0x2467,
 	0x263a, 0x7810, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x007c, 0xa184,
-	0xff00, 0x0040, 0x247c, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004,
-	0x8007, 0xa100, 0x0078, 0x247f, 0x8107, 0x8004, 0x8004, 0x7a9c,
+	0xff00, 0x0040, 0x2474, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004,
+	0x8007, 0xa100, 0x0078, 0x2477, 0x8107, 0x8004, 0x8004, 0x7a9c,
 	0xa210, 0x721a, 0x7a98, 0xa006, 0xa211, 0x721e, 0xd4c4, 0x0040,
-	0x248f, 0x7aa4, 0xa211, 0x7222, 0x7aa0, 0xa211, 0x7226, 0x20a1,
-	0x0030, 0x7003, 0x0000, 0x2009, 0x9254, 0x260a, 0x8109, 0x2198,
-	0x2104, 0xd084, 0x0040, 0x249d, 0x8633, 0xa6b0, 0x0002, 0x26a8,
+	0x2487, 0x7aa4, 0xa211, 0x7222, 0x7aa0, 0xa211, 0x7226, 0x20a1,
+	0x0030, 0x7003, 0x0000, 0x2009, 0x9554, 0x260a, 0x8109, 0x2198,
+	0x2104, 0xd084, 0x0040, 0x2495, 0x8633, 0xa6b0, 0x0002, 0x26a8,
 	0x53a6, 0x8603, 0x7012, 0x7007, 0x0001, 0x7990, 0x7894, 0x8000,
-	0xa10a, 0x00c8, 0x24ac, 0xa006, 0x2028, 0x7974, 0xa184, 0xff00,
-	0x0040, 0x24bb, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007,
-	0xa100, 0x0078, 0x24be, 0x8107, 0x8004, 0x8004, 0x797c, 0xa108,
-	0x7a78, 0xa006, 0xa211, 0xd4c4, 0x0040, 0x24ca, 0x7b84, 0xa319,
-	0x7c80, 0xa421, 0x7008, 0xd0fc, 0x0040, 0x24ca, 0xa084, 0x01e0,
-	0x0040, 0x24ef, 0x7d10, 0x2031, 0x9254, 0x2634, 0x78a8, 0x8000,
-	0x78aa, 0xd08c, 0x00c0, 0x24e4, 0x7007, 0x0006, 0x7004, 0xd094,
-	0x00c0, 0x24de, 0x0078, 0x2456, 0x2069, 0x4a47, 0x206b, 0x0003,
-	0x78ac, 0xa085, 0x0300, 0x78ae, 0xa006, 0x0078, 0x24f8, 0x2030,
+	0xa10a, 0x00c8, 0x24a4, 0xa006, 0x2028, 0x7974, 0xa184, 0xff00,
+	0x0040, 0x24b3, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004, 0x8007,
+	0xa100, 0x0078, 0x24b6, 0x8107, 0x8004, 0x8004, 0x797c, 0xa108,
+	0x7a78, 0xa006, 0xa211, 0xd4c4, 0x0040, 0x24c2, 0x7b84, 0xa319,
+	0x7c80, 0xa421, 0x7008, 0xd0fc, 0x0040, 0x24c2, 0xa084, 0x01e0,
+	0x0040, 0x24e7, 0x7d10, 0x2031, 0x9554, 0x2634, 0x78a8, 0x8000,
+	0x78aa, 0xd08c, 0x00c0, 0x24dc, 0x7007, 0x0006, 0x7004, 0xd094,
+	0x00c0, 0x24d6, 0x0078, 0x244e, 0x2069, 0x4d47, 0x206b, 0x0003,
+	0x78ac, 0xa085, 0x0300, 0x78ae, 0xa006, 0x0078, 0x24f0, 0x2030,
 	0x75d6, 0x2091, 0x4080, 0x7d96, 0x7d10, 0xa5ac, 0xffcf, 0x7d12,
 	0x2091, 0x8001, 0x78aa, 0x7007, 0x0006, 0x263a, 0x7003, 0x0001,
-	0x711a, 0x721e, 0xd5c4, 0x0040, 0x2507, 0x7322, 0x7426, 0x007c,
-	0x6084, 0xa086, 0x0103, 0x00c0, 0x252b, 0x6114, 0x6018, 0xa105,
-	0x00c0, 0x252b, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0, 0x252b,
+	0x711a, 0x721e, 0xd5c4, 0x0040, 0x24ff, 0x7322, 0x7426, 0x007c,
+	0x6084, 0xa086, 0x0103, 0x00c0, 0x2523, 0x6114, 0x6018, 0xa105,
+	0x00c0, 0x2523, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0, 0x2523,
 	0x600c, 0x70c6, 0x6010, 0x70ca, 0x70c3, 0x8020, 0x681b, 0x0001,
-	0x2091, 0x4080, 0x1078, 0x203d, 0x0068, 0x252a, 0x786c, 0xa065,
-	0x00c0, 0x2508, 0x007c, 0x1078, 0x253f, 0x00c0, 0x254e, 0x786c,
-	0xa065, 0x00c0, 0x2508, 0x0078, 0x254e, 0x1078, 0x253f, 0x00c0,
-	0x254e, 0x786c, 0xa065, 0x00c0, 0x2535, 0x0078, 0x254e, 0x1078,
-	0x2554, 0x00c0, 0x2546, 0xa085, 0x0001, 0x007c, 0x1078, 0x2563,
-	0x00c0, 0x254c, 0x2041, 0x0001, 0x7d10, 0x007c, 0x88ff, 0x0040,
-	0x2553, 0x2091, 0x4080, 0x007c, 0x7b90, 0x7994, 0x70d4, 0xa102,
-	0x00c0, 0x255d, 0xa385, 0x0000, 0x007c, 0x0048, 0x2561, 0xa302,
-	0x007c, 0x8002, 0x007c, 0x7810, 0xd0ec, 0x0040, 0x257b, 0x0e7e,
-	0x2091, 0x8000, 0x2071, 0x0020, 0x7004, 0xa005, 0x00c0, 0x2578,
-	0x7008, 0x0e7f, 0xa086, 0x0008, 0x0040, 0x257b, 0x0078, 0x25cc,
-	0x0e7f, 0x0078, 0x25cc, 0xa184, 0xff00, 0x0040, 0x2588, 0x810f,
-	0x810c, 0x810c, 0x8004, 0x8004, 0x8007, 0xa100, 0x0078, 0x258b,
-	0x8107, 0x8004, 0x8004, 0x7a9c, 0x7b98, 0x7ca4, 0x7da0, 0xa210,
-	0xa006, 0xa319, 0xa421, 0xa529, 0x2009, 0x0018, 0x6028, 0xa005,
-	0x0040, 0x259c, 0x2009, 0x0040, 0x1078, 0x1d92, 0x0040, 0x25be,
-	0x78a8, 0x8000, 0x78aa, 0xd08c, 0x00c0, 0x25cc, 0x6014, 0xd0fc,
-	0x00c0, 0x25ae, 0x2069, 0x4a40, 0x0078, 0x25b0, 0x2069, 0x4a80,
-	0x2091, 0x8000, 0x681f, 0x0003, 0x78ab, 0x0000, 0x78ac, 0xa085,
-	0x0300, 0x78ae, 0x2091, 0x8001, 0x0078, 0x25cc, 0x78ab, 0x0000,
-	0x1078, 0x203d, 0x7990, 0x7894, 0x8000, 0xa10a, 0x00c8, 0x25c9,
-	0xa006, 0x7896, 0x70d6, 0xa006, 0x2071, 0x0010, 0x2091, 0x8001,
-	0x007c, 0x2138, 0xd7fc, 0x00c0, 0x25d9, 0x2009, 0x4a59, 0x0078,
-	0x25db, 0x2009, 0x4a99, 0x2091, 0x8000, 0x200a, 0x0f7e, 0xd7fc,
-	0x00c0, 0x25f2, 0x2009, 0x4a40, 0x2001, 0x4a04, 0x2004, 0xd0ec,
-	0x0040, 0x25ee, 0x2079, 0x0100, 0x0078, 0x25f6, 0x2079, 0x0200,
-	0x0078, 0x25f6, 0x2009, 0x4a80, 0x2079, 0x0100, 0x2104, 0xa086,
-	0x0000, 0x00c0, 0x260f, 0xd7fc, 0x00c0, 0x2602, 0x2009, 0x4a45,
-	0x0078, 0x2604, 0x2009, 0x4a85, 0x2104, 0xa005, 0x00c0, 0x260f,
-	0x7830, 0xa084, 0x00c0, 0x00c0, 0x260f, 0x781b, 0x0045, 0x0f7f,
-	0x007c, 0x2009, 0x0002, 0x2069, 0x4a00, 0x6810, 0xd0ec, 0x00c0,
-	0x2672, 0x2071, 0x4a80, 0x2079, 0x0100, 0x2021, 0x4cbf, 0x784b,
-	0x000f, 0x2019, 0x4205, 0xd184, 0x0040, 0x2632, 0x6810, 0xd0ec,
-	0x0040, 0x262e, 0x20a1, 0x012b, 0x0078, 0x2634, 0x20a1, 0x022b,
-	0x0078, 0x2634, 0x20a1, 0x012b, 0x2304, 0xa005, 0x0040, 0x2641,
-	0x789a, 0x8318, 0x23ac, 0x8318, 0x2398, 0x53a6, 0x3318, 0x0078,
-	0x2634, 0x789b, 0x0020, 0x20a9, 0x0010, 0x78af, 0x0000, 0x78af,
-	0x8020, 0x00f0, 0x2645, 0x7003, 0x0000, 0x017e, 0xd18c, 0x2009,
-	0x0000, 0x0040, 0x2654, 0xc1bd, 0x1078, 0x283d, 0x017f, 0x7020,
-	0xa084, 0x000f, 0x007e, 0x6814, 0xd0e4, 0x007f, 0x00c0, 0x2664,
-	0xa085, 0x6340, 0x0078, 0x2666, 0xa085, 0x62c0, 0x7806, 0x780f,
-	0x9200, 0x7843, 0x00d8, 0x7853, 0x0080, 0x780b, 0x0008, 0x7456,
-	0x7053, 0x0000, 0x8109, 0x0040, 0x2685, 0x2071, 0x4a40, 0x6810,
-	0xd0ec, 0x0040, 0x267f, 0x2079, 0x0100, 0x0078, 0x2681, 0x2079,
-	0x0200, 0x2021, 0x4abf, 0x0078, 0x261f, 0x007c, 0x017e, 0xd1bc,
-	0x00c0, 0x269a, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f,
-	0x0040, 0x2696, 0x2011, 0x0101, 0x0078, 0x269c, 0x2011, 0x0201,
-	0x0078, 0x269c, 0x2011, 0x0101, 0xa18c, 0x000f, 0x2204, 0xa084,
-	0xfff0, 0xa105, 0x2012, 0x017f, 0x1078, 0x283d, 0x007c, 0xd3fc,
-	0x00c0, 0x26ba, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f,
-	0x0040, 0x26b6, 0x2011, 0x0101, 0x0078, 0x26bc, 0x2011, 0x0201,
-	0x0078, 0x26bc, 0x2011, 0x0101, 0x20a9, 0x0009, 0x810b, 0x00f0,
-	0x26be, 0xa18c, 0x0e00, 0x2204, 0xa084, 0xf1ff, 0xa105, 0x2012,
-	0x007c, 0x2019, 0x0002, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x0040,
-	0x26d6, 0x8319, 0x2009, 0x0101, 0x0078, 0x26d8, 0x2009, 0x0101,
-	0x20a9, 0x0005, 0x8213, 0x00f0, 0x26da, 0xa294, 0x00e0, 0x2104,
-	0xa084, 0xff1f, 0xa205, 0x200a, 0x8319, 0x0040, 0x26eb, 0x2009,
-	0x0201, 0x0078, 0x26d8, 0x007c, 0xd3fc, 0x00c0, 0x26ff, 0x007e,
-	0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x26fb, 0x2011,
-	0x0101, 0x0078, 0x2701, 0x2011, 0x0201, 0x0078, 0x2701, 0x2011,
-	0x0101, 0x20a9, 0x000c, 0x810b, 0x00f0, 0x2703, 0xa18c, 0xf000,
-	0x2204, 0xa084, 0x0fff, 0xa105, 0x2012, 0x007c, 0xd3fc, 0x00c0,
-	0x2721, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040,
-	0x271d, 0x2011, 0x0102, 0x0078, 0x2723, 0x2011, 0x0202, 0x0078,
-	0x2723, 0x2011, 0x0102, 0x2204, 0xa084, 0xffcf, 0xa105, 0x2012,
-	0x007c, 0x0c7e, 0xd1bc, 0x00c0, 0x273d, 0x007e, 0x2001, 0x4a04,
-	0x2004, 0xd0ec, 0x007f, 0x0040, 0x2739, 0x2061, 0x0100, 0x0078,
-	0x273f, 0x2061, 0x0200, 0x0078, 0x273f, 0x2061, 0x0100, 0xc1bc,
-	0x8103, 0x8003, 0xa080, 0x0020, 0x609a, 0x62ac, 0x63ac, 0x0c7f,
-	0x007c, 0x0c7e, 0xd1bc, 0x00c0, 0x275d, 0x007e, 0x2001, 0x4a04,
-	0x2004, 0xd0ec, 0x007f, 0x0040, 0x2759, 0x2061, 0x0100, 0x0078,
-	0x275f, 0x2061, 0x0200, 0x0078, 0x275f, 0x2061, 0x0100, 0xc1bc,
-	0x8103, 0x8003, 0xa080, 0x0022, 0x609a, 0x60a4, 0xa084, 0xffdf,
-	0x60ae, 0x0c7f, 0x007c, 0x0c7e, 0xd1bc, 0x00c0, 0x277f, 0x007e,
-	0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x277b, 0x2061,
-	0x0100, 0x0078, 0x2781, 0x2061, 0x0200, 0x0078, 0x2781, 0x2061,
-	0x0100, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0022, 0x609a, 0x60a4,
-	0xa085, 0x0020, 0x60ae, 0x0c7f, 0x007c, 0x0c7e, 0xd1bc, 0x00c0,
-	0x27a1, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040,
-	0x279d, 0x2061, 0x0100, 0x0078, 0x27a3, 0x2061, 0x0200, 0x0078,
-	0x27a3, 0x2061, 0x0100, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0020,
-	0x609a, 0x60a4, 0xa28c, 0x0020, 0x0040, 0x27b1, 0xc2ac, 0xa39d,
-	0x4000, 0xc3fc, 0xd3b4, 0x00c0, 0x27b6, 0xc3fd, 0x62ae, 0x2010,
-	0x60a4, 0x63ae, 0x2018, 0x0c7f, 0x007c, 0x2091, 0x8000, 0x0c7e,
-	0x0e7e, 0x6818, 0xa005, 0x0040, 0x281b, 0xd1fc, 0x0040, 0x27cc,
-	0x2061, 0x91d0, 0x0078, 0x27ce, 0x2061, 0x90c0, 0x1078, 0x2823,
-	0x0040, 0x2801, 0x20a9, 0x0101, 0xd1fc, 0x0040, 0x27db, 0x2061,
-	0x90d0, 0x0078, 0x27dd, 0x2061, 0x8fc0, 0x0c7e, 0x1078, 0x2823,
-	0x0040, 0x27e8, 0x0c7f, 0x8c60, 0x00f0, 0x27dd, 0x0078, 0x281b,
-	0x007f, 0xd1fc, 0x0040, 0x27f2, 0xa082, 0x90d0, 0x2071, 0x4a80,
-	0x0078, 0x27f6, 0xa082, 0x8fc0, 0x2071, 0x4a40, 0x707a, 0x7176,
-	0x2001, 0x0004, 0x7066, 0x7083, 0x000f, 0x1078, 0x25d1, 0x0078,
-	0x2817, 0xd1fc, 0x00c0, 0x2808, 0x2071, 0x4a40, 0x0078, 0x280a,
-	0x2071, 0x4a80, 0x6020, 0xc0dd, 0x6022, 0x7176, 0x2c00, 0x707e,
-	0x2001, 0x0006, 0x7066, 0x7083, 0x000f, 0x1078, 0x25d1, 0x2001,
-	0x0000, 0x0078, 0x281d, 0x2001, 0x0001, 0x2091, 0x8001, 0xa005,
-	0x0e7f, 0x0c7f, 0x007c, 0x2c04, 0xa005, 0x0040, 0x283a, 0x2060,
-	0x6010, 0xa306, 0x00c0, 0x2837, 0x600c, 0xa206, 0x00c0, 0x2837,
-	0x6014, 0xa106, 0x00c0, 0x2837, 0xa006, 0x0078, 0x283c, 0x6000,
-	0x0078, 0x2824, 0xa085, 0x0001, 0x007c, 0x0f7e, 0x0e7e, 0x017e,
-	0xd1bc, 0x00c0, 0x2855, 0x2079, 0x4a40, 0x007e, 0x2001, 0x4a04,
-	0x2004, 0xd0ec, 0x007f, 0x0040, 0x2851, 0x2071, 0x0100, 0x0078,
-	0x2859, 0x2071, 0x0200, 0x0078, 0x2859, 0x2079, 0x4a80, 0x2071,
-	0x0100, 0x7920, 0xa18c, 0x000f, 0x70ec, 0xd0c4, 0x00c0, 0x2863,
-	0x017f, 0x0078, 0x287e, 0x810b, 0x810b, 0x810b, 0x810b, 0x007f,
-	0xd0bc, 0x00c0, 0x287b, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec,
-	0x007f, 0x0040, 0x2877, 0xa18d, 0x0f00, 0x0078, 0x287d, 0xa18d,
-	0x0f00, 0x0078, 0x287d, 0xa18d, 0x0800, 0x2104, 0x0e7f, 0x0f7f,
-	0x007c, 0x0e7e, 0x2001, 0x4a01, 0x2004, 0xd0ac, 0x00c0, 0x28ea,
-	0x68e4, 0xd0ac, 0x0040, 0x28ea, 0xa084, 0x0006, 0x00c0, 0x28ea,
-	0x6014, 0xd0fc, 0x00c0, 0x2898, 0x2071, 0x4ec0, 0x0078, 0x289a,
-	0x2071, 0x4f40, 0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003,
-	0xae70, 0x7004, 0xa084, 0x000a, 0x00c0, 0x28ea, 0x7108, 0xa194,
-	0xff00, 0x0040, 0x28ea, 0xa18c, 0x00ff, 0x2001, 0x000a, 0xa106,
-	0x0040, 0x28cd, 0x2001, 0x000c, 0xa106, 0x0040, 0x28d1, 0x2001,
-	0x0012, 0xa106, 0x0040, 0x28d5, 0x2001, 0x0014, 0xa106, 0x0040,
-	0x28d9, 0x2001, 0x0019, 0xa106, 0x0040, 0x28dd, 0x2001, 0x0032,
-	0xa106, 0x0040, 0x28e1, 0x0078, 0x28e5, 0x2009, 0x000c, 0x0078,
-	0x28e7, 0x2009, 0x0012, 0x0078, 0x28e7, 0x2009, 0x0014, 0x0078,
-	0x28e7, 0x2009, 0x0019, 0x0078, 0x28e7, 0x2009, 0x0020, 0x0078,
-	0x28e7, 0x2009, 0x003f, 0x0078, 0x28e7, 0x2011, 0x0000, 0x2100,
-	0xa205, 0x700a, 0x0e7f, 0x007c, 0x0068, 0x28ec, 0x2091, 0x8000,
-	0x2071, 0x0000, 0x007e, 0x7018, 0xd084, 0x00c0, 0x28f3, 0x007f,
+	0x2091, 0x4080, 0x1078, 0x2026, 0x0068, 0x2522, 0x786c, 0xa065,
+	0x00c0, 0x2500, 0x007c, 0x1078, 0x2537, 0x00c0, 0x255a, 0x786c,
+	0xa065, 0x00c0, 0x2500, 0x0078, 0x255a, 0x1078, 0x2537, 0x00c0,
+	0x255a, 0x786c, 0xa065, 0x00c0, 0x252d, 0x0078, 0x255a, 0x6084,
+	0xa086, 0x0103, 0x00c0, 0x254b, 0x6018, 0xc0fc, 0x601a, 0xa086,
+	0x0004, 0x00c0, 0x254b, 0x7804, 0xd0a4, 0x0040, 0x254b, 0x1078,
+	0x2026, 0xa006, 0x007c, 0x1078, 0x2560, 0x00c0, 0x2552, 0xa085,
+	0x0001, 0x007c, 0x1078, 0x256f, 0x00c0, 0x2558, 0x2041, 0x0001,
+	0x7d10, 0x007c, 0x88ff, 0x0040, 0x255f, 0x2091, 0x4080, 0x007c,
+	0x7b90, 0x7994, 0x70d4, 0xa102, 0x00c0, 0x2569, 0xa385, 0x0000,
+	0x007c, 0x0048, 0x256d, 0xa302, 0x007c, 0x8002, 0x007c, 0x7810,
+	0xd0ec, 0x0040, 0x2587, 0x0e7e, 0x2091, 0x8000, 0x2071, 0x0020,
+	0x7004, 0xa005, 0x00c0, 0x2584, 0x7008, 0x0e7f, 0xa086, 0x0008,
+	0x0040, 0x2587, 0x0078, 0x25d8, 0x0e7f, 0x0078, 0x25d8, 0xa184,
+	0xff00, 0x0040, 0x2594, 0x810f, 0x810c, 0x810c, 0x8004, 0x8004,
+	0x8007, 0xa100, 0x0078, 0x2597, 0x8107, 0x8004, 0x8004, 0x7a9c,
+	0x7b98, 0x7ca4, 0x7da0, 0xa210, 0xa006, 0xa319, 0xa421, 0xa529,
+	0x2009, 0x0018, 0x6028, 0xa005, 0x0040, 0x25a8, 0x2009, 0x0040,
+	0x1078, 0x1d5b, 0x0040, 0x25ca, 0x78a8, 0x8000, 0x78aa, 0xd08c,
+	0x00c0, 0x25d8, 0x6014, 0xd0fc, 0x00c0, 0x25ba, 0x2069, 0x4d40,
+	0x0078, 0x25bc, 0x2069, 0x4d80, 0x2091, 0x8000, 0x681f, 0x0003,
+	0x78ab, 0x0000, 0x78ac, 0xa085, 0x0300, 0x78ae, 0x2091, 0x8001,
+	0x0078, 0x25d8, 0x78ab, 0x0000, 0x1078, 0x2026, 0x7990, 0x7894,
+	0x8000, 0xa10a, 0x00c8, 0x25d5, 0xa006, 0x7896, 0x70d6, 0xa006,
+	0x2071, 0x0010, 0x2091, 0x8001, 0x007c, 0x2138, 0xd7fc, 0x00c0,
+	0x25e5, 0x2009, 0x4d59, 0x0078, 0x25e7, 0x2009, 0x4d99, 0x2091,
+	0x8000, 0x200a, 0x0f7e, 0xd7fc, 0x00c0, 0x25fe, 0x2009, 0x4d40,
+	0x2001, 0x4d04, 0x2004, 0xd0ec, 0x0040, 0x25fa, 0x2079, 0x0100,
+	0x0078, 0x2602, 0x2079, 0x0200, 0x0078, 0x2602, 0x2009, 0x4d80,
+	0x2079, 0x0100, 0x2104, 0xa086, 0x0000, 0x00c0, 0x261b, 0xd7fc,
+	0x00c0, 0x260e, 0x2009, 0x4d45, 0x0078, 0x2610, 0x2009, 0x4d85,
+	0x2104, 0xa005, 0x00c0, 0x261b, 0x7830, 0xa084, 0x00c0, 0x00c0,
+	0x261b, 0x781b, 0x0045, 0x0f7f, 0x007c, 0x2009, 0x0002, 0x2069,
+	0x4d00, 0x6810, 0xd0ec, 0x00c0, 0x267e, 0x2071, 0x4d80, 0x2079,
+	0x0100, 0x2021, 0x4fbf, 0x784b, 0x000f, 0x2019, 0x43d2, 0xd184,
+	0x0040, 0x263e, 0x6810, 0xd0ec, 0x0040, 0x263a, 0x20a1, 0x012b,
+	0x0078, 0x2640, 0x20a1, 0x022b, 0x0078, 0x2640, 0x20a1, 0x012b,
+	0x2304, 0xa005, 0x0040, 0x264d, 0x789a, 0x8318, 0x23ac, 0x8318,
+	0x2398, 0x53a6, 0x3318, 0x0078, 0x2640, 0x789b, 0x0020, 0x20a9,
+	0x0010, 0x78af, 0x0000, 0x78af, 0x8020, 0x00f0, 0x2651, 0x7003,
+	0x0000, 0x017e, 0xd18c, 0x2009, 0x0000, 0x0040, 0x2660, 0xc1bd,
+	0x1078, 0x2849, 0x017f, 0x7020, 0xa084, 0x000f, 0x007e, 0x6814,
+	0xd0e4, 0x007f, 0x00c0, 0x2670, 0xa085, 0x6340, 0x0078, 0x2672,
+	0xa085, 0x62c0, 0x7806, 0x780f, 0x9200, 0x7843, 0x00d8, 0x7853,
+	0x0080, 0x780b, 0x0008, 0x7456, 0x7053, 0x0000, 0x8109, 0x0040,
+	0x2691, 0x2071, 0x4d40, 0x6810, 0xd0ec, 0x0040, 0x268b, 0x2079,
+	0x0100, 0x0078, 0x268d, 0x2079, 0x0200, 0x2021, 0x4dbf, 0x0078,
+	0x262b, 0x007c, 0x017e, 0xd1bc, 0x00c0, 0x26a6, 0x007e, 0x2001,
+	0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x26a2, 0x2011, 0x0101,
+	0x0078, 0x26a8, 0x2011, 0x0201, 0x0078, 0x26a8, 0x2011, 0x0101,
+	0xa18c, 0x000f, 0x2204, 0xa084, 0xfff0, 0xa105, 0x2012, 0x017f,
+	0x1078, 0x2849, 0x007c, 0xd3fc, 0x00c0, 0x26c6, 0x007e, 0x2001,
+	0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x26c2, 0x2011, 0x0101,
+	0x0078, 0x26c8, 0x2011, 0x0201, 0x0078, 0x26c8, 0x2011, 0x0101,
+	0x20a9, 0x0009, 0x810b, 0x00f0, 0x26ca, 0xa18c, 0x0e00, 0x2204,
+	0xa084, 0xf1ff, 0xa105, 0x2012, 0x007c, 0x2019, 0x0002, 0x2001,
+	0x4d04, 0x2004, 0xd0ec, 0x0040, 0x26e2, 0x8319, 0x2009, 0x0101,
+	0x0078, 0x26e4, 0x2009, 0x0101, 0x20a9, 0x0005, 0x8213, 0x00f0,
+	0x26e6, 0xa294, 0x00e0, 0x2104, 0xa084, 0xff1f, 0xa205, 0x200a,
+	0x8319, 0x0040, 0x26f7, 0x2009, 0x0201, 0x0078, 0x26e4, 0x007c,
+	0xd3fc, 0x00c0, 0x270b, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x007f, 0x0040, 0x2707, 0x2011, 0x0101, 0x0078, 0x270d, 0x2011,
+	0x0201, 0x0078, 0x270d, 0x2011, 0x0101, 0x20a9, 0x000c, 0x810b,
+	0x00f0, 0x270f, 0xa18c, 0xf000, 0x2204, 0xa084, 0x0fff, 0xa105,
+	0x2012, 0x007c, 0xd3fc, 0x00c0, 0x272d, 0x007e, 0x2001, 0x4d04,
+	0x2004, 0xd0ec, 0x007f, 0x0040, 0x2729, 0x2011, 0x0102, 0x0078,
+	0x272f, 0x2011, 0x0202, 0x0078, 0x272f, 0x2011, 0x0102, 0x2204,
+	0xa084, 0xffcf, 0xa105, 0x2012, 0x007c, 0x0c7e, 0xd1bc, 0x00c0,
+	0x2749, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040,
+	0x2745, 0x2061, 0x0100, 0x0078, 0x274b, 0x2061, 0x0200, 0x0078,
+	0x274b, 0x2061, 0x0100, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0020,
+	0x609a, 0x62ac, 0x63ac, 0x0c7f, 0x007c, 0x0c7e, 0xd1bc, 0x00c0,
+	0x2769, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040,
+	0x2765, 0x2061, 0x0100, 0x0078, 0x276b, 0x2061, 0x0200, 0x0078,
+	0x276b, 0x2061, 0x0100, 0xc1bc, 0x8103, 0x8003, 0xa080, 0x0022,
+	0x609a, 0x60a4, 0xa084, 0xffdf, 0x60ae, 0x0c7f, 0x007c, 0x0c7e,
+	0xd1bc, 0x00c0, 0x278b, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x007f, 0x0040, 0x2787, 0x2061, 0x0100, 0x0078, 0x278d, 0x2061,
+	0x0200, 0x0078, 0x278d, 0x2061, 0x0100, 0xc1bc, 0x8103, 0x8003,
+	0xa080, 0x0022, 0x609a, 0x60a4, 0xa085, 0x0020, 0x60ae, 0x0c7f,
+	0x007c, 0x0c7e, 0xd1bc, 0x00c0, 0x27ad, 0x007e, 0x2001, 0x4d04,
+	0x2004, 0xd0ec, 0x007f, 0x0040, 0x27a9, 0x2061, 0x0100, 0x0078,
+	0x27af, 0x2061, 0x0200, 0x0078, 0x27af, 0x2061, 0x0100, 0xc1bc,
+	0x8103, 0x8003, 0xa080, 0x0020, 0x609a, 0x60a4, 0xa28c, 0x0020,
+	0x0040, 0x27bd, 0xc2ac, 0xa39d, 0x4000, 0xc3fc, 0xd3b4, 0x00c0,
+	0x27c2, 0xc3fd, 0x62ae, 0x2010, 0x60a4, 0x63ae, 0x2018, 0x0c7f,
+	0x007c, 0x2091, 0x8000, 0x0c7e, 0x0e7e, 0x6818, 0xa005, 0x0040,
+	0x2827, 0xd1fc, 0x0040, 0x27d8, 0x2061, 0x94d0, 0x0078, 0x27da,
+	0x2061, 0x93c0, 0x1078, 0x282f, 0x0040, 0x280d, 0x20a9, 0x0101,
+	0xd1fc, 0x0040, 0x27e7, 0x2061, 0x93d0, 0x0078, 0x27e9, 0x2061,
+	0x92c0, 0x0c7e, 0x1078, 0x282f, 0x0040, 0x27f4, 0x0c7f, 0x8c60,
+	0x00f0, 0x27e9, 0x0078, 0x2827, 0x007f, 0xd1fc, 0x0040, 0x27fe,
+	0xa082, 0x93d0, 0x2071, 0x4d80, 0x0078, 0x2802, 0xa082, 0x92c0,
+	0x2071, 0x4d40, 0x707a, 0x7176, 0x2001, 0x0004, 0x7066, 0x7083,
+	0x000f, 0x1078, 0x25dd, 0x0078, 0x2823, 0xd1fc, 0x00c0, 0x2814,
+	0x2071, 0x4d40, 0x0078, 0x2816, 0x2071, 0x4d80, 0x6020, 0xc0dd,
+	0x6022, 0x7176, 0x2c00, 0x707e, 0x2001, 0x0006, 0x7066, 0x7083,
+	0x000f, 0x1078, 0x25dd, 0x2001, 0x0000, 0x0078, 0x2829, 0x2001,
+	0x0001, 0x2091, 0x8001, 0xa005, 0x0e7f, 0x0c7f, 0x007c, 0x2c04,
+	0xa005, 0x0040, 0x2846, 0x2060, 0x6010, 0xa306, 0x00c0, 0x2843,
+	0x600c, 0xa206, 0x00c0, 0x2843, 0x6014, 0xa106, 0x00c0, 0x2843,
+	0xa006, 0x0078, 0x2848, 0x6000, 0x0078, 0x2830, 0xa085, 0x0001,
+	0x007c, 0x0f7e, 0x0e7e, 0x017e, 0xd1bc, 0x00c0, 0x2861, 0x2079,
+	0x4d40, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040,
+	0x285d, 0x2071, 0x0100, 0x0078, 0x2865, 0x2071, 0x0200, 0x0078,
+	0x2865, 0x2079, 0x4d80, 0x2071, 0x0100, 0x7920, 0xa18c, 0x000f,
+	0x70ec, 0xd0c4, 0x00c0, 0x286f, 0x017f, 0x0078, 0x288a, 0x810b,
+	0x810b, 0x810b, 0x810b, 0x007f, 0xd0bc, 0x00c0, 0x2887, 0x007e,
+	0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x2883, 0xa18d,
+	0x0f00, 0x0078, 0x2889, 0xa18d, 0x0f00, 0x0078, 0x2889, 0xa18d,
+	0x0800, 0x2104, 0x0e7f, 0x0f7f, 0x007c, 0x0e7e, 0x2001, 0x4d01,
+	0x2004, 0xd0ac, 0x00c0, 0x290a, 0x68e4, 0xd0ac, 0x0040, 0x290a,
+	0xa084, 0x0006, 0x00c0, 0x290a, 0x6014, 0xd0fc, 0x00c0, 0x28a4,
+	0x2071, 0x51c0, 0x0078, 0x28a6, 0x2071, 0x5240, 0x8007, 0xa084,
+	0x000f, 0x8003, 0x8003, 0x8003, 0xae70, 0x7004, 0xa084, 0x000a,
+	0x00c0, 0x290a, 0x7108, 0xa194, 0xff00, 0x0040, 0x290a, 0xa18c,
+	0x00ff, 0x2001, 0x000a, 0xa106, 0x0040, 0x28d9, 0x2001, 0x000c,
+	0xa106, 0x0040, 0x28dd, 0x2001, 0x0012, 0xa106, 0x0040, 0x28e1,
+	0x2001, 0x0014, 0xa106, 0x0040, 0x28e5, 0x2001, 0x0019, 0xa106,
+	0x0040, 0x28e9, 0x2001, 0x0032, 0xa106, 0x0040, 0x28ed, 0x0078,
+	0x28f1, 0x2009, 0x000c, 0x0078, 0x28f3, 0x2009, 0x0012, 0x0078,
+	0x28f3, 0x2009, 0x0014, 0x0078, 0x28f3, 0x2009, 0x0019, 0x0078,
+	0x28f3, 0x2009, 0x0020, 0x0078, 0x28f3, 0x2009, 0x003f, 0x0078,
+	0x28f3, 0x2011, 0x0000, 0x2100, 0xa205, 0x700a, 0x2071, 0x4d00,
+	0x7004, 0xd0bc, 0x0040, 0x290a, 0x6014, 0xd0fc, 0x00c0, 0x2905,
+	0x70ea, 0x2071, 0x4d40, 0x0078, 0x2908, 0x70ee, 0x2071, 0x4d80,
+	0x701f, 0x800f, 0x0e7f, 0x007c, 0x0068, 0x290c, 0x2091, 0x8000,
+	0x2071, 0x0000, 0x007e, 0x7018, 0xd084, 0x00c0, 0x2913, 0x007f,
 	0x2071, 0x0010, 0x70ca, 0x007f, 0x70c6, 0x70c3, 0x8002, 0x70db,
-	0x0809, 0x70df, 0x0000, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091,
-	0x4080, 0x0078, 0x2909, 0x7f3c, 0x7e58, 0x7c30, 0x7d38, 0x78a0,
+	0x080d, 0x70df, 0x0008, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091,
+	0x4080, 0x0078, 0x2929, 0x7f3c, 0x7e58, 0x7c30, 0x7d38, 0x78a0,
 	0x708e, 0x7592, 0x7496, 0x769a, 0x779e, 0xa594, 0x003f, 0xd4f4,
-	0x0040, 0x2920, 0xa784, 0x007d, 0x00c0, 0x417b, 0x1078, 0x28ec,
-	0xa49c, 0x000f, 0xa382, 0x0004, 0x0050, 0x292b, 0xa3a6, 0x0007,
-	0x00c0, 0x28ec, 0x2418, 0x8507, 0xa084, 0x000f, 0x0079, 0x2930,
-	0x2f45, 0x3035, 0x3060, 0x32c1, 0x363b, 0x36a1, 0x3741, 0x37bd,
-	0x38a1, 0x398a, 0x2943, 0x2940, 0x2d2a, 0x2e43, 0x360e, 0x2940,
-	0x1078, 0x28ec, 0x007c, 0xa006, 0x0078, 0x294d, 0x7808, 0xc08d,
+	0x0040, 0x2940, 0xa784, 0x007d, 0x00c0, 0x4348, 0x1078, 0x290c,
+	0xa49c, 0x000f, 0xa382, 0x0004, 0x0050, 0x294b, 0xa3a6, 0x0007,
+	0x00c0, 0x290c, 0x2418, 0x8507, 0xa084, 0x000f, 0x0079, 0x2950,
+	0x2fc6, 0x30b5, 0x30e0, 0x3341, 0x372a, 0x379f, 0x3853, 0x38cf,
+	0x39bd, 0x3aac, 0x2963, 0x2960, 0x2d99, 0x2eba, 0x36fb, 0x2960,
+	0x1078, 0x290c, 0x007c, 0xa006, 0x0078, 0x296d, 0x7808, 0xc08d,
 	0x780a, 0xa006, 0x7002, 0x704e, 0x7046, 0x70d2, 0x7060, 0xa005,
-	0x00c0, 0x2a64, 0x7064, 0xa084, 0x0007, 0x0079, 0x2957, 0x295f,
-	0x29cf, 0x29d8, 0x29e3, 0x29ee, 0x2a4a, 0x29f9, 0x29cf, 0x7830,
-	0xd0bc, 0x00c0, 0x2942, 0x71d4, 0xd1b4, 0x00c0, 0x29ac, 0x70a4,
-	0xa086, 0x0001, 0x0040, 0x2942, 0x70b4, 0xa06d, 0x6800, 0xa065,
-	0xa055, 0x789b, 0x0010, 0x6b0c, 0x7baa, 0x6808, 0xa045, 0x6d10,
-	0x6804, 0xa06d, 0xa05d, 0xa886, 0x0001, 0x0040, 0x2982, 0x69bc,
-	0x7daa, 0x79aa, 0x68c0, 0xa04d, 0x6e1c, 0x2001, 0x0010, 0x0078,
-	0x2bbd, 0x7060, 0xa005, 0x00c0, 0x2942, 0x0c7e, 0x0d7e, 0x70b4,
+	0x00c0, 0x2ad3, 0x7064, 0xa084, 0x0007, 0x0079, 0x2977, 0x297f,
+	0x29f2, 0x29fb, 0x2a06, 0x2a11, 0x2ab9, 0x2a1c, 0x29f2, 0x7830,
+	0xd0bc, 0x00c0, 0x2962, 0x71d4, 0xd1bc, 0x00c0, 0x2962, 0xd1b4,
+	0x00c0, 0x29cf, 0x70a4, 0xa086, 0x0001, 0x0040, 0x2962, 0x70b4,
 	0xa06d, 0x6800, 0xa065, 0xa055, 0x789b, 0x0010, 0x6b0c, 0x7baa,
 	0x6808, 0xa045, 0x6d10, 0x6804, 0xa06d, 0xa05d, 0xa886, 0x0001,
 	0x0040, 0x29a5, 0x69bc, 0x7daa, 0x79aa, 0x68c0, 0xa04d, 0x6e1c,
-	0x2001, 0x0020, 0x0078, 0x2bbd, 0x1078, 0x411c, 0x00c0, 0x2942,
-	0x781b, 0x005b, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6,
-	0x78de, 0x6898, 0x78d2, 0x78da, 0x7808, 0xc08d, 0x780a, 0x68bc,
-	0x7042, 0xc1b4, 0x71d6, 0x70b8, 0xa065, 0x68c0, 0x705a, 0x7003,
-	0x0002, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x007c, 0x1078,
-	0x411c, 0x00c0, 0x29d7, 0x781b, 0x0047, 0x7003, 0x0004, 0x007c,
-	0x1078, 0x411c, 0x00c0, 0x29e2, 0x2011, 0x000c, 0x1078, 0x2a09,
-	0x7003, 0x0004, 0x007c, 0x1078, 0x411c, 0x00c0, 0x29ed, 0x2011,
-	0x0006, 0x1078, 0x2a09, 0x7003, 0x0004, 0x007c, 0x1078, 0x411c,
-	0x00c0, 0x29f8, 0x2011, 0x000d, 0x1078, 0x2a09, 0x7003, 0x0004,
-	0x007c, 0x1078, 0x411c, 0x00c0, 0x2a08, 0x2011, 0x0006, 0x1078,
-	0x2a09, 0x707c, 0x707f, 0x0000, 0x2068, 0x704e, 0x7003, 0x0001,
-	0x007c, 0x7174, 0xc1fc, 0x8107, 0x7882, 0x789b, 0x0010, 0xa286,
-	0x000c, 0x00c0, 0x2a18, 0x7aaa, 0x2001, 0x0001, 0x0078, 0x2a2d,
-	0xa18c, 0x001f, 0xa18d, 0x00c0, 0x79aa, 0xa286, 0x000d, 0x0040,
-	0x2a26, 0x7aaa, 0x2001, 0x0002, 0x0078, 0x2a2d, 0x78ab, 0x0020,
-	0x7178, 0x79aa, 0x7aaa, 0x2001, 0x0004, 0x789b, 0x0060, 0x78aa,
-	0x785b, 0x0004, 0x781b, 0x0108, 0x1078, 0x4131, 0x7083, 0x000f,
-	0x70d4, 0xd0b4, 0x0040, 0x2a49, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8,
-	0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a,
-	0x0c7f, 0x007c, 0x1078, 0x411c, 0x00c0, 0x2942, 0x707c, 0x2068,
-	0x7774, 0x1078, 0x3fe1, 0x2c50, 0x1078, 0x41f0, 0x789b, 0x0010,
-	0x6814, 0xa084, 0x001f, 0xc0bd, 0x78aa, 0x6e1c, 0x2041, 0x0001,
-	0x2001, 0x0004, 0x0078, 0x2bc3, 0x1078, 0x411c, 0x00c0, 0x2942,
-	0x789b, 0x0010, 0x7060, 0x2068, 0x6f14, 0x70d4, 0xd0b4, 0x0040,
-	0x2a7e, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8, 0xa065, 0x6008, 0xa084,
-	0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f, 0x1078, 0x3fe1,
-	0x2c50, 0x1078, 0x41f0, 0x6824, 0xa005, 0x0040, 0x2a8f, 0xa082,
-	0x0006, 0x0048, 0x2a8d, 0x0078, 0x2a8f, 0x6827, 0x0005, 0x6814,
-	0xa084, 0x001f, 0xc0bd, 0x78aa, 0x2031, 0x0020, 0x2041, 0x0001,
-	0x2001, 0x0003, 0x0078, 0x2bc3, 0xc28d, 0x72d6, 0x72c0, 0xa200,
-	0xa015, 0x7154, 0x8108, 0xa12a, 0x0048, 0x2aa7, 0x71c0, 0x2164,
-	0x6504, 0x85ff, 0x00c0, 0x2abe, 0x7156, 0x8421, 0x00c0, 0x2aa2,
-	0x70d4, 0xd08c, 0x0040, 0x2aba, 0x70d0, 0xa005, 0x00c0, 0x2aba,
-	0x70d3, 0x000a, 0x007c, 0x2200, 0x0078, 0x2aac, 0x70d4, 0xc08c,
-	0x70d6, 0x70d3, 0x0000, 0x603c, 0xa005, 0x00c0, 0x2abb, 0x6708,
-	0xa784, 0x073f, 0x0040, 0x2aed, 0xd7d4, 0x00c0, 0x2abb, 0xa784,
-	0x0021, 0x00c0, 0x2abb, 0xa784, 0x0002, 0x0040, 0x2ade, 0xa784,
-	0x0004, 0x0040, 0x2abb, 0xa7bc, 0xfffb, 0x670a, 0xa784, 0x0218,
-	0x00c0, 0x2abb, 0xa784, 0x0100, 0x0040, 0x2aed, 0x6018, 0xa005,
-	0x00c0, 0x2abb, 0xa7bc, 0xfeff, 0x670a, 0x2568, 0x6823, 0x0000,
-	0x6e1c, 0xa684, 0x000e, 0x6318, 0x0040, 0x2afe, 0x601c, 0xa302,
-	0x0048, 0x2b01, 0x0040, 0x2b01, 0x0078, 0x2abb, 0x83ff, 0x00c0,
-	0x2abb, 0x2d58, 0x2c50, 0x7156, 0xd7bc, 0x00c0, 0x2b09, 0x7028,
-	0x6022, 0xc7bc, 0x670a, 0x68c0, 0xa065, 0xa04d, 0x6100, 0x2a60,
-	0x2041, 0x0001, 0x6b14, 0xa39c, 0x001f, 0xa39d, 0x00c0, 0xd1fc,
-	0x0040, 0x2b1d, 0xd684, 0x0040, 0x2b1f, 0xa39c, 0xffbf, 0xd6a4,
-	0x0040, 0x2b24, 0xa39d, 0x0020, 0xa684, 0x000e, 0x00c0, 0x2b6f,
-	0xc7a5, 0x670a, 0x2c00, 0x68c6, 0x77a4, 0xa786, 0x0001, 0x00c0,
-	0x2b43, 0x70d4, 0xd0b4, 0x00c0, 0x2b43, 0x7000, 0xa082, 0x0002,
-	0x00c8, 0x2b43, 0x7830, 0xd0bc, 0x00c0, 0x2b43, 0x789b, 0x0010,
-	0x7baa, 0x0078, 0x2bbb, 0x8739, 0x77a6, 0x2750, 0x77b0, 0xa7b0,
-	0x0005, 0x70ac, 0xa606, 0x00c0, 0x2b4e, 0x76a8, 0x76b2, 0x2c3a,
-	0x8738, 0x2d3a, 0x8738, 0x283a, 0x8738, 0x233a, 0x8738, 0x253a,
-	0x7830, 0xd0bc, 0x0040, 0x2b66, 0x2091, 0x8000, 0x2091, 0x303d,
-	0x70d4, 0xa084, 0x303d, 0x2091, 0x8000, 0x2090, 0xaad5, 0x0000,
-	0x0040, 0x2b6e, 0x8421, 0x2200, 0x00c0, 0x2aa1, 0x007c, 0xd1dc,
-	0x0040, 0x3be5, 0x2029, 0x0020, 0xd69c, 0x00c0, 0x2b7c, 0x8528,
-	0xd68c, 0x00c0, 0x2b7c, 0x8528, 0x8840, 0x6f14, 0x610c, 0x8108,
-	0xa18c, 0x00ff, 0x70cc, 0xa160, 0x2c64, 0x8cff, 0x0040, 0x2b9b,
-	0x6014, 0xa706, 0x00c0, 0x2b84, 0x60b8, 0x8001, 0x60ba, 0x00c0,
-	0x2b7f, 0x2a60, 0x6008, 0xa085, 0x0100, 0x600a, 0x2200, 0x8421,
-	0x00c0, 0x2aa1, 0x007c, 0x2a60, 0x610e, 0x69be, 0x2c00, 0x68c6,
-	0x8840, 0x6008, 0xc0d5, 0x600a, 0x77a4, 0xa786, 0x0001, 0x00c0,
-	0x2b43, 0x70d4, 0xd0b4, 0x00c0, 0x2b43, 0x7000, 0xa082, 0x0002,
-	0x00c8, 0x2b43, 0x7830, 0xd0bc, 0x00c0, 0x2b43, 0x789b, 0x0010,
-	0x7baa, 0x7daa, 0x79aa, 0x2001, 0x0002, 0x007e, 0x6018, 0x8000,
-	0x601a, 0x0078, 0x2bc4, 0x007e, 0x2960, 0x6104, 0x2a60, 0xa184,
-	0x0018, 0x0040, 0x2be0, 0xa184, 0x0010, 0x0040, 0x2bd3, 0x1078,
-	0x3df6, 0x00c0, 0x2c05, 0xa184, 0x0008, 0x0040, 0x2be0, 0x69a0,
-	0xa184, 0x0600, 0x00c0, 0x2be0, 0x1078, 0x3cda, 0x0078, 0x2c05,
-	0x69a0, 0xa184, 0x1e00, 0x0040, 0x2c10, 0xa184, 0x0800, 0x0040,
-	0x2bf9, 0x0c7e, 0x2960, 0x6000, 0xa085, 0x2000, 0x6002, 0x6104,
-	0xa18d, 0x0010, 0x6106, 0x0c7f, 0x1078, 0x3df6, 0x00c0, 0x2c05,
-	0x69a0, 0xa184, 0x0200, 0x0040, 0x2c01, 0x1078, 0x3d3a, 0x0078,
-	0x2c05, 0xa184, 0x0400, 0x00c0, 0x2bdc, 0x69a0, 0xa184, 0x1000,
-	0x0040, 0x2c10, 0x6914, 0xa18c, 0xff00, 0x810f, 0x1078, 0x2749,
-	0x027f, 0xa68c, 0x00e0, 0xa684, 0x0060, 0x0040, 0x2c1d, 0xa086,
-	0x0060, 0x00c0, 0x2c1d, 0xa18d, 0x4000, 0xa18d, 0x0104, 0x69b6,
-	0x789b, 0x0060, 0x2800, 0x78aa, 0x6818, 0xc0fd, 0x681a, 0xd6bc,
-	0x0040, 0x2c38, 0xc0fc, 0x7087, 0x0000, 0xa08a, 0x000d, 0x0050,
-	0x2c36, 0xa08a, 0x000c, 0x7186, 0x2001, 0x000c, 0x800c, 0x718a,
-	0x78aa, 0x3518, 0x3340, 0x3428, 0x8000, 0x80ac, 0xaf80, 0x002b,
-	0x20a0, 0x789b, 0x0000, 0xad80, 0x000b, 0x2098, 0x53a6, 0x23a8,
-	0x2898, 0x25a0, 0xa286, 0x0020, 0x00c0, 0x2c70, 0x70d4, 0xc0b5,
-	0x70d6, 0x2c00, 0x70ba, 0x2d00, 0x70be, 0x6814, 0xc0fc, 0x8007,
-	0x7882, 0xa286, 0x0002, 0x0040, 0x2ca6, 0x70a4, 0x8000, 0x70a6,
-	0x74b4, 0xa498, 0x0005, 0x70ac, 0xa306, 0x00c0, 0x2c68, 0x73a8,
-	0x73b6, 0xa286, 0x0010, 0x0040, 0x2942, 0x0d7f, 0x0c7f, 0x007c,
-	0x7000, 0xa005, 0x00c0, 0x2c4e, 0xa286, 0x0002, 0x00c0, 0x2cc0,
-	0x1078, 0x411c, 0x00c0, 0x2c4e, 0x6814, 0xc0fc, 0x8007, 0x7882,
-	0x2091, 0x8000, 0x781b, 0x005b, 0x68b4, 0x785a, 0x6894, 0x78d6,
-	0x78de, 0x6898, 0x78d2, 0x78da, 0x2091, 0x8001, 0x7808, 0xc08d,
-	0x780a, 0x127e, 0x0d7e, 0x0c7e, 0x70d4, 0xa084, 0x2700, 0x2090,
-	0x0c7f, 0x0d7f, 0x127f, 0x2900, 0x705a, 0x68bc, 0x7042, 0x7003,
-	0x0002, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x7830, 0xd0bc,
-	0x0040, 0x2cb2, 0x2091, 0x303d, 0x70d4, 0xa084, 0x303d, 0x2091,
-	0x8000, 0x2090, 0x70a4, 0xa005, 0x00c0, 0x2cb7, 0x007c, 0x8421,
-	0x0040, 0x2cb6, 0x7250, 0x70c0, 0xa200, 0xa015, 0x0078, 0x2aa1,
-	0xa286, 0x0010, 0x00c0, 0x2cf1, 0x1078, 0x411c, 0x00c0, 0x2c4e,
-	0x6814, 0xc0fc, 0x8007, 0x7882, 0x781b, 0x005b, 0x68b4, 0x785a,
-	0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0x7808, 0xc08d,
-	0x780a, 0x70a4, 0x8000, 0x70a6, 0x74b4, 0xa490, 0x0005, 0x70ac,
-	0xa206, 0x00c0, 0x2ce4, 0x72a8, 0x72b6, 0x2900, 0x705a, 0x68bc,
-	0x7042, 0x7003, 0x0002, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046,
-	0x007c, 0x6bb4, 0xa39d, 0x2000, 0x7b5a, 0x6814, 0xc0fc, 0x8007,
-	0x7882, 0x6b94, 0x7bd6, 0x7bde, 0x6e98, 0x7ed2, 0x7eda, 0x781b,
-	0x005b, 0x2900, 0x705a, 0x7202, 0x7808, 0xc08d, 0x780a, 0x2300,
-	0xa605, 0x0040, 0x2d1c, 0x70d4, 0xa084, 0x2700, 0xa086, 0x2300,
-	0x00c0, 0x2d16, 0x2009, 0x0000, 0x0078, 0x2d18, 0x2009, 0x0001,
-	0xa284, 0x000f, 0x1079, 0x2d20, 0xad80, 0x0009, 0x7046, 0x007c,
-	0x2d28, 0x45f7, 0x45f7, 0x45e4, 0x45f7, 0x2d28, 0x2d28, 0x2d28,
-	0x1078, 0x28ec, 0x7808, 0xa084, 0xfffd, 0x780a, 0x0f7e, 0x2079,
-	0x4a00, 0x78ac, 0x0f7f, 0xd084, 0x0040, 0x2d4e, 0x7064, 0xa086,
-	0x0001, 0x00c0, 0x2d3e, 0x7066, 0x0078, 0x2e27, 0x7064, 0xa086,
-	0x0005, 0x00c0, 0x2d4c, 0x707c, 0x2068, 0x681b, 0x0004, 0x6817,
-	0x0000, 0x6820, 0xc09d, 0x6822, 0x7067, 0x0000, 0x70a7, 0x0000,
-	0x70a8, 0x70b2, 0x70b6, 0x70d4, 0xd0b4, 0x0040, 0x2d64, 0xc0b4,
+	0x2001, 0x0010, 0x0078, 0x2c2c, 0x7060, 0xa005, 0x00c0, 0x2962,
+	0x0c7e, 0x0d7e, 0x70b4, 0xa06d, 0x6800, 0xa065, 0xa055, 0x789b,
+	0x0010, 0x6b0c, 0x7baa, 0x6808, 0xa045, 0x6d10, 0x6804, 0xa06d,
+	0xa05d, 0xa886, 0x0001, 0x0040, 0x29c8, 0x69bc, 0x7daa, 0x79aa,
+	0x68c0, 0xa04d, 0x6e1c, 0x2001, 0x0020, 0x0078, 0x2c2c, 0x1078,
+	0x42e9, 0x00c0, 0x2962, 0x781b, 0x005b, 0x70bc, 0xa06d, 0x68b4,
+	0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0x7808,
+	0xc08d, 0x780a, 0x68bc, 0x7042, 0xc1b4, 0x71d6, 0x70b8, 0xa065,
+	0x68c0, 0x705a, 0x7003, 0x0002, 0x2d00, 0x704e, 0xad80, 0x0009,
+	0x7046, 0x007c, 0x1078, 0x42e9, 0x00c0, 0x29fa, 0x781b, 0x0047,
+	0x7003, 0x0004, 0x007c, 0x1078, 0x42e9, 0x00c0, 0x2a05, 0x2011,
+	0x000c, 0x1078, 0x2a2c, 0x7003, 0x0004, 0x007c, 0x1078, 0x42e9,
+	0x00c0, 0x2a10, 0x2011, 0x0006, 0x1078, 0x2a2c, 0x7003, 0x0004,
+	0x007c, 0x1078, 0x42e9, 0x00c0, 0x2a1b, 0x2011, 0x000d, 0x1078,
+	0x2a2c, 0x7003, 0x0004, 0x007c, 0x1078, 0x42e9, 0x00c0, 0x2a2b,
+	0x2011, 0x0006, 0x1078, 0x2a2c, 0x707c, 0x707f, 0x0000, 0x2068,
+	0x704e, 0x7003, 0x0001, 0x007c, 0x7174, 0xc1fc, 0x8107, 0x7882,
+	0x789b, 0x0010, 0xa286, 0x000c, 0x00c0, 0x2a3b, 0x7aaa, 0x2001,
+	0x0001, 0x0078, 0x2a50, 0xa18c, 0x001f, 0xa18d, 0x00c0, 0x79aa,
+	0xa286, 0x000d, 0x0040, 0x2a49, 0x7aaa, 0x2001, 0x0002, 0x0078,
+	0x2a50, 0x78ab, 0x0020, 0x7178, 0x79aa, 0x7aaa, 0x2001, 0x0004,
+	0x789b, 0x0060, 0x78aa, 0x785b, 0x0004, 0x781b, 0x0110, 0x1078,
+	0x42fe, 0x7083, 0x000f, 0x70d4, 0xd0b4, 0x0040, 0x2a6c, 0xc0b4,
 	0x70d6, 0x0c7e, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a,
-	0x6018, 0x8001, 0x601a, 0x0c7f, 0x157e, 0x2011, 0x0004, 0x7164,
-	0xa186, 0x0001, 0x0040, 0x2d7d, 0xa186, 0x0007, 0x00c0, 0x2d74,
-	0x701f, 0x0005, 0x0078, 0x2d7d, 0x701f, 0x0001, 0x7067, 0x0000,
-	0x70d4, 0xc0dd, 0x70d6, 0x0078, 0x2d7f, 0x7067, 0x0000, 0x2001,
-	0x4a0a, 0x2004, 0xa084, 0x00ff, 0xa086, 0x0018, 0x0040, 0x2d8f,
-	0x7018, 0x7016, 0xa005, 0x00c0, 0x2d8f, 0x70a7, 0x0001, 0x1078,
-	0x4326, 0x20a9, 0x0010, 0x2039, 0x0000, 0x1078, 0x3edb, 0xa7b8,
-	0x0100, 0x00f0, 0x2d95, 0x7000, 0x0079, 0x2d9e, 0x2dcd, 0x2db3,
-	0x2db3, 0x2da8, 0x2dcd, 0x2dcd, 0x2dcd, 0x2da6, 0x1078, 0x28ec,
-	0x7060, 0xa005, 0x0040, 0x2dcd, 0xad06, 0x00c0, 0x2db3, 0x6800,
-	0x7062, 0x0078, 0x2dc5, 0x6820, 0xd084, 0x00c0, 0x2dc1, 0x6f14,
-	0x1078, 0x3fe1, 0x6008, 0xc0d4, 0x600a, 0x1078, 0x3bb5, 0x0078,
-	0x2dc5, 0x705c, 0x2060, 0x6800, 0x6002, 0x6a1a, 0x6817, 0x0000,
-	0x6820, 0xc09d, 0x6822, 0x1078, 0x202a, 0xb284, 0x0400, 0x0040,
-	0x2dd5, 0x2021, 0x91d0, 0x0078, 0x2dd7, 0x2021, 0x90c0, 0x1078,
-	0x2e2c, 0xb284, 0x0400, 0x0040, 0x2de1, 0x2021, 0x4a98, 0x0078,
-	0x2de3, 0x2021, 0x4a58, 0x1078, 0x2e2c, 0x20a9, 0x0101, 0xb284,
-	0x0400, 0x0040, 0x2def, 0x2021, 0x90d0, 0x0078, 0x2df1, 0x2021,
-	0x8fc0, 0x1078, 0x2e2c, 0x8420, 0x00f0, 0x2df1, 0xb284, 0x0300,
-	0x0040, 0x2dfe, 0x2061, 0x4fc0, 0x0078, 0x2e00, 0x2061, 0x6fc0,
-	0x2021, 0x0002, 0x20a9, 0x0100, 0x6110, 0x81ff, 0x0040, 0x2e1d,
-	0x6018, 0x017e, 0x007e, 0x2011, 0x4a02, 0x220c, 0xa102, 0x2012,
-	0x007f, 0x017f, 0xa102, 0x0050, 0x2e1d, 0x6012, 0x00c0, 0x2e1d,
-	0x2011, 0x4a04, 0x2204, 0xc0a5, 0x2012, 0x601b, 0x0000, 0xace0,
-	0x0010, 0x00f0, 0x2e04, 0x8421, 0x00c0, 0x2e02, 0x157f, 0x7003,
-	0x0000, 0x704f, 0x0000, 0x007c, 0x047e, 0x2404, 0xa005, 0x0040,
-	0x2e3f, 0x2068, 0x6800, 0x007e, 0x6a1a, 0x6817, 0x0000, 0x6820,
-	0xc09d, 0x6822, 0x1078, 0x202a, 0x007f, 0x0078, 0x2e2e, 0x047f,
-	0x2023, 0x0000, 0x007c, 0xa282, 0x0003, 0x0050, 0x2e49, 0x1078,
-	0x28ec, 0x2300, 0x0079, 0x2e4c, 0x2e4f, 0x2eda, 0x2ef7, 0xa282,
-	0x0002, 0x0040, 0x2e55, 0x1078, 0x28ec, 0x7064, 0x7067, 0x0000,
-	0x7083, 0x0000, 0x0079, 0x2e5c, 0x2e64, 0x2e64, 0x2e66, 0x2ea6,
-	0x3bf1, 0x2e64, 0x2ea6, 0x2e64, 0x1078, 0x28ec, 0x7774, 0x1078,
-	0x3edb, 0x7774, 0xa7bc, 0x8f00, 0x1078, 0x3fe1, 0x6018, 0xa005,
-	0x0040, 0x2e9d, 0xd7fc, 0x00c0, 0x2e79, 0x2021, 0x90c0, 0x0078,
-	0x2e7b, 0x2021, 0x91d0, 0x2009, 0x0005, 0x2011, 0x0010, 0x1078,
-	0x2f12, 0x0040, 0x2e9d, 0x157e, 0x20a9, 0x0101, 0xd7fc, 0x00c0,
-	0x2e8d, 0x2021, 0x8fc0, 0x0078, 0x2e8f, 0x2021, 0x90d0, 0x047e,
-	0x2009, 0x0005, 0x2011, 0x0010, 0x1078, 0x2f12, 0x047f, 0x0040,
-	0x2e9c, 0x8420, 0x00f0, 0x2e8f, 0x157f, 0x8738, 0xa784, 0x001f,
-	0x00c0, 0x2e6c, 0x0078, 0x2946, 0x0078, 0x2946, 0x7774, 0x1078,
-	0x3fe1, 0x6018, 0xa005, 0x0040, 0x2ed8, 0xd7fc, 0x00c0, 0x2eb4,
-	0x2021, 0x90c0, 0x0078, 0x2eb6, 0x2021, 0x91d0, 0x2009, 0x0005,
-	0x2011, 0x0020, 0x1078, 0x2f12, 0x0040, 0x2ed8, 0x157e, 0x20a9,
-	0x0101, 0xd7fc, 0x00c0, 0x2ec8, 0x2021, 0x8fc0, 0x0078, 0x2eca,
-	0x2021, 0x90d0, 0x047e, 0x2009, 0x0005, 0x2011, 0x0020, 0x1078,
-	0x2f12, 0x047f, 0x0040, 0x2ed7, 0x8420, 0x00f0, 0x2eca, 0x157f,
-	0x0078, 0x2946, 0x2200, 0x0079, 0x2edd, 0x2ee0, 0x2ee2, 0x2ee2,
-	0x1078, 0x28ec, 0x2009, 0x0012, 0x7064, 0xa086, 0x0002, 0x0040,
-	0x2eeb, 0x2009, 0x000e, 0x6818, 0xd0fc, 0x0040, 0x2ef0, 0x691a,
-	0x7067, 0x0000, 0x70d4, 0xc0dd, 0x70d6, 0x0078, 0x40c9, 0x2200,
-	0x0079, 0x2efa, 0x2eff, 0x2ee2, 0x2efd, 0x1078, 0x28ec, 0x1078,
-	0x4326, 0x7000, 0xa086, 0x0002, 0x00c0, 0x3b7a, 0x1078, 0x3bd2,
-	0x6008, 0xa084, 0xfbef, 0x600a, 0x1078, 0x3b6b, 0x0040, 0x3b7a,
-	0x0078, 0x2946, 0x2404, 0xa005, 0x0040, 0x2f41, 0x2068, 0x2d04,
-	0x007e, 0x6814, 0xa706, 0x0040, 0x2f21, 0x2d20, 0x007f, 0x0078,
-	0x2f13, 0x007f, 0x2022, 0x691a, 0x6817, 0x0000, 0x6820, 0xa205,
-	0x6822, 0x1078, 0x202a, 0x2021, 0x4a02, 0x241c, 0x8319, 0x2322,
-	0x6010, 0x8001, 0x6012, 0x00c0, 0x2f3a, 0x2021, 0x4a04, 0x2404,
-	0xc0a5, 0x2022, 0x6008, 0xa084, 0xf9ef, 0x600a, 0x1078, 0x3bd2,
-	0x007c, 0xa085, 0x0001, 0x0078, 0x2f40, 0x2300, 0x0079, 0x2f48,
-	0x2f4d, 0x2f4b, 0x2fce, 0x1078, 0x28ec, 0x78e4, 0xa005, 0x00d0,
-	0x2f84, 0x3208, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f,
-	0x0040, 0x2f5e, 0xa18c, 0x0300, 0x0078, 0x2f60, 0xa18c, 0x0400,
-	0x0040, 0x2f66, 0x0018, 0x2942, 0x0078, 0x2f68, 0x0028, 0x2942,
-	0x2008, 0xa084, 0x0030, 0x00c0, 0x2f70, 0x781b, 0x005b, 0x007c,
-	0x78ec, 0xa084, 0x0003, 0x0040, 0x2f6d, 0x2100, 0xa084, 0x0007,
-	0x0079, 0x2f7a, 0x2fae, 0x2fb8, 0x2fa3, 0x2f82, 0x4111, 0x4111,
-	0x2f82, 0x2fc3, 0x1078, 0x28ec, 0x7000, 0xa086, 0x0004, 0x00c0,
-	0x2f9e, 0x7064, 0xa086, 0x0002, 0x00c0, 0x2f94, 0x2011, 0x0002,
-	0x2019, 0x0000, 0x0078, 0x2e43, 0x7064, 0xa086, 0x0006, 0x0040,
-	0x2f8e, 0x7064, 0xa086, 0x0004, 0x0040, 0x2f8e, 0x79e4, 0x2001,
-	0x0003, 0x0078, 0x3304, 0x6818, 0xd0fc, 0x0040, 0x2fa9, 0x681b,
-	0x001d, 0x1078, 0x3eae, 0x781b, 0x0061, 0x007c, 0x6818, 0xd0fc,
-	0x0040, 0x2fb4, 0x681b, 0x001d, 0x1078, 0x3eae, 0x0078, 0x40ed,
-	0x6818, 0xd0fc, 0x0040, 0x2fbe, 0x681b, 0x001d, 0x1078, 0x3eae,
-	0x781b, 0x00ef, 0x007c, 0x6818, 0xd0fc, 0x0040, 0x2fc9, 0x681b,
-	0x001d, 0x1078, 0x3eae, 0x781b, 0x00bf, 0x007c, 0xa584, 0x000f,
-	0x00c0, 0x2feb, 0x7000, 0x0079, 0x2fd5, 0x2946, 0x2fdd, 0x2fdf,
-	0x3b7a, 0x3b7a, 0x3b7a, 0x2fdd, 0x2fdd, 0x1078, 0x28ec, 0x1078,
-	0x3bd2, 0x6008, 0xa084, 0xfbef, 0x600a, 0x1078, 0x3b6b, 0x0040,
-	0x3b7a, 0x0078, 0x2946, 0x78e4, 0xa005, 0x00d0, 0x2f84, 0x3208,
-	0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x2ffc,
-	0xa18c, 0x0300, 0x0078, 0x2ffe, 0xa18c, 0x0400, 0x0040, 0x3004,
-	0x0018, 0x2f84, 0x0078, 0x3006, 0x0028, 0x2f84, 0x2008, 0xa084,
-	0x0030, 0x00c0, 0x300e, 0x781b, 0x005b, 0x007c, 0x78ec, 0xa084,
-	0x0003, 0x0040, 0x300b, 0x2100, 0xa184, 0x0007, 0x0079, 0x3018,
-	0x3027, 0x302b, 0x3022, 0x3020, 0x4111, 0x4111, 0x3020, 0x410b,
-	0x1078, 0x28ec, 0x1078, 0x3eb6, 0x781b, 0x0061, 0x007c, 0x1078,
-	0x3eb6, 0x0078, 0x40ed, 0x1078, 0x3eb6, 0x781b, 0x00ef, 0x007c,
-	0x1078, 0x3eb6, 0x781b, 0x00bf, 0x007c, 0x2300, 0x0079, 0x3038,
-	0x303d, 0x303b, 0x303f, 0x1078, 0x28ec, 0x0078, 0x37bd, 0x681b,
-	0x0016, 0x78a3, 0x0000, 0x79e4, 0xa184, 0x0030, 0x0040, 0x37bd,
-	0x78ec, 0xa084, 0x0003, 0x0040, 0x37bd, 0xa184, 0x0100, 0x0040,
-	0x3043, 0xa184, 0x0007, 0x0079, 0x3055, 0x305d, 0x302b, 0x2fa3,
-	0x40c9, 0x4111, 0x4111, 0x40c9, 0x410b, 0x1078, 0x40d5, 0x007c,
-	0xa282, 0x0005, 0x0050, 0x3066, 0x1078, 0x28ec, 0x2300, 0x0079,
-	0x3069, 0x306c, 0x328b, 0x3296, 0x2200, 0x0079, 0x306f, 0x3089,
-	0x3076, 0x3089, 0x3074, 0x326e, 0x1078, 0x28ec, 0x789b, 0x0018,
-	0x78a8, 0xa084, 0x00ff, 0xa082, 0x0020, 0x0048, 0x3e9d, 0xa08a,
-	0x0004, 0x00c8, 0x3e9d, 0x0079, 0x3085, 0x3e9d, 0x3e9d, 0x3e9d,
-	0x3e47, 0x789b, 0x0018, 0x79a8, 0xa184, 0x0080, 0x0040, 0x309a,
-	0x0078, 0x3e9d, 0x7000, 0xa005, 0x00c0, 0x3090, 0x2011, 0x0004,
-	0x0078, 0x3998, 0xa184, 0x00ff, 0xa08a, 0x0010, 0x00c8, 0x3e9d,
-	0x0079, 0x30a2, 0x30b4, 0x30b2, 0x30c9, 0x30cd, 0x318f, 0x3e9d,
-	0x3e9d, 0x3191, 0x3e9d, 0x3e9d, 0x326a, 0x326a, 0x3e9d, 0x3e9d,
-	0x3e9d, 0x326c, 0x1078, 0x28ec, 0xd6e4, 0x0040, 0x30bf, 0x2001,
-	0x0300, 0x8000, 0x8000, 0x783a, 0x781b, 0x00ba, 0x007c, 0x6818,
-	0xd0fc, 0x0040, 0x30c7, 0x681b, 0x001d, 0x0078, 0x30b7, 0x0078,
-	0x40c9, 0x681b, 0x001d, 0x0078, 0x3ea7, 0x6920, 0x6922, 0xa684,
-	0x1800, 0x00c0, 0x3121, 0x6820, 0xd084, 0x00c0, 0x3127, 0x6818,
-	0xa086, 0x0008, 0x00c0, 0x30de, 0x681b, 0x0000, 0xd6d4, 0x0040,
-	0x318c, 0xd6bc, 0x0040, 0x311e, 0x7087, 0x0000, 0x6818, 0xa084,
-	0x003f, 0xa08a, 0x000d, 0x0050, 0x311e, 0xa08a, 0x000c, 0x7186,
+	0x6018, 0x8001, 0x601a, 0x0c7f, 0x007c, 0x7014, 0xa005, 0x00c0,
+	0x2a7b, 0x70d4, 0xd0b4, 0x0040, 0x2a7c, 0x70b8, 0xac06, 0x00c0,
+	0x2a7c, 0x1078, 0x2a5b, 0x007c, 0x017e, 0x71a4, 0xa186, 0x0001,
+	0x0040, 0x2aae, 0x0d7e, 0x027e, 0x2100, 0x2011, 0x0001, 0xa212,
+	0x70b4, 0x2068, 0x6800, 0xac06, 0x0040, 0x2a95, 0x8211, 0x0040,
+	0x2aac, 0x1078, 0x2ab0, 0x0078, 0x2a8a, 0x0c7e, 0x2100, 0x2011,
+	0x0001, 0xa212, 0x70b4, 0x2068, 0x6800, 0x2060, 0x6008, 0xa084,
+	0xfbef, 0x600a, 0x8211, 0x0040, 0x2aa9, 0x1078, 0x2ab0, 0x0078,
+	0x2a9c, 0x70a7, 0x0001, 0x0c7f, 0x027f, 0x0d7f, 0x017f, 0x007c,
+	0xade8, 0x0005, 0x70ac, 0xad06, 0x00c0, 0x2ab8, 0x70a8, 0x2068,
+	0x007c, 0x1078, 0x42e9, 0x00c0, 0x2962, 0x707c, 0x2068, 0x7774,
+	0x1078, 0x4187, 0x2c50, 0x1078, 0x43bd, 0x789b, 0x0010, 0x6814,
+	0xa084, 0x001f, 0xc0bd, 0x78aa, 0x6e1c, 0x2041, 0x0001, 0x2001,
+	0x0004, 0x0078, 0x2c32, 0x1078, 0x42e9, 0x00c0, 0x2962, 0x789b,
+	0x0010, 0x7060, 0x2068, 0x6f14, 0x70d4, 0xd0b4, 0x0040, 0x2aed,
+	0xc0b4, 0x70d6, 0x0c7e, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef,
+	0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f, 0x1078, 0x4187, 0x2c50,
+	0x1078, 0x43bd, 0x6824, 0xa005, 0x0040, 0x2afe, 0xa082, 0x0006,
+	0x0048, 0x2afc, 0x0078, 0x2afe, 0x6827, 0x0005, 0x6814, 0xa084,
+	0x001f, 0xc0bd, 0x78aa, 0x2031, 0x0020, 0x2041, 0x0001, 0x2001,
+	0x0003, 0x0078, 0x2c32, 0xc28d, 0x72d6, 0x72c0, 0xa200, 0xa015,
+	0x7154, 0x8108, 0xa12a, 0x0048, 0x2b16, 0x71c0, 0x2164, 0x6504,
+	0x85ff, 0x00c0, 0x2b2d, 0x7156, 0x8421, 0x00c0, 0x2b11, 0x70d4,
+	0xd08c, 0x0040, 0x2b29, 0x70d0, 0xa005, 0x00c0, 0x2b29, 0x70d3,
+	0x000a, 0x007c, 0x2200, 0x0078, 0x2b1b, 0x70d4, 0xc08c, 0x70d6,
+	0x70d3, 0x0000, 0x6034, 0xa005, 0x00c0, 0x2b2a, 0x6708, 0xa784,
+	0x073f, 0x0040, 0x2b5c, 0xd7d4, 0x00c0, 0x2b2a, 0xa784, 0x0021,
+	0x00c0, 0x2b2a, 0xa784, 0x0002, 0x0040, 0x2b4d, 0xa784, 0x0004,
+	0x0040, 0x2b2a, 0xa7bc, 0xfffb, 0x670a, 0xa784, 0x0218, 0x00c0,
+	0x2b2a, 0xa784, 0x0100, 0x0040, 0x2b5c, 0x6018, 0xa005, 0x00c0,
+	0x2b2a, 0xa7bc, 0xfeff, 0x670a, 0x2568, 0x6823, 0x0000, 0x6e1c,
+	0xa684, 0x000e, 0x6318, 0x0040, 0x2b6d, 0x601c, 0xa302, 0x0048,
+	0x2b70, 0x0040, 0x2b70, 0x0078, 0x2b2a, 0x83ff, 0x00c0, 0x2b2a,
+	0x2d58, 0x2c50, 0x7156, 0xd7bc, 0x00c0, 0x2b78, 0x7028, 0x6022,
+	0xc7bc, 0x670a, 0x68c0, 0xa065, 0xa04d, 0x6100, 0x2a60, 0x2041,
+	0x0001, 0x6b14, 0xa39c, 0x001f, 0xa39d, 0x00c0, 0xd1fc, 0x0040,
+	0x2b8c, 0xd684, 0x0040, 0x2b8e, 0xa39c, 0xffbf, 0xd6a4, 0x0040,
+	0x2b93, 0xa39d, 0x0020, 0xa684, 0x000e, 0x00c0, 0x2bde, 0xc7a5,
+	0x670a, 0x2c00, 0x68c6, 0x77a4, 0xa786, 0x0001, 0x00c0, 0x2bb2,
+	0x70d4, 0xd0b4, 0x00c0, 0x2bb2, 0x7000, 0xa082, 0x0002, 0x00c8,
+	0x2bb2, 0x7830, 0xd0bc, 0x00c0, 0x2bb2, 0x789b, 0x0010, 0x7baa,
+	0x0078, 0x2c2a, 0x8739, 0x77a6, 0x2750, 0x77b0, 0xa7b0, 0x0005,
+	0x70ac, 0xa606, 0x00c0, 0x2bbd, 0x76a8, 0x76b2, 0x2c3a, 0x8738,
+	0x2d3a, 0x8738, 0x283a, 0x8738, 0x233a, 0x8738, 0x253a, 0x7830,
+	0xd0bc, 0x0040, 0x2bd5, 0x2091, 0x8000, 0x2091, 0x303d, 0x70d4,
+	0xa084, 0x303d, 0x2091, 0x8000, 0x2090, 0xaad5, 0x0000, 0x0040,
+	0x2bdd, 0x8421, 0x2200, 0x00c0, 0x2b10, 0x007c, 0xd1dc, 0x0040,
+	0x3d86, 0x2029, 0x0020, 0xd69c, 0x00c0, 0x2beb, 0x8528, 0xd68c,
+	0x00c0, 0x2beb, 0x8528, 0x8840, 0x6f14, 0x610c, 0x8108, 0xa18c,
+	0x00ff, 0x70cc, 0xa160, 0x2c64, 0x8cff, 0x0040, 0x2c0a, 0x6014,
+	0xa706, 0x00c0, 0x2bf3, 0x60b8, 0x8001, 0x60ba, 0x00c0, 0x2bee,
+	0x2a60, 0x6008, 0xa085, 0x0100, 0x600a, 0x2200, 0x8421, 0x00c0,
+	0x2b10, 0x007c, 0x2a60, 0x610e, 0x69be, 0x2c00, 0x68c6, 0x8840,
+	0x6008, 0xc0d5, 0x600a, 0x77a4, 0xa786, 0x0001, 0x00c0, 0x2bb2,
+	0x70d4, 0xd0b4, 0x00c0, 0x2bb2, 0x7000, 0xa082, 0x0002, 0x00c8,
+	0x2bb2, 0x7830, 0xd0bc, 0x00c0, 0x2bb2, 0x789b, 0x0010, 0x7baa,
+	0x7daa, 0x79aa, 0x2001, 0x0002, 0x007e, 0x6018, 0x8000, 0x601a,
+	0x0078, 0x2c33, 0x007e, 0x2960, 0x6104, 0x2a60, 0xa184, 0x0018,
+	0x0040, 0x2c4f, 0xa184, 0x0010, 0x0040, 0x2c42, 0x1078, 0x3f99,
+	0x00c0, 0x2c74, 0xa184, 0x0008, 0x0040, 0x2c4f, 0x69a0, 0xa184,
+	0x0600, 0x00c0, 0x2c4f, 0x1078, 0x3e7c, 0x0078, 0x2c74, 0x69a0,
+	0xa184, 0x1e00, 0x0040, 0x2c7f, 0xa184, 0x0800, 0x0040, 0x2c68,
+	0x0c7e, 0x2960, 0x6000, 0xa085, 0x2000, 0x6002, 0x6104, 0xa18d,
+	0x0010, 0x6106, 0x0c7f, 0x1078, 0x3f99, 0x00c0, 0x2c74, 0x69a0,
+	0xa184, 0x0200, 0x0040, 0x2c70, 0x1078, 0x3edc, 0x0078, 0x2c74,
+	0xa184, 0x0400, 0x00c0, 0x2c4b, 0x69a0, 0xa184, 0x1000, 0x0040,
+	0x2c7f, 0x6914, 0xa18c, 0xff00, 0x810f, 0x1078, 0x2755, 0x027f,
+	0xa68c, 0x00e0, 0xa684, 0x0060, 0x0040, 0x2c8c, 0xa086, 0x0060,
+	0x00c0, 0x2c8c, 0xa18d, 0x4000, 0xa18d, 0x0104, 0x69b6, 0x789b,
+	0x0060, 0x2800, 0x78aa, 0x6818, 0xc0fd, 0x681a, 0xd6bc, 0x0040,
+	0x2ca7, 0xc0fc, 0x7087, 0x0000, 0xa08a, 0x000d, 0x0050, 0x2ca5,
+	0xa08a, 0x000c, 0x7186, 0x2001, 0x000c, 0x800c, 0x718a, 0x78aa,
+	0x3518, 0x3340, 0x3428, 0x8000, 0x80ac, 0xaf80, 0x002b, 0x20a0,
+	0x789b, 0x0000, 0xad80, 0x000b, 0x2098, 0x53a6, 0x23a8, 0x2898,
+	0x25a0, 0xa286, 0x0020, 0x00c0, 0x2cdf, 0x70d4, 0xc0b5, 0x70d6,
+	0x2c00, 0x70ba, 0x2d00, 0x70be, 0x6814, 0xc0fc, 0x8007, 0x7882,
+	0xa286, 0x0002, 0x0040, 0x2d15, 0x70a4, 0x8000, 0x70a6, 0x74b4,
+	0xa498, 0x0005, 0x70ac, 0xa306, 0x00c0, 0x2cd7, 0x73a8, 0x73b6,
+	0xa286, 0x0010, 0x0040, 0x2962, 0x0d7f, 0x0c7f, 0x007c, 0x7000,
+	0xa005, 0x00c0, 0x2cbd, 0xa286, 0x0002, 0x00c0, 0x2d2f, 0x1078,
+	0x42e9, 0x00c0, 0x2cbd, 0x6814, 0xc0fc, 0x8007, 0x7882, 0x2091,
+	0x8000, 0x781b, 0x005b, 0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de,
+	0x6898, 0x78d2, 0x78da, 0x2091, 0x8001, 0x7808, 0xc08d, 0x780a,
+	0x127e, 0x0d7e, 0x0c7e, 0x70d4, 0xa084, 0x2700, 0x2090, 0x0c7f,
+	0x0d7f, 0x127f, 0x2900, 0x705a, 0x68bc, 0x7042, 0x7003, 0x0002,
+	0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x7830, 0xd0bc, 0x0040,
+	0x2d21, 0x2091, 0x303d, 0x70d4, 0xa084, 0x303d, 0x2091, 0x8000,
+	0x2090, 0x70a4, 0xa005, 0x00c0, 0x2d26, 0x007c, 0x8421, 0x0040,
+	0x2d25, 0x7250, 0x70c0, 0xa200, 0xa015, 0x0078, 0x2b10, 0xa286,
+	0x0010, 0x00c0, 0x2d60, 0x1078, 0x42e9, 0x00c0, 0x2cbd, 0x6814,
+	0xc0fc, 0x8007, 0x7882, 0x781b, 0x005b, 0x68b4, 0x785a, 0x6894,
+	0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0x7808, 0xc08d, 0x780a,
+	0x70a4, 0x8000, 0x70a6, 0x74b4, 0xa490, 0x0005, 0x70ac, 0xa206,
+	0x00c0, 0x2d53, 0x72a8, 0x72b6, 0x2900, 0x705a, 0x68bc, 0x7042,
+	0x7003, 0x0002, 0x2d00, 0x704e, 0xad80, 0x0009, 0x7046, 0x007c,
+	0x6bb4, 0xa39d, 0x2000, 0x7b5a, 0x6814, 0xc0fc, 0x8007, 0x7882,
+	0x6b94, 0x7bd6, 0x7bde, 0x6e98, 0x7ed2, 0x7eda, 0x781b, 0x005b,
+	0x2900, 0x705a, 0x7202, 0x7808, 0xc08d, 0x780a, 0x2300, 0xa605,
+	0x0040, 0x2d8b, 0x70d4, 0xa084, 0x2700, 0xa086, 0x2300, 0x00c0,
+	0x2d85, 0x2009, 0x0000, 0x0078, 0x2d87, 0x2009, 0x0001, 0xa284,
+	0x000f, 0x1079, 0x2d8f, 0xad80, 0x0009, 0x7046, 0x007c, 0x2d97,
+	0x4834, 0x4834, 0x4821, 0x4834, 0x2d97, 0x2d97, 0x2d97, 0x1078,
+	0x290c, 0x7808, 0xa084, 0xfffd, 0x780a, 0x0f7e, 0x2079, 0x4d00,
+	0x78ac, 0x0f7f, 0xd084, 0x0040, 0x2dbf, 0x7064, 0xa086, 0x0001,
+	0x00c0, 0x2dad, 0x7066, 0x0078, 0x2e96, 0x7064, 0xa086, 0x0005,
+	0x00c0, 0x2dbd, 0x707c, 0x2068, 0x681b, 0x0004, 0x6817, 0x0000,
+	0x6820, 0xa084, 0x00ff, 0xc09d, 0x6822, 0x7067, 0x0000, 0x70a7,
+	0x0000, 0x70a8, 0x70b2, 0x70b6, 0x1078, 0x2a5b, 0x157e, 0x2011,
+	0x0004, 0x7164, 0xa186, 0x0001, 0x0040, 0x2ddf, 0xa186, 0x0007,
+	0x00c0, 0x2dd6, 0x701f, 0x0005, 0x0078, 0x2ddf, 0x701f, 0x0001,
+	0x7067, 0x0000, 0x70d4, 0xc0dd, 0x70d6, 0x0078, 0x2de1, 0x7067,
+	0x0000, 0x2001, 0x4d0a, 0x2004, 0xa084, 0x00ff, 0xa086, 0x0018,
+	0x0040, 0x2df1, 0x7018, 0x7016, 0xa005, 0x00c0, 0x2df1, 0x70a7,
+	0x0001, 0x067e, 0x1078, 0x44fb, 0x20a9, 0x0010, 0x2039, 0x0000,
+	0x1078, 0x4081, 0xa7b8, 0x0100, 0x00f0, 0x2df8, 0x067f, 0x7000,
+	0x0079, 0x2e02, 0x2e3c, 0x2e17, 0x2e17, 0x2e0c, 0x2e3c, 0x2e3c,
+	0x2e3c, 0x2e0a, 0x1078, 0x290c, 0x7060, 0xa005, 0x0040, 0x2e3c,
+	0xad06, 0x00c0, 0x2e17, 0x6800, 0x7062, 0x0078, 0x2e29, 0x6820,
+	0xd084, 0x00c0, 0x2e25, 0x6f14, 0x1078, 0x4187, 0x6008, 0xc0d4,
+	0x600a, 0x1078, 0x3d56, 0x0078, 0x2e29, 0x705c, 0x2060, 0x6800,
+	0x6002, 0xa684, 0x5f00, 0x681e, 0x6818, 0xd0fc, 0x0040, 0x2e31,
+	0x6a1a, 0x6817, 0x0000, 0x682b, 0x0000, 0x6820, 0xa084, 0x00ff,
+	0xc09d, 0x6822, 0x1078, 0x2013, 0xb284, 0x0400, 0x0040, 0x2e44,
+	0x2021, 0x94d0, 0x0078, 0x2e46, 0x2021, 0x93c0, 0x1078, 0x2e9b,
+	0xb284, 0x0400, 0x0040, 0x2e50, 0x2021, 0x4d98, 0x0078, 0x2e52,
+	0x2021, 0x4d58, 0x1078, 0x2e9b, 0x20a9, 0x0101, 0xb284, 0x0400,
+	0x0040, 0x2e5e, 0x2021, 0x93d0, 0x0078, 0x2e60, 0x2021, 0x92c0,
+	0x1078, 0x2e9b, 0x8420, 0x00f0, 0x2e60, 0xb284, 0x0300, 0x0040,
+	0x2e6d, 0x2061, 0x52c0, 0x0078, 0x2e6f, 0x2061, 0x72c0, 0x2021,
+	0x0002, 0x20a9, 0x0100, 0x6110, 0x81ff, 0x0040, 0x2e8c, 0x6018,
+	0x017e, 0x007e, 0x2011, 0x4d02, 0x220c, 0xa102, 0x2012, 0x007f,
+	0x017f, 0xa102, 0x0050, 0x2e8c, 0x6012, 0x00c0, 0x2e8c, 0x2011,
+	0x4d04, 0x2204, 0xc0a5, 0x2012, 0x601b, 0x0000, 0xace0, 0x0010,
+	0x00f0, 0x2e73, 0x8421, 0x00c0, 0x2e71, 0x157f, 0x7003, 0x0000,
+	0x704f, 0x0000, 0x007c, 0x047e, 0x2404, 0xa005, 0x0040, 0x2eb6,
+	0x2068, 0x6800, 0x007e, 0x6a1a, 0x6817, 0x0000, 0x682b, 0x0000,
+	0x68b4, 0xa084, 0x5f00, 0x681e, 0x6820, 0xa084, 0x00ff, 0xc09d,
+	0x6822, 0x1078, 0x2013, 0x007f, 0x0078, 0x2e9d, 0x047f, 0x2023,
+	0x0000, 0x007c, 0xa282, 0x0003, 0x0050, 0x2ec0, 0x1078, 0x290c,
+	0x2300, 0x0079, 0x2ec3, 0x2ec6, 0x2f51, 0x2f6e, 0xa282, 0x0002,
+	0x0040, 0x2ecc, 0x1078, 0x290c, 0x7064, 0x7067, 0x0000, 0x7083,
+	0x0000, 0x0079, 0x2ed3, 0x2edb, 0x2edb, 0x2edd, 0x2f1d, 0x3d92,
+	0x2edb, 0x2f1d, 0x2edb, 0x1078, 0x290c, 0x7774, 0x1078, 0x4081,
+	0x7774, 0xa7bc, 0x8f00, 0x1078, 0x4187, 0x6018, 0xa005, 0x0040,
+	0x2f14, 0xd7fc, 0x00c0, 0x2ef0, 0x2021, 0x93c0, 0x0078, 0x2ef2,
+	0x2021, 0x94d0, 0x2009, 0x0005, 0x2011, 0x0010, 0x1078, 0x2f89,
+	0x0040, 0x2f14, 0x157e, 0x20a9, 0x0101, 0xd7fc, 0x00c0, 0x2f04,
+	0x2021, 0x92c0, 0x0078, 0x2f06, 0x2021, 0x93d0, 0x047e, 0x2009,
+	0x0005, 0x2011, 0x0010, 0x1078, 0x2f89, 0x047f, 0x0040, 0x2f13,
+	0x8420, 0x00f0, 0x2f06, 0x157f, 0x8738, 0xa784, 0x001f, 0x00c0,
+	0x2ee3, 0x0078, 0x2966, 0x0078, 0x2966, 0x7774, 0x1078, 0x4187,
+	0x6018, 0xa005, 0x0040, 0x2f4f, 0xd7fc, 0x00c0, 0x2f2b, 0x2021,
+	0x93c0, 0x0078, 0x2f2d, 0x2021, 0x94d0, 0x2009, 0x0005, 0x2011,
+	0x0020, 0x1078, 0x2f89, 0x0040, 0x2f4f, 0x157e, 0x20a9, 0x0101,
+	0xd7fc, 0x00c0, 0x2f3f, 0x2021, 0x92c0, 0x0078, 0x2f41, 0x2021,
+	0x93d0, 0x047e, 0x2009, 0x0005, 0x2011, 0x0020, 0x1078, 0x2f89,
+	0x047f, 0x0040, 0x2f4e, 0x8420, 0x00f0, 0x2f41, 0x157f, 0x0078,
+	0x2966, 0x2200, 0x0079, 0x2f54, 0x2f57, 0x2f59, 0x2f59, 0x1078,
+	0x290c, 0x2009, 0x0012, 0x7064, 0xa086, 0x0002, 0x0040, 0x2f62,
+	0x2009, 0x000e, 0x6818, 0xd0fc, 0x0040, 0x2f67, 0x691a, 0x7067,
+	0x0000, 0x70d4, 0xc0dd, 0x70d6, 0x0078, 0x4296, 0x2200, 0x0079,
+	0x2f71, 0x2f76, 0x2f59, 0x2f74, 0x1078, 0x290c, 0x1078, 0x44fb,
+	0x7000, 0xa086, 0x0002, 0x00c0, 0x3d04, 0x1078, 0x3d73, 0x6008,
+	0xa084, 0xfbef, 0x600a, 0x1078, 0x3cf5, 0x0040, 0x3d04, 0x0078,
+	0x2966, 0x2404, 0xa005, 0x0040, 0x2fc2, 0x2068, 0x2d04, 0x007e,
+	0x6814, 0xa706, 0x0040, 0x2f98, 0x2d20, 0x007f, 0x0078, 0x2f8a,
+	0x007f, 0x2022, 0x691a, 0x6817, 0x0000, 0x682b, 0x0000, 0x68b4,
+	0xa084, 0x5f00, 0x681e, 0x6820, 0xa084, 0x00ff, 0xa205, 0x6822,
+	0x1078, 0x2013, 0x2021, 0x4d02, 0x241c, 0x8319, 0x2322, 0x6010,
+	0x8001, 0x6012, 0x00c0, 0x2fb9, 0x2021, 0x4d04, 0x2404, 0xc0a5,
+	0x2022, 0x6008, 0xa084, 0xf9ef, 0x600a, 0x1078, 0x2a7c, 0x1078,
+	0x3d73, 0x007c, 0xa085, 0x0001, 0x0078, 0x2fc1, 0x2300, 0x0079,
+	0x2fc9, 0x2fce, 0x2fcc, 0x304e, 0x1078, 0x290c, 0x78e4, 0xa005,
+	0x00d0, 0x3004, 0x3208, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x007f, 0x0040, 0x2fdf, 0xa18c, 0x0300, 0x0078, 0x2fe1, 0xa18c,
+	0x0400, 0x0040, 0x2fe7, 0x0018, 0x2962, 0x0078, 0x2fe9, 0x0028,
+	0x2962, 0x2008, 0xa084, 0x0030, 0x00c0, 0x2ff0, 0x0078, 0x36fb,
+	0x78ec, 0xa084, 0x0003, 0x0040, 0x2fee, 0x2100, 0xa084, 0x0007,
+	0x0079, 0x2ffa, 0x302e, 0x3038, 0x3023, 0x3002, 0x42de, 0x42de,
+	0x3002, 0x3043, 0x1078, 0x290c, 0x7000, 0xa086, 0x0004, 0x00c0,
+	0x301e, 0x7064, 0xa086, 0x0002, 0x00c0, 0x3014, 0x2011, 0x0002,
+	0x2019, 0x0000, 0x0078, 0x2eba, 0x7064, 0xa086, 0x0006, 0x0040,
+	0x300e, 0x7064, 0xa086, 0x0004, 0x0040, 0x300e, 0x79e4, 0x2001,
+	0x0003, 0x0078, 0x3385, 0x6818, 0xd0fc, 0x0040, 0x3029, 0x681b,
+	0x001d, 0x1078, 0x4051, 0x781b, 0x0061, 0x007c, 0x6818, 0xd0fc,
+	0x0040, 0x3034, 0x681b, 0x001d, 0x1078, 0x4051, 0x0078, 0x42ba,
+	0x6818, 0xd0fc, 0x0040, 0x303e, 0x681b, 0x001d, 0x1078, 0x4051,
+	0x781b, 0x00f5, 0x007c, 0x6818, 0xd0fc, 0x0040, 0x3049, 0x681b,
+	0x001d, 0x1078, 0x4051, 0x781b, 0x00c5, 0x007c, 0xa584, 0x000f,
+	0x00c0, 0x306b, 0x7000, 0x0079, 0x3055, 0x2966, 0x305d, 0x305f,
+	0x3d04, 0x3d04, 0x3d04, 0x305d, 0x305d, 0x1078, 0x290c, 0x1078,
+	0x3d73, 0x6008, 0xa084, 0xfbef, 0x600a, 0x1078, 0x3cf5, 0x0040,
+	0x3d04, 0x0078, 0x2966, 0x78e4, 0xa005, 0x00d0, 0x3004, 0x3208,
+	0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x307c,
+	0xa18c, 0x0300, 0x0078, 0x307e, 0xa18c, 0x0400, 0x0040, 0x3084,
+	0x0018, 0x3004, 0x0078, 0x3086, 0x0028, 0x3004, 0x2008, 0xa084,
+	0x0030, 0x00c0, 0x308e, 0x781b, 0x005b, 0x007c, 0x78ec, 0xa084,
+	0x0003, 0x0040, 0x308b, 0x2100, 0xa184, 0x0007, 0x0079, 0x3098,
+	0x30a7, 0x30ab, 0x30a2, 0x30a0, 0x42de, 0x42de, 0x30a0, 0x42d8,
+	0x1078, 0x290c, 0x1078, 0x4059, 0x781b, 0x0061, 0x007c, 0x1078,
+	0x4059, 0x0078, 0x42ba, 0x1078, 0x4059, 0x781b, 0x00f5, 0x007c,
+	0x1078, 0x4059, 0x781b, 0x00c5, 0x007c, 0x2300, 0x0079, 0x30b8,
+	0x30bd, 0x30bb, 0x30bf, 0x1078, 0x290c, 0x0078, 0x38cf, 0x681b,
+	0x0016, 0x78a3, 0x0000, 0x79e4, 0xa184, 0x0030, 0x0040, 0x38cf,
+	0x78ec, 0xa084, 0x0003, 0x0040, 0x38cf, 0xa184, 0x0100, 0x0040,
+	0x30c3, 0xa184, 0x0007, 0x0079, 0x30d5, 0x30dd, 0x30ab, 0x3023,
+	0x4296, 0x42de, 0x42de, 0x4296, 0x42d8, 0x1078, 0x42a2, 0x007c,
+	0xa282, 0x0005, 0x0050, 0x30e6, 0x1078, 0x290c, 0x2300, 0x0079,
+	0x30e9, 0x30ec, 0x330b, 0x3316, 0x2200, 0x0079, 0x30ef, 0x3109,
+	0x30f6, 0x3109, 0x30f4, 0x32ee, 0x1078, 0x290c, 0x789b, 0x0018,
+	0x78a8, 0xa084, 0x00ff, 0xa082, 0x0020, 0x0048, 0x4040, 0xa08a,
+	0x0004, 0x00c8, 0x4040, 0x0079, 0x3105, 0x4040, 0x4040, 0x4040,
+	0x3fea, 0x789b, 0x0018, 0x79a8, 0xa184, 0x0080, 0x0040, 0x311a,
+	0x0078, 0x4040, 0x7000, 0xa005, 0x00c0, 0x3110, 0x2011, 0x0004,
+	0x0078, 0x3aba, 0xa184, 0x00ff, 0xa08a, 0x0010, 0x00c8, 0x4040,
+	0x0079, 0x3122, 0x3134, 0x3132, 0x3149, 0x314d, 0x320f, 0x4040,
+	0x4040, 0x3211, 0x4040, 0x4040, 0x32ea, 0x32ea, 0x4040, 0x4040,
+	0x4040, 0x32ec, 0x1078, 0x290c, 0xd6e4, 0x0040, 0x313f, 0x2001,
+	0x0300, 0x8000, 0x8000, 0x783a, 0x781b, 0x00c0, 0x007c, 0x6818,
+	0xd0fc, 0x0040, 0x3147, 0x681b, 0x001d, 0x0078, 0x3137, 0x0078,
+	0x4296, 0x681b, 0x001d, 0x0078, 0x404a, 0x6920, 0x6922, 0xa684,
+	0x1800, 0x00c0, 0x31a1, 0x6820, 0xd084, 0x00c0, 0x31a7, 0x6818,
+	0xa086, 0x0008, 0x00c0, 0x315e, 0x681b, 0x0000, 0xd6d4, 0x0040,
+	0x320c, 0xd6bc, 0x0040, 0x319e, 0x7087, 0x0000, 0x6818, 0xa084,
+	0x003f, 0xa08a, 0x000d, 0x0050, 0x319e, 0xa08a, 0x000c, 0x7186,
 	0x2001, 0x000c, 0x800c, 0x718a, 0x789b, 0x0061, 0x78aa, 0x157e,
-	0x137e, 0x147e, 0x017e, 0x3208, 0xa18c, 0x0300, 0x0040, 0x3110,
-	0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x310c,
-	0x20a1, 0x012b, 0x0078, 0x3112, 0x20a1, 0x022b, 0x0078, 0x3112,
+	0x137e, 0x147e, 0x017e, 0x3208, 0xa18c, 0x0300, 0x0040, 0x3190,
+	0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x318c,
+	0x20a1, 0x012b, 0x0078, 0x3192, 0x20a1, 0x022b, 0x0078, 0x3192,
 	0x20a1, 0x012b, 0x017f, 0x789b, 0x0000, 0x8000, 0x80ac, 0xad80,
 	0x000b, 0x2098, 0x53a6, 0x147f, 0x137f, 0x157f, 0x781b, 0x0064,
-	0x007c, 0xd6e4, 0x0040, 0x3127, 0x781b, 0x0076, 0x007c, 0xa684,
-	0x0060, 0x0040, 0x3189, 0xd6dc, 0x0040, 0x3189, 0xd6fc, 0x00c0,
-	0x3133, 0x0078, 0x314a, 0xc6fc, 0x7e5a, 0x6eb6, 0x7adc, 0x79d8,
-	0x78d0, 0x801b, 0x00c8, 0x313d, 0x8000, 0xa084, 0x003f, 0xa108,
+	0x007c, 0xd6e4, 0x0040, 0x31a7, 0x781b, 0x0076, 0x007c, 0xa684,
+	0x0060, 0x0040, 0x3209, 0xd6dc, 0x0040, 0x3209, 0xd6fc, 0x00c0,
+	0x31b3, 0x0078, 0x31ca, 0xc6fc, 0x7e5a, 0x6eb6, 0x7adc, 0x79d8,
+	0x78d0, 0x801b, 0x00c8, 0x31bd, 0x8000, 0xa084, 0x003f, 0xa108,
 	0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200,
-	0xa303, 0x68ae, 0xd6f4, 0x0040, 0x3150, 0xc6f4, 0x7e5a, 0x6eb6,
-	0x7000, 0xa086, 0x0003, 0x00c0, 0x315e, 0x007e, 0x1078, 0x4326,
-	0x1078, 0x45f7, 0x007f, 0x781b, 0x0073, 0x007c, 0xa006, 0x1078,
-	0x46e5, 0x6ab0, 0x69ac, 0x6c98, 0x6b94, 0x2200, 0xa105, 0x0040,
-	0x316d, 0x2200, 0xa422, 0x2100, 0xa31b, 0x6caa, 0x7cd2, 0x7cda,
-	0x6ba6, 0x7bd6, 0x7bde, 0x2300, 0xa405, 0x00c0, 0x317d, 0xc6f5,
+	0xa303, 0x68ae, 0xd6f4, 0x0040, 0x31d0, 0xc6f4, 0x7e5a, 0x6eb6,
+	0x7000, 0xa086, 0x0003, 0x00c0, 0x31de, 0x007e, 0x1078, 0x44fb,
+	0x1078, 0x4834, 0x007f, 0x781b, 0x0073, 0x007c, 0xa006, 0x1078,
+	0x493a, 0x6ab0, 0x69ac, 0x6c98, 0x6b94, 0x2200, 0xa105, 0x0040,
+	0x31ed, 0x2200, 0xa422, 0x2100, 0xa31b, 0x6caa, 0x7cd2, 0x7cda,
+	0x6ba6, 0x7bd6, 0x7bde, 0x2300, 0xa405, 0x00c0, 0x31fd, 0xc6f5,
 	0x7e5a, 0x6eb6, 0x781b, 0x0073, 0x007c, 0x781b, 0x0073, 0x2200,
-	0xa115, 0x00c0, 0x3186, 0x1078, 0x45f7, 0x007c, 0x1078, 0x462d,
+	0xa115, 0x00c0, 0x3206, 0x1078, 0x4834, 0x007c, 0x1078, 0x486c,
 	0x007c, 0x781b, 0x0076, 0x007c, 0x781b, 0x0064, 0x007c, 0x1078,
-	0x28ec, 0x0078, 0x31dd, 0x6920, 0xd1c4, 0x0040, 0x31a6, 0xc1c4,
+	0x290c, 0x0078, 0x325d, 0x6920, 0xd1c4, 0x0040, 0x3226, 0xc1c4,
 	0x6922, 0x0c7e, 0x7058, 0x2060, 0x6000, 0xc0e4, 0x6002, 0x6004,
-	0xa084, 0xfff5, 0x6006, 0x0c7f, 0x0078, 0x31d1, 0xd1cc, 0x0040,
-	0x31d1, 0xc1cc, 0x6922, 0x0c7e, 0x7058, 0x2060, 0x6000, 0xc0ec,
+	0xa084, 0xfff5, 0x6006, 0x0c7f, 0x0078, 0x3251, 0xd1cc, 0x0040,
+	0x3251, 0xc1cc, 0x6922, 0x0c7e, 0x7058, 0x2060, 0x6000, 0xc0ec,
 	0x6002, 0x6004, 0xc0a4, 0x6006, 0x2008, 0x2c48, 0x0c7f, 0xd19c,
-	0x0040, 0x31d1, 0x1078, 0x3fdd, 0x1078, 0x3cda, 0x88ff, 0x0040,
-	0x31d1, 0x789b, 0x0060, 0x2800, 0x78aa, 0x7e58, 0xc695, 0x7e5a,
-	0xd6d4, 0x00c0, 0x31ce, 0x781b, 0x0061, 0x007c, 0x781b, 0x0075,
-	0x007c, 0x7e58, 0xd6d4, 0x00c0, 0x31d8, 0x781b, 0x0064, 0x007c,
-	0x781b, 0x0076, 0x007c, 0x0078, 0x3ea2, 0x2019, 0x0000, 0x7990,
-	0xa18c, 0x0007, 0x00c0, 0x31eb, 0x6820, 0xa084, 0x0100, 0x0040,
-	0x31db, 0x2009, 0x0008, 0x789b, 0x0010, 0x78a8, 0xa094, 0x00ff,
-	0xa286, 0x0001, 0x00c0, 0x3207, 0x2300, 0x7ca8, 0xa400, 0x2018,
-	0xa102, 0x0040, 0x31ff, 0x0048, 0x31ff, 0x0078, 0x3201, 0x0078,
-	0x3193, 0x24a8, 0x7aa8, 0x00f0, 0x3201, 0x0078, 0x31ed, 0xa284,
-	0x00f0, 0xa086, 0x0020, 0x00c0, 0x325b, 0x8318, 0x8318, 0x2300,
-	0xa102, 0x0040, 0x3217, 0x0048, 0x3217, 0x0078, 0x3258, 0xa286,
-	0x0023, 0x0040, 0x31db, 0x681c, 0xa084, 0xfff1, 0x681e, 0x7e58,
+	0x0040, 0x3251, 0x1078, 0x4183, 0x1078, 0x3e7c, 0x88ff, 0x0040,
+	0x3251, 0x789b, 0x0060, 0x2800, 0x78aa, 0x7e58, 0xc695, 0x7e5a,
+	0xd6d4, 0x00c0, 0x324e, 0x781b, 0x0061, 0x007c, 0x781b, 0x0075,
+	0x007c, 0x7e58, 0xd6d4, 0x00c0, 0x3258, 0x781b, 0x0064, 0x007c,
+	0x781b, 0x0076, 0x007c, 0x0078, 0x4045, 0x2019, 0x0000, 0x7990,
+	0xa18c, 0x0007, 0x00c0, 0x326b, 0x6820, 0xa084, 0x0100, 0x0040,
+	0x325b, 0x2009, 0x0008, 0x789b, 0x0010, 0x78a8, 0xa094, 0x00ff,
+	0xa286, 0x0001, 0x00c0, 0x3287, 0x2300, 0x7ca8, 0xa400, 0x2018,
+	0xa102, 0x0040, 0x327f, 0x0048, 0x327f, 0x0078, 0x3281, 0x0078,
+	0x3213, 0x24a8, 0x7aa8, 0x00f0, 0x3281, 0x0078, 0x326d, 0xa284,
+	0x00f0, 0xa086, 0x0020, 0x00c0, 0x32db, 0x8318, 0x8318, 0x2300,
+	0xa102, 0x0040, 0x3297, 0x0048, 0x3297, 0x0078, 0x32d8, 0xa286,
+	0x0023, 0x0040, 0x325b, 0x681c, 0xa084, 0xfff1, 0x681e, 0x7e58,
 	0xa684, 0xfff1, 0xc0a5, 0x2030, 0x7e5a, 0x6008, 0xc0a5, 0x600a,
 	0x0c7e, 0x7058, 0x2060, 0x6004, 0x2008, 0x2c48, 0x0c7f, 0xd1a4,
-	0x0040, 0x3238, 0x1078, 0x3fdd, 0x1078, 0x3df6, 0x0078, 0x3246,
+	0x0040, 0x32b8, 0x1078, 0x4183, 0x1078, 0x3f99, 0x0078, 0x32c6,
 	0x0c7e, 0x7058, 0x2060, 0x6004, 0x2008, 0x2c48, 0x0c7f, 0xd19c,
-	0x0040, 0x31d1, 0x1078, 0x3fdd, 0x1078, 0x3cda, 0x88ff, 0x0040,
-	0x31d1, 0x789b, 0x0060, 0x2800, 0x78aa, 0xc695, 0x7e5a, 0xd6d4,
-	0x00c0, 0x3255, 0x781b, 0x0061, 0x007c, 0x781b, 0x0075, 0x007c,
-	0x7aa8, 0x0078, 0x31ed, 0x8318, 0x2300, 0xa102, 0x0040, 0x3264,
-	0x0048, 0x3264, 0x0078, 0x31ed, 0xa284, 0x0080, 0x00c0, 0x3ea7,
-	0x0078, 0x3ea2, 0x0078, 0x3ea7, 0x0078, 0x3e9d, 0x7058, 0xa04d,
+	0x0040, 0x3251, 0x1078, 0x4183, 0x1078, 0x3e7c, 0x88ff, 0x0040,
+	0x3251, 0x789b, 0x0060, 0x2800, 0x78aa, 0xc695, 0x7e5a, 0xd6d4,
+	0x00c0, 0x32d5, 0x781b, 0x0061, 0x007c, 0x781b, 0x0075, 0x007c,
+	0x7aa8, 0x0078, 0x326d, 0x8318, 0x2300, 0xa102, 0x0040, 0x32e4,
+	0x0048, 0x32e4, 0x0078, 0x326d, 0xa284, 0x0080, 0x00c0, 0x404a,
+	0x0078, 0x4045, 0x0078, 0x404a, 0x0078, 0x4040, 0x7058, 0xa04d,
 	0x789b, 0x0018, 0x78a8, 0xa084, 0x00ff, 0xa08e, 0x0001, 0x0040,
-	0x327b, 0x1078, 0x28ec, 0x7aa8, 0xa294, 0x00ff, 0x78a8, 0xa084,
-	0x00ff, 0xa08a, 0x0004, 0x00c8, 0x3e9d, 0x0079, 0x3287, 0x3e9d,
-	0x3c2c, 0x3e9d, 0x3d9e, 0xa282, 0x0000, 0x00c0, 0x3291, 0x1078,
-	0x28ec, 0x1078, 0x3eae, 0x781b, 0x0075, 0x007c, 0xa282, 0x0003,
-	0x00c0, 0x329c, 0x1078, 0x28ec, 0xd4fc, 0x00c0, 0x32bc, 0x7064,
-	0xa005, 0x0040, 0x32a5, 0x1078, 0x28ec, 0x6f14, 0x7776, 0xa7bc,
-	0x8f00, 0x1078, 0x3fe1, 0x6008, 0xa085, 0x0021, 0x600a, 0x8738,
-	0xa784, 0x001f, 0x00c0, 0x32a9, 0x1078, 0x3eb2, 0x7067, 0x0002,
-	0x701f, 0x0009, 0x0078, 0x32be, 0x1078, 0x3ebe, 0x781b, 0x0075,
-	0x007c, 0xa282, 0x0004, 0x0050, 0x32c7, 0x1078, 0x28ec, 0x2300,
-	0x0079, 0x32ca, 0x32cd, 0x346b, 0x34ae, 0xa286, 0x0003, 0x0040,
-	0x3304, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0, 0x71d4, 0xd1b4, 0x0078,
-	0x32fc, 0x0040, 0x32fc, 0x7868, 0xa084, 0x00ff, 0x00c0, 0x32fc,
-	0xa282, 0x0002, 0x00c8, 0x32fc, 0x0d7e, 0x783b, 0x8300, 0x781b,
-	0x004c, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de,
-	0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030, 0x0d7f,
-	0x2001, 0x0000, 0x0078, 0x3308, 0x783b, 0x1300, 0x781b, 0x004a,
-	0x2001, 0x0000, 0x0078, 0x3308, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0,
-	0x704a, 0x68a0, 0xd0ec, 0x0040, 0x3310, 0x6008, 0xc08d, 0x600a,
-	0xa284, 0x000f, 0x0079, 0x3314, 0x344b, 0x3321, 0x331e, 0x35ae,
-	0x35f2, 0x2946, 0x331c, 0x331c, 0x1078, 0x28ec, 0x6008, 0xc0d4,
-	0x600a, 0xd6e4, 0x00c0, 0x3328, 0x1078, 0x4326, 0x0040, 0x3404,
-	0x7868, 0xa08c, 0x00ff, 0x0040, 0x3369, 0xa186, 0x0008, 0x00c0,
-	0x333e, 0x1078, 0x3bd2, 0x6008, 0xc0a4, 0x600a, 0x1078, 0x3b6b,
-	0x0040, 0x3369, 0x1078, 0x4326, 0x0078, 0x3353, 0xa186, 0x0028,
-	0x00c0, 0x3369, 0x1078, 0x4326, 0x6008, 0xc0a4, 0x600a, 0x6018,
-	0xa005, 0x0040, 0x3353, 0x8001, 0x601a, 0x0040, 0x3353, 0x8001,
-	0x0040, 0x3353, 0x601e, 0x6820, 0xd084, 0x0040, 0x2946, 0xc084,
-	0x6822, 0x705c, 0x0c7e, 0x2060, 0x6800, 0x6002, 0x0c7f, 0x6004,
-	0x6802, 0xa005, 0x2d00, 0x00c0, 0x3366, 0x6002, 0x6006, 0x0078,
-	0x2946, 0x017e, 0x81ff, 0x00c0, 0x33b0, 0x7000, 0xa086, 0x0030,
-	0x0040, 0x33b0, 0x71d4, 0xd1b4, 0x00c0, 0x3397, 0x7060, 0xa005,
-	0x00c0, 0x33b0, 0x70a4, 0xa086, 0x0001, 0x0040, 0x33b0, 0x7003,
-	0x0000, 0x047e, 0x057e, 0x077e, 0x067e, 0x0c7e, 0x0d7e, 0x1078,
-	0x296c, 0x0d7f, 0x0c7f, 0x067f, 0x077f, 0x057f, 0x047f, 0x71d4,
-	0xd1b4, 0x00c0, 0x33b0, 0x7003, 0x0040, 0x0078, 0x33b0, 0x1078,
-	0x411c, 0x00c0, 0x33b0, 0x781b, 0x005b, 0x0d7e, 0x70bc, 0xa06d,
-	0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da,
-	0xc1b4, 0x71d6, 0x7003, 0x0030, 0x7808, 0xc08d, 0x780a, 0x0d7f,
-	0x1078, 0x34e8, 0x017f, 0x81ff, 0x0040, 0x3403, 0xa684, 0xdf00,
-	0x681e, 0x682b, 0x0000, 0x6f14, 0xa186, 0x0002, 0x00c0, 0x3404,
-	0x70d4, 0xd0b4, 0x0040, 0x33d1, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8,
-	0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a,
-	0x0c7f, 0x6820, 0xd0dc, 0x00c0, 0x3404, 0x8717, 0xa294, 0x000f,
-	0x8213, 0x8213, 0x8213, 0xb284, 0x0300, 0x0040, 0x33e3, 0xa290,
-	0x4ec0, 0x0078, 0x33e5, 0xa290, 0x4f40, 0xa290, 0x0000, 0x221c,
-	0xd3c4, 0x00c0, 0x33ed, 0x0078, 0x33f3, 0x8210, 0x2204, 0xa085,
-	0x0018, 0x2012, 0x8211, 0xd3d4, 0x0040, 0x33fe, 0x68a0, 0xd0c4,
-	0x00c0, 0x33fe, 0x1078, 0x3562, 0x0078, 0x2946, 0x6008, 0xc08d,
-	0x600a, 0x0078, 0x3404, 0x692a, 0x6916, 0x6818, 0xd0fc, 0x0040,
-	0x340b, 0x7048, 0x681a, 0xa68c, 0xdf00, 0x691e, 0x6410, 0x84ff,
-	0x0040, 0x3420, 0x2009, 0x4a02, 0x2104, 0x8001, 0x200a, 0x8421,
-	0x6412, 0x00c0, 0x3420, 0x2021, 0x4a04, 0x2404, 0xc0a5, 0x2022,
-	0x6018, 0xa005, 0x0040, 0x3428, 0x8001, 0x601a, 0x00c0, 0x342b,
-	0x6008, 0xc0a4, 0x600a, 0x6820, 0xd084, 0x00c0, 0x3437, 0x6800,
-	0xa005, 0x00c0, 0x3434, 0x6002, 0x6006, 0x0078, 0x343b, 0x705c,
-	0x2060, 0x6800, 0x6002, 0x2061, 0x4a00, 0x6887, 0x0103, 0x2d08,
-	0x206b, 0x0000, 0x6068, 0xa005, 0x616a, 0x0040, 0x344a, 0x2d02,
-	0x0078, 0x344b, 0x616e, 0x7200, 0xa286, 0x0030, 0x0040, 0x345b,
-	0xa286, 0x0040, 0x00c0, 0x2946, 0x7003, 0x0002, 0x704c, 0x2068,
-	0x68c4, 0x2060, 0x007c, 0x7003, 0x0002, 0x70bc, 0xa06d, 0x68bc,
-	0x7042, 0x70b8, 0xa065, 0x68c0, 0x705a, 0x2d00, 0x704e, 0xad80,
-	0x0009, 0x7046, 0x007c, 0xa282, 0x0004, 0x0048, 0x3471, 0x1078,
-	0x28ec, 0x2200, 0x0079, 0x3474, 0x3478, 0x3489, 0x3496, 0x3489,
-	0xa586, 0x1300, 0x0040, 0x3489, 0xa586, 0x8300, 0x00c0, 0x346f,
-	0x7003, 0x0000, 0x6018, 0x8001, 0x601a, 0x6008, 0xa084, 0xfbef,
-	0x600a, 0x7000, 0xa086, 0x0005, 0x0040, 0x3493, 0x1078, 0x3eae,
-	0x781b, 0x0075, 0x007c, 0x781b, 0x0076, 0x007c, 0x7890, 0x8007,
-	0x8001, 0xa084, 0x0007, 0xa080, 0x0018, 0x789a, 0x79a8, 0xa18c,
-	0x00ff, 0xa186, 0x0003, 0x0040, 0x34ab, 0xa186, 0x0000, 0x0040,
-	0x34ab, 0x0078, 0x3e9d, 0x781b, 0x0076, 0x007c, 0x6820, 0xc095,
-	0x6822, 0x82ff, 0x00c0, 0x34b8, 0x1078, 0x3eae, 0x0078, 0x34bf,
-	0x8211, 0x0040, 0x34bd, 0x1078, 0x28ec, 0x1078, 0x3ebe, 0x781b,
-	0x0075, 0x007c, 0x1078, 0x4131, 0x7830, 0xa084, 0x00c0, 0x00c0,
-	0x34e5, 0x017e, 0x3208, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec,
-	0x007f, 0x0040, 0x34d7, 0xa18c, 0x0300, 0x0078, 0x34d9, 0xa18c,
-	0x0400, 0x017f, 0x0040, 0x34e0, 0x0018, 0x34e5, 0x0078, 0x34e2,
-	0x0028, 0x34e5, 0x791a, 0xa006, 0x007c, 0xa085, 0x0001, 0x007c,
-	0xa684, 0x0060, 0x00c0, 0x34f2, 0x682f, 0x0000, 0x6833, 0x0000,
-	0x0078, 0x3561, 0xd6dc, 0x00c0, 0x350a, 0x68b4, 0xd0dc, 0x00c0,
-	0x350a, 0x6998, 0x6a94, 0x692e, 0x6a32, 0x7048, 0xa005, 0x00c0,
-	0x3507, 0x2200, 0xa105, 0x0040, 0x4326, 0x704b, 0x0015, 0x0078,
-	0x4326, 0x007c, 0xd6ac, 0x0040, 0x3530, 0xd6f4, 0x0040, 0x3516,
-	0x682f, 0x0000, 0x6833, 0x0000, 0x0078, 0x4326, 0x68b4, 0xa084,
-	0x4000, 0xa635, 0xd6f4, 0x00c0, 0x3510, 0x7048, 0xa005, 0x00c0,
-	0x3523, 0x704b, 0x0015, 0xd6dc, 0x00c0, 0x352c, 0x68b4, 0xd0dc,
-	0x0040, 0x352c, 0x6ca8, 0x6da4, 0x6c2e, 0x6d32, 0x0078, 0x4326,
-	0xd6f4, 0x0040, 0x3539, 0x682f, 0x0000, 0x6833, 0x0000, 0x0078,
-	0x4326, 0x68b4, 0xa084, 0x4800, 0xa635, 0xd6f4, 0x00c0, 0x3533,
-	0x7048, 0xa005, 0x00c0, 0x3546, 0x704b, 0x0015, 0x2408, 0x2510,
-	0x2700, 0x80fb, 0x00c8, 0x354d, 0x8000, 0xa084, 0x003f, 0xa108,
-	0xa291, 0x0000, 0x692e, 0x6a32, 0x2100, 0xa205, 0x00c0, 0x355a,
-	0x0078, 0x4326, 0x7000, 0xa086, 0x0006, 0x0040, 0x3561, 0x0078,
-	0x4326, 0x007c, 0x6008, 0xc0cd, 0xd3cc, 0x0040, 0x3568, 0xc08d,
-	0x600a, 0x681b, 0x0006, 0x688f, 0x0000, 0x6893, 0x0000, 0x6a30,
-	0x692c, 0x6a3e, 0x6942, 0x682f, 0x0003, 0x6833, 0x0000, 0x6837,
-	0x0020, 0x6897, 0x0000, 0x689b, 0x0020, 0x7000, 0x0079, 0x3580,
-	0x2946, 0x3592, 0x358a, 0x3588, 0x3588, 0x3588, 0x3588, 0x3588,
-	0x1078, 0x28ec, 0x6820, 0xd084, 0x00c0, 0x3592, 0x1078, 0x3bb5,
-	0x0078, 0x3598, 0x705c, 0x2c50, 0x2060, 0x6800, 0x6002, 0x2a60,
-	0x3208, 0xa18c, 0x0300, 0x0040, 0x35a1, 0x2021, 0x4a58, 0x0078,
-	0x35a3, 0x2021, 0x4a98, 0x2404, 0xa005, 0x0040, 0x35aa, 0x2020,
-	0x0078, 0x35a3, 0x2d22, 0x206b, 0x0000, 0x007c, 0x1078, 0x3bbc,
-	0x1078, 0x3bd2, 0x6008, 0xc0cc, 0x600a, 0x682b, 0x0000, 0x789b,
-	0x000e, 0x6f14, 0x6817, 0x0002, 0x3208, 0xa18c, 0x0300, 0x0040,
-	0x35c5, 0x2009, 0x0000, 0x0078, 0x35c7, 0x2009, 0x0001, 0x1078,
-	0x471a, 0xd6dc, 0x0040, 0x35cf, 0x691c, 0xc1ed, 0x691e, 0x6818,
-	0xd0fc, 0x0040, 0x35de, 0x7868, 0xa08c, 0x00ff, 0x0040, 0x35dc,
-	0x681b, 0x001e, 0x0078, 0x35de, 0x681b, 0x0000, 0xb284, 0x0300,
-	0x00c0, 0x35e6, 0x2021, 0x4a98, 0x0078, 0x35e8, 0x2021, 0x4a58,
-	0x6800, 0x2022, 0x6a3c, 0x6940, 0x6a32, 0x692e, 0x1078, 0x202a,
-	0x0078, 0x2946, 0x7cd8, 0x7ddc, 0x7fd0, 0x1078, 0x34e8, 0x682b,
-	0x0000, 0x789b, 0x000e, 0x6f14, 0x1078, 0x4135, 0xa08c, 0x00ff,
-	0x6916, 0x6818, 0xd0fc, 0x0040, 0x3607, 0x7048, 0x681a, 0xa68c,
-	0xdf00, 0x691e, 0x7067, 0x0000, 0x0078, 0x2946, 0x7000, 0xa005,
-	0x00c0, 0x3614, 0x0078, 0x2946, 0xa006, 0x1078, 0x4326, 0x6817,
-	0x0000, 0x681b, 0x0014, 0xa68c, 0xdf00, 0x691e, 0x682b, 0x0000,
-	0x6820, 0xa084, 0x00ff, 0x6822, 0x7000, 0x0079, 0x3627, 0x2946,
-	0x3634, 0x3631, 0x3636, 0x3636, 0x3636, 0x362f, 0x362f, 0x1078,
-	0x28ec, 0x6008, 0xc0d4, 0x600a, 0x1078, 0x3bd2, 0x6008, 0xc0a4,
-	0x600a, 0x0078, 0x3b85, 0x2300, 0x0079, 0x363e, 0x3641, 0x3643,
-	0x369f, 0x1078, 0x28ec, 0xd6fc, 0x00c0, 0x3686, 0x7000, 0xa00d,
-	0x0079, 0x364a, 0x2946, 0x3654, 0x3654, 0x3678, 0x3654, 0x3683,
-	0x3652, 0x3652, 0x1078, 0x28ec, 0xa684, 0x0060, 0xa086, 0x0060,
-	0x00c0, 0x3675, 0xc6ac, 0xc6f4, 0xc6ed, 0x7e5a, 0x681c, 0xc0ac,
-	0x681e, 0xa186, 0x0002, 0x0040, 0x3667, 0x1078, 0x4326, 0x1078,
-	0x45f7, 0x781b, 0x0076, 0x71d4, 0xd1b4, 0x00c0, 0x2942, 0x70a4,
-	0xa086, 0x0001, 0x00c0, 0x2989, 0x007c, 0xd6ec, 0x0040, 0x365c,
-	0x6818, 0xd0fc, 0x0040, 0x3683, 0x681b, 0x0015, 0xd6f4, 0x0040,
-	0x3683, 0x681b, 0x0007, 0x1078, 0x40d5, 0x007c, 0xc6fc, 0x7e5a,
-	0x7adc, 0x79d8, 0x78d0, 0x801b, 0x00c8, 0x368f, 0x8000, 0xa084,
-	0x003f, 0xa108, 0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2,
-	0x6b94, 0x2200, 0xa303, 0x68ae, 0x781b, 0x0076, 0x007c, 0x1078,
-	0x28ec, 0x2300, 0x0079, 0x36a4, 0x36a9, 0x36c5, 0x3719, 0x1078,
-	0x28ec, 0x7000, 0x0079, 0x36ac, 0x36b4, 0x36b6, 0x36b6, 0x36b4,
-	0x36b4, 0x36b4, 0x36b4, 0x36b4, 0x1078, 0x28ec, 0x1078, 0x45f7,
-	0x681c, 0xc0b4, 0x681e, 0x70d4, 0xd0b4, 0x00c0, 0x2942, 0x70a4,
-	0xa086, 0x0001, 0x00c0, 0x2989, 0x007c, 0xd6fc, 0x00c0, 0x3709,
-	0x7000, 0xa00d, 0x0079, 0x36cc, 0x2946, 0x36dc, 0x36d6, 0x3700,
-	0x36dc, 0x3706, 0x36d4, 0x36d4, 0x1078, 0x28ec, 0x6894, 0x78d6,
-	0x78de, 0x6898, 0x78d2, 0x78da, 0xa684, 0x0060, 0xa086, 0x0060,
-	0x00c0, 0x36fd, 0xa6b4, 0xbfbf, 0xc6ed, 0x7e5a, 0xa186, 0x0002,
-	0x0040, 0x36ec, 0x1078, 0x4326, 0x1078, 0x45f7, 0x781b, 0x0076,
-	0x681c, 0xc0b4, 0x681e, 0x71d4, 0xd1b4, 0x00c0, 0x2942, 0x70a4,
-	0xa086, 0x0001, 0x00c0, 0x2989, 0x007c, 0xd6ec, 0x0040, 0x36e4,
-	0x6818, 0xd0fc, 0x0040, 0x3706, 0x681b, 0x0007, 0x781b, 0x00f0,
-	0x007c, 0xc6fc, 0x7e5a, 0x7adc, 0x79d8, 0x6b98, 0x2100, 0xa302,
-	0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae, 0x79d2, 0x781b, 0x0076,
-	0x007c, 0xd6dc, 0x0040, 0x3722, 0x782b, 0x3009, 0x781b, 0x0076,
-	0x0078, 0x2942, 0x7884, 0xc0ac, 0x7886, 0x78e4, 0xa084, 0x0008,
-	0x00c0, 0x3735, 0xa484, 0x0200, 0x0040, 0x372f, 0xc6f5, 0xc6dd,
-	0x7e5a, 0x781b, 0x0076, 0x0078, 0x2942, 0x6820, 0xc095, 0x6822,
-	0x1078, 0x4062, 0xc6dd, 0x1078, 0x3eae, 0x781b, 0x0075, 0x0078,
-	0x2942, 0x2300, 0x0079, 0x3744, 0x3747, 0x3749, 0x374b, 0x1078,
-	0x28ec, 0x0078, 0x3ea7, 0xd6d4, 0x00c0, 0x3771, 0x79e4, 0xd1ac,
-	0x0040, 0x3759, 0x78ec, 0xa084, 0x0003, 0x0040, 0x3759, 0x782b,
-	0x3009, 0x789b, 0x0060, 0x78ab, 0x0000, 0xa684, 0xfffb, 0x785a,
-	0x79e4, 0xd1ac, 0x0040, 0x3769, 0x78ec, 0xa084, 0x0003, 0x00c0,
-	0x376d, 0x2001, 0x0014, 0x0078, 0x3304, 0xa184, 0x0007, 0x0079,
-	0x37a7, 0x7a90, 0xa294, 0x0007, 0x789b, 0x0060, 0x79a8, 0x81ff,
-	0x0040, 0x37a5, 0x789b, 0x0010, 0x7ba8, 0xa384, 0x0001, 0x00c0,
-	0x3798, 0x7ba8, 0x7ba8, 0xa386, 0x0001, 0x00c0, 0x378b, 0x2009,
-	0xfff7, 0x0078, 0x3791, 0xa386, 0x0003, 0x00c0, 0x3798, 0x2009,
-	0xffef, 0x0c7e, 0x7058, 0x2060, 0x6004, 0xa104, 0x6006, 0x0c7f,
-	0x789b, 0x0060, 0x78ab, 0x0000, 0xa684, 0xfffb, 0x785a, 0x782b,
-	0x3009, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0078, 0x40c9, 0x2fae,
-	0x2fb8, 0x37b1, 0x37b7, 0x37af, 0x37af, 0x40c9, 0x40c9, 0x1078,
-	0x28ec, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0078, 0x40cf, 0x6920,
-	0xa18c, 0xfcff, 0x6922, 0x0078, 0x40c9, 0x79e4, 0xa184, 0x0030,
-	0x0040, 0x37c7, 0x78ec, 0xa084, 0x0003, 0x00c0, 0x37f1, 0x7000,
-	0xa086, 0x0004, 0x00c0, 0x37e1, 0x7064, 0xa086, 0x0002, 0x00c0,
-	0x37d7, 0x2011, 0x0002, 0x2019, 0x0000, 0x0078, 0x2e43, 0x7064,
-	0xa086, 0x0006, 0x0040, 0x37d1, 0x7064, 0xa086, 0x0004, 0x0040,
-	0x37d1, 0x7000, 0xa086, 0x0000, 0x0040, 0x2942, 0x6820, 0xd0ac,
-	0x00c0, 0x37ed, 0x6818, 0xc0fd, 0x681a, 0x2001, 0x0014, 0x0078,
-	0x3304, 0xa184, 0x0007, 0x0079, 0x37f5, 0x40c9, 0x40c9, 0x37fd,
-	0x40c9, 0x4111, 0x4111, 0x40c9, 0x40c9, 0xd6bc, 0x0040, 0x383f,
-	0x7184, 0x81ff, 0x0040, 0x383f, 0xa182, 0x000d, 0x00d0, 0x380c,
-	0x7087, 0x0000, 0x0078, 0x3811, 0xa182, 0x000c, 0x7086, 0x2009,
-	0x000c, 0x789b, 0x0061, 0x79aa, 0x157e, 0x137e, 0x147e, 0x7088,
-	0x8114, 0xa210, 0x728a, 0xa080, 0x000b, 0xad00, 0x2098, 0xb284,
-	0x0300, 0x0040, 0x3833, 0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec,
-	0x007f, 0x0040, 0x382f, 0x20a1, 0x012b, 0x0078, 0x3835, 0x20a1,
-	0x022b, 0x0078, 0x3835, 0x20a1, 0x012b, 0x789b, 0x0000, 0x8108,
-	0x81ac, 0x53a6, 0x147f, 0x137f, 0x157f, 0x0078, 0x40cf, 0xd6d4,
-	0x00c0, 0x3893, 0x6820, 0xd084, 0x0040, 0x40cf, 0xa68c, 0x0060,
-	0xa684, 0x0060, 0x0040, 0x3851, 0xa086, 0x0060, 0x00c0, 0x3851,
-	0xc1f5, 0xc194, 0x795a, 0x69b6, 0x789b, 0x0060, 0x78ab, 0x0000,
-	0x789b, 0x0061, 0x6818, 0xc0fd, 0x681a, 0x78aa, 0x8008, 0x810c,
-	0x0040, 0x3beb, 0xa18c, 0x00f8, 0x00c0, 0x3beb, 0x157e, 0x137e,
-	0x147e, 0x017e, 0x3208, 0xa18c, 0x0300, 0x0040, 0x387f, 0x007e,
-	0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x387b, 0x20a1,
-	0x012b, 0x0078, 0x3881, 0x20a1, 0x022b, 0x0078, 0x3881, 0x20a1,
-	0x012b, 0x017f, 0x789b, 0x0000, 0x8000, 0x80ac, 0xad80, 0x000b,
-	0x2098, 0x53a6, 0x147f, 0x137f, 0x157f, 0x6814, 0xc0fc, 0x8007,
-	0x7882, 0x0078, 0x40cf, 0x6818, 0xd0fc, 0x0040, 0x3899, 0x681b,
-	0x0008, 0x6820, 0xc0ad, 0x6822, 0x1078, 0x3eb6, 0x781b, 0x00e1,
-	0x007c, 0x2300, 0x0079, 0x38a4, 0x38a9, 0x397b, 0x38a7, 0x1078,
-	0x28ec, 0x7cd8, 0x7ddc, 0x7fd0, 0x82ff, 0x00c0, 0x38d1, 0x7200,
-	0xa286, 0x0003, 0x0040, 0x32d2, 0x71d4, 0xd1b4, 0x0078, 0x38d4,
-	0x0040, 0x38d4, 0x0d7e, 0x783b, 0x8800, 0x781b, 0x004c, 0x70bc,
-	0xa06d, 0x68b4, 0xc0a5, 0x785a, 0x6894, 0x78d6, 0x78de, 0x6898,
-	0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030, 0x0d7f, 0x0078,
-	0x38d8, 0x7200, 0x0078, 0x38d8, 0x783b, 0x1800, 0x781b, 0x004a,
-	0xa284, 0x000f, 0x0079, 0x38dc, 0x3966, 0x391a, 0x38e6, 0x3300,
-	0x38e4, 0x3966, 0x38e4, 0x38e4, 0x1078, 0x28ec, 0x681c, 0xd0ec,
-	0x0040, 0x38ed, 0x6008, 0xc08d, 0x600a, 0x6920, 0xc185, 0x6922,
-	0x6800, 0x6006, 0xa005, 0x00c0, 0x38f6, 0x6002, 0x6008, 0xc0d4,
-	0x600a, 0x681c, 0xa084, 0x000e, 0x00c0, 0x390a, 0xb284, 0x0300,
-	0x0040, 0x3906, 0x2009, 0x90c0, 0x0078, 0x390f, 0x2009, 0x91d0,
-	0x0078, 0x390f, 0x7030, 0x68ba, 0x7140, 0x70cc, 0xa108, 0x2104,
-	0x6802, 0x2d0a, 0x715e, 0xd6dc, 0x00c0, 0x391a, 0xc6fc, 0x6eb6,
-	0x0078, 0x3966, 0x6eb6, 0xa684, 0x0060, 0x0040, 0x3966, 0xd6dc,
-	0x00c0, 0x392d, 0xa684, 0x7fff, 0x68b6, 0x6894, 0x68a6, 0x6898,
-	0x68aa, 0x1078, 0x4326, 0x0078, 0x3966, 0xd6ac, 0x0040, 0x3939,
-	0xa006, 0x1078, 0x4326, 0x2408, 0x2510, 0x69aa, 0x6aa6, 0x0078,
-	0x3949, 0x2408, 0x2510, 0x2700, 0x801b, 0x00c8, 0x3940, 0x8000,
-	0xa084, 0x003f, 0xa108, 0xa291, 0x0000, 0x69aa, 0x6aa6, 0x1078,
-	0x4326, 0xd6fc, 0x0040, 0x3966, 0xa684, 0x7fff, 0x68b6, 0x2510,
-	0x2408, 0xd6ac, 0x00c0, 0x395e, 0x2700, 0x801b, 0x00c8, 0x3959,
-	0x8000, 0xa084, 0x003f, 0xa108, 0xa291, 0x0000, 0x6b98, 0x2100,
-	0xa302, 0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae, 0x7000, 0xa086,
-	0x0030, 0x00c0, 0x2946, 0x7003, 0x0002, 0x70bc, 0xa06d, 0x68bc,
-	0x7042, 0x70b8, 0xa065, 0x68c0, 0x705a, 0x2d00, 0x704e, 0xad80,
-	0x0009, 0x7046, 0x007c, 0xa586, 0x8800, 0x00c0, 0x3988, 0x7003,
-	0x0000, 0x6018, 0x8001, 0x601a, 0x6008, 0xa084, 0xfbef, 0x600a,
-	0x0078, 0x3ea7, 0x7047, 0x0000, 0xa282, 0x0006, 0x0050, 0x3992,
-	0x1078, 0x28ec, 0x2300, 0x0079, 0x3995, 0x3998, 0x39cf, 0x3a01,
-	0x2200, 0x0079, 0x399b, 0x39a1, 0x3ea7, 0x39a3, 0x39a1, 0x3a38,
-	0x3a9b, 0x1078, 0x28ec, 0x7003, 0x0005, 0xb284, 0x0300, 0x0040,
-	0x39ad, 0x2001, 0x91e0, 0x0078, 0x39af, 0x2001, 0x9212, 0x2068,
+	0x32fb, 0x1078, 0x290c, 0x7aa8, 0xa294, 0x00ff, 0x78a8, 0xa084,
+	0x00ff, 0xa08a, 0x0004, 0x00c8, 0x4040, 0x0079, 0x3307, 0x4040,
+	0x3dce, 0x4040, 0x3f41, 0xa282, 0x0000, 0x00c0, 0x3311, 0x1078,
+	0x290c, 0x1078, 0x4051, 0x781b, 0x0075, 0x007c, 0xa282, 0x0003,
+	0x00c0, 0x331c, 0x1078, 0x290c, 0xd4fc, 0x00c0, 0x333c, 0x7064,
+	0xa005, 0x0040, 0x3325, 0x1078, 0x290c, 0x6f14, 0x7776, 0xa7bc,
+	0x8f00, 0x1078, 0x4187, 0x6008, 0xa085, 0x0021, 0x600a, 0x8738,
+	0xa784, 0x001f, 0x00c0, 0x3329, 0x1078, 0x4055, 0x7067, 0x0002,
+	0x701f, 0x0009, 0x0078, 0x333e, 0x1078, 0x4064, 0x781b, 0x0075,
+	0x007c, 0xa282, 0x0004, 0x0050, 0x3347, 0x1078, 0x290c, 0x2300,
+	0x0079, 0x334a, 0x334d, 0x350d, 0x3550, 0xa286, 0x0003, 0x0040,
+	0x3385, 0x7200, 0x7cd8, 0x7ddc, 0x7fd0, 0x71d4, 0xd1bc, 0x00c0,
+	0x337d, 0xd1b4, 0x0040, 0x337d, 0x7868, 0xa084, 0x00ff, 0x00c0,
+	0x337d, 0xa282, 0x0002, 0x00c8, 0x337d, 0x0d7e, 0x783b, 0x8300,
+	0x781b, 0x004c, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6,
+	0x78de, 0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030,
+	0x0d7f, 0x2001, 0x0000, 0x0078, 0x3389, 0x783b, 0x1300, 0x781b,
+	0x004a, 0x2001, 0x0000, 0x0078, 0x3389, 0x7200, 0x7cd8, 0x7ddc,
+	0x7fd0, 0x704a, 0x68a0, 0xd0ec, 0x0040, 0x3391, 0x6008, 0xc08d,
+	0x600a, 0xa284, 0x000f, 0x0079, 0x3395, 0x34ed, 0x33a2, 0x339f,
+	0x3653, 0x36df, 0x2966, 0x339d, 0x339d, 0x1078, 0x290c, 0x6008,
+	0xc0d4, 0x600a, 0xd6e4, 0x0040, 0x33aa, 0x7048, 0xa086, 0x0014,
+	0x00c0, 0x33ca, 0x1078, 0x44fb, 0x2009, 0x0000, 0x6818, 0xd0fc,
+	0x0040, 0x33b3, 0x7048, 0xa086, 0x0014, 0x0040, 0x33c4, 0x6818,
+	0xa086, 0x0008, 0x00c0, 0x34a5, 0x7858, 0xd09c, 0x0040, 0x34a5,
+	0x6820, 0xd0ac, 0x0040, 0x34a5, 0x681b, 0x0014, 0x2009, 0x0002,
+	0x0078, 0x3409, 0x7868, 0xa08c, 0x00ff, 0x0040, 0x3409, 0xa186,
+	0x0008, 0x00c0, 0x33e0, 0x6008, 0xc0a4, 0x600a, 0x1078, 0x3cf5,
+	0x0040, 0x3409, 0x1078, 0x3d73, 0x1078, 0x44fb, 0x0078, 0x33f1,
+	0xa186, 0x0028, 0x00c0, 0x3409, 0x6018, 0xa005, 0x0040, 0x33d3,
+	0x8001, 0x0040, 0x33d3, 0x8001, 0x0040, 0x33d3, 0x601e, 0x0078,
+	0x33d3, 0x6820, 0xd084, 0x0040, 0x2966, 0xc084, 0x6822, 0x1078,
+	0x2a6d, 0x705c, 0x0c7e, 0x2060, 0x6800, 0x6002, 0x0c7f, 0x6004,
+	0x6802, 0xa005, 0x2d00, 0x00c0, 0x3406, 0x6002, 0x6006, 0x0078,
+	0x2966, 0x017e, 0x81ff, 0x00c0, 0x3453, 0x7000, 0xa086, 0x0030,
+	0x0040, 0x3453, 0x71d4, 0xd1bc, 0x00c0, 0x3453, 0xd1b4, 0x00c0,
+	0x343a, 0x7060, 0xa005, 0x00c0, 0x3453, 0x70a4, 0xa086, 0x0001,
+	0x0040, 0x3453, 0x7003, 0x0000, 0x047e, 0x057e, 0x077e, 0x067e,
+	0x0c7e, 0x0d7e, 0x1078, 0x298f, 0x0d7f, 0x0c7f, 0x067f, 0x077f,
+	0x057f, 0x047f, 0x71d4, 0xd1b4, 0x00c0, 0x3453, 0x7003, 0x0040,
+	0x0078, 0x3453, 0x1078, 0x42e9, 0x00c0, 0x3453, 0x781b, 0x005b,
+	0x0d7e, 0x70bc, 0xa06d, 0x68b4, 0x785a, 0x6894, 0x78d6, 0x78de,
+	0x6898, 0x78d2, 0x78da, 0xc1b4, 0x71d6, 0x7003, 0x0030, 0x7808,
+	0xc08d, 0x780a, 0x0d7f, 0x1078, 0x358a, 0x017f, 0x81ff, 0x0040,
+	0x34a5, 0xa684, 0xdf00, 0x681e, 0x682b, 0x0000, 0x6f14, 0xa186,
+	0x0002, 0x00c0, 0x34a6, 0x6818, 0xa086, 0x0014, 0x00c0, 0x346f,
+	0x2008, 0xd6e4, 0x0040, 0x346f, 0x7868, 0xa08c, 0x00ff, 0x1078,
+	0x2a5b, 0x1078, 0x2a7c, 0x6820, 0xd0dc, 0x00c0, 0x34a6, 0x8717,
+	0xa294, 0x000f, 0x8213, 0x8213, 0x8213, 0xb284, 0x0300, 0x0040,
+	0x3485, 0xa290, 0x51c0, 0x0078, 0x3487, 0xa290, 0x5240, 0xa290,
+	0x0000, 0x221c, 0xd3c4, 0x00c0, 0x348f, 0x0078, 0x3495, 0x8210,
+	0x2204, 0xa085, 0x0018, 0x2012, 0x8211, 0xd3d4, 0x0040, 0x34a0,
+	0x68a0, 0xd0c4, 0x00c0, 0x34a0, 0x1078, 0x3604, 0x0078, 0x2966,
+	0x6008, 0xc08d, 0x600a, 0x0078, 0x34a6, 0x692a, 0x6916, 0x6818,
+	0xd0fc, 0x0040, 0x34ad, 0x7048, 0x681a, 0xa68c, 0xdf00, 0x691e,
+	0x6410, 0x84ff, 0x0040, 0x34c2, 0x2009, 0x4d02, 0x2104, 0x8001,
+	0x200a, 0x8421, 0x6412, 0x00c0, 0x34c2, 0x2021, 0x4d04, 0x2404,
+	0xc0a5, 0x2022, 0x6018, 0xa005, 0x0040, 0x34ca, 0x8001, 0x601a,
+	0x00c0, 0x34cd, 0x6008, 0xc0a4, 0x600a, 0x6820, 0xd084, 0x00c0,
+	0x34d9, 0x6800, 0xa005, 0x00c0, 0x34d6, 0x6002, 0x6006, 0x0078,
+	0x34dd, 0x705c, 0x2060, 0x6800, 0x6002, 0x2061, 0x4d00, 0x6887,
+	0x0103, 0x2d08, 0x206b, 0x0000, 0x6068, 0xa005, 0x616a, 0x0040,
+	0x34ec, 0x2d02, 0x0078, 0x34ed, 0x616e, 0x7200, 0xa286, 0x0030,
+	0x0040, 0x34fd, 0xa286, 0x0040, 0x00c0, 0x2966, 0x7003, 0x0002,
+	0x704c, 0x2068, 0x68c4, 0x2060, 0x007c, 0x7003, 0x0002, 0x70bc,
+	0xa06d, 0x68bc, 0x7042, 0x70b8, 0xa065, 0x68c0, 0x705a, 0x2d00,
+	0x704e, 0xad80, 0x0009, 0x7046, 0x007c, 0xa282, 0x0004, 0x0048,
+	0x3513, 0x1078, 0x290c, 0x2200, 0x0079, 0x3516, 0x351a, 0x352b,
+	0x3538, 0x352b, 0xa586, 0x1300, 0x0040, 0x352b, 0xa586, 0x8300,
+	0x00c0, 0x3511, 0x7003, 0x0000, 0x6018, 0x8001, 0x601a, 0x6008,
+	0xa084, 0xfbef, 0x600a, 0x7000, 0xa086, 0x0005, 0x0040, 0x3535,
+	0x1078, 0x4051, 0x781b, 0x0075, 0x007c, 0x781b, 0x0076, 0x007c,
+	0x7890, 0x8007, 0x8001, 0xa084, 0x0007, 0xa080, 0x0018, 0x789a,
+	0x79a8, 0xa18c, 0x00ff, 0xa186, 0x0003, 0x0040, 0x354d, 0xa186,
+	0x0000, 0x0040, 0x354d, 0x0078, 0x4040, 0x781b, 0x0076, 0x007c,
+	0x6820, 0xc095, 0x6822, 0x82ff, 0x00c0, 0x355a, 0x1078, 0x4051,
+	0x0078, 0x3561, 0x8211, 0x0040, 0x355f, 0x1078, 0x290c, 0x1078,
+	0x4064, 0x781b, 0x0075, 0x007c, 0x1078, 0x42fe, 0x7830, 0xa084,
+	0x00c0, 0x00c0, 0x3587, 0x017e, 0x3208, 0x007e, 0x2001, 0x4d04,
+	0x2004, 0xd0ec, 0x007f, 0x0040, 0x3579, 0xa18c, 0x0300, 0x0078,
+	0x357b, 0xa18c, 0x0400, 0x017f, 0x0040, 0x3582, 0x0018, 0x3587,
+	0x0078, 0x3584, 0x0028, 0x3587, 0x791a, 0xa006, 0x007c, 0xa085,
+	0x0001, 0x007c, 0xa684, 0x0060, 0x00c0, 0x3594, 0x682f, 0x0000,
+	0x6833, 0x0000, 0x0078, 0x3603, 0xd6dc, 0x00c0, 0x35ac, 0x68b4,
+	0xd0dc, 0x00c0, 0x35ac, 0x6998, 0x6a94, 0x692e, 0x6a32, 0x7048,
+	0xa005, 0x00c0, 0x35a9, 0x2200, 0xa105, 0x0040, 0x44fb, 0x704b,
+	0x0015, 0x0078, 0x44fb, 0x007c, 0xd6ac, 0x0040, 0x35d2, 0xd6f4,
+	0x0040, 0x35b8, 0x682f, 0x0000, 0x6833, 0x0000, 0x0078, 0x44fb,
+	0x68b4, 0xa084, 0x4000, 0xa635, 0xd6f4, 0x00c0, 0x35b2, 0x7048,
+	0xa005, 0x00c0, 0x35c5, 0x704b, 0x0015, 0xd6dc, 0x00c0, 0x35ce,
+	0x68b4, 0xd0dc, 0x0040, 0x35ce, 0x6ca8, 0x6da4, 0x6c2e, 0x6d32,
+	0x0078, 0x44fb, 0xd6f4, 0x0040, 0x35db, 0x682f, 0x0000, 0x6833,
+	0x0000, 0x0078, 0x44fb, 0x68b4, 0xa084, 0x4800, 0xa635, 0xd6f4,
+	0x00c0, 0x35d5, 0x7048, 0xa005, 0x00c0, 0x35e8, 0x704b, 0x0015,
+	0x2408, 0x2510, 0x2700, 0x80fb, 0x00c8, 0x35ef, 0x8000, 0xa084,
+	0x003f, 0xa108, 0xa291, 0x0000, 0x692e, 0x6a32, 0x2100, 0xa205,
+	0x00c0, 0x35fc, 0x0078, 0x44fb, 0x7000, 0xa086, 0x0006, 0x0040,
+	0x3603, 0x0078, 0x44fb, 0x007c, 0x6946, 0x6008, 0xc0cd, 0xd3cc,
+	0x0040, 0x360b, 0xc08d, 0x600a, 0x6818, 0x683a, 0x681b, 0x0006,
+	0x688f, 0x0000, 0x6893, 0x0000, 0x6a30, 0x692c, 0x6a3e, 0x6942,
+	0x682f, 0x0003, 0x6833, 0x0000, 0x6837, 0x0020, 0x6897, 0x0000,
+	0x689b, 0x0020, 0x7000, 0x0079, 0x3625, 0x2966, 0x3637, 0x362f,
+	0x362d, 0x362d, 0x362d, 0x362d, 0x362d, 0x1078, 0x290c, 0x6820,
+	0xd084, 0x00c0, 0x3637, 0x1078, 0x3d56, 0x0078, 0x363d, 0x705c,
+	0x2c50, 0x2060, 0x6800, 0x6002, 0x2a60, 0x3208, 0xa18c, 0x0300,
+	0x0040, 0x3646, 0x2021, 0x4d58, 0x0078, 0x3648, 0x2021, 0x4d98,
+	0x2404, 0xa005, 0x0040, 0x364f, 0x2020, 0x0078, 0x3648, 0x2d22,
+	0x206b, 0x0000, 0x007c, 0x1078, 0x3d5d, 0x1078, 0x3d73, 0x6008,
+	0xc0cc, 0x600a, 0x682b, 0x0000, 0x789b, 0x000e, 0x6f14, 0x6938,
+	0x691a, 0x6944, 0x6916, 0x3208, 0xa18c, 0x0300, 0x0040, 0x366c,
+	0x2009, 0x0000, 0x0078, 0x366e, 0x2009, 0x0001, 0x1078, 0x496f,
+	0xd6dc, 0x0040, 0x3676, 0x691c, 0xc1ed, 0x691e, 0x6818, 0xd0fc,
+	0x0040, 0x3685, 0x7868, 0xa08c, 0x00ff, 0x0040, 0x3683, 0x681b,
+	0x001e, 0x0078, 0x3685, 0x681b, 0x0000, 0xb284, 0x0300, 0x00c0,
+	0x368d, 0x2021, 0x4d98, 0x0078, 0x368f, 0x2021, 0x4d58, 0x6800,
+	0x2022, 0x6a3c, 0x6940, 0x6a32, 0x692e, 0x68c0, 0x2060, 0x6000,
+	0xd0a4, 0x0040, 0x36cf, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051,
+	0x0020, 0x0d7e, 0x0f7e, 0x157e, 0x147e, 0x2079, 0x4d00, 0x1078,
+	0x1de6, 0x147f, 0x157f, 0x0f7f, 0x70cc, 0x2010, 0x2009, 0x0101,
+	0x027e, 0x2204, 0xa06d, 0x0040, 0x36bf, 0x6814, 0xa706, 0x0040,
+	0x36bc, 0x6800, 0x0078, 0x36b2, 0x6820, 0xc0d5, 0x6822, 0x027f,
+	0x8210, 0x8109, 0x00c0, 0x36b0, 0x0d7f, 0x7067, 0x0003, 0x707f,
+	0x0000, 0x7776, 0x7083, 0x000f, 0x71d4, 0xc1dc, 0x71d6, 0x6818,
+	0xa086, 0x0002, 0x00c0, 0x36db, 0x6817, 0x0000, 0x682b, 0x0000,
+	0x681c, 0xc0ec, 0x681e, 0x1078, 0x2013, 0x0078, 0x2966, 0x7cd8,
+	0x7ddc, 0x7fd0, 0x1078, 0x358a, 0x682b, 0x0000, 0x789b, 0x000e,
+	0x6f14, 0x1078, 0x4302, 0xa08c, 0x00ff, 0x6916, 0x6818, 0xd0fc,
+	0x0040, 0x36f4, 0x7048, 0x681a, 0xa68c, 0xdf00, 0x691e, 0x7067,
+	0x0000, 0x0078, 0x2966, 0x7000, 0xa005, 0x00c0, 0x3701, 0x0078,
+	0x2966, 0xa006, 0x1078, 0x44fb, 0x6920, 0xd1ac, 0x00c0, 0x370a,
+	0x681b, 0x0014, 0xa68c, 0xdf00, 0x691e, 0x682b, 0x0000, 0x6820,
+	0xa084, 0x00ff, 0x6822, 0x7000, 0x0079, 0x3716, 0x2966, 0x3720,
+	0x3720, 0x3723, 0x3723, 0x3723, 0x371e, 0x371e, 0x1078, 0x290c,
+	0x6818, 0x0078, 0x3385, 0x6008, 0xc0a4, 0x600a, 0x6817, 0x0000,
+	0x0078, 0x3d1b, 0x2300, 0x0079, 0x372d, 0x3730, 0x3732, 0x379d,
+	0x1078, 0x290c, 0xd6fc, 0x00c0, 0x3784, 0x7000, 0xa00d, 0x0079,
+	0x3739, 0x2966, 0x3743, 0x3743, 0x3772, 0x3743, 0x3781, 0x3741,
+	0x3741, 0x1078, 0x290c, 0xa684, 0x0060, 0x0040, 0x3772, 0xa086,
+	0x0060, 0x00c0, 0x376f, 0xc6ac, 0xc6f4, 0xc6ed, 0x7e5a, 0x681c,
+	0xc0ac, 0x681e, 0xa186, 0x0002, 0x0040, 0x3761, 0x1078, 0x44fb,
+	0x69ac, 0x68b0, 0xa115, 0x0040, 0x3761, 0x1078, 0x486c, 0x0078,
+	0x3763, 0x1078, 0x4834, 0x781b, 0x0076, 0x71d4, 0xd1b4, 0x00c0,
+	0x2962, 0x70a4, 0xa086, 0x0001, 0x00c0, 0x29ac, 0x007c, 0xd6ec,
+	0x0040, 0x374d, 0x6818, 0xd0fc, 0x0040, 0x3781, 0xd6f4, 0x00c0,
+	0x377f, 0x681b, 0x0015, 0x781b, 0x0076, 0x0078, 0x2962, 0x681b,
+	0x0007, 0x1078, 0x42a2, 0x007c, 0xc6fc, 0x7e5a, 0x7adc, 0x79d8,
+	0x78d0, 0x801b, 0x00c8, 0x378d, 0x8000, 0xa084, 0x003f, 0xa108,
+	0xa291, 0x0000, 0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200,
+	0xa303, 0x68ae, 0x781b, 0x0076, 0x007c, 0x1078, 0x290c, 0x2300,
+	0x0079, 0x37a2, 0x37a7, 0x37cc, 0x382b, 0x1078, 0x290c, 0x7000,
+	0x0079, 0x37aa, 0x37b2, 0x37b4, 0x37bd, 0x37b2, 0x37b2, 0x37b2,
+	0x37b2, 0x37b2, 0x1078, 0x290c, 0x69ac, 0x68b0, 0xa115, 0x0040,
+	0x37bd, 0x1078, 0x486c, 0x0078, 0x37bf, 0x1078, 0x4834, 0x681c,
+	0xc0b4, 0x681e, 0x70d4, 0xd0b4, 0x00c0, 0x2962, 0x70a4, 0xa086,
+	0x0001, 0x00c0, 0x29ac, 0x007c, 0xd6fc, 0x00c0, 0x381b, 0x7000,
+	0xa00d, 0x0079, 0x37d3, 0x2966, 0x37e3, 0x37dd, 0x3812, 0x37e3,
+	0x3818, 0x37db, 0x37db, 0x1078, 0x290c, 0x6894, 0x78d6, 0x78de,
+	0x6898, 0x78d2, 0x78da, 0xa684, 0x0060, 0x0040, 0x3812, 0xa086,
+	0x0060, 0x00c0, 0x380f, 0xa6b4, 0xbfbf, 0xc6ed, 0x7e5a, 0xa186,
+	0x0002, 0x0040, 0x37fe, 0x1078, 0x44fb, 0x69ac, 0x68b0, 0xa115,
+	0x0040, 0x37fe, 0x1078, 0x486c, 0x0078, 0x3800, 0x1078, 0x4834,
+	0x781b, 0x0076, 0x681c, 0xc0b4, 0x681e, 0x71d4, 0xd1b4, 0x00c0,
+	0x2962, 0x70a4, 0xa086, 0x0001, 0x00c0, 0x29ac, 0x007c, 0xd6ec,
+	0x0040, 0x37ed, 0x6818, 0xd0fc, 0x0040, 0x3818, 0x681b, 0x0007,
+	0x781b, 0x00f6, 0x007c, 0xc6fc, 0x7e5a, 0x7adc, 0x79d8, 0x6b98,
+	0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae, 0x79d2,
+	0x781b, 0x0076, 0x007c, 0xd6dc, 0x0040, 0x3834, 0x782b, 0x3009,
+	0x781b, 0x0076, 0x0078, 0x2962, 0x7884, 0xc0ac, 0x7886, 0x78e4,
+	0xa084, 0x0008, 0x00c0, 0x3847, 0xa484, 0x0200, 0x0040, 0x3841,
+	0xc6f5, 0xc6dd, 0x7e5a, 0x781b, 0x0076, 0x0078, 0x2962, 0x6820,
+	0xc095, 0x6822, 0x1078, 0x421b, 0xc6dd, 0x1078, 0x4051, 0x781b,
+	0x0075, 0x0078, 0x2962, 0x2300, 0x0079, 0x3856, 0x3859, 0x385b,
+	0x385d, 0x1078, 0x290c, 0x0078, 0x404a, 0xd6d4, 0x00c0, 0x3883,
+	0x79e4, 0xd1ac, 0x0040, 0x386b, 0x78ec, 0xa084, 0x0003, 0x0040,
+	0x386b, 0x782b, 0x3009, 0x789b, 0x0060, 0x78ab, 0x0000, 0xa684,
+	0xfffb, 0x785a, 0x79e4, 0xd1ac, 0x0040, 0x387b, 0x78ec, 0xa084,
+	0x0003, 0x00c0, 0x387f, 0x2001, 0x0014, 0x0078, 0x3385, 0xa184,
+	0x0007, 0x0079, 0x38b9, 0x7a90, 0xa294, 0x0007, 0x789b, 0x0060,
+	0x79a8, 0x81ff, 0x0040, 0x38b7, 0x789b, 0x0010, 0x7ba8, 0xa384,
+	0x0001, 0x00c0, 0x38aa, 0x7ba8, 0x7ba8, 0xa386, 0x0001, 0x00c0,
+	0x389d, 0x2009, 0xfff7, 0x0078, 0x38a3, 0xa386, 0x0003, 0x00c0,
+	0x38aa, 0x2009, 0xffef, 0x0c7e, 0x7058, 0x2060, 0x6004, 0xa104,
+	0x6006, 0x0c7f, 0x789b, 0x0060, 0x78ab, 0x0000, 0xa684, 0xfffb,
+	0x785a, 0x782b, 0x3009, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0078,
+	0x4296, 0x302e, 0x3038, 0x38c3, 0x38c9, 0x38c1, 0x38c1, 0x4296,
+	0x4296, 0x1078, 0x290c, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0078,
+	0x429c, 0x6920, 0xa18c, 0xfcff, 0x6922, 0x0078, 0x4296, 0x79e4,
+	0xa184, 0x0030, 0x0040, 0x38d9, 0x78ec, 0xa084, 0x0003, 0x00c0,
+	0x390d, 0x7000, 0xa086, 0x0004, 0x00c0, 0x38f3, 0x7064, 0xa086,
+	0x0002, 0x00c0, 0x38e9, 0x2011, 0x0002, 0x2019, 0x0000, 0x0078,
+	0x2eba, 0x7064, 0xa086, 0x0006, 0x0040, 0x38e3, 0x7064, 0xa086,
+	0x0004, 0x0040, 0x38e3, 0x7000, 0xa086, 0x0000, 0x0040, 0x2962,
+	0x6920, 0xa184, 0x0420, 0x0040, 0x3902, 0xc1d4, 0x6922, 0x6818,
+	0x0078, 0x3385, 0x6818, 0xa08e, 0x0002, 0x0040, 0x390b, 0xc0fd,
+	0x681a, 0x2001, 0x0014, 0x0078, 0x3385, 0xa184, 0x0007, 0x0079,
+	0x3911, 0x4296, 0x4296, 0x3919, 0x4296, 0x42de, 0x42de, 0x4296,
+	0x4296, 0xd6bc, 0x0040, 0x395b, 0x7184, 0x81ff, 0x0040, 0x395b,
+	0xa182, 0x000d, 0x00d0, 0x3928, 0x7087, 0x0000, 0x0078, 0x392d,
+	0xa182, 0x000c, 0x7086, 0x2009, 0x000c, 0x789b, 0x0061, 0x79aa,
+	0x157e, 0x137e, 0x147e, 0x7088, 0x8114, 0xa210, 0x728a, 0xa080,
+	0x000b, 0xad00, 0x2098, 0xb284, 0x0300, 0x0040, 0x394f, 0x007e,
+	0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x394b, 0x20a1,
+	0x012b, 0x0078, 0x3951, 0x20a1, 0x022b, 0x0078, 0x3951, 0x20a1,
+	0x012b, 0x789b, 0x0000, 0x8108, 0x81ac, 0x53a6, 0x147f, 0x137f,
+	0x157f, 0x0078, 0x429c, 0xd6d4, 0x00c0, 0x39af, 0x6820, 0xd084,
+	0x0040, 0x429c, 0xa68c, 0x0060, 0xa684, 0x0060, 0x0040, 0x396d,
+	0xa086, 0x0060, 0x00c0, 0x396d, 0xc1f5, 0xc194, 0x795a, 0x69b6,
+	0x789b, 0x0060, 0x78ab, 0x0000, 0x789b, 0x0061, 0x6818, 0xc0fd,
+	0x681a, 0x78aa, 0x8008, 0x810c, 0x0040, 0x3d8c, 0xa18c, 0x00f8,
+	0x00c0, 0x3d8c, 0x157e, 0x137e, 0x147e, 0x017e, 0x3208, 0xa18c,
+	0x0300, 0x0040, 0x399b, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x007f, 0x0040, 0x3997, 0x20a1, 0x012b, 0x0078, 0x399d, 0x20a1,
+	0x022b, 0x0078, 0x399d, 0x20a1, 0x012b, 0x017f, 0x789b, 0x0000,
+	0x8000, 0x80ac, 0xad80, 0x000b, 0x2098, 0x53a6, 0x147f, 0x137f,
+	0x157f, 0x6814, 0xc0fc, 0x8007, 0x7882, 0x0078, 0x429c, 0x6818,
+	0xd0fc, 0x0040, 0x39b5, 0x681b, 0x0008, 0x6820, 0xc0ad, 0x6822,
+	0x1078, 0x4059, 0x781b, 0x00e7, 0x007c, 0x2300, 0x0079, 0x39c0,
+	0x39c5, 0x3a9d, 0x39c3, 0x1078, 0x290c, 0x7cd8, 0x7ddc, 0x7fd0,
+	0x82ff, 0x00c0, 0x39ee, 0x7200, 0xa286, 0x0003, 0x0040, 0x3352,
+	0x71d4, 0xd1bc, 0x00c0, 0x39f1, 0xd1b4, 0x0040, 0x39f1, 0x0d7e,
+	0x783b, 0x8800, 0x781b, 0x004c, 0x70bc, 0xa06d, 0x68b4, 0xc0a5,
+	0x785a, 0x6894, 0x78d6, 0x78de, 0x6898, 0x78d2, 0x78da, 0xc1b4,
+	0x71d6, 0x7003, 0x0030, 0x0d7f, 0x0078, 0x39f5, 0x7200, 0x0078,
+	0x39f5, 0x783b, 0x1800, 0x781b, 0x004a, 0xa284, 0x000f, 0x0079,
+	0x39f9, 0x3a88, 0x3a37, 0x3a03, 0x3381, 0x3a01, 0x3a88, 0x3a01,
+	0x3a01, 0x1078, 0x290c, 0x681c, 0xd0ec, 0x0040, 0x3a0a, 0x6008,
+	0xc08d, 0x600a, 0x6920, 0xc185, 0x6922, 0x6800, 0x6006, 0xa005,
+	0x00c0, 0x3a13, 0x6002, 0x6008, 0xc0d4, 0x600a, 0x681c, 0xa084,
+	0x000e, 0x00c0, 0x3a27, 0xb284, 0x0300, 0x0040, 0x3a23, 0x2009,
+	0x93c0, 0x0078, 0x3a2c, 0x2009, 0x94d0, 0x0078, 0x3a2c, 0x7030,
+	0x68ba, 0x7140, 0x70cc, 0xa108, 0x2104, 0x6802, 0x2d0a, 0x715e,
+	0xd6dc, 0x00c0, 0x3a37, 0xc6fc, 0x6eb6, 0x0078, 0x3a88, 0x6eb6,
+	0xa684, 0x0060, 0x00c0, 0x3a41, 0xa684, 0x7fff, 0x68b6, 0x0078,
+	0x3a88, 0xd6dc, 0x00c0, 0x3a4f, 0xa684, 0x7fff, 0x68b6, 0x6894,
+	0x68a6, 0x6898, 0x68aa, 0x1078, 0x44fb, 0x0078, 0x3a88, 0xd6ac,
+	0x0040, 0x3a5b, 0xa006, 0x1078, 0x44fb, 0x2408, 0x2510, 0x69aa,
+	0x6aa6, 0x0078, 0x3a6b, 0x2408, 0x2510, 0x2700, 0x801b, 0x00c8,
+	0x3a62, 0x8000, 0xa084, 0x003f, 0xa108, 0xa291, 0x0000, 0x69aa,
+	0x6aa6, 0x1078, 0x44fb, 0xd6fc, 0x0040, 0x3a88, 0xa684, 0x7fff,
+	0x68b6, 0x2510, 0x2408, 0xd6ac, 0x00c0, 0x3a80, 0x2700, 0x801b,
+	0x00c8, 0x3a7b, 0x8000, 0xa084, 0x003f, 0xa108, 0xa291, 0x0000,
+	0x6b98, 0x2100, 0xa302, 0x68b2, 0x6b94, 0x2200, 0xa303, 0x68ae,
+	0x7000, 0xa086, 0x0030, 0x00c0, 0x2966, 0x7003, 0x0002, 0x70bc,
+	0xa06d, 0x68bc, 0x7042, 0x70b8, 0xa065, 0x68c0, 0x705a, 0x2d00,
+	0x704e, 0xad80, 0x0009, 0x7046, 0x007c, 0xa586, 0x8800, 0x00c0,
+	0x3aaa, 0x7003, 0x0000, 0x6018, 0x8001, 0x601a, 0x6008, 0xa084,
+	0xfbef, 0x600a, 0x0078, 0x404a, 0x7047, 0x0000, 0xa282, 0x0006,
+	0x0050, 0x3ab4, 0x1078, 0x290c, 0x2300, 0x0079, 0x3ab7, 0x3aba,
+	0x3af1, 0x3b23, 0x2200, 0x0079, 0x3abd, 0x3ac3, 0x404a, 0x3ac5,
+	0x3ac3, 0x3b5a, 0x3bc2, 0x1078, 0x290c, 0x7003, 0x0005, 0xb284,
+	0x0300, 0x0040, 0x3acf, 0x2001, 0x94e0, 0x0078, 0x3ad1, 0x2001,
+	0x9512, 0x2068, 0x704e, 0x157e, 0x20a9, 0x0032, 0x2003, 0x0000,
+	0x8000, 0x00f0, 0x3ad6, 0x157f, 0xb284, 0x0300, 0x0040, 0x3ae4,
+	0x6817, 0x0000, 0x0078, 0x3ae6, 0x6817, 0x8000, 0xad80, 0x0009,
+	0x7046, 0x68b7, 0x0700, 0x6823, 0x0800, 0x6827, 0x0003, 0x0078,
+	0x4040, 0x7000, 0xa086, 0x0002, 0x00c0, 0x3b02, 0x1078, 0x3d73,
+	0x0078, 0x3afc, 0x1078, 0x44fb, 0x6008, 0xa084, 0xfbef, 0x600a,
+	0x0078, 0x3b07, 0x7000, 0xa086, 0x0003, 0x0040, 0x3afa, 0x7003,
+	0x0005, 0xb284, 0x0300, 0x0040, 0x3b11, 0x2001, 0x94e0, 0x0078,
+	0x3b13, 0x2001, 0x9512, 0x2068, 0x704e, 0xad80, 0x0009, 0x7046,
+	0x2200, 0x0079, 0x3b1b, 0x404a, 0x3b21, 0x3b21, 0x3b5a, 0x3b21,
+	0x404a, 0x1078, 0x290c, 0x7000, 0xa086, 0x0002, 0x00c0, 0x3b34,
+	0x1078, 0x3d73, 0x0078, 0x3b2e, 0x1078, 0x44fb, 0x6008, 0xa084,
+	0xfbef, 0x600a, 0x0078, 0x3b39, 0x7000, 0xa086, 0x0003, 0x0040,
+	0x3b2c, 0x7003, 0x0005, 0xb284, 0x0300, 0x0040, 0x3b43, 0x2001,
+	0x94e0, 0x0078, 0x3b45, 0x2001, 0x9512, 0x2068, 0x704e, 0xad80,
+	0x0009, 0x7046, 0x2200, 0x0079, 0x3b4d, 0x3b55, 0x3b53, 0x3b53,
+	0x3b55, 0x3b53, 0x3b55, 0x1078, 0x290c, 0x1078, 0x4064, 0x781b,
+	0x0075, 0x007c, 0x7000, 0xa086, 0x0002, 0x00c0, 0x3b6c, 0x70d4,
+	0xc0b5, 0x70d6, 0x2c00, 0x70ba, 0x2d00, 0x70be, 0x0078, 0x3b71,
+	0x1078, 0x44fb, 0x0078, 0x3b71, 0x7000, 0xa086, 0x0003, 0x0040,
+	0x3b68, 0x7003, 0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b, 0x0018,
+	0x7ca8, 0xa484, 0x001f, 0xa215, 0x2069, 0x93c0, 0xb284, 0x0300,
+	0x00c0, 0x3b85, 0xc2fd, 0x2069, 0x94d0, 0x2d04, 0x2d08, 0x715e,
+	0xa06d, 0x0040, 0x3b92, 0x6814, 0xa206, 0x0040, 0x3bb2, 0x6800,
+	0x0078, 0x3b86, 0x7003, 0x0005, 0xd2fc, 0x00c0, 0x3b9b, 0x2001,
+	0x94e0, 0x0078, 0x3b9d, 0x2001, 0x9512, 0x2068, 0x704e, 0x157e,
+	0x20a9, 0x0032, 0x2003, 0x0000, 0x8000, 0x00f0, 0x3ba2, 0x157f,
+	0xad80, 0x0009, 0x7046, 0x6a16, 0x68b7, 0x0700, 0x6823, 0x0800,
+	0x6827, 0x0003, 0x6eb4, 0x7e5a, 0x6920, 0xa184, 0x0c00, 0x0040,
+	0x3c3c, 0x681b, 0x0005, 0xc1ad, 0xc1d4, 0x6922, 0x1078, 0x4059,
+	0x0078, 0x3c3c, 0x7200, 0xa286, 0x0002, 0x00c0, 0x3bd4, 0x70d4,
+	0xc0b5, 0x70d6, 0x2c00, 0x70ba, 0x2d00, 0x70be, 0x0078, 0x3bd8,
+	0x1078, 0x44fb, 0x0078, 0x3bd8, 0xa286, 0x0003, 0x0040, 0x3bd0,
+	0x7003, 0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b, 0x0018, 0x7ca8,
+	0xa484, 0x001f, 0xa215, 0xb284, 0x0300, 0x00c0, 0x3be8, 0xc2fd,
+	0x79a8, 0x79a8, 0xa18c, 0x00ff, 0x70cc, 0xa168, 0x2d04, 0x2d08,
+	0x715e, 0xa06d, 0x0040, 0x3bfb, 0x6814, 0xa206, 0x0040, 0x3c24,
+	0x6800, 0x0078, 0x3bef, 0x7003, 0x0005, 0xb284, 0x0300, 0x0040,
+	0x3c05, 0x2001, 0x94e0, 0x0078, 0x3c07, 0x2001, 0x9512, 0x2068,
 	0x704e, 0x157e, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000, 0x00f0,
-	0x39b4, 0x157f, 0xb284, 0x0300, 0x0040, 0x39c2, 0x6817, 0x0000,
-	0x0078, 0x39c4, 0x6817, 0x8000, 0xad80, 0x0009, 0x7046, 0x68b7,
-	0x0700, 0x6823, 0x0800, 0x6827, 0x0003, 0x0078, 0x3e9d, 0x7000,
-	0xa086, 0x0002, 0x00c0, 0x39e0, 0x1078, 0x3bd2, 0x0078, 0x39da,
-	0x1078, 0x4326, 0x6008, 0xa084, 0xfbef, 0x600a, 0x0078, 0x39e5,
-	0x7000, 0xa086, 0x0003, 0x0040, 0x39d8, 0x7003, 0x0005, 0xb284,
-	0x0300, 0x0040, 0x39ef, 0x2001, 0x91e0, 0x0078, 0x39f1, 0x2001,
-	0x9212, 0x2068, 0x704e, 0xad80, 0x0009, 0x7046, 0x2200, 0x0079,
-	0x39f9, 0x3ea7, 0x39ff, 0x39ff, 0x3a38, 0x39ff, 0x3ea7, 0x1078,
-	0x28ec, 0x7000, 0xa086, 0x0002, 0x00c0, 0x3a12, 0x1078, 0x3bd2,
-	0x0078, 0x3a0c, 0x1078, 0x4326, 0x6008, 0xa084, 0xfbef, 0x600a,
-	0x0078, 0x3a17, 0x7000, 0xa086, 0x0003, 0x0040, 0x3a0a, 0x7003,
-	0x0005, 0xb284, 0x0300, 0x0040, 0x3a21, 0x2001, 0x91e0, 0x0078,
-	0x3a23, 0x2001, 0x9212, 0x2068, 0x704e, 0xad80, 0x0009, 0x7046,
-	0x2200, 0x0079, 0x3a2b, 0x3a33, 0x3a31, 0x3a31, 0x3a33, 0x3a31,
-	0x3a33, 0x1078, 0x28ec, 0x1078, 0x3ebe, 0x781b, 0x0075, 0x007c,
-	0x7000, 0xa086, 0x0002, 0x00c0, 0x3a4a, 0x70d4, 0xc0b5, 0x70d6,
-	0x2c00, 0x70ba, 0x2d00, 0x70be, 0x0078, 0x3a4f, 0x1078, 0x4326,
-	0x0078, 0x3a4f, 0x7000, 0xa086, 0x0003, 0x0040, 0x3a46, 0x7003,
-	0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b, 0x0018, 0x7ca8, 0xa484,
-	0x001f, 0xa215, 0x2069, 0x90c0, 0xb284, 0x0300, 0x00c0, 0x3a63,
-	0xc2fd, 0x2069, 0x91d0, 0x2d04, 0x2d08, 0x715e, 0xa06d, 0x0040,
-	0x3a70, 0x6814, 0xa206, 0x0040, 0x3a90, 0x6800, 0x0078, 0x3a64,
-	0x7003, 0x0005, 0xd2fc, 0x00c0, 0x3a79, 0x2001, 0x91e0, 0x0078,
-	0x3a7b, 0x2001, 0x9212, 0x2068, 0x704e, 0x157e, 0x20a9, 0x0032,
-	0x2003, 0x0000, 0x8000, 0x00f0, 0x3a80, 0x157f, 0xad80, 0x0009,
-	0x7046, 0x6a16, 0x68b7, 0x0700, 0x6823, 0x0800, 0x6827, 0x0003,
-	0x6eb4, 0x7e5a, 0x6820, 0xa084, 0x0c00, 0x0040, 0x3b10, 0x1078,
-	0x3eb6, 0x0078, 0x3b10, 0x7200, 0xa286, 0x0002, 0x00c0, 0x3aad,
-	0x70d4, 0xc0b5, 0x70d6, 0x2c00, 0x70ba, 0x2d00, 0x70be, 0x0078,
-	0x3ab1, 0x1078, 0x4326, 0x0078, 0x3ab1, 0xa286, 0x0003, 0x0040,
-	0x3aa9, 0x7003, 0x0001, 0x7a80, 0xa294, 0x0f00, 0x789b, 0x0018,
-	0x7ca8, 0xa484, 0x001f, 0xa215, 0xb284, 0x0300, 0x00c0, 0x3ac1,
-	0xc2fd, 0x79a8, 0x79a8, 0xa18c, 0x00ff, 0x70cc, 0xa168, 0x2d04,
-	0x2d08, 0x715e, 0xa06d, 0x0040, 0x3ad4, 0x6814, 0xa206, 0x0040,
-	0x3afd, 0x6800, 0x0078, 0x3ac8, 0x7003, 0x0005, 0xb284, 0x0300,
-	0x0040, 0x3ade, 0x2001, 0x91e0, 0x0078, 0x3ae0, 0x2001, 0x9212,
-	0x2068, 0x704e, 0x157e, 0x20a9, 0x0032, 0x2003, 0x0000, 0x8000,
-	0x00f0, 0x3ae5, 0x157f, 0xb284, 0x0300, 0x0040, 0x3af2, 0xc2fc,
-	0x0078, 0x3af3, 0xc2fd, 0x6a16, 0xad80, 0x0009, 0x7046, 0x68b7,
-	0x0700, 0x6823, 0x0800, 0x6827, 0x0003, 0x6eb4, 0x6820, 0xa084,
-	0x0c00, 0x0040, 0x3b10, 0xd0dc, 0x0040, 0x3b0a, 0x1078, 0x3eba,
-	0x0078, 0x3b10, 0x1078, 0x3eb6, 0x707f, 0x0000, 0x0078, 0x3b10,
-	0xa6ac, 0x0060, 0x0040, 0x3b4e, 0x6b98, 0x6c94, 0x69ac, 0x68b0,
-	0xa105, 0x00c0, 0x3b33, 0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0xa6b4,
-	0xb7ff, 0xa586, 0x0060, 0x0040, 0x3b4e, 0xc6ed, 0x7e5a, 0x2009,
-	0x0076, 0xd69c, 0x0040, 0x3b2e, 0x2009, 0x0075, 0x791a, 0x1078,
-	0x45f7, 0x0078, 0x3b57, 0x68b0, 0xa31a, 0x2100, 0xa423, 0x2400,
-	0xa305, 0x0040, 0x3b4e, 0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0x68b0,
-	0xc6f4, 0x7e5a, 0x2011, 0x0076, 0xd69c, 0x0040, 0x3b49, 0x2011,
-	0x0075, 0x7a1a, 0x1078, 0x462d, 0x0078, 0x3b57, 0x7e5a, 0x2009,
-	0x0076, 0xd69c, 0x0040, 0x3b56, 0x2009, 0x0075, 0x791a, 0x68c0,
-	0x705a, 0x2d00, 0x704e, 0x68c4, 0x2060, 0x71d4, 0xd1b4, 0x00c0,
-	0x2942, 0x2300, 0xa405, 0x0040, 0x2942, 0x70a4, 0xa086, 0x0001,
-	0x00c0, 0x2989, 0x007c, 0x6020, 0xa005, 0x0040, 0x3b79, 0x8001,
-	0x6022, 0x6008, 0xa085, 0x0008, 0x600a, 0x700f, 0x0100, 0x702c,
-	0x6026, 0x007c, 0xa006, 0x1078, 0x4326, 0x6817, 0x0000, 0x681b,
-	0x0001, 0x6823, 0x0040, 0x681f, 0x0100, 0x7000, 0xa084, 0x000f,
-	0x0079, 0x3b8a, 0x2946, 0x3b94, 0x3b94, 0x3bb1, 0x3b9c, 0x2946,
-	0x3b92, 0x3b92, 0x1078, 0x28ec, 0x1078, 0x3bbc, 0x1078, 0x3bb5,
-	0x1078, 0x202a, 0x0078, 0x2946, 0x7064, 0x7067, 0x0000, 0x7083,
-	0x0000, 0x0079, 0x3ba3, 0x3bad, 0x3bad, 0x3bab, 0x3bab, 0x3bab,
-	0x3bad, 0x3bab, 0x3bad, 0x0079, 0x2e5c, 0x7067, 0x0000, 0x0078,
-	0x2946, 0x681b, 0x0000, 0x0078, 0x35ae, 0x6800, 0xa005, 0x00c0,
-	0x3bba, 0x6002, 0x6006, 0x007c, 0x6410, 0x84ff, 0x0040, 0x3bce,
-	0x2009, 0x4a02, 0x2104, 0x8001, 0x200a, 0x8421, 0x6412, 0x00c0,
-	0x3bce, 0x2021, 0x4a04, 0x2404, 0xc0a5, 0x2022, 0x6008, 0xc0a4,
-	0x600a, 0x007c, 0x6018, 0xa005, 0x0040, 0x3bd8, 0x8001, 0x601a,
-	0x007c, 0x1078, 0x4131, 0x681b, 0x0018, 0x0078, 0x3c1a, 0x1078,
-	0x4131, 0x681b, 0x0019, 0x0078, 0x3c1a, 0x1078, 0x4131, 0x681b,
-	0x001a, 0x0078, 0x3c1a, 0x1078, 0x4131, 0x681b, 0x0003, 0x0078,
-	0x3c1a, 0x7774, 0x1078, 0x3fe1, 0x7178, 0xa18c, 0x00ff, 0x3210,
-	0xa294, 0x0300, 0x0040, 0x3c00, 0xa1e8, 0x8fc0, 0x0078, 0x3c02,
-	0xa1e8, 0x90d0, 0x2d04, 0x2d08, 0x2068, 0xa005, 0x00c0, 0x3c0a,
-	0x0078, 0x2946, 0x6814, 0xc0fc, 0x7274, 0xc2fc, 0xa206, 0x0040,
-	0x3c14, 0x6800, 0x0078, 0x3c03, 0x6800, 0x200a, 0x681b, 0x0005,
-	0x707f, 0x0000, 0x1078, 0x3bbc, 0x6820, 0xd084, 0x00c0, 0x3c22,
-	0x1078, 0x3bb5, 0x1078, 0x3bd2, 0x681f, 0x0000, 0x6823, 0x0020,
-	0x1078, 0x202a, 0x0078, 0x2946, 0xa282, 0x0003, 0x00c0, 0x3e9d,
-	0x7da8, 0xa5ac, 0x00ff, 0x7ea8, 0xa6b4, 0x00ff, 0x6920, 0xc1bd,
-	0x6922, 0xd1c4, 0x0040, 0x3c86, 0xc1c4, 0x6922, 0xa6b4, 0x00ff,
-	0x0040, 0x3c73, 0xa682, 0x000c, 0x0048, 0x3c4a, 0x0040, 0x3c4a,
-	0x2031, 0x000c, 0x2500, 0xa086, 0x000a, 0x0040, 0x3c51, 0x852b,
-	0x852b, 0x1078, 0x3f73, 0x0040, 0x3c59, 0x1078, 0x3d55, 0x0078,
-	0x3c7c, 0x1078, 0x3f2e, 0x0c7e, 0x2960, 0x6004, 0xa084, 0xfff5,
-	0x6006, 0x1078, 0x3d8a, 0x0c7f, 0x6920, 0xc1c5, 0x6922, 0x7e58,
-	0xc695, 0x7e5a, 0xd6d4, 0x00c0, 0x3c70, 0x781b, 0x0061, 0x007c,
-	0x781b, 0x0075, 0x007c, 0x0c7e, 0x2960, 0x6004, 0xa084, 0xfff5,
-	0x6006, 0x1078, 0x3d8a, 0x0c7f, 0x7e58, 0xd6d4, 0x00c0, 0x3c83,
-	0x781b, 0x0064, 0x007c, 0x781b, 0x0076, 0x007c, 0x0c7e, 0x7058,
-	0x2060, 0x6100, 0xd1e4, 0x0040, 0x3ccf, 0x6208, 0x8217, 0xa294,
-	0x00ff, 0xa282, 0x000c, 0x0048, 0x3c99, 0x0040, 0x3c99, 0x2011,
-	0x000c, 0x2600, 0xa202, 0x00c8, 0x3c9e, 0x2230, 0x6208, 0xa294,
-	0x00ff, 0x2001, 0x4a05, 0x2004, 0xd0e4, 0x00c0, 0x3cb3, 0x78ec,
-	0xd0e4, 0x0040, 0x3cb3, 0xa282, 0x000a, 0x00c8, 0x3cb9, 0x2011,
-	0x000a, 0x0078, 0x3cb9, 0xa282, 0x000c, 0x00c8, 0x3cb9, 0x2011,
-	0x000c, 0x2200, 0xa502, 0x00c8, 0x3cbe, 0x2228, 0x1078, 0x3f32,
-	0x2500, 0xa086, 0x000a, 0x0040, 0x3cc7, 0x852b, 0x852b, 0x1078,
-	0x3f73, 0x0040, 0x3ccf, 0x1078, 0x3d55, 0x0078, 0x3cd3, 0x1078,
-	0x3f2e, 0x1078, 0x3d8a, 0x7858, 0xc095, 0x785a, 0x0c7f, 0x781b,
-	0x0075, 0x007c, 0x0c7e, 0x2960, 0x6000, 0xd0e4, 0x00c0, 0x3cf1,
-	0x6010, 0xa084, 0x000f, 0x00c0, 0x3ceb, 0x6104, 0xa18c, 0xfff5,
-	0x6106, 0x0c7f, 0x007c, 0x2011, 0x0032, 0x2019, 0x0000, 0x0078,
-	0x3d1c, 0x68a0, 0xd0cc, 0x00c0, 0x3ceb, 0x6208, 0xa294, 0x00ff,
-	0x2001, 0x4a05, 0x2004, 0xd0e4, 0x00c0, 0x3d0a, 0x78ec, 0xd0e4,
-	0x0040, 0x3d0a, 0xa282, 0x000a, 0x00c0, 0x3d0a, 0x2011, 0x000a,
-	0x0078, 0x3d10, 0xa282, 0x000c, 0x00c8, 0x3d10, 0x2011, 0x000c,
-	0x6308, 0x831f, 0xa39c, 0x00ff, 0xa382, 0x000c, 0x0048, 0x3d1c,
-	0x0040, 0x3d1c, 0x2019, 0x000c, 0x78ab, 0x0001, 0x78ab, 0x0003,
-	0x78ab, 0x0001, 0x7aaa, 0x7baa, 0xa8c0, 0x0005, 0x6820, 0xc0c5,
-	0x6822, 0x70d4, 0xd0b4, 0x0040, 0x3d38, 0xc0b4, 0x70d6, 0x70b8,
-	0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a,
-	0x0c7f, 0x007c, 0x0c7e, 0x2960, 0x6104, 0xa18c, 0xfff5, 0x6106,
-	0x2011, 0x0032, 0x2019, 0x0000, 0x0078, 0x3d46, 0x78ab, 0x0001,
+	0x3c0c, 0x157f, 0xb284, 0x0300, 0x0040, 0x3c19, 0xc2fc, 0x0078,
+	0x3c1a, 0xc2fd, 0x6a16, 0xad80, 0x0009, 0x7046, 0x68b7, 0x0700,
+	0x6823, 0x0800, 0x6827, 0x0003, 0x6eb4, 0x6920, 0xa184, 0x0c00,
+	0x0040, 0x3c3c, 0xd0dc, 0x0040, 0x3c31, 0x1078, 0x4060, 0x0078,
+	0x3c3c, 0x681b, 0x0005, 0xc1ad, 0xc1d4, 0x6922, 0x1078, 0x4059,
+	0x707f, 0x0000, 0x0078, 0x3c3c, 0xc6ec, 0xa6ac, 0x0060, 0x0040,
+	0x3c90, 0x6b98, 0x6c94, 0x69ac, 0x68b0, 0xa105, 0x00c0, 0x3c69,
+	0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0xa586, 0x0060, 0x0040, 0x3c8e,
+	0xd6f4, 0x00c0, 0x3c54, 0xc6ed, 0xa6b4, 0xb7ff, 0x7e5a, 0x2009,
+	0x0076, 0xd69c, 0x0040, 0x3c61, 0x2009, 0x0075, 0x2019, 0x0000,
+	0x2320, 0x791a, 0xd6ec, 0x0040, 0x3c99, 0x1078, 0x4834, 0x0078,
+	0x3c99, 0x68b0, 0xa31a, 0x2100, 0xa423, 0x2400, 0xa305, 0x0040,
+	0x3c90, 0x7bd2, 0x7bda, 0x7cd6, 0x7cde, 0x68b0, 0xd6f4, 0x00c0,
+	0x3c7a, 0xc6ed, 0xc6f4, 0x7e5a, 0x2011, 0x0076, 0xd69c, 0x0040,
+	0x3c86, 0x2011, 0x0075, 0x2019, 0x0000, 0x2320, 0x7a1a, 0xd6ec,
+	0x0040, 0x3c99, 0x1078, 0x486c, 0x0078, 0x3c99, 0xa6b4, 0xb7ff,
+	0x7e5a, 0x2009, 0x0076, 0xd69c, 0x0040, 0x3c98, 0x2009, 0x0075,
+	0x791a, 0x68c0, 0x705a, 0x2d00, 0x704e, 0x68c4, 0x2060, 0x71d4,
+	0x70d8, 0xa02d, 0x0040, 0x3cc1, 0xd1bc, 0x0040, 0x3cdb, 0x7a80,
+	0xa294, 0x0f00, 0x70dc, 0xa206, 0x0040, 0x3cb2, 0x78e0, 0xa504,
+	0x00c0, 0x3ce8, 0x70da, 0xc1bc, 0x71d6, 0x0078, 0x3ce8, 0x2031,
+	0x0001, 0x852c, 0x0048, 0x3cc0, 0x8633, 0x8210, 0x0078, 0x3cb9,
+	0x007c, 0x7de0, 0xa594, 0xff00, 0x0040, 0x3cce, 0x2011, 0x0008,
+	0x852f, 0x1078, 0x3cb7, 0x8637, 0x0078, 0x3cd0, 0x1078, 0x3cb7,
+	0x8217, 0x7880, 0xa084, 0x0f00, 0xa206, 0x0040, 0x3ce8, 0x72de,
+	0x76da, 0x0078, 0x3ce8, 0x7a80, 0xa294, 0x0f00, 0x70dc, 0xa236,
+	0x0040, 0x3cd8, 0x78e0, 0xa534, 0x0040, 0x3cd8, 0xc1bd, 0x71d6,
+	0xd1b4, 0x00c0, 0x2962, 0x2300, 0xa405, 0x0040, 0x2962, 0x70a4,
+	0xa086, 0x0001, 0x00c0, 0x29ac, 0x007c, 0x6020, 0xa005, 0x0040,
+	0x3d03, 0x8001, 0x6022, 0x6008, 0xa085, 0x0008, 0x600a, 0x700f,
+	0x0100, 0x702c, 0x6026, 0x007c, 0xa006, 0x1078, 0x44fb, 0x7000,
+	0xa086, 0x0002, 0x0040, 0x3d11, 0x7064, 0xa086, 0x0005, 0x00c0,
+	0x3d1b, 0x682b, 0x0000, 0x6817, 0x0000, 0x681b, 0x0001, 0x6823,
+	0x0040, 0x681f, 0x0100, 0x7000, 0xa084, 0x000f, 0x0079, 0x3d20,
+	0x2966, 0x3d30, 0x3d2a, 0x3d52, 0x3d3a, 0x2966, 0x3d28, 0x3d28,
+	0x1078, 0x290c, 0x1078, 0x3d5d, 0x1078, 0x3d56, 0x0078, 0x3d36,
+	0x1078, 0x3d5d, 0x705c, 0x2060, 0x6800, 0x6002, 0x1078, 0x2013,
+	0x0078, 0x2966, 0x7064, 0x7067, 0x0000, 0x7083, 0x0000, 0x0079,
+	0x3d41, 0x3d4e, 0x3d4e, 0x3d49, 0x3d49, 0x3d49, 0x3d4e, 0x3d49,
+	0x3d4e, 0x77d4, 0xc7dd, 0x77d6, 0x0079, 0x2ed3, 0x7067, 0x0000,
+	0x0078, 0x2966, 0x681b, 0x0000, 0x0078, 0x3653, 0x6800, 0xa005,
+	0x00c0, 0x3d5b, 0x6002, 0x6006, 0x007c, 0x6410, 0x84ff, 0x0040,
+	0x3d6f, 0x2009, 0x4d02, 0x2104, 0x8001, 0x200a, 0x8421, 0x6412,
+	0x00c0, 0x3d6f, 0x2021, 0x4d04, 0x2404, 0xc0a5, 0x2022, 0x6008,
+	0xc0a4, 0x600a, 0x007c, 0x6018, 0xa005, 0x0040, 0x3d79, 0x8001,
+	0x601a, 0x007c, 0x1078, 0x42fe, 0x681b, 0x0018, 0x0078, 0x3dbc,
+	0x1078, 0x42fe, 0x681b, 0x0019, 0x0078, 0x3dbc, 0x1078, 0x42fe,
+	0x681b, 0x001a, 0x0078, 0x3dbc, 0x1078, 0x42fe, 0x681b, 0x0003,
+	0x0078, 0x3dbc, 0x7774, 0x1078, 0x4187, 0x7178, 0xa18c, 0x00ff,
+	0x3210, 0xa294, 0x0300, 0x0040, 0x3da1, 0xa1e8, 0x92c0, 0x0078,
+	0x3da3, 0xa1e8, 0x93d0, 0x2d04, 0x2d08, 0x2068, 0xa005, 0x00c0,
+	0x3dac, 0x707e, 0x0078, 0x2966, 0x6814, 0xc0fc, 0x7274, 0xc2fc,
+	0xa206, 0x0040, 0x3db6, 0x6800, 0x0078, 0x3da4, 0x6800, 0x200a,
+	0x681b, 0x0005, 0x707f, 0x0000, 0x1078, 0x3d5d, 0x6820, 0xd084,
+	0x00c0, 0x3dc4, 0x1078, 0x3d56, 0x1078, 0x3d73, 0x681f, 0x0000,
+	0x6823, 0x0020, 0x1078, 0x2013, 0x0078, 0x2966, 0xa282, 0x0003,
+	0x00c0, 0x4040, 0x7da8, 0xa5ac, 0x00ff, 0x7ea8, 0xa6b4, 0x00ff,
+	0x6920, 0xc1bd, 0x6922, 0xd1c4, 0x0040, 0x3e28, 0xc1c4, 0x6922,
+	0xa6b4, 0x00ff, 0x0040, 0x3e15, 0xa682, 0x000c, 0x0048, 0x3dec,
+	0x0040, 0x3dec, 0x2031, 0x000c, 0x2500, 0xa086, 0x000a, 0x0040,
+	0x3df3, 0x852b, 0x852b, 0x1078, 0x4119, 0x0040, 0x3dfb, 0x1078,
+	0x3ef7, 0x0078, 0x3e1e, 0x1078, 0x40d4, 0x0c7e, 0x2960, 0x6004,
+	0xa084, 0xfff5, 0x6006, 0x1078, 0x3f2d, 0x0c7f, 0x6920, 0xc1c5,
+	0x6922, 0x7e58, 0xc695, 0x7e5a, 0xd6d4, 0x00c0, 0x3e12, 0x781b,
+	0x0061, 0x007c, 0x781b, 0x0075, 0x007c, 0x0c7e, 0x2960, 0x6004,
+	0xa084, 0xfff5, 0x6006, 0x1078, 0x3f2d, 0x0c7f, 0x7e58, 0xd6d4,
+	0x00c0, 0x3e25, 0x781b, 0x0064, 0x007c, 0x781b, 0x0076, 0x007c,
+	0x0c7e, 0x7058, 0x2060, 0x6100, 0xd1e4, 0x0040, 0x3e71, 0x6208,
+	0x8217, 0xa294, 0x00ff, 0xa282, 0x000c, 0x0048, 0x3e3b, 0x0040,
+	0x3e3b, 0x2011, 0x000c, 0x2600, 0xa202, 0x00c8, 0x3e40, 0x2230,
+	0x6208, 0xa294, 0x00ff, 0x2001, 0x4d05, 0x2004, 0xd0e4, 0x00c0,
+	0x3e55, 0x78ec, 0xd0e4, 0x0040, 0x3e55, 0xa282, 0x000a, 0x00c8,
+	0x3e5b, 0x2011, 0x000a, 0x0078, 0x3e5b, 0xa282, 0x000c, 0x00c8,
+	0x3e5b, 0x2011, 0x000c, 0x2200, 0xa502, 0x00c8, 0x3e60, 0x2228,
+	0x1078, 0x40d8, 0x2500, 0xa086, 0x000a, 0x0040, 0x3e69, 0x852b,
+	0x852b, 0x1078, 0x4119, 0x0040, 0x3e71, 0x1078, 0x3ef7, 0x0078,
+	0x3e75, 0x1078, 0x40d4, 0x1078, 0x3f2d, 0x7858, 0xc095, 0x785a,
+	0x0c7f, 0x781b, 0x0075, 0x007c, 0x0c7e, 0x2960, 0x6000, 0xd0e4,
+	0x00c0, 0x3e93, 0x6010, 0xa084, 0x000f, 0x00c0, 0x3e8d, 0x6104,
+	0xa18c, 0xfff5, 0x6106, 0x0c7f, 0x007c, 0x2011, 0x0032, 0x2019,
+	0x0000, 0x0078, 0x3ebe, 0x68a0, 0xd0cc, 0x00c0, 0x3e8d, 0x6208,
+	0xa294, 0x00ff, 0x2001, 0x4d05, 0x2004, 0xd0e4, 0x00c0, 0x3eac,
+	0x78ec, 0xd0e4, 0x0040, 0x3eac, 0xa282, 0x000b, 0x00c8, 0x3eac,
+	0x2011, 0x000a, 0x0078, 0x3eb2, 0xa282, 0x000c, 0x00c8, 0x3eb2,
+	0x2011, 0x000c, 0x6308, 0x831f, 0xa39c, 0x00ff, 0xa382, 0x000c,
+	0x0048, 0x3ebe, 0x0040, 0x3ebe, 0x2019, 0x000c, 0x78ab, 0x0001,
 	0x78ab, 0x0003, 0x78ab, 0x0001, 0x7aaa, 0x7baa, 0xa8c0, 0x0005,
-	0x6820, 0xc0c5, 0x6822, 0x0c7f, 0x007c, 0x0c7e, 0x7158, 0x2160,
-	0x2018, 0xa08c, 0x0020, 0x0040, 0x3d5e, 0xc0ac, 0x2008, 0xa084,
-	0xfff0, 0xa635, 0x7e86, 0x6018, 0x789a, 0x7eae, 0x6612, 0x78a4,
-	0xa084, 0xfff0, 0xa18c, 0x000f, 0xa105, 0xa39c, 0x0020, 0x0040,
-	0x3d73, 0xa085, 0x4000, 0xc0fc, 0xd0b4, 0x00c0, 0x3d78, 0xc0fd,
-	0x78a6, 0x6016, 0x788a, 0xa6b4, 0x000f, 0x8637, 0x8204, 0x8004,
-	0xa084, 0x00ff, 0xa605, 0x600e, 0x6004, 0xa084, 0xfff5, 0x6006,
-	0x0c7f, 0x007c, 0x0c7e, 0x7058, 0x2060, 0x6018, 0x789a, 0x78a4,
-	0xa084, 0xfff0, 0x78a6, 0x6012, 0x7884, 0xa084, 0xfff0, 0x7886,
-	0x600c, 0xa084, 0x00ff, 0x600e, 0x0c7f, 0x007c, 0xa282, 0x0002,
-	0x00c0, 0x3e9d, 0x7aa8, 0x6920, 0xc1bd, 0x6922, 0xd1cc, 0x0040,
-	0x3dd9, 0xc1cc, 0x6922, 0xa294, 0x00ff, 0xa282, 0x0002, 0x00c8,
-	0x3e9d, 0x1078, 0x3e2a, 0x1078, 0x3d8a, 0xa980, 0x0001, 0x200c,
-	0x1078, 0x3fdd, 0x1078, 0x3cda, 0x88ff, 0x0040, 0x3dcf, 0x789b,
-	0x0060, 0x2800, 0x78aa, 0x7e58, 0xc695, 0x7e5a, 0xd6d4, 0x00c0,
-	0x3dcc, 0x781b, 0x0061, 0x007c, 0x781b, 0x0075, 0x007c, 0x7e58,
-	0xd6d4, 0x00c0, 0x3dd6, 0x781b, 0x0064, 0x007c, 0x781b, 0x0076,
-	0x007c, 0xa282, 0x0002, 0x00c8, 0x3de1, 0xa284, 0x0001, 0x0040,
-	0x3dea, 0x7158, 0xa188, 0x0000, 0x210c, 0xd1ec, 0x00c0, 0x3dea,
-	0x2011, 0x0000, 0x1078, 0x3f0f, 0x1078, 0x3e2a, 0x1078, 0x3d8a,
-	0x7858, 0xc095, 0x785a, 0x781b, 0x0075, 0x007c, 0x0c7e, 0x027e,
-	0x2960, 0x6000, 0x2011, 0x0001, 0xd0ec, 0x00c0, 0x3e0b, 0x6014,
-	0xa084, 0x0040, 0x00c0, 0x3e09, 0xc1a4, 0x6106, 0xa006, 0x0078,
-	0x3e27, 0x2011, 0x0000, 0x78ab, 0x0001, 0x78ab, 0x0002, 0x78ab,
-	0x0003, 0x7aaa, 0xa8c0, 0x0004, 0x70d4, 0xd0b4, 0x0040, 0x3e23,
-	0xc0b4, 0x70d6, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a,
-	0x6018, 0x8001, 0x601a, 0x6820, 0xa085, 0x0200, 0x6822, 0x027f,
-	0x0c7f, 0x007c, 0x0c7e, 0x7058, 0x2060, 0x82ff, 0x0040, 0x3e32,
-	0x2011, 0x0040, 0x6018, 0xa080, 0x0002, 0x789a, 0x78a4, 0xa084,
-	0xffbf, 0xa205, 0xc0fc, 0xd0b4, 0x00c0, 0x3e3f, 0xc0fd, 0x78a6,
-	0x6016, 0x788a, 0x6004, 0xc0a4, 0x6006, 0x0c7f, 0x007c, 0x007e,
-	0x7000, 0xa086, 0x0003, 0x0040, 0x3e50, 0x007f, 0x0078, 0x3e53,
-	0x007f, 0x0078, 0x3e9a, 0xd6ac, 0x0040, 0x3e9a, 0x7888, 0xa084,
-	0x0040, 0x0040, 0x3e9a, 0x7bb8, 0xa384, 0x003f, 0x831b, 0x00c8,
-	0x3e62, 0x8000, 0xa005, 0x0040, 0x3e77, 0x831b, 0x00c8, 0x3e6b,
-	0x8001, 0x0040, 0x3e97, 0xd6f4, 0x0040, 0x3e77, 0x78b8, 0x801b,
-	0x00c8, 0x3e73, 0x8000, 0xa084, 0x003f, 0x00c0, 0x3e97, 0xc6f4,
-	0x7e5a, 0x79d8, 0x7adc, 0x2001, 0x0001, 0xa108, 0x00c8, 0x3e82,
-	0xa291, 0x0000, 0x79d2, 0x79da, 0x7ad6, 0x7ade, 0x1078, 0x46e5,
-	0x781b, 0x0073, 0xb284, 0x0300, 0x0040, 0x3e92, 0x2001, 0x0000,
-	0x0078, 0x3e94, 0x2001, 0x0001, 0x1078, 0x4585, 0x007c, 0x781b,
-	0x0073, 0x007c, 0x781b, 0x0076, 0x007c, 0x1078, 0x3ec2, 0x781b,
-	0x0075, 0x007c, 0x1078, 0x3eae, 0x781b, 0x0075, 0x007c, 0x6827,
-	0x0002, 0x1078, 0x3eb6, 0x781b, 0x0075, 0x007c, 0x2001, 0x0005,
-	0x0078, 0x3ec4, 0x2001, 0x000c, 0x0078, 0x3ec4, 0x2001, 0x0006,
-	0x0078, 0x3ec4, 0x2001, 0x000d, 0x0078, 0x3ec4, 0x2001, 0x0009,
-	0x0078, 0x3ec4, 0x2001, 0x0007, 0x789b, 0x007e, 0x78aa, 0xc69d,
-	0x7e5a, 0x70d4, 0xd0b4, 0x0040, 0x3eda, 0xc0b4, 0x70d6, 0x0c7e,
-	0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001,
-	0x601a, 0x0c7f, 0x007c, 0x077e, 0x873f, 0xa7bc, 0x000f, 0x873b,
-	0x873b, 0x8703, 0x017e, 0xb28c, 0x0300, 0x0040, 0x3eeb, 0xa0e0,
-	0x4ec0, 0x0078, 0x3eed, 0xa0e0, 0x4f40, 0x017f, 0xa7b8, 0x0020,
-	0x7f9a, 0x79a4, 0xa184, 0x000f, 0x0040, 0x3efd, 0xa184, 0xfff0,
-	0x78a6, 0x6012, 0x6004, 0xc09d, 0x6006, 0x8738, 0x8738, 0x7f9a,
-	0x79a4, 0xa184, 0x0040, 0x0040, 0x3f0d, 0xa184, 0xffbf, 0xc0fd,
-	0x78a6, 0x6016, 0x6004, 0xc0a5, 0x6006, 0x077f, 0x007c, 0x789b,
-	0x0010, 0x78ab, 0x0001, 0x78ab, 0x0002, 0x78ab, 0x0003, 0x7aaa,
-	0x789b, 0x0060, 0x78ab, 0x0004, 0x70d4, 0xd0b4, 0x0040, 0x3f2d,
-	0xc0b4, 0x70d6, 0x0c7e, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef,
-	0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f, 0x007c, 0x2031, 0x0000,
-	0x2029, 0x0032, 0x789b, 0x0010, 0x78ab, 0x0001, 0x78ab, 0x0003,
-	0x78ab, 0x0001, 0x7daa, 0x7eaa, 0x789b, 0x0060, 0x78ab, 0x0005,
-	0x70d4, 0xd0b4, 0x0040, 0x3f51, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8,
-	0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a,
-	0x0c7f, 0x007c, 0x157e, 0x8007, 0xa084, 0x00ff, 0x8003, 0x8003,
-	0xa080, 0x0020, 0x789a, 0x79a4, 0xa18c, 0xfff0, 0x2021, 0x3fc6,
-	0x2019, 0x0011, 0x20a9, 0x000e, 0x2011, 0x0032, 0x2404, 0xa084,
-	0xfff0, 0xa106, 0x0040, 0x3f71, 0x8420, 0x2300, 0xa210, 0x00f0,
-	0x3f66, 0x157f, 0x007c, 0x157e, 0x2001, 0x4a05, 0x2004, 0xd0e4,
-	0x00c0, 0x3fa4, 0x2021, 0x3fd4, 0x20a9, 0x0009, 0x2011, 0x0028,
-	0xa582, 0x0019, 0x0040, 0x3fba, 0x0048, 0x3fba, 0x8420, 0x95a9,
-	0x2011, 0x0032, 0xa582, 0x0032, 0x0040, 0x3fba, 0x0048, 0x3fba,
-	0x8420, 0x95a9, 0x2019, 0x000a, 0x2011, 0x0064, 0x2200, 0xa502,
-	0x0040, 0x3fba, 0x0048, 0x3fba, 0x8420, 0x2300, 0xa210, 0x00f0,
-	0x3f96, 0x157f, 0x0078, 0x3fb8, 0x2021, 0x3fc6, 0x2019, 0x0011,
-	0x20a9, 0x000e, 0x2011, 0x0032, 0x2200, 0xa502, 0x0040, 0x3fba,
-	0x0048, 0x3fba, 0x8420, 0x2300, 0xa210, 0x00f0, 0x3fac, 0x157f,
-	0xa006, 0x007c, 0x157f, 0xa582, 0x0064, 0x00c8, 0x3fc3, 0x7808,
-	0xa085, 0x0070, 0x780a, 0x2404, 0xa005, 0x007c, 0x1209, 0x3002,
-	0x3202, 0x4203, 0x4403, 0x5404, 0x5604, 0x6605, 0x6805, 0x7806,
-	0x7a06, 0x0c07, 0x0c07, 0x0e07, 0x10e1, 0x330a, 0x5805, 0x5a05,
-	0x6a06, 0x6c06, 0x7c07, 0x7e07, 0x0e00, 0x789b, 0x0010, 0xa046,
-	0x007c, 0xa784, 0x0f00, 0x800b, 0xa784, 0x001f, 0x8003, 0x8003,
-	0x8003, 0x8003, 0xa105, 0xd7fc, 0x0040, 0x3ff2, 0xa0e0, 0x6fc0,
-	0x0078, 0x3ff4, 0xa0e0, 0x4fc0, 0x007c, 0x0e7e, 0x0f7e, 0xd084,
-	0x0040, 0x4002, 0x2079, 0x0100, 0x2009, 0x4a80, 0x2071, 0x4a80,
-	0x0078, 0x4014, 0x2009, 0x4a40, 0x007e, 0x2001, 0x4a04, 0x2004,
-	0xd0ec, 0x007f, 0x0040, 0x4010, 0x2079, 0x0100, 0x0078, 0x4014,
-	0x2079, 0x0200, 0x2071, 0x4a40, 0x2091, 0x8000, 0x2104, 0xa084,
-	0x000f, 0x0079, 0x401b, 0x405d, 0x4025, 0x4025, 0x4025, 0x4025,
-	0x4025, 0x4023, 0x4023, 0x1078, 0x28ec, 0x784b, 0x0004, 0x7848,
-	0xa084, 0x0004, 0x00c0, 0x4027, 0x784b, 0x0008, 0x7848, 0xa084,
-	0x0008, 0x00c0, 0x402e, 0x68b4, 0xc0f5, 0x68b6, 0x7858, 0xc0f5,
-	0x785a, 0x7830, 0xd0bc, 0x00c0, 0x405d, 0x007e, 0x2001, 0x4a04,
-	0x2004, 0xd0ec, 0x007f, 0x0040, 0x4049, 0xb284, 0x0300, 0x0078,
-	0x404b, 0xb284, 0x0400, 0x0040, 0x4051, 0x0018, 0x405d, 0x0078,
-	0x4053, 0x0028, 0x405d, 0x681c, 0xd0ac, 0x00c0, 0x405b, 0x1078,
-	0x40d5, 0x0078, 0x405d, 0x781b, 0x00f0, 0x2091, 0x8001, 0x0f7f,
-	0x0e7f, 0x007c, 0x0c7e, 0x2001, 0x4a01, 0x2004, 0xd0ac, 0x00c0,
-	0x40c7, 0x6814, 0x8007, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003,
-	0xb28c, 0x0300, 0x0040, 0x4078, 0xa0e0, 0x4ec0, 0x0078, 0x407a,
-	0xa0e0, 0x4f40, 0x6004, 0xa084, 0x000a, 0x00c0, 0x40c7, 0x6108,
-	0xa194, 0xff00, 0x0040, 0x40c7, 0xa18c, 0x00ff, 0x2001, 0x000a,
-	0xa106, 0x0040, 0x40a6, 0x2001, 0x000c, 0xa106, 0x0040, 0x40aa,
-	0x2001, 0x0012, 0xa106, 0x0040, 0x40ae, 0x2001, 0x0014, 0xa106,
-	0x0040, 0x40b2, 0x2001, 0x0019, 0xa106, 0x0040, 0x40b6, 0x2001,
-	0x0032, 0xa106, 0x0040, 0x40ba, 0x0078, 0x40be, 0x2009, 0x000c,
-	0x0078, 0x40c0, 0x2009, 0x0012, 0x0078, 0x40c0, 0x2009, 0x0014,
-	0x0078, 0x40c0, 0x2009, 0x0019, 0x0078, 0x40c0, 0x2009, 0x0020,
-	0x0078, 0x40c0, 0x2009, 0x003f, 0x0078, 0x40c0, 0x2011, 0x0000,
-	0x2100, 0xa205, 0x600a, 0x6004, 0xa085, 0x0002, 0x6006, 0x0c7f,
-	0x007c, 0x781b, 0x0076, 0x007c, 0x781b, 0x0075, 0x007c, 0x781b,
-	0x0064, 0x007c, 0x781b, 0x0061, 0x007c, 0x2009, 0x4a19, 0x210c,
-	0xa186, 0x0000, 0x0040, 0x40e7, 0xa186, 0x0001, 0x0040, 0x40ea,
-	0x701f, 0x000b, 0x7067, 0x0001, 0x781b, 0x0047, 0x007c, 0x781b,
-	0x00e7, 0x007c, 0x701f, 0x000a, 0x007c, 0x2009, 0x4a19, 0x210c,
-	0xa186, 0x0000, 0x0040, 0x4102, 0xa186, 0x0001, 0x0040, 0x40ff,
-	0x701f, 0x000b, 0x7067, 0x0001, 0x781b, 0x0047, 0x007c, 0x701f,
-	0x000a, 0x007c, 0x781b, 0x00e6, 0x007c, 0x781b, 0x00f0, 0x007c,
-	0x781b, 0x00ef, 0x007c, 0x781b, 0x00c0, 0x007c, 0x781b, 0x00bf,
-	0x007c, 0x6818, 0xd0fc, 0x0040, 0x4117, 0x681b, 0x001d, 0x7067,
-	0x0001, 0x781b, 0x0047, 0x007c, 0x7830, 0xa084, 0x00c0, 0x00c0,
-	0x4130, 0x7808, 0xc08c, 0x780a, 0x0005, 0x0005, 0x0005, 0x0005,
-	0x78ec, 0xa084, 0x0021, 0x0040, 0x4130, 0x7808, 0xc08d, 0x780a,
-	0x007c, 0x7808, 0xc08d, 0x780a, 0x007c, 0x7830, 0xa084, 0x0040,
-	0x00c0, 0x4135, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x0040, 0x4144,
-	0xb284, 0x0300, 0x0078, 0x4146, 0xb284, 0x0400, 0x0040, 0x414c,
-	0x0098, 0x4150, 0x0078, 0x414e, 0x00a8, 0x4150, 0x78ac, 0x007c,
-	0x7808, 0xa084, 0xfffd, 0x780a, 0x0005, 0x0005, 0x0005, 0x0005,
-	0x78ec, 0xa084, 0x0021, 0x0040, 0x4173, 0x007e, 0x2001, 0x4a04,
-	0x2004, 0xd0ec, 0x007f, 0x0040, 0x4169, 0xb284, 0x0300, 0x0078,
-	0x416b, 0xb284, 0x0400, 0x0040, 0x4171, 0x0098, 0x416d, 0x0078,
-	0x4173, 0x00a8, 0x4171, 0x78ac, 0x007e, 0x7808, 0xa085, 0x0002,
-	0x780a, 0x007f, 0x007c, 0xa784, 0x0001, 0x00c0, 0x360e, 0xa784,
-	0x0070, 0x0040, 0x418b, 0x0c7e, 0x2d60, 0x2f68, 0x1078, 0x2881,
-	0x2d78, 0x2c68, 0x0c7f, 0xa784, 0x0008, 0x0040, 0x4198, 0x784b,
-	0x0008, 0x78ec, 0xa084, 0x0003, 0x0040, 0x2946, 0x0078, 0x40c9,
-	0xa784, 0x0004, 0x0040, 0x41c7, 0x78b8, 0xa084, 0x4001, 0x0040,
-	0x41c7, 0x784b, 0x0008, 0x78ec, 0xa084, 0x0003, 0x0040, 0x2946,
-	0x78e4, 0xa084, 0x0007, 0xa086, 0x0001, 0x00c0, 0x41c7, 0x78c0,
-	0xa685, 0x4800, 0x2030, 0x7e5a, 0x781b, 0x00f0, 0x007c, 0x784b,
-	0x0008, 0x6818, 0xd0fc, 0x0040, 0x41c4, 0x681b, 0x0015, 0xd6f4,
-	0x0040, 0x41c4, 0x681b, 0x0007, 0x1078, 0x40d5, 0x007c, 0x681b,
-	0x0003, 0x7858, 0xa084, 0x3f00, 0x681e, 0x682f, 0x0000, 0x6833,
-	0x0000, 0x784b, 0x0008, 0x78ec, 0xa084, 0x0003, 0x0040, 0x2f84,
-	0x007e, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x41e4,
-	0xb284, 0x0300, 0x0078, 0x41e6, 0xb284, 0x0400, 0x0040, 0x41ec,
-	0x0018, 0x2942, 0x0078, 0x41ee, 0x0028, 0x2942, 0x0078, 0x3ea2,
-	0x6b14, 0x8307, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xd3fc,
-	0x0040, 0x41fe, 0xa080, 0x4f40, 0x0078, 0x4200, 0xa080, 0x4ec0,
-	0x2060, 0x2048, 0x705a, 0x2a60, 0x007c, 0x0020, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000,
-	0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0062,
-	0x0009, 0x0014, 0x0014, 0x9848, 0x0014, 0x0014, 0x9906, 0x98f4,
-	0x0014, 0x0014, 0x0080, 0x00f1, 0x0100, 0x0402, 0x2008, 0xf880,
-	0x0018, 0xa20a, 0x0014, 0x300b, 0xa20c, 0x0014, 0x2500, 0x0013,
-	0x2500, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010,
-	0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0xa200,
-	0x3806, 0x8839, 0x20c4, 0x0864, 0xa850, 0x3008, 0x28c1, 0x9d0d,
-	0xa201, 0x300c, 0x2847, 0x8161, 0x846a, 0x8000, 0x84a4, 0x1856,
-	0x883a, 0xa808, 0x28e2, 0x9cc2, 0xa8f3, 0x0864, 0xa83e, 0x300c,
-	0xa801, 0x3008, 0x28e1, 0x9cc2, 0x2021, 0xa81b, 0xa205, 0x870c,
-	0xd8de, 0x64a0, 0x6de0, 0x6fc0, 0x63a4, 0x6c80, 0x0212, 0xa205,
-	0x883d, 0x9d25, 0x882b, 0x1814, 0x883b, 0x9d2b, 0x883b, 0x7027,
-	0x85f2, 0xa737, 0xa532, 0xf003, 0x8576, 0x8677, 0xa812, 0x883e,
-	0xa810, 0x280c, 0xa204, 0x64c0, 0x6de0, 0x67a0, 0x6fc0, 0x9d25,
-	0x1814, 0x9d2b, 0x883b, 0x7023, 0x8576, 0x8677, 0xa802, 0x7861,
-	0x883e, 0x206b, 0x28c1, 0x9d0d, 0x2044, 0x2103, 0x20a2, 0x2081,
-	0xa8c9, 0xa207, 0x2901, 0xa80a, 0x0014, 0xa203, 0x8000, 0x85a4,
-	0x1872, 0x879a, 0x883c, 0x1fe2, 0xf601, 0xa208, 0x856e, 0x866f,
-	0x7161, 0x0014, 0x0704, 0x3008, 0x9cc2, 0x0014, 0xa202, 0x8000,
-	0x85a4, 0x3009, 0x84a8, 0x19e2, 0xf844, 0x856e, 0x883f, 0x08e6,
-	0xa8f5, 0xf861, 0xa8ea, 0xf801, 0x0014, 0xf881, 0x0016, 0x85b2,
-	0x80f0, 0x9532, 0xfaa2, 0x1de2, 0x0014, 0x8532, 0xf221, 0x0014,
-	0x1de2, 0x84a8, 0xd6e0, 0x1fe6, 0x0014, 0x3008, 0x8000, 0x284a,
-	0x1011, 0xa8fc, 0x3008, 0x9d25, 0x8000, 0xa000, 0x2802, 0x1011,
-	0xa8fd, 0x9d2b, 0xa887, 0x3008, 0x9d25, 0x283b, 0x1011, 0xa8fd,
-	0xa209, 0x0017, 0x300c, 0x8000, 0x85a4, 0x1de2, 0xdac1, 0x0014,
-	0x0210, 0xa801, 0x0014, 0x26e0, 0x873a, 0xfaa3, 0x19f2, 0x26e0,
-	0x18f2, 0x0014, 0xa20b, 0x0014, 0xa20d, 0x3806, 0x0210, 0x9d17,
-	0x0704, 0xa206, 0x6865, 0x817e, 0x842a, 0x1dc1, 0x8823, 0x0016,
-	0x6042, 0x8008, 0xa8fa, 0x8000, 0x84a4, 0x8160, 0x842a, 0xf021,
-	0x3008, 0x84a8, 0x11d6, 0x7042, 0x20dd, 0x0011, 0x20d4, 0x8822,
-	0x0016, 0x7944, 0x8421, 0xa020, 0xa532, 0x84a1, 0x0016, 0x7944,
-	0x8421, 0xa0df, 0x9532, 0x84a1, 0x0016, 0x0000, 0x127e, 0x70d4,
-	0xa084, 0x4600, 0x8004, 0x2090, 0x7204, 0x7008, 0xc09c, 0xa205,
-	0x00c0, 0x4342, 0x720c, 0x82ff, 0x0040, 0x433d, 0x8aff, 0x00c0,
-	0x4342, 0x7200, 0xd284, 0x00c0, 0x4342, 0x7003, 0x0008, 0x127f,
-	0x2000, 0x007c, 0x7000, 0xa084, 0x0003, 0x7002, 0xc69c, 0xd084,
-	0x0040, 0x4374, 0x2001, 0x4a05, 0x2004, 0xd0ec, 0x00c0, 0x43a5,
-	0xd0e4, 0x00c0, 0x435a, 0x2001, 0x04fd, 0x2004, 0xa086, 0x0003,
-	0x0040, 0x43a5, 0x0e7e, 0x2071, 0x0010, 0x2009, 0x0007, 0x7008,
-	0xa084, 0x3000, 0x00c0, 0x435d, 0x8109, 0x00c0, 0x435f, 0x0e7f,
-	0x2009, 0x0007, 0x7008, 0xa084, 0x3000, 0x00c0, 0x435a, 0x8109,
-	0x00c0, 0x436a, 0x0078, 0x43a5, 0x7108, 0xd1fc, 0x0040, 0x437f,
-	0x1078, 0x44ba, 0x8aff, 0x0040, 0x432c, 0x0078, 0x4374, 0x700c,
-	0xa08c, 0x03ff, 0x0040, 0x43aa, 0x7004, 0xd084, 0x0040, 0x439c,
-	0x7014, 0xa005, 0x00c0, 0x4398, 0x7010, 0x7310, 0xa306, 0x00c0,
-	0x438c, 0x2300, 0xa005, 0x0040, 0x439c, 0xa102, 0x00c8, 0x4374,
-	0x7007, 0x0010, 0x0078, 0x43a5, 0x8aff, 0x0040, 0x43aa, 0x1078,
-	0x46a3, 0x00c0, 0x439f, 0x0040, 0x4374, 0x1078, 0x4443, 0x127f,
-	0x2000, 0x007c, 0x7204, 0x7108, 0xc19c, 0x8103, 0x00c8, 0x43b9,
-	0x1078, 0x44ba, 0x0078, 0x43aa, 0x7003, 0x0008, 0x127f, 0x2000,
-	0x007c, 0xa205, 0x00c0, 0x43a5, 0x7003, 0x0008, 0x127f, 0x2000,
-	0x007c, 0x6428, 0x84ff, 0x0040, 0x43ed, 0x2c70, 0x7004, 0xa0bc,
-	0x000f, 0xa7b8, 0x43fd, 0x273c, 0x87fb, 0x00c0, 0x43db, 0x0048,
-	0x43d3, 0x1078, 0x28ec, 0x609c, 0xa075, 0x0040, 0x43ed, 0x0078,
-	0x43c6, 0x2039, 0x43f2, 0x2704, 0xae68, 0x6808, 0xa630, 0x680c,
-	0xa529, 0x8421, 0x0040, 0x43ed, 0x8738, 0x2704, 0xa005, 0x00c0,
-	0x43dc, 0x709c, 0xa075, 0x00c0, 0x43c6, 0x007c, 0x0000, 0x0005,
-	0x0009, 0x000d, 0x0011, 0x0015, 0x0019, 0x001d, 0x0000, 0x0003,
-	0x0009, 0x000f, 0x0015, 0x001b, 0x0000, 0x0000, 0x43f2, 0x43ef,
-	0x0000, 0x0000, 0x8000, 0x0000, 0x43f2, 0x0000, 0x43fa, 0x43f7,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x43fa, 0x0000, 0x43f5, 0x43f5,
-	0x0000, 0x0000, 0x8000, 0x0000, 0x43f5, 0x0000, 0x43fb, 0x43fb,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x43fb, 0x2079, 0x4a00, 0x2071,
-	0x0010, 0x7007, 0x000a, 0x7007, 0x0002, 0x7003, 0x0001, 0x7810,
-	0xd0ec, 0x0040, 0x4431, 0x2009, 0x0001, 0x2071, 0x0020, 0x0078,
-	0x4435, 0x2009, 0x0002, 0x2071, 0x0050, 0x7007, 0x000a, 0x7007,
-	0x0002, 0x7003, 0x0000, 0x8109, 0x0040, 0x4442, 0x2071, 0x0020,
-	0x0078, 0x4435, 0x007c, 0x7004, 0x8004, 0x00c8, 0x44a6, 0x7007,
-	0x0012, 0x2019, 0x0000, 0x7108, 0x7008, 0xa106, 0x00c0, 0x444b,
-	0xa184, 0x01e0, 0x0040, 0x4456, 0x1078, 0x28ec, 0x7810, 0xd0ec,
-	0x0040, 0x4470, 0x2001, 0x04fd, 0x2004, 0xa086, 0x0003, 0x00c0,
-	0x4474, 0xa184, 0x4000, 0x0040, 0x4478, 0xa382, 0x0003, 0x00c8,
-	0x4478, 0xa184, 0x0004, 0x0040, 0x444b, 0x8318, 0x0078, 0x444b,
-	0x7814, 0xd0ec, 0x00c0, 0x4478, 0xa184, 0x4000, 0x00c0, 0x444b,
-	0xa19c, 0x300c, 0xa386, 0x2004, 0x0040, 0x4486, 0xa386, 0x0008,
-	0x0040, 0x4491, 0xa386, 0x200c, 0x00c0, 0x444b, 0x7200, 0x8204,
-	0x0048, 0x4491, 0x730c, 0xa384, 0x03ff, 0x0040, 0x4491, 0x1078,
-	0x28ec, 0x7007, 0x0012, 0x7000, 0xd084, 0x00c0, 0x44a6, 0x7008,
-	0xa084, 0x01e0, 0x00c0, 0x44a6, 0x7310, 0x7014, 0xa305, 0x0040,
-	0x44a6, 0x710c, 0xa184, 0x03ff, 0x00c0, 0x4443, 0x7007, 0x0012,
-	0x7007, 0x0008, 0x7004, 0xd09c, 0x00c0, 0x44aa, 0x7007, 0x0012,
-	0x7108, 0x8103, 0x0048, 0x44ae, 0x7003, 0x0008, 0x007c, 0x7108,
-	0x0078, 0x44ba, 0xa184, 0x01e0, 0x00c0, 0x44ee, 0x7108, 0xa184,
-	0x01e0, 0x00c0, 0x44ee, 0xa184, 0x0007, 0x0079, 0x44c7, 0x44d1,
-	0x44e1, 0x44cf, 0x44e1, 0x44cf, 0x4533, 0x44cf, 0x4531, 0x1078,
-	0x28ec, 0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, 0x00c0,
-	0x44dc, 0x2049, 0x0000, 0x007c, 0x1078, 0x46a3, 0x00c0, 0x44dc,
-	0x007c, 0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, 0x0040,
-	0x44ed, 0x1078, 0x46a3, 0x00c0, 0x44e9, 0x007c, 0x7007, 0x0012,
-	0x7108, 0x00e0, 0x44f1, 0x2091, 0x6000, 0x00e0, 0x44f5, 0x2091,
-	0x6000, 0x7007, 0x0012, 0x7007, 0x0008, 0x7004, 0xd09c, 0x00c0,
-	0x44fd, 0x7007, 0x0012, 0x7108, 0xd1fc, 0x00c0, 0x4501, 0x7003,
-	0x0000, 0x7000, 0xa005, 0x00c0, 0x4515, 0x7004, 0xa005, 0x00c0,
-	0x4515, 0x700c, 0xa005, 0x0040, 0x4517, 0x0078, 0x44f9, 0x2049,
-	0x0000, 0xb284, 0x0100, 0x0040, 0x4521, 0x2001, 0x0000, 0x0078,
-	0x4523, 0x2001, 0x0001, 0x1078, 0x3ff5, 0x6818, 0xa084, 0x8000,
-	0x0040, 0x452c, 0x681b, 0x0002, 0x007c, 0x1078, 0x28ec, 0x1078,
-	0x28ec, 0x1078, 0x4570, 0x7210, 0x7114, 0x700c, 0xa09c, 0x03ff,
-	0x2800, 0xa300, 0xa211, 0xa189, 0x0000, 0x1078, 0x4570, 0x2704,
-	0x2c58, 0xac60, 0x6308, 0x2200, 0xa322, 0x630c, 0x2100, 0xa31b,
-	0x2400, 0xa305, 0x0040, 0x4556, 0x00c8, 0x4556, 0x8412, 0x8210,
-	0x830a, 0xa189, 0x0000, 0x2b60, 0x0078, 0x453d, 0x2b60, 0x8a07,
-	0x007e, 0x6004, 0xa084, 0x0008, 0x0040, 0x4562, 0xa7ba, 0x43f7,
-	0x0078, 0x4564, 0xa7ba, 0x43ef, 0x007f, 0xa73d, 0x2c00, 0x6886,
-	0x6f8a, 0x6c92, 0x6b8e, 0x7007, 0x0012, 0x1078, 0x4443, 0x007c,
-	0x8a50, 0x8739, 0x2704, 0xa004, 0x00c0, 0x4584, 0x6000, 0xa064,
-	0x00c0, 0x457b, 0x2d60, 0x6004, 0xa084, 0x000f, 0xa080, 0x440d,
-	0x203c, 0x87fb, 0x1040, 0x28ec, 0x007c, 0x127e, 0x0d7e, 0x70d4,
-	0xa084, 0x4600, 0x8004, 0x2090, 0x0d7f, 0x6884, 0x2060, 0x6888,
-	0x6b8c, 0x6c90, 0x8057, 0xaad4, 0x00ff, 0xa084, 0x00ff, 0x007e,
-	0x6804, 0xa084, 0x0008, 0x007f, 0x0040, 0x45a2, 0xa0b8, 0x43f7,
-	0x0078, 0x45a4, 0xa0b8, 0x43ef, 0xb284, 0x0100, 0x0040, 0x45ab,
-	0x7e20, 0x0078, 0x45ac, 0x7e24, 0xa6b5, 0x000c, 0x681c, 0xd0b4,
-	0x0040, 0x45b3, 0xc685, 0x2400, 0xa305, 0x0040, 0x45dd, 0x2c58,
-	0x2704, 0x6104, 0xac60, 0x6000, 0xa400, 0x701a, 0x6004, 0xa301,
-	0x701e, 0xa184, 0x0008, 0x0040, 0x45cd, 0x6010, 0xa081, 0x0000,
-	0x7022, 0x6014, 0xa081, 0x0000, 0x7026, 0x6208, 0x2400, 0xa202,
-	0x7012, 0x620c, 0x2300, 0xa203, 0x7016, 0x7602, 0x7007, 0x0001,
-	0x2b60, 0x1078, 0x46c6, 0x0078, 0x45df, 0x1078, 0x46a3, 0x00c0,
-	0x45dd, 0x127f, 0x2000, 0x007c, 0x127e, 0x0d7e, 0x70d4, 0xa084,
-	0x4600, 0x8004, 0x2090, 0x0d7f, 0x7007, 0x0004, 0x7004, 0xd094,
-	0x00c0, 0x45ee, 0x7003, 0x0008, 0x127f, 0x2000, 0x007c, 0x127e,
-	0x0d7e, 0x70d4, 0xa084, 0x4600, 0x8004, 0x2090, 0x0d7f, 0x7e20,
-	0xb284, 0x0100, 0x00c0, 0x4605, 0x7e24, 0xa6b5, 0x000c, 0x681c,
-	0xd0ac, 0x00c0, 0x4610, 0xc685, 0x7003, 0x0000, 0x7007, 0x0004,
-	0x6828, 0x2050, 0x2d60, 0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x43fd,
-	0x273c, 0x87fb, 0x00c0, 0x4626, 0x0048, 0x4620, 0x1078, 0x28ec,
-	0x689c, 0xa065, 0x0040, 0x462a, 0x0078, 0x4613, 0x1078, 0x46a3,
-	0x00c0, 0x4626, 0x127f, 0x2000, 0x007c, 0x127e, 0x007e, 0x017e,
-	0x0d7e, 0x70d4, 0xa084, 0x4600, 0x8004, 0x2090, 0x7e20, 0xb284,
-	0x0100, 0x00c0, 0x463c, 0x7e24, 0x0d7f, 0x037f, 0x047f, 0xa6b5,
-	0x000c, 0x681c, 0xd0b4, 0x0040, 0x464a, 0xc685, 0x7003, 0x0000,
-	0x7007, 0x0004, 0x2049, 0x462d, 0x6828, 0xa055, 0x0040, 0x46a0,
-	0x2d70, 0x2e60, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x43fd, 0x273c,
-	0x87fb, 0x00c0, 0x4666, 0x0048, 0x465f, 0x1078, 0x28ec, 0x709c,
-	0xa075, 0x2060, 0x0040, 0x46a0, 0x0078, 0x4652, 0x2704, 0xae68,
-	0x6808, 0xa422, 0x680c, 0xa31b, 0x0048, 0x467f, 0x8a51, 0x00c0,
-	0x4673, 0x1078, 0x28ec, 0x8738, 0x2704, 0xa005, 0x00c0, 0x4667,
-	0x709c, 0xa075, 0x2060, 0x0040, 0x46a0, 0x0078, 0x4652, 0x8422,
-	0x8420, 0x831a, 0xa399, 0x0000, 0x6908, 0x2400, 0xa122, 0x690c,
-	0x2300, 0xa11b, 0x00c8, 0x468e, 0x1078, 0x28ec, 0xb284, 0x0100,
-	0x0040, 0x469c, 0x2001, 0x4a04, 0x2004, 0xd0ec, 0x00c0, 0x469c,
-	0x2071, 0x0050, 0x0078, 0x469e, 0x2071, 0x0020, 0x0078, 0x45b3,
-	0x127f, 0x2000, 0x007c, 0x7008, 0xa084, 0x0003, 0xa086, 0x0003,
-	0x00c0, 0x46ab, 0x007c, 0x2704, 0xac78, 0x7800, 0x701a, 0x7804,
-	0x701e, 0x7808, 0x7012, 0x780c, 0x7016, 0x6004, 0xa084, 0x0008,
-	0x0040, 0x46be, 0x7810, 0x7022, 0x7814, 0x7026, 0x7602, 0x7004,
-	0xa084, 0x0010, 0xc085, 0x7006, 0x2079, 0x4a00, 0x8a51, 0x0040,
-	0x46e1, 0x8738, 0x2704, 0xa005, 0x00c0, 0x46dc, 0x609c, 0xa005,
-	0x0040, 0x46e2, 0x2060, 0x6004, 0xa084, 0x000f, 0xa080, 0x43fd,
-	0x203c, 0x87fb, 0x1040, 0x28ec, 0x7008, 0xa084, 0x0003, 0xa086,
-	0x0003, 0x007c, 0x2051, 0x0000, 0x007c, 0x127e, 0x007e, 0x0d7e,
-	0x70d4, 0xa084, 0x4600, 0x8004, 0x2090, 0x0d7f, 0x087f, 0x7108,
-	0xa184, 0x0003, 0x00c0, 0x46fa, 0x6828, 0xa005, 0x0040, 0x470a,
-	0x0078, 0x4342, 0x7108, 0xd1fc, 0x0040, 0x4702, 0x1078, 0x44ba,
-	0x0078, 0x46ef, 0x7007, 0x0010, 0x7108, 0xd1fc, 0x0040, 0x4704,
-	0x1078, 0x44ba, 0x7008, 0xa086, 0x0008, 0x00c0, 0x46ef, 0x7000,
-	0xa005, 0x00c0, 0x46ef, 0x7003, 0x0000, 0x2049, 0x0000, 0x127f,
-	0x2000, 0x007c, 0x127e, 0x147e, 0x137e, 0x157e, 0x0c7e, 0x0d7e,
-	0x70d4, 0xa084, 0x4600, 0x8004, 0x2090, 0x0d7f, 0x2049, 0x471a,
-	0xad80, 0x0011, 0x20a0, 0xb284, 0x0100, 0x0040, 0x473d, 0x2001,
-	0x4a04, 0x2004, 0xd0ec, 0x0040, 0x4739, 0x2099, 0x0031, 0x0078,
-	0x473f, 0x2099, 0x0032, 0x0078, 0x473f, 0x2099, 0x0031, 0x700c,
-	0xa084, 0x03ff, 0x682a, 0x7007, 0x0008, 0x7007, 0x0002, 0x7003,
-	0x0001, 0x0040, 0x474e, 0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084,
-	0x03ff, 0x0040, 0x475a, 0x7007, 0x0004, 0x7004, 0xa084, 0x0004,
-	0x00c0, 0x4755, 0x0c7f, 0x2049, 0x0000, 0x7003, 0x0000, 0x157f,
-	0x137f, 0x147f, 0x127f, 0x2000, 0x007c, 0x2091, 0x8000, 0x2091,
-	0x6000, 0x78ac, 0xa005, 0x00c0, 0x477c, 0x7974, 0x70d0, 0xa106,
-	0x00c0, 0x477c, 0x781c, 0xa005, 0x0040, 0x477c, 0x781f, 0x0000,
-	0x0068, 0x477c, 0x2091, 0x4080, 0x7830, 0x8001, 0x7832, 0x00c0,
-	0x4804, 0x7834, 0x7832, 0x7810, 0xd0ec, 0x00c0, 0x47fd, 0x2061,
-	0x6fc0, 0x2069, 0x4a80, 0xc7fd, 0x68d0, 0xa005, 0x0040, 0x4796,
-	0x8001, 0x68d2, 0x00c0, 0x4796, 0x1078, 0x4998, 0x6800, 0xa084,
-	0x000f, 0x0040, 0x47ab, 0xa086, 0x0001, 0x0040, 0x47ab, 0x6844,
-	0xa00d, 0x0040, 0x47ab, 0x2104, 0xa005, 0x0040, 0x47ab, 0x8001,
-	0x200a, 0x0040, 0x4909, 0x6814, 0xa005, 0x0040, 0x47d0, 0x8001,
-	0x6816, 0x00c0, 0x47d0, 0x68a7, 0x0001, 0x0f7e, 0xd7fc, 0x00c0,
-	0x47c5, 0x7810, 0xd0ec, 0x0040, 0x47c1, 0x2079, 0x0100, 0x0078,
-	0x47c7, 0x2079, 0x0200, 0x0078, 0x47c7, 0x2079, 0x0100, 0x1078,
-	0x4131, 0x0f7f, 0x6864, 0xa005, 0x0040, 0x47d0, 0x1078, 0x25de,
-	0x6880, 0xa005, 0x0040, 0x47dd, 0x8001, 0x6882, 0x00c0, 0x47dd,
-	0x6867, 0x0000, 0x68d4, 0xc0dd, 0x68d6, 0x68d4, 0xd0fc, 0x0040,
-	0x47fa, 0xc0fc, 0x68d6, 0x20a9, 0x0200, 0x603c, 0xa005, 0x0040,
-	0x47f6, 0x8001, 0x603e, 0x68d4, 0xc0fd, 0x68d6, 0x00c0, 0x47f6,
-	0x6010, 0xa005, 0x0040, 0x47f6, 0x1078, 0x25de, 0xace0, 0x0010,
-	0x00f0, 0x47e5, 0xd7fc, 0x0040, 0x4804, 0x2061, 0x4fc0, 0x2069,
-	0x4a40, 0xc7fc, 0x0078, 0x478c, 0x1078, 0x4840, 0x7838, 0x8001,
-	0x783a, 0x00c0, 0x4826, 0x783c, 0x783a, 0x2061, 0x4fc0, 0x2069,
-	0x4a40, 0xc7fc, 0x680c, 0xa005, 0x0040, 0x4818, 0x1078, 0x487f,
-	0xd7fc, 0x00c0, 0x4826, 0x7810, 0xd0ec, 0x00c0, 0x4826, 0x2061,
-	0x6fc0, 0x2069, 0x4a80, 0xc7fd, 0x0078, 0x4812, 0x7814, 0xd0e4,
-	0x00c0, 0x482a, 0x7810, 0xd0cc, 0x0040, 0x483d, 0xd0ac, 0x00c0,
-	0x4836, 0xd0a4, 0x0040, 0x483d, 0xc0ad, 0x7812, 0x2091, 0x8001,
-	0x0068, 0x483c, 0x1078, 0x2368, 0x007c, 0x2091, 0x8001, 0x007c,
-	0x7840, 0x8001, 0x7842, 0x00c0, 0x487e, 0x7844, 0x7842, 0x2091,
-	0x8000, 0x2061, 0x4fc0, 0x2069, 0x4a40, 0xc7fc, 0x6810, 0xa005,
-	0x00c0, 0x4854, 0x2001, 0x0101, 0x8001, 0x6812, 0xd7fc, 0x0040,
-	0x485d, 0xa080, 0x90d0, 0x0078, 0x485f, 0xa080, 0x8fc0, 0x2040,
-	0x2004, 0xa065, 0x0040, 0x4870, 0x6024, 0xa005, 0x0040, 0x486c,
-	0x8001, 0x6026, 0x0040, 0x48ad, 0x6000, 0x2c40, 0x0078, 0x4861,
-	0xd7fc, 0x00c0, 0x487e, 0x7810, 0xd0ec, 0x00c0, 0x487e, 0x2061,
-	0x6fc0, 0x2069, 0x4a80, 0xc7fd, 0x0078, 0x484e, 0x007c, 0x2009,
-	0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0040, 0x4899, 0x6024,
-	0xa005, 0x0040, 0x488f, 0x8001, 0x6026, 0x0078, 0x4897, 0x6008,
-	0xc09c, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0078, 0x4899, 0xa18d,
-	0x0100, 0xace0, 0x0010, 0x00f0, 0x4883, 0xa184, 0x0001, 0x0040,
-	0x48a8, 0xa18c, 0xfffe, 0x690e, 0x1078, 0x25de, 0x0078, 0x48a9,
-	0x690e, 0x007c, 0x00c0, 0x48a9, 0x786c, 0x6800, 0xa005, 0x0040,
-	0x48b5, 0x684c, 0xac06, 0x0040, 0x4909, 0x6864, 0xa005, 0x0040,
-	0x48bd, 0x6027, 0x0001, 0x0078, 0x4906, 0x2c00, 0x687e, 0x601b,
+	0x6820, 0xc0c5, 0x6822, 0x70d4, 0xd0b4, 0x0040, 0x3eda, 0xc0b4,
+	0x70d6, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018,
+	0x8001, 0x601a, 0x0c7f, 0x007c, 0x0c7e, 0x2960, 0x6104, 0xa18c,
+	0xfff5, 0x6106, 0x2011, 0x0032, 0x2019, 0x0000, 0x0078, 0x3ee8,
+	0x78ab, 0x0001, 0x78ab, 0x0003, 0x78ab, 0x0001, 0x7aaa, 0x7baa,
+	0xa8c0, 0x0005, 0x6820, 0xc0c5, 0x6822, 0x0c7f, 0x007c, 0x0c7e,
+	0x7158, 0x2160, 0x2018, 0xa08c, 0x0020, 0x0040, 0x3f00, 0xc0ac,
+	0x2008, 0xa084, 0xfff0, 0xa635, 0x7e86, 0x6018, 0x789a, 0x7eae,
+	0x6612, 0x78a4, 0xa084, 0xfff0, 0xa18c, 0x000f, 0xa105, 0xc0f4,
+	0xa39c, 0x0020, 0x0040, 0x3f16, 0xa085, 0x4000, 0xc0fc, 0xd0b4,
+	0x00c0, 0x3f1b, 0xc0fd, 0x78a6, 0x6016, 0x788a, 0xa6b4, 0x000f,
+	0x8637, 0x8204, 0x8004, 0xa084, 0x00ff, 0xa605, 0x600e, 0x6004,
+	0xa084, 0xfff5, 0x6006, 0x0c7f, 0x007c, 0x0c7e, 0x7058, 0x2060,
+	0x6018, 0x789a, 0x78a4, 0xa084, 0xfff0, 0x78a6, 0x6012, 0x7884,
+	0xa084, 0xfff0, 0x7886, 0x600c, 0xa084, 0x00ff, 0x600e, 0x0c7f,
+	0x007c, 0xa282, 0x0002, 0x00c0, 0x4040, 0x7aa8, 0x6920, 0xc1bd,
+	0x6922, 0xd1cc, 0x0040, 0x3f7c, 0xc1cc, 0x6922, 0xa294, 0x00ff,
+	0xa282, 0x0002, 0x00c8, 0x4040, 0x1078, 0x3fcd, 0x1078, 0x3f2d,
+	0xa980, 0x0001, 0x200c, 0x1078, 0x4183, 0x1078, 0x3e7c, 0x88ff,
+	0x0040, 0x3f72, 0x789b, 0x0060, 0x2800, 0x78aa, 0x7e58, 0xc695,
+	0x7e5a, 0xd6d4, 0x00c0, 0x3f6f, 0x781b, 0x0061, 0x007c, 0x781b,
+	0x0075, 0x007c, 0x7e58, 0xd6d4, 0x00c0, 0x3f79, 0x781b, 0x0064,
+	0x007c, 0x781b, 0x0076, 0x007c, 0xa282, 0x0002, 0x00c8, 0x3f84,
+	0xa284, 0x0001, 0x0040, 0x3f8d, 0x7158, 0xa188, 0x0000, 0x210c,
+	0xd1ec, 0x00c0, 0x3f8d, 0x2011, 0x0000, 0x1078, 0x40b5, 0x1078,
+	0x3fcd, 0x1078, 0x3f2d, 0x7858, 0xc095, 0x785a, 0x781b, 0x0075,
+	0x007c, 0x0c7e, 0x027e, 0x2960, 0x6000, 0x2011, 0x0001, 0xd0ec,
+	0x00c0, 0x3fae, 0x6014, 0xa084, 0x0040, 0x00c0, 0x3fac, 0xc1a4,
+	0x6106, 0xa006, 0x0078, 0x3fca, 0x2011, 0x0000, 0x78ab, 0x0001,
+	0x78ab, 0x0002, 0x78ab, 0x0003, 0x7aaa, 0xa8c0, 0x0004, 0x70d4,
+	0xd0b4, 0x0040, 0x3fc6, 0xc0b4, 0x70d6, 0x70b8, 0xa065, 0x6008,
+	0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x6820, 0xa085,
+	0x0200, 0x6822, 0x027f, 0x0c7f, 0x007c, 0x0c7e, 0x7058, 0x2060,
+	0x82ff, 0x0040, 0x3fd5, 0x2011, 0x0040, 0x6018, 0xa080, 0x0002,
+	0x789a, 0x78a4, 0xa084, 0xffbf, 0xa205, 0xc0fc, 0xd0b4, 0x00c0,
+	0x3fe2, 0xc0fd, 0x78a6, 0x6016, 0x788a, 0x6004, 0xc0a4, 0x6006,
+	0x0c7f, 0x007c, 0x007e, 0x7000, 0xa086, 0x0003, 0x0040, 0x3ff3,
+	0x007f, 0x0078, 0x3ff6, 0x007f, 0x0078, 0x403d, 0xd6ac, 0x0040,
+	0x403d, 0x7888, 0xa084, 0x0040, 0x0040, 0x403d, 0x7bb8, 0xa384,
+	0x003f, 0x831b, 0x00c8, 0x4005, 0x8000, 0xa005, 0x0040, 0x401a,
+	0x831b, 0x00c8, 0x400e, 0x8001, 0x0040, 0x403a, 0xd6f4, 0x0040,
+	0x401a, 0x78b8, 0x801b, 0x00c8, 0x4016, 0x8000, 0xa084, 0x003f,
+	0x00c0, 0x403a, 0xc6f4, 0x7e5a, 0x79d8, 0x7adc, 0x2001, 0x0001,
+	0xa108, 0x00c8, 0x4025, 0xa291, 0x0000, 0x79d2, 0x79da, 0x7ad6,
+	0x7ade, 0x1078, 0x493a, 0x781b, 0x0073, 0xb284, 0x0300, 0x0040,
+	0x4035, 0x2001, 0x0000, 0x0078, 0x4037, 0x2001, 0x0001, 0x1078,
+	0x47c2, 0x007c, 0x781b, 0x0073, 0x007c, 0x781b, 0x0076, 0x007c,
+	0x1078, 0x4068, 0x781b, 0x0075, 0x007c, 0x1078, 0x4051, 0x781b,
+	0x0075, 0x007c, 0x6827, 0x0002, 0x1078, 0x4059, 0x781b, 0x0075,
+	0x007c, 0x2001, 0x0005, 0x0078, 0x406a, 0x2001, 0x000c, 0x0078,
+	0x406a, 0x6820, 0xc0d5, 0x6822, 0x2001, 0x0006, 0x0078, 0x406a,
+	0x2001, 0x000d, 0x0078, 0x406a, 0x2001, 0x0009, 0x0078, 0x406a,
+	0x2001, 0x0007, 0x789b, 0x007e, 0x78aa, 0xc69d, 0x7e5a, 0x70d4,
+	0xd0b4, 0x0040, 0x4080, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8, 0xa065,
+	0x6008, 0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f,
+	0x007c, 0x077e, 0x873f, 0xa7bc, 0x000f, 0x873b, 0x873b, 0x8703,
+	0x017e, 0xb28c, 0x0300, 0x0040, 0x4091, 0xa0e0, 0x51c0, 0x0078,
+	0x4093, 0xa0e0, 0x5240, 0x017f, 0xa7b8, 0x0020, 0x7f9a, 0x79a4,
+	0xa184, 0x000f, 0x0040, 0x40a3, 0xa184, 0xfff0, 0x78a6, 0x6012,
+	0x6004, 0xc09d, 0x6006, 0x8738, 0x8738, 0x7f9a, 0x79a4, 0xa184,
+	0x0040, 0x0040, 0x40b3, 0xa184, 0xffbf, 0xc0fd, 0x78a6, 0x6016,
+	0x6004, 0xc0a5, 0x6006, 0x077f, 0x007c, 0x789b, 0x0010, 0x78ab,
+	0x0001, 0x78ab, 0x0002, 0x78ab, 0x0003, 0x7aaa, 0x789b, 0x0060,
+	0x78ab, 0x0004, 0x70d4, 0xd0b4, 0x0040, 0x40d3, 0xc0b4, 0x70d6,
+	0x0c7e, 0x70b8, 0xa065, 0x6008, 0xa084, 0xfbef, 0x600a, 0x6018,
+	0x8001, 0x601a, 0x0c7f, 0x007c, 0x2031, 0x0000, 0x2029, 0x0032,
+	0x789b, 0x0010, 0x78ab, 0x0001, 0x78ab, 0x0003, 0x78ab, 0x0001,
+	0x7daa, 0x7eaa, 0x789b, 0x0060, 0x78ab, 0x0005, 0x70d4, 0xd0b4,
+	0x0040, 0x40f7, 0xc0b4, 0x70d6, 0x0c7e, 0x70b8, 0xa065, 0x6008,
+	0xa084, 0xfbef, 0x600a, 0x6018, 0x8001, 0x601a, 0x0c7f, 0x007c,
+	0x157e, 0x8007, 0xa084, 0x00ff, 0x8003, 0x8003, 0xa080, 0x0020,
+	0x789a, 0x79a4, 0xa18c, 0xfff0, 0x2021, 0x416c, 0x2019, 0x0011,
+	0x20a9, 0x000e, 0x2011, 0x0032, 0x2404, 0xa084, 0xfff0, 0xa106,
+	0x0040, 0x4117, 0x8420, 0x2300, 0xa210, 0x00f0, 0x410c, 0x157f,
+	0x007c, 0x157e, 0x2001, 0x4d05, 0x2004, 0xd0e4, 0x00c0, 0x414a,
+	0x2021, 0x417a, 0x20a9, 0x0009, 0x2011, 0x0028, 0xa582, 0x0019,
+	0x0040, 0x4160, 0x0048, 0x4160, 0x8420, 0x95a9, 0x2011, 0x0032,
+	0xa582, 0x0032, 0x0040, 0x4160, 0x0048, 0x4160, 0x8420, 0x95a9,
+	0x2019, 0x000a, 0x2011, 0x0064, 0x2200, 0xa502, 0x0040, 0x4160,
+	0x0048, 0x4160, 0x8420, 0x2300, 0xa210, 0x00f0, 0x413c, 0x157f,
+	0x0078, 0x415e, 0x2021, 0x416c, 0x2019, 0x0011, 0x20a9, 0x000e,
+	0x2011, 0x0032, 0x2200, 0xa502, 0x0040, 0x4160, 0x0048, 0x4160,
+	0x8420, 0x2300, 0xa210, 0x00f0, 0x4152, 0x157f, 0xa006, 0x007c,
+	0x157f, 0xa582, 0x0064, 0x00c8, 0x4169, 0x7808, 0xa085, 0x0070,
+	0x780a, 0x2404, 0xa005, 0x007c, 0x1209, 0x3002, 0x3202, 0x4203,
+	0x4403, 0x5404, 0x5604, 0x6605, 0x6805, 0x7806, 0x7a06, 0x0c07,
+	0x0c07, 0x0e07, 0x10e1, 0x330a, 0x5805, 0x5a05, 0x6a06, 0x6c06,
+	0x7c07, 0x7e07, 0x0e00, 0x789b, 0x0010, 0xa046, 0x007c, 0xa784,
+	0x0f00, 0x800b, 0xa784, 0x001f, 0x8003, 0x8003, 0x8003, 0x8003,
+	0xa105, 0xd7fc, 0x0040, 0x4198, 0xa0e0, 0x72c0, 0x0078, 0x419a,
+	0xa0e0, 0x52c0, 0x007c, 0x0e7e, 0x0f7e, 0xd084, 0x0040, 0x41a8,
+	0x2079, 0x0100, 0x2009, 0x4d80, 0x2071, 0x4d80, 0x0078, 0x41b8,
+	0x2009, 0x4d40, 0x2071, 0x4d40, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x0040, 0x41b6, 0x2079, 0x0100, 0x0078, 0x41b8, 0x2079, 0x0200,
+	0x2091, 0x8000, 0x2104, 0xa084, 0x000f, 0x0079, 0x41bf, 0x41c9,
+	0x41c9, 0x41c9, 0x41c9, 0x41c9, 0x41c9, 0x41c7, 0x41c7, 0x1078,
+	0x290c, 0x69b4, 0xc1f5, 0xa18c, 0xff9f, 0x69b6, 0xa005, 0x0040,
+	0x4218, 0x7858, 0xa084, 0xff9f, 0xa085, 0x6000, 0x785a, 0x7828,
+	0xa086, 0x1814, 0x00c0, 0x4218, 0x784b, 0x0004, 0x7848, 0xa084,
+	0x0004, 0x00c0, 0x41de, 0x784b, 0x0008, 0x7848, 0xa084, 0x0008,
+	0x00c0, 0x41e5, 0x7830, 0xd0bc, 0x00c0, 0x4218, 0x007e, 0x2001,
+	0x4d04, 0x2004, 0xd0ec, 0x007f, 0x0040, 0x41fa, 0xb284, 0x0300,
+	0x0078, 0x41fc, 0xb284, 0x0400, 0x0040, 0x4202, 0x0018, 0x4218,
+	0x0078, 0x4204, 0x0028, 0x4218, 0x79e4, 0xa184, 0x0030, 0x0040,
+	0x4218, 0x78ec, 0xa084, 0x0003, 0x0040, 0x4218, 0x681c, 0xd0ac,
+	0x00c0, 0x4216, 0x1078, 0x42a2, 0x0078, 0x4218, 0x781b, 0x00f6,
+	0x0f7f, 0x0e7f, 0x007c, 0x0c7e, 0x2001, 0x4d01, 0x2004, 0xd0ac,
+	0x00c0, 0x4294, 0x6814, 0x8007, 0xa084, 0x000f, 0x8003, 0x8003,
+	0x8003, 0xb28c, 0x0300, 0x0040, 0x4231, 0xa0e0, 0x51c0, 0x0078,
+	0x4233, 0xa0e0, 0x5240, 0x6004, 0xa084, 0x000a, 0x00c0, 0x4294,
+	0x6108, 0xa194, 0xff00, 0x0040, 0x4294, 0xa18c, 0x00ff, 0x2001,
+	0x000a, 0xa106, 0x0040, 0x425f, 0x2001, 0x000c, 0xa106, 0x0040,
+	0x4263, 0x2001, 0x0012, 0xa106, 0x0040, 0x4267, 0x2001, 0x0014,
+	0xa106, 0x0040, 0x426b, 0x2001, 0x0019, 0xa106, 0x0040, 0x426f,
+	0x2001, 0x0032, 0xa106, 0x0040, 0x4273, 0x0078, 0x4277, 0x2009,
+	0x000c, 0x0078, 0x4279, 0x2009, 0x0012, 0x0078, 0x4279, 0x2009,
+	0x0014, 0x0078, 0x4279, 0x2009, 0x0019, 0x0078, 0x4279, 0x2009,
+	0x0020, 0x0078, 0x4279, 0x2009, 0x003f, 0x0078, 0x4279, 0x2011,
+	0x0000, 0x2100, 0xa205, 0x600a, 0x6004, 0xa085, 0x0002, 0x6006,
+	0x2061, 0x4d00, 0x6004, 0xd0bc, 0x0040, 0x4294, 0x6814, 0xd0fc,
+	0x00c0, 0x428f, 0x60ea, 0x2061, 0x4d40, 0x0078, 0x4292, 0x60ee,
+	0x2061, 0x4d80, 0x601f, 0x800f, 0x0c7f, 0x007c, 0x781b, 0x0076,
+	0x007c, 0x781b, 0x0075, 0x007c, 0x781b, 0x0064, 0x007c, 0x781b,
+	0x0061, 0x007c, 0x2009, 0x4d19, 0x210c, 0xa186, 0x0000, 0x0040,
+	0x42b4, 0xa186, 0x0001, 0x0040, 0x42b7, 0x701f, 0x000b, 0x7067,
+	0x0001, 0x781b, 0x0047, 0x007c, 0x781b, 0x00ed, 0x007c, 0x701f,
+	0x000a, 0x007c, 0x2009, 0x4d19, 0x210c, 0xa186, 0x0000, 0x0040,
+	0x42cf, 0xa186, 0x0001, 0x0040, 0x42cc, 0x701f, 0x000b, 0x7067,
+	0x0001, 0x781b, 0x0047, 0x007c, 0x701f, 0x000a, 0x007c, 0x781b,
+	0x00ec, 0x007c, 0x781b, 0x00f6, 0x007c, 0x781b, 0x00f5, 0x007c,
+	0x781b, 0x00c6, 0x007c, 0x781b, 0x00c5, 0x007c, 0x6818, 0xd0fc,
+	0x0040, 0x42e4, 0x681b, 0x001d, 0x7067, 0x0001, 0x781b, 0x0047,
+	0x007c, 0x7830, 0xa084, 0x00c0, 0x00c0, 0x42fd, 0x7808, 0xc08c,
+	0x780a, 0x0005, 0x0005, 0x0005, 0x0005, 0x78ec, 0xa084, 0x0021,
+	0x0040, 0x42fd, 0x7808, 0xc08d, 0x780a, 0x007c, 0x7808, 0xc08d,
+	0x780a, 0x007c, 0x7830, 0xa084, 0x0040, 0x00c0, 0x4302, 0x2001,
+	0x4d04, 0x2004, 0xd0ec, 0x0040, 0x4311, 0xb284, 0x0300, 0x0078,
+	0x4313, 0xb284, 0x0400, 0x0040, 0x4319, 0x0098, 0x431d, 0x0078,
+	0x431b, 0x00a8, 0x431d, 0x78ac, 0x007c, 0x7808, 0xa084, 0xfffd,
+	0x780a, 0x0005, 0x0005, 0x0005, 0x0005, 0x78ec, 0xa084, 0x0021,
+	0x0040, 0x4340, 0x007e, 0x2001, 0x4d04, 0x2004, 0xd0ec, 0x007f,
+	0x0040, 0x4336, 0xb284, 0x0300, 0x0078, 0x4338, 0xb284, 0x0400,
+	0x0040, 0x433e, 0x0098, 0x433a, 0x0078, 0x4340, 0x00a8, 0x433e,
+	0x78ac, 0x007e, 0x7808, 0xa085, 0x0002, 0x780a, 0x007f, 0x007c,
+	0xa784, 0x0001, 0x00c0, 0x36fb, 0xa784, 0x0070, 0x0040, 0x4358,
+	0x0c7e, 0x2d60, 0x2f68, 0x1078, 0x288d, 0x2d78, 0x2c68, 0x0c7f,
+	0xa784, 0x0008, 0x0040, 0x4365, 0x784b, 0x0008, 0x78ec, 0xa084,
+	0x0003, 0x0040, 0x2966, 0x0078, 0x4296, 0xa784, 0x0004, 0x0040,
+	0x4394, 0x78b8, 0xa084, 0x4001, 0x0040, 0x4394, 0x784b, 0x0008,
+	0x78ec, 0xa084, 0x0003, 0x0040, 0x2966, 0x78e4, 0xa084, 0x0007,
+	0xa086, 0x0001, 0x00c0, 0x4394, 0x78c0, 0xa685, 0x4800, 0x2030,
+	0x7e5a, 0x781b, 0x00f6, 0x007c, 0x784b, 0x0008, 0x6818, 0xd0fc,
+	0x0040, 0x4391, 0x681b, 0x0015, 0xd6f4, 0x0040, 0x4391, 0x681b,
+	0x0007, 0x1078, 0x42a2, 0x007c, 0x681b, 0x0003, 0x7858, 0xa084,
+	0x3f00, 0x681e, 0x682f, 0x0000, 0x6833, 0x0000, 0x784b, 0x0008,
+	0x78ec, 0xa084, 0x0003, 0x0040, 0x3004, 0x007e, 0x2001, 0x4d04,
+	0x2004, 0xd0ec, 0x007f, 0x0040, 0x43b1, 0xb284, 0x0300, 0x0078,
+	0x43b3, 0xb284, 0x0400, 0x0040, 0x43b9, 0x0018, 0x2962, 0x0078,
+	0x43bb, 0x0028, 0x2962, 0x0078, 0x4045, 0x6b14, 0x8307, 0xa084,
+	0x000f, 0x8003, 0x8003, 0x8003, 0xd3fc, 0x0040, 0x43cb, 0xa080,
+	0x5240, 0x0078, 0x43cd, 0xa080, 0x51c0, 0x2060, 0x2048, 0x705a,
+	0x2a60, 0x007c, 0x0020, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020,
+	0x0000, 0x0020, 0x0000, 0x0020, 0x0062, 0x0009, 0x0014, 0x0014,
+	0x9848, 0x0014, 0x0014, 0x990e, 0x98fa, 0x0014, 0x0014, 0x0080,
+	0x00f9, 0x0100, 0x0402, 0x2008, 0xf880, 0x0018, 0xa20a, 0x0014,
+	0x300b, 0xa20c, 0x0014, 0x2500, 0x0013, 0x2500, 0x0010, 0x0010,
+	0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010,
+	0x0010, 0x0010, 0x0010, 0x0010, 0xa200, 0x3806, 0x8839, 0x20c4,
+	0x0864, 0xa856, 0x3008, 0x28c1, 0x9d15, 0xa201, 0x300c, 0x2847,
+	0x8161, 0x846a, 0x8000, 0x84a4, 0x1856, 0x883a, 0xa808, 0x28e2,
+	0x9cc8, 0xa8f3, 0x0864, 0xa844, 0x300c, 0xa801, 0x3008, 0x28e1,
+	0x9cc8, 0x2021, 0xa81d, 0xa205, 0x870c, 0xd8de, 0x64a0, 0x6de0,
+	0x6fc0, 0x63a4, 0x6c80, 0x0212, 0xa205, 0x883d, 0x7942, 0x8020,
+	0xa4a1, 0x882b, 0x1814, 0x883b, 0x80df, 0x94a1, 0x7027, 0x85f2,
+	0xa737, 0xa532, 0xf003, 0x8576, 0x8677, 0xa816, 0x883e, 0xa814,
+	0x2001, 0xa812, 0xa204, 0x64c0, 0x6de0, 0x67a0, 0x6fc0, 0x7942,
+	0x8020, 0xa4a1, 0x1814, 0x80df, 0x94a1, 0x883b, 0x7023, 0x8576,
+	0x8677, 0xa802, 0x7861, 0x883e, 0x206b, 0x28c1, 0x9d15, 0x2044,
+	0x2103, 0x20a2, 0x2081, 0xa8c3, 0xa207, 0x2901, 0xa80a, 0x0014,
+	0xa203, 0x8000, 0x85a4, 0x1872, 0x879a, 0x883c, 0x1fe2, 0xf601,
+	0xa208, 0x856e, 0x866f, 0x7161, 0x0014, 0x0704, 0x3008, 0x9cc8,
+	0x0014, 0xa202, 0x8000, 0x85a4, 0x3009, 0x84a8, 0x19e2, 0xf844,
+	0x856e, 0x883f, 0x08e6, 0xa8f5, 0xf861, 0xa8ea, 0xf801, 0x0014,
+	0xf881, 0x0016, 0x85b2, 0x80f0, 0x9532, 0xfaa2, 0x1de2, 0x0014,
+	0x8532, 0xf221, 0x0014, 0x1de2, 0x84a8, 0xd6e0, 0x1fe6, 0x0014,
+	0x3008, 0x8000, 0x284a, 0x1011, 0xa8fc, 0x3008, 0x9d2d, 0x8000,
+	0xa000, 0x2802, 0x1011, 0xa8fd, 0x9d33, 0xa8bd, 0x3008, 0x9d2d,
+	0x283b, 0x1011, 0xa8fd, 0xa209, 0x0017, 0x300c, 0xa209, 0x8000,
+	0x85a4, 0x1de2, 0xa209, 0xdac1, 0x0014, 0x0210, 0xa801, 0x0014,
+	0x26e0, 0x873a, 0xfaa3, 0x19f2, 0x26e0, 0x18f2, 0x0014, 0xa20b,
+	0x0014, 0xa20d, 0x3806, 0x0210, 0x9d1f, 0x0704, 0xa206, 0x6865,
+	0x817e, 0x842a, 0x1dc1, 0x8823, 0x0016, 0x6042, 0x8008, 0xa8fa,
+	0x8000, 0x84a4, 0x8160, 0x842a, 0xf021, 0x3008, 0x84a8, 0x11d6,
+	0x7042, 0x20dd, 0x0011, 0x20d4, 0x8822, 0x0016, 0x7944, 0x8421,
+	0xa020, 0xa532, 0x84a1, 0x0016, 0x7944, 0x8421, 0xa0df, 0x9532,
+	0x84a1, 0x0016, 0x0000, 0x127e, 0x70d4, 0xa084, 0x4600, 0x8004,
+	0x2090, 0x7204, 0x7008, 0xc09c, 0xa205, 0x00c0, 0x4517, 0x720c,
+	0x82ff, 0x0040, 0x4512, 0x8aff, 0x00c0, 0x4517, 0x7200, 0xd284,
+	0x00c0, 0x4517, 0x7003, 0x0008, 0x127f, 0x2000, 0x007c, 0x7000,
+	0xa084, 0x0003, 0x7002, 0xc69c, 0xd084, 0x0040, 0x455a, 0x7108,
+	0x0005, 0x7008, 0xa106, 0x00c0, 0x451f, 0xa184, 0x0003, 0x0040,
+	0x458b, 0xa184, 0x01e0, 0x00c0, 0x458b, 0xd1f4, 0x00c0, 0x451f,
+	0xa184, 0x3000, 0xa086, 0x1000, 0x0040, 0x451f, 0x2011, 0x0180,
+	0x710c, 0x8211, 0x0040, 0x4544, 0x7008, 0xd0f4, 0x00c0, 0x451f,
+	0x700c, 0xa106, 0x0040, 0x4539, 0x7007, 0x0012, 0x7108, 0x0005,
+	0x7008, 0xa106, 0x00c0, 0x4546, 0xa184, 0x0003, 0x0040, 0x458b,
+	0xd194, 0x0040, 0x4546, 0xd1f4, 0x0040, 0x458b, 0x7007, 0x0002,
+	0x0078, 0x451f, 0x7108, 0xd1fc, 0x0040, 0x4565, 0x1078, 0x46e0,
+	0x8aff, 0x0040, 0x4501, 0x0078, 0x455a, 0x700c, 0xa08c, 0x03ff,
+	0x0040, 0x4590, 0x7004, 0xd084, 0x0040, 0x4582, 0x7014, 0xa005,
+	0x00c0, 0x457e, 0x7010, 0x7310, 0xa306, 0x00c0, 0x4572, 0x2300,
+	0xa005, 0x0040, 0x4582, 0xa102, 0x00c8, 0x455a, 0x7007, 0x0010,
+	0x0078, 0x458b, 0x8aff, 0x0040, 0x4590, 0x1078, 0x48e7, 0x00c0,
+	0x4585, 0x0040, 0x455a, 0x1078, 0x4629, 0x127f, 0x2000, 0x007c,
+	0x7204, 0x7108, 0xc19c, 0x8103, 0x00c8, 0x459f, 0x1078, 0x46e0,
+	0x0078, 0x4590, 0x7003, 0x0008, 0x127f, 0x2000, 0x007c, 0xa205,
+	0x00c0, 0x458b, 0x7003, 0x0008, 0x127f, 0x2000, 0x007c, 0x6428,
+	0x84ff, 0x0040, 0x45d3, 0x2c70, 0x7004, 0xa0bc, 0x000f, 0xa7b8,
+	0x45e3, 0x273c, 0x87fb, 0x00c0, 0x45c1, 0x0048, 0x45b9, 0x1078,
+	0x290c, 0x609c, 0xa075, 0x0040, 0x45d3, 0x0078, 0x45ac, 0x2039,
+	0x45d8, 0x2704, 0xae68, 0x6808, 0xa630, 0x680c, 0xa529, 0x8421,
+	0x0040, 0x45d3, 0x8738, 0x2704, 0xa005, 0x00c0, 0x45c2, 0x709c,
+	0xa075, 0x00c0, 0x45ac, 0x007c, 0x0000, 0x0005, 0x0009, 0x000d,
+	0x0011, 0x0015, 0x0019, 0x001d, 0x0000, 0x0003, 0x0009, 0x000f,
+	0x0015, 0x001b, 0x0000, 0x0000, 0x45d8, 0x45d5, 0x0000, 0x0000,
+	0x8000, 0x0000, 0x45d8, 0x0000, 0x45e0, 0x45dd, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x45e0, 0x0000, 0x45db, 0x45db, 0x0000, 0x0000,
+	0x8000, 0x0000, 0x45db, 0x0000, 0x45e1, 0x45e1, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x45e1, 0x2079, 0x4d00, 0x2071, 0x0010, 0x7007,
+	0x000a, 0x7007, 0x0002, 0x7003, 0x0001, 0x7810, 0xd0ec, 0x0040,
+	0x4617, 0x2009, 0x0001, 0x2071, 0x0020, 0x0078, 0x461b, 0x2009,
+	0x0002, 0x2071, 0x0050, 0x7007, 0x000a, 0x7007, 0x0002, 0x7003,
+	0x0000, 0x8109, 0x0040, 0x4628, 0x2071, 0x0020, 0x0078, 0x461b,
+	0x007c, 0x7004, 0x8004, 0x00c8, 0x46b2, 0x7108, 0x7008, 0xa106,
+	0x00c0, 0x462d, 0xa184, 0x01e0, 0x0040, 0x463a, 0x1078, 0x4723,
+	0x0078, 0x46da, 0x7007, 0x0012, 0x2019, 0x0000, 0x7108, 0x7008,
+	0xa106, 0x00c0, 0x463e, 0xa184, 0x01e0, 0x0040, 0x464b, 0x1078,
+	0x4723, 0x0078, 0x46da, 0x7810, 0xd0ec, 0x0040, 0x4665, 0x2001,
+	0x04fd, 0x2004, 0xa086, 0x0003, 0x00c0, 0x4669, 0xa184, 0x4000,
+	0x0040, 0x466d, 0xa382, 0x0003, 0x00c8, 0x466d, 0xa184, 0x0004,
+	0x0040, 0x463e, 0x8318, 0x0078, 0x463e, 0x7814, 0xd0ec, 0x00c0,
+	0x466d, 0xa184, 0x4000, 0x00c0, 0x463e, 0xa19c, 0x300c, 0xa386,
+	0x2004, 0x0040, 0x468a, 0xa386, 0x0008, 0x0040, 0x4695, 0x7004,
+	0xd084, 0x00c0, 0x4686, 0x7108, 0x7008, 0xa106, 0x00c0, 0x467b,
+	0xa184, 0x0003, 0x0040, 0x4686, 0x0078, 0x4723, 0xa386, 0x200c,
+	0x00c0, 0x463e, 0x7200, 0x8204, 0x0048, 0x4695, 0x730c, 0xa384,
+	0x03ff, 0x0040, 0x4695, 0x1078, 0x290c, 0x7108, 0x7008, 0xa106,
+	0x00c0, 0x4695, 0xa184, 0x01e0, 0x0040, 0x46a2, 0x1078, 0x4723,
+	0x0078, 0x46da, 0x7007, 0x0012, 0x7000, 0xd084, 0x00c0, 0x46b2,
+	0x7310, 0x7014, 0xa305, 0x0040, 0x46b2, 0x710c, 0xa184, 0x03ff,
+	0x00c0, 0x4629, 0x7108, 0x7008, 0xa106, 0x00c0, 0x46b2, 0xa184,
+	0x01e0, 0x0040, 0x46bf, 0x1078, 0x4723, 0x0078, 0x46da, 0x7007,
+	0x0012, 0x7007, 0x0008, 0x7004, 0xd09c, 0x00c0, 0x46c3, 0x7108,
+	0x7008, 0xa106, 0x00c0, 0x46c7, 0xa184, 0x01e0, 0x0040, 0x46d4,
+	0x1078, 0x4723, 0x0078, 0x46da, 0x7007, 0x0012, 0x7108, 0x8103,
+	0x0048, 0x46c7, 0x7003, 0x0008, 0x007c, 0x7108, 0x0078, 0x46e0,
+	0xa184, 0x01e0, 0x00c0, 0x4723, 0x7108, 0xa184, 0x01e0, 0x00c0,
+	0x4723, 0xa184, 0x0007, 0x0079, 0x46ed, 0x46f7, 0x4707, 0x46f5,
+	0x4707, 0x46f5, 0x4765, 0x46f5, 0x4763, 0x1078, 0x290c, 0x7004,
+	0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, 0x00c0, 0x4702, 0x2049,
+	0x0000, 0x007c, 0x1078, 0x48e7, 0x00c0, 0x4702, 0x007c, 0x7004,
+	0xa084, 0x0010, 0xc08d, 0x7006, 0x7004, 0xd084, 0x00c0, 0x471b,
+	0x7108, 0x7008, 0xa106, 0x00c0, 0x4710, 0xa184, 0x0003, 0x0040,
+	0x471b, 0x0078, 0x4723, 0x8aff, 0x0040, 0x4722, 0x1078, 0x48e7,
+	0x00c0, 0x471e, 0x007c, 0x7007, 0x0012, 0x7108, 0x00e0, 0x4726,
+	0x2091, 0x6000, 0x00e0, 0x472a, 0x2091, 0x6000, 0x7007, 0x0012,
+	0x7007, 0x0008, 0x7004, 0xd09c, 0x00c0, 0x4732, 0x7007, 0x0012,
+	0x7108, 0xd1fc, 0x00c0, 0x4736, 0x7003, 0x0000, 0x7000, 0xa005,
+	0x00c0, 0x474a, 0x7004, 0xa005, 0x00c0, 0x474a, 0x700c, 0xa005,
+	0x0040, 0x474c, 0x0078, 0x472e, 0x2049, 0x0000, 0xb284, 0x0100,
+	0x0040, 0x4756, 0x2001, 0x0000, 0x0078, 0x4758, 0x2001, 0x0001,
+	0x1078, 0x419b, 0x681b, 0x0002, 0x2051, 0x0000, 0x007c, 0x1078,
+	0x290c, 0x1078, 0x290c, 0x1078, 0x47ad, 0x7210, 0x7114, 0x700c,
+	0xa09c, 0x03ff, 0x2800, 0xa300, 0xa211, 0xa189, 0x0000, 0x1078,
+	0x47ad, 0x2704, 0x2c58, 0xac60, 0x6308, 0x2200, 0xa322, 0x630c,
+	0x2100, 0xa31b, 0x2400, 0xa305, 0x0040, 0x4788, 0x00c8, 0x4788,
+	0x8412, 0x8210, 0x830a, 0xa189, 0x0000, 0x2b60, 0x0078, 0x476f,
+	0x2b60, 0x8a07, 0x007e, 0x6004, 0xa084, 0x0008, 0x0040, 0x4794,
+	0xa7ba, 0x45dd, 0x0078, 0x4796, 0xa7ba, 0x45d5, 0x007f, 0xa73d,
+	0x2c00, 0x6886, 0x6f8a, 0x6c92, 0x6b8e, 0x7108, 0x7008, 0xa106,
+	0x00c0, 0x479d, 0xa184, 0x01e0, 0x0040, 0x47a8, 0x1078, 0x4723,
+	0x7007, 0x0012, 0x1078, 0x4629, 0x007c, 0x8a50, 0x8739, 0x2704,
+	0xa004, 0x00c0, 0x47c1, 0x6000, 0xa064, 0x00c0, 0x47b8, 0x2d60,
+	0x6004, 0xa084, 0x000f, 0xa080, 0x45f3, 0x203c, 0x87fb, 0x1040,
+	0x290c, 0x007c, 0x127e, 0x0d7e, 0x70d4, 0xa084, 0x4600, 0x8004,
+	0x2090, 0x0d7f, 0x6884, 0x2060, 0x6888, 0x6b8c, 0x6c90, 0x8057,
+	0xaad4, 0x00ff, 0xa084, 0x00ff, 0x007e, 0x6804, 0xa084, 0x0008,
+	0x007f, 0x0040, 0x47df, 0xa0b8, 0x45dd, 0x0078, 0x47e1, 0xa0b8,
+	0x45d5, 0xb284, 0x0100, 0x0040, 0x47e8, 0x7e20, 0x0078, 0x47e9,
+	0x7e24, 0xa6b5, 0x000c, 0x681c, 0xd0b4, 0x0040, 0x47f0, 0xc685,
+	0x2400, 0xa305, 0x0040, 0x481a, 0x2c58, 0x2704, 0x6104, 0xac60,
+	0x6000, 0xa400, 0x701a, 0x6004, 0xa301, 0x701e, 0xa184, 0x0008,
+	0x0040, 0x480a, 0x6010, 0xa081, 0x0000, 0x7022, 0x6014, 0xa081,
+	0x0000, 0x7026, 0x6208, 0x2400, 0xa202, 0x7012, 0x620c, 0x2300,
+	0xa203, 0x7016, 0x7602, 0x7007, 0x0001, 0x2b60, 0x1078, 0x4912,
+	0x0078, 0x481c, 0x1078, 0x48e7, 0x00c0, 0x481a, 0x127f, 0x2000,
+	0x007c, 0x127e, 0x0d7e, 0x70d4, 0xa084, 0x4600, 0x8004, 0x2090,
+	0x0d7f, 0x7007, 0x0004, 0x7004, 0xd094, 0x00c0, 0x482b, 0x7003,
+	0x0008, 0x127f, 0x2000, 0x007c, 0x127e, 0x0d7e, 0x70d4, 0xa084,
+	0x4600, 0x8004, 0x007e, 0x2090, 0x007f, 0x0d7f, 0x7e20, 0xb284,
+	0x0100, 0x00c0, 0x4844, 0x7e24, 0xa6b5, 0x000c, 0x681c, 0xd0ac,
+	0x00c0, 0x484f, 0xc685, 0x7003, 0x0000, 0x7007, 0x0004, 0x6828,
+	0x2050, 0x2d60, 0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x45e3, 0x273c,
+	0x87fb, 0x00c0, 0x4865, 0x0048, 0x485f, 0x1078, 0x290c, 0x689c,
+	0xa065, 0x0040, 0x4869, 0x0078, 0x4852, 0x1078, 0x48e7, 0x00c0,
+	0x4865, 0x127f, 0x2000, 0x007c, 0x127e, 0x007e, 0x017e, 0x0d7e,
+	0x70d4, 0xa084, 0x4600, 0x8004, 0x007e, 0x2090, 0x007f, 0x7e20,
+	0xb284, 0x0100, 0x00c0, 0x487d, 0x7e24, 0x0d7f, 0x037f, 0x047f,
+	0xa6b5, 0x000c, 0x681c, 0xd0b4, 0x0040, 0x488b, 0xc685, 0x7003,
+	0x0000, 0x7007, 0x0004, 0x2049, 0x486c, 0x6828, 0xa055, 0x0d7e,
+	0x0040, 0x48e3, 0x2d70, 0x2e60, 0x7004, 0xa0bc, 0x000f, 0xa7b8,
+	0x45e3, 0x273c, 0x87fb, 0x00c0, 0x48a8, 0x0048, 0x48a1, 0x1078,
+	0x290c, 0x709c, 0xa075, 0x2060, 0x0040, 0x48e3, 0x0078, 0x4894,
+	0x2704, 0xae68, 0x6808, 0xa422, 0x680c, 0xa31b, 0x0048, 0x48c1,
+	0x8a51, 0x00c0, 0x48b5, 0x1078, 0x290c, 0x8738, 0x2704, 0xa005,
+	0x00c0, 0x48a9, 0x709c, 0xa075, 0x2060, 0x0040, 0x48e3, 0x0078,
+	0x4894, 0x8422, 0x8420, 0x831a, 0xa399, 0x0000, 0x6908, 0x2400,
+	0xa122, 0x690c, 0x2300, 0xa11b, 0x00c8, 0x48d0, 0x1078, 0x290c,
+	0xb284, 0x0100, 0x0040, 0x48de, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x00c0, 0x48de, 0x2071, 0x0050, 0x0078, 0x48e0, 0x2071, 0x0020,
+	0x0d7f, 0x0078, 0x47f0, 0x0d7f, 0x127f, 0x2000, 0x007c, 0x7008,
+	0x007e, 0xa084, 0x01e0, 0x007f, 0x0040, 0x48f0, 0xa006, 0x007c,
+	0xa084, 0x0003, 0xa086, 0x0003, 0x00c0, 0x48f7, 0x007c, 0x2704,
+	0xac78, 0x7800, 0x701a, 0x7804, 0x701e, 0x7808, 0x7012, 0x780c,
+	0x7016, 0x6004, 0xa084, 0x0008, 0x0040, 0x490a, 0x7810, 0x7022,
+	0x7814, 0x7026, 0x7602, 0x7004, 0xa084, 0x0010, 0xc085, 0x7006,
+	0x2079, 0x4d00, 0x8a51, 0x0040, 0x4936, 0x8738, 0x2704, 0xa005,
+	0x00c0, 0x4928, 0x609c, 0xa005, 0x0040, 0x4937, 0x2060, 0x6004,
+	0xa084, 0x000f, 0xa080, 0x45e3, 0x203c, 0x87fb, 0x1040, 0x290c,
+	0x7008, 0x007e, 0xa084, 0x01e0, 0x007f, 0x0040, 0x4932, 0xa006,
+	0x0078, 0x4937, 0xa084, 0x0003, 0xa086, 0x0003, 0x007c, 0x2051,
+	0x0000, 0x007c, 0x127e, 0x007e, 0x0d7e, 0x70d4, 0xa084, 0x4600,
+	0x8004, 0x2090, 0x0d7f, 0x087f, 0x7108, 0xa184, 0x0003, 0x00c0,
+	0x494f, 0x6828, 0xa005, 0x0040, 0x495f, 0x0078, 0x4517, 0x7108,
+	0xd1fc, 0x0040, 0x4957, 0x1078, 0x46e0, 0x0078, 0x4944, 0x7007,
+	0x0010, 0x7108, 0xd1fc, 0x0040, 0x4959, 0x1078, 0x46e0, 0x7008,
+	0xa086, 0x0008, 0x00c0, 0x4944, 0x7000, 0xa005, 0x00c0, 0x4944,
+	0x7003, 0x0000, 0x2049, 0x0000, 0x127f, 0x2000, 0x007c, 0x127e,
+	0x147e, 0x137e, 0x157e, 0x0c7e, 0x0d7e, 0x70d4, 0xa084, 0x4600,
+	0x8004, 0x2090, 0x0d7f, 0x2049, 0x496f, 0xad80, 0x0011, 0x20a0,
+	0xb284, 0x0100, 0x0040, 0x4992, 0x2001, 0x4d04, 0x2004, 0xd0ec,
+	0x0040, 0x498e, 0x2099, 0x0031, 0x0078, 0x4994, 0x2099, 0x0032,
+	0x0078, 0x4994, 0x2099, 0x0031, 0x700c, 0xa084, 0x03ff, 0x682a,
+	0x7007, 0x0008, 0x7007, 0x0002, 0x7003, 0x0001, 0x0040, 0x49a3,
+	0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084, 0x03ff, 0x0040, 0x49af,
+	0x7007, 0x0004, 0x7004, 0xa084, 0x0004, 0x00c0, 0x49aa, 0x0c7f,
+	0x2049, 0x0000, 0x7003, 0x0000, 0x157f, 0x137f, 0x147f, 0x127f,
+	0x2000, 0x007c, 0x2091, 0x8000, 0x2091, 0x6000, 0x78ac, 0xa005,
+	0x00c0, 0x49d1, 0x7974, 0x70d0, 0xa106, 0x00c0, 0x49d1, 0x781c,
+	0xa005, 0x0040, 0x49d1, 0x781f, 0x0000, 0x0068, 0x49d1, 0x2091,
+	0x4080, 0x7830, 0x8001, 0x7832, 0x00c0, 0x4a59, 0x7834, 0x7832,
+	0x7810, 0xd0ec, 0x00c0, 0x4a52, 0x2061, 0x72c0, 0x2069, 0x4d80,
+	0xc7fd, 0x68d0, 0xa005, 0x0040, 0x49eb, 0x8001, 0x68d2, 0x00c0,
+	0x49eb, 0x1078, 0x4c22, 0x6800, 0xa084, 0x000f, 0x0040, 0x4a00,
+	0xa086, 0x0001, 0x0040, 0x4a00, 0x6844, 0xa00d, 0x0040, 0x4a00,
+	0x2104, 0xa005, 0x0040, 0x4a00, 0x8001, 0x200a, 0x0040, 0x4b95,
+	0x6814, 0xa005, 0x0040, 0x4a25, 0x8001, 0x6816, 0x00c0, 0x4a25,
+	0x68a7, 0x0001, 0x0f7e, 0xd7fc, 0x00c0, 0x4a1a, 0x7810, 0xd0ec,
+	0x0040, 0x4a16, 0x2079, 0x0100, 0x0078, 0x4a1c, 0x2079, 0x0200,
+	0x0078, 0x4a1c, 0x2079, 0x0100, 0x1078, 0x42fe, 0x0f7f, 0x6864,
+	0xa005, 0x0040, 0x4a25, 0x1078, 0x25ea, 0x6880, 0xa005, 0x0040,
+	0x4a32, 0x8001, 0x6882, 0x00c0, 0x4a32, 0x6867, 0x0000, 0x68d4,
+	0xc0dd, 0x68d6, 0x68d4, 0xd0fc, 0x0040, 0x4a4f, 0xc0fc, 0x68d6,
+	0x20a9, 0x0200, 0x6034, 0xa005, 0x0040, 0x4a4b, 0x8001, 0x6036,
+	0x68d4, 0xc0fd, 0x68d6, 0x00c0, 0x4a4b, 0x6010, 0xa005, 0x0040,
+	0x4a4b, 0x1078, 0x25ea, 0xace0, 0x0010, 0x00f0, 0x4a3a, 0xd7fc,
+	0x0040, 0x4a59, 0x2061, 0x52c0, 0x2069, 0x4d40, 0xc7fc, 0x0078,
+	0x49e1, 0x1078, 0x4a95, 0x7838, 0x8001, 0x783a, 0x00c0, 0x4a7b,
+	0x783c, 0x783a, 0x2061, 0x52c0, 0x2069, 0x4d40, 0xc7fc, 0x680c,
+	0xa005, 0x0040, 0x4a6d, 0x1078, 0x4aec, 0xd7fc, 0x00c0, 0x4a7b,
+	0x7810, 0xd0ec, 0x00c0, 0x4a7b, 0x2061, 0x72c0, 0x2069, 0x4d80,
+	0xc7fd, 0x0078, 0x4a67, 0x7814, 0xd0e4, 0x00c0, 0x4a7f, 0x7810,
+	0xd0cc, 0x0040, 0x4a92, 0xd0ac, 0x00c0, 0x4a8b, 0xd0a4, 0x0040,
+	0x4a92, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0068, 0x4a91, 0x1078,
+	0x2356, 0x007c, 0x2091, 0x8001, 0x007c, 0x7840, 0x8001, 0x7842,
+	0x00c0, 0x4aeb, 0x7844, 0x7842, 0x2091, 0x8000, 0x2061, 0x52c0,
+	0x2069, 0x4d40, 0xc7fc, 0x7810, 0x2079, 0x0200, 0xd0ec, 0x0040,
+	0x4aab, 0x2079, 0x0100, 0x68d8, 0xa005, 0x0040, 0x4ab7, 0x7de0,
+	0xa504, 0x00c0, 0x4ab7, 0x68da, 0x68d4, 0xc0bc, 0x68d6, 0x2079,
+	0x4d00, 0x6810, 0xa005, 0x00c0, 0x4abf, 0x2001, 0x0101, 0x8001,
+	0x6812, 0xd7fc, 0x0040, 0x4ac8, 0xa080, 0x93d0, 0x0078, 0x4aca,
+	0xa080, 0x92c0, 0x2040, 0x2004, 0xa065, 0x0040, 0x4adb, 0x6024,
+	0xa005, 0x0040, 0x4ad7, 0x8001, 0x6026, 0x0040, 0x4b37, 0x6000,
+	0x2c40, 0x0078, 0x4acc, 0xd7fc, 0x00c0, 0x4aeb, 0x7810, 0xd0ec,
+	0x00c0, 0x4aeb, 0x2061, 0x72c0, 0x2069, 0x4d80, 0xc7fd, 0x2079,
+	0x0200, 0x0078, 0x4aab, 0x007c, 0x2009, 0x0000, 0x20a9, 0x0200,
+	0x6008, 0xd09c, 0x0040, 0x4b23, 0x6024, 0xa005, 0x0040, 0x4afc,
+	0x8001, 0x6026, 0x0078, 0x4b21, 0x6008, 0xc09c, 0xd084, 0x00c0,
+	0x4b04, 0xd0ac, 0x0040, 0x4b1b, 0x600a, 0x6004, 0xa06d, 0x0040,
+	0x4b23, 0x0c7e, 0x017e, 0x6010, 0x8001, 0x6012, 0x1078, 0x3d56,
+	0x2d00, 0x2c68, 0x2060, 0x1078, 0x1e42, 0x1078, 0x2004, 0x017f,
+	0x0c7f, 0x0078, 0x4b23, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0078,
+	0x4b23, 0xa18d, 0x0100, 0xace0, 0x0010, 0x00f0, 0x4af0, 0xa184,
+	0x0001, 0x0040, 0x4b32, 0xa18c, 0xfffe, 0x690e, 0x1078, 0x25ea,
+	0x0078, 0x4b33, 0x690e, 0x007c, 0x00c0, 0x4b33, 0x786c, 0x6800,
+	0xa005, 0x0040, 0x4b3f, 0x684c, 0xac06, 0x0040, 0x4b95, 0x6864,
+	0xa005, 0x0040, 0x4b47, 0x6027, 0x0001, 0x0078, 0x4b94, 0x2c00,
+	0x687e, 0x6714, 0x6f76, 0x6017, 0x0000, 0x602b, 0x0000, 0x601b,
 	0x0006, 0x60b4, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff,
-	0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x6714, 0x6f76, 0x1078,
-	0x1e02, 0x6818, 0xa005, 0x0040, 0x48d7, 0x8001, 0x681a, 0x6808,
-	0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0,
-	0x48e3, 0x1078, 0x28ec, 0x6812, 0x00c0, 0x48e9, 0x7910, 0xc1a5,
-	0x7912, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x1078, 0x202a,
-	0xd7fc, 0x00c0, 0x48f7, 0x2069, 0x4a40, 0x0078, 0x48f9, 0x2069,
-	0x4a80, 0x6910, 0xa184, 0x0100, 0x2001, 0x0006, 0x00c0, 0x4903,
-	0x697a, 0x2001, 0x0004, 0x2708, 0x1078, 0x25d1, 0x2091, 0x8001,
-	0x007c, 0x0d7e, 0x694c, 0x2160, 0xd7fc, 0x00c0, 0x491b, 0x7810,
-	0xd0ec, 0x0040, 0x4917, 0x2069, 0x0100, 0x0078, 0x491d, 0x2069,
-	0x0200, 0x0078, 0x491d, 0x2069, 0x0100, 0x1078, 0x2881, 0x601b,
-	0x0006, 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff,
-	0xa085, 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6830,
-	0xd0b4, 0x0040, 0x494b, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848,
-	0xd094, 0x0040, 0x493d, 0x00f0, 0x4937, 0x684b, 0x0009, 0x20a9,
-	0x0014, 0x6848, 0xd084, 0x0040, 0x4947, 0x00f0, 0x4941, 0x20a9,
-	0x00fa, 0x00f0, 0x4949, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b,
-	0x0047, 0x0d7f, 0x6867, 0x0007, 0x2091, 0x8001, 0x007c, 0x2079,
-	0x4a00, 0x1078, 0x498b, 0x1078, 0x4971, 0x1078, 0x497e, 0x2009,
-	0x0002, 0x2069, 0x4a80, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817,
-	0x0000, 0x8109, 0x0040, 0x4970, 0x2069, 0x4a40, 0x0078, 0x4963,
-	0x007c, 0x7810, 0xd0ec, 0x0040, 0x4979, 0x2019, 0x00cc, 0x0078,
-	0x497b, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c, 0x7814, 0xd0e4,
-	0x00c0, 0x4986, 0x2019, 0x0040, 0x0078, 0x4988, 0x2019, 0x0026,
-	0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x4993, 0x2019,
-	0x3f94, 0x0078, 0x4995, 0x2019, 0x2624, 0x7b32, 0x7b36, 0x007c,
-	0x6950, 0xa185, 0x0000, 0x0040, 0x49ad, 0x0c7e, 0x6ac0, 0x2264,
-	0x602b, 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5, 0x600a, 0x8210,
-	0x8109, 0x00c0, 0x499f, 0x6952, 0x0c7f, 0x007c, 0x70ec, 0xd0dc,
-	0x00c0, 0x49b7, 0xd0d4, 0x0040, 0x49d6, 0x0078, 0x49d9, 0x7810,
-	0xd0ec, 0x0040, 0x49c2, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x49dd,
-	0x0078, 0x49d9, 0xae8e, 0x0100, 0x0040, 0x49ce, 0x7814, 0xc0f5,
-	0x7816, 0xd0d4, 0x00c0, 0x49dd, 0x0078, 0x49d9, 0x7814, 0xc0fd,
-	0x7816, 0xd0d4, 0x00c0, 0x49dd, 0x0078, 0x49d9, 0xd0e4, 0x0040,
-	0x49df, 0x7804, 0xd08c, 0x0040, 0x49df, 0x681f, 0x000c, 0x70a0,
-	0x70a2, 0x007c, 0x699a
+	0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x1078, 0x1dcb, 0x6818,
+	0xa005, 0x0040, 0x4b65, 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a,
+	0x6810, 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0, 0x4b71, 0x1078,
+	0x290c, 0x6812, 0x00c0, 0x4b77, 0x7910, 0xc1a5, 0x7912, 0x602f,
+	0x0000, 0x6033, 0x0000, 0x2c68, 0x1078, 0x2013, 0xd7fc, 0x00c0,
+	0x4b85, 0x2069, 0x4d40, 0x0078, 0x4b87, 0x2069, 0x4d80, 0x6910,
+	0xa184, 0x0100, 0x2001, 0x0006, 0x00c0, 0x4b91, 0x697a, 0x2001,
+	0x0004, 0x2708, 0x1078, 0x25dd, 0x007c, 0x0d7e, 0x694c, 0x2160,
+	0xd7fc, 0x00c0, 0x4ba7, 0x7810, 0xd0ec, 0x0040, 0x4ba3, 0x2069,
+	0x0100, 0x0078, 0x4ba9, 0x2069, 0x0200, 0x0078, 0x4ba9, 0x2069,
+	0x0100, 0x1078, 0x288d, 0x601b, 0x0006, 0x6858, 0xa084, 0x3f00,
+	0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f,
+	0x0000, 0x6033, 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830,
+	0xd0b4, 0x0040, 0x4bdb, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848,
+	0xd094, 0x0040, 0x4bcd, 0x00f0, 0x4bc7, 0x684b, 0x0009, 0x20a9,
+	0x0014, 0x6848, 0xd084, 0x0040, 0x4bd7, 0x00f0, 0x4bd1, 0x20a9,
+	0x00fa, 0x00f0, 0x4bd9, 0x681b, 0x0047, 0x0d7f, 0x6867, 0x0007,
+	0x007c, 0x2079, 0x4d00, 0x1078, 0x4c15, 0x1078, 0x4bfb, 0x1078,
+	0x4c08, 0x2009, 0x0002, 0x2069, 0x4d80, 0x680f, 0x0000, 0x6813,
+	0x0000, 0x6817, 0x0000, 0x8109, 0x0040, 0x4bfa, 0x2069, 0x4d40,
+	0x0078, 0x4bed, 0x007c, 0x7810, 0xd0ec, 0x0040, 0x4c03, 0x2019,
+	0x00cc, 0x0078, 0x4c05, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c,
+	0x7814, 0xd0e4, 0x00c0, 0x4c10, 0x2019, 0x0040, 0x0078, 0x4c12,
+	0x2019, 0x0026, 0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0,
+	0x4c1d, 0x2019, 0x3f94, 0x0078, 0x4c1f, 0x2019, 0x2624, 0x7b32,
+	0x7b36, 0x007c, 0x6950, 0xa185, 0x0000, 0x0040, 0x4c37, 0x0c7e,
+	0x6ac0, 0x2264, 0x602b, 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5,
+	0x600a, 0x8210, 0x8109, 0x00c0, 0x4c29, 0x6952, 0x0c7f, 0x007c,
+	0x70ec, 0xd0dc, 0x00c0, 0x4c41, 0xd0d4, 0x0040, 0x4c64, 0x0078,
+	0x4c67, 0x2008, 0x7810, 0xd0ec, 0x0040, 0x4c50, 0xd1c4, 0x00c0,
+	0x4c6f, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x4c6b, 0x0078, 0x4c67,
+	0xae8e, 0x0100, 0x0040, 0x4c5c, 0x7814, 0xc0f5, 0x7816, 0xd0d4,
+	0x00c0, 0x4c6b, 0x0078, 0x4c67, 0x7814, 0xc0fd, 0x7816, 0xd0d4,
+	0x00c0, 0x4c6b, 0x0078, 0x4c67, 0xd0e4, 0x0040, 0x4c6d, 0x7804,
+	0xd08c, 0x0040, 0x4c6d, 0x681f, 0x000c, 0x70a0, 0x70a2, 0x007c,
+	0x3782
 };
-unsigned short   fw1280ei_length01 = 0x39e3;
+#ifdef UNIQUE_FW_NAME
+unsigned short   fw1280ei_length01 = 0x3c71;
+#else
+unsigned short   risc_code_length01 = 0x3c71;
+#endif
 
diff -urN linux-2.4.16/drivers/scsi/ql2100_fw.h lia64-2.4/drivers/scsi/ql2100_fw.h
--- linux-2.4.16/drivers/scsi/ql2100_fw.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/ql2100_fw.h	Mon Jul 23 14:11:58 2001
@@ -0,0 +1,4740 @@
+/************************************************************************
+ *									*
+ * 	 --- ISP2100 Fabric Initiator/Target Firmware ---               *
+ *                   with expanded LUN addressing                       *
+ *                   and FcTape (FCP-2) support                         *
+ *									*
+ *									*
+ ************************************************************************
+  Copyright (C) 2000 and 2001 Qlogic Corporation 
+  (www.qlogic.com)
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+************************************************************************/
+/*
+ *	Firmware Version 1.19.16 (10:36 Nov 02, 2000)
+ */
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2100tp_version = 1*1024+19;
+#else
+unsigned short risc_code_version = 1*1024+19;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned char fw2100tp_version_str[] = {1,19,16};
+#else
+unsigned char firmware_version[] = {1,19,16};
+#endif
+
+#ifdef UNIQUE_FW_NAME
+#define fw2100tp_VERSION_STRING "1.19.16"
+#else
+#define FW_VERSION_STRING "1.19.16"
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2100tp_addr01 = 0x1000 ;
+#else
+unsigned short risc_code_addr01 = 0x1000 ;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2100tp_code01[] = { 
+#else
+unsigned short risc_code01[] = { 
+#endif
+	0x0078, 0x102d, 0x0000, 0x9260, 0x0000, 0x0001, 0x0013, 0x0010,
+	0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2031, 0x3939,
+	0x3920, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
+	0x5449, 0x4f4e, 0x2049, 0x5350, 0x3231, 0x3030, 0x2046, 0x6972,
+	0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
+	0x312e, 0x3139, 0x2020, 0x2020, 0x2400, 0x2091, 0x2000, 0x20c1,
+	0x0021, 0x2039, 0xffff, 0x2019, 0xaaaa, 0x2760, 0x2069, 0x7fff,
+	0x20c1, 0x0020, 0x2c2c, 0x2d34, 0x2762, 0x236a, 0x2c24, 0x2d04,
+	0x266a, 0x2562, 0xa406, 0x00c0, 0x1052, 0x20c1, 0x0021, 0x2c2c,
+	0x2362, 0x2c04, 0x2562, 0xa306, 0x0040, 0x1052, 0x20c1, 0x0020,
+	0x2039, 0x8fff, 0x20a1, 0xaa00, 0x2708, 0x810d, 0x810d, 0x810d,
+	0x810d, 0xa18c, 0x000f, 0x2001, 0x000a, 0xa112, 0xa00e, 0x21a8,
+	0x41a4, 0x3400, 0x8211, 0x00c0, 0x105f, 0x2708, 0x3400, 0xa102,
+	0x0040, 0x106f, 0x0048, 0x106f, 0x20a8, 0xa00e, 0x41a4, 0x20a1,
+	0xa260, 0x2009, 0x0000, 0x20a9, 0x07a0, 0x41a4, 0x3400, 0x20c9,
+	0xa7ff, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x255d,
+	0x2051, 0xa300, 0x2a70, 0x775e, 0xa786, 0x8fff, 0x0040, 0x1092,
+	0x705b, 0xca00, 0x7057, 0xc9f1, 0x7063, 0x0200, 0x7067, 0x0200,
+	0x0078, 0x109a, 0x7057, 0xba01, 0x7063, 0x0100, 0x7067, 0x0100,
+	0x705b, 0xba00, 0x1078, 0x12df, 0x1078, 0x13c0, 0x1078, 0x1569,
+	0x1078, 0x1ca4, 0x1078, 0x4229, 0x1078, 0x74cf, 0x1078, 0x134b,
+	0x1078, 0x2a3f, 0x1078, 0x4da2, 0x1078, 0x48b2, 0x1078, 0x57df,
+	0x1078, 0x21f7, 0x1078, 0x5abf, 0x1078, 0x5369, 0x1078, 0x210d,
+	0x1078, 0x21d4, 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x10cf,
+	0x7820, 0xa086, 0x0002, 0x00c0, 0x10cf, 0x7823, 0x4000, 0x0068,
+	0x10c7, 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70,
+	0x7003, 0x0000, 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000,
+	0xa08e, 0x0003, 0x00c0, 0x10ef, 0x1078, 0x35bc, 0x1078, 0x2a67,
+	0x1078, 0x4df2, 0x1078, 0x4a75, 0x2009, 0x0100, 0x2104, 0xa082,
+	0x0002, 0x0048, 0x10f3, 0x1078, 0x57fb, 0x0078, 0x10d6, 0x1079,
+	0x10f7, 0x0078, 0x10dc, 0x1078, 0x6fa9, 0x0078, 0x10eb, 0x1101,
+	0x1102, 0x11be, 0x10ff, 0x1246, 0x12dc, 0x12dd, 0x12de, 0x1078,
+	0x1328, 0x007c, 0x127e, 0x0f7e, 0x2091, 0x8000, 0x7000, 0xa086,
+	0x0001, 0x00c0, 0x1198, 0x1078, 0x3a43, 0x2079, 0x0100, 0x7844,
+	0xa005, 0x00c0, 0x1198, 0x2011, 0x4129, 0x1078, 0x58d4, 0x1078,
+	0x1ab1, 0x780f, 0x00ff, 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011,
+	0x8010, 0x73c0, 0x1078, 0x3579, 0x2001, 0xffff, 0x1078, 0x5975,
+	0x7238, 0xc284, 0x723a, 0x2001, 0xa30c, 0x2014, 0xc2ac, 0x2202,
+	0x1078, 0x6db5, 0x2011, 0x0004, 0x1078, 0x8a59, 0x1078, 0x47ce,
+	0x1078, 0x4211, 0x0040, 0x1144, 0x7083, 0x0001, 0x70bb, 0x0000,
+	0x1078, 0x3bf5, 0x0078, 0x1198, 0x1078, 0x4897, 0x0040, 0x114d,
+	0x7a0c, 0xc2b4, 0x7a0e, 0x0078, 0x1159, 0x1078, 0x8ddf, 0x70c8,
+	0xd09c, 0x00c0, 0x1159, 0x7094, 0xa005, 0x0040, 0x1159, 0x1078,
+	0x41f5, 0x70d3, 0x0000, 0x70cf, 0x0000, 0x72c8, 0x2079, 0xa351,
+	0x7804, 0xd0ac, 0x0040, 0x1165, 0xc295, 0x72ca, 0xa296, 0x0004,
+	0x0040, 0x1186, 0x2011, 0x0001, 0x1078, 0x8a59, 0x708f, 0x0000,
+	0x7093, 0xffff, 0x7003, 0x0002, 0x0f7f, 0x1078, 0x260d, 0x2011,
+	0x0005, 0x1078, 0x6ef2, 0x1078, 0x6109, 0x0c7e, 0x2061, 0x0100,
+	0x60e3, 0x0008, 0x0c7f, 0x127f, 0x0078, 0x119a, 0x708f, 0x0000,
+	0x7093, 0xffff, 0x7003, 0x0002, 0x2011, 0x0005, 0x1078, 0x6ef2,
+	0x1078, 0x6109, 0x0c7e, 0x2061, 0x0100, 0x60e3, 0x0008, 0x0c7f,
+	0x0f7f, 0x127f, 0x007c, 0x0c7e, 0x20a9, 0x0082, 0x2009, 0x007e,
+	0x017e, 0x027e, 0x037e, 0x2110, 0x027e, 0x2019, 0x0029, 0x1078,
+	0x71e0, 0x027f, 0x1078, 0xa190, 0x037f, 0x027f, 0x017f, 0x1078,
+	0x2921, 0x8108, 0x00f0, 0x11a0, 0x0c7f, 0x706b, 0x0000, 0x706c,
+	0xa084, 0x00ff, 0x706e, 0x7097, 0x0000, 0x007c, 0x127e, 0x2091,
+	0x8000, 0x7000, 0xa086, 0x0002, 0x00c0, 0x1244, 0x7090, 0xa086,
+	0xffff, 0x0040, 0x11d1, 0x1078, 0x260d, 0x1078, 0x6109, 0x0078,
+	0x1244, 0x70c8, 0xd09c, 0x0040, 0x11fd, 0xd084, 0x0040, 0x11fd,
+	0x0f7e, 0x2079, 0x0100, 0x790c, 0xc1b5, 0x790e, 0x0f7f, 0xd08c,
+	0x0040, 0x11fd, 0x70cc, 0xa086, 0xffff, 0x0040, 0x11f9, 0x1078,
+	0x278a, 0x1078, 0x6109, 0x70c8, 0xd094, 0x00c0, 0x1244, 0x2011,
+	0x0001, 0x2019, 0x0000, 0x1078, 0x27c2, 0x1078, 0x6109, 0x0078,
+	0x1244, 0x70d0, 0xa005, 0x00c0, 0x1244, 0x708c, 0xa005, 0x00c0,
+	0x1244, 0x1078, 0x4897, 0x00c0, 0x1244, 0x2001, 0xa352, 0x2004,
+	0xd0ac, 0x0040, 0x1227, 0x157e, 0x0c7e, 0x20a9, 0x007f, 0x2009,
+	0x0000, 0x017e, 0x1078, 0x4501, 0x00c0, 0x121a, 0x6000, 0xd0ec,
+	0x00c0, 0x1222, 0x017f, 0x8108, 0x00f0, 0x1211, 0x0c7f, 0x157f,
+	0x0078, 0x1227, 0x017f, 0x0c7f, 0x157f, 0x0078, 0x1244, 0x7003,
+	0x0003, 0x7093, 0xffff, 0x2001, 0x0000, 0x1078, 0x2480, 0x1078,
+	0x35f7, 0x2001, 0xa5ac, 0x2004, 0xa086, 0x0005, 0x00c0, 0x123c,
+	0x2011, 0x0000, 0x1078, 0x6ef2, 0x2011, 0x0000, 0x1078, 0x6efc,
+	0x1078, 0x6109, 0x1078, 0x61d3, 0x127f, 0x007c, 0x017e, 0x0f7e,
+	0x127e, 0x2091, 0x8000, 0x2079, 0x0100, 0x2009, 0x00f7, 0x1078,
+	0x41de, 0x7940, 0xa18c, 0x0010, 0x7942, 0x7924, 0xd1b4, 0x0040,
+	0x125b, 0x7827, 0x0040, 0xd19c, 0x0040, 0x1260, 0x7827, 0x0008,
+	0x007e, 0x037e, 0x157e, 0xa006, 0x1078, 0x5975, 0x7900, 0xa18a,
+	0x0003, 0x0050, 0x1289, 0x7954, 0xd1ac, 0x00c0, 0x1289, 0x2009,
+	0x00f8, 0x1078, 0x41de, 0x7843, 0x0090, 0x7843, 0x0010, 0x20a9,
+	0x09c4, 0x7820, 0xd09c, 0x00c0, 0x1281, 0x7824, 0xd0ac, 0x00c0,
+	0x12ca, 0x00f0, 0x1279, 0x2001, 0x0001, 0x1078, 0x2480, 0x0078,
+	0x12d5, 0x7853, 0x0000, 0x782f, 0x0020, 0x20a9, 0x0050, 0x00e0,
+	0x128f, 0x2091, 0x6000, 0x00f0, 0x128f, 0x7853, 0x0400, 0x782f,
+	0x0000, 0x2009, 0x00f8, 0x1078, 0x41de, 0x20a9, 0x000e, 0x0005,
+	0x00f0, 0x129f, 0x7853, 0x1400, 0x7843, 0x0090, 0x7843, 0x0010,
+	0x2019, 0x61a8, 0x7854, 0x0005, 0x0005, 0xd08c, 0x0040, 0x12b4,
+	0x7824, 0xd0ac, 0x00c0, 0x12ca, 0x8319, 0x00c0, 0x12aa, 0x2009,
+	0xa331, 0x2104, 0x8000, 0x200a, 0xa084, 0xfff0, 0x0040, 0x12c4,
+	0x200b, 0x0000, 0x1078, 0x251e, 0x2001, 0x0001, 0x1078, 0x2480,
+	0x0078, 0x12d3, 0x2001, 0xa331, 0x2003, 0x0000, 0x7828, 0xc09d,
+	0x782a, 0x7827, 0x0048, 0x7853, 0x0400, 0x157f, 0x037f, 0x007f,
+	0x127f, 0x0f7f, 0x017f, 0x007c, 0x007c, 0x007c, 0x007c, 0x2a70,
+	0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, 0x12eb, 0x704f,
+	0xffff, 0x0078, 0x12ed, 0x704f, 0x0000, 0x7053, 0xffff, 0x706b,
+	0x0000, 0x706f, 0x0000, 0x1078, 0x8ddf, 0x2061, 0xa58c, 0x6003,
+	0x0909, 0x6007, 0x0000, 0x600b, 0x8800, 0x600f, 0x0200, 0x6013,
+	0x00ff, 0x6017, 0x0003, 0x601b, 0x0000, 0x601f, 0x07d0, 0x2061,
+	0xa594, 0x6003, 0x8000, 0x6007, 0x0000, 0x600b, 0x0000, 0x600f,
+	0x0200, 0x6013, 0x00ff, 0x6017, 0x0000, 0x601b, 0x0001, 0x601f,
+	0x0000, 0x2061, 0xa5a3, 0x6003, 0x514c, 0x6007, 0x4f47, 0x600b,
+	0x4943, 0x600f, 0x2020, 0x2001, 0xa325, 0x2003, 0x0000, 0x007c,
+	0x2091, 0x8000, 0x0068, 0x132a, 0x007e, 0x017e, 0x2079, 0x0000,
+	0x7818, 0xd084, 0x00c0, 0x1330, 0x017f, 0x792e, 0x007f, 0x782a,
+	0x007f, 0x7826, 0x3900, 0x783a, 0x7823, 0x8002, 0x781b, 0x0001,
+	0x2091, 0x5000, 0x2091, 0x4080, 0x2079, 0xa300, 0x7803, 0x0005,
+	0x0078, 0x1348, 0x007c, 0x2071, 0xa300, 0x7158, 0x712e, 0x2021,
+	0x0001, 0xa190, 0x002d, 0xa298, 0x002d, 0x0048, 0x1361, 0x705c,
+	0xa302, 0x00c8, 0x1361, 0x220a, 0x2208, 0x2310, 0x8420, 0x0078,
+	0x1353, 0x200b, 0x0000, 0x74a6, 0x74aa, 0x007c, 0x0e7e, 0x127e,
+	0x2091, 0x8000, 0x2071, 0xa300, 0x70a8, 0xa0ea, 0x0010, 0x00c8,
+	0x1374, 0xa06e, 0x0078, 0x137e, 0x8001, 0x70aa, 0x702c, 0x2068,
+	0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, 0x127f, 0x0e7f,
+	0x007c, 0x0e7e, 0x2071, 0xa300, 0x127e, 0x2091, 0x8000, 0x70a8,
+	0x8001, 0x00c8, 0x138e, 0xa06e, 0x0078, 0x1397, 0x70aa, 0x702c,
+	0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, 0x127f,
+	0x0e7f, 0x007c, 0x0e7e, 0x127e, 0x2091, 0x8000, 0x2071, 0xa300,
+	0x702c, 0x206a, 0x2d00, 0x702e, 0x70a8, 0x8000, 0x70aa, 0x127f,
+	0x0e7f, 0x007c, 0x8dff, 0x0040, 0x13b6, 0x6804, 0x6807, 0x0000,
+	0x007e, 0x1078, 0x139a, 0x0d7f, 0x0078, 0x13aa, 0x007c, 0x0e7e,
+	0x2071, 0xa300, 0x70a8, 0xa08a, 0x0010, 0xa00d, 0x0e7f, 0x007c,
+	0x0e7e, 0x2071, 0xa5d0, 0x7007, 0x0000, 0x701b, 0x0000, 0x701f,
+	0x0000, 0x2071, 0x0000, 0x7010, 0xa085, 0x8004, 0x7012, 0x0e7f,
+	0x007c, 0x0e7e, 0x2270, 0x700b, 0x0000, 0x2071, 0xa5d0, 0x7018,
+	0xa088, 0xa5d9, 0x220a, 0x8000, 0xa084, 0x0007, 0x701a, 0x7004,
+	0xa005, 0x00c0, 0x13e9, 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13fa,
+	0x0f7f, 0x0e7f, 0x007c, 0x0e7e, 0x2071, 0xa5d0, 0x7004, 0xa005,
+	0x00c0, 0x13f8, 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13fa, 0x0f7f,
+	0x0e7f, 0x007c, 0x7000, 0x0079, 0x13fd, 0x1401, 0x146b, 0x1488,
+	0x1488, 0x7018, 0x711c, 0xa106, 0x00c0, 0x1409, 0x7007, 0x0000,
+	0x007c, 0x0d7e, 0xa180, 0xa5d9, 0x2004, 0x700a, 0x2068, 0x8108,
+	0xa18c, 0x0007, 0x711e, 0x7803, 0x0026, 0x6824, 0x7832, 0x6828,
+	0x7836, 0x682c, 0x783a, 0x6830, 0x783e, 0x6810, 0x700e, 0x680c,
+	0x7016, 0x6804, 0x0d7f, 0xd084, 0x0040, 0x142b, 0x7007, 0x0001,
+	0x1078, 0x1430, 0x007c, 0x7007, 0x0002, 0x1078, 0x1446, 0x007c,
+	0x017e, 0x027e, 0x710c, 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8,
+	0x143b, 0x2110, 0xa006, 0x700e, 0x7212, 0x8203, 0x7822, 0x7803,
+	0x0020, 0x7803, 0x0041, 0x027f, 0x017f, 0x007c, 0x017e, 0x027e,
+	0x137e, 0x147e, 0x157e, 0x7014, 0x2098, 0x20a1, 0x0014, 0x7803,
+	0x0026, 0x710c, 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8, 0x145a,
+	0x2110, 0xa006, 0x700e, 0x22a8, 0x53a6, 0x8203, 0x7822, 0x7803,
+	0x0020, 0x3300, 0x7016, 0x7803, 0x0001, 0x157f, 0x147f, 0x137f,
+	0x027f, 0x017f, 0x007c, 0x137e, 0x147e, 0x157e, 0x2099, 0xa3f9,
+	0x20a1, 0x0018, 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e,
+	0x2091, 0x8000, 0x7803, 0x0041, 0x7007, 0x0003, 0x7000, 0xc084,
+	0x7002, 0x700b, 0xa3f4, 0x127f, 0x157f, 0x147f, 0x137f, 0x007c,
+	0x137e, 0x147e, 0x157e, 0x2001, 0xa428, 0x209c, 0x20a1, 0x0014,
+	0x7803, 0x0026, 0x2001, 0xa429, 0x20ac, 0x53a6, 0x2099, 0xa42a,
+	0x20a1, 0x0018, 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e,
+	0x2091, 0x8000, 0x7803, 0x0001, 0x7007, 0x0004, 0x7000, 0xc08c,
+	0x7002, 0x700b, 0xa425, 0x127f, 0x157f, 0x147f, 0x137f, 0x007c,
+	0x017e, 0x0e7e, 0x2071, 0xa5d0, 0x0f7e, 0x2079, 0x0010, 0x7904,
+	0x7803, 0x0002, 0xd1fc, 0x0040, 0x14c2, 0xa18c, 0x0700, 0x7004,
+	0x1079, 0x14c6, 0x0f7f, 0x0e7f, 0x017f, 0x007c, 0x13fa, 0x14ce,
+	0x14fb, 0x1523, 0x1556, 0x14cc, 0x0078, 0x14cc, 0xa18c, 0x0700,
+	0x00c0, 0x14f4, 0x137e, 0x147e, 0x157e, 0x7014, 0x20a0, 0x2099,
+	0x0014, 0x7803, 0x0040, 0x7010, 0x20a8, 0x53a5, 0x3400, 0x7016,
+	0x157f, 0x147f, 0x137f, 0x700c, 0xa005, 0x0040, 0x1510, 0x1078,
+	0x1430, 0x007c, 0x7008, 0xa080, 0x0002, 0x2003, 0x0100, 0x7007,
+	0x0000, 0x1078, 0x13fa, 0x007c, 0x7008, 0xa080, 0x0002, 0x2003,
+	0x0200, 0x0078, 0x14ef, 0xa18c, 0x0700, 0x00c0, 0x1506, 0x700c,
+	0xa005, 0x0040, 0x1510, 0x1078, 0x1446, 0x007c, 0x7008, 0xa080,
+	0x0002, 0x2003, 0x0200, 0x7007, 0x0000, 0x1078, 0x13fa, 0x007c,
+	0x0d7e, 0x7008, 0x2068, 0x7830, 0x6826, 0x7834, 0x682a, 0x7838,
+	0x682e, 0x783c, 0x6832, 0x680b, 0x0100, 0x0d7f, 0x7007, 0x0000,
+	0x1078, 0x13fa, 0x007c, 0xa18c, 0x0700, 0x00c0, 0x1550, 0x137e,
+	0x147e, 0x157e, 0x2001, 0xa3f7, 0x2004, 0xa080, 0x000d, 0x20a0,
+	0x2099, 0x0014, 0x7803, 0x0040, 0x20a9, 0x0020, 0x53a5, 0x2001,
+	0xa3f9, 0x2004, 0xd0bc, 0x0040, 0x1546, 0x2001, 0xa402, 0x2004,
+	0xa080, 0x000d, 0x20a0, 0x20a9, 0x0020, 0x53a5, 0x157f, 0x147f,
+	0x137f, 0x7007, 0x0000, 0x1078, 0x4e9b, 0x1078, 0x13fa, 0x007c,
+	0x2011, 0x8003, 0x1078, 0x3579, 0x0078, 0x1554, 0xa18c, 0x0700,
+	0x00c0, 0x1563, 0x2001, 0xa427, 0x2003, 0x0100, 0x7007, 0x0000,
+	0x1078, 0x13fa, 0x007c, 0x2011, 0x8004, 0x1078, 0x3579, 0x0078,
+	0x1567, 0x127e, 0x2091, 0x2100, 0x2079, 0x0030, 0x2071, 0xa5e1,
+	0x7803, 0x0004, 0x7003, 0x0000, 0x700f, 0xa5e7, 0x7013, 0xa5e7,
+	0x780f, 0x0076, 0x7803, 0x0004, 0x127f, 0x007c, 0x6934, 0xa184,
+	0x0007, 0x0079, 0x1583, 0x158b, 0x15d1, 0x158b, 0x158b, 0x158b,
+	0x15b6, 0x159a, 0x158f, 0xa085, 0x0001, 0x0078, 0x15eb, 0x684c,
+	0xd0bc, 0x0040, 0x158b, 0x6860, 0x682e, 0x685c, 0x682a, 0x6858,
+	0x0078, 0x15d9, 0xa18c, 0x00ff, 0xa186, 0x001e, 0x00c0, 0x158b,
+	0x684c, 0xd0bc, 0x0040, 0x158b, 0x6860, 0x682e, 0x685c, 0x682a,
+	0x6804, 0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080,
+	0x2015, 0x2004, 0x6832, 0x6858, 0x0078, 0x15e1, 0xa18c, 0x00ff,
+	0xa186, 0x0015, 0x00c0, 0x158b, 0x684c, 0xd0ac, 0x0040, 0x158b,
+	0x6804, 0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080,
+	0x2015, 0x2004, 0x6832, 0xa006, 0x682e, 0x682a, 0x6858, 0x0078,
+	0x15e1, 0x684c, 0xd0ac, 0x0040, 0x158b, 0xa006, 0x682e, 0x682a,
+	0x6858, 0xa18c, 0x000f, 0xa188, 0x2015, 0x210c, 0x6932, 0x2d08,
+	0x691a, 0x6826, 0x684c, 0xc0dd, 0x684e, 0xa006, 0x680a, 0x697c,
+	0x6912, 0x6980, 0x6916, 0x007c, 0x20e1, 0x0007, 0x20e1, 0x2000,
+	0x2001, 0x020a, 0x2004, 0x82ff, 0x0040, 0x160e, 0xa280, 0x0004,
+	0x0d7e, 0x206c, 0x684c, 0xd0dc, 0x00c0, 0x160a, 0x1078, 0x157e,
+	0x0040, 0x160a, 0x0d7f, 0xa280, 0x0000, 0x2003, 0x0002, 0xa016,
+	0x0078, 0x160e, 0x6808, 0x8000, 0x680a, 0x0d7f, 0x127e, 0x047e,
+	0x037e, 0x027e, 0x2091, 0x2100, 0x027f, 0x037f, 0x047f, 0x7000,
+	0xa005, 0x00c0, 0x1622, 0x7206, 0x2001, 0x1643, 0x007e, 0x2260,
+	0x0078, 0x17be, 0x710c, 0x220a, 0x8108, 0x230a, 0x8108, 0x240a,
+	0x8108, 0xa182, 0xa602, 0x0048, 0x162f, 0x2009, 0xa5e7, 0x710e,
+	0x7010, 0xa102, 0xa082, 0x0009, 0x0040, 0x163a, 0xa080, 0x001b,
+	0x00c0, 0x163d, 0x2009, 0x0138, 0x200a, 0x7000, 0xa005, 0x00c0,
+	0x1643, 0x1078, 0x179f, 0x127f, 0x007c, 0x127e, 0x027e, 0x037e,
+	0x0c7e, 0x007e, 0x2091, 0x2100, 0x007f, 0x047f, 0x037f, 0x027f,
+	0x0d7e, 0x0c7e, 0x2460, 0x6110, 0x2168, 0x6a62, 0x6b5e, 0xa005,
+	0x0040, 0x16cf, 0x6808, 0xa005, 0x0040, 0x173c, 0x7000, 0xa005,
+	0x00c0, 0x1664, 0x0078, 0x16c4, 0x700c, 0x7110, 0xa106, 0x00c0,
+	0x1745, 0x7004, 0xa406, 0x00c0, 0x16c4, 0x2001, 0x0005, 0x2004,
+	0xd08c, 0x0040, 0x1681, 0x047e, 0x1078, 0x18e2, 0x047f, 0x2460,
+	0x6010, 0xa080, 0x0002, 0x2004, 0xa005, 0x0040, 0x173c, 0x0078,
+	0x165e, 0x2001, 0x0207, 0x2004, 0xd09c, 0x00c0, 0x166d, 0x7804,
+	0xa084, 0x6000, 0x0040, 0x1692, 0xa086, 0x6000, 0x0040, 0x1692,
+	0x0078, 0x166d, 0x7100, 0xa186, 0x0002, 0x00c0, 0x16b2, 0x0e7e,
+	0x2b68, 0x6818, 0x2060, 0x1078, 0x1fea, 0x2804, 0xac70, 0x6034,
+	0xd09c, 0x00c0, 0x16a7, 0x7108, 0x720c, 0x0078, 0x16a9, 0x7110,
+	0x7214, 0x6810, 0xa100, 0x6812, 0x6814, 0xa201, 0x6816, 0x0e7f,
+	0x0078, 0x16b6, 0xa186, 0x0001, 0x00c0, 0x16be, 0x7820, 0x6910,
+	0xa100, 0x6812, 0x7824, 0x6914, 0xa101, 0x6816, 0x7803, 0x0004,
+	0x7003, 0x0000, 0x7004, 0x2060, 0x6100, 0xa18e, 0x0004, 0x00c0,
+	0x1745, 0x2009, 0x0048, 0x1078, 0x756c, 0x0078, 0x1745, 0x6808,
+	0xa005, 0x0040, 0x173c, 0x7000, 0xa005, 0x00c0, 0x16d9, 0x0078,
+	0x173c, 0x700c, 0x7110, 0xa106, 0x00c0, 0x16e2, 0x7004, 0xa406,
+	0x00c0, 0x173c, 0x2001, 0x0005, 0x2004, 0xd08c, 0x0040, 0x16f6,
+	0x047e, 0x1078, 0x18e2, 0x047f, 0x2460, 0x6010, 0xa080, 0x0002,
+	0x2004, 0xa005, 0x0040, 0x173c, 0x0078, 0x16d3, 0x2001, 0x0207,
+	0x2004, 0xd09c, 0x00c0, 0x16e2, 0x2001, 0x0005, 0x2004, 0xd08c,
+	0x00c0, 0x16e8, 0x7804, 0xa084, 0x6000, 0x0040, 0x170d, 0xa086,
+	0x6000, 0x0040, 0x170d, 0x0078, 0x16e2, 0x7007, 0x0000, 0xa016,
+	0x2218, 0x7000, 0xa08e, 0x0001, 0x0040, 0x172e, 0xa08e, 0x0002,
+	0x00c0, 0x173c, 0x0c7e, 0x0e7e, 0x6818, 0x2060, 0x1078, 0x1fea,
+	0x2804, 0xac70, 0x6034, 0xd09c, 0x00c0, 0x172a, 0x7308, 0x720c,
+	0x0078, 0x172c, 0x7310, 0x7214, 0x0e7f, 0x0c7f, 0x7820, 0xa318,
+	0x7824, 0xa211, 0x6810, 0xa300, 0x6812, 0x6814, 0xa201, 0x6816,
+	0x7803, 0x0004, 0x7003, 0x0000, 0x6100, 0xa18e, 0x0004, 0x00c0,
+	0x1745, 0x2009, 0x0048, 0x1078, 0x756c, 0x0c7f, 0x0d7f, 0x127f,
+	0x007c, 0x0f7e, 0x0e7e, 0x027e, 0x037e, 0x047e, 0x1078, 0x1af7,
+	0x027e, 0x2071, 0xa5e1, 0x7000, 0xa086, 0x0000, 0x0040, 0x1790,
+	0x7004, 0xac06, 0x00c0, 0x1781, 0x2079, 0x0030, 0x7000, 0xa086,
+	0x0003, 0x0040, 0x1781, 0x7804, 0xd0fc, 0x00c0, 0x177d, 0x2001,
+	0x0207, 0x2004, 0xd09c, 0x00c0, 0x1763, 0x7803, 0x0004, 0x7804,
+	0xd0ac, 0x00c0, 0x176f, 0x7803, 0x0002, 0x7803, 0x0009, 0x7003,
+	0x0003, 0x7007, 0x0000, 0x0078, 0x1781, 0x1078, 0x18e2, 0x0078,
+	0x1753, 0x157e, 0x20a9, 0x0009, 0x2009, 0xa5e7, 0x2104, 0xac06,
+	0x00c0, 0x178b, 0x200a, 0xa188, 0x0003, 0x00f0, 0x1786, 0x157f,
+	0x027f, 0x2001, 0x015d, 0x201c, 0x831a, 0x2302, 0x2001, 0x0138,
+	0x2202, 0x047f, 0x037f, 0x027f, 0x0e7f, 0x0f7f, 0x007c, 0x700c,
+	0x7110, 0xa106, 0x00c0, 0x17a7, 0x7003, 0x0000, 0x007c, 0x2104,
+	0x7006, 0x2060, 0x8108, 0x211c, 0x8108, 0x2124, 0x8108, 0xa182,
+	0xa602, 0x0048, 0x17b5, 0x2009, 0xa5e7, 0x7112, 0x700c, 0xa106,
+	0x00c0, 0x17be, 0x2001, 0x0138, 0x2003, 0x0008, 0x8cff, 0x00c0,
+	0x17c5, 0x1078, 0x1b22, 0x0078, 0x1823, 0x6010, 0x2068, 0x2d58,
+	0x6828, 0xa406, 0x00c0, 0x17d0, 0x682c, 0xa306, 0x0040, 0x17fe,
+	0x601c, 0xa086, 0x0008, 0x0040, 0x17fe, 0x6024, 0xd0f4, 0x00c0,
+	0x17fa, 0xd0d4, 0x0040, 0x17f6, 0x6038, 0xa402, 0x6034, 0xa303,
+	0x0040, 0x17e4, 0x00c8, 0x17f6, 0x643a, 0x6336, 0x6c2a, 0x6b2e,
+	0x047e, 0x037e, 0x2400, 0x6c7c, 0xa402, 0x6812, 0x2300, 0x6b80,
+	0xa303, 0x6816, 0x037f, 0x047f, 0x0078, 0x17fa, 0x1078, 0x8d8e,
+	0x0040, 0x17c1, 0x1078, 0x2035, 0x00c0, 0x17c1, 0x0c7e, 0x7004,
+	0x2060, 0x6024, 0xc0d4, 0x6026, 0x0c7f, 0x684c, 0xd0f4, 0x0040,
+	0x180f, 0x6817, 0xffff, 0x6813, 0xffff, 0x0078, 0x17c1, 0x6824,
+	0x2050, 0x6818, 0x2060, 0x6830, 0x2040, 0x6034, 0xa0cc, 0x000f,
+	0x2009, 0x0011, 0x1078, 0x1824, 0x0040, 0x1822, 0x2009, 0x0001,
+	0x1078, 0x1824, 0x2d58, 0x007c, 0x8aff, 0x0040, 0x18bb, 0xa03e,
+	0x2730, 0x6850, 0xd0fc, 0x00c0, 0x1846, 0xd0f4, 0x00c0, 0x1856,
+	0x0d7e, 0x2804, 0xac68, 0x2900, 0x0079, 0x1836, 0x189d, 0x185d,
+	0x185d, 0x189d, 0x189d, 0x1895, 0x189d, 0x185d, 0x189d, 0x1863,
+	0x1863, 0x189d, 0x189d, 0x189d, 0x188c, 0x1863, 0xc0fc, 0x6852,
+	0x6b6c, 0x6a70, 0x6d1c, 0x6c20, 0x0d7e, 0xd99c, 0x0040, 0x18a0,
+	0x2804, 0xac68, 0x6f08, 0x6e0c, 0x0078, 0x18a0, 0xc0f4, 0x6852,
+	0x6b6c, 0x6a70, 0x0d7e, 0x0078, 0x18a7, 0x6b08, 0x6a0c, 0x6d00,
+	0x6c04, 0x0078, 0x18a0, 0x7b0c, 0xd3bc, 0x0040, 0x1884, 0x7004,
+	0x0e7e, 0x2070, 0x701c, 0x0e7f, 0xa086, 0x0008, 0x00c0, 0x1884,
+	0x7b08, 0xa39c, 0x0fff, 0x2d20, 0x0d7f, 0x0d7e, 0x6a14, 0x82ff,
+	0x00c0, 0x187f, 0x6810, 0xa302, 0x0048, 0x187f, 0x6b10, 0x2011,
+	0x0000, 0x2468, 0x0078, 0x1886, 0x6b10, 0x6a14, 0x6d00, 0x6c04,
+	0x6f08, 0x6e0c, 0x0078, 0x18a0, 0x0d7f, 0x0d7e, 0x6834, 0xa084,
+	0x00ff, 0xa086, 0x001e, 0x00c0, 0x189d, 0x0d7f, 0x1078, 0x1fd1,
+	0x00c0, 0x1824, 0xa00e, 0x0078, 0x18bb, 0x0d7f, 0x1078, 0x1328,
+	0x7b22, 0x7a26, 0x7d32, 0x7c36, 0x7f3a, 0x7e3e, 0x7902, 0x7000,
+	0x8000, 0x7002, 0x0d7f, 0x6828, 0xa300, 0x682a, 0x682c, 0xa201,
+	0x682e, 0x2300, 0x6b10, 0xa302, 0x6812, 0x2200, 0x6a14, 0xa203,
+	0x6816, 0x1078, 0x1fd1, 0x007c, 0x1078, 0x1328, 0x1078, 0x1c52,
+	0x7004, 0x2060, 0x0d7e, 0x6010, 0x2068, 0x7003, 0x0000, 0x1078,
+	0x1ac6, 0x1078, 0x8a44, 0x0040, 0x18db, 0x6808, 0x8001, 0x680a,
+	0x697c, 0x6912, 0x6980, 0x6916, 0x682b, 0xffff, 0x682f, 0xffff,
+	0x6850, 0xc0bd, 0x6852, 0x0d7f, 0x1078, 0x8758, 0x0078, 0x1aad,
+	0x1078, 0x1328, 0x127e, 0x2091, 0x2100, 0x007e, 0x017e, 0x2b68,
+	0x6818, 0x2060, 0x7904, 0x7803, 0x0002, 0xa184, 0x0700, 0x00c0,
+	0x18be, 0xa184, 0x0003, 0xa086, 0x0003, 0x0040, 0x18e0, 0x7000,
+	0x0079, 0x18fa, 0x1902, 0x1904, 0x1a06, 0x1a84, 0x1a9b, 0x1902,
+	0x1902, 0x1902, 0x1078, 0x1328, 0x8001, 0x7002, 0xa184, 0x0880,
+	0x00c0, 0x1919, 0x8aff, 0x0040, 0x199b, 0x2009, 0x0001, 0x1078,
+	0x1824, 0x0040, 0x1aad, 0x2009, 0x0001, 0x1078, 0x1824, 0x0078,
+	0x1aad, 0x7803, 0x0004, 0x7003, 0x0000, 0xd1bc, 0x00c0, 0x1979,
+	0x027e, 0x037e, 0x7808, 0xd0ec, 0x00c0, 0x1930, 0x7c20, 0x7d24,
+	0x7e30, 0x7f34, 0x7803, 0x0009, 0x7003, 0x0004, 0x0078, 0x1932,
+	0x1078, 0x1b9f, 0x6b28, 0x6a2c, 0x2400, 0x686e, 0xa31a, 0x2500,
+	0x6872, 0xa213, 0x6b2a, 0x6a2e, 0x0c7e, 0x7004, 0x2060, 0x6024,
+	0xd0f4, 0x00c0, 0x1945, 0x633a, 0x6236, 0x0c7f, 0x2400, 0x6910,
+	0xa100, 0x6812, 0x2500, 0x6914, 0xa101, 0x6816, 0x037f, 0x027f,
+	0x2600, 0x681e, 0x2700, 0x6822, 0x1078, 0x1fea, 0x2a00, 0x6826,
+	0x2c00, 0x681a, 0x2800, 0x6832, 0x6850, 0xc0fd, 0x6852, 0x6808,
+	0x8001, 0x680a, 0x00c0, 0x196e, 0x684c, 0xd0e4, 0x0040, 0x196e,
+	0x7004, 0x2060, 0x2009, 0x0048, 0x1078, 0x756c, 0x7000, 0xa086,
+	0x0004, 0x0040, 0x1aad, 0x7003, 0x0000, 0x1078, 0x179f, 0x0078,
+	0x1aad, 0x057e, 0x7d0c, 0xd5bc, 0x00c0, 0x1980, 0x1078, 0xa20c,
+	0x057f, 0x1078, 0x1ac6, 0x0f7e, 0x7004, 0x2078, 0x1078, 0x4893,
+	0x0040, 0x198d, 0x7824, 0xc0f5, 0x7826, 0x0f7f, 0x682b, 0xffff,
+	0x682f, 0xffff, 0x6808, 0x8001, 0x680a, 0x697c, 0x6912, 0x6980,
+	0x6916, 0x0078, 0x1aad, 0x7004, 0x0c7e, 0x2060, 0x6024, 0x0c7f,
+	0xd0f4, 0x0040, 0x19a8, 0x6808, 0x8001, 0x680a, 0x0078, 0x1aad,
+	0x684c, 0xc0f5, 0x684e, 0x7814, 0xa005, 0x00c0, 0x19c0, 0x7003,
+	0x0000, 0x6808, 0x8001, 0x680a, 0x00c0, 0x19bc, 0x7004, 0x2060,
+	0x2009, 0x0048, 0x1078, 0x756c, 0x1078, 0x179f, 0x0078, 0x1aad,
+	0x7814, 0x6910, 0xa102, 0x6812, 0x6914, 0xa183, 0x0000, 0x6816,
+	0x7814, 0x7908, 0xa18c, 0x0fff, 0xa188, 0x0007, 0x8114, 0x8214,
+	0x8214, 0xa10a, 0x8104, 0x8004, 0x8004, 0xa20a, 0x810b, 0x810b,
+	0x810b, 0x1078, 0x1b4d, 0x7803, 0x0004, 0x780f, 0xffff, 0x7803,
+	0x0001, 0x7804, 0xd0fc, 0x0040, 0x19e1, 0x7803, 0x0002, 0x7803,
+	0x0004, 0x780f, 0x0076, 0x7004, 0x7007, 0x0000, 0x2060, 0x2009,
+	0x0048, 0x1078, 0x756c, 0x1078, 0x1b81, 0x0040, 0x19bc, 0x7908,
+	0xd1ec, 0x00c0, 0x19ff, 0x2009, 0x0009, 0x0078, 0x1a01, 0x2009,
+	0x0019, 0x7902, 0x7003, 0x0003, 0x0078, 0x1aad, 0x8001, 0x7002,
+	0xd194, 0x0040, 0x1a18, 0x7804, 0xd0fc, 0x00c0, 0x18ea, 0x8aff,
+	0x0040, 0x1aad, 0x2009, 0x0001, 0x1078, 0x1824, 0x0078, 0x1aad,
+	0xa184, 0x0880, 0x00c0, 0x1a25, 0x8aff, 0x0040, 0x1aad, 0x2009,
+	0x0001, 0x1078, 0x1824, 0x0078, 0x1aad, 0x7803, 0x0004, 0x7003,
+	0x0000, 0xd1bc, 0x00c0, 0x1a65, 0x027e, 0x037e, 0x7808, 0xd0ec,
+	0x00c0, 0x1a38, 0x7803, 0x0009, 0x7003, 0x0004, 0x0078, 0x1a3a,
+	0x1078, 0x1b9f, 0x6b28, 0x6a2c, 0x1078, 0x1fea, 0x0d7e, 0x0f7e,
+	0x2d78, 0x2804, 0xac68, 0x6034, 0xd09c, 0x00c0, 0x1a55, 0x6808,
+	0x2008, 0xa31a, 0x680c, 0xa213, 0x7810, 0xa100, 0x7812, 0x690c,
+	0x7814, 0xa101, 0x7816, 0x0078, 0x1a61, 0x6810, 0x2008, 0xa31a,
+	0x6814, 0xa213, 0x7810, 0xa100, 0x7812, 0x6914, 0x7814, 0xa101,
+	0x7816, 0x0f7f, 0x0d7f, 0x0078, 0x1934, 0x057e, 0x7d0c, 0x1078,
+	0xa20c, 0x057f, 0x1078, 0x1ac6, 0x0f7e, 0x7004, 0x2078, 0x1078,
+	0x4893, 0x0040, 0x1a76, 0x7824, 0xc0f5, 0x7826, 0x0f7f, 0x682b,
+	0xffff, 0x682f, 0xffff, 0x6808, 0x8001, 0x680a, 0x697c, 0x6912,
+	0x6980, 0x6916, 0x0078, 0x1aad, 0x7803, 0x0004, 0x7003, 0x0000,
+	0x7004, 0xa00d, 0x0040, 0x1a97, 0x6808, 0x8001, 0x680a, 0x00c0,
+	0x1a97, 0x7004, 0x2060, 0x2009, 0x0048, 0x1078, 0x756c, 0x1078,
+	0x179f, 0x0078, 0x1aad, 0x7803, 0x0004, 0x7003, 0x0000, 0x7004,
+	0x2060, 0x6010, 0xa005, 0x0040, 0x1a97, 0x2068, 0x6808, 0x8000,
+	0x680a, 0x6c28, 0x6b2c, 0x1078, 0x17be, 0x017f, 0x007f, 0x127f,
+	0x007c, 0x127e, 0x2091, 0x2100, 0x7000, 0xa086, 0x0003, 0x00c0,
+	0x1ac4, 0x700c, 0x7110, 0xa106, 0x0040, 0x1ac4, 0x20e1, 0x9028,
+	0x700f, 0xa5e7, 0x7013, 0xa5e7, 0x127f, 0x007c, 0x0c7e, 0x1078,
+	0x1af7, 0x20e1, 0x9028, 0x700c, 0x7110, 0xa106, 0x0040, 0x1aed,
+	0x2104, 0xa005, 0x0040, 0x1ada, 0x2060, 0x6010, 0x2060, 0x6008,
+	0x8001, 0x600a, 0xa188, 0x0003, 0xa182, 0xa602, 0x0048, 0x1ae2,
+	0x2009, 0xa5e7, 0x7112, 0x700c, 0xa106, 0x00c0, 0x1acb, 0x2001,
+	0x0138, 0x2003, 0x0008, 0x0078, 0x1acb, 0x2001, 0x015d, 0x200c,
+	0x810a, 0x2102, 0x2001, 0x0138, 0x2202, 0x0c7f, 0x007c, 0x2001,
+	0x0138, 0x2014, 0x2003, 0x0000, 0x2021, 0xb015, 0x2001, 0x0141,
+	0x201c, 0xd3dc, 0x00c0, 0x1b14, 0x2001, 0x0109, 0x201c, 0xa39c,
+	0x0048, 0x00c0, 0x1b14, 0x2001, 0x0111, 0x201c, 0x83ff, 0x00c0,
+	0x1b14, 0x8421, 0x00c0, 0x1afe, 0x007c, 0x2011, 0x0201, 0x2009,
+	0x003c, 0x2204, 0xa005, 0x00c0, 0x1b21, 0x8109, 0x00c0, 0x1b19,
+	0x007c, 0x007c, 0x1078, 0x1b15, 0x0040, 0x1b4a, 0x7908, 0xd1ec,
+	0x00c0, 0x1b3a, 0x1078, 0x1b81, 0x0040, 0x1b3a, 0x7803, 0x0009,
+	0x7904, 0xd1fc, 0x0040, 0x1b30, 0x7803, 0x0006, 0x1078, 0x1b15,
+	0x0040, 0x1b4a, 0x780c, 0xd0a4, 0x00c0, 0x1b4a, 0x7007, 0x0000,
+	0x1078, 0x1b81, 0x0040, 0x1b4c, 0x7803, 0x0019, 0x7003, 0x0003,
+	0x0078, 0x1b4c, 0x1078, 0x1ac6, 0x007c, 0x0e7e, 0x2071, 0x0200,
+	0x7808, 0xa084, 0xf000, 0xa10d, 0x1078, 0x1af7, 0x2019, 0x5000,
+	0x8319, 0x0040, 0x1b6b, 0x2001, 0xa602, 0x2004, 0xa086, 0x0000,
+	0x0040, 0x1b6b, 0x2001, 0x0021, 0xd0fc, 0x0040, 0x1b58, 0x1078,
+	0x1e5d, 0x0078, 0x1b56, 0x20e1, 0x7000, 0x7324, 0x7420, 0x7028,
+	0x7028, 0x7426, 0x7037, 0x0001, 0x810f, 0x712e, 0x702f, 0x0100,
+	0x7037, 0x0008, 0x7326, 0x7422, 0x2001, 0x0138, 0x2202, 0x0e7f,
+	0x007c, 0x7908, 0xa18c, 0x0fff, 0xa182, 0x0009, 0x0048, 0x1b8c,
+	0xa085, 0x0001, 0x0078, 0x1b9e, 0x2001, 0x020a, 0x81ff, 0x0040,
+	0x1b97, 0x20e1, 0x6000, 0x200c, 0x200c, 0x200c, 0x200c, 0x20e1,
+	0x7000, 0x200c, 0x200c, 0x7003, 0x0000, 0xa006, 0x007c, 0x7c20,
+	0x7d24, 0x7e30, 0x7f34, 0x700c, 0x7110, 0xa106, 0x0040, 0x1c24,
+	0x7004, 0x017e, 0x210c, 0xa106, 0x017f, 0x0040, 0x1c24, 0x0d7e,
+	0x0c7e, 0x216c, 0x2d00, 0xa005, 0x0040, 0x1c22, 0x6824, 0xd0d4,
+	0x00c0, 0x1c22, 0x6810, 0x2068, 0x6850, 0xd0fc, 0x0040, 0x1bec,
+	0x8108, 0x2104, 0x6b2c, 0xa306, 0x00c0, 0x1c22, 0x8108, 0x2104,
+	0x6a28, 0xa206, 0x00c0, 0x1c22, 0x6850, 0xc0fc, 0xc0f5, 0x6852,
+	0x686c, 0x7822, 0x6870, 0x7826, 0x681c, 0x7832, 0x6820, 0x7836,
+	0x6818, 0x2060, 0x6034, 0xd09c, 0x0040, 0x1be7, 0x6830, 0x2004,
+	0xac68, 0x6808, 0x783a, 0x680c, 0x783e, 0x0078, 0x1c20, 0xa006,
+	0x783a, 0x783e, 0x0078, 0x1c20, 0x8108, 0x2104, 0xa005, 0x00c0,
+	0x1c22, 0x8108, 0x2104, 0xa005, 0x00c0, 0x1c22, 0x6850, 0xc0f5,
+	0x6852, 0x6830, 0x2004, 0x6918, 0xa160, 0xa180, 0x000d, 0x2004,
+	0xd09c, 0x00c0, 0x1c12, 0x6008, 0x7822, 0x686e, 0x600c, 0x7826,
+	0x6872, 0x6000, 0x7832, 0x6004, 0x7836, 0xa006, 0x783a, 0x783e,
+	0x0078, 0x1c20, 0x6010, 0x7822, 0x686e, 0x6014, 0x7826, 0x6872,
+	0x6000, 0x7832, 0x6004, 0x7836, 0x6008, 0x783a, 0x600c, 0x783e,
+	0x7803, 0x0011, 0x0c7f, 0x0d7f, 0x007c, 0x0f7e, 0x0e7e, 0x017e,
+	0x027e, 0x2071, 0xa5e1, 0x2079, 0x0030, 0x2011, 0x0050, 0x7000,
+	0xa086, 0x0000, 0x0040, 0x1c4d, 0x8211, 0x0040, 0x1c4b, 0x2001,
+	0x0005, 0x2004, 0xd08c, 0x0040, 0x1c34, 0x7904, 0xa18c, 0x0780,
+	0x017e, 0x1078, 0x18e2, 0x017f, 0x81ff, 0x00c0, 0x1c4b, 0x2011,
+	0x0050, 0x0078, 0x1c2f, 0xa085, 0x0001, 0x027f, 0x017f, 0x0e7f,
+	0x0f7f, 0x007c, 0x7803, 0x0004, 0x2009, 0x0064, 0x7804, 0xd0ac,
+	0x0040, 0x1ca3, 0x8109, 0x00c0, 0x1c56, 0x2009, 0x0100, 0x210c,
+	0xa18a, 0x0003, 0x1048, 0x1328, 0x1078, 0x1f75, 0x0e7e, 0x0f7e,
+	0x2071, 0xa5d0, 0x2079, 0x0010, 0x7004, 0xa086, 0x0000, 0x0040,
+	0x1c9b, 0x7800, 0x007e, 0x7820, 0x007e, 0x7830, 0x007e, 0x7834,
+	0x007e, 0x7838, 0x007e, 0x783c, 0x007e, 0x7803, 0x0004, 0x7823,
+	0x0000, 0x0005, 0x0005, 0x2079, 0x0030, 0x7804, 0xd0ac, 0x10c0,
+	0x1328, 0x2079, 0x0010, 0x007f, 0x783e, 0x007f, 0x783a, 0x007f,
+	0x7836, 0x007f, 0x7832, 0x007f, 0x7822, 0x007f, 0x7802, 0x0f7f,
+	0x0e7f, 0x0078, 0x1ca1, 0x0f7f, 0x0e7f, 0x7804, 0xd0ac, 0x10c0,
+	0x1328, 0x1078, 0x61d3, 0x007c, 0x0e7e, 0x2071, 0xa602, 0x7003,
+	0x0000, 0x0e7f, 0x007c, 0x0d7e, 0xa280, 0x0004, 0x206c, 0x694c,
+	0xd1dc, 0x00c0, 0x1d26, 0x6934, 0xa184, 0x0007, 0x0079, 0x1cb8,
+	0x1cc0, 0x1d11, 0x1cc0, 0x1cc0, 0x1cc0, 0x1cf6, 0x1cd3, 0x1cc2,
+	0x1078, 0x1328, 0x684c, 0xd0b4, 0x0040, 0x1e34, 0x6860, 0x682e,
+	0x6816, 0x685c, 0x682a, 0x6812, 0x687c, 0x680a, 0x6880, 0x680e,
+	0x6958, 0x0078, 0x1d19, 0x6834, 0xa084, 0x00ff, 0xa086, 0x001e,
+	0x00c0, 0x1cc0, 0x684c, 0xd0b4, 0x0040, 0x1e34, 0x6860, 0x682e,
+	0x6816, 0x685c, 0x682a, 0x6812, 0x687c, 0x680a, 0x6880, 0x680e,
+	0x6804, 0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080,
+	0x2015, 0x2004, 0x6832, 0x6958, 0x0078, 0x1d22, 0xa18c, 0x00ff,
+	0xa186, 0x0015, 0x00c0, 0x1d26, 0x684c, 0xd0b4, 0x0040, 0x1e34,
+	0x6804, 0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080,
+	0x2015, 0x2004, 0x6832, 0x6958, 0xa006, 0x682e, 0x682a, 0x0078,
+	0x1d22, 0x684c, 0xd0b4, 0x0040, 0x18bc, 0x6958, 0xa006, 0x682e,
+	0x682a, 0x2d00, 0x681a, 0x6834, 0xa084, 0x000f, 0xa080, 0x2015,
+	0x2004, 0x6832, 0x6926, 0x684c, 0xc0dd, 0x684e, 0x0d7f, 0x007c,
+	0x0f7e, 0x2079, 0x0020, 0x7804, 0xd0fc, 0x10c0, 0x1e5d, 0x0e7e,
+	0x0d7e, 0x2071, 0xa602, 0x7000, 0xa005, 0x00c0, 0x1dab, 0x0c7e,
+	0x7206, 0xa280, 0x0004, 0x205c, 0x7004, 0x2068, 0x7803, 0x0004,
+	0x6818, 0x0d7e, 0x2068, 0x686c, 0x7812, 0x6890, 0x0f7e, 0x20e1,
+	0x9040, 0x2079, 0x0200, 0x781a, 0x2079, 0x0100, 0x8004, 0x78d6,
+	0x0f7f, 0x0d7f, 0x2b68, 0x6824, 0x2050, 0x6818, 0x2060, 0x6830,
+	0x2040, 0x6034, 0xa0cc, 0x000f, 0x6908, 0x2001, 0x04fd, 0x2004,
+	0xa086, 0x0007, 0x0040, 0x1d6d, 0xa184, 0x0007, 0x0040, 0x1d6d,
+	0x017e, 0x2009, 0x0008, 0xa102, 0x017f, 0xa108, 0x791a, 0x7116,
+	0x701e, 0x680c, 0xa081, 0x0000, 0x781e, 0x701a, 0xa006, 0x700e,
+	0x7012, 0x7004, 0x692c, 0x6814, 0xa106, 0x00c0, 0x1d84, 0x6928,
+	0x6810, 0xa106, 0x0040, 0x1d91, 0x037e, 0x047e, 0x6b14, 0x6c10,
+	0x1078, 0x2035, 0x047f, 0x037f, 0x0040, 0x1d91, 0x0c7f, 0x0078,
+	0x1dab, 0x8aff, 0x00c0, 0x1d99, 0x0c7f, 0xa085, 0x0001, 0x0078,
+	0x1dab, 0x127e, 0x2091, 0x8000, 0x2079, 0x0020, 0x2009, 0x0001,
+	0x1078, 0x1daf, 0x0040, 0x1da8, 0x2009, 0x0001, 0x1078, 0x1daf,
+	0x127f, 0x0c7f, 0xa006, 0x0d7f, 0x0e7f, 0x0f7f, 0x007c, 0x077e,
+	0x067e, 0x057e, 0x047e, 0x037e, 0x027e, 0x8aff, 0x0040, 0x1e2d,
+	0x700c, 0x7214, 0xa23a, 0x7010, 0x7218, 0xa203, 0x0048, 0x1e2c,
+	0xa705, 0x0040, 0x1e2c, 0xa03e, 0x2730, 0x6850, 0xd0fc, 0x00c0,
+	0x1ddf, 0x0d7e, 0x2804, 0xac68, 0x2900, 0x0079, 0x1dcf, 0x1e0e,
+	0x1def, 0x1def, 0x1e0e, 0x1e0e, 0x1e06, 0x1e0e, 0x1def, 0x1e0e,
+	0x1df5, 0x1df5, 0x1e0e, 0x1e0e, 0x1e0e, 0x1dfd, 0x1df5, 0xc0fc,
+	0x6852, 0x6b6c, 0x6a70, 0x6d1c, 0x6c20, 0xd99c, 0x0040, 0x1e12,
+	0x0d7e, 0x2804, 0xac68, 0x6f08, 0x6e0c, 0x0078, 0x1e11, 0x6b08,
+	0x6a0c, 0x6d00, 0x6c04, 0x0078, 0x1e11, 0x6b10, 0x6a14, 0x6d00,
+	0x6c04, 0x6f08, 0x6e0c, 0x0078, 0x1e11, 0x0d7f, 0x0d7e, 0x6834,
+	0xa084, 0x00ff, 0xa086, 0x001e, 0x00c0, 0x1e0e, 0x0d7f, 0x1078,
+	0x1fd1, 0x00c0, 0x1db5, 0xa00e, 0x0078, 0x1e2d, 0x0d7f, 0x1078,
+	0x1328, 0x0d7f, 0x7b22, 0x7a26, 0x7d32, 0x7c36, 0x7f3a, 0x7e3e,
+	0x7902, 0x7000, 0x8000, 0x7002, 0x6828, 0xa300, 0x682a, 0x682c,
+	0xa201, 0x682e, 0x700c, 0xa300, 0x700e, 0x7010, 0xa201, 0x7012,
+	0x1078, 0x1fd1, 0x0078, 0x1e2d, 0xa006, 0x027f, 0x037f, 0x047f,
+	0x057f, 0x067f, 0x077f, 0x007c, 0x1078, 0x1328, 0x027e, 0x2001,
+	0x0105, 0x2003, 0x0010, 0x20e1, 0x9040, 0x7803, 0x0004, 0x7003,
+	0x0000, 0x7004, 0x2060, 0x0d7e, 0x6010, 0x2068, 0x1078, 0x8a44,
+	0x0040, 0x1e4d, 0x6850, 0xc0bd, 0x6852, 0x0d7f, 0x1078, 0x8758,
+	0x20e1, 0x9040, 0x1078, 0x719a, 0x2011, 0x0000, 0x1078, 0x6efc,
+	0x1078, 0x61d3, 0x027f, 0x0078, 0x1f29, 0x127e, 0x2091, 0x2200,
+	0x007e, 0x017e, 0x0f7e, 0x0e7e, 0x0d7e, 0x0c7e, 0x2079, 0x0020,
+	0x2071, 0xa602, 0x2b68, 0x6818, 0x2060, 0x7904, 0x7803, 0x0002,
+	0xa184, 0x0700, 0x00c0, 0x1e36, 0x7000, 0x0079, 0x1e77, 0x1f29,
+	0x1e7b, 0x1ef6, 0x1f27, 0x8001, 0x7002, 0xd19c, 0x00c0, 0x1e8f,
+	0x8aff, 0x0040, 0x1eae, 0x2009, 0x0001, 0x1078, 0x1daf, 0x0040,
+	0x1f29, 0x2009, 0x0001, 0x1078, 0x1daf, 0x0078, 0x1f29, 0x7803,
+	0x0004, 0xd194, 0x0040, 0x1e9f, 0x6850, 0xc0fc, 0x6852, 0x8aff,
+	0x00c0, 0x1ea4, 0x684c, 0xc0f5, 0x684e, 0x0078, 0x1ea4, 0x1078,
+	0x1fea, 0x6850, 0xc0fd, 0x6852, 0x2a00, 0x6826, 0x2c00, 0x681a,
+	0x2800, 0x6832, 0x7003, 0x0000, 0x0078, 0x1f29, 0x711c, 0x81ff,
+	0x0040, 0x1ec4, 0x7918, 0x7922, 0x7827, 0x0000, 0x7803, 0x0001,
+	0x7000, 0x8000, 0x7002, 0x700c, 0xa100, 0x700e, 0x7010, 0xa081,
+	0x0000, 0x7012, 0x0078, 0x1f29, 0x0f7e, 0x027e, 0x781c, 0x007e,
+	0x7818, 0x007e, 0x2079, 0x0100, 0x7a14, 0xa284, 0x0004, 0xa085,
+	0x0012, 0x7816, 0x037e, 0x2019, 0x1000, 0x8319, 0x1040, 0x1328,
+	0x7820, 0xd0bc, 0x00c0, 0x1ed5, 0x037f, 0x79c8, 0x007f, 0xa102,
+	0x017f, 0x007e, 0x017e, 0x79c4, 0x007f, 0xa103, 0x78c6, 0x007f,
+	0x78ca, 0xa284, 0x0004, 0xa085, 0x0012, 0x7816, 0x027f, 0x0f7f,
+	0x7803, 0x0008, 0x7003, 0x0000, 0x0078, 0x1f29, 0x8001, 0x7002,
+	0xd194, 0x0040, 0x1f0b, 0x7804, 0xd0fc, 0x00c0, 0x1e6d, 0xd19c,
+	0x00c0, 0x1f25, 0x8aff, 0x0040, 0x1f29, 0x2009, 0x0001, 0x1078,
+	0x1daf, 0x0078, 0x1f29, 0x027e, 0x037e, 0x6b28, 0x6a2c, 0x1078,
+	0x1fea, 0x0d7e, 0x2804, 0xac68, 0x6034, 0xd09c, 0x00c0, 0x1f1e,
+	0x6808, 0xa31a, 0x680c, 0xa213, 0x0078, 0x1f22, 0x6810, 0xa31a,
+	0x6814, 0xa213, 0x0d7f, 0x0078, 0x1e9f, 0x0078, 0x1e9f, 0x1078,
+	0x1328, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f, 0x017f, 0x007f, 0x127f,
+	0x007c, 0x0f7e, 0x0e7e, 0x2071, 0xa602, 0x7000, 0xa086, 0x0000,
+	0x0040, 0x1f72, 0x2079, 0x0020, 0x017e, 0x2009, 0x0207, 0x210c,
+	0xd194, 0x0040, 0x1f4f, 0x2009, 0x020c, 0x210c, 0xa184, 0x0003,
+	0x0040, 0x1f4f, 0x20e1, 0x9040, 0x2001, 0x020c, 0x2102, 0x2009,
+	0x0206, 0x2104, 0x2009, 0x0203, 0x210c, 0xa106, 0x00c0, 0x1f5a,
+	0x20e1, 0x9040, 0x7804, 0xd0fc, 0x0040, 0x1f3d, 0x1078, 0x1e5d,
+	0x7000, 0xa086, 0x0000, 0x00c0, 0x1f3d, 0x017f, 0x7803, 0x0004,
+	0x7804, 0xd0ac, 0x00c0, 0x1f68, 0x20e1, 0x9040, 0x7803, 0x0002,
+	0x7003, 0x0000, 0x0e7f, 0x0f7f, 0x007c, 0x027e, 0x0c7e, 0x0d7e,
+	0x0e7e, 0x0f7e, 0x2071, 0xa602, 0x2079, 0x0020, 0x7000, 0xa086,
+	0x0000, 0x0040, 0x1fae, 0x7004, 0x2060, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x1f98, 0x6850, 0xc0b5, 0x6852, 0x680c, 0x7a1c,
+	0xa206, 0x00c0, 0x1f98, 0x6808, 0x7a18, 0xa206, 0x0040, 0x1fb4,
+	0x2001, 0x0105, 0x2003, 0x0010, 0x20e1, 0x9040, 0x7803, 0x0004,
+	0x7003, 0x0000, 0x7004, 0x2060, 0x1078, 0x8758, 0x20e1, 0x9040,
+	0x1078, 0x719a, 0x2011, 0x0000, 0x1078, 0x6efc, 0x0f7f, 0x0e7f,
+	0x0d7f, 0x0c7f, 0x027f, 0x007c, 0x6810, 0x6a14, 0xa205, 0x00c0,
+	0x1f98, 0x684c, 0xc0dc, 0x684e, 0x2c10, 0x1078, 0x1cab, 0x2001,
+	0x0105, 0x2003, 0x0010, 0x20e1, 0x9040, 0x7803, 0x0004, 0x7003,
+	0x0000, 0x2069, 0xa5ab, 0x6833, 0x0000, 0x683f, 0x0000, 0x0078,
+	0x1fae, 0x8840, 0x2804, 0xa005, 0x00c0, 0x1fe5, 0x6004, 0xa005,
+	0x0040, 0x1fe7, 0x681a, 0x2060, 0x6034, 0xa084, 0x000f, 0xa080,
+	0x2015, 0x2044, 0x88ff, 0x1040, 0x1328, 0x8a51, 0x007c, 0x2051,
+	0x0000, 0x007c, 0x8a50, 0x8841, 0x2804, 0xa005, 0x00c0, 0x2004,
+	0x2c00, 0xad06, 0x0040, 0x1ff9, 0x6000, 0xa005, 0x00c0, 0x1ff9,
+	0x2d00, 0x2060, 0x681a, 0x6034, 0xa084, 0x000f, 0xa080, 0x2025,
+	0x2044, 0x88ff, 0x1040, 0x1328, 0x007c, 0x0000, 0x0011, 0x0015,
+	0x0019, 0x001d, 0x0021, 0x0025, 0x0029, 0x0000, 0x000f, 0x0015,
+	0x001b, 0x0021, 0x0027, 0x0000, 0x0000, 0x0000, 0x200a, 0x2006,
+	0x0000, 0x0000, 0x2014, 0x0000, 0x200a, 0x0000, 0x2011, 0x200e,
+	0x0000, 0x0000, 0x0000, 0x2014, 0x2011, 0x0000, 0x200c, 0x200c,
+	0x0000, 0x0000, 0x2014, 0x0000, 0x200c, 0x0000, 0x2012, 0x2012,
+	0x0000, 0x0000, 0x0000, 0x2014, 0x2012, 0x0a7e, 0x097e, 0x087e,
+	0x6b2e, 0x6c2a, 0x6858, 0xa055, 0x0040, 0x20d8, 0x2d60, 0x6034,
+	0xa0cc, 0x000f, 0xa9c0, 0x2015, 0xa986, 0x0007, 0x0040, 0x2050,
+	0xa986, 0x000e, 0x0040, 0x2050, 0xa986, 0x000f, 0x00c0, 0x2054,
+	0x605c, 0xa422, 0x6060, 0xa31a, 0x2804, 0xa045, 0x00c0, 0x2062,
+	0x0050, 0x205c, 0x0078, 0x20d8, 0x6004, 0xa065, 0x0040, 0x20d8,
+	0x0078, 0x203f, 0x2804, 0xa005, 0x0040, 0x2080, 0xac68, 0xd99c,
+	0x00c0, 0x2070, 0x6808, 0xa422, 0x680c, 0xa31b, 0x0078, 0x2074,
+	0x6810, 0xa422, 0x6814, 0xa31b, 0x0048, 0x209f, 0x2300, 0xa405,
+	0x0040, 0x2086, 0x8a51, 0x0040, 0x20d8, 0x8840, 0x0078, 0x2062,
+	0x6004, 0xa065, 0x0040, 0x20d8, 0x0078, 0x203f, 0x8a51, 0x0040,
+	0x20d8, 0x8840, 0x2804, 0xa005, 0x00c0, 0x2099, 0x6004, 0xa065,
+	0x0040, 0x20d8, 0x6034, 0xa0cc, 0x000f, 0xa9c0, 0x2015, 0x2804,
+	0x2040, 0x2b68, 0x6850, 0xc0fc, 0x6852, 0x0078, 0x20cc, 0x8422,
+	0x8420, 0x831a, 0xa399, 0x0000, 0x0d7e, 0x2b68, 0x6c6e, 0x6b72,
+	0x0d7f, 0xd99c, 0x00c0, 0x20ba, 0x6908, 0x2400, 0xa122, 0x690c,
+	0x2300, 0xa11b, 0x1048, 0x1328, 0x6800, 0xa420, 0x6804, 0xa319,
+	0x0078, 0x20c6, 0x6910, 0x2400, 0xa122, 0x6914, 0x2300, 0xa11b,
+	0x1048, 0x1328, 0x6800, 0xa420, 0x6804, 0xa319, 0x2b68, 0x6c1e,
+	0x6b22, 0x6850, 0xc0fd, 0x6852, 0x2c00, 0x681a, 0x2800, 0x6832,
+	0x2a00, 0x6826, 0x007f, 0x007f, 0x007f, 0xa006, 0x0078, 0x20dd,
+	0x087f, 0x097f, 0x0a7f, 0xa085, 0x0001, 0x007c, 0x2001, 0x0005,
+	0x2004, 0xa084, 0x0007, 0x0079, 0x20e5, 0x20ed, 0x20ee, 0x20f1,
+	0x20f4, 0x20f9, 0x20fc, 0x2101, 0x2106, 0x007c, 0x1078, 0x1e5d,
+	0x007c, 0x1078, 0x18e2, 0x007c, 0x1078, 0x18e2, 0x1078, 0x1e5d,
+	0x007c, 0x1078, 0x14b0, 0x007c, 0x1078, 0x1e5d, 0x1078, 0x14b0,
+	0x007c, 0x1078, 0x18e2, 0x1078, 0x14b0, 0x007c, 0x1078, 0x18e2,
+	0x1078, 0x1e5d, 0x1078, 0x14b0, 0x007c, 0x127e, 0x2091, 0x2300,
+	0x2079, 0x0200, 0x2071, 0xa880, 0x2069, 0xa300, 0x2009, 0x0004,
+	0x7912, 0x7817, 0x0004, 0x1078, 0x24b5, 0x781b, 0x0002, 0x20e1,
+	0x8700, 0x127f, 0x007c, 0x127e, 0x2091, 0x2300, 0x781c, 0xa084,
+	0x0007, 0x0079, 0x212b, 0x214f, 0x2133, 0x2137, 0x213b, 0x2141,
+	0x2145, 0x2149, 0x214d, 0x1078, 0x5372, 0x0078, 0x214f, 0x1078,
+	0x53b3, 0x0078, 0x214f, 0x1078, 0x5372, 0x1078, 0x53b3, 0x0078,
+	0x214f, 0x1078, 0x2151, 0x0078, 0x214f, 0x1078, 0x2151, 0x0078,
+	0x214f, 0x1078, 0x2151, 0x0078, 0x214f, 0x1078, 0x2151, 0x127f,
+	0x007c, 0x007e, 0x017e, 0x027e, 0x7930, 0xa184, 0x0003, 0x0040,
+	0x215d, 0x20e1, 0x9040, 0x0078, 0x2186, 0xa184, 0x0030, 0x0040,
+	0x216e, 0x6a00, 0xa286, 0x0003, 0x00c0, 0x2168, 0x0078, 0x216a,
+	0x1078, 0x4171, 0x20e1, 0x9010, 0x0078, 0x2186, 0xa184, 0x00c0,
+	0x0040, 0x2180, 0x0e7e, 0x037e, 0x047e, 0x057e, 0x2071, 0xa5e1,
+	0x1078, 0x1ac6, 0x057f, 0x047f, 0x037f, 0x0e7f, 0x0078, 0x2186,
+	0xa184, 0x0300, 0x0040, 0x2186, 0x20e1, 0x9020, 0x7932, 0x027f,
+	0x017f, 0x007f, 0x007c, 0x017e, 0x0e7e, 0x0f7e, 0x2071, 0xa300,
+	0x7128, 0x2001, 0xa58f, 0x2102, 0x2001, 0xa597, 0x2102, 0xa182,
+	0x0211, 0x00c8, 0x219f, 0x2009, 0x0008, 0x0078, 0x21c9, 0xa182,
+	0x0259, 0x00c8, 0x21a7, 0x2009, 0x0007, 0x0078, 0x21c9, 0xa182,
+	0x02c1, 0x00c8, 0x21af, 0x2009, 0x0006, 0x0078, 0x21c9, 0xa182,
+	0x0349, 0x00c8, 0x21b7, 0x2009, 0x0005, 0x0078, 0x21c9, 0xa182,
+	0x0421, 0x00c8, 0x21bf, 0x2009, 0x0004, 0x0078, 0x21c9, 0xa182,
+	0x0581, 0x00c8, 0x21c7, 0x2009, 0x0003, 0x0078, 0x21c9, 0x2009,
+	0x0002, 0x2079, 0x0200, 0x7912, 0x7817, 0x0004, 0x1078, 0x24b5,
+	0x0f7f, 0x0e7f, 0x017f, 0x007c, 0x127e, 0x2091, 0x2200, 0x2061,
+	0x0100, 0x2071, 0xa300, 0x6024, 0x6026, 0x6053, 0x0030, 0x6033,
+	0x00ef, 0x60e7, 0x0000, 0x60eb, 0x00ef, 0x60e3, 0x0008, 0x604b,
+	0xf7f7, 0x6043, 0x0000, 0x602f, 0x0080, 0x602f, 0x0000, 0x6007,
+	0x0eaf, 0x600f, 0x00ff, 0x602b, 0x002f, 0x127f, 0x007c, 0x2001,
+	0xa32f, 0x2003, 0x0000, 0x2001, 0xa32e, 0x2003, 0x0001, 0x007c,
+	0x127e, 0x2091, 0x2200, 0x007e, 0x017e, 0x027e, 0x6124, 0xa184,
+	0x002c, 0x00c0, 0x220f, 0xa184, 0x0007, 0x0079, 0x2215, 0xa195,
+	0x0004, 0xa284, 0x0007, 0x0079, 0x2215, 0x2241, 0x221d, 0x2221,
+	0x2225, 0x222b, 0x222f, 0x2235, 0x223b, 0x1078, 0x5ad2, 0x0078,
+	0x2241, 0x1078, 0x5bc1, 0x0078, 0x2241, 0x1078, 0x5bc1, 0x1078,
+	0x5ad2, 0x0078, 0x2241, 0x1078, 0x2246, 0x0078, 0x2241, 0x1078,
+	0x5ad2, 0x1078, 0x2246, 0x0078, 0x2241, 0x1078, 0x5bc1, 0x1078,
+	0x2246, 0x0078, 0x2241, 0x1078, 0x5bc1, 0x1078, 0x5ad2, 0x1078,
+	0x2246, 0x027f, 0x017f, 0x007f, 0x127f, 0x007c, 0x6124, 0xd1ac,
+	0x0040, 0x2342, 0x017e, 0x047e, 0x0c7e, 0x644c, 0xa486, 0xf0f0,
+	0x00c0, 0x2259, 0x2061, 0x0100, 0x644a, 0x6043, 0x0090, 0x6043,
+	0x0010, 0x74c2, 0xa48c, 0xff00, 0x7034, 0xd084, 0x0040, 0x2271,
+	0xa186, 0xf800, 0x00c0, 0x2271, 0x7038, 0xd084, 0x00c0, 0x2271,
+	0xc085, 0x703a, 0x037e, 0x2418, 0x2011, 0x8016, 0x1078, 0x3579,
+	0x037f, 0xa196, 0xff00, 0x0040, 0x22b3, 0x6030, 0xa084, 0x00ff,
+	0x810f, 0xa116, 0x0040, 0x22b3, 0x7130, 0xd184, 0x00c0, 0x22b3,
+	0x2011, 0xa352, 0x2214, 0xd2ec, 0x0040, 0x228e, 0xc18d, 0x7132,
+	0x2011, 0xa352, 0x2214, 0xd2ac, 0x00c0, 0x22b3, 0x6240, 0xa294,
+	0x0010, 0x0040, 0x229a, 0x6248, 0xa294, 0xff00, 0xa296, 0xff00,
+	0x0040, 0x22b3, 0x7030, 0xd08c, 0x0040, 0x2305, 0x7034, 0xd08c,
+	0x00c0, 0x22aa, 0x2001, 0xa30c, 0x200c, 0xd1ac, 0x00c0, 0x2305,
+	0xc1ad, 0x2102, 0x037e, 0x73c0, 0x2011, 0x8013, 0x1078, 0x3579,
+	0x037f, 0x0078, 0x2305, 0x7034, 0xd08c, 0x00c0, 0x22bf, 0x2001,
+	0xa30c, 0x200c, 0xd1ac, 0x00c0, 0x2305, 0xc1ad, 0x2102, 0x037e,
+	0x73c0, 0x2011, 0x8013, 0x1078, 0x3579, 0x037f, 0x7130, 0xc185,
+	0x7132, 0x2011, 0xa352, 0x220c, 0xd1a4, 0x0040, 0x22e9, 0x017e,
+	0x2009, 0x0001, 0x2011, 0x0100, 0x1078, 0x5a6d, 0x2019, 0x000e,
+	0x1078, 0x9e3b, 0xa484, 0x00ff, 0xa080, 0x293f, 0x200c, 0xa18c,
+	0xff00, 0x810f, 0x8127, 0xa006, 0x2009, 0x000e, 0x1078, 0x9ec0,
+	0x017f, 0xd1ac, 0x00c0, 0x22f6, 0x017e, 0x2009, 0x0000, 0x2019,
+	0x0004, 0x1078, 0x27e2, 0x017f, 0x0078, 0x2305, 0x157e, 0x20a9,
+	0x007f, 0x2009, 0x0000, 0x1078, 0x4501, 0x00c0, 0x2301, 0x1078,
+	0x4235, 0x8108, 0x00f0, 0x22fb, 0x157f, 0x0c7f, 0x047f, 0x0f7e,
+	0x2079, 0xa5be, 0x783c, 0xa086, 0x0000, 0x0040, 0x2317, 0x6027,
+	0x0004, 0x783f, 0x0000, 0x2079, 0x0140, 0x7803, 0x0000, 0x0f7f,
+	0x2011, 0x0003, 0x1078, 0x6ef2, 0x2011, 0x0002, 0x1078, 0x6efc,
+	0x1078, 0x6dda, 0x1078, 0x595a, 0x037e, 0x2019, 0x0000, 0x1078,
+	0x6e6c, 0x037f, 0x60e3, 0x0000, 0x017f, 0x2001, 0xa300, 0x2014,
+	0xa296, 0x0004, 0x00c0, 0x233a, 0xd19c, 0x00c0, 0x233a, 0x6228,
+	0xc29d, 0x622a, 0x2003, 0x0001, 0x2001, 0xa321, 0x2003, 0x0000,
+	0x6027, 0x0020, 0xd194, 0x0040, 0x2426, 0x0f7e, 0x2079, 0xa5be,
+	0x783c, 0xa086, 0x0001, 0x00c0, 0x2366, 0x017e, 0x6027, 0x0004,
+	0x783f, 0x0000, 0x2079, 0x0140, 0x7803, 0x1000, 0x7803, 0x0000,
+	0x2079, 0xa5ab, 0x7807, 0x0000, 0x7833, 0x0000, 0x1078, 0x6109,
+	0x1078, 0x61d3, 0x017f, 0x0f7f, 0x0078, 0x2426, 0x0f7f, 0x017e,
+	0x3900, 0xa082, 0xa6cd, 0x00c8, 0x2371, 0x017e, 0x1078, 0x728a,
+	0x017f, 0x6220, 0xd2b4, 0x0040, 0x23dc, 0x1078, 0x595a, 0x1078,
+	0x6c41, 0x6027, 0x0004, 0x0f7e, 0x2019, 0xa5b4, 0x2304, 0xa07d,
+	0x0040, 0x23b2, 0x7804, 0xa086, 0x0032, 0x00c0, 0x23b2, 0x0d7e,
+	0x0c7e, 0x0e7e, 0x2069, 0x0140, 0x618c, 0x6288, 0x7818, 0x608e,
+	0x7808, 0x608a, 0x6043, 0x0002, 0x2001, 0x0003, 0x8001, 0x00c0,
+	0x2396, 0x6043, 0x0000, 0x6803, 0x1000, 0x6803, 0x0000, 0x618e,
+	0x628a, 0x1078, 0x6010, 0x1078, 0x6109, 0x7810, 0x2070, 0x7037,
+	0x0103, 0x2f60, 0x1078, 0x753d, 0x0e7f, 0x0c7f, 0x0d7f, 0x0f7f,
+	0x017f, 0x007c, 0x0f7f, 0x0d7e, 0x2069, 0x0140, 0x6804, 0xa084,
+	0x4000, 0x0040, 0x23bf, 0x6803, 0x1000, 0x6803, 0x0000, 0x0d7f,
+	0x0c7e, 0x2061, 0xa5ab, 0x6028, 0xa09a, 0x00c8, 0x00c8, 0x23cf,
+	0x8000, 0x602a, 0x0c7f, 0x1078, 0x6c33, 0x0078, 0x2425, 0x2019,
+	0xa5b4, 0x2304, 0xa065, 0x0040, 0x23d9, 0x2009, 0x0027, 0x1078,
+	0x756c, 0x0c7f, 0x0078, 0x2425, 0xd2bc, 0x0040, 0x2425, 0x1078,
+	0x5967, 0x6017, 0x0010, 0x6027, 0x0004, 0x0d7e, 0x2069, 0x0140,
+	0x6804, 0xa084, 0x4000, 0x0040, 0x23f1, 0x6803, 0x1000, 0x6803,
+	0x0000, 0x0d7f, 0x0c7e, 0x2061, 0xa5ab, 0x6044, 0xa09a, 0x00c8,
+	0x00c8, 0x2414, 0x8000, 0x6046, 0x603c, 0x0c7f, 0xa005, 0x0040,
+	0x2425, 0x2009, 0x07d0, 0x1078, 0x595f, 0xa080, 0x0007, 0x2004,
+	0xa086, 0x0006, 0x00c0, 0x2410, 0x6017, 0x0012, 0x0078, 0x2425,
+	0x6017, 0x0016, 0x0078, 0x2425, 0x037e, 0x2019, 0x0001, 0x1078,
+	0x6e6c, 0x037f, 0x2019, 0xa5ba, 0x2304, 0xa065, 0x0040, 0x2424,
+	0x2009, 0x004f, 0x1078, 0x756c, 0x0c7f, 0x017f, 0xd19c, 0x0040,
+	0x247c, 0x7034, 0xd0ac, 0x00c0, 0x2457, 0x017e, 0x157e, 0x6027,
+	0x0008, 0x602f, 0x0020, 0x20a9, 0x000a, 0x00f0, 0x2435, 0x602f,
+	0x0000, 0x6150, 0xa185, 0x1400, 0x6052, 0x20a9, 0x0320, 0x00e0,
+	0x243f, 0x2091, 0x6000, 0x6020, 0xd09c, 0x00c0, 0x244e, 0x157f,
+	0x6152, 0x017f, 0x6027, 0x0008, 0x0078, 0x247c, 0x1078, 0x250d,
+	0x00f0, 0x243f, 0x157f, 0x6152, 0x017f, 0x6027, 0x0008, 0x017e,
+	0x6028, 0xc09c, 0x602a, 0x2011, 0x0003, 0x1078, 0x6ef2, 0x2011,
+	0x0002, 0x1078, 0x6efc, 0x1078, 0x6dda, 0x1078, 0x595a, 0x037e,
+	0x2019, 0x0000, 0x1078, 0x6e6c, 0x037f, 0x60e3, 0x0000, 0x1078,
+	0xa22a, 0x1078, 0xa248, 0x2001, 0xa300, 0x2003, 0x0004, 0x6027,
+	0x0008, 0x1078, 0x1246, 0x017f, 0xa18c, 0xffd0, 0x6126, 0x007c,
+	0x007e, 0x017e, 0x027e, 0x0e7e, 0x0f7e, 0x127e, 0x2091, 0x8000,
+	0x2071, 0xa300, 0x71b8, 0x70ba, 0xa116, 0x0040, 0x24ae, 0x81ff,
+	0x0040, 0x2498, 0x2011, 0x8011, 0x1078, 0x3579, 0x0078, 0x24ae,
+	0x2011, 0x8012, 0x1078, 0x3579, 0x2001, 0xa371, 0x2004, 0xd0fc,
+	0x00c0, 0x24ae, 0x037e, 0x0c7e, 0x2061, 0x0100, 0x2019, 0x0028,
+	0x2009, 0x0000, 0x1078, 0x27e2, 0x0c7f, 0x037f, 0x127f, 0x0f7f,
+	0x0e7f, 0x027f, 0x017f, 0x007f, 0x007c, 0x0c7e, 0x0f7e, 0x007e,
+	0x027e, 0x2061, 0x0100, 0xa190, 0x24d1, 0x2204, 0x60f2, 0x2011,
+	0x24de, 0x6000, 0xa082, 0x0003, 0x00c8, 0x24ca, 0x2001, 0x00ff,
+	0x0078, 0x24cb, 0x2204, 0x60ee, 0x027f, 0x007f, 0x0f7f, 0x0c7f,
+	0x007c, 0x0840, 0x0840, 0x0840, 0x0580, 0x0420, 0x0348, 0x02c0,
+	0x0258, 0x0210, 0x01a8, 0x01a8, 0x01a8, 0x01a8, 0x0140, 0x00f8,
+	0x00d0, 0x00b0, 0x00a0, 0x2028, 0xa18c, 0x00ff, 0x2130, 0xa094,
+	0xff00, 0x00c0, 0x24ee, 0x81ff, 0x0040, 0x24f2, 0x1078, 0x5623,
+	0x0078, 0x24f9, 0xa080, 0x293f, 0x200c, 0xa18c, 0xff00, 0x810f,
+	0xa006, 0x007c, 0xa080, 0x293f, 0x200c, 0xa18c, 0x00ff, 0x007c,
+	0x0c7e, 0x2061, 0xa300, 0x6030, 0x0040, 0x2509, 0xc09d, 0x0078,
+	0x250a, 0xc09c, 0x6032, 0x0c7f, 0x007c, 0x007e, 0x157e, 0x0f7e,
+	0x2079, 0x0100, 0x20a9, 0x000a, 0x7854, 0xd08c, 0x00c0, 0x251a,
+	0x00f0, 0x2514, 0x0f7f, 0x157f, 0x007f, 0x007c, 0x0c7e, 0x007e,
+	0x2061, 0x0100, 0x6030, 0x007e, 0x6048, 0x007e, 0x60e4, 0x007e,
+	0x60e8, 0x007e, 0x6050, 0x007e, 0x60f0, 0x007e, 0x60ec, 0x007e,
+	0x600c, 0x007e, 0x6004, 0x007e, 0x6028, 0x007e, 0x60e0, 0x007e,
+	0x602f, 0x0100, 0x602f, 0x0000, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x602f, 0x0040, 0x602f, 0x0000, 0x007f, 0x60e2, 0x007f, 0x602a,
+	0x007f, 0x6006, 0x007f, 0x600e, 0x007f, 0x60ee, 0x007f, 0x60f2,
+	0x007f, 0x6052, 0x007f, 0x60ea, 0x007f, 0x60e6, 0x007f, 0x604a,
+	0x007f, 0x6032, 0x007f, 0x0c7f, 0x007c, 0x257d, 0x2581, 0x2585,
+	0x258b, 0x2591, 0x2597, 0x259d, 0x25a5, 0x25ad, 0x25b3, 0x25b9,
+	0x25c1, 0x25c9, 0x25d1, 0x25d9, 0x25e3, 0x25ed, 0x25ed, 0x25ed,
+	0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x25ed,
+	0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x25ed, 0x107e, 0x007e, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078,
+	0x2200, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078, 0x2200, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x20de, 0x0078, 0x2606, 0x107e,
+	0x007e, 0x1078, 0x20de, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078,
+	0x2200, 0x1078, 0x20de, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078,
+	0x2200, 0x1078, 0x20de, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078,
+	0x2123, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078, 0x2123, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x2200, 0x1078, 0x2123, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x2200, 0x1078, 0x2123, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x20de, 0x1078, 0x2123, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x20de, 0x1078, 0x2123, 0x0078,
+	0x2606, 0x107e, 0x007e, 0x1078, 0x2200, 0x1078, 0x20de, 0x1078,
+	0x2123, 0x0078, 0x2606, 0x107e, 0x007e, 0x1078, 0x2200, 0x1078,
+	0x20de, 0x1078, 0x2123, 0x0078, 0x2606, 0x0005, 0x0078, 0x25ed,
+	0xb084, 0x003c, 0x8004, 0x8004, 0x0079, 0x25f6, 0x2606, 0x2583,
+	0x2587, 0x258d, 0x2593, 0x2599, 0x259f, 0x25a7, 0x25af, 0x25b5,
+	0x25bb, 0x25c3, 0x25cb, 0x25d3, 0x25db, 0x25e5, 0x0008, 0x25f0,
+	0x007f, 0x107f, 0x2091, 0x8001, 0x007c, 0x0c7e, 0x027e, 0x047e,
+	0x2021, 0x0000, 0x1078, 0x4897, 0x00c0, 0x2705, 0x70c8, 0xd09c,
+	0x0040, 0x2624, 0xd084, 0x00c0, 0x2624, 0xd0bc, 0x00c0, 0x2705,
+	0x1078, 0x2709, 0x0078, 0x2705, 0xd094, 0x0040, 0x262b, 0x7093,
+	0xffff, 0x0078, 0x2705, 0x2001, 0x010c, 0x203c, 0x7280, 0xd284,
+	0x0040, 0x2694, 0xd28c, 0x00c0, 0x2694, 0x037e, 0x7390, 0xa38e,
+	0xffff, 0x0040, 0x263e, 0x83ff, 0x00c0, 0x2640, 0x2019, 0x0001,
+	0x8314, 0xa2e0, 0xa9c0, 0x2c04, 0xa38c, 0x0001, 0x0040, 0x264d,
+	0xa084, 0xff00, 0x8007, 0x0078, 0x264f, 0xa084, 0x00ff, 0xa70e,
+	0x0040, 0x2689, 0xa08e, 0x0000, 0x0040, 0x2689, 0xa08e, 0x00ff,
+	0x00c0, 0x2666, 0x7230, 0xd284, 0x00c0, 0x268f, 0x7280, 0xc28d,
+	0x7282, 0x7093, 0xffff, 0x037f, 0x0078, 0x2694, 0x2009, 0x0000,
+	0x1078, 0x24e3, 0x1078, 0x4499, 0x00c0, 0x268c, 0x6004, 0xa084,
+	0x00ff, 0xa086, 0x0006, 0x00c0, 0x2683, 0x7030, 0xd08c, 0x0040,
+	0x267d, 0x6000, 0xd0bc, 0x0040, 0x2683, 0x1078, 0x271f, 0x0040,
+	0x268c, 0x0078, 0x2689, 0x1078, 0x2857, 0x1078, 0x274c, 0x0040,
+	0x268c, 0x8318, 0x0078, 0x2640, 0x7392, 0x0078, 0x2691, 0x7093,
+	0xffff, 0x037f, 0x0078, 0x2705, 0xa780, 0x293f, 0x203c, 0xa7bc,
+	0xff00, 0x873f, 0x2041, 0x007e, 0x7090, 0xa096, 0xffff, 0x00c0,
+	0x26a6, 0x2009, 0x0000, 0x28a8, 0x0078, 0x26b2, 0xa812, 0x0048,
+	0x26ae, 0x2008, 0xa802, 0x20a8, 0x0078, 0x26b2, 0x7093, 0xffff,
+	0x0078, 0x2705, 0x2700, 0x157e, 0x017e, 0xa106, 0x0040, 0x26f9,
+	0xc484, 0x1078, 0x4501, 0x0040, 0x26c3, 0x1078, 0x4499, 0x00c0,
+	0x2702, 0x0078, 0x26c4, 0xc485, 0x6004, 0xa084, 0x00ff, 0xa086,
+	0x0006, 0x00c0, 0x26d3, 0x7030, 0xd08c, 0x0040, 0x26f1, 0x6000,
+	0xd0bc, 0x00c0, 0x26f1, 0x7280, 0xd28c, 0x0040, 0x26e9, 0x6004,
+	0xa084, 0x00ff, 0xa082, 0x0006, 0x0048, 0x26f9, 0xd484, 0x00c0,
+	0x26e5, 0x1078, 0x44bc, 0x0078, 0x26e7, 0x1078, 0x2921, 0x0078,
+	0x26f9, 0x1078, 0x2857, 0x1078, 0x274c, 0x0040, 0x2702, 0x0078,
+	0x26f9, 0x1078, 0x28ec, 0x0040, 0x26f9, 0x1078, 0x271f, 0x0040,
+	0x2702, 0x017f, 0x8108, 0x157f, 0x00f0, 0x26b2, 0x7093, 0xffff,
+	0x0078, 0x2705, 0x017f, 0x157f, 0x7192, 0x047f, 0x027f, 0x0c7f,
+	0x007c, 0x0c7e, 0x017e, 0x7093, 0x0000, 0x2009, 0x007e, 0x1078,
+	0x4499, 0x00c0, 0x271c, 0x1078, 0x2857, 0x1078, 0x274c, 0x0040,
+	0x271c, 0x70c8, 0xc0bd, 0x70ca, 0x017f, 0x0c7f, 0x007c, 0x017e,
+	0x077e, 0x0d7e, 0x0c7e, 0x2c68, 0x2001, 0xa356, 0x2004, 0xa084,
+	0x00ff, 0x6842, 0x1078, 0x74d7, 0x0040, 0x2747, 0x2d00, 0x601a,
+	0x601f, 0x0001, 0x2001, 0x0000, 0x1078, 0x442b, 0x2001, 0x0000,
+	0x1078, 0x443f, 0x127e, 0x2091, 0x8000, 0x708c, 0x8000, 0x708e,
+	0x127f, 0x2009, 0x0004, 0x1078, 0x756c, 0xa085, 0x0001, 0x0c7f,
+	0x0d7f, 0x077f, 0x017f, 0x007c, 0x017e, 0x077e, 0x0d7e, 0x0c7e,
+	0x2c68, 0x2001, 0xa356, 0x2004, 0xa084, 0x00ff, 0x6842, 0x1078,
+	0x74d7, 0x0040, 0x2785, 0x2d00, 0x601a, 0x6800, 0xc0c4, 0x6802,
+	0x68a0, 0xa086, 0x007e, 0x0040, 0x276e, 0x6804, 0xa084, 0x00ff,
+	0xa086, 0x0006, 0x00c0, 0x276e, 0x1078, 0x2813, 0x601f, 0x0001,
+	0x2001, 0x0000, 0x1078, 0x442b, 0x2001, 0x0002, 0x1078, 0x443f,
+	0x127e, 0x2091, 0x8000, 0x708c, 0x8000, 0x708e, 0x127f, 0x2009,
+	0x0002, 0x1078, 0x756c, 0xa085, 0x0001, 0x0c7f, 0x0d7f, 0x077f,
+	0x017f, 0x007c, 0x0c7e, 0x027e, 0x2009, 0x0080, 0x1078, 0x4499,
+	0x00c0, 0x2798, 0x1078, 0x279b, 0x0040, 0x2798, 0x70cf, 0xffff,
+	0x027f, 0x0c7f, 0x007c, 0x017e, 0x077e, 0x0d7e, 0x0c7e, 0x2c68,
+	0x1078, 0x74d7, 0x0040, 0x27bd, 0x2d00, 0x601a, 0x601f, 0x0001,
+	0x2001, 0x0000, 0x1078, 0x442b, 0x2001, 0x0002, 0x1078, 0x443f,
+	0x127e, 0x2091, 0x8000, 0x70d0, 0x8000, 0x70d2, 0x127f, 0x2009,
+	0x0002, 0x1078, 0x756c, 0xa085, 0x0001, 0x0c7f, 0x0d7f, 0x077f,
+	0x017f, 0x007c, 0x0c7e, 0x0d7e, 0x127e, 0x2091, 0x8000, 0x2009,
+	0x007f, 0x1078, 0x4499, 0x00c0, 0x27de, 0x2c68, 0x1078, 0x74d7,
+	0x0040, 0x27de, 0x2d00, 0x601a, 0x6312, 0x601f, 0x0001, 0x620a,
+	0x2009, 0x0022, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f, 0x0d7f,
+	0x0c7f, 0x007c, 0x0e7e, 0x0c7e, 0x067e, 0x037e, 0x027e, 0x1078,
+	0x5d60, 0x1078, 0x5d02, 0x1078, 0x7ddf, 0x2130, 0x81ff, 0x0040,
+	0x27f7, 0x20a9, 0x007e, 0x2009, 0x0000, 0x0078, 0x27fb, 0x20a9,
+	0x007f, 0x2009, 0x0000, 0x017e, 0x1078, 0x4501, 0x00c0, 0x2804,
+	0x1078, 0x471b, 0x1078, 0x4235, 0x017f, 0x8108, 0x00f0, 0x27fb,
+	0x86ff, 0x00c0, 0x280d, 0x1078, 0x119b, 0x027f, 0x037f, 0x067f,
+	0x0c7f, 0x0e7f, 0x007c, 0x0e7e, 0x0c7e, 0x037e, 0x027e, 0x017e,
+	0x6218, 0x2270, 0x72a0, 0x027e, 0x2019, 0x0029, 0x1078, 0x5d53,
+	0x077e, 0x2039, 0x0000, 0x1078, 0x5c78, 0x2c08, 0x1078, 0x9c38,
+	0x077f, 0x017f, 0x2e60, 0x1078, 0x471b, 0x6210, 0x6314, 0x1078,
+	0x4235, 0x6212, 0x6316, 0x017f, 0x027f, 0x037f, 0x0c7f, 0x0e7f,
+	0x007c, 0x0e7e, 0x007e, 0x6018, 0xa080, 0x0028, 0x2004, 0xd0bc,
+	0x00c0, 0x284d, 0x2071, 0xa300, 0x708c, 0xa005, 0x0040, 0x284a,
+	0x8001, 0x708e, 0x007f, 0x0e7f, 0x007c, 0x2071, 0xa300, 0x70d0,
+	0xa005, 0x0040, 0x284a, 0x8001, 0x70d2, 0x0078, 0x284a, 0x6000,
+	0xc08c, 0x6002, 0x007c, 0x0f7e, 0x0e7e, 0x0c7e, 0x037e, 0x027e,
+	0x017e, 0x157e, 0x2178, 0x81ff, 0x00c0, 0x286a, 0x20a9, 0x0001,
+	0x0078, 0x2885, 0x2001, 0xa352, 0x2004, 0xd0c4, 0x0040, 0x2881,
+	0xd0a4, 0x0040, 0x2881, 0x047e, 0x6018, 0xa080, 0x0028, 0x2024,
+	0xa4a4, 0x00ff, 0x8427, 0xa006, 0x2009, 0x002d, 0x1078, 0x9ec0,
+	0x047f, 0x20a9, 0x00ff, 0x2011, 0x0000, 0x027e, 0xa28e, 0x007e,
+	0x0040, 0x28c9, 0xa28e, 0x007f, 0x0040, 0x28c9, 0xa28e, 0x0080,
+	0x0040, 0x28c9, 0xa288, 0xa434, 0x210c, 0x81ff, 0x0040, 0x28c9,
+	0x8fff, 0x1040, 0x28d5, 0x0c7e, 0x2160, 0x2001, 0x0001, 0x1078,
+	0x48a2, 0x0c7f, 0x2019, 0x0029, 0x1078, 0x5d53, 0x077e, 0x2039,
+	0x0000, 0x1078, 0x5c78, 0x0c7e, 0x027e, 0x2160, 0x6204, 0xa294,
+	0x00ff, 0xa286, 0x0006, 0x00c0, 0x28b9, 0x6007, 0x0404, 0x0078,
+	0x28be, 0x2001, 0x0004, 0x8007, 0xa215, 0x6206, 0x027f, 0x0c7f,
+	0x017e, 0x2c08, 0x1078, 0x9c38, 0x017f, 0x077f, 0x2160, 0x1078,
+	0x471b, 0x027f, 0x8210, 0x00f0, 0x2885, 0x157f, 0x017f, 0x027f,
+	0x037f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c, 0x047e, 0x027e, 0x017e,
+	0x2001, 0xa352, 0x2004, 0xd0c4, 0x0040, 0x28e8, 0xd0a4, 0x0040,
+	0x28e8, 0xa006, 0x2220, 0x8427, 0x2009, 0x0029, 0x1078, 0x9ec0,
+	0x017f, 0x027f, 0x047f, 0x007c, 0x017e, 0x027e, 0x037e, 0x0c7e,
+	0x7280, 0x82ff, 0x0040, 0x291a, 0xa290, 0xa352, 0x2214, 0xd2ac,
+	0x00c0, 0x291a, 0x2100, 0x1078, 0x24fa, 0x81ff, 0x0040, 0x291c,
+	0x2019, 0x0001, 0x8314, 0xa2e0, 0xa9c0, 0x2c04, 0xd384, 0x0040,
+	0x290e, 0xa084, 0xff00, 0x8007, 0x0078, 0x2910, 0xa084, 0x00ff,
+	0xa116, 0x0040, 0x291c, 0xa096, 0x00ff, 0x0040, 0x291a, 0x8318,
+	0x0078, 0x2902, 0xa085, 0x0001, 0x0c7f, 0x037f, 0x027f, 0x017f,
+	0x007c, 0x017e, 0x0c7e, 0x127e, 0x2091, 0x8000, 0xa180, 0xa434,
+	0x2004, 0xa065, 0x0040, 0x293b, 0x017e, 0x0c7e, 0x1078, 0x8ec0,
+	0x017f, 0x1040, 0x1328, 0x611a, 0x1078, 0x2813, 0x1078, 0x753d,
+	0x017f, 0x1078, 0x44bc, 0x127f, 0x0c7f, 0x017f, 0x007c, 0x7eef,
+	0x7de8, 0x7ce4, 0x80e2, 0x7be1, 0x80e0, 0x80dc, 0x80da, 0x7ad9,
+	0x80d6, 0x80d5, 0x80d4, 0x80d3, 0x80d2, 0x80d1, 0x79ce, 0x78cd,
+	0x80cc, 0x80cb, 0x80ca, 0x80c9, 0x80c7, 0x80c6, 0x77c5, 0x76c3,
+	0x80bc, 0x80ba, 0x75b9, 0x80b6, 0x74b5, 0x73b4, 0x72b3, 0x80b2,
+	0x80b1, 0x80ae, 0x71ad, 0x80ac, 0x70ab, 0x6faa, 0x6ea9, 0x80a7,
+	0x6da6, 0x6ca5, 0x6ba3, 0x6a9f, 0x699e, 0x689d, 0x809b, 0x8098,
+	0x6797, 0x6690, 0x658f, 0x6488, 0x6384, 0x6282, 0x8081, 0x8080,
+	0x617c, 0x607a, 0x8079, 0x5f76, 0x8075, 0x8074, 0x8073, 0x8072,
+	0x8071, 0x806e, 0x5e6d, 0x806c, 0x5d6b, 0x5c6a, 0x5b69, 0x8067,
+	0x5a66, 0x5965, 0x5863, 0x575c, 0x565a, 0x5559, 0x8056, 0x8055,
+	0x5454, 0x5353, 0x5252, 0x5151, 0x504e, 0x4f4d, 0x804c, 0x804b,
+	0x4e4a, 0x4d49, 0x8047, 0x4c46, 0x8045, 0x8043, 0x803c, 0x803a,
+	0x8039, 0x8036, 0x4b35, 0x8034, 0x4a33, 0x4932, 0x4831, 0x802e,
+	0x472d, 0x462c, 0x452b, 0x442a, 0x4329, 0x4227, 0x8026, 0x8025,
+	0x4123, 0x401f, 0x3f1e, 0x3e1d, 0x3d1b, 0x3c18, 0x8017, 0x8010,
+	0x3b0f, 0x3a08, 0x8004, 0x3902, 0x8001, 0x8000, 0x8000, 0x3800,
+	0x3700, 0x3600, 0x8000, 0x3500, 0x8000, 0x8000, 0x8000, 0x3400,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x3300, 0x3200,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x3100, 0x3000,
+	0x8000, 0x8000, 0x2f00, 0x8000, 0x2e00, 0x2d00, 0x2c00, 0x8000,
+	0x8000, 0x8000, 0x2b00, 0x8000, 0x2a00, 0x2900, 0x2800, 0x8000,
+	0x2700, 0x2600, 0x2500, 0x2400, 0x2300, 0x2200, 0x8000, 0x8000,
+	0x2100, 0x2000, 0x1f00, 0x1e00, 0x1d00, 0x1c00, 0x8000, 0x8000,
+	0x1b00, 0x1a00, 0x8000, 0x1900, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x1800, 0x8000, 0x1700, 0x1600, 0x1500, 0x8000,
+	0x1400, 0x1300, 0x1200, 0x1100, 0x1000, 0x0f00, 0x8000, 0x8000,
+	0x0e00, 0x0d00, 0x0c00, 0x0b00, 0x0a00, 0x0900, 0x8000, 0x8000,
+	0x0800, 0x0700, 0x8000, 0x0600, 0x8000, 0x8000, 0x8000, 0x0500,
+	0x0400, 0x0300, 0x8000, 0x0200, 0x8000, 0x8000, 0x8000, 0x0100,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x0000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x2071,
+	0xa381, 0x7003, 0x0002, 0xa006, 0x7012, 0x7016, 0x703a, 0x703e,
+	0x7033, 0xa391, 0x7037, 0xa391, 0x7007, 0x0001, 0x2061, 0xa3d1,
+	0x6003, 0x0002, 0x007c, 0x0090, 0x2a66, 0x0068, 0x2a66, 0x2071,
+	0xa381, 0x2b78, 0x7818, 0xd084, 0x00c0, 0x2a66, 0x2a60, 0x7820,
+	0xa08e, 0x0069, 0x00c0, 0x2b56, 0x0079, 0x2aea, 0x007c, 0x2071,
+	0xa381, 0x7004, 0x0079, 0x2a6c, 0x2a70, 0x2a71, 0x2a7b, 0x2a8d,
+	0x007c, 0x0090, 0x2a7a, 0x0068, 0x2a7a, 0x2b78, 0x7818, 0xd084,
+	0x0040, 0x2a99, 0x007c, 0x2b78, 0x2061, 0xa3d1, 0x6008, 0xa08e,
+	0x0100, 0x0040, 0x2a88, 0xa086, 0x0200, 0x0040, 0x2b4e, 0x007c,
+	0x7014, 0x2068, 0x2a60, 0x7018, 0x007a, 0x7010, 0x2068, 0x6834,
+	0xa086, 0x0103, 0x0040, 0x2a95, 0x007c, 0x2a60, 0x2b78, 0x7018,
+	0x007a, 0x2a60, 0x7820, 0xa08a, 0x0040, 0x00c8, 0x2aa2, 0x61b8,
+	0x0079, 0x2aaa, 0x2100, 0xa08a, 0x003f, 0x00c8, 0x2b4a, 0x61b8,
+	0x0079, 0x2aea, 0x2b2c, 0x2b5e, 0x2b66, 0x2b6a, 0x2b72, 0x2b78,
+	0x2b7c, 0x2b88, 0x2b8c, 0x2b96, 0x2b9a, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b9e, 0x2b4a, 0x2bae, 0x2bc5, 0x2bdc, 0x2c58, 0x2c5d, 0x2c8a,
+	0x2ce4, 0x2cf5, 0x2d13, 0x2d54, 0x2d5e, 0x2d6b, 0x2d7e, 0x2d9d,
+	0x2da6, 0x2de3, 0x2de9, 0x2b4a, 0x2e05, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2e0c, 0x2e16, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2e1e, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2e30, 0x2e47, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2e59, 0x2eb0, 0x2f0e, 0x2f1f, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x38f1, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2b96, 0x2b9a, 0x2f36, 0x2b4a, 0x2f43, 0x397d,
+	0x39da, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a,
+	0x2b4a, 0x2b4a, 0x2f90, 0x30c5, 0x30e1, 0x30ed, 0x3150, 0x31a9,
+	0x31b4, 0x31f3, 0x3202, 0x3211, 0x3214, 0x2f47, 0x3238, 0x3284,
+	0x3291, 0x33a2, 0x34cd, 0x34f7, 0x3604, 0x3614, 0x3621, 0x365b,
+	0x372a, 0x2b4a, 0x2b4a, 0x2b4a, 0x2b4a, 0x3792, 0x37ae, 0x3828,
+	0x38e2, 0x713c, 0x0078, 0x2b2c, 0x2021, 0x4000, 0x1078, 0x3553,
+	0x127e, 0x2091, 0x8000, 0x0068, 0x2b39, 0x7818, 0xd084, 0x0040,
+	0x2b3c, 0x127f, 0x0078, 0x2b30, 0x7c22, 0x7926, 0x7a2a, 0x7b2e,
+	0x781b, 0x0001, 0x2091, 0x4080, 0x7007, 0x0001, 0x2091, 0x5000,
+	0x127f, 0x007c, 0x2021, 0x4001, 0x0078, 0x2b2e, 0x2021, 0x4002,
+	0x0078, 0x2b2e, 0x2021, 0x4003, 0x0078, 0x2b2e, 0x2021, 0x4005,
+	0x0078, 0x2b2e, 0x2021, 0x4006, 0x0078, 0x2b2e, 0xa02e, 0x2520,
+	0x7b28, 0x7a2c, 0x7824, 0x7930, 0x0078, 0x3562, 0x7823, 0x0004,
+	0x7824, 0x007a, 0xa02e, 0x2520, 0x7b28, 0x7a2c, 0x7824, 0x7930,
+	0x0078, 0x3566, 0x7924, 0x7828, 0x2114, 0x200a, 0x0078, 0x2b2c,
+	0x7924, 0x2114, 0x0078, 0x2b2c, 0x2099, 0x0009, 0x20a1, 0x0009,
+	0x20a9, 0x0007, 0x53a3, 0x7924, 0x7a28, 0x7b2c, 0x0078, 0x2b2c,
+	0x7824, 0x2060, 0x0078, 0x2ba0, 0x2009, 0x0001, 0x2011, 0x0013,
+	0x2019, 0x0010, 0x783b, 0x0017, 0x0078, 0x2b2c, 0x7d38, 0x7c3c,
+	0x0078, 0x2b60, 0x7d38, 0x7c3c, 0x0078, 0x2b6c, 0x2061, 0x1000,
+	0x610c, 0xa006, 0x2c14, 0xa200, 0x8c60, 0x8109, 0x00c0, 0x2ba2,
+	0x2010, 0xa005, 0x0040, 0x2b2c, 0x0078, 0x2b52, 0x2069, 0xa351,
+	0x7824, 0x7930, 0xa11a, 0x00c8, 0x2b5a, 0x8019, 0x0040, 0x2b5a,
+	0x684a, 0x6942, 0x782c, 0x6852, 0x7828, 0x6856, 0xa006, 0x685a,
+	0x685e, 0x1078, 0x4dbd, 0x0078, 0x2b2c, 0x2069, 0xa351, 0x7824,
+	0x7934, 0xa11a, 0x00c8, 0x2b5a, 0x8019, 0x0040, 0x2b5a, 0x684e,
+	0x6946, 0x782c, 0x6862, 0x7828, 0x6866, 0xa006, 0x686a, 0x686e,
+	0x1078, 0x494d, 0x0078, 0x2b2c, 0xa02e, 0x2520, 0x81ff, 0x00c0,
+	0x2b56, 0x7924, 0x7b28, 0x7a2c, 0x20a9, 0x0005, 0x20a1, 0xa388,
+	0x41a1, 0x1078, 0x3518, 0x0040, 0x2b56, 0x2009, 0x0020, 0x1078,
+	0x3562, 0x701b, 0x2bf4, 0x007c, 0x6834, 0x2008, 0xa084, 0x00ff,
+	0xa096, 0x0011, 0x0040, 0x2c00, 0xa096, 0x0019, 0x00c0, 0x2b56,
+	0x810f, 0xa18c, 0x00ff, 0x0040, 0x2b56, 0x710e, 0x700c, 0x8001,
+	0x0040, 0x2c31, 0x700e, 0x1078, 0x3518, 0x0040, 0x2b56, 0x2009,
+	0x0020, 0x2061, 0xa3d1, 0x6224, 0x6328, 0x642c, 0x6530, 0xa290,
+	0x0040, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0x1078,
+	0x3562, 0x701b, 0x2c24, 0x007c, 0x6834, 0xa084, 0x00ff, 0xa096,
+	0x0002, 0x0040, 0x2c2f, 0xa096, 0x000a, 0x00c0, 0x2b56, 0x0078,
+	0x2c06, 0x7010, 0x2068, 0x6838, 0xc0fd, 0x683a, 0x1078, 0x436e,
+	0x00c0, 0x2c3f, 0x7007, 0x0003, 0x701b, 0x2c41, 0x007c, 0x1078,
+	0x4a60, 0x127e, 0x2091, 0x8000, 0x20a9, 0x0005, 0x2099, 0xa388,
+	0x530a, 0x2100, 0xa210, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9,
+	0x0000, 0xad80, 0x000d, 0x2009, 0x0020, 0x127f, 0x0078, 0x3566,
+	0x61a0, 0x7824, 0x60a2, 0x0078, 0x2b2c, 0x2091, 0x8000, 0x7823,
+	0x4000, 0x7827, 0x4953, 0x782b, 0x5020, 0x782f, 0x2020, 0x2009,
+	0x017f, 0x2104, 0x7832, 0x3f00, 0x7836, 0x2061, 0x0100, 0x6200,
+	0x2061, 0x0200, 0x603c, 0x8007, 0xa205, 0x783a, 0x2009, 0x04fd,
+	0x2104, 0x783e, 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080,
+	0x2071, 0x0010, 0x20c1, 0x00f0, 0xa08a, 0x0003, 0x00c8, 0x0427,
+	0x0078, 0x0423, 0x81ff, 0x00c0, 0x2b56, 0x7924, 0x810f, 0xa18c,
+	0x00ff, 0x1078, 0x4501, 0x00c0, 0x2b5a, 0x7e38, 0xa684, 0x3fff,
+	0xa082, 0x4000, 0x0048, 0x2c9e, 0x0078, 0x2b5a, 0x7c28, 0x7d2c,
+	0x1078, 0x46d6, 0xd28c, 0x00c0, 0x2ca9, 0x1078, 0x466a, 0x0078,
+	0x2cab, 0x1078, 0x46a4, 0x00c0, 0x2cd5, 0x2061, 0xaa00, 0x127e,
+	0x2091, 0x8000, 0x6000, 0xa086, 0x0000, 0x0040, 0x2cc3, 0x6010,
+	0xa06d, 0x0040, 0x2cc3, 0x683c, 0xa406, 0x00c0, 0x2cc3, 0x6840,
+	0xa506, 0x0040, 0x2cce, 0x127f, 0xace0, 0x0010, 0x2001, 0xa315,
+	0x2004, 0xac02, 0x00c8, 0x2b56, 0x0078, 0x2caf, 0x1078, 0x8758,
+	0x127f, 0x0040, 0x2b56, 0x0078, 0x2b2c, 0xa00e, 0x2001, 0x0005,
+	0x1078, 0x4a60, 0x127e, 0x2091, 0x8000, 0x1078, 0x8cc0, 0x1078,
+	0x4982, 0x127f, 0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56, 0x1078,
+	0x3530, 0x0040, 0x2b5a, 0x1078, 0x45a7, 0x0040, 0x2b56, 0x1078,
+	0x46e4, 0x0040, 0x2b56, 0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56,
+	0x1078, 0x3542, 0x0040, 0x2b5a, 0x1078, 0x475f, 0x0040, 0x2b56,
+	0x2019, 0x0005, 0x1078, 0x4705, 0x0040, 0x2b56, 0x7828, 0xa08a,
+	0x1000, 0x00c8, 0x2b5a, 0x8003, 0x800b, 0x810b, 0xa108, 0x1078,
+	0x58e1, 0x0078, 0x2b2c, 0x127e, 0x2091, 0x8000, 0x81ff, 0x0040,
+	0x2d1d, 0x2009, 0x0001, 0x0078, 0x2d4e, 0x2029, 0x00ff, 0x644c,
+	0x2400, 0xa506, 0x0040, 0x2d48, 0x2508, 0x1078, 0x4501, 0x00c0,
+	0x2d48, 0x1078, 0x475f, 0x00c0, 0x2d33, 0x2009, 0x0002, 0x62a8,
+	0x2518, 0x0078, 0x2d4e, 0x2019, 0x0004, 0x1078, 0x4705, 0x00c0,
+	0x2d3d, 0x2009, 0x0006, 0x0078, 0x2d4e, 0x7824, 0xa08a, 0x1000,
+	0x00c8, 0x2d51, 0x8003, 0x800b, 0x810b, 0xa108, 0x1078, 0x58e1,
+	0x8529, 0x00c8, 0x2d20, 0x127f, 0x0078, 0x2b2c, 0x127f, 0x0078,
+	0x2b56, 0x127f, 0x0078, 0x2b5a, 0x1078, 0x3530, 0x0040, 0x2b5a,
+	0x1078, 0x461b, 0x1078, 0x46d6, 0x0078, 0x2b2c, 0x81ff, 0x00c0,
+	0x2b56, 0x1078, 0x3530, 0x0040, 0x2b5a, 0x1078, 0x460a, 0x1078,
+	0x46d6, 0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x3530,
+	0x0040, 0x2b5a, 0x1078, 0x46a7, 0x0040, 0x2b56, 0x1078, 0x43c1,
+	0x1078, 0x4663, 0x1078, 0x46d6, 0x0078, 0x2b2c, 0x1078, 0x3530,
+	0x0040, 0x2b5a, 0x1078, 0x45a7, 0x0040, 0x2b56, 0x62a0, 0x2019,
+	0x0005, 0x0c7e, 0x1078, 0x471b, 0x0c7f, 0x1078, 0x5d53, 0x077e,
+	0x2039, 0x0000, 0x1078, 0x5c78, 0x2009, 0x0000, 0x1078, 0x9c38,
+	0x077f, 0x1078, 0x46d6, 0x0078, 0x2b2c, 0x1078, 0x3530, 0x0040,
+	0x2b5a, 0x1078, 0x46d6, 0x2208, 0x0078, 0x2b2c, 0x157e, 0x0d7e,
+	0x0e7e, 0x2069, 0xa413, 0x6810, 0x6914, 0xa10a, 0x00c8, 0x2db2,
+	0x2009, 0x0000, 0x6816, 0x2011, 0x0000, 0x2019, 0x0000, 0x20a9,
+	0x00ff, 0x2069, 0xa434, 0x2d04, 0xa075, 0x0040, 0x2dc7, 0x704c,
+	0x1078, 0x2dd1, 0xa210, 0x7080, 0x1078, 0x2dd1, 0xa318, 0x8d68,
+	0x00f0, 0x2dbb, 0x2300, 0xa218, 0x0e7f, 0x0d7f, 0x157f, 0x0078,
+	0x2b2c, 0x0f7e, 0x017e, 0xa07d, 0x0040, 0x2de0, 0x2001, 0x0000,
+	0x8000, 0x2f0c, 0x81ff, 0x0040, 0x2de0, 0x2178, 0x0078, 0x2dd8,
+	0x017f, 0x0f7f, 0x007c, 0x2069, 0xa413, 0x6910, 0x62a4, 0x0078,
+	0x2b2c, 0x81ff, 0x00c0, 0x2b56, 0x614c, 0xa190, 0x293f, 0x2214,
+	0xa294, 0x00ff, 0x606c, 0xa084, 0xff00, 0xa215, 0x6368, 0x67c8,
+	0xd79c, 0x0040, 0x2dff, 0x2031, 0x0001, 0x0078, 0x2e01, 0x2031,
+	0x0000, 0x7e3a, 0x7f3e, 0x0078, 0x2b2c, 0x613c, 0x6240, 0x2019,
+	0xa5a0, 0x231c, 0x0078, 0x2b2c, 0x127e, 0x2091, 0x8000, 0x6134,
+	0xa006, 0x2010, 0x2018, 0x127f, 0x0078, 0x2b2c, 0x1078, 0x3542,
+	0x0040, 0x2b5a, 0x6244, 0x6338, 0x0078, 0x2b2c, 0x613c, 0x6240,
+	0x7824, 0x603e, 0x7b28, 0x6342, 0x2069, 0xa351, 0x831f, 0xa305,
+	0x6816, 0x782c, 0x2069, 0xa5a0, 0x2d1c, 0x206a, 0x0078, 0x2b2c,
+	0x017e, 0x127e, 0x2091, 0x8000, 0x7824, 0x6036, 0xd094, 0x0040,
+	0x2e43, 0x7828, 0xa085, 0x0001, 0x2009, 0xa5a9, 0x200a, 0x2001,
+	0xffff, 0x1078, 0x5975, 0x127f, 0x017f, 0x0078, 0x2b2c, 0x1078,
+	0x3542, 0x0040, 0x2b5a, 0x7828, 0xa00d, 0x0040, 0x2b5a, 0x782c,
+	0xa005, 0x0040, 0x2b5a, 0x6244, 0x6146, 0x6338, 0x603a, 0x0078,
+	0x2b2c, 0x2001, 0xa300, 0x2004, 0xa086, 0x0003, 0x00c0, 0x2b56,
+	0x0c7e, 0x2061, 0x0100, 0x7924, 0x810f, 0xa18c, 0x00ff, 0xa196,
+	0x00ff, 0x00c0, 0x2e70, 0x6030, 0xa085, 0xff00, 0x0078, 0x2e7f,
+	0xa182, 0x007f, 0x00c8, 0x2ea9, 0xa188, 0x293f, 0x210c, 0xa18c,
+	0x00ff, 0x6030, 0xa116, 0x0040, 0x2ea9, 0x810f, 0xa105, 0x127e,
+	0x2091, 0x8000, 0x007e, 0x1078, 0x74d7, 0x007f, 0x0040, 0x2ea5,
+	0x601a, 0x600b, 0xbc09, 0x601f, 0x0001, 0x1078, 0x3518, 0x0040,
+	0x2eac, 0x6837, 0x0000, 0x7007, 0x0003, 0x6833, 0x0000, 0x6838,
+	0xc0fd, 0x683a, 0x701b, 0x2f07, 0x2d00, 0x6012, 0x2009, 0x0032,
+	0x1078, 0x756c, 0x127f, 0x0c7f, 0x007c, 0x127f, 0x0c7f, 0x0078,
+	0x2b56, 0x0c7f, 0x0078, 0x2b5a, 0x1078, 0x753d, 0x0078, 0x2ea5,
+	0x2001, 0xa300, 0x2004, 0xa086, 0x0003, 0x00c0, 0x2b56, 0x0c7e,
+	0x2061, 0x0100, 0x7924, 0x810f, 0xa18c, 0x00ff, 0xa196, 0x00ff,
+	0x00c0, 0x2ec7, 0x6030, 0xa085, 0xff00, 0x0078, 0x2ed6, 0xa182,
+	0x007f, 0x00c8, 0x2f00, 0xa188, 0x293f, 0x210c, 0xa18c, 0x00ff,
+	0x6030, 0xa116, 0x0040, 0x2f00, 0x810f, 0xa105, 0x127e, 0x2091,
+	0x8000, 0x007e, 0x1078, 0x74d7, 0x007f, 0x0040, 0x2efc, 0x601a,
+	0x600b, 0xbc05, 0x601f, 0x0001, 0x1078, 0x3518, 0x0040, 0x2f03,
+	0x6837, 0x0000, 0x7007, 0x0003, 0x6833, 0x0000, 0x6838, 0xc0fd,
+	0x683a, 0x701b, 0x2f07, 0x2d00, 0x6012, 0x2009, 0x0032, 0x1078,
+	0x756c, 0x127f, 0x0c7f, 0x007c, 0x127f, 0x0c7f, 0x0078, 0x2b56,
+	0x0c7f, 0x0078, 0x2b5a, 0x1078, 0x753d, 0x0078, 0x2efc, 0x6830,
+	0xa086, 0x0100, 0x0040, 0x2b56, 0x0078, 0x2b2c, 0x2061, 0xa62d,
+	0x127e, 0x2091, 0x8000, 0x6000, 0xd084, 0x0040, 0x2f1c, 0x6104,
+	0x6208, 0x127f, 0x0078, 0x2b2c, 0x127f, 0x0078, 0x2b5a, 0x81ff,
+	0x00c0, 0x2b56, 0x127e, 0x2091, 0x8000, 0x6244, 0x6060, 0xa202,
+	0x0048, 0x2f33, 0xa085, 0x0001, 0x1078, 0x2500, 0x1078, 0x3bf5,
+	0x127f, 0x0078, 0x2b2c, 0x127f, 0x0078, 0x2b5a, 0x127e, 0x2091,
+	0x8000, 0x20a9, 0x0011, 0x2001, 0xa340, 0x20a0, 0xa006, 0x40a4,
+	0x127f, 0x0078, 0x2b2c, 0x7d38, 0x7c3c, 0x0078, 0x2bde, 0x7824,
+	0xa09c, 0x00ff, 0xa39a, 0x0003, 0x00c8, 0x2b56, 0x624c, 0xa084,
+	0xff00, 0x8007, 0xa206, 0x00c0, 0x2f5f, 0x2001, 0xa340, 0x2009,
+	0x000c, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0078, 0x3566, 0x81ff,
+	0x00c0, 0x2b56, 0x1078, 0x3542, 0x0040, 0x2b5a, 0x6004, 0xa084,
+	0x00ff, 0xa086, 0x0006, 0x00c0, 0x2b56, 0x0c7e, 0x1078, 0x3518,
+	0x0c7f, 0x0040, 0x2b56, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a,
+	0x1078, 0x8b85, 0x0040, 0x2b56, 0x7007, 0x0003, 0x701b, 0x2f81,
+	0x007c, 0x6830, 0xa086, 0x0100, 0x0040, 0x2b56, 0xad80, 0x000e,
+	0x2009, 0x000c, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0078, 0x3566,
+	0x1078, 0x3518, 0x0040, 0x2b56, 0x1078, 0x421a, 0x2009, 0x001c,
+	0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x1078, 0x3562, 0x701b, 0x2fa1,
+	0x007c, 0xade8, 0x000d, 0x6800, 0xa005, 0x0040, 0x2b5a, 0x6804,
+	0xd0ac, 0x0040, 0x2fae, 0xd0a4, 0x0040, 0x2b5a, 0xd094, 0x0040,
+	0x2fb9, 0x0c7e, 0x2061, 0x0100, 0x6104, 0xa18c, 0xffdf, 0x6106,
+	0x0c7f, 0xd08c, 0x0040, 0x2fc4, 0x0c7e, 0x2061, 0x0100, 0x6104,
+	0xa18d, 0x0010, 0x6106, 0x0c7f, 0x2009, 0x0100, 0x210c, 0xa18a,
+	0x0002, 0x0048, 0x2fd9, 0xd084, 0x0040, 0x2fd9, 0x6a28, 0xa28a,
+	0x007f, 0x00c8, 0x2b5a, 0xa288, 0x293f, 0x210c, 0xa18c, 0x00ff,
+	0x6152, 0xd0dc, 0x0040, 0x2fe2, 0x6828, 0xa08a, 0x007f, 0x00c8,
+	0x2b5a, 0x604e, 0x6808, 0xa08a, 0x0100, 0x0048, 0x2b5a, 0xa08a,
+	0x0841, 0x00c8, 0x2b5a, 0xa084, 0x0007, 0x00c0, 0x2b5a, 0x680c,
+	0xa005, 0x0040, 0x2b5a, 0x6810, 0xa005, 0x0040, 0x2b5a, 0x6848,
+	0x6940, 0xa10a, 0x00c8, 0x2b5a, 0x8001, 0x0040, 0x2b5a, 0x684c,
+	0x6944, 0xa10a, 0x00c8, 0x2b5a, 0x8001, 0x0040, 0x2b5a, 0x6804,
+	0xd0fc, 0x0040, 0x3038, 0x1078, 0x3518, 0x0040, 0x2b56, 0x2009,
+	0x0014, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0xa290, 0x0038, 0xa399,
+	0x0000, 0x1078, 0x3562, 0x701b, 0x301e, 0x007c, 0xade8, 0x000d,
+	0x20a9, 0x0014, 0x2d98, 0x2069, 0xa36d, 0x2da0, 0x53a3, 0x7010,
+	0xa0e8, 0x000d, 0x2001, 0xa371, 0x200c, 0xd1e4, 0x0040, 0x3038,
+	0x0c7e, 0x2061, 0x0100, 0x6004, 0xa085, 0x0b00, 0x6006, 0x0c7f,
+	0x20a9, 0x001c, 0x2d98, 0x2069, 0xa351, 0x2da0, 0x53a3, 0x6814,
+	0xa08c, 0x00ff, 0x613e, 0x8007, 0xa084, 0x00ff, 0x6042, 0x1078,
+	0x4dbd, 0x1078, 0x48dd, 0x1078, 0x494d, 0x6000, 0xa086, 0x0000,
+	0x00c0, 0x30c3, 0x6808, 0x602a, 0x1078, 0x218b, 0x6818, 0x691c,
+	0x6a20, 0x6b24, 0x8007, 0x810f, 0x8217, 0x831f, 0x6016, 0x611a,
+	0x621e, 0x6322, 0x6c04, 0xd4f4, 0x0040, 0x3070, 0x6830, 0x6934,
+	0x6a38, 0x6b3c, 0x8007, 0x810f, 0x8217, 0x831f, 0x0078, 0x3072,
+	0xa084, 0xf0ff, 0x6006, 0x610a, 0x620e, 0x6312, 0x1078, 0x59a8,
+	0x6904, 0xd1fc, 0x0040, 0x30a5, 0x0c7e, 0x2009, 0x0000, 0x20a9,
+	0x0001, 0x6b70, 0xd384, 0x0040, 0x30a2, 0x0078, 0x308c, 0x839d,
+	0x00c8, 0x30a2, 0x3508, 0x8109, 0x1078, 0x5364, 0x6878, 0x6016,
+	0x6874, 0x2008, 0xa084, 0xff00, 0x8007, 0x600a, 0xa184, 0x00ff,
+	0x6006, 0x8108, 0x00c0, 0x30a0, 0x6003, 0x0003, 0x0078, 0x30a2,
+	0x6003, 0x0001, 0x00f0, 0x3087, 0x0c7f, 0x0c7e, 0x2061, 0x0100,
+	0x602f, 0x0040, 0x602f, 0x0000, 0x0c7f, 0x1078, 0x3784, 0x0040,
+	0x30b3, 0x1078, 0x2500, 0x60bc, 0xa005, 0x0040, 0x30bf, 0x6003,
+	0x0001, 0x2091, 0x301d, 0x1078, 0x4171, 0x0078, 0x30c3, 0x6003,
+	0x0004, 0x2091, 0x301d, 0x0078, 0x2b2c, 0x6000, 0xa086, 0x0000,
+	0x0040, 0x2b56, 0x2069, 0xa351, 0x7830, 0x6842, 0x7834, 0x6846,
+	0x6804, 0xd0fc, 0x0040, 0x30d8, 0x2009, 0x0030, 0x0078, 0x30da,
+	0x2009, 0x001c, 0x2d00, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0078,
+	0x3566, 0xa006, 0x1078, 0x2500, 0x81ff, 0x00c0, 0x2b56, 0x1078,
+	0x421a, 0x1078, 0x4171, 0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56,
+	0x6180, 0x81ff, 0x0040, 0x3107, 0x703f, 0x0000, 0x2001, 0xa9c0,
+	0x2009, 0x0040, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x127e, 0x2091,
+	0x8000, 0x1078, 0x3566, 0x701b, 0x2b29, 0x127f, 0x007c, 0x703f,
+	0x0001, 0x0d7e, 0x2069, 0xa9c0, 0x20a9, 0x0040, 0x20a1, 0xa9c0,
+	0x2019, 0xffff, 0x43a4, 0x654c, 0xa588, 0x293f, 0x210c, 0xa18c,
+	0x00ff, 0x216a, 0xa00e, 0x2011, 0x0002, 0x2100, 0xa506, 0x0040,
+	0x3139, 0x1078, 0x4501, 0x00c0, 0x3139, 0x6014, 0x821c, 0x0048,
+	0x3131, 0xa398, 0xa9c0, 0xa085, 0xff00, 0x8007, 0x201a, 0x0078,
+	0x3138, 0xa398, 0xa9c0, 0x2324, 0xa4a4, 0xff00, 0xa405, 0x201a,
+	0x8210, 0x8108, 0xa182, 0x0080, 0x00c8, 0x3140, 0x0078, 0x311d,
+	0x8201, 0x8007, 0x2d0c, 0xa105, 0x206a, 0x0d7f, 0x20a9, 0x0040,
+	0x20a1, 0xa9c0, 0x2099, 0xa9c0, 0x1078, 0x41be, 0x0078, 0x30f6,
+	0x1078, 0x3542, 0x0040, 0x2b5a, 0x0c7e, 0x1078, 0x3518, 0x0c7f,
+	0x00c0, 0x315e, 0x2009, 0x0002, 0x0078, 0x2b56, 0x2001, 0xa352,
+	0x2004, 0xd0b4, 0x0040, 0x3185, 0x6000, 0xd08c, 0x00c0, 0x3185,
+	0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x00c0, 0x3185, 0x6837,
+	0x0000, 0x6838, 0xc0fd, 0x683a, 0x1078, 0x8bd9, 0x00c0, 0x317c,
+	0x2009, 0x0003, 0x0078, 0x2b56, 0x7007, 0x0003, 0x701b, 0x3181,
+	0x007c, 0x1078, 0x3542, 0x0040, 0x2b5a, 0x20a9, 0x002b, 0x2c98,
+	0xade8, 0x0002, 0x2da0, 0x53a3, 0x20a9, 0x0004, 0xac80, 0x0006,
+	0x2098, 0xad80, 0x0006, 0x20a0, 0x1078, 0x41be, 0x20a9, 0x0004,
+	0xac80, 0x000a, 0x2098, 0xad80, 0x000a, 0x20a0, 0x1078, 0x41be,
+	0x2d00, 0x2009, 0x002b, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0078,
+	0x3566, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x3530, 0x0040, 0x2b5a,
+	0x1078, 0x46ef, 0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56, 0x7828,
+	0xa08a, 0x1000, 0x00c8, 0x2b5a, 0x1078, 0x3542, 0x0040, 0x2b5a,
+	0x1078, 0x475f, 0x0040, 0x2b56, 0x2019, 0x0004, 0x1078, 0x4705,
+	0x7924, 0x810f, 0x7a28, 0x1078, 0x31cf, 0x0078, 0x2b2c, 0xa186,
+	0x00ff, 0x0040, 0x31d7, 0x1078, 0x31e7, 0x0078, 0x31e6, 0x2029,
+	0x007e, 0x2061, 0xa300, 0x644c, 0x2400, 0xa506, 0x0040, 0x31e3,
+	0x2508, 0x1078, 0x31e7, 0x8529, 0x00c8, 0x31dc, 0x007c, 0x1078,
+	0x4501, 0x00c0, 0x31f2, 0x2200, 0x8003, 0x800b, 0x810b, 0xa108,
+	0x1078, 0x58e1, 0x007c, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x3530,
+	0x0040, 0x2b5a, 0x1078, 0x45a7, 0x0040, 0x2b56, 0x1078, 0x46fa,
+	0x0078, 0x2b2c, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x3530, 0x0040,
+	0x2b5a, 0x1078, 0x45a7, 0x0040, 0x2b56, 0x1078, 0x46e4, 0x0078,
+	0x2b2c, 0x6100, 0x0078, 0x2b2c, 0x1078, 0x3542, 0x0040, 0x2b5a,
+	0x2001, 0xa300, 0x2004, 0xa086, 0x0003, 0x00c0, 0x2b56, 0x0d7e,
+	0xace8, 0x000a, 0x7924, 0xd184, 0x0040, 0x3228, 0xace8, 0x0006,
+	0x680c, 0x8007, 0x783e, 0x6808, 0x8007, 0x783a, 0x6b04, 0x831f,
+	0x6a00, 0x8217, 0x0d7f, 0x6100, 0xa18c, 0x0200, 0x0078, 0x2b2c,
+	0xa006, 0x1078, 0x2500, 0x7824, 0xa084, 0x00ff, 0xa086, 0x00ff,
+	0x0040, 0x3245, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x421a, 0x7828,
+	0xa08a, 0x1000, 0x00c8, 0x2b5a, 0x7924, 0xa18c, 0xff00, 0x810f,
+	0xa186, 0x00ff, 0x0040, 0x325b, 0xa182, 0x007f, 0x00c8, 0x2b5a,
+	0x2100, 0x1078, 0x24fa, 0x027e, 0x0c7e, 0x127e, 0x2091, 0x8000,
+	0x2061, 0xa5be, 0x601b, 0x0000, 0x601f, 0x0000, 0x2061, 0x0100,
+	0x6030, 0xa084, 0x00ff, 0x810f, 0xa105, 0x604a, 0x6043, 0x0090,
+	0x6043, 0x0010, 0x2009, 0x002d, 0x2011, 0x4196, 0x1078, 0x596c,
+	0x7924, 0xa18c, 0xff00, 0x810f, 0x7a28, 0x1078, 0x31cf, 0x127f,
+	0x0c7f, 0x027f, 0x0078, 0x2b2c, 0x7924, 0xa18c, 0xff00, 0x810f,
+	0x0c7e, 0x1078, 0x4499, 0x2c08, 0x0c7f, 0x00c0, 0x2b5a, 0x0078,
+	0x2b2c, 0x81ff, 0x0040, 0x3298, 0x2009, 0x0001, 0x0078, 0x2b56,
+	0x60c8, 0xd09c, 0x00c0, 0x32a0, 0x2009, 0x0005, 0x0078, 0x2b56,
+	0x1078, 0x3518, 0x00c0, 0x32a8, 0x2009, 0x0002, 0x0078, 0x2b56,
+	0x7924, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x1078, 0x3562, 0x701b,
+	0x32b2, 0x007c, 0x2009, 0x0080, 0x1078, 0x4501, 0x00c0, 0x32bf,
+	0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x0040, 0x32c3, 0x2021,
+	0x400a, 0x0078, 0x2b2e, 0x0d7e, 0xade8, 0x000d, 0x6900, 0x6a08,
+	0x6b0c, 0x6c10, 0x6d14, 0x6e18, 0x6820, 0xa0be, 0x0100, 0x0040,
+	0x3336, 0xa0be, 0x0112, 0x0040, 0x3336, 0xa0be, 0x0113, 0x0040,
+	0x3336, 0xa0be, 0x0114, 0x0040, 0x3336, 0xa0be, 0x0117, 0x0040,
+	0x3336, 0xa0be, 0x011a, 0x0040, 0x3336, 0xa0be, 0x0121, 0x0040,
+	0x332c, 0xa0be, 0x0131, 0x0040, 0x332c, 0xa0be, 0x0171, 0x0040,
+	0x3336, 0xa0be, 0x0173, 0x0040, 0x3336, 0xa0be, 0x01a1, 0x00c0,
+	0x32fe, 0x6830, 0x8007, 0x6832, 0x0078, 0x333c, 0xa0be, 0x0212,
+	0x0040, 0x3332, 0xa0be, 0x0213, 0x0040, 0x3332, 0xa0be, 0x0214,
+	0x0040, 0x3324, 0xa0be, 0x0217, 0x0040, 0x331e, 0xa0be, 0x021a,
+	0x00c0, 0x3317, 0x6838, 0x8007, 0x683a, 0x0078, 0x3336, 0xa0be,
+	0x0300, 0x0040, 0x3336, 0x0d7f, 0x0078, 0x2b5a, 0xad80, 0x0010,
+	0x20a9, 0x0007, 0x1078, 0x337e, 0xad80, 0x000e, 0x20a9, 0x0001,
+	0x1078, 0x337e, 0x0078, 0x3336, 0xad80, 0x000c, 0x1078, 0x338c,
+	0x0078, 0x333c, 0xad80, 0x000e, 0x1078, 0x338c, 0xad80, 0x000c,
+	0x20a9, 0x0001, 0x1078, 0x337e, 0x0c7e, 0x1078, 0x3518, 0x0040,
+	0x336f, 0x6838, 0xc0fd, 0x683a, 0x6837, 0x0119, 0x6853, 0x0000,
+	0x684f, 0x0020, 0x685b, 0x0001, 0x810b, 0x697e, 0x6883, 0x0000,
+	0x6a86, 0x6b8a, 0x6c8e, 0x6d92, 0x6996, 0x689b, 0x0000, 0x0c7f,
+	0x0d7f, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x6823, 0x0000,
+	0x6804, 0x2068, 0x1078, 0x8ba1, 0x00c0, 0x336a, 0x2009, 0x0003,
+	0x0078, 0x2b56, 0x7007, 0x0003, 0x701b, 0x3375, 0x007c, 0x0c7f,
+	0x0d7f, 0x2009, 0x0002, 0x0078, 0x2b56, 0x6820, 0xa086, 0x8001,
+	0x00c0, 0x2b2c, 0x2009, 0x0004, 0x0078, 0x2b56, 0x017e, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x290a, 0x8108, 0x280a, 0x8108,
+	0x00f0, 0x3380, 0x017f, 0x007c, 0x017e, 0x0a7e, 0x0b7e, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x2054, 0x8000, 0x205c, 0x2b0a,
+	0x8108, 0x2a0a, 0x8108, 0x290a, 0x8108, 0x280a, 0x0b7f, 0x0a7f,
+	0x017f, 0x007c, 0x81ff, 0x0040, 0x33a9, 0x2009, 0x0001, 0x0078,
+	0x2b56, 0x7924, 0x2140, 0xa18c, 0xff00, 0x810f, 0xa182, 0x0080,
+	0x0048, 0x2b5a, 0xa182, 0x00ff, 0x00c8, 0x2b5a, 0x7a2c, 0x7b28,
+	0x6068, 0xa306, 0x00c0, 0x33c4, 0x606c, 0xa24e, 0x0040, 0x2b5a,
+	0xa9cc, 0xff00, 0x0040, 0x2b5a, 0x0c7e, 0x1078, 0x346d, 0x2c68,
+	0x0c7f, 0x0040, 0x33fc, 0xa0c6, 0x4000, 0x00c0, 0x33e2, 0x0c7e,
+	0x007e, 0x2d60, 0x2009, 0x0000, 0x1078, 0x47cb, 0x00c0, 0x33d9,
+	0xc185, 0x6000, 0xd0bc, 0x0040, 0x33de, 0xc18d, 0x007f, 0x0c7f,
+	0x0078, 0x33f9, 0xa0c6, 0x4007, 0x00c0, 0x33e9, 0x2408, 0x0078,
+	0x33f9, 0xa0c6, 0x4008, 0x00c0, 0x33f1, 0x2708, 0x2610, 0x0078,
+	0x33f9, 0xa0c6, 0x4009, 0x00c0, 0x33f7, 0x0078, 0x33f9, 0x2001,
+	0x4006, 0x2020, 0x0078, 0x2b2e, 0x2d00, 0x7022, 0x017e, 0x0b7e,
+	0x0c7e, 0x0e7e, 0x2c70, 0x1078, 0x74d7, 0x0040, 0x3442, 0x2d00,
+	0x601a, 0x2001, 0xa356, 0x2004, 0xa084, 0x00ff, 0x6842, 0x2e58,
+	0x0e7f, 0x0e7e, 0x0c7e, 0x1078, 0x3518, 0x0c7f, 0x2b70, 0x00c0,
+	0x3423, 0x1078, 0x753d, 0x0e7f, 0x0c7f, 0x0b7f, 0x017f, 0x2009,
+	0x0002, 0x0078, 0x2b56, 0x6837, 0x0000, 0x2d00, 0x6012, 0x6833,
+	0x0000, 0x6838, 0xc0fd, 0x683a, 0x127e, 0x2091, 0x8000, 0x1078,
+	0x2813, 0x127f, 0x601f, 0x0001, 0x2001, 0x0000, 0x1078, 0x442b,
+	0x2001, 0x0002, 0x1078, 0x443f, 0x2009, 0x0002, 0x1078, 0x756c,
+	0xa085, 0x0001, 0x0e7f, 0x0c7f, 0x0b7f, 0x017f, 0x00c0, 0x344c,
+	0x2009, 0x0003, 0x0078, 0x2b56, 0x7007, 0x0003, 0x701b, 0x3451,
+	0x007c, 0x6830, 0xa086, 0x0100, 0x7020, 0x2060, 0x00c0, 0x345f,
+	0x2009, 0x0004, 0x6204, 0xa294, 0x00ff, 0x0078, 0x2b56, 0x2009,
+	0x0000, 0x1078, 0x47cb, 0x00c0, 0x3466, 0xc185, 0x6000, 0xd0bc,
+	0x0040, 0x346b, 0xc18d, 0x0078, 0x2b2c, 0x0e7e, 0x0d7e, 0x2029,
+	0x0000, 0x2021, 0x0080, 0x20a9, 0x007f, 0x2071, 0xa4b4, 0x2e04,
+	0xa005, 0x00c0, 0x3482, 0x2100, 0xa406, 0x00c0, 0x34b3, 0x2428,
+	0x0078, 0x34b3, 0x2068, 0x6f10, 0x2700, 0xa306, 0x00c0, 0x34a4,
+	0x6e14, 0x2600, 0xa206, 0x00c0, 0x34a4, 0x2400, 0xa106, 0x00c0,
+	0x34a0, 0x2d60, 0xd884, 0x0040, 0x34c8, 0x6004, 0xa084, 0x00ff,
+	0xa086, 0x0006, 0x00c0, 0x34c8, 0x2001, 0x4000, 0x0078, 0x34c9,
+	0x2001, 0x4007, 0x0078, 0x34c9, 0x2400, 0xa106, 0x00c0, 0x34b3,
+	0x6e14, 0x87ff, 0x00c0, 0x34af, 0x86ff, 0x0040, 0x347f, 0x2001,
+	0x4008, 0x0078, 0x34c9, 0x8420, 0x8e70, 0x00f0, 0x3477, 0x85ff,
+	0x00c0, 0x34c2, 0x2001, 0x4009, 0x0078, 0x34c9, 0x2001, 0x0001,
+	0x0078, 0x34c9, 0x1078, 0x4499, 0x00c0, 0x34be, 0x6312, 0x6216,
+	0xa006, 0xa005, 0x0d7f, 0x0e7f, 0x007c, 0x81ff, 0x00c0, 0x2b56,
+	0x1078, 0x3518, 0x0040, 0x2b56, 0x6837, 0x0000, 0x6838, 0xc0fd,
+	0x683a, 0x7824, 0xa005, 0x0040, 0x2b5a, 0xa096, 0x00ff, 0x0040,
+	0x34e5, 0xa092, 0x0004, 0x00c8, 0x2b5a, 0x2010, 0x2d18, 0x1078,
+	0x27c2, 0x0040, 0x2b56, 0x7007, 0x0003, 0x701b, 0x34f0, 0x007c,
+	0x6830, 0xa086, 0x0100, 0x0040, 0x2b56, 0x0078, 0x2b2c, 0x7924,
+	0xa18c, 0xff00, 0x810f, 0xa182, 0x0080, 0x0048, 0x2b5a, 0xa182,
+	0x00ff, 0x00c8, 0x2b5a, 0x127e, 0x2091, 0x8000, 0x1078, 0x8a89,
+	0x00c0, 0x3515, 0xa190, 0xa434, 0x2204, 0xa065, 0x0040, 0x3515,
+	0x1078, 0x4235, 0x127f, 0x0078, 0x2b2c, 0x127f, 0x0078, 0x2b56,
+	0x1078, 0x1381, 0x0040, 0x352f, 0xa006, 0x6802, 0x7010, 0xa005,
+	0x00c0, 0x3527, 0x2d00, 0x7012, 0x7016, 0x0078, 0x352d, 0x7014,
+	0x6802, 0x2060, 0x2d00, 0x6006, 0x7016, 0xad80, 0x000d, 0x007c,
+	0x7924, 0x810f, 0xa18c, 0x00ff, 0x1078, 0x4501, 0x00c0, 0x353f,
+	0x7e28, 0xa684, 0x3fff, 0xa082, 0x4000, 0x0048, 0x3540, 0xa066,
+	0x8cff, 0x007c, 0x7e24, 0x860f, 0xa18c, 0x00ff, 0x1078, 0x4501,
+	0x00c0, 0x3550, 0xa6b4, 0x00ff, 0xa682, 0x4000, 0x0048, 0x3551,
+	0xa066, 0x8cff, 0x007c, 0x017e, 0x7110, 0x81ff, 0x0040, 0x355e,
+	0x2168, 0x6904, 0x1078, 0x139a, 0x0078, 0x3555, 0x7112, 0x7116,
+	0x017f, 0x007c, 0x2031, 0x0001, 0x0078, 0x3568, 0x2031, 0x0000,
+	0x2061, 0xa3d1, 0x6606, 0x6112, 0x600e, 0x6226, 0x632a, 0x642e,
+	0x6532, 0x2c10, 0x1078, 0x13d1, 0x7007, 0x0002, 0x701b, 0x2b2c,
+	0x007c, 0x0f7e, 0x127e, 0x2091, 0x8000, 0x2079, 0x0000, 0x2001,
+	0xa38f, 0x2004, 0xa005, 0x00c0, 0x3594, 0x0068, 0x3594, 0x7818,
+	0xd084, 0x00c0, 0x3594, 0x7a22, 0x7b26, 0x7c2a, 0x781b, 0x0001,
+	0x2091, 0x4080, 0x0078, 0x35b9, 0x017e, 0x0c7e, 0x0e7e, 0x2071,
+	0xa381, 0x7138, 0xa182, 0x0008, 0x0048, 0x35a2, 0x7030, 0x2060,
+	0x0078, 0x35b3, 0x7030, 0xa0e0, 0x0008, 0xac82, 0xa3d1, 0x0048,
+	0x35ab, 0x2061, 0xa391, 0x2c00, 0x7032, 0x81ff, 0x00c0, 0x35b1,
+	0x7036, 0x8108, 0x713a, 0x2262, 0x6306, 0x640a, 0x0e7f, 0x0c7f,
+	0x017f, 0x127f, 0x0f7f, 0x007c, 0x0e7e, 0x2071, 0xa381, 0x7038,
+	0xa005, 0x0040, 0x35f5, 0x127e, 0x2091, 0x8000, 0x0068, 0x35f4,
+	0x0f7e, 0x2079, 0x0000, 0x7818, 0xd084, 0x00c0, 0x35f3, 0x0c7e,
+	0x7034, 0x2060, 0x2c04, 0x7822, 0x6004, 0x7826, 0x6008, 0x782a,
+	0x781b, 0x0001, 0x2091, 0x4080, 0x7038, 0x8001, 0x703a, 0xa005,
+	0x00c0, 0x35e9, 0x7033, 0xa391, 0x7037, 0xa391, 0x0c7f, 0x0078,
+	0x35f3, 0xac80, 0x0008, 0xa0fa, 0xa3d1, 0x0048, 0x35f1, 0x2001,
+	0xa391, 0x7036, 0x0c7f, 0x0f7f, 0x127f, 0x0e7f, 0x007c, 0x027e,
+	0x2001, 0xa352, 0x2004, 0xd0c4, 0x0040, 0x3602, 0x2011, 0x8014,
+	0x1078, 0x3579, 0x027f, 0x007c, 0x81ff, 0x00c0, 0x2b56, 0x127e,
+	0x2091, 0x8000, 0x6030, 0xc08d, 0xc085, 0xc0ac, 0x6032, 0x1078,
+	0x4171, 0x127f, 0x0078, 0x2b2c, 0x7824, 0x2008, 0xa18c, 0xfffd,
+	0x00c0, 0x361f, 0x61d4, 0xa10d, 0x61d6, 0x0078, 0x2b2c, 0x0078,
+	0x2b5a, 0x81ff, 0x00c0, 0x2b56, 0x6000, 0xa086, 0x0003, 0x00c0,
+	0x2b56, 0x2001, 0xa352, 0x2004, 0xd0ac, 0x00c0, 0x2b56, 0x1078,
+	0x3542, 0x0040, 0x2b5a, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006,
+	0x00c0, 0x363e, 0x7828, 0xa005, 0x0040, 0x2b2c, 0x0c7e, 0x1078,
+	0x3518, 0x0c7f, 0x0040, 0x2b56, 0x6837, 0x0000, 0x6833, 0x0000,
+	0x6838, 0xc0fd, 0x683a, 0x1078, 0x8c4d, 0x0040, 0x2b56, 0x7007,
+	0x0003, 0x701b, 0x3654, 0x007c, 0x6830, 0xa086, 0x0100, 0x0040,
+	0x2b56, 0x0078, 0x2b2c, 0x2001, 0xa300, 0x2004, 0xa086, 0x0003,
+	0x00c0, 0x2b56, 0x7f24, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x1078,
+	0x3518, 0x0040, 0x2b56, 0x2009, 0x0000, 0x2031, 0x0000, 0x7023,
+	0x0000, 0x702f, 0x0000, 0xad80, 0x0005, 0x7026, 0x20a0, 0x1078,
+	0x4501, 0x00c0, 0x36d8, 0x6004, 0xa0c4, 0x00ff, 0xa8c6, 0x0006,
+	0x0040, 0x3688, 0xa0c4, 0xff00, 0xa8c6, 0x0600, 0x00c0, 0x36d8,
+	0x2001, 0xa352, 0x2004, 0xd0ac, 0x00c0, 0x3695, 0x1078, 0x47cb,
+	0x00c0, 0x3695, 0xd79c, 0x0040, 0x36d8, 0xd794, 0x00c0, 0x369b,
+	0xd784, 0x0040, 0x36a7, 0xac80, 0x0006, 0x2098, 0x3400, 0x20a9,
+	0x0004, 0x53a3, 0x1078, 0x338c, 0xd794, 0x0040, 0x36b0, 0xac80,
+	0x000a, 0x2098, 0x3400, 0x20a9, 0x0004, 0x53a3, 0x1078, 0x338c,
+	0x21a2, 0xd794, 0x0040, 0x36d0, 0xac80, 0x0000, 0x2098, 0x94a0,
+	0x20a9, 0x0002, 0x53a3, 0xac80, 0x0003, 0x20a6, 0x94a0, 0xac80,
+	0x0004, 0x2098, 0x3400, 0x20a9, 0x0002, 0x53a3, 0x1078, 0x337e,
+	0xac80, 0x0026, 0x2098, 0x20a9, 0x0002, 0x53a3, 0x0078, 0x36d1,
+	0x94a0, 0xd794, 0x0040, 0x36d6, 0xa6b0, 0x000b, 0xa6b0, 0x0005,
+	0x8108, 0xd78c, 0x0040, 0x36e2, 0xa186, 0x0100, 0x0040, 0x36f3,
+	0x0078, 0x36e6, 0xa186, 0x007e, 0x0040, 0x36f3, 0xd794, 0x0040,
+	0x36ed, 0xa686, 0x0020, 0x0078, 0x36ef, 0xa686, 0x0028, 0x0040,
+	0x36fc, 0x0078, 0x3677, 0x86ff, 0x00c0, 0x36fa, 0x7120, 0x810b,
+	0x0078, 0x2b2c, 0x702f, 0x0001, 0x711e, 0x7020, 0xa600, 0x7022,
+	0x772a, 0x2061, 0xa3d1, 0x6007, 0x0000, 0x6612, 0x7024, 0x600e,
+	0x6226, 0x632a, 0x642e, 0x6532, 0x2c10, 0x1078, 0x13d1, 0x7007,
+	0x0002, 0x701b, 0x3714, 0x007c, 0x702c, 0xa005, 0x00c0, 0x3726,
+	0x711c, 0x7024, 0x20a0, 0x7728, 0x2031, 0x0000, 0x2061, 0xa3d1,
+	0x6224, 0x6328, 0x642c, 0x6530, 0x0078, 0x3677, 0x7120, 0x810b,
+	0x0078, 0x2b2c, 0x2029, 0x007e, 0x7924, 0x7a28, 0x7b2c, 0x7c38,
+	0xa184, 0xff00, 0x8007, 0xa0e2, 0x0020, 0x0048, 0x2b5a, 0xa502,
+	0x0048, 0x2b5a, 0xa184, 0x00ff, 0xa0e2, 0x0020, 0x0048, 0x2b5a,
+	0xa502, 0x0048, 0x2b5a, 0xa284, 0xff00, 0x8007, 0xa0e2, 0x0020,
+	0x0048, 0x2b5a, 0xa502, 0x0048, 0x2b5a, 0xa284, 0x00ff, 0xa0e2,
+	0x0020, 0x0048, 0x2b5a, 0xa502, 0x0048, 0x2b5a, 0xa384, 0xff00,
+	0x8007, 0xa0e2, 0x0020, 0x0048, 0x2b5a, 0xa502, 0x0048, 0x2b5a,
+	0xa384, 0x00ff, 0xa0e2, 0x0020, 0x0048, 0x2b5a, 0xa502, 0x0048,
+	0x2b5a, 0xa484, 0xff00, 0x8007, 0xa0e2, 0x0020, 0x0048, 0x2b5a,
+	0xa502, 0x0048, 0x2b5a, 0xa484, 0x00ff, 0xa0e2, 0x0020, 0x0048,
+	0x2b5a, 0xa502, 0x0048, 0x2b5a, 0x2061, 0xa5a3, 0x6102, 0x6206,
+	0x630a, 0x640e, 0x0078, 0x2b2c, 0x007e, 0x2001, 0xa352, 0x2004,
+	0xd0cc, 0x007f, 0x007c, 0x007e, 0x2001, 0xa371, 0x2004, 0xd0bc,
+	0x007f, 0x007c, 0x6160, 0x7a24, 0x6300, 0x82ff, 0x00c0, 0x379b,
+	0x7926, 0x0078, 0x2b2c, 0x83ff, 0x00c0, 0x2b5a, 0x2001, 0xfff0,
+	0xa200, 0x00c8, 0x2b5a, 0x2019, 0xffff, 0x6064, 0xa302, 0xa200,
+	0x0048, 0x2b5a, 0x7926, 0x6262, 0x0078, 0x2b2c, 0x2001, 0xa300,
+	0x2004, 0xa086, 0x0003, 0x00c0, 0x2b56, 0x7c28, 0x7d24, 0x7e38,
+	0x7f2c, 0x1078, 0x3518, 0x0040, 0x2b56, 0x2009, 0x0000, 0x2019,
+	0x0000, 0x7023, 0x0000, 0x702f, 0x0000, 0xad80, 0x0003, 0x7026,
+	0x20a0, 0xa1e0, 0xa434, 0x2c64, 0x8cff, 0x0040, 0x37e8, 0x6004,
+	0xa084, 0x00ff, 0xa086, 0x0006, 0x0040, 0x37dd, 0x6004, 0xa084,
+	0xff00, 0xa086, 0x0600, 0x00c0, 0x37e8, 0x6014, 0x20a2, 0x94a0,
+	0x6010, 0x8007, 0xa105, 0x8007, 0x20a2, 0x94a0, 0xa398, 0x0002,
+	0x8108, 0xa182, 0x00ff, 0x0040, 0x37f3, 0xa386, 0x002a, 0x0040,
+	0x37fc, 0x0078, 0x37c9, 0x83ff, 0x00c0, 0x37fa, 0x7120, 0x810c,
+	0x0078, 0x2b2c, 0x702f, 0x0001, 0x711e, 0x7020, 0xa300, 0x7022,
+	0x2061, 0xa3d1, 0x6007, 0x0000, 0x6312, 0x7024, 0x600e, 0x6426,
+	0x652a, 0x662e, 0x6732, 0x2c10, 0x1078, 0x13d1, 0x7007, 0x0002,
+	0x701b, 0x3813, 0x007c, 0x702c, 0xa005, 0x00c0, 0x3824, 0x711c,
+	0x7024, 0x20a0, 0x2019, 0x0000, 0x2061, 0xa3d1, 0x6424, 0x6528,
+	0x662c, 0x6730, 0x0078, 0x37c9, 0x7120, 0x810c, 0x0078, 0x2b2c,
+	0x81ff, 0x00c0, 0x2b56, 0x60c8, 0xd09c, 0x0040, 0x2b56, 0x1078,
+	0x3518, 0x0040, 0x2b56, 0x7924, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38,
+	0x1078, 0x3562, 0x701b, 0x383d, 0x007c, 0x0d7e, 0xade8, 0x000d,
+	0x6828, 0xa0be, 0x7000, 0x0040, 0x3850, 0xa0be, 0x7100, 0x0040,
+	0x3850, 0xa0be, 0x7200, 0x0040, 0x3850, 0x0d7f, 0x0078, 0x2b5a,
+	0x6820, 0x6924, 0x1078, 0x24e3, 0x00c0, 0x387b, 0x1078, 0x4499,
+	0x00c0, 0x387b, 0x7122, 0x6612, 0x6516, 0x6e18, 0x0c7e, 0x1078,
+	0x3518, 0x0040, 0x387b, 0x1078, 0x3518, 0x0040, 0x387b, 0x0c7f,
+	0x0d7f, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x6823, 0x0000,
+	0x6804, 0x2068, 0x1078, 0x8bbd, 0x0040, 0x2b56, 0x7007, 0x0003,
+	0x701b, 0x387e, 0x007c, 0x0d7f, 0x0078, 0x2b56, 0x7120, 0x1078,
+	0x2921, 0x6820, 0xa086, 0x8001, 0x0040, 0x2b56, 0x2d00, 0x701e,
+	0x6804, 0xa080, 0x0002, 0x007e, 0x20a9, 0x002a, 0x2098, 0x20a0,
+	0x1078, 0x41be, 0x007f, 0xade8, 0x000d, 0x6a08, 0x6b0c, 0x6c10,
+	0x6d14, 0x2061, 0xa3d1, 0x6007, 0x0000, 0x6e00, 0x6f28, 0xa7c6,
+	0x7000, 0x00c0, 0x38a5, 0x0078, 0x38a9, 0xa7c6, 0x7100, 0x00c0,
+	0x38b1, 0xa6c2, 0x0004, 0x0048, 0x2b5a, 0x2009, 0x0004, 0x0078,
+	0x3566, 0xa7c6, 0x7200, 0x00c0, 0x2b5a, 0xa6c2, 0x0054, 0x0048,
+	0x2b5a, 0x600e, 0x6013, 0x002a, 0x6226, 0x632a, 0x642e, 0x6532,
+	0x2c10, 0x1078, 0x13d1, 0x7007, 0x0002, 0x701b, 0x38c8, 0x007c,
+	0x701c, 0x2068, 0x6804, 0xa080, 0x0001, 0x2004, 0xa080, 0x0002,
+	0x007e, 0x20a9, 0x002a, 0x2098, 0x20a0, 0x1078, 0x41be, 0x007f,
+	0x2009, 0x002a, 0x2061, 0xa3d1, 0x6224, 0x6328, 0x642c, 0x6530,
+	0x0078, 0x3566, 0x81ff, 0x00c0, 0x2b56, 0x1078, 0x3530, 0x0040,
+	0x2b5a, 0x1078, 0x45a7, 0x0040, 0x2b56, 0x1078, 0x4710, 0x0078,
+	0x2b2c, 0x7824, 0xd084, 0x0040, 0x3150, 0x1078, 0x3542, 0x0040,
+	0x2b5a, 0x0c7e, 0x1078, 0x3518, 0x0c7f, 0x00c0, 0x3903, 0x2009,
+	0x0002, 0x0078, 0x2b56, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006,
+	0x0040, 0x3910, 0xa08e, 0x0004, 0x0040, 0x3910, 0xa08e, 0x0005,
+	0x00c0, 0x3934, 0x2001, 0xa352, 0x2004, 0xd0b4, 0x0040, 0x3185,
+	0x6000, 0xd08c, 0x00c0, 0x3185, 0x6837, 0x0000, 0x6838, 0xc0fd,
+	0x683a, 0x1078, 0x8bd9, 0x00c0, 0x3929, 0x2009, 0x0003, 0x0078,
+	0x2b56, 0x7007, 0x0003, 0x701b, 0x392e, 0x007c, 0x1078, 0x3542,
+	0x0040, 0x2b5a, 0x0078, 0x3185, 0x2009, 0xa32e, 0x210c, 0x81ff,
+	0x0040, 0x393e, 0x2009, 0x0001, 0x0078, 0x2b56, 0x2001, 0xa300,
+	0x2004, 0xa086, 0x0003, 0x0040, 0x3949, 0x2009, 0x0007, 0x0078,
+	0x2b56, 0x2001, 0xa352, 0x2004, 0xd0ac, 0x0040, 0x3953, 0x2009,
+	0x0008, 0x0078, 0x2b56, 0x609c, 0xd0a4, 0x00c0, 0x395a, 0xd0ac,
+	0x00c0, 0x3185, 0x6837, 0x0000, 0x6833, 0x0000, 0x6838, 0xc0fd,
+	0x683a, 0x1078, 0x8c4d, 0x00c0, 0x3969, 0x2009, 0x0003, 0x0078,
+	0x2b56, 0x7007, 0x0003, 0x701b, 0x396e, 0x007c, 0x6830, 0xa086,
+	0x0100, 0x00c0, 0x3977, 0x2009, 0x0004, 0x0078, 0x2b56, 0x1078,
+	0x3542, 0x0040, 0x2b5a, 0x0078, 0x3912, 0x81ff, 0x2009, 0x0001,
+	0x00c0, 0x2b56, 0x6000, 0xa086, 0x0003, 0x2009, 0x0007, 0x00c0,
+	0x2b56, 0x2001, 0xa352, 0x2004, 0xd0ac, 0x2009, 0x0008, 0x00c0,
+	0x2b56, 0x1078, 0x3542, 0x0040, 0x2b5a, 0x6004, 0xa084, 0x00ff,
+	0xa086, 0x0006, 0x2009, 0x0009, 0x00c0, 0x2b56, 0x0c7e, 0x1078,
+	0x3518, 0x0c7f, 0x2009, 0x0002, 0x0040, 0x2b56, 0x6837, 0x0000,
+	0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x7928, 0xa194, 0xff00,
+	0xa18c, 0x00ff, 0xa006, 0x82ff, 0x00c0, 0x39bc, 0xc0ed, 0x6952,
+	0x792c, 0x6956, 0x0078, 0x39c5, 0xa28e, 0x0100, 0x00c0, 0x2b5a,
+	0xc0e5, 0x6853, 0x0000, 0x6857, 0x0000, 0x683e, 0x1078, 0x8df6,
+	0x2009, 0x0003, 0x0040, 0x2b56, 0x7007, 0x0003, 0x701b, 0x39d1,
+	0x007c, 0x6830, 0xa086, 0x0100, 0x2009, 0x0004, 0x0040, 0x2b56,
+	0x0078, 0x2b2c, 0x81ff, 0x2009, 0x0001, 0x00c0, 0x2b56, 0x6000,
+	0xa086, 0x0003, 0x2009, 0x0007, 0x00c0, 0x2b56, 0x1078, 0x3542,
+	0x0040, 0x2b5a, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x2009,
+	0x0009, 0x00c0, 0x2b56, 0x0c7e, 0x1078, 0x3518, 0x0c7f, 0x2009,
+	0x0002, 0x0040, 0x2b56, 0xad80, 0x000f, 0x2009, 0x0008, 0x7a2c,
+	0x7b28, 0x7c3c, 0x7d38, 0x1078, 0x3562, 0x701b, 0x3a08, 0x007c,
+	0x0d7e, 0xade8, 0x000f, 0x6800, 0xa086, 0x0500, 0x00c0, 0x3a1b,
+	0x6804, 0xa005, 0x00c0, 0x3a1b, 0x6808, 0xa084, 0xff00, 0x00c0,
+	0x3a1b, 0x0078, 0x3a1e, 0x0d7f, 0x00c0, 0x2b5a, 0x0d7f, 0x6837,
+	0x0000, 0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x0c7e, 0x1078,
+	0x3542, 0x00c0, 0x3a2e, 0x0c7f, 0x0078, 0x2b5a, 0x1078, 0x8e52,
+	0x2009, 0x0003, 0x0c7f, 0x0040, 0x2b56, 0x7007, 0x0003, 0x701b,
+	0x3a3a, 0x007c, 0x6830, 0xa086, 0x0100, 0x2009, 0x0004, 0x0040,
+	0x2b56, 0x0078, 0x2b2c, 0x127e, 0x0c7e, 0x0e7e, 0x2061, 0x0100,
+	0x2071, 0xa300, 0x6044, 0xd0a4, 0x00c0, 0x3a6c, 0xd084, 0x0040,
+	0x3a55, 0x1078, 0x3bcc, 0x0078, 0x3a68, 0xd08c, 0x0040, 0x3a5c,
+	0x1078, 0x3ae3, 0x0078, 0x3a68, 0xd094, 0x0040, 0x3a63, 0x1078,
+	0x3ab7, 0x0078, 0x3a68, 0xd09c, 0x0040, 0x3a68, 0x1078, 0x3a76,
+	0x0e7f, 0x0c7f, 0x127f, 0x007c, 0x017e, 0x6128, 0xd19c, 0x00c0,
+	0x3a73, 0xc19d, 0x612a, 0x017f, 0x0078, 0x3a68, 0x624c, 0xa286,
+	0xf0f0, 0x00c0, 0x3a87, 0x6048, 0xa086, 0xf0f0, 0x0040, 0x3a87,
+	0x624a, 0x6043, 0x0090, 0x6043, 0x0010, 0x0078, 0x3ab6, 0xa294,
+	0xff00, 0xa296, 0xf700, 0x0040, 0x3a9c, 0x7134, 0xd1a4, 0x00c0,
+	0x3a9c, 0x6240, 0xa294, 0x0010, 0x0040, 0x3a9c, 0x2009, 0x00f7,
+	0x1078, 0x41de, 0x0078, 0x3ab6, 0x6043, 0x0040, 0x6043, 0x0000,
+	0x7073, 0x0000, 0x708b, 0x0001, 0x70af, 0x0000, 0x70cb, 0x0000,
+	0x2009, 0xa9c0, 0x200b, 0x0000, 0x7083, 0x0000, 0x7077, 0x000f,
+	0x2009, 0x000f, 0x2011, 0x4122, 0x1078, 0x596c, 0x007c, 0x157e,
+	0x7074, 0xa005, 0x00c0, 0x3ae1, 0x2011, 0x4122, 0x1078, 0x58d4,
+	0x6040, 0xa094, 0x0010, 0xa285, 0x0020, 0x6042, 0x20a9, 0x00c8,
+	0x6044, 0xd08c, 0x00c0, 0x3ada, 0x00f0, 0x3ac8, 0x6242, 0x7087,
+	0x0000, 0x6040, 0xa094, 0x0010, 0xa285, 0x0080, 0x6042, 0x6242,
+	0x0078, 0x3ae1, 0x6242, 0x7087, 0x0000, 0x707b, 0x0000, 0x0078,
+	0x3ae1, 0x157f, 0x007c, 0x7078, 0xa08a, 0x0003, 0x00c8, 0x3aec,
+	0x1079, 0x3aef, 0x0078, 0x3aee, 0x1078, 0x1328, 0x007c, 0x3af2,
+	0x3b41, 0x3bcb, 0x0f7e, 0x707b, 0x0001, 0x20e1, 0xa000, 0x20e1,
+	0x8700, 0x1078, 0x218b, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2079,
+	0xa800, 0x207b, 0x2200, 0x7807, 0x00ef, 0x780b, 0x0000, 0x780f,
+	0x00ef, 0x7813, 0x0138, 0x7817, 0x0000, 0x781b, 0x0000, 0x781f,
+	0x0000, 0x7823, 0xffff, 0x7827, 0xffff, 0x782b, 0x0000, 0x782f,
+	0x0000, 0x2079, 0xa80c, 0x207b, 0x1101, 0x7807, 0x0000, 0x2099,
+	0xa305, 0x20a1, 0xa80e, 0x20a9, 0x0004, 0x53a3, 0x2079, 0xa812,
+	0x207b, 0x0000, 0x7807, 0x0000, 0x2099, 0xa800, 0x20a1, 0x020b,
+	0x20a9, 0x0014, 0x53a6, 0x60c3, 0x000c, 0x600f, 0x0000, 0x1078,
+	0x4158, 0x0f7f, 0x707f, 0x0000, 0x6043, 0x0008, 0x6043, 0x0000,
+	0x007c, 0x0d7e, 0x707c, 0x707f, 0x0000, 0xa025, 0x0040, 0x3bb5,
+	0x6020, 0xd0b4, 0x00c0, 0x3bb3, 0x7188, 0x81ff, 0x0040, 0x3ba2,
+	0xa486, 0x000c, 0x00c0, 0x3bad, 0xa480, 0x0018, 0x8004, 0x20a8,
+	0x2011, 0xa880, 0x2019, 0xa800, 0x220c, 0x2304, 0xa106, 0x00c0,
+	0x3b79, 0x8210, 0x8318, 0x00f0, 0x3b5c, 0x6043, 0x0004, 0x608b,
+	0xbc94, 0x608f, 0xf0f0, 0x6043, 0x0006, 0x707b, 0x0002, 0x7087,
+	0x0002, 0x2009, 0x07d0, 0x2011, 0x4129, 0x1078, 0x596c, 0x0078,
+	0x3bb3, 0x2069, 0xa880, 0x6930, 0xa18e, 0x1101, 0x00c0, 0x3bad,
+	0x6834, 0xa005, 0x00c0, 0x3bad, 0x6900, 0xa18c, 0x00ff, 0x00c0,
+	0x3b8d, 0x6804, 0xa005, 0x0040, 0x3ba2, 0x2011, 0xa88e, 0x2019,
+	0xa305, 0x20a9, 0x0004, 0x220c, 0x2304, 0xa102, 0x0048, 0x3ba0,
+	0x00c0, 0x3bad, 0x8210, 0x8318, 0x00f0, 0x3b93, 0x0078, 0x3bad,
+	0x708b, 0x0000, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xa880,
+	0x20a1, 0x020b, 0x20a9, 0x0014, 0x53a6, 0x6043, 0x0008, 0x6043,
+	0x0000, 0x0078, 0x3bb5, 0x0d7f, 0x007c, 0x6020, 0xd0b4, 0x00c0,
+	0x3bb3, 0x60c3, 0x000c, 0x2011, 0xa5b5, 0x2013, 0x0000, 0x707f,
+	0x0000, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7, 0x9575, 0x1078,
+	0x6c38, 0x0078, 0x3bb3, 0x007c, 0x7084, 0xa08a, 0x001d, 0x00c8,
+	0x3bd5, 0x1079, 0x3bd8, 0x0078, 0x3bd7, 0x1078, 0x1328, 0x007c,
+	0x3c02, 0x3c11, 0x3c40, 0x3c59, 0x3c85, 0x3cb1, 0x3cdd, 0x3d13,
+	0x3d3f, 0x3d67, 0x3daa, 0x3dd4, 0x3df6, 0x3e0c, 0x3e32, 0x3e45,
+	0x3e4e, 0x3e7e, 0x3eaa, 0x3ed6, 0x3f02, 0x3f38, 0x3f7d, 0x3fac,
+	0x3fce, 0x4010, 0x4036, 0x404f, 0x4050, 0x0c7e, 0x2061, 0xa300,
+	0x6003, 0x0007, 0x2061, 0x0100, 0x6004, 0xa084, 0xfff9, 0x6006,
+	0x0c7f, 0x007c, 0x608b, 0xbc94, 0x608f, 0xf0f0, 0x6043, 0x0002,
+	0x7087, 0x0001, 0x2009, 0x07d0, 0x2011, 0x4129, 0x1078, 0x596c,
+	0x007c, 0x0f7e, 0x707c, 0xa086, 0x0014, 0x00c0, 0x3c3e, 0x6043,
+	0x0000, 0x6020, 0xd0b4, 0x00c0, 0x3c3e, 0x2079, 0xa880, 0x7a30,
+	0xa296, 0x1102, 0x00c0, 0x3c3c, 0x7834, 0xa005, 0x00c0, 0x3c3c,
+	0x7a38, 0xd2fc, 0x0040, 0x3c32, 0x70ac, 0xa005, 0x00c0, 0x3c32,
+	0x70af, 0x0001, 0x2011, 0x4129, 0x1078, 0x58d4, 0x7087, 0x0010,
+	0x1078, 0x3e4e, 0x0078, 0x3c3e, 0x1078, 0x4171, 0x0f7f, 0x007c,
+	0x7087, 0x0003, 0x6043, 0x0004, 0x2011, 0x4129, 0x1078, 0x58d4,
+	0x1078, 0x41c6, 0x20a3, 0x1102, 0x20a3, 0x0000, 0x20a9, 0x000a,
+	0x20a3, 0x0000, 0x00f0, 0x3c50, 0x60c3, 0x0014, 0x1078, 0x4158,
+	0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040, 0x3c83, 0x2011, 0x4129,
+	0x1078, 0x58d4, 0xa086, 0x0014, 0x00c0, 0x3c81, 0x2079, 0xa880,
+	0x7a30, 0xa296, 0x1102, 0x00c0, 0x3c81, 0x7834, 0xa005, 0x00c0,
+	0x3c81, 0x7a38, 0xd2fc, 0x0040, 0x3c7b, 0x70ac, 0xa005, 0x00c0,
+	0x3c7b, 0x70af, 0x0001, 0x7087, 0x0004, 0x1078, 0x3c85, 0x0078,
+	0x3c83, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087, 0x0005, 0x1078,
+	0x41c6, 0x20a3, 0x1103, 0x20a3, 0x0000, 0x3430, 0x2011, 0xa88e,
+	0x1078, 0x4211, 0x00c0, 0x3ca3, 0x7070, 0xa005, 0x00c0, 0x3ca3,
+	0x714c, 0xa186, 0xffff, 0x0040, 0x3ca3, 0x1078, 0x40ea, 0x0040,
+	0x3ca3, 0x1078, 0x41f5, 0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x1078, 0x4158,
+	0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040, 0x3cdb, 0x2011, 0x4129,
+	0x1078, 0x58d4, 0xa086, 0x0014, 0x00c0, 0x3cd9, 0x2079, 0xa880,
+	0x7a30, 0xa296, 0x1103, 0x00c0, 0x3cd9, 0x7834, 0xa005, 0x00c0,
+	0x3cd9, 0x7a38, 0xd2fc, 0x0040, 0x3cd3, 0x70ac, 0xa005, 0x00c0,
+	0x3cd3, 0x70af, 0x0001, 0x7087, 0x0006, 0x1078, 0x3cdd, 0x0078,
+	0x3cdb, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087, 0x0007, 0x1078,
+	0x41c6, 0x20a3, 0x1104, 0x20a3, 0x0000, 0x3430, 0x2011, 0xa88e,
+	0x1078, 0x4211, 0x00c0, 0x3d05, 0x7070, 0xa005, 0x00c0, 0x3d05,
+	0x7150, 0xa186, 0xffff, 0x0040, 0x3d05, 0xa180, 0x293f, 0x200c,
+	0xa18c, 0xff00, 0x810f, 0x1078, 0x40ea, 0x0040, 0x3d05, 0x1078,
+	0x378b, 0x0040, 0x3d05, 0x1078, 0x2500, 0x20a9, 0x0008, 0x2298,
+	0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014,
+	0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040, 0x3d3d,
+	0x2011, 0x4129, 0x1078, 0x58d4, 0xa086, 0x0014, 0x00c0, 0x3d3b,
+	0x2079, 0xa880, 0x7a30, 0xa296, 0x1104, 0x00c0, 0x3d3b, 0x7834,
+	0xa005, 0x00c0, 0x3d3b, 0x7a38, 0xd2fc, 0x0040, 0x3d35, 0x70ac,
+	0xa005, 0x00c0, 0x3d35, 0x70af, 0x0001, 0x7087, 0x0008, 0x1078,
+	0x3d3f, 0x0078, 0x3d3d, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087,
+	0x0009, 0x1078, 0x41c6, 0x20a3, 0x1105, 0x20a3, 0x0100, 0x3430,
+	0x1078, 0x4211, 0x00c0, 0x3d58, 0x7070, 0xa005, 0x00c0, 0x3d58,
+	0x1078, 0x4051, 0x00c0, 0x3d62, 0xa085, 0x0001, 0x1078, 0x2500,
+	0x20a9, 0x0008, 0x2099, 0xa88e, 0x26a0, 0x53a6, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x60c3, 0x0014, 0x1078, 0x4158, 0x007c, 0x0f7e,
+	0x707c, 0xa005, 0x0040, 0x3da8, 0x2011, 0x4129, 0x1078, 0x58d4,
+	0xa086, 0x0014, 0x00c0, 0x3da6, 0x2079, 0xa880, 0x7a30, 0xa296,
+	0x1105, 0x00c0, 0x3da6, 0x7834, 0x2011, 0x0100, 0xa21e, 0x00c0,
+	0x3d91, 0x7a38, 0xd2fc, 0x0040, 0x3d8b, 0x70ac, 0xa005, 0x00c0,
+	0x3d8b, 0x70af, 0x0001, 0x7087, 0x000a, 0x1078, 0x3daa, 0x0078,
+	0x3da8, 0xa005, 0x00c0, 0x3da6, 0x7a38, 0xd2fc, 0x0040, 0x3d9e,
+	0x70ac, 0xa005, 0x00c0, 0x3d9e, 0x70af, 0x0001, 0x7083, 0x0000,
+	0x7087, 0x000e, 0x1078, 0x3e32, 0x0078, 0x3da8, 0x1078, 0x4171,
+	0x0f7f, 0x007c, 0x7087, 0x000b, 0x2011, 0xa80e, 0x22a0, 0x20a9,
+	0x0040, 0x2019, 0xffff, 0x43a4, 0x20a9, 0x0002, 0x2009, 0x0000,
+	0x41a4, 0x1078, 0x41c6, 0x20a3, 0x1106, 0x20a3, 0x0000, 0x1078,
+	0x4211, 0x0040, 0x3dc7, 0x2013, 0x0000, 0x0078, 0x3dcb, 0x6030,
+	0xa085, 0x0100, 0x2012, 0x2298, 0x20a9, 0x0042, 0x53a6, 0x60c3,
+	0x0084, 0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040,
+	0x3df4, 0x2011, 0x4129, 0x1078, 0x58d4, 0xa086, 0x0084, 0x00c0,
+	0x3df2, 0x2079, 0xa880, 0x7a30, 0xa296, 0x1106, 0x00c0, 0x3df2,
+	0x7834, 0xa005, 0x00c0, 0x3df2, 0x7087, 0x000c, 0x1078, 0x3df6,
+	0x0078, 0x3df4, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087, 0x000d,
+	0x1078, 0x41c6, 0x20a3, 0x1107, 0x20a3, 0x0000, 0x2099, 0xa88e,
+	0x20a9, 0x0040, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3,
+	0x0084, 0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040,
+	0x3e30, 0x2011, 0x4129, 0x1078, 0x58d4, 0xa086, 0x0084, 0x00c0,
+	0x3e2e, 0x2079, 0xa880, 0x7a30, 0xa296, 0x1107, 0x00c0, 0x3e2e,
+	0x7834, 0xa005, 0x00c0, 0x3e2e, 0x7083, 0x0001, 0x1078, 0x41b8,
+	0x7087, 0x000e, 0x1078, 0x3e32, 0x0078, 0x3e30, 0x1078, 0x4171,
+	0x0f7f, 0x007c, 0x7087, 0x000f, 0x707f, 0x0000, 0x608b, 0xbc85,
+	0x608f, 0xb5b5, 0x6043, 0x0005, 0x6043, 0x0004, 0x2009, 0x07d0,
+	0x2011, 0x4129, 0x1078, 0x58c7, 0x007c, 0x707c, 0xa005, 0x0040,
+	0x3e4d, 0x2011, 0x4129, 0x1078, 0x58d4, 0x007c, 0x7087, 0x0011,
+	0x1078, 0x4211, 0x00c0, 0x3e67, 0x7168, 0x81ff, 0x0040, 0x3e67,
+	0x2009, 0x0000, 0x706c, 0xa084, 0x00ff, 0x1078, 0x24e3, 0xa186,
+	0x0080, 0x0040, 0x3e67, 0x2011, 0xa88e, 0x1078, 0x40ea, 0x20e1,
+	0x9080, 0x20e1, 0x4000, 0x2099, 0xa880, 0x20a1, 0x020b, 0x747c,
+	0xa480, 0x0018, 0xa080, 0x0007, 0xa084, 0x03f8, 0x8004, 0x20a8,
+	0x53a6, 0x60c3, 0x0014, 0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c,
+	0xa005, 0x0040, 0x3ea8, 0x2011, 0x4129, 0x1078, 0x58d4, 0xa086,
+	0x0014, 0x00c0, 0x3ea6, 0x2079, 0xa880, 0x7a30, 0xa296, 0x1103,
+	0x00c0, 0x3ea6, 0x7834, 0xa005, 0x00c0, 0x3ea6, 0x7a38, 0xd2fc,
+	0x0040, 0x3ea0, 0x70ac, 0xa005, 0x00c0, 0x3ea0, 0x70af, 0x0001,
+	0x7087, 0x0012, 0x1078, 0x3eaa, 0x0078, 0x3ea8, 0x1078, 0x4171,
+	0x0f7f, 0x007c, 0x7087, 0x0013, 0x1078, 0x41d2, 0x20a3, 0x1103,
+	0x20a3, 0x0000, 0x3430, 0x2011, 0xa88e, 0x1078, 0x4211, 0x00c0,
+	0x3ec8, 0x7070, 0xa005, 0x00c0, 0x3ec8, 0x714c, 0xa186, 0xffff,
+	0x0040, 0x3ec8, 0x1078, 0x40ea, 0x0040, 0x3ec8, 0x1078, 0x41f5,
+	0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x60c3, 0x0014, 0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c,
+	0xa005, 0x0040, 0x3f00, 0x2011, 0x4129, 0x1078, 0x58d4, 0xa086,
+	0x0014, 0x00c0, 0x3efe, 0x2079, 0xa880, 0x7a30, 0xa296, 0x1104,
+	0x00c0, 0x3efe, 0x7834, 0xa005, 0x00c0, 0x3efe, 0x7a38, 0xd2fc,
+	0x0040, 0x3ef8, 0x70ac, 0xa005, 0x00c0, 0x3ef8, 0x70af, 0x0001,
+	0x7087, 0x0014, 0x1078, 0x3f02, 0x0078, 0x3f00, 0x1078, 0x4171,
+	0x0f7f, 0x007c, 0x7087, 0x0015, 0x1078, 0x41d2, 0x20a3, 0x1104,
+	0x20a3, 0x0000, 0x3430, 0x2011, 0xa88e, 0x1078, 0x4211, 0x00c0,
+	0x3f2a, 0x7070, 0xa005, 0x00c0, 0x3f2a, 0x7150, 0xa186, 0xffff,
+	0x0040, 0x3f2a, 0xa180, 0x293f, 0x200c, 0xa18c, 0xff00, 0x810f,
+	0x1078, 0x40ea, 0x0040, 0x3f2a, 0x1078, 0x378b, 0x0040, 0x3f2a,
+	0x1078, 0x2500, 0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x1078, 0x4158, 0x007c,
+	0x0f7e, 0x707c, 0xa005, 0x0040, 0x3f7b, 0x2011, 0x4129, 0x1078,
+	0x58d4, 0xa086, 0x0014, 0x00c0, 0x3f79, 0x2079, 0xa880, 0x7a30,
+	0xa296, 0x1105, 0x00c0, 0x3f79, 0x7834, 0x2011, 0x0100, 0xa21e,
+	0x00c0, 0x3f5e, 0x7a38, 0xd2fc, 0x0040, 0x3f5c, 0x70ac, 0xa005,
+	0x00c0, 0x3f5c, 0x70af, 0x0001, 0x0078, 0x3f6d, 0xa005, 0x00c0,
+	0x3f79, 0x7a38, 0xd2fc, 0x0040, 0x3f6b, 0x70ac, 0xa005, 0x00c0,
+	0x3f6b, 0x70af, 0x0001, 0x7083, 0x0000, 0x7a38, 0xd2f4, 0x0040,
+	0x3f73, 0x70cb, 0x0008, 0x7087, 0x0016, 0x1078, 0x3f7d, 0x0078,
+	0x3f7b, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x20e1, 0x9080, 0x20e1,
+	0x4000, 0x2099, 0xa880, 0x20a1, 0x020b, 0x20a9, 0x000e, 0x53a6,
+	0x3430, 0x2011, 0xa88e, 0x7087, 0x0017, 0x1078, 0x4211, 0x00c0,
+	0x3f9d, 0x7070, 0xa005, 0x00c0, 0x3f9d, 0x1078, 0x4051, 0x00c0,
+	0x3fa7, 0xa085, 0x0001, 0x1078, 0x2500, 0x20a9, 0x0008, 0x2099,
+	0xa88e, 0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3,
+	0x0014, 0x1078, 0x4158, 0x007c, 0x0f7e, 0x707c, 0xa005, 0x0040,
+	0x3fcc, 0x2011, 0x4129, 0x1078, 0x58d4, 0xa086, 0x0084, 0x00c0,
+	0x3fca, 0x2079, 0xa880, 0x7a30, 0xa296, 0x1106, 0x00c0, 0x3fca,
+	0x7834, 0xa005, 0x00c0, 0x3fca, 0x7087, 0x0018, 0x1078, 0x3fce,
+	0x0078, 0x3fcc, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087, 0x0019,
+	0x1078, 0x41d2, 0x20a3, 0x1106, 0x20a3, 0x0000, 0x3430, 0x2099,
+	0xa88e, 0x2039, 0xa80e, 0x27a0, 0x20a9, 0x0040, 0x53a3, 0x1078,
+	0x4211, 0x00c0, 0x4002, 0x2728, 0x2514, 0x8207, 0xa084, 0x00ff,
+	0x8000, 0x2018, 0xa294, 0x00ff, 0x8007, 0xa205, 0x202a, 0x6030,
+	0x2310, 0x8214, 0xa2a0, 0xa80e, 0x2414, 0xa38c, 0x0001, 0x0040,
+	0x3ffd, 0xa294, 0xff00, 0x0078, 0x4000, 0xa294, 0x00ff, 0x8007,
+	0xa215, 0x2222, 0x2798, 0x26a0, 0x20a9, 0x0040, 0x53a6, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x0084, 0x1078, 0x4158, 0x007c,
+	0x0f7e, 0x707c, 0xa005, 0x0040, 0x4034, 0x2011, 0x4129, 0x1078,
+	0x58d4, 0xa086, 0x0084, 0x00c0, 0x4032, 0x2079, 0xa880, 0x7a30,
+	0xa296, 0x1107, 0x00c0, 0x4032, 0x7834, 0xa005, 0x00c0, 0x4032,
+	0x7083, 0x0001, 0x1078, 0x41b8, 0x7087, 0x001a, 0x1078, 0x4036,
+	0x0078, 0x4034, 0x1078, 0x4171, 0x0f7f, 0x007c, 0x7087, 0x001b,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xa880, 0x20a1, 0x020b,
+	0x747c, 0xa480, 0x0018, 0xa080, 0x0007, 0xa084, 0x03f8, 0x8004,
+	0x20a8, 0x53a6, 0x60c3, 0x0084, 0x1078, 0x4158, 0x007c, 0x007c,
+	0x007c, 0x087e, 0x097e, 0x2029, 0xa352, 0x252c, 0x20a9, 0x0008,
+	0x2041, 0xa80e, 0x28a0, 0x2099, 0xa88e, 0x53a3, 0x20a9, 0x0008,
+	0x2011, 0x0007, 0xd5d4, 0x0040, 0x4067, 0x2011, 0x0000, 0x2800,
+	0xa200, 0x200c, 0xa1a6, 0xffff, 0x00c0, 0x4079, 0xd5d4, 0x0040,
+	0x4074, 0x8210, 0x0078, 0x4075, 0x8211, 0x00f0, 0x4067, 0x0078,
+	0x40e1, 0x82ff, 0x00c0, 0x408b, 0xd5d4, 0x0040, 0x4085, 0xa1a6,
+	0x3fff, 0x0040, 0x4071, 0x0078, 0x4089, 0xa1a6, 0x3fff, 0x0040,
+	0x40e1, 0xa18d, 0xc000, 0x20a9, 0x0010, 0x2019, 0x0001, 0xd5d4,
+	0x0040, 0x4094, 0x2019, 0x0010, 0x2120, 0xd5d4, 0x0040, 0x409b,
+	0x8423, 0x0078, 0x409c, 0x8424, 0x00c8, 0x40a9, 0xd5d4, 0x0040,
+	0x40a4, 0x8319, 0x0078, 0x40a5, 0x8318, 0x00f0, 0x4095, 0x0078,
+	0x40e1, 0x23a8, 0x2021, 0x0001, 0x8426, 0x8425, 0x00f0, 0x40ad,
+	0x2328, 0x8529, 0xa2be, 0x0007, 0x0040, 0x40c1, 0x007e, 0x2039,
+	0x0007, 0x2200, 0xa73a, 0x007f, 0x27a8, 0xa5a8, 0x0010, 0x00f0,
+	0x40bd, 0x754e, 0xa5c8, 0x293f, 0x292c, 0xa5ac, 0x00ff, 0x6532,
+	0x60e7, 0x0000, 0x65ea, 0x706b, 0x0000, 0x756e, 0x2018, 0x2304,
+	0xa405, 0x201a, 0x7073, 0x0001, 0x26a0, 0x2898, 0x20a9, 0x0008,
+	0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0xa085, 0x0001, 0x0078,
+	0x40e7, 0xa006, 0x0078, 0x40e7, 0xa006, 0x1078, 0x1328, 0x097f,
+	0x087f, 0x007c, 0x2118, 0x2021, 0x0000, 0x2001, 0x0007, 0xa39a,
+	0x0010, 0x0048, 0x40f7, 0x8420, 0x8001, 0x0078, 0x40ef, 0x2118,
+	0x84ff, 0x0040, 0x4100, 0xa39a, 0x0010, 0x8421, 0x00c0, 0x40fb,
+	0x2021, 0x0001, 0x83ff, 0x0040, 0x4109, 0x8423, 0x8319, 0x00c0,
+	0x4105, 0xa238, 0x2704, 0xa42c, 0x00c0, 0x4121, 0xa405, 0x203a,
+	0x714e, 0xa1a0, 0x293f, 0x242c, 0xa5ac, 0x00ff, 0x6532, 0x60e7,
+	0x0000, 0x65ea, 0x706b, 0x0000, 0x756e, 0x7073, 0x0001, 0xa084,
+	0x0000, 0x007c, 0x0e7e, 0x2071, 0xa300, 0x7077, 0x0000, 0x0e7f,
+	0x007c, 0x0e7e, 0x0f7e, 0x2001, 0x0002, 0x1078, 0x5975, 0x2079,
+	0x0100, 0x2071, 0x0140, 0x1078, 0x6c41, 0x7004, 0xa084, 0x4000,
+	0x0040, 0x413e, 0x7003, 0x1000, 0x7003, 0x0000, 0x127e, 0x2091,
+	0x8000, 0x2071, 0xa321, 0x2073, 0x0000, 0x7840, 0x027e, 0x017e,
+	0x2009, 0x00f7, 0x1078, 0x41de, 0x017f, 0xa094, 0x0010, 0xa285,
+	0x0080, 0x7842, 0x7a42, 0x027f, 0x127f, 0x0f7f, 0x0e7f, 0x007c,
+	0x127e, 0x2091, 0x8000, 0x2011, 0xa5b5, 0x2013, 0x0000, 0x707f,
+	0x0000, 0x127f, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7, 0x9575,
+	0x1078, 0x6c38, 0x2009, 0x07d0, 0x2011, 0x4129, 0x1078, 0x596c,
+	0x007c, 0x017e, 0x027e, 0x0c7e, 0x127e, 0x2091, 0x8000, 0x2009,
+	0x00f7, 0x1078, 0x41de, 0x2061, 0xa5be, 0x601b, 0x0000, 0x601f,
+	0x0000, 0x2061, 0xa300, 0x6003, 0x0001, 0x2061, 0x0100, 0x6043,
+	0x0090, 0x6043, 0x0010, 0x2009, 0x002d, 0x2011, 0x4196, 0x1078,
+	0x58c7, 0x127f, 0x0c7f, 0x027f, 0x017f, 0x007c, 0x0e7e, 0x007e,
+	0x127e, 0x2091, 0x8000, 0x2001, 0x0001, 0x1078, 0x5975, 0x2071,
+	0x0100, 0x1078, 0x6c41, 0x2071, 0x0140, 0x7004, 0xa084, 0x4000,
+	0x0040, 0x41ae, 0x7003, 0x1000, 0x7003, 0x0000, 0x2001, 0x0001,
+	0x1078, 0x2480, 0x1078, 0x4171, 0x127f, 0x007f, 0x0e7f, 0x007c,
+	0x20a9, 0x0040, 0x20a1, 0xa9c0, 0x2099, 0xa88e, 0x3304, 0x8007,
+	0x20a2, 0x9398, 0x94a0, 0x00f0, 0x41be, 0x007c, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x2099, 0xa800, 0x20a1, 0x020b, 0x20a9, 0x000c,
+	0x53a6, 0x007c, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xa880,
+	0x20a1, 0x020b, 0x20a9, 0x000c, 0x53a6, 0x007c, 0x0c7e, 0x007e,
+	0x2061, 0x0100, 0x810f, 0x2001, 0xa32e, 0x2004, 0xa005, 0x00c0,
+	0x41ef, 0x6030, 0xa084, 0x00ff, 0xa105, 0x0078, 0x41f1, 0xa185,
+	0x00f7, 0x604a, 0x007f, 0x0c7f, 0x007c, 0x017e, 0x047e, 0x2001,
+	0xa352, 0x2004, 0xd0a4, 0x0040, 0x4208, 0xa006, 0x2020, 0x2009,
+	0x002a, 0x1078, 0x9ec0, 0x2001, 0xa30c, 0x200c, 0xc195, 0x2102,
+	0x2019, 0x002a, 0x2009, 0x0000, 0x1078, 0x27e2, 0x047f, 0x017f,
+	0x007c, 0x007e, 0x2001, 0xa30c, 0x2004, 0xd09c, 0x0040, 0x4218,
+	0x007f, 0x007c, 0x007e, 0x017e, 0x127e, 0x2091, 0x8000, 0x2001,
+	0x0101, 0x200c, 0xa18d, 0x0006, 0x2102, 0x127f, 0x017f, 0x007f,
+	0x007c, 0x157e, 0x20a9, 0x00ff, 0x2009, 0xa434, 0xa006, 0x200a,
+	0x8108, 0x00f0, 0x422f, 0x157f, 0x007c, 0x0d7e, 0x037e, 0x157e,
+	0x137e, 0x147e, 0x2069, 0xa351, 0xa006, 0x6002, 0x6007, 0x0707,
+	0x600a, 0x600e, 0x6012, 0xa198, 0x293f, 0x231c, 0xa39c, 0x00ff,
+	0x6316, 0x20a9, 0x0004, 0xac98, 0x0006, 0x23a0, 0x40a4, 0x20a9,
+	0x0004, 0xac98, 0x000a, 0x23a0, 0x40a4, 0x603e, 0x6042, 0x604e,
+	0x6052, 0x6056, 0x605a, 0x605e, 0x6062, 0x6066, 0x606a, 0x606e,
+	0x6072, 0x6076, 0x607a, 0x607e, 0x6082, 0x6086, 0x608a, 0x608e,
+	0x6092, 0x6096, 0x609a, 0x609e, 0x60ae, 0x61a2, 0x0d7e, 0x60a4,
+	0xa06d, 0x0040, 0x4275, 0x1078, 0x139a, 0x60a7, 0x0000, 0x60a8,
+	0xa06d, 0x0040, 0x427d, 0x1078, 0x139a, 0x60ab, 0x0000, 0x0d7f,
+	0xa006, 0x604a, 0x6810, 0x603a, 0x680c, 0x6046, 0x6814, 0xa084,
+	0x00ff, 0x6042, 0x147f, 0x137f, 0x157f, 0x037f, 0x0d7f, 0x007c,
+	0x127e, 0x2091, 0x8000, 0x6944, 0x6e48, 0xa684, 0x3fff, 0xa082,
+	0x4000, 0x00c8, 0x4361, 0xa18c, 0xff00, 0x810f, 0xa182, 0x00ff,
+	0x00c8, 0x4367, 0x2001, 0xa30c, 0x2004, 0xa084, 0x0003, 0x0040,
+	0x42c2, 0x2001, 0xa30c, 0x2004, 0xd084, 0x00c0, 0x4342, 0xa188,
+	0xa434, 0x2104, 0xa065, 0x0040, 0x4342, 0x6004, 0xa084, 0x00ff,
+	0xa08e, 0x0006, 0x00c0, 0x4342, 0x6000, 0xd0c4, 0x0040, 0x4342,
+	0x0078, 0x42cf, 0xa188, 0xa434, 0x2104, 0xa065, 0x0040, 0x4326,
+	0x6004, 0xa084, 0x00ff, 0xa08e, 0x0006, 0x00c0, 0x432c, 0x60a4,
+	0xa00d, 0x0040, 0x42d7, 0x1078, 0x4749, 0x0040, 0x4320, 0x60a8,
+	0xa00d, 0x0040, 0x42f1, 0x1078, 0x479a, 0x00c0, 0x42f1, 0x694c,
+	0xd1fc, 0x00c0, 0x42e7, 0x1078, 0x441c, 0x0078, 0x431b, 0x1078,
+	0x43d6, 0x694c, 0xd1ec, 0x00c0, 0x431b, 0x1078, 0x460a, 0x0078,
+	0x431b, 0x694c, 0xa184, 0xa000, 0x0040, 0x430b, 0xd1ec, 0x0040,
+	0x4304, 0xd1fc, 0x0040, 0x4300, 0x1078, 0x461b, 0x0078, 0x4307,
+	0x1078, 0x461b, 0x0078, 0x430b, 0xd1fc, 0x0040, 0x430b, 0x1078,
+	0x43d6, 0x0078, 0x431b, 0x6050, 0xa00d, 0x0040, 0x4316, 0x2d00,
+	0x200a, 0x6803, 0x0000, 0x6052, 0x0078, 0x431b, 0x2d00, 0x6052,
+	0x604e, 0x6803, 0x0000, 0x1078, 0x5c17, 0xa006, 0x127f, 0x007c,
+	0x2001, 0x0005, 0x2009, 0x0000, 0x0078, 0x436b, 0x2001, 0x0028,
+	0x2009, 0x0000, 0x0078, 0x436b, 0xa082, 0x0006, 0x00c8, 0x4342,
+	0x60a0, 0xd0bc, 0x00c0, 0x433e, 0x6100, 0xd1fc, 0x0040, 0x42cf,
+	0x2001, 0x0029, 0x2009, 0x1000, 0x0078, 0x436b, 0x2001, 0x0028,
+	0x0078, 0x435d, 0x2009, 0xa30c, 0x210c, 0xd18c, 0x0040, 0x434c,
+	0x2001, 0x0004, 0x0078, 0x435d, 0xd184, 0x0040, 0x4353, 0x2001,
+	0x0004, 0x0078, 0x435d, 0x2001, 0x0029, 0x6100, 0xd1fc, 0x0040,
+	0x435d, 0x2009, 0x1000, 0x0078, 0x436b, 0x2009, 0x0000, 0x0078,
+	0x436b, 0x2001, 0x0029, 0x2009, 0x0000, 0x0078, 0x436b, 0x2001,
+	0x0029, 0x2009, 0x0000, 0xa005, 0x127f, 0x007c, 0x6944, 0x6e48,
+	0xa684, 0x3fff, 0xa082, 0x4000, 0x00c8, 0x43bb, 0xa18c, 0xff00,
+	0x810f, 0xa182, 0x00ff, 0x00c8, 0x43a1, 0xa188, 0xa434, 0x2104,
+	0xa065, 0x0040, 0x43a1, 0x6004, 0xa084, 0x00ff, 0xa08e, 0x0006,
+	0x00c0, 0x43a7, 0x684c, 0xd0ec, 0x0040, 0x4394, 0x1078, 0x461b,
+	0x1078, 0x43d6, 0x0078, 0x439c, 0x1078, 0x43d6, 0x684c, 0xd0fc,
+	0x0040, 0x439c, 0x1078, 0x460a, 0x1078, 0x4663, 0xa006, 0x0078,
+	0x43bf, 0x2001, 0x0028, 0x2009, 0x0000, 0x0078, 0x43bf, 0xa082,
+	0x0006, 0x00c8, 0x43b5, 0x6100, 0xd1fc, 0x0040, 0x438a, 0x2001,
+	0x0029, 0x2009, 0x1000, 0x0078, 0x43bf, 0x2001, 0x0029, 0x2009,
+	0x0000, 0x0078, 0x43bf, 0x2001, 0x0029, 0x2009, 0x0000, 0xa005,
+	0x007c, 0x127e, 0x2091, 0x8000, 0x6050, 0xa00d, 0x0040, 0x43cf,
+	0x2d00, 0x200a, 0x6803, 0x0000, 0x6052, 0x127f, 0x007c, 0x2d00,
+	0x6052, 0x604e, 0x6803, 0x0000, 0x0078, 0x43cd, 0x127e, 0x2091,
+	0x8000, 0x604c, 0xa005, 0x0040, 0x43ec, 0x0e7e, 0x2071, 0xa5ab,
+	0x7004, 0xa086, 0x0002, 0x0040, 0x43f3, 0x0e7f, 0x604c, 0x6802,
+	0x2d00, 0x604e, 0x127f, 0x007c, 0x2d00, 0x6052, 0x604e, 0x6803,
+	0x0000, 0x0078, 0x43ea, 0x701c, 0xac06, 0x00c0, 0x43e5, 0x604c,
+	0x2070, 0x7000, 0x6802, 0x2d00, 0x7002, 0x0e7f, 0x127f, 0x007c,
+	0x127e, 0x2091, 0x8000, 0x604c, 0xa06d, 0x0040, 0x440e, 0x6800,
+	0xa005, 0x00c0, 0x440c, 0x6052, 0x604e, 0xad05, 0x127f, 0x007c,
+	0x604c, 0xa06d, 0x0040, 0x441b, 0x6800, 0xa005, 0x00c0, 0x4419,
+	0x6052, 0x604e, 0xad05, 0x007c, 0x6803, 0x0000, 0x6084, 0xa00d,
+	0x0040, 0x4426, 0x2d00, 0x200a, 0x6086, 0x007c, 0x2d00, 0x6086,
+	0x6082, 0x0078, 0x4425, 0x127e, 0x0c7e, 0x027e, 0x2091, 0x8000,
+	0x6218, 0x2260, 0x6200, 0xa005, 0x0040, 0x4439, 0xc285, 0x0078,
+	0x443a, 0xc284, 0x6202, 0x027f, 0x0c7f, 0x127f, 0x007c, 0x127e,
+	0x0c7e, 0x2091, 0x8000, 0x6218, 0x2260, 0x6204, 0x007e, 0xa086,
+	0x0006, 0x00c0, 0x445e, 0x609c, 0xd0ac, 0x0040, 0x445e, 0x2001,
+	0xa352, 0x2004, 0xd0a4, 0x0040, 0x445e, 0xa284, 0xff00, 0x8007,
+	0xa086, 0x0007, 0x00c0, 0x445e, 0x2011, 0x0600, 0x007f, 0xa294,
+	0xff00, 0xa215, 0x6206, 0x007e, 0xa086, 0x0006, 0x00c0, 0x446e,
+	0x6290, 0x82ff, 0x00c0, 0x446e, 0x1078, 0x1328, 0x007f, 0x0c7f,
+	0x127f, 0x007c, 0x127e, 0x0c7e, 0x2091, 0x8000, 0x6218, 0x2260,
+	0x6204, 0x007e, 0xa086, 0x0006, 0x00c0, 0x4490, 0x609c, 0xd0a4,
+	0x0040, 0x4490, 0x2001, 0xa352, 0x2004, 0xd0ac, 0x00c0, 0x4490,
+	0xa284, 0x00ff, 0xa086, 0x0007, 0x00c0, 0x4490, 0x2011, 0x0006,
+	0x007f, 0xa294, 0x00ff, 0x8007, 0xa215, 0x6206, 0x0c7f, 0x127f,
+	0x007c, 0x027e, 0xa182, 0x00ff, 0x0048, 0x44a2, 0xa085, 0x0001,
+	0x0078, 0x44ba, 0xa190, 0xa434, 0x2204, 0xa065, 0x00c0, 0x44b9,
+	0x017e, 0x0d7e, 0x1078, 0x1366, 0x2d60, 0x0d7f, 0x017f, 0x0040,
+	0x449e, 0x2c00, 0x2012, 0x60a7, 0x0000, 0x60ab, 0x0000, 0x1078,
+	0x4235, 0xa006, 0x027f, 0x007c, 0x127e, 0x2091, 0x8000, 0x027e,
+	0xa182, 0x00ff, 0x0048, 0x44c8, 0xa085, 0x0001, 0x0078, 0x44fe,
+	0x0d7e, 0xa190, 0xa434, 0x2204, 0xa06d, 0x0040, 0x44fc, 0x2013,
+	0x0000, 0x0d7e, 0x0c7e, 0x2d60, 0x60a4, 0xa06d, 0x0040, 0x44da,
+	0x1078, 0x139a, 0x60a8, 0xa06d, 0x0040, 0x44e0, 0x1078, 0x139a,
+	0x0c7f, 0x0d7f, 0x0d7e, 0x0c7e, 0x68ac, 0x2060, 0x8cff, 0x0040,
+	0x44f8, 0x600c, 0x007e, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040,
+	0x44f3, 0x1078, 0x13aa, 0x1078, 0x753d, 0x0c7f, 0x0078, 0x44e6,
+	0x0c7f, 0x0d7f, 0x1078, 0x139a, 0x0d7f, 0xa006, 0x027f, 0x127f,
+	0x007c, 0x017e, 0xa182, 0x00ff, 0x0048, 0x450a, 0xa085, 0x0001,
+	0x0078, 0x4511, 0xa188, 0xa434, 0x2104, 0xa065, 0x0040, 0x4506,
+	0xa006, 0x017f, 0x007c, 0x0d7e, 0x157e, 0x137e, 0x147e, 0x600b,
+	0x0000, 0x600f, 0x0000, 0x6000, 0xc08c, 0x6002, 0x2069, 0xa88e,
+	0x6808, 0x605e, 0x6810, 0x6062, 0x6138, 0xa10a, 0x0048, 0x4529,
+	0x603a, 0x6814, 0x6066, 0x2099, 0xa896, 0xac88, 0x000a, 0x21a0,
+	0x20a9, 0x0004, 0x53a3, 0x2099, 0xa89a, 0xac88, 0x0006, 0x21a0,
+	0x20a9, 0x0004, 0x53a3, 0x2069, 0xa8ae, 0x6808, 0x606a, 0x690c,
+	0x616e, 0x6810, 0x6072, 0x6818, 0x6076, 0xa182, 0x0211, 0x00c8,
+	0x454d, 0x2009, 0x0008, 0x0078, 0x4577, 0xa182, 0x0259, 0x00c8,
+	0x4555, 0x2009, 0x0007, 0x0078, 0x4577, 0xa182, 0x02c1, 0x00c8,
+	0x455d, 0x2009, 0x0006, 0x0078, 0x4577, 0xa182, 0x0349, 0x00c8,
+	0x4565, 0x2009, 0x0005, 0x0078, 0x4577, 0xa182, 0x0421, 0x00c8,
+	0x456d, 0x2009, 0x0004, 0x0078, 0x4577, 0xa182, 0x0581, 0x00c8,
+	0x4575, 0x2009, 0x0003, 0x0078, 0x4577, 0x2009, 0x0002, 0x6192,
+	0x147f, 0x137f, 0x157f, 0x0d7f, 0x007c, 0x017e, 0x027e, 0x0e7e,
+	0x2071, 0xa88d, 0x2e04, 0x6896, 0x2071, 0xa88e, 0x7004, 0x689a,
+	0x701c, 0x689e, 0x6a00, 0x2009, 0xa371, 0x210c, 0xd0bc, 0x0040,
+	0x4597, 0xd1ec, 0x0040, 0x4597, 0xc2ad, 0x0078, 0x4598, 0xc2ac,
+	0xd0c4, 0x0040, 0x45a1, 0xd1e4, 0x0040, 0x45a1, 0xc2bd, 0x0078,
+	0x45a2, 0xc2bc, 0x6a02, 0x0e7f, 0x027f, 0x017f, 0x007c, 0x0d7e,
+	0x127e, 0x2091, 0x8000, 0x60a4, 0xa06d, 0x0040, 0x45cb, 0x6900,
+	0x81ff, 0x00c0, 0x45df, 0x6a04, 0xa282, 0x0010, 0x00c8, 0x45e4,
+	0xad88, 0x0004, 0x20a9, 0x0010, 0x2104, 0xa086, 0xffff, 0x0040,
+	0x45c6, 0x8108, 0x00f0, 0x45bc, 0x1078, 0x1328, 0x260a, 0x8210,
+	0x6a06, 0x0078, 0x45df, 0x1078, 0x1381, 0x0040, 0x45e4, 0x2d00,
+	0x60a6, 0x6803, 0x0000, 0xad88, 0x0004, 0x20a9, 0x0010, 0x200b,
+	0xffff, 0x8108, 0x00f0, 0x45d7, 0x6807, 0x0001, 0x6e12, 0xa085,
+	0x0001, 0x127f, 0x0d7f, 0x007c, 0xa006, 0x0078, 0x45e1, 0x127e,
+	0x2091, 0x8000, 0x0d7e, 0x60a4, 0xa00d, 0x0040, 0x4607, 0x2168,
+	0x6800, 0xa005, 0x00c0, 0x4603, 0x1078, 0x4749, 0x00c0, 0x4607,
+	0x200b, 0xffff, 0x6804, 0xa08a, 0x0002, 0x0048, 0x4603, 0x8001,
+	0x6806, 0x0078, 0x4607, 0x1078, 0x139a, 0x60a7, 0x0000, 0x0d7f,
+	0x127f, 0x007c, 0x127e, 0x2091, 0x8000, 0x1078, 0x47af, 0x0078,
+	0x4613, 0x1078, 0x43c1, 0x1078, 0x46a7, 0x00c0, 0x4611, 0x1078,
+	0x4663, 0x127f, 0x007c, 0x0d7e, 0x127e, 0x2091, 0x8000, 0x60a8,
+	0xa06d, 0x0040, 0x463f, 0x6950, 0x81ff, 0x00c0, 0x4653, 0x6a54,
+	0xa282, 0x0010, 0x00c8, 0x4660, 0xad88, 0x0018, 0x20a9, 0x0010,
+	0x2104, 0xa086, 0xffff, 0x0040, 0x463a, 0x8108, 0x00f0, 0x4630,
+	0x1078, 0x1328, 0x260a, 0x8210, 0x6a56, 0x0078, 0x4653, 0x1078,
+	0x1381, 0x0040, 0x4660, 0x2d00, 0x60aa, 0x6853, 0x0000, 0xad88,
+	0x0018, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108, 0x00f0, 0x464b,
+	0x6857, 0x0001, 0x6e62, 0x0078, 0x4657, 0x1078, 0x441c, 0x1078,
+	0x466d, 0x00c0, 0x4655, 0xa085, 0x0001, 0x127f, 0x0d7f, 0x007c,
+	0xa006, 0x0078, 0x465d, 0x127e, 0x2091, 0x8000, 0x1078, 0x5c17,
+	0x127f, 0x007c, 0xa01e, 0x0078, 0x466f, 0x2019, 0x0001, 0xa00e,
+	0x127e, 0x2091, 0x8000, 0x604c, 0x2068, 0x6000, 0xd0dc, 0x00c0,
+	0x468d, 0x8dff, 0x0040, 0x46a2, 0x83ff, 0x0040, 0x4685, 0x6848,
+	0xa606, 0x0040, 0x4692, 0x0078, 0x468d, 0x683c, 0xa406, 0x00c0,
+	0x468d, 0x6840, 0xa506, 0x0040, 0x4692, 0x2d08, 0x6800, 0x2068,
+	0x0078, 0x4679, 0x6a00, 0x604c, 0xad06, 0x00c0, 0x469a, 0x624e,
+	0x0078, 0x469d, 0xa180, 0x0000, 0x2202, 0x82ff, 0x00c0, 0x46a2,
+	0x6152, 0x8dff, 0x127f, 0x007c, 0xa01e, 0x0078, 0x46a9, 0x2019,
+	0x0001, 0xa00e, 0x6080, 0x2068, 0x8dff, 0x0040, 0x46d5, 0x83ff,
+	0x0040, 0x46b8, 0x6848, 0xa606, 0x0040, 0x46c5, 0x0078, 0x46c0,
+	0x683c, 0xa406, 0x00c0, 0x46c0, 0x6840, 0xa506, 0x0040, 0x46c5,
+	0x2d08, 0x6800, 0x2068, 0x0078, 0x46ac, 0x6a00, 0x6080, 0xad06,
+	0x00c0, 0x46cd, 0x6282, 0x0078, 0x46d0, 0xa180, 0x0000, 0x2202,
+	0x82ff, 0x00c0, 0x46d5, 0x6186, 0x8dff, 0x007c, 0xa016, 0x1078,
+	0x4742, 0x00c0, 0x46dd, 0x2011, 0x0001, 0x1078, 0x4793, 0x00c0,
+	0x46e3, 0xa295, 0x0002, 0x007c, 0x1078, 0x47cb, 0x0040, 0x46ec,
+	0x1078, 0x8b12, 0x0078, 0x46ee, 0xa085, 0x0001, 0x007c, 0x1078,
+	0x47cb, 0x0040, 0x46f7, 0x1078, 0x8aaa, 0x0078, 0x46f9, 0xa085,
+	0x0001, 0x007c, 0x1078, 0x47cb, 0x0040, 0x4702, 0x1078, 0x8af4,
+	0x0078, 0x4704, 0xa085, 0x0001, 0x007c, 0x1078, 0x47cb, 0x0040,
+	0x470d, 0x1078, 0x8ac6, 0x0078, 0x470f, 0xa085, 0x0001, 0x007c,
+	0x1078, 0x47cb, 0x0040, 0x4718, 0x1078, 0x8b30, 0x0078, 0x471a,
+	0xa085, 0x0001, 0x007c, 0x127e, 0x007e, 0x0d7e, 0x2091, 0x8000,
+	0x6080, 0xa06d, 0x0040, 0x473a, 0x6800, 0x007e, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x1078, 0x8cb8, 0x007e, 0x6000, 0xd0fc,
+	0x0040, 0x4734, 0x1078, 0xa18c, 0x007f, 0x1078, 0x4982, 0x007f,
+	0x0078, 0x4721, 0x6083, 0x0000, 0x6087, 0x0000, 0x0d7f, 0x007f,
+	0x127f, 0x007c, 0x60a4, 0xa00d, 0x00c0, 0x4749, 0xa085, 0x0001,
+	0x007c, 0x0e7e, 0x2170, 0x7000, 0xa005, 0x00c0, 0x475c, 0x20a9,
+	0x0010, 0xae88, 0x0004, 0x2104, 0xa606, 0x0040, 0x475c, 0x8108,
+	0x00f0, 0x4753, 0xa085, 0x0001, 0xa006, 0x0e7f, 0x007c, 0x0d7e,
+	0x127e, 0x2091, 0x8000, 0x60a4, 0xa06d, 0x00c0, 0x476d, 0x1078,
+	0x1381, 0x0040, 0x477f, 0x2d00, 0x60a6, 0x6803, 0x0001, 0x6807,
+	0x0000, 0xad88, 0x0004, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108,
+	0x00f0, 0x4775, 0xa085, 0x0001, 0x127f, 0x0d7f, 0x007c, 0xa006,
+	0x0078, 0x477c, 0x0d7e, 0x127e, 0x2091, 0x8000, 0x60a4, 0xa06d,
+	0x0040, 0x4790, 0x60a7, 0x0000, 0x1078, 0x139a, 0xa085, 0x0001,
+	0x127f, 0x0d7f, 0x007c, 0x60a8, 0xa00d, 0x00c0, 0x479a, 0xa085,
+	0x0001, 0x007c, 0x0e7e, 0x2170, 0x7050, 0xa005, 0x00c0, 0x47ad,
+	0x20a9, 0x0010, 0xae88, 0x0018, 0x2104, 0xa606, 0x0040, 0x47ad,
+	0x8108, 0x00f0, 0x47a4, 0xa085, 0x0001, 0x0e7f, 0x007c, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x4793, 0x00c0, 0x47c9, 0x200b, 0xffff,
+	0x0d7e, 0x60a8, 0x2068, 0x6854, 0xa08a, 0x0002, 0x0048, 0x47c4,
+	0x8001, 0x6856, 0x0078, 0x47c8, 0x1078, 0x139a, 0x60ab, 0x0000,
+	0x0d7f, 0x127f, 0x007c, 0x609c, 0xd0a4, 0x007c, 0x0f7e, 0x71ac,
+	0x81ff, 0x00c0, 0x47e9, 0x71c8, 0xd19c, 0x0040, 0x47e9, 0x2001,
+	0x007e, 0xa080, 0xa434, 0x2004, 0xa07d, 0x0040, 0x47e9, 0x7804,
+	0xa084, 0x00ff, 0xa086, 0x0006, 0x00c0, 0x47e9, 0x7800, 0xc0ed,
+	0x7802, 0x2079, 0xa351, 0x7804, 0xd0a4, 0x0040, 0x480f, 0x157e,
+	0x0c7e, 0x20a9, 0x007f, 0x2009, 0x0000, 0x017e, 0x1078, 0x4501,
+	0x00c0, 0x4809, 0x6004, 0xa084, 0xff00, 0x8007, 0xa096, 0x0004,
+	0x0040, 0x4806, 0xa086, 0x0006, 0x00c0, 0x4809, 0x6000, 0xc0ed,
+	0x6002, 0x017f, 0x8108, 0x00f0, 0x47f5, 0x0c7f, 0x157f, 0x1078,
+	0x4897, 0x0040, 0x4818, 0x2001, 0xa59f, 0x200c, 0x0078, 0x4820,
+	0x2079, 0xa351, 0x7804, 0xd0a4, 0x0040, 0x4824, 0x2009, 0x07d0,
+	0x2011, 0x4826, 0x1078, 0x596c, 0x0f7f, 0x007c, 0x2011, 0x4826,
+	0x1078, 0x58d4, 0x1078, 0x4897, 0x0040, 0x484e, 0x2001, 0xa4b2,
+	0x2004, 0xa080, 0x0000, 0x200c, 0xc1ec, 0x2102, 0x2001, 0xa352,
+	0x2004, 0xd0a4, 0x0040, 0x4842, 0x2009, 0x07d0, 0x2011, 0x4826,
+	0x1078, 0x596c, 0x0e7e, 0x2071, 0xa300, 0x706b, 0x0000, 0x706f,
+	0x0000, 0x1078, 0x260d, 0x0e7f, 0x0078, 0x4886, 0x157e, 0x0c7e,
+	0x20a9, 0x007f, 0x2009, 0x0000, 0x017e, 0x1078, 0x4501, 0x00c0,
+	0x4880, 0x6000, 0xd0ec, 0x0040, 0x4880, 0x047e, 0x62a0, 0xa294,
+	0x00ff, 0x8227, 0xa006, 0x2009, 0x0029, 0x1078, 0x9ec0, 0x6000,
+	0xc0e5, 0xc0ec, 0x6002, 0x6004, 0xa084, 0x00ff, 0xa085, 0x0700,
+	0x6006, 0x2019, 0x0029, 0x1078, 0x5d53, 0x077e, 0x2039, 0x0000,
+	0x1078, 0x5c78, 0x2009, 0x0000, 0x1078, 0x9c38, 0x077f, 0x047f,
+	0x017f, 0x8108, 0x00f0, 0x4854, 0x0c7f, 0x157f, 0x007c, 0x0c7e,
+	0x6018, 0x2060, 0x6000, 0xc0ec, 0x6002, 0x0c7f, 0x007c, 0x7818,
+	0x2004, 0xd0ac, 0x007c, 0x7818, 0x2004, 0xd0bc, 0x007c, 0x0f7e,
+	0x2001, 0xa4b2, 0x2004, 0xa07d, 0x0040, 0x48a0, 0x7800, 0xd0ec,
+	0x0f7f, 0x007c, 0x127e, 0x027e, 0x2091, 0x8000, 0x6200, 0xa005,
+	0x0040, 0x48ad, 0xc2fd, 0x0078, 0x48ae, 0xc2fc, 0x6202, 0x027f,
+	0x127f, 0x007c, 0x2071, 0xa413, 0x7003, 0x0001, 0x7007, 0x0000,
+	0x7013, 0x0000, 0x7017, 0x0000, 0x701b, 0x0000, 0x701f, 0x0000,
+	0x700b, 0x0000, 0x704b, 0x0001, 0x704f, 0x0000, 0x705b, 0x0020,
+	0x705f, 0x0040, 0x707f, 0x0000, 0x2071, 0xa57c, 0x7003, 0xa413,
+	0x7007, 0x0000, 0x700b, 0x0000, 0x700f, 0xa55c, 0x7013, 0x0020,
+	0x7017, 0x0040, 0x7037, 0x0000, 0x007c, 0x017e, 0x0e7e, 0x2071,
+	0xa534, 0xa00e, 0x7186, 0x718a, 0x7097, 0x0001, 0x2001, 0xa352,
+	0x2004, 0xd0fc, 0x00c0, 0x48f7, 0x2001, 0xa352, 0x2004, 0xa00e,
+	0xd09c, 0x0040, 0x48f4, 0x8108, 0x7102, 0x0078, 0x494a, 0x2001,
+	0xa371, 0x200c, 0xa184, 0x000f, 0x2009, 0xa372, 0x210c, 0x0079,
+	0x4901, 0x48ec, 0x4922, 0x492a, 0x4935, 0x493b, 0x48ec, 0x48ec,
+	0x48ec, 0x4911, 0x48ec, 0x48ec, 0x48ec, 0x48ec, 0x48ec, 0x48ec,
+	0x48ec, 0x7003, 0x0004, 0x137e, 0x147e, 0x157e, 0x2099, 0xa375,
+	0x20a1, 0xa585, 0x20a9, 0x0004, 0x53a3, 0x157f, 0x147f, 0x137f,
+	0x0078, 0x494a, 0x708f, 0x0005, 0x7007, 0x0122, 0x2001, 0x0002,
+	0x0078, 0x4930, 0x708f, 0x0002, 0x7007, 0x0121, 0x2001, 0x0003,
+	0x7002, 0x7097, 0x0001, 0x0078, 0x4947, 0x7007, 0x0122, 0x2001,
+	0x0002, 0x0078, 0x493f, 0x7007, 0x0121, 0x2001, 0x0003, 0x7002,
+	0xa006, 0x7096, 0x708e, 0xa184, 0xff00, 0x8007, 0x709a, 0xa184,
+	0x00ff, 0x7092, 0x0e7f, 0x017f, 0x007c, 0x0e7e, 0x2071, 0xa413,
+	0x684c, 0xa005, 0x00c0, 0x495b, 0x7028, 0xc085, 0x702a, 0xa085,
+	0x0001, 0x0078, 0x4980, 0x6a60, 0x7236, 0x6b64, 0x733a, 0x6868,
+	0x703e, 0x7076, 0x686c, 0x7042, 0x707a, 0x684c, 0x702e, 0x6844,
+	0x7032, 0x2009, 0x000d, 0x200a, 0x700b, 0x0000, 0x8007, 0x8006,
+	0x8006, 0xa08c, 0x003f, 0xa084, 0xffc0, 0xa210, 0x2100, 0xa319,
+	0x726e, 0x7372, 0x7028, 0xc084, 0x702a, 0x7007, 0x0001, 0xa006,
+	0x0e7f, 0x007c, 0x0e7e, 0x027e, 0x6838, 0xd0fc, 0x00c0, 0x49d8,
+	0x6804, 0xa00d, 0x0040, 0x499e, 0x0d7e, 0x2071, 0xa300, 0xa016,
+	0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x00c0,
+	0x4991, 0x702e, 0x70a8, 0xa200, 0x70aa, 0x0d7f, 0x2071, 0xa413,
+	0x701c, 0xa005, 0x00c0, 0x49ea, 0x0068, 0x49e8, 0x2071, 0xa534,
+	0x7200, 0x82ff, 0x0040, 0x49e8, 0x6934, 0xa186, 0x0103, 0x00c0,
+	0x49fb, 0x6948, 0x6844, 0xa105, 0x00c0, 0x49db, 0x2009, 0x8020,
+	0x2200, 0x0079, 0x49bb, 0x49e8, 0x49c0, 0x4a18, 0x4a26, 0x49e8,
+	0x2071, 0x0000, 0x7018, 0xd084, 0x00c0, 0x49e8, 0x7122, 0x683c,
+	0x7026, 0x6840, 0x702a, 0x701b, 0x0001, 0x2091, 0x4080, 0x2071,
+	0xa300, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70a8, 0x8000, 0x70aa,
+	0x027f, 0x0e7f, 0x007c, 0x6844, 0xa086, 0x0100, 0x00c0, 0x49e8,
+	0x6868, 0xa005, 0x00c0, 0x49e8, 0x2009, 0x8020, 0x0078, 0x49b8,
+	0x2071, 0xa413, 0x2d08, 0x206b, 0x0000, 0x7010, 0x8000, 0x7012,
+	0x7018, 0xa06d, 0x711a, 0x0040, 0x49f8, 0x6902, 0x0078, 0x49f9,
+	0x711e, 0x0078, 0x49d8, 0xa18c, 0x00ff, 0xa186, 0x0017, 0x0040,
+	0x4a09, 0xa186, 0x001e, 0x0040, 0x4a09, 0xa18e, 0x001f, 0x00c0,
+	0x49e8, 0x684c, 0xd0cc, 0x0040, 0x49e8, 0x6850, 0xa084, 0x00ff,
+	0xa086, 0x0001, 0x00c0, 0x49e8, 0x2009, 0x8021, 0x0078, 0x49b8,
+	0x7084, 0x8008, 0xa092, 0x001e, 0x00c8, 0x49e8, 0x7186, 0xae90,
+	0x0003, 0xa210, 0x683c, 0x2012, 0x0078, 0x4a36, 0x7084, 0x8008,
+	0xa092, 0x000f, 0x00c8, 0x49e8, 0x7186, 0xae90, 0x0003, 0x8003,
+	0xa210, 0x683c, 0x2012, 0x8210, 0x6840, 0x2012, 0x7088, 0xa10a,
+	0x0048, 0x49cf, 0x718c, 0x7084, 0xa10a, 0x0048, 0x49cf, 0x2071,
+	0x0000, 0x7018, 0xd084, 0x00c0, 0x49cf, 0x2071, 0xa534, 0x7000,
+	0xa086, 0x0002, 0x00c0, 0x4a56, 0x1078, 0x4cd2, 0x2071, 0x0000,
+	0x701b, 0x0001, 0x2091, 0x4080, 0x0078, 0x49cf, 0x1078, 0x4cfd,
+	0x2071, 0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0078, 0x49cf,
+	0x007e, 0x684c, 0x007e, 0x6837, 0x0103, 0x20a9, 0x001c, 0xad80,
+	0x0011, 0x20a0, 0x2001, 0x0000, 0x40a4, 0x007f, 0xa084, 0x00ff,
+	0x684e, 0x007f, 0x684a, 0x6952, 0x007c, 0x2071, 0xa413, 0x7004,
+	0x0079, 0x4a7a, 0x4a84, 0x4a95, 0x4ca3, 0x4ca4, 0x4ccb, 0x4cd1,
+	0x4a85, 0x4c91, 0x4c32, 0x4cb4, 0x007c, 0x127e, 0x2091, 0x8000,
+	0x0068, 0x4a94, 0x2009, 0x000d, 0x7030, 0x200a, 0x2091, 0x4080,
+	0x7007, 0x0001, 0x700b, 0x0000, 0x127f, 0x2069, 0xa5be, 0x6844,
+	0xa005, 0x0050, 0x4abd, 0x00c0, 0x4abd, 0x127e, 0x2091, 0x8000,
+	0x2069, 0x0000, 0x6934, 0x2001, 0xa41f, 0x2004, 0xa10a, 0x0040,
+	0x4ab8, 0x0068, 0x4abc, 0x2069, 0x0000, 0x6818, 0xd084, 0x00c0,
+	0x4abc, 0x2009, 0x8040, 0x6922, 0x681b, 0x0001, 0x2091, 0x4080,
+	0x2069, 0xa5be, 0x6847, 0xffff, 0x127f, 0x2069, 0xa300, 0x6844,
+	0x6960, 0xa102, 0x2069, 0xa534, 0x688a, 0x6984, 0x701c, 0xa06d,
+	0x0040, 0x4acf, 0x81ff, 0x0040, 0x4b17, 0x0078, 0x4ae5, 0x81ff,
+	0x0040, 0x4be9, 0x2071, 0xa534, 0x7184, 0x7088, 0xa10a, 0x00c8,
+	0x4ae5, 0x7190, 0x2071, 0xa5be, 0x7040, 0xa005, 0x0040, 0x4ae5,
+	0x00d0, 0x4be9, 0x7142, 0x0078, 0x4be9, 0x2071, 0xa534, 0x718c,
+	0x127e, 0x2091, 0x8000, 0x7084, 0xa10a, 0x0048, 0x4c06, 0x0068,
+	0x4b9b, 0x2071, 0x0000, 0x7018, 0xd084, 0x00c0, 0x4b9b, 0x2001,
+	0xffff, 0x2071, 0xa5be, 0x7042, 0x2071, 0xa534, 0x7000, 0xa086,
+	0x0002, 0x00c0, 0x4b0d, 0x1078, 0x4cd2, 0x2071, 0x0000, 0x701b,
+	0x0001, 0x2091, 0x4080, 0x0078, 0x4b9b, 0x1078, 0x4cfd, 0x2071,
+	0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0078, 0x4b9b, 0x2071,
+	0xa534, 0x7000, 0xa005, 0x0040, 0x4bc8, 0x6934, 0xa186, 0x0103,
+	0x00c0, 0x4b9e, 0x684c, 0xd0bc, 0x00c0, 0x4bc8, 0x6948, 0x6844,
+	0xa105, 0x00c0, 0x4bbb, 0x2009, 0x8020, 0x2071, 0xa534, 0x7000,
+	0x0079, 0x4b32, 0x4bc8, 0x4b80, 0x4b58, 0x4b6a, 0x4b37, 0x137e,
+	0x147e, 0x157e, 0x2099, 0xa375, 0x20a1, 0xa585, 0x20a9, 0x0004,
+	0x53a3, 0x157f, 0x147f, 0x137f, 0x2071, 0xa57c, 0xad80, 0x000f,
+	0x700e, 0x7013, 0x0002, 0x7007, 0x0002, 0x700b, 0x0000, 0x2e10,
+	0x1078, 0x13d1, 0x2071, 0xa413, 0x7007, 0x0009, 0x0078, 0x4be9,
+	0x7084, 0x8008, 0xa092, 0x001e, 0x00c8, 0x4be9, 0xae90, 0x0003,
+	0xa210, 0x683c, 0x2012, 0x7186, 0x2071, 0xa413, 0x1078, 0x4d5b,
+	0x0078, 0x4be9, 0x7084, 0x8008, 0xa092, 0x000f, 0x00c8, 0x4be9,
+	0xae90, 0x0003, 0x8003, 0xa210, 0x683c, 0x2012, 0x8210, 0x6840,
+	0x2012, 0x7186, 0x2071, 0xa413, 0x1078, 0x4d5b, 0x0078, 0x4be9,
+	0x127e, 0x2091, 0x8000, 0x0068, 0x4b9b, 0x2071, 0x0000, 0x7018,
+	0xd084, 0x00c0, 0x4b9b, 0x7122, 0x683c, 0x7026, 0x6840, 0x702a,
+	0x701b, 0x0001, 0x2091, 0x4080, 0x127f, 0x2071, 0xa413, 0x1078,
+	0x4d5b, 0x0078, 0x4be9, 0x127f, 0x0078, 0x4be9, 0xa18c, 0x00ff,
+	0xa186, 0x0017, 0x0040, 0x4bac, 0xa186, 0x001e, 0x0040, 0x4bac,
+	0xa18e, 0x001f, 0x00c0, 0x4bc8, 0x684c, 0xd0cc, 0x0040, 0x4bc8,
+	0x6850, 0xa084, 0x00ff, 0xa086, 0x0001, 0x00c0, 0x4bc8, 0x2009,
+	0x8021, 0x0078, 0x4b2d, 0x6844, 0xa086, 0x0100, 0x00c0, 0x4bc8,
+	0x6868, 0xa005, 0x00c0, 0x4bc8, 0x2009, 0x8020, 0x0078, 0x4b2d,
+	0x2071, 0xa413, 0x1078, 0x4d6f, 0x0040, 0x4be9, 0x2071, 0xa413,
+	0x700f, 0x0001, 0x6934, 0xa184, 0x00ff, 0xa086, 0x0003, 0x00c0,
+	0x4be0, 0x810f, 0xa18c, 0x00ff, 0x8101, 0x0040, 0x4be0, 0x710e,
+	0x7007, 0x0003, 0x1078, 0x4d8f, 0x7050, 0xa086, 0x0100, 0x0040,
+	0x4ca4, 0x127e, 0x2091, 0x8000, 0x2071, 0xa413, 0x7008, 0xa086,
+	0x0001, 0x00c0, 0x4c04, 0x0068, 0x4c04, 0x2009, 0x000d, 0x7030,
+	0x200a, 0x2091, 0x4080, 0x700b, 0x0000, 0x7004, 0xa086, 0x0006,
+	0x00c0, 0x4c04, 0x7007, 0x0001, 0x127f, 0x007c, 0x2071, 0xa413,
+	0x1078, 0x4d6f, 0x0040, 0x4c2f, 0x2071, 0xa534, 0x7084, 0x700a,
+	0x20a9, 0x0020, 0x2099, 0xa535, 0x20a1, 0xa55c, 0x53a3, 0x7087,
+	0x0000, 0x2071, 0xa413, 0x2069, 0xa57c, 0x706c, 0x6826, 0x7070,
+	0x682a, 0x7074, 0x682e, 0x7078, 0x6832, 0x2d10, 0x1078, 0x13d1,
+	0x7007, 0x0008, 0x2001, 0xffff, 0x2071, 0xa5be, 0x7042, 0x127f,
+	0x0078, 0x4be9, 0x2069, 0xa57c, 0x6808, 0xa08e, 0x0000, 0x0040,
+	0x4c90, 0xa08e, 0x0200, 0x0040, 0x4c8e, 0xa08e, 0x0100, 0x00c0,
+	0x4c90, 0x127e, 0x2091, 0x8000, 0x0068, 0x4c8b, 0x2069, 0x0000,
+	0x6818, 0xd084, 0x00c0, 0x4c8b, 0x702c, 0x7130, 0x8108, 0xa102,
+	0x0048, 0x4c59, 0xa00e, 0x7034, 0x706e, 0x7038, 0x7072, 0x0078,
+	0x4c63, 0x706c, 0xa080, 0x0040, 0x706e, 0x00c8, 0x4c63, 0x7070,
+	0xa081, 0x0000, 0x7072, 0x7132, 0x6936, 0x700b, 0x0000, 0x2001,
+	0xa559, 0x2004, 0xa005, 0x00c0, 0x4c82, 0x6934, 0x2069, 0xa534,
+	0x689c, 0x699e, 0x2069, 0xa5be, 0xa102, 0x00c0, 0x4c7b, 0x6844,
+	0xa005, 0x00d0, 0x4c89, 0x2001, 0xa55a, 0x200c, 0x810d, 0x6946,
+	0x0078, 0x4c89, 0x2009, 0x8040, 0x6922, 0x681b, 0x0001, 0x2091,
+	0x4080, 0x7007, 0x0001, 0x127f, 0x0078, 0x4c90, 0x7007, 0x0005,
+	0x007c, 0x701c, 0xa06d, 0x0040, 0x4ca2, 0x1078, 0x4d6f, 0x0040,
+	0x4ca2, 0x7007, 0x0003, 0x1078, 0x4d8f, 0x7050, 0xa086, 0x0100,
+	0x0040, 0x4ca4, 0x007c, 0x007c, 0x7050, 0xa09e, 0x0100, 0x00c0,
+	0x4cad, 0x7007, 0x0004, 0x0078, 0x4ccb, 0xa086, 0x0200, 0x00c0,
+	0x4cb3, 0x7007, 0x0005, 0x007c, 0x2001, 0xa57e, 0x2004, 0xa08e,
+	0x0100, 0x00c0, 0x4cc0, 0x7007, 0x0001, 0x1078, 0x4d5b, 0x007c,
+	0xa08e, 0x0000, 0x0040, 0x4cbf, 0xa08e, 0x0200, 0x00c0, 0x4cbf,
+	0x7007, 0x0005, 0x007c, 0x1078, 0x4d25, 0x7006, 0x1078, 0x4d5b,
+	0x007c, 0x007c, 0x0e7e, 0x157e, 0x2071, 0xa534, 0x7184, 0x81ff,
+	0x0040, 0x4cfa, 0xa006, 0x7086, 0xae80, 0x0003, 0x2071, 0x0000,
+	0x21a8, 0x2014, 0x7226, 0x8000, 0x0070, 0x4cf7, 0x2014, 0x722a,
+	0x8000, 0x0070, 0x4cf7, 0x2014, 0x722e, 0x8000, 0x0070, 0x4cf7,
+	0x2014, 0x723a, 0x8000, 0x0070, 0x4cf7, 0x2014, 0x723e, 0xa180,
+	0x8030, 0x7022, 0x157f, 0x0e7f, 0x007c, 0x0e7e, 0x157e, 0x2071,
+	0xa534, 0x7184, 0x81ff, 0x0040, 0x4d22, 0xa006, 0x7086, 0xae80,
+	0x0003, 0x2071, 0x0000, 0x21a8, 0x2014, 0x7226, 0x8000, 0x2014,
+	0x722a, 0x8000, 0x0070, 0x4d1b, 0x2014, 0x723a, 0x8000, 0x2014,
+	0x723e, 0x0078, 0x4d1f, 0x2001, 0x8020, 0x0078, 0x4d21, 0x2001,
+	0x8042, 0x7022, 0x157f, 0x0e7f, 0x007c, 0x702c, 0x7130, 0x8108,
+	0xa102, 0x0048, 0x4d32, 0xa00e, 0x7034, 0x706e, 0x7038, 0x7072,
+	0x0078, 0x4d3c, 0x706c, 0xa080, 0x0040, 0x706e, 0x00c8, 0x4d3c,
+	0x7070, 0xa081, 0x0000, 0x7072, 0x7132, 0x700c, 0x8001, 0x700e,
+	0x00c0, 0x4d52, 0x127e, 0x2091, 0x8000, 0x0068, 0x4d55, 0x2001,
+	0x000d, 0x2102, 0x2091, 0x4080, 0x2001, 0x0001, 0x700b, 0x0000,
+	0x127f, 0x007c, 0x2001, 0x0007, 0x007c, 0x2001, 0x0006, 0x700b,
+	0x0001, 0x127f, 0x007c, 0x701c, 0xa06d, 0x0040, 0x4d6e, 0x127e,
+	0x2091, 0x8000, 0x7010, 0x8001, 0x7012, 0x2d04, 0x701e, 0xa005,
+	0x00c0, 0x4d6b, 0x701a, 0x127f, 0x1078, 0x139a, 0x007c, 0x2019,
+	0x000d, 0x2304, 0x230c, 0xa10e, 0x0040, 0x4d7e, 0x2304, 0x230c,
+	0xa10e, 0x0040, 0x4d7e, 0xa006, 0x0078, 0x4d8e, 0x732c, 0x8319,
+	0x7130, 0xa102, 0x00c0, 0x4d88, 0x2300, 0xa005, 0x0078, 0x4d8e,
+	0x0048, 0x4d8d, 0xa302, 0x0078, 0x4d8e, 0x8002, 0x007c, 0x2d00,
+	0x7026, 0xa080, 0x000d, 0x7056, 0x7053, 0x0000, 0x127e, 0x2091,
+	0x8000, 0x2009, 0xa5d0, 0x2104, 0xc08d, 0x200a, 0x127f, 0x1078,
+	0x13eb, 0x007c, 0x2071, 0xa3e1, 0x7003, 0x0000, 0x7007, 0x0000,
+	0x700f, 0x0000, 0x702b, 0x0001, 0x704f, 0x0000, 0x7053, 0x0001,
+	0x705f, 0x0020, 0x7063, 0x0040, 0x7083, 0x0000, 0x708b, 0x0000,
+	0x708f, 0x0001, 0x70bf, 0x0000, 0x007c, 0x0e7e, 0x2071, 0xa3e1,
+	0x6848, 0xa005, 0x00c0, 0x4dcb, 0x7028, 0xc085, 0x702a, 0xa085,
+	0x0001, 0x0078, 0x4df0, 0x6a50, 0x7236, 0x6b54, 0x733a, 0x6858,
+	0x703e, 0x707a, 0x685c, 0x7042, 0x707e, 0x6848, 0x702e, 0x6840,
+	0x7032, 0x2009, 0x000c, 0x200a, 0x8007, 0x8006, 0x8006, 0xa08c,
+	0x003f, 0xa084, 0xffc0, 0xa210, 0x2100, 0xa319, 0x7272, 0x7376,
+	0x7028, 0xc084, 0x702a, 0x7007, 0x0001, 0x700f, 0x0000, 0xa006,
+	0x0e7f, 0x007c, 0x2b78, 0x2071, 0xa3e1, 0x7004, 0x1079, 0x4e50,
+	0x700c, 0x0079, 0x4dfb, 0x4e00, 0x4df5, 0x4df5, 0x4df5, 0x4df5,
+	0x007c, 0x700c, 0x0079, 0x4e04, 0x4e09, 0x4e4e, 0x4e4e, 0x4e4f,
+	0x4e4f, 0x7830, 0x7930, 0xa106, 0x0040, 0x4e13, 0x7830, 0x7930,
+	0xa106, 0x00c0, 0x4e39, 0x7030, 0xa10a, 0x0040, 0x4e39, 0x00c8,
+	0x4e1b, 0x712c, 0xa10a, 0xa18a, 0x0002, 0x00c8, 0x4e3a, 0x1078,
+	0x1366, 0x0040, 0x4e39, 0x2d00, 0x705a, 0x7063, 0x0040, 0x2001,
+	0x0003, 0x7057, 0x0000, 0x127e, 0x007e, 0x2091, 0x8000, 0x2009,
+	0xa5d0, 0x2104, 0xc085, 0x200a, 0x007f, 0x700e, 0x127f, 0x1078,
+	0x13eb, 0x007c, 0x1078, 0x1366, 0x0040, 0x4e39, 0x2d00, 0x705a,
+	0x1078, 0x1366, 0x00c0, 0x4e46, 0x0078, 0x4e25, 0x2d00, 0x7086,
+	0x7063, 0x0080, 0x2001, 0x0004, 0x0078, 0x4e29, 0x007c, 0x007c,
+	0x4e61, 0x4e62, 0x4e99, 0x4e9a, 0x4e4e, 0x4ed0, 0x4ed5, 0x4f0c,
+	0x4f0d, 0x4f28, 0x4f29, 0x4f2a, 0x4f2b, 0x4f2c, 0x4f2d, 0x4fad,
+	0x4fd7, 0x007c, 0x700c, 0x0079, 0x4e65, 0x4e6a, 0x4e6d, 0x4e7d,
+	0x4e98, 0x4e98, 0x1078, 0x4e01, 0x007c, 0x127e, 0x8001, 0x700e,
+	0x7058, 0x007e, 0x1078, 0x5348, 0x0040, 0x4e7a, 0x2091, 0x8000,
+	0x1078, 0x4e01, 0x0d7f, 0x0078, 0x4e86, 0x127e, 0x8001, 0x700e,
+	0x1078, 0x5348, 0x7058, 0x2068, 0x7084, 0x705a, 0x6803, 0x0000,
+	0x6807, 0x0000, 0x6834, 0xa084, 0x00ff, 0xa08a, 0x0020, 0x00c8,
+	0x4e95, 0x1079, 0x4eb0, 0x127f, 0x007c, 0x127f, 0x1078, 0x4f2e,
+	0x007c, 0x007c, 0x007c, 0x0e7e, 0x2071, 0xa3e1, 0x700c, 0x0079,
+	0x4ea1, 0x4ea6, 0x4ea6, 0x4ea6, 0x4ea8, 0x4eac, 0x0e7f, 0x007c,
+	0x700f, 0x0001, 0x0078, 0x4eae, 0x700f, 0x0002, 0x0e7f, 0x007c,
+	0x4f2e, 0x4f2e, 0x4f4a, 0x4f2e, 0x5080, 0x4f2e, 0x4f2e, 0x4f2e,
+	0x4f2e, 0x4f2e, 0x4f4a, 0x50ca, 0x5117, 0x5170, 0x5186, 0x4f2e,
+	0x4f2e, 0x4f66, 0x4f4a, 0x4f2e, 0x4f2e, 0x4f87, 0x5245, 0x5263,
+	0x4f2e, 0x4f66, 0x4f2e, 0x4f2e, 0x4f2e, 0x4f2e, 0x4f7c, 0x5263,
+	0x7020, 0x2068, 0x1078, 0x139a, 0x007c, 0x700c, 0x0079, 0x4ed8,
+	0x4edd, 0x4ee0, 0x4ef0, 0x4f0b, 0x4f0b, 0x1078, 0x4e01, 0x007c,
+	0x127e, 0x8001, 0x700e, 0x7058, 0x007e, 0x1078, 0x5348, 0x0040,
+	0x4eed, 0x2091, 0x8000, 0x1078, 0x4e01, 0x0d7f, 0x0078, 0x4ef9,
+	0x127e, 0x8001, 0x700e, 0x1078, 0x5348, 0x7058, 0x2068, 0x7084,
+	0x705a, 0x6803, 0x0000, 0x6807, 0x0000, 0x6834, 0xa084, 0x00ff,
+	0xa08a, 0x001a, 0x00c8, 0x4f08, 0x1079, 0x4f0e, 0x127f, 0x007c,
+	0x127f, 0x1078, 0x4f2e, 0x007c, 0x007c, 0x007c, 0x4f2e, 0x4f4a,
+	0x506a, 0x4f2e, 0x4f4a, 0x4f2e, 0x4f4a, 0x4f4a, 0x4f2e, 0x4f4a,
+	0x506a, 0x4f4a, 0x4f4a, 0x4f4a, 0x4f4a, 0x4f4a, 0x4f2e, 0x4f4a,
+	0x506a, 0x4f2e, 0x4f2e, 0x4f4a, 0x4f2e, 0x4f2e, 0x4f2e, 0x4f4a,
+	0x007c, 0x007c, 0x007c, 0x007c, 0x007c, 0x007c, 0x7007, 0x0001,
+	0x6838, 0xa084, 0x00ff, 0xc0d5, 0x683a, 0x127e, 0x2091, 0x8000,
+	0x1078, 0x4982, 0x127f, 0x007c, 0x7007, 0x0001, 0x6838, 0xa084,
+	0x00ff, 0xc0e5, 0x683a, 0x127e, 0x2091, 0x8000, 0x1078, 0x4982,
+	0x127f, 0x007c, 0x7007, 0x0001, 0x6838, 0xa084, 0x00ff, 0xc0ed,
+	0x683a, 0x127e, 0x2091, 0x8000, 0x1078, 0x4982, 0x127f, 0x007c,
+	0x7007, 0x0001, 0x6838, 0xa084, 0x00ff, 0xc0dd, 0x683a, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x4982, 0x127f, 0x007c, 0x6834, 0x8007,
+	0xa084, 0x00ff, 0x0040, 0x4f3c, 0x8001, 0x00c0, 0x4f73, 0x7007,
+	0x0001, 0x0078, 0x5049, 0x7007, 0x0006, 0x7012, 0x2d00, 0x7016,
+	0x701a, 0x704b, 0x5049, 0x007c, 0x684c, 0xa084, 0x00c0, 0xa086,
+	0x00c0, 0x00c0, 0x4f87, 0x7007, 0x0001, 0x0078, 0x5280, 0x2d00,
+	0x7016, 0x701a, 0x20a9, 0x0004, 0xa080, 0x0024, 0x2098, 0x20a1,
+	0xa40c, 0x53a3, 0x6858, 0x7012, 0xa082, 0x0401, 0x00c8, 0x4f58,
+	0x6884, 0xa08a, 0x0002, 0x00c8, 0x4f58, 0x82ff, 0x00c0, 0x4fa9,
+	0x6888, 0x698c, 0xa105, 0x0040, 0x4fa9, 0x2001, 0x5019, 0x0078,
+	0x4fac, 0xa280, 0x500f, 0x2004, 0x70c6, 0x7010, 0xa015, 0x0040,
+	0x4ff7, 0x1078, 0x1366, 0x00c0, 0x4fb8, 0x7007, 0x000f, 0x007c,
+	0x2d00, 0x7022, 0x70c4, 0x2060, 0x6000, 0x6836, 0x6004, 0xad00,
+	0x7096, 0x6008, 0xa20a, 0x00c8, 0x4fc7, 0xa00e, 0x2200, 0x7112,
+	0x620c, 0x8003, 0x800b, 0xa296, 0x0004, 0x0040, 0x4fd0, 0xa108,
+	0x719a, 0x810b, 0x719e, 0xae90, 0x0022, 0x1078, 0x13d1, 0x7090,
+	0xa08e, 0x0100, 0x0040, 0x4feb, 0xa086, 0x0200, 0x0040, 0x4fe3,
+	0x7007, 0x0010, 0x007c, 0x7020, 0x2068, 0x1078, 0x139a, 0x7014,
+	0x2068, 0x0078, 0x4f58, 0x7020, 0x2068, 0x7018, 0x6802, 0x6807,
+	0x0000, 0x2d08, 0x2068, 0x6906, 0x711a, 0x0078, 0x4fad, 0x7014,
+	0x2068, 0x7007, 0x0001, 0x6884, 0xa005, 0x00c0, 0x5006, 0x6888,
+	0x698c, 0xa105, 0x0040, 0x5006, 0x1078, 0x501d, 0x6834, 0xa084,
+	0x00ff, 0xa086, 0x001e, 0x0040, 0x5280, 0x0078, 0x5049, 0x5011,
+	0x5015, 0x0002, 0x0011, 0x0007, 0x0004, 0x000a, 0x000f, 0x0005,
+	0x0006, 0x000a, 0x0011, 0x0005, 0x0004, 0x0f7e, 0x0e7e, 0x0c7e,
+	0x077e, 0x067e, 0x6f88, 0x6e8c, 0x6804, 0x2060, 0xacf0, 0x0021,
+	0xacf8, 0x0027, 0x2009, 0x0005, 0x700c, 0x7816, 0x7008, 0x7812,
+	0x7004, 0x7806, 0x7000, 0x7802, 0x7e0e, 0x7f0a, 0x8109, 0x0040,
+	0x503f, 0xaef2, 0x0004, 0xaffa, 0x0006, 0x0078, 0x502c, 0x6004,
+	0xa065, 0x00c0, 0x5026, 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x0f7f,
+	0x007c, 0x2009, 0xa32e, 0x210c, 0x81ff, 0x00c0, 0x5064, 0x6838,
+	0xa084, 0x00ff, 0x683a, 0x1078, 0x4290, 0x00c0, 0x5058, 0x007c,
+	0x1078, 0x4a60, 0x127e, 0x2091, 0x8000, 0x1078, 0x8cb8, 0x1078,
+	0x4982, 0x127f, 0x0078, 0x5057, 0x2001, 0x0028, 0x2009, 0x0000,
+	0x0078, 0x5058, 0x7018, 0x6802, 0x2d08, 0x2068, 0x6906, 0x711a,
+	0x7010, 0x8001, 0x7012, 0x0040, 0x5079, 0x7007, 0x0006, 0x0078,
+	0x507f, 0x7014, 0x2068, 0x7007, 0x0001, 0x7048, 0x107a, 0x007c,
+	0x7007, 0x0001, 0x6944, 0x810f, 0xa18c, 0x00ff, 0x6848, 0xa084,
+	0x00ff, 0x20a9, 0x0001, 0xa096, 0x0001, 0x0040, 0x50a9, 0x2009,
+	0x0000, 0x20a9, 0x00ff, 0xa096, 0x0002, 0x0040, 0x50a9, 0xa005,
+	0x00c0, 0x50bc, 0x6944, 0x810f, 0xa18c, 0x00ff, 0x1078, 0x4501,
+	0x00c0, 0x50bc, 0x067e, 0x6e50, 0x1078, 0x45e7, 0x067f, 0x0078,
+	0x50bc, 0x047e, 0x2011, 0xa30c, 0x2224, 0xc484, 0xc48c, 0x2412,
+	0x047f, 0x0c7e, 0x1078, 0x4501, 0x00c0, 0x50b8, 0x1078, 0x4782,
+	0x8108, 0x00f0, 0x50b2, 0x0c7f, 0x684c, 0xd084, 0x00c0, 0x50c3,
+	0x1078, 0x139a, 0x007c, 0x127e, 0x2091, 0x8000, 0x1078, 0x4982,
+	0x127f, 0x007c, 0x127e, 0x2091, 0x8000, 0x7007, 0x0001, 0x2001,
+	0xa352, 0x2004, 0xd0a4, 0x0040, 0x510e, 0x2061, 0xa62d, 0x6100,
+	0xd184, 0x0040, 0x50ee, 0x6858, 0xa084, 0x00ff, 0x00c0, 0x5111,
+	0x6000, 0xd084, 0x0040, 0x510e, 0x6004, 0xa005, 0x00c0, 0x5114,
+	0x6003, 0x0000, 0x600b, 0x0000, 0x0078, 0x510b, 0x2011, 0x0001,
+	0x6860, 0xa005, 0x00c0, 0x50f6, 0x2001, 0x001e, 0x8000, 0x6016,
+	0x6858, 0xa084, 0x00ff, 0x0040, 0x510e, 0x6006, 0x6858, 0x8007,
+	0xa084, 0x00ff, 0x0040, 0x510e, 0x600a, 0x6858, 0x8000, 0x00c0,
+	0x510a, 0xc28d, 0x6202, 0x127f, 0x0078, 0x5337, 0x127f, 0x0078,
+	0x532f, 0x127f, 0x0078, 0x5327, 0x127f, 0x0078, 0x532b, 0x127e,
+	0x2091, 0x8000, 0x7007, 0x0001, 0x2001, 0xa352, 0x2004, 0xd0a4,
+	0x0040, 0x516d, 0x2061, 0xa62d, 0x6000, 0xd084, 0x0040, 0x516d,
+	0x6204, 0x6308, 0xd08c, 0x00c0, 0x515f, 0x6c48, 0xa484, 0x0003,
+	0x0040, 0x5145, 0x6958, 0xa18c, 0x00ff, 0x8001, 0x00c0, 0x513e,
+	0x2100, 0xa210, 0x0048, 0x516a, 0x0078, 0x5145, 0x8001, 0x00c0,
+	0x516a, 0x2100, 0xa212, 0x0048, 0x516a, 0xa484, 0x000c, 0x0040,
+	0x515f, 0x6958, 0x810f, 0xa18c, 0x00ff, 0xa082, 0x0004, 0x00c0,
+	0x5157, 0x2100, 0xa318, 0x0048, 0x516a, 0x0078, 0x515f, 0xa082,
+	0x0004, 0x00c0, 0x516a, 0x2100, 0xa31a, 0x0048, 0x516a, 0x6860,
+	0xa005, 0x0040, 0x5165, 0x8000, 0x6016, 0x6206, 0x630a, 0x127f,
+	0x0078, 0x5337, 0x127f, 0x0078, 0x5333, 0x127f, 0x0078, 0x532f,
+	0x127e, 0x2091, 0x8000, 0x7007, 0x0001, 0x2061, 0xa62d, 0x6300,
+	0xd38c, 0x00c0, 0x5180, 0x6308, 0x8318, 0x0048, 0x5183, 0x630a,
+	0x127f, 0x0078, 0x5345, 0x127f, 0x0078, 0x5333, 0x127e, 0x0c7e,
+	0x2091, 0x8000, 0x7007, 0x0001, 0x684c, 0xd0ac, 0x0040, 0x519a,
+	0x0c7e, 0x2061, 0xa62d, 0x6000, 0xa084, 0xfcff, 0x6002, 0x0c7f,
+	0x0078, 0x51c9, 0x6858, 0xa005, 0x0040, 0x51e0, 0x685c, 0xa065,
+	0x0040, 0x51dc, 0x2001, 0xa32e, 0x2004, 0xa005, 0x0040, 0x51ac,
+	0x1078, 0x8c01, 0x0078, 0x51ba, 0x6013, 0x0400, 0x6037, 0x0000,
+	0x694c, 0xd1a4, 0x0040, 0x51b6, 0x6950, 0x6136, 0x2009, 0x0041,
+	0x1078, 0x756c, 0x6958, 0xa18c, 0xff00, 0xa186, 0x2000, 0x00c0,
+	0x51c9, 0x027e, 0x2009, 0x0000, 0x2011, 0xfdff, 0x1078, 0x5a6d,
+	0x027f, 0x684c, 0xd0c4, 0x0040, 0x51d8, 0x2061, 0xa62d, 0x6000,
+	0xd08c, 0x00c0, 0x51d8, 0x6008, 0x8000, 0x0048, 0x51dc, 0x600a,
+	0x0c7f, 0x127f, 0x0078, 0x5337, 0x0c7f, 0x127f, 0x0078, 0x532f,
+	0x6954, 0xa186, 0x0045, 0x0040, 0x5213, 0xa186, 0x002a, 0x00c0,
+	0x51f0, 0x2001, 0xa30c, 0x200c, 0xc194, 0x2102, 0x0078, 0x51c9,
+	0xa186, 0x0020, 0x0040, 0x5209, 0xa186, 0x0029, 0x0040, 0x51fc,
+	0xa186, 0x002d, 0x00c0, 0x51dc, 0x6944, 0xa18c, 0xff00, 0x810f,
+	0x1078, 0x4501, 0x00c0, 0x51c9, 0x6000, 0xc0e4, 0x6002, 0x0078,
+	0x51c9, 0x685c, 0xa065, 0x0040, 0x51dc, 0x2001, 0xa5a1, 0x2004,
+	0x6016, 0x0078, 0x51c9, 0x685c, 0xa065, 0x0040, 0x51dc, 0x0e7e,
+	0x6860, 0xa075, 0x2001, 0xa32e, 0x2004, 0xa005, 0x0040, 0x522b,
+	0x1078, 0x8c01, 0x8eff, 0x0040, 0x5228, 0x2e60, 0x1078, 0x8c01,
+	0x0e7f, 0x0078, 0x51c9, 0x6024, 0xc0dc, 0xc0d5, 0x6026, 0x2e60,
+	0x6007, 0x003a, 0x6870, 0xa005, 0x0040, 0x523c, 0x6007, 0x003b,
+	0x6874, 0x602a, 0x6878, 0x6012, 0x6003, 0x0001, 0x1078, 0x5bf8,
+	0x1078, 0x6109, 0x0e7f, 0x0078, 0x51c9, 0x2061, 0xa62d, 0x6000,
+	0xd084, 0x0040, 0x525f, 0xd08c, 0x00c0, 0x5345, 0x2091, 0x8000,
+	0x6204, 0x8210, 0x0048, 0x5259, 0x6206, 0x2091, 0x8001, 0x0078,
+	0x5345, 0x2091, 0x8001, 0x6853, 0x0016, 0x0078, 0x533e, 0x6853,
+	0x0007, 0x0078, 0x533e, 0x6834, 0x8007, 0xa084, 0x00ff, 0x00c0,
+	0x526d, 0x1078, 0x4f3c, 0x0078, 0x527f, 0x2030, 0x8001, 0x00c0,
+	0x5277, 0x7007, 0x0001, 0x1078, 0x5280, 0x0078, 0x527f, 0x7007,
+	0x0006, 0x7012, 0x2d00, 0x7016, 0x701a, 0x704b, 0x5280, 0x007c,
+	0x0e7e, 0x127e, 0x2091, 0x8000, 0x2009, 0xa32e, 0x210c, 0x81ff,
+	0x00c0, 0x530b, 0x2009, 0xa30c, 0x210c, 0xd194, 0x00c0, 0x5315,
+	0x6848, 0x2070, 0xae82, 0xaa00, 0x0048, 0x52fb, 0x2001, 0xa315,
+	0x2004, 0xae02, 0x00c8, 0x52fb, 0x2061, 0xa62d, 0x6100, 0xa184,
+	0x0301, 0xa086, 0x0001, 0x00c0, 0x52de, 0x711c, 0xa186, 0x0006,
+	0x00c0, 0x52e6, 0x7018, 0xa005, 0x0040, 0x530b, 0x2004, 0xd0e4,
+	0x00c0, 0x530f, 0x7024, 0xd0dc, 0x00c0, 0x5319, 0x6853, 0x0000,
+	0x6803, 0x0000, 0x2d08, 0x7010, 0xa005, 0x00c0, 0x52ca, 0x7112,
+	0x684c, 0xd0f4, 0x00c0, 0x531d, 0x2e60, 0x1078, 0x59b6, 0x127f,
+	0x0e7f, 0x007c, 0x2068, 0x6800, 0xa005, 0x00c0, 0x52ca, 0x6902,
+	0x2168, 0x684c, 0xd0f4, 0x00c0, 0x531d, 0x127f, 0x0e7f, 0x007c,
+	0x127f, 0x0e7f, 0x6853, 0x0006, 0x0078, 0x533e, 0xd184, 0x0040,
+	0x52d8, 0xd1c4, 0x00c0, 0x52ff, 0x0078, 0x5303, 0x6944, 0xa18c,
+	0xff00, 0x810f, 0x1078, 0x4501, 0x00c0, 0x530f, 0x6000, 0xd0e4,
+	0x00c0, 0x530f, 0x711c, 0xa186, 0x0007, 0x00c0, 0x52fb, 0x6853,
+	0x0002, 0x0078, 0x5311, 0x6853, 0x0008, 0x0078, 0x5311, 0x6853,
+	0x000e, 0x0078, 0x5311, 0x6853, 0x0017, 0x0078, 0x5311, 0x6853,
+	0x0035, 0x0078, 0x5311, 0x6853, 0x0028, 0x0078, 0x5311, 0x6853,
+	0x0029, 0x127f, 0x0e7f, 0x0078, 0x533e, 0x6853, 0x002a, 0x0078,
+	0x5311, 0x6853, 0x0045, 0x0078, 0x5311, 0x2e60, 0x2019, 0x0002,
+	0x6017, 0x0014, 0x1078, 0x9a6a, 0x127f, 0x0e7f, 0x007c, 0x2009,
+	0x003e, 0x0078, 0x5339, 0x2009, 0x0004, 0x0078, 0x5339, 0x2009,
+	0x0006, 0x0078, 0x5339, 0x2009, 0x0016, 0x0078, 0x5339, 0x2009,
+	0x0001, 0x6854, 0xa084, 0xff00, 0xa105, 0x6856, 0x2091, 0x8000,
+	0x1078, 0x4982, 0x2091, 0x8001, 0x007c, 0x1078, 0x139a, 0x007c,
+	0x702c, 0x7130, 0x8108, 0xa102, 0x0048, 0x5355, 0xa00e, 0x7034,
+	0x7072, 0x7038, 0x7076, 0x0078, 0x5361, 0x7070, 0xa080, 0x0040,
+	0x7072, 0x00c8, 0x5361, 0x7074, 0xa081, 0x0000, 0x7076, 0xa085,
+	0x0001, 0x7932, 0x7132, 0x007c, 0x0d7e, 0x1078, 0x59ad, 0x0d7f,
+	0x007c, 0x0d7e, 0x2011, 0x0004, 0x2204, 0xa085, 0x8002, 0x2012,
+	0x0d7f, 0x007c, 0x20e1, 0x0002, 0x3d08, 0x20e1, 0x2000, 0x3d00,
+	0xa084, 0x7000, 0x0040, 0x5380, 0xa086, 0x1000, 0x00c0, 0x53ac,
+	0x20e1, 0x0000, 0x3d00, 0xa094, 0xff00, 0x8217, 0xa084, 0xf000,
+	0xa086, 0x3000, 0x00c0, 0x5390, 0x1078, 0x5570, 0x0078, 0x53a7,
+	0x20e1, 0x0004, 0x3d60, 0xd1bc, 0x00c0, 0x5397, 0x3e60, 0xac84,
+	0x000f, 0x00c0, 0x53ac, 0xac82, 0xaa00, 0x0048, 0x53ac, 0x6854,
+	0xac02, 0x00c8, 0x53ac, 0x2009, 0x0047, 0x1078, 0x756c, 0x7a1c,
+	0xd284, 0x00c0, 0x5372, 0x007c, 0xa016, 0x1078, 0x15ec, 0x0078,
+	0x53a7, 0x0078, 0x53ac, 0x781c, 0xd08c, 0x0040, 0x53db, 0x157e,
+	0x137e, 0x147e, 0x20e1, 0x3000, 0x3d20, 0x3e28, 0xa584, 0x0076,
+	0x00c0, 0x53f1, 0xa484, 0x7000, 0xa086, 0x1000, 0x00c0, 0x53e0,
+	0x1078, 0x540c, 0x0040, 0x53f1, 0x20e1, 0x3000, 0x7828, 0x7828,
+	0x1078, 0x542a, 0x147f, 0x137f, 0x157f, 0x2009, 0xa5b3, 0x2104,
+	0xa005, 0x00c0, 0x53dc, 0x007c, 0x1078, 0x6109, 0x0078, 0x53db,
+	0xa484, 0x7000, 0x00c0, 0x53f1, 0x1078, 0x540c, 0x0040, 0x5403,
+	0x7000, 0xa084, 0xff00, 0xa086, 0x8100, 0x0040, 0x53cc, 0x0078,
+	0x5403, 0x1078, 0xa1ee, 0xd5a4, 0x0040, 0x53ff, 0x1078, 0x1af7,
+	0x20e1, 0x9010, 0x2001, 0x0138, 0x2202, 0x0078, 0x5407, 0x1078,
+	0x540c, 0x687f, 0x0000, 0x20e1, 0x3000, 0x7828, 0x7828, 0x147f,
+	0x137f, 0x157f, 0x0078, 0x53db, 0xa484, 0x01ff, 0x687e, 0xa005,
+	0x0040, 0x541e, 0xa080, 0x001f, 0xa084, 0x03f8, 0x80ac, 0x20e1,
+	0x1000, 0x2ea0, 0x2099, 0x020a, 0x53a5, 0x007c, 0x20a9, 0x000c,
+	0x20e1, 0x1000, 0x2ea0, 0x2099, 0x020a, 0x53a5, 0xa085, 0x0001,
+	0x0078, 0x541d, 0x7000, 0xa084, 0xff00, 0xa08c, 0xf000, 0x8007,
+	0xa196, 0x0000, 0x00c0, 0x5437, 0x0078, 0x567c, 0x007c, 0xa196,
+	0x2000, 0x00c0, 0x5448, 0x6900, 0xa18e, 0x0001, 0x00c0, 0x5444,
+	0x1078, 0x3a43, 0x0078, 0x5436, 0x1078, 0x5450, 0x0078, 0x5436,
+	0xa196, 0x8000, 0x00c0, 0x5436, 0x1078, 0x570c, 0x0078, 0x5436,
+	0x0c7e, 0x7110, 0xa18c, 0xff00, 0x810f, 0xa196, 0x0001, 0x0040,
+	0x545d, 0xa196, 0x0023, 0x00c0, 0x5568, 0xa08e, 0x0023, 0x00c0,
+	0x5492, 0x1078, 0x57b2, 0x0040, 0x5568, 0x7124, 0x610a, 0x7030,
+	0xa08e, 0x0200, 0x00c0, 0x5476, 0x7034, 0xa005, 0x00c0, 0x5568,
+	0x2009, 0x0015, 0x1078, 0x756c, 0x0078, 0x5568, 0xa08e, 0x0214,
+	0x0040, 0x547e, 0xa08e, 0x0210, 0x00c0, 0x5484, 0x2009, 0x0015,
+	0x1078, 0x756c, 0x0078, 0x5568, 0xa08e, 0x0100, 0x00c0, 0x5568,
+	0x7034, 0xa005, 0x00c0, 0x5568, 0x2009, 0x0016, 0x1078, 0x756c,
+	0x0078, 0x5568, 0xa08e, 0x0022, 0x00c0, 0x5568, 0x7030, 0xa08e,
+	0x0300, 0x00c0, 0x54a3, 0x7034, 0xa005, 0x00c0, 0x5568, 0x2009,
+	0x0017, 0x0078, 0x5534, 0xa08e, 0x0500, 0x00c0, 0x54af, 0x7034,
+	0xa005, 0x00c0, 0x5568, 0x2009, 0x0018, 0x0078, 0x5534, 0xa08e,
+	0x2010, 0x00c0, 0x54b7, 0x2009, 0x0019, 0x0078, 0x5534, 0xa08e,
+	0x2110, 0x00c0, 0x54bf, 0x2009, 0x001a, 0x0078, 0x5534, 0xa08e,
+	0x5200, 0x00c0, 0x54cb, 0x7034, 0xa005, 0x00c0, 0x5568, 0x2009,
+	0x001b, 0x0078, 0x5534, 0xa08e, 0x5000, 0x00c0, 0x54d7, 0x7034,
+	0xa005, 0x00c0, 0x5568, 0x2009, 0x001c, 0x0078, 0x5534, 0xa08e,
+	0x1300, 0x00c0, 0x54df, 0x2009, 0x0034, 0x0078, 0x5534, 0xa08e,
+	0x1200, 0x00c0, 0x54eb, 0x7034, 0xa005, 0x00c0, 0x5568, 0x2009,
+	0x0024, 0x0078, 0x5534, 0xa08c, 0xff00, 0xa18e, 0x2400, 0x00c0,
+	0x54f5, 0x2009, 0x002d, 0x0078, 0x5534, 0xa08c, 0xff00, 0xa18e,
+	0x5300, 0x00c0, 0x54ff, 0x2009, 0x002a, 0x0078, 0x5534, 0xa08e,
+	0x0f00, 0x00c0, 0x5507, 0x2009, 0x0020, 0x0078, 0x5534, 0xa08e,
+	0x5300, 0x00c0, 0x550d, 0x0078, 0x552a, 0xa08e, 0x6104, 0x00c0,
+	0x552a, 0x2011, 0xa88d, 0x8208, 0x2204, 0xa082, 0x0004, 0x20a8,
+	0x95ac, 0x95ac, 0x2011, 0x8015, 0x211c, 0x8108, 0x047e, 0x2124,
+	0x1078, 0x3579, 0x047f, 0x8108, 0x00f0, 0x551a, 0x2009, 0x0023,
+	0x0078, 0x5534, 0xa08e, 0x6000, 0x00c0, 0x5532, 0x2009, 0x003f,
+	0x0078, 0x5534, 0x2009, 0x001d, 0x017e, 0x2011, 0xa883, 0x2204,
+	0x8211, 0x220c, 0x1078, 0x24e3, 0x00c0, 0x556a, 0x1078, 0x4499,
+	0x00c0, 0x556a, 0x6612, 0x6516, 0x86ff, 0x0040, 0x555a, 0x017f,
+	0x017e, 0xa186, 0x0017, 0x00c0, 0x555a, 0x6868, 0xa606, 0x00c0,
+	0x555a, 0x686c, 0xa506, 0xa084, 0xff00, 0x00c0, 0x555a, 0x6000,
+	0xc0f5, 0x6002, 0x0c7e, 0x1078, 0x74d7, 0x0040, 0x556d, 0x017f,
+	0x611a, 0x601f, 0x0004, 0x7120, 0x610a, 0x017f, 0x1078, 0x756c,
+	0x0c7f, 0x007c, 0x017f, 0x0078, 0x5568, 0x0c7f, 0x0078, 0x556a,
+	0x0c7e, 0x1078, 0x55d4, 0x00c0, 0x55d2, 0xa184, 0xff00, 0x8007,
+	0xa086, 0x0008, 0x00c0, 0x55d2, 0xa28e, 0x0033, 0x00c0, 0x55a3,
+	0x1078, 0x57b2, 0x0040, 0x55d2, 0x7124, 0x610a, 0x7030, 0xa08e,
+	0x0200, 0x00c0, 0x5595, 0x7034, 0xa005, 0x00c0, 0x55d2, 0x2009,
+	0x0015, 0x1078, 0x756c, 0x0078, 0x55d2, 0xa08e, 0x0100, 0x00c0,
+	0x55d2, 0x7034, 0xa005, 0x00c0, 0x55d2, 0x2009, 0x0016, 0x1078,
+	0x756c, 0x0078, 0x55d2, 0xa28e, 0x0032, 0x00c0, 0x55d2, 0x7030,
+	0xa08e, 0x1400, 0x00c0, 0x55d2, 0x2009, 0x0038, 0x017e, 0x2011,
+	0xa883, 0x2204, 0x8211, 0x220c, 0x1078, 0x24e3, 0x00c0, 0x55d1,
+	0x1078, 0x4499, 0x00c0, 0x55d1, 0x6612, 0x6516, 0x0c7e, 0x1078,
+	0x74d7, 0x0040, 0x55d0, 0x017f, 0x611a, 0x601f, 0x0004, 0x7120,
+	0x610a, 0x017f, 0x1078, 0x756c, 0x1078, 0x6109, 0x0078, 0x55d2,
+	0x0c7f, 0x017f, 0x0c7f, 0x007c, 0x0f7e, 0x0d7e, 0x027e, 0x017e,
+	0x137e, 0x147e, 0x157e, 0x3c00, 0x007e, 0x2079, 0x0030, 0x2069,
+	0x0200, 0x1078, 0x1c25, 0x00c0, 0x5615, 0x1078, 0x1b15, 0x0040,
+	0x561f, 0x7908, 0xa18c, 0x1fff, 0xa182, 0x0011, 0x00c8, 0x561f,
+	0x20a9, 0x000c, 0x20e1, 0x0000, 0x2ea0, 0x2099, 0x020a, 0x53a5,
+	0x20e1, 0x2000, 0x2001, 0x020a, 0x2004, 0x7a0c, 0x7808, 0xa080,
+	0x0007, 0xa084, 0x1ff8, 0xa08a, 0x0140, 0x10c8, 0x1328, 0x80ac,
+	0x20e1, 0x6000, 0x2099, 0x020a, 0x53a5, 0x20e1, 0x7000, 0x6828,
+	0x6828, 0x7803, 0x0004, 0xa294, 0x0070, 0x007f, 0x20e0, 0x157f,
+	0x147f, 0x137f, 0x017f, 0x027f, 0x0d7f, 0x0f7f, 0x007c, 0xa085,
+	0x0001, 0x0078, 0x5615, 0x047e, 0x0e7e, 0x0d7e, 0x2028, 0x2130,
+	0xa696, 0x00ff, 0x00c0, 0x5644, 0xa596, 0xfffd, 0x00c0, 0x5634,
+	0x2009, 0x007f, 0x0078, 0x5677, 0xa596, 0xfffe, 0x00c0, 0x563c,
+	0x2009, 0x007e, 0x0078, 0x5677, 0xa596, 0xfffc, 0x00c0, 0x5644,
+	0x2009, 0x0080, 0x0078, 0x5677, 0x2011, 0x0000, 0x2021, 0x0081,
+	0x20a9, 0x007e, 0x2071, 0xa4b5, 0x2e1c, 0x83ff, 0x00c0, 0x5656,
+	0x82ff, 0x00c0, 0x566b, 0x2410, 0x0078, 0x566b, 0x2368, 0x6f10,
+	0x007e, 0x2100, 0xa706, 0x007f, 0x6b14, 0x00c0, 0x5665, 0xa346,
+	0x00c0, 0x5665, 0x2408, 0x0078, 0x5677, 0x87ff, 0x00c0, 0x566b,
+	0x83ff, 0x0040, 0x5650, 0x8420, 0x8e70, 0x00f0, 0x564c, 0x82ff,
+	0x00c0, 0x5676, 0xa085, 0x0001, 0x0078, 0x5678, 0x2208, 0xa006,
+	0x0d7f, 0x0e7f, 0x047f, 0x007c, 0xa084, 0x0007, 0x0079, 0x5681,
+	0x007c, 0x5689, 0x5689, 0x5689, 0x57c8, 0x5689, 0x568a, 0x56a3,
+	0x56f3, 0x007c, 0x7110, 0xd1bc, 0x0040, 0x56a2, 0x7120, 0x2160,
+	0xac8c, 0x000f, 0x00c0, 0x56a2, 0xac8a, 0xaa00, 0x0048, 0x56a2,
+	0x6854, 0xac02, 0x00c8, 0x56a2, 0x7124, 0x610a, 0x2009, 0x0046,
+	0x1078, 0x756c, 0x007c, 0x0c7e, 0x7110, 0xd1bc, 0x00c0, 0x56f1,
+	0x2011, 0xa883, 0x2204, 0x8211, 0x220c, 0x1078, 0x24e3, 0x00c0,
+	0x56f1, 0x1078, 0x4499, 0x00c0, 0x56f1, 0x6612, 0x6516, 0x6000,
+	0xd0ec, 0x00c0, 0x56f1, 0x6204, 0xa294, 0xff00, 0x8217, 0xa286,
+	0x0006, 0x00c0, 0x56d6, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040,
+	0x56f1, 0x611a, 0x601f, 0x0006, 0x7120, 0x610a, 0x7130, 0x6122,
+	0x2009, 0x0044, 0x1078, 0x756c, 0x0078, 0x56f1, 0x0c7e, 0x1078,
+	0x74d7, 0x017f, 0x0040, 0x56f1, 0x611a, 0x601f, 0x0004, 0x7120,
+	0x610a, 0xa286, 0x0004, 0x00c0, 0x56e9, 0x6007, 0x0005, 0x0078,
+	0x56eb, 0x6007, 0x0001, 0x6003, 0x0001, 0x1078, 0x5c45, 0x1078,
+	0x6109, 0x0c7f, 0x007c, 0x7110, 0xd1bc, 0x0040, 0x570b, 0x7020,
+	0x2060, 0xac84, 0x000f, 0x00c0, 0x570b, 0xac82, 0xaa00, 0x0048,
+	0x570b, 0x6854, 0xac02, 0x00c8, 0x570b, 0x7124, 0x610a, 0x2009,
+	0x0045, 0x1078, 0x756c, 0x007c, 0x7110, 0xa18c, 0xff00, 0x810f,
+	0xa18e, 0x0000, 0x00c0, 0x571c, 0xa084, 0x000f, 0xa08a, 0x0006,
+	0x00c8, 0x571c, 0x1079, 0x571d, 0x007c, 0x5723, 0x5724, 0x5723,
+	0x5723, 0x5794, 0x57a3, 0x007c, 0x7110, 0xd1bc, 0x0040, 0x572c,
+	0x702c, 0xd084, 0x0040, 0x5793, 0x700c, 0x7108, 0x1078, 0x24e3,
+	0x00c0, 0x5793, 0x1078, 0x4499, 0x00c0, 0x5793, 0x6612, 0x6516,
+	0x6204, 0x7110, 0xd1bc, 0x0040, 0x575e, 0xa28c, 0x00ff, 0xa186,
+	0x0004, 0x0040, 0x5747, 0xa186, 0x0006, 0x00c0, 0x5784, 0x0c7e,
+	0x1078, 0x57b2, 0x0c7f, 0x0040, 0x5793, 0x0c7e, 0x1078, 0x74d7,
+	0x017f, 0x0040, 0x5793, 0x611a, 0x601f, 0x0002, 0x7120, 0x610a,
+	0x2009, 0x0088, 0x1078, 0x756c, 0x0078, 0x5793, 0xa28c, 0x00ff,
+	0xa186, 0x0006, 0x0040, 0x5773, 0xa186, 0x0004, 0x0040, 0x5773,
+	0xa294, 0xff00, 0x8217, 0xa286, 0x0004, 0x0040, 0x5773, 0xa286,
+	0x0006, 0x00c0, 0x5784, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040,
+	0x5793, 0x611a, 0x601f, 0x0005, 0x7120, 0x610a, 0x2009, 0x0088,
+	0x1078, 0x756c, 0x0078, 0x5793, 0x0c7e, 0x1078, 0x74d7, 0x017f,
+	0x0040, 0x5793, 0x611a, 0x601f, 0x0004, 0x7120, 0x610a, 0x2009,
+	0x0001, 0x1078, 0x756c, 0x007c, 0x7110, 0xd1bc, 0x0040, 0x57a2,
+	0x1078, 0x57b2, 0x0040, 0x57a2, 0x7124, 0x610a, 0x2009, 0x0089,
+	0x1078, 0x756c, 0x007c, 0x7110, 0xd1bc, 0x0040, 0x57b1, 0x1078,
+	0x57b2, 0x0040, 0x57b1, 0x7124, 0x610a, 0x2009, 0x008a, 0x1078,
+	0x756c, 0x007c, 0x7020, 0x2060, 0xac84, 0x000f, 0x00c0, 0x57c5,
+	0xac82, 0xaa00, 0x0048, 0x57c5, 0x2001, 0xa315, 0x2004, 0xac02,
+	0x00c8, 0x57c5, 0xa085, 0x0001, 0x007c, 0xa006, 0x0078, 0x57c4,
+	0x7110, 0xd1bc, 0x00c0, 0x57de, 0x7024, 0x2060, 0xac84, 0x000f,
+	0x00c0, 0x57de, 0xac82, 0xaa00, 0x0048, 0x57de, 0x6854, 0xac02,
+	0x00c8, 0x57de, 0x2009, 0x0051, 0x1078, 0x756c, 0x007c, 0x2071,
+	0xa5be, 0x7003, 0x0003, 0x700f, 0x0361, 0xa006, 0x701a, 0x7012,
+	0x7017, 0xaa00, 0x7007, 0x0000, 0x7026, 0x702b, 0x6c4e, 0x7032,
+	0x7037, 0x6ca0, 0x703b, 0x0002, 0x703f, 0x0000, 0x7043, 0xffff,
+	0x7047, 0xffff, 0x007c, 0x2071, 0xa5be, 0x00e0, 0x58c1, 0x2091,
+	0x6000, 0x700c, 0x8001, 0x700e, 0x00c0, 0x5873, 0x700f, 0x0361,
+	0x7007, 0x0001, 0x127e, 0x2091, 0x8000, 0x7138, 0x8109, 0x713a,
+	0x00c0, 0x5871, 0x703b, 0x0002, 0x2009, 0x0100, 0x2104, 0xa082,
+	0x0003, 0x00c8, 0x5871, 0x703c, 0xa086, 0x0001, 0x00c0, 0x584e,
+	0x0d7e, 0x2069, 0x0140, 0x6804, 0xa084, 0x4000, 0x0040, 0x582c,
+	0x6803, 0x1000, 0x0078, 0x5833, 0x6804, 0xa084, 0x1000, 0x0040,
+	0x5833, 0x6803, 0x0100, 0x6803, 0x0000, 0x703f, 0x0000, 0x2069,
+	0xa5ab, 0x6804, 0xa082, 0x0006, 0x00c0, 0x5840, 0x6807, 0x0000,
+	0x6830, 0xa082, 0x0003, 0x00c0, 0x5847, 0x6833, 0x0000, 0x1078,
+	0x6109, 0x1078, 0x61d3, 0x0d7f, 0x0078, 0x5871, 0x0d7e, 0x2069,
+	0xa300, 0x6944, 0x6860, 0xa102, 0x00c8, 0x5870, 0x2069, 0xa5ab,
+	0x6804, 0xa086, 0x0000, 0x00c0, 0x5870, 0x6830, 0xa086, 0x0000,
+	0x00c0, 0x5870, 0x703f, 0x0001, 0x6807, 0x0006, 0x6833, 0x0003,
+	0x2069, 0x0100, 0x6830, 0x689e, 0x2069, 0x0140, 0x6803, 0x0600,
+	0x0d7f, 0x0078, 0x5876, 0x127e, 0x2091, 0x8000, 0x7024, 0xa00d,
+	0x0040, 0x588e, 0x7020, 0x8001, 0x7022, 0x00c0, 0x588e, 0x7023,
+	0x0009, 0x8109, 0x7126, 0xa186, 0x03e8, 0x00c0, 0x5889, 0x7028,
+	0x107a, 0x81ff, 0x00c0, 0x588e, 0x7028, 0x107a, 0x7030, 0xa00d,
+	0x0040, 0x589f, 0x702c, 0x8001, 0x702e, 0x00c0, 0x589f, 0x702f,
+	0x0009, 0x8109, 0x7132, 0x00c0, 0x589f, 0x7034, 0x107a, 0x7040,
+	0xa005, 0x0040, 0x58a7, 0x0050, 0x58a7, 0x8001, 0x7042, 0x7044,
+	0xa005, 0x0040, 0x58af, 0x0050, 0x58af, 0x8001, 0x7046, 0x7018,
+	0xa00d, 0x0040, 0x58c0, 0x7008, 0x8001, 0x700a, 0x00c0, 0x58c0,
+	0x700b, 0x0009, 0x8109, 0x711a, 0x00c0, 0x58c0, 0x701c, 0x107a,
+	0x127f, 0x7004, 0x0079, 0x58c4, 0x58eb, 0x58ec, 0x5908, 0x0e7e,
+	0x2071, 0xa5be, 0x7018, 0xa005, 0x00c0, 0x58d2, 0x711a, 0x721e,
+	0x700b, 0x0009, 0x0e7f, 0x007c, 0x0e7e, 0x007e, 0x2071, 0xa5be,
+	0x701c, 0xa206, 0x00c0, 0x58de, 0x701a, 0x701e, 0x007f, 0x0e7f,
+	0x007c, 0x0e7e, 0x2071, 0xa5be, 0x6088, 0xa102, 0x0048, 0x58e9,
+	0x618a, 0x0e7f, 0x007c, 0x007c, 0x7110, 0x1078, 0x4501, 0x00c0,
+	0x58fe, 0x6088, 0x8001, 0x0048, 0x58fe, 0x608a, 0x00c0, 0x58fe,
+	0x127e, 0x2091, 0x8000, 0x1078, 0x6109, 0x127f, 0x8108, 0xa182,
+	0x00ff, 0x0048, 0x5906, 0xa00e, 0x7007, 0x0002, 0x7112, 0x007c,
+	0x7014, 0x2060, 0x127e, 0x2091, 0x8000, 0x603c, 0xa005, 0x0040,
+	0x5917, 0x8001, 0x603e, 0x00c0, 0x5917, 0x1078, 0x8cd7, 0x6014,
+	0xa005, 0x0040, 0x5941, 0x8001, 0x6016, 0x00c0, 0x5941, 0x611c,
+	0xa186, 0x0003, 0x0040, 0x5928, 0xa186, 0x0006, 0x00c0, 0x593f,
+	0x6010, 0x2068, 0x6854, 0xa08a, 0x199a, 0x0048, 0x593f, 0xa082,
+	0x1999, 0x6856, 0xa08a, 0x199a, 0x0048, 0x5938, 0x2001, 0x1999,
+	0x8003, 0x800b, 0x810b, 0xa108, 0x6116, 0x0078, 0x5941, 0x1078,
+	0x8810, 0x127f, 0xac88, 0x0010, 0x7116, 0x2001, 0xca00, 0xa102,
+	0x0048, 0x594e, 0x7017, 0xaa00, 0x7007, 0x0000, 0x007c, 0x0e7e,
+	0x2071, 0xa5be, 0x7027, 0x07d0, 0x7023, 0x0009, 0x703b, 0x0002,
+	0x0e7f, 0x007c, 0x2001, 0xa5c7, 0x2003, 0x0000, 0x007c, 0x0e7e,
+	0x2071, 0xa5be, 0x7132, 0x702f, 0x0009, 0x0e7f, 0x007c, 0x2011,
+	0xa5ca, 0x2013, 0x0000, 0x007c, 0x0e7e, 0x2071, 0xa5be, 0x711a,
+	0x721e, 0x700b, 0x0009, 0x0e7f, 0x007c, 0x027e, 0x0e7e, 0x0f7e,
+	0x2079, 0xa300, 0x7a34, 0xd294, 0x0040, 0x59a4, 0x2071, 0xa5aa,
+	0x2e14, 0xa0fe, 0x0000, 0x0040, 0x5991, 0xa0fe, 0x0001, 0x0040,
+	0x5995, 0xa0fe, 0x0002, 0x00c0, 0x59a0, 0xa292, 0x0085, 0x0078,
+	0x5997, 0xa292, 0x0005, 0x0078, 0x5997, 0xa292, 0x0002, 0x2272,
+	0x0040, 0x599c, 0x00c8, 0x59a4, 0x2011, 0x8037, 0x1078, 0x3579,
+	0x2011, 0xa5a9, 0x2204, 0x2072, 0x0f7f, 0x0e7f, 0x027f, 0x007c,
+	0x0c7e, 0x2061, 0xa62d, 0x0c7f, 0x007c, 0xa184, 0x000f, 0x8003,
+	0x8003, 0x8003, 0xa080, 0xa62d, 0x2060, 0x007c, 0x6854, 0xa08a,
+	0x199a, 0x0048, 0x59bd, 0x2001, 0x1999, 0xa005, 0x00c0, 0x59cc,
+	0x0c7e, 0x2061, 0xa62d, 0x6014, 0x0c7f, 0xa005, 0x00c0, 0x59d1,
+	0x2001, 0x001e, 0x0078, 0x59d1, 0xa08e, 0xffff, 0x00c0, 0x59d1,
+	0xa006, 0x8003, 0x800b, 0x810b, 0xa108, 0x6116, 0x684c, 0xa08c,
+	0x00c0, 0xa18e, 0x00c0, 0x0040, 0x5a24, 0xd0b4, 0x00c0, 0x59e8,
+	0xd0bc, 0x00c0, 0x5a14, 0x2009, 0x0006, 0x1078, 0x5a43, 0x007c,
+	0xd0fc, 0x0040, 0x59f3, 0xa084, 0x0003, 0x0040, 0x59f3, 0xa086,
+	0x0003, 0x00c0, 0x5a3c, 0x6024, 0xd0d4, 0x0040, 0x59fd, 0xc0d4,
+	0x6026, 0x6860, 0x602a, 0x685c, 0x602e, 0x2009, 0xa373, 0x2104,
+	0xd084, 0x0040, 0x5a0f, 0x6118, 0xa188, 0x0027, 0x2104, 0xd08c,
+	0x00c0, 0x5a0f, 0x2009, 0x0042, 0x1078, 0x756c, 0x007c, 0x2009,
+	0x0043, 0x1078, 0x756c, 0x007c, 0xd0fc, 0x0040, 0x5a1f, 0xa084,
+	0x0003, 0x0040, 0x5a1f, 0xa086, 0x0003, 0x00c0, 0x5a3c, 0x2009,
+	0x0042, 0x1078, 0x756c, 0x007c, 0xd0fc, 0x0040, 0x5a32, 0xa084,
+	0x0003, 0xa08e, 0x0002, 0x0040, 0x5a36, 0x2009, 0x0041, 0x1078,
+	0x756c, 0x007c, 0x1078, 0x5a41, 0x0078, 0x5a31, 0x2009, 0x0043,
+	0x1078, 0x756c, 0x0078, 0x5a31, 0x2009, 0x0004, 0x1078, 0x5a43,
+	0x007c, 0x2009, 0x0001, 0x0d7e, 0x6010, 0xa0ec, 0xf000, 0x0040,
+	0x5a6b, 0x2068, 0x6952, 0x6800, 0x6012, 0xa186, 0x0001, 0x00c0,
+	0x5a65, 0x694c, 0xa18c, 0x8100, 0xa18e, 0x8100, 0x00c0, 0x5a65,
+	0x0c7e, 0x2061, 0xa62d, 0x6200, 0xd28c, 0x00c0, 0x5a64, 0x6204,
+	0x8210, 0x0048, 0x5a64, 0x6206, 0x0c7f, 0x1078, 0x4982, 0x6010,
+	0xa06d, 0x10c0, 0x59b6, 0x0d7f, 0x007c, 0x157e, 0x0c7e, 0x2061,
+	0xa62d, 0x6000, 0x81ff, 0x0040, 0x5a78, 0xa205, 0x0078, 0x5a79,
+	0xa204, 0x6002, 0x0c7f, 0x157f, 0x007c, 0x6800, 0xd08c, 0x00c0,
+	0x5a89, 0x6808, 0xa005, 0x0040, 0x5a89, 0x8001, 0x680a, 0xa085,
+	0x0001, 0x007c, 0x20a9, 0x0010, 0xa006, 0x8004, 0x8086, 0x818e,
+	0x00c8, 0x5a93, 0xa200, 0x00f0, 0x5a8e, 0x8086, 0x818e, 0x007c,
+	0x157e, 0x20a9, 0x0010, 0xa005, 0x0040, 0x5ab9, 0xa11a, 0x00c8,
+	0x5ab9, 0x8213, 0x818d, 0x0048, 0x5aac, 0xa11a, 0x00c8, 0x5aad,
+	0x00f0, 0x5aa1, 0x0078, 0x5ab1, 0xa11a, 0x2308, 0x8210, 0x00f0,
+	0x5aa1, 0x007e, 0x3200, 0xa084, 0xf7ff, 0x2080, 0x007f, 0x157f,
+	0x007c, 0x007e, 0x3200, 0xa085, 0x0800, 0x0078, 0x5ab5, 0x127e,
+	0x2091, 0x2200, 0x2079, 0xa5ab, 0x127f, 0x0d7e, 0x2069, 0xa5ab,
+	0x6803, 0x0005, 0x2069, 0x0004, 0x2d04, 0xa085, 0x8001, 0x206a,
+	0x0d7f, 0x007c, 0x0c7e, 0x6027, 0x0001, 0x7804, 0xa084, 0x0007,
+	0x0079, 0x5ada, 0x5ae4, 0x5b09, 0x5b64, 0x5aea, 0x5b09, 0x5ae4,
+	0x5ae2, 0x5ae2, 0x1078, 0x1328, 0x1078, 0x595a, 0x1078, 0x6109,
+	0x0c7f, 0x007c, 0x62c0, 0x82ff, 0x00c0, 0x5af0, 0x0c7f, 0x007c,
+	0x2011, 0x4129, 0x1078, 0x58d4, 0x7828, 0xa092, 0x00c8, 0x00c8,
+	0x5aff, 0x8000, 0x782a, 0x1078, 0x4168, 0x0078, 0x5aee, 0x1078,
+	0x4129, 0x7807, 0x0003, 0x7827, 0x0000, 0x782b, 0x0000, 0x0078,
+	0x5aee, 0x1078, 0x595a, 0x3c00, 0x007e, 0x2011, 0x0209, 0x20e1,
+	0x4000, 0x2214, 0x007f, 0x20e0, 0x82ff, 0x0040, 0x5b27, 0x62c0,
+	0x82ff, 0x00c0, 0x5b27, 0x782b, 0x0000, 0x7824, 0xa065, 0x1040,
+	0x1328, 0x2009, 0x0013, 0x1078, 0x756c, 0x0c7f, 0x007c, 0x3900,
+	0xa082, 0xa6cd, 0x00c8, 0x5b2e, 0x1078, 0x728a, 0x0c7e, 0x7824,
+	0xa065, 0x1040, 0x1328, 0x7804, 0xa086, 0x0004, 0x0040, 0x5ba9,
+	0x7828, 0xa092, 0x2710, 0x00c8, 0x5b44, 0x8000, 0x782a, 0x0c7f,
+	0x1078, 0x6c33, 0x0078, 0x5b25, 0x6104, 0xa186, 0x0003, 0x00c0,
+	0x5b5b, 0x0e7e, 0x2071, 0xa300, 0x70d4, 0x0e7f, 0xd08c, 0x0040,
+	0x5b5b, 0x0c7e, 0x0e7e, 0x2061, 0x0100, 0x2071, 0xa300, 0x1078,
+	0x4171, 0x0e7f, 0x0c7f, 0x1078, 0xa241, 0x2009, 0x0014, 0x1078,
+	0x756c, 0x0c7f, 0x0078, 0x5b25, 0x2001, 0xa5c7, 0x2003, 0x0000,
+	0x62c0, 0x82ff, 0x00c0, 0x5b78, 0x782b, 0x0000, 0x7824, 0xa065,
+	0x1040, 0x1328, 0x2009, 0x0013, 0x1078, 0x75c3, 0x0c7f, 0x007c,
+	0x0c7e, 0x0d7e, 0x3900, 0xa082, 0xa6cd, 0x00c8, 0x5b81, 0x1078,
+	0x728a, 0x7824, 0xa005, 0x1040, 0x1328, 0x781c, 0xa06d, 0x1040,
+	0x1328, 0x6800, 0xc0dc, 0x6802, 0x7924, 0x2160, 0x1078, 0x753d,
+	0x693c, 0x81ff, 0x1040, 0x1328, 0x8109, 0x693e, 0x6854, 0xa015,
+	0x0040, 0x5b9d, 0x7a1e, 0x0078, 0x5b9f, 0x7918, 0x791e, 0x7807,
+	0x0000, 0x7827, 0x0000, 0x0d7f, 0x0c7f, 0x1078, 0x6109, 0x0078,
+	0x5b76, 0x6104, 0xa186, 0x0002, 0x0040, 0x5bb4, 0xa186, 0x0004,
+	0x0040, 0x5bb4, 0x0078, 0x5b38, 0x7808, 0xac06, 0x0040, 0x5b38,
+	0x1078, 0x6010, 0x1078, 0x5c45, 0x0c7f, 0x1078, 0x6109, 0x0078,
+	0x5b25, 0x0c7e, 0x6027, 0x0002, 0x62c8, 0x82ff, 0x00c0, 0x5bdb,
+	0x62c4, 0x82ff, 0x00c0, 0x5bdb, 0x793c, 0xa1e5, 0x0000, 0x0040,
+	0x5bd5, 0x2009, 0x0049, 0x1078, 0x756c, 0x2011, 0xa5ca, 0x2013,
+	0x0000, 0x0c7f, 0x007c, 0x3908, 0xa192, 0xa6cd, 0x00c8, 0x5be2,
+	0x1078, 0x728a, 0x6017, 0x0010, 0x793c, 0x81ff, 0x0040, 0x5bd5,
+	0x793c, 0xa188, 0x0007, 0x210c, 0xa18e, 0x0006, 0x00c0, 0x5bf4,
+	0x6017, 0x0012, 0x0078, 0x5bd9, 0x6017, 0x0016, 0x0078, 0x5bd9,
+	0x007e, 0x017e, 0x0c7e, 0x127e, 0x2091, 0x8000, 0x600f, 0x0000,
+	0x2c08, 0x2061, 0xa5ab, 0x6020, 0x8000, 0x6022, 0x6010, 0xa005,
+	0x0040, 0x5c13, 0xa080, 0x0003, 0x2102, 0x6112, 0x127f, 0x0c7f,
+	0x017f, 0x007f, 0x007c, 0x6116, 0x6112, 0x0078, 0x5c0e, 0x0d7e,
+	0x2069, 0xa5ab, 0x6000, 0xd0d4, 0x0040, 0x5c2c, 0x6820, 0x8000,
+	0x6822, 0xa086, 0x0001, 0x00c0, 0x5c27, 0x2c00, 0x681e, 0x6804,
+	0xa084, 0x0007, 0x0079, 0x6111, 0xc0d5, 0x6002, 0x6818, 0xa005,
+	0x0040, 0x5c3e, 0x6056, 0x605b, 0x0000, 0x007e, 0x2c00, 0x681a,
+	0x0d7f, 0x685a, 0x2069, 0xa5ab, 0x0078, 0x5c1e, 0x6056, 0x605a,
+	0x2c00, 0x681a, 0x681e, 0x0078, 0x5c1e, 0x007e, 0x017e, 0x0c7e,
+	0x127e, 0x2091, 0x8000, 0x600f, 0x0000, 0x2c08, 0x2061, 0xa5ab,
+	0x6020, 0x8000, 0x6022, 0x6008, 0xa005, 0x0040, 0x5c60, 0xa080,
+	0x0003, 0x2102, 0x610a, 0x127f, 0x0c7f, 0x017f, 0x007f, 0x007c,
+	0x610e, 0x610a, 0x0078, 0x5c5b, 0x0c7e, 0x600f, 0x0000, 0x2c08,
+	0x2061, 0xa5ab, 0x6034, 0xa005, 0x0040, 0x5c74, 0xa080, 0x0003,
+	0x2102, 0x6136, 0x0c7f, 0x007c, 0x613a, 0x6136, 0x0078, 0x5c72,
+	0x0f7e, 0x0e7e, 0x0d7e, 0x0c7e, 0x067e, 0x027e, 0x017e, 0x007e,
+	0x127e, 0x2071, 0xa5ab, 0x7638, 0x2660, 0x2678, 0x2091, 0x8000,
+	0x8cff, 0x0040, 0x5ced, 0x6018, 0xa080, 0x0028, 0x2004, 0xa206,
+	0x00c0, 0x5ce8, 0x87ff, 0x0040, 0x5c99, 0x6020, 0xa106, 0x00c0,
+	0x5ce8, 0x703c, 0xac06, 0x00c0, 0x5cab, 0x037e, 0x2019, 0x0001,
+	0x1078, 0x6e6c, 0x7033, 0x0000, 0x703f, 0x0000, 0x7043, 0x0000,
+	0x7047, 0x0000, 0x037f, 0x7038, 0xac36, 0x00c0, 0x5cb1, 0x660c,
+	0x763a, 0x7034, 0xac36, 0x00c0, 0x5cbf, 0x2c00, 0xaf36, 0x0040,
+	0x5cbd, 0x2f00, 0x7036, 0x0078, 0x5cbf, 0x7037, 0x0000, 0x660c,
+	0x067e, 0x2c00, 0xaf06, 0x0040, 0x5cc8, 0x7e0e, 0x0078, 0x5cc9,
+	0x2678, 0x600f, 0x0000, 0x1078, 0x8a44, 0x0040, 0x5ce3, 0x6010,
+	0x2068, 0x601c, 0xa086, 0x0003, 0x00c0, 0x5cf7, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x1078, 0x8cb8, 0x1078, 0xa181, 0x1078,
+	0x4982, 0x1078, 0x8bf4, 0x1078, 0x8c01, 0x0c7f, 0x0078, 0x5c88,
+	0x2c78, 0x600c, 0x2060, 0x0078, 0x5c88, 0x127f, 0x007f, 0x017f,
+	0x027f, 0x067f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f, 0x007c, 0x601c,
+	0xa086, 0x0006, 0x00c0, 0x5cd6, 0x1078, 0xa181, 0x1078, 0x9e70,
+	0x0078, 0x5ce3, 0x007e, 0x067e, 0x0c7e, 0x0d7e, 0x0f7e, 0x2031,
+	0x0000, 0x127e, 0x2091, 0x8000, 0x2079, 0xa5ab, 0x7838, 0xa065,
+	0x0040, 0x5d41, 0x600c, 0x007e, 0x600f, 0x0000, 0x783c, 0xac06,
+	0x00c0, 0x5d28, 0x037e, 0x2019, 0x0001, 0x1078, 0x6e6c, 0x7833,
+	0x0000, 0x783f, 0x0000, 0x7843, 0x0000, 0x7847, 0x0000, 0x037f,
+	0x1078, 0x8a44, 0x0040, 0x5d3c, 0x6010, 0x2068, 0x601c, 0xa086,
+	0x0003, 0x00c0, 0x5d4a, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000,
+	0x1078, 0x4982, 0x1078, 0x8bf4, 0x1078, 0x8c01, 0x007f, 0x0078,
+	0x5d0f, 0x7e3a, 0x7e36, 0x127f, 0x0f7f, 0x0d7f, 0x0c7f, 0x067f,
+	0x007f, 0x007c, 0x601c, 0xa086, 0x0006, 0x00c0, 0x5d33, 0x1078,
+	0x9e70, 0x0078, 0x5d3c, 0x017e, 0x027e, 0x087e, 0x2041, 0x0000,
+	0x1078, 0x5d6d, 0x1078, 0x5e21, 0x087f, 0x027f, 0x017f, 0x007c,
+	0x0f7e, 0x127e, 0x2079, 0xa5ab, 0x2091, 0x8000, 0x1078, 0x5ebc,
+	0x1078, 0x5f32, 0x127f, 0x0f7f, 0x007c, 0x0f7e, 0x0e7e, 0x0d7e,
+	0x0c7e, 0x067e, 0x017e, 0x007e, 0x127e, 0x2091, 0x8000, 0x2071,
+	0xa5ab, 0x7614, 0x2660, 0x2678, 0x8cff, 0x0040, 0x5e01, 0x6018,
+	0xa080, 0x0028, 0x2004, 0xa206, 0x00c0, 0x5dfc, 0x88ff, 0x0040,
+	0x5d8d, 0x6020, 0xa106, 0x00c0, 0x5dfc, 0x7024, 0xac06, 0x00c0,
+	0x5dbd, 0x2069, 0x0100, 0x68c0, 0xa005, 0x0040, 0x5db8, 0x1078,
+	0x595a, 0x1078, 0x6c41, 0x68c3, 0x0000, 0x1078, 0x7188, 0x7027,
+	0x0000, 0x037e, 0x2069, 0x0140, 0x6b04, 0xa384, 0x1000, 0x0040,
+	0x5dad, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824,
+	0xd084, 0x0040, 0x5db5, 0x6827, 0x0001, 0x037f, 0x0078, 0x5dbd,
+	0x6003, 0x0009, 0x630a, 0x0078, 0x5dfc, 0x7014, 0xac36, 0x00c0,
+	0x5dc3, 0x660c, 0x7616, 0x7010, 0xac36, 0x00c0, 0x5dd1, 0x2c00,
+	0xaf36, 0x0040, 0x5dcf, 0x2f00, 0x7012, 0x0078, 0x5dd1, 0x7013,
+	0x0000, 0x660c, 0x067e, 0x2c00, 0xaf06, 0x0040, 0x5dda, 0x7e0e,
+	0x0078, 0x5ddb, 0x2678, 0x600f, 0x0000, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x5df5, 0x601c, 0xa086, 0x0003, 0x00c0, 0x5e0a,
+	0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x1078, 0x8cb8, 0x1078,
+	0xa181, 0x1078, 0x4982, 0x1078, 0x8bf4, 0x1078, 0x8c01, 0x1078,
+	0x7045, 0x0c7f, 0x0078, 0x5d7c, 0x2c78, 0x600c, 0x2060, 0x0078,
+	0x5d7c, 0x127f, 0x007f, 0x017f, 0x067f, 0x0c7f, 0x0d7f, 0x0e7f,
+	0x0f7f, 0x007c, 0x601c, 0xa086, 0x0006, 0x00c0, 0x5e15, 0x1078,
+	0xa181, 0x1078, 0x9e70, 0x0078, 0x5df5, 0x601c, 0xa086, 0x0002,
+	0x00c0, 0x5df5, 0x6004, 0xa086, 0x0085, 0x0040, 0x5de8, 0x0078,
+	0x5df5, 0x0c7e, 0x007e, 0x127e, 0x2091, 0x8000, 0xa280, 0xa434,
+	0x2004, 0xa065, 0x0040, 0x5eb8, 0x0f7e, 0x0e7e, 0x0d7e, 0x067e,
+	0x2071, 0xa5ab, 0x6654, 0x7018, 0xac06, 0x00c0, 0x5e38, 0x761a,
+	0x701c, 0xac06, 0x00c0, 0x5e44, 0x86ff, 0x00c0, 0x5e43, 0x7018,
+	0x701e, 0x0078, 0x5e44, 0x761e, 0x6058, 0xa07d, 0x0040, 0x5e49,
+	0x7e56, 0xa6ed, 0x0000, 0x0040, 0x5e4f, 0x2f00, 0x685a, 0x6057,
+	0x0000, 0x605b, 0x0000, 0x6000, 0xc0d4, 0xc0dc, 0x6002, 0x1078,
+	0x4410, 0x0040, 0x5eb4, 0x7624, 0x86ff, 0x0040, 0x5ea2, 0xa680,
+	0x0004, 0x2004, 0xad06, 0x00c0, 0x5ea2, 0x0d7e, 0x2069, 0x0100,
+	0x68c0, 0xa005, 0x0040, 0x5e99, 0x1078, 0x595a, 0x1078, 0x6c41,
+	0x68c3, 0x0000, 0x1078, 0x7188, 0x7027, 0x0000, 0x037e, 0x2069,
+	0x0140, 0x6b04, 0xa384, 0x1000, 0x0040, 0x5e82, 0x6803, 0x0100,
+	0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0040, 0x5e8a,
+	0x6827, 0x0001, 0x037f, 0x0d7f, 0x0c7e, 0x603c, 0xa005, 0x0040,
+	0x5e93, 0x8001, 0x603e, 0x2660, 0x1078, 0x8c01, 0x0c7f, 0x0078,
+	0x5ea2, 0x0d7f, 0x0c7e, 0x2660, 0x6003, 0x0009, 0x630a, 0x0c7f,
+	0x0078, 0x5e57, 0x8dff, 0x0040, 0x5eb0, 0x6837, 0x0103, 0x6b4a,
+	0x6847, 0x0000, 0x1078, 0x8cb8, 0x1078, 0xa181, 0x1078, 0x4982,
+	0x1078, 0x7045, 0x0078, 0x5e57, 0x067f, 0x0d7f, 0x0e7f, 0x0f7f,
+	0x127f, 0x007f, 0x0c7f, 0x007c, 0x007e, 0x067e, 0x0c7e, 0x0d7e,
+	0x2031, 0x0000, 0x7814, 0xa065, 0x0040, 0x5f16, 0x600c, 0x007e,
+	0x600f, 0x0000, 0x7824, 0xac06, 0x00c0, 0x5efb, 0x2069, 0x0100,
+	0x68c0, 0xa005, 0x0040, 0x5ef5, 0x1078, 0x595a, 0x1078, 0x6c41,
+	0x68c3, 0x0000, 0x1078, 0x7188, 0x7827, 0x0000, 0x037e, 0x2069,
+	0x0140, 0x6b04, 0xa384, 0x1000, 0x0040, 0x5eea, 0x6803, 0x0100,
+	0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0040, 0x5ef2,
+	0x6827, 0x0001, 0x037f, 0x0078, 0x5efb, 0x6003, 0x0009, 0x630a,
+	0x2c30, 0x0078, 0x5f13, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040,
+	0x5f0f, 0x601c, 0xa086, 0x0003, 0x00c0, 0x5f1d, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x1078, 0x4982, 0x1078, 0x8bf4, 0x1078,
+	0x8c01, 0x1078, 0x7045, 0x007f, 0x0078, 0x5ec3, 0x7e16, 0x7e12,
+	0x0d7f, 0x0c7f, 0x067f, 0x007f, 0x007c, 0x601c, 0xa086, 0x0006,
+	0x00c0, 0x5f26, 0x1078, 0x9e70, 0x0078, 0x5f0f, 0x601c, 0xa086,
+	0x0002, 0x00c0, 0x5f0f, 0x6004, 0xa086, 0x0085, 0x0040, 0x5f06,
+	0x0078, 0x5f0f, 0x007e, 0x067e, 0x0c7e, 0x0d7e, 0x7818, 0xa065,
+	0x0040, 0x5fa0, 0x6054, 0x007e, 0x6057, 0x0000, 0x605b, 0x0000,
+	0x6000, 0xc0d4, 0xc0dc, 0x6002, 0x1078, 0x4410, 0x0040, 0x5f9d,
+	0x7e24, 0x86ff, 0x0040, 0x5f8f, 0xa680, 0x0004, 0x2004, 0xad06,
+	0x00c0, 0x5f8f, 0x0d7e, 0x2069, 0x0100, 0x68c0, 0xa005, 0x0040,
+	0x5f86, 0x1078, 0x595a, 0x1078, 0x6c41, 0x68c3, 0x0000, 0x1078,
+	0x7188, 0x7827, 0x0000, 0x037e, 0x2069, 0x0140, 0x6b04, 0xa384,
+	0x1000, 0x0040, 0x5f6f, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069,
+	0x0100, 0x6824, 0xd084, 0x0040, 0x5f77, 0x6827, 0x0001, 0x037f,
+	0x0d7f, 0x0c7e, 0x603c, 0xa005, 0x0040, 0x5f80, 0x8001, 0x603e,
+	0x2660, 0x1078, 0x8c01, 0x0c7f, 0x0078, 0x5f8f, 0x0d7f, 0x0c7e,
+	0x2660, 0x6003, 0x0009, 0x630a, 0x0c7f, 0x0078, 0x5f44, 0x8dff,
+	0x0040, 0x5f99, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x1078,
+	0x4982, 0x1078, 0x7045, 0x0078, 0x5f44, 0x007f, 0x0078, 0x5f37,
+	0x781e, 0x781a, 0x0d7f, 0x0c7f, 0x067f, 0x007f, 0x007c, 0x0e7e,
+	0x0d7e, 0x067e, 0x6000, 0xd0dc, 0x0040, 0x5fc4, 0x604c, 0xa06d,
+	0x0040, 0x5fc4, 0x6848, 0xa606, 0x00c0, 0x5fc4, 0x2071, 0xa5ab,
+	0x7024, 0xa035, 0x0040, 0x5fc4, 0xa080, 0x0004, 0x2004, 0xad06,
+	0x00c0, 0x5fc4, 0x1078, 0x5fc8, 0x067f, 0x0d7f, 0x0e7f, 0x007c,
+	0x0f7e, 0x2079, 0x0100, 0x78c0, 0xa005, 0x00c0, 0x5fd7, 0x0c7e,
+	0x2660, 0x6003, 0x0009, 0x630a, 0x0c7f, 0x0078, 0x600e, 0x1078,
+	0x6c41, 0x78c3, 0x0000, 0x1078, 0x7188, 0x7027, 0x0000, 0x037e,
+	0x2079, 0x0140, 0x7b04, 0xa384, 0x1000, 0x0040, 0x5feb, 0x7803,
+	0x0100, 0x7803, 0x0000, 0x2079, 0x0100, 0x7824, 0xd084, 0x0040,
+	0x5ff3, 0x7827, 0x0001, 0x1078, 0x7188, 0x037f, 0x1078, 0x4410,
+	0x0c7e, 0x603c, 0xa005, 0x0040, 0x5fff, 0x8001, 0x603e, 0x2660,
+	0x1078, 0x753d, 0x0c7f, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000,
+	0x1078, 0x8cb8, 0x1078, 0x4982, 0x1078, 0x7045, 0x0f7f, 0x007c,
+	0x0e7e, 0x0c7e, 0x2071, 0xa5ab, 0x7004, 0xa084, 0x0007, 0x0079,
+	0x6019, 0x6023, 0x6026, 0x603f, 0x605b, 0x60a0, 0x6023, 0x6023,
+	0x6021, 0x1078, 0x1328, 0x0c7f, 0x0e7f, 0x007c, 0x7024, 0xa065,
+	0x0040, 0x6034, 0x7020, 0x8001, 0x7022, 0x600c, 0xa015, 0x0040,
+	0x603b, 0x7216, 0x600f, 0x0000, 0x7007, 0x0000, 0x7027, 0x0000,
+	0x0c7f, 0x0e7f, 0x007c, 0x7216, 0x7212, 0x0078, 0x6034, 0x6018,
+	0x2060, 0x1078, 0x4410, 0x6000, 0xc0dc, 0x6002, 0x7020, 0x8001,
+	0x7022, 0x0040, 0x6050, 0x6054, 0xa015, 0x0040, 0x6057, 0x721e,
+	0x7007, 0x0000, 0x7027, 0x0000, 0x0c7f, 0x0e7f, 0x007c, 0x7218,
+	0x721e, 0x0078, 0x6050, 0x7024, 0xa065, 0x0040, 0x609d, 0x700c,
+	0xac06, 0x00c0, 0x6072, 0x1078, 0x7045, 0x600c, 0xa015, 0x0040,
+	0x606e, 0x720e, 0x600f, 0x0000, 0x0078, 0x609b, 0x720e, 0x720a,
+	0x0078, 0x609b, 0x7014, 0xac06, 0x00c0, 0x6085, 0x1078, 0x7045,
+	0x600c, 0xa015, 0x0040, 0x6081, 0x7216, 0x600f, 0x0000, 0x0078,
+	0x609b, 0x7216, 0x7212, 0x0078, 0x609b, 0x6018, 0x2060, 0x1078,
+	0x4410, 0x6000, 0xc0dc, 0x6002, 0x1078, 0x7045, 0x701c, 0xa065,
+	0x0040, 0x609b, 0x6054, 0xa015, 0x0040, 0x6099, 0x721e, 0x0078,
+	0x609b, 0x7218, 0x721e, 0x7027, 0x0000, 0x0c7f, 0x0e7f, 0x007c,
+	0x7024, 0xa065, 0x0040, 0x60ad, 0x1078, 0x7045, 0x600c, 0xa015,
+	0x0040, 0x60b4, 0x720e, 0x600f, 0x0000, 0x1078, 0x7188, 0x7027,
+	0x0000, 0x0c7f, 0x0e7f, 0x007c, 0x720e, 0x720a, 0x0078, 0x60ad,
+	0x0d7e, 0x2069, 0xa5ab, 0x6830, 0xa084, 0x0003, 0x0079, 0x60c0,
+	0x60c6, 0x60c8, 0x60ee, 0x60c6, 0x1078, 0x1328, 0x0d7f, 0x007c,
+	0x0c7e, 0x6840, 0xa086, 0x0001, 0x0040, 0x60e4, 0x683c, 0xa065,
+	0x0040, 0x60d9, 0x600c, 0xa015, 0x0040, 0x60e0, 0x6a3a, 0x600f,
+	0x0000, 0x6833, 0x0000, 0x683f, 0x0000, 0x0c7f, 0x0d7f, 0x007c,
+	0x683a, 0x6836, 0x0078, 0x60d9, 0x6843, 0x0000, 0x6838, 0xa065,
+	0x0040, 0x60d9, 0x6003, 0x0003, 0x0078, 0x60d9, 0x0c7e, 0x6843,
+	0x0000, 0x6847, 0x0000, 0x683c, 0xa065, 0x0040, 0x6106, 0x600c,
+	0xa015, 0x0040, 0x6102, 0x6a3a, 0x600f, 0x0000, 0x683f, 0x0000,
+	0x0078, 0x6106, 0x683f, 0x0000, 0x683a, 0x6836, 0x0c7f, 0x0d7f,
+	0x007c, 0x0d7e, 0x2069, 0xa5ab, 0x6804, 0xa084, 0x0007, 0x0079,
+	0x6111, 0x611b, 0x61c2, 0x61c2, 0x61c2, 0x61c2, 0x61c4, 0x61c2,
+	0x6119, 0x1078, 0x1328, 0x6820, 0xa005, 0x00c0, 0x6121, 0x0d7f,
+	0x007c, 0x0c7e, 0x680c, 0xa065, 0x0040, 0x6130, 0x6807, 0x0004,
+	0x6826, 0x682b, 0x0000, 0x1078, 0x620a, 0x0c7f, 0x0d7f, 0x007c,
+	0x6814, 0xa065, 0x0040, 0x613e, 0x6807, 0x0001, 0x6826, 0x682b,
+	0x0000, 0x1078, 0x620a, 0x0c7f, 0x0d7f, 0x007c, 0x0e7e, 0x037e,
+	0x6a1c, 0xa2f5, 0x0000, 0x0040, 0x61bd, 0x704c, 0xa00d, 0x0040,
+	0x614d, 0x7088, 0xa005, 0x0040, 0x6165, 0x7054, 0xa075, 0x0040,
+	0x6156, 0xa20e, 0x0040, 0x61bd, 0x0078, 0x615b, 0x6818, 0xa20e,
+	0x0040, 0x61bd, 0x2070, 0x704c, 0xa00d, 0x0040, 0x614d, 0x7088,
+	0xa005, 0x00c0, 0x614d, 0x2e00, 0x681e, 0x733c, 0x7038, 0xa302,
+	0x00c8, 0x614d, 0x1078, 0x750c, 0x0040, 0x61bd, 0x8318, 0x733e,
+	0x6112, 0x2e10, 0x621a, 0xa180, 0x0014, 0x2004, 0xa084, 0x00ff,
+	0x6032, 0xa180, 0x0014, 0x2003, 0x0000, 0xa180, 0x0015, 0x2004,
+	0xa08a, 0x199a, 0x0048, 0x6186, 0x2001, 0x1999, 0x8003, 0x801b,
+	0x831b, 0xa318, 0x6316, 0x037f, 0x0f7e, 0x2c78, 0x71a0, 0xd1bc,
+	0x0040, 0x619f, 0x7100, 0xd1f4, 0x0040, 0x619b, 0x7114, 0xa18c,
+	0x00ff, 0x0078, 0x61a4, 0x2009, 0x0000, 0x0078, 0x61a4, 0xa1e0,
+	0x293f, 0x2c0c, 0xa18c, 0x00ff, 0x2061, 0x0100, 0x619a, 0x1078,
+	0x679b, 0x7300, 0xc3dd, 0x7302, 0x6807, 0x0002, 0x2f18, 0x6b26,
+	0x682b, 0x0000, 0x781f, 0x0003, 0x7803, 0x0001, 0x7807, 0x0040,
+	0x0f7f, 0x0e7f, 0x0c7f, 0x0d7f, 0x007c, 0x037f, 0x0e7f, 0x0c7f,
+	0x0078, 0x61bb, 0x0d7f, 0x007c, 0x0c7e, 0x680c, 0xa065, 0x0040,
+	0x61d0, 0x6807, 0x0004, 0x6826, 0x682b, 0x0000, 0x1078, 0x620a,
+	0x0c7f, 0x0d7f, 0x007c, 0x0f7e, 0x0d7e, 0x2069, 0xa5ab, 0x6830,
+	0xa086, 0x0000, 0x00c0, 0x61f1, 0x6838, 0xa07d, 0x0040, 0x61f1,
+	0x6833, 0x0001, 0x683e, 0x6847, 0x0000, 0x127e, 0x0f7e, 0x2091,
+	0x2200, 0x027f, 0x1078, 0x1d28, 0x00c0, 0x61f4, 0x127f, 0x1078,
+	0x6ae5, 0x0d7f, 0x0f7f, 0x007c, 0x127f, 0x6843, 0x0000, 0x7803,
+	0x0002, 0x780c, 0xa015, 0x0040, 0x6206, 0x6a3a, 0x780f, 0x0000,
+	0x6833, 0x0000, 0x683f, 0x0000, 0x0078, 0x61f1, 0x683a, 0x6836,
+	0x0078, 0x6200, 0x601c, 0xa084, 0x000f, 0x1079, 0x6210, 0x007c,
+	0x6219, 0x621e, 0x663f, 0x6758, 0x621e, 0x663f, 0x6758, 0x6219,
+	0x621e, 0x1078, 0x6010, 0x1078, 0x6109, 0x007c, 0x157e, 0x137e,
+	0x147e, 0x0c7e, 0x0f7e, 0x6004, 0xa08a, 0x0044, 0x10c8, 0x1328,
+	0x6118, 0x2178, 0x79a0, 0xd1bc, 0x0040, 0x623b, 0x7900, 0xd1f4,
+	0x0040, 0x6237, 0x7914, 0xa18c, 0x00ff, 0x0078, 0x6240, 0x2009,
+	0x0000, 0x0078, 0x6240, 0xa1f8, 0x293f, 0x2f0c, 0xa18c, 0x00ff,
+	0x2c78, 0x2061, 0x0100, 0x619a, 0xa08a, 0x0040, 0x00c8, 0x6292,
+	0x1079, 0x6250, 0x0f7f, 0x0c7f, 0x147f, 0x137f, 0x157f, 0x007c,
+	0x62f8, 0x6340, 0x6368, 0x6403, 0x6433, 0x643b, 0x6462, 0x6473,
+	0x6484, 0x648c, 0x64a4, 0x648c, 0x650f, 0x6473, 0x6530, 0x6538,
+	0x6484, 0x6538, 0x6549, 0x6290, 0x6290, 0x6290, 0x6290, 0x6290,
+	0x6290, 0x6290, 0x6290, 0x6290, 0x6290, 0x6290, 0x6d05, 0x6d2a,
+	0x6d3f, 0x6d62, 0x6d83, 0x6462, 0x6290, 0x6462, 0x648c, 0x6290,
+	0x6368, 0x6403, 0x6290, 0x72ac, 0x648c, 0x6290, 0x72cc, 0x648c,
+	0x6290, 0x6290, 0x62f3, 0x62a1, 0x6290, 0x72f1, 0x7368, 0x7450,
+	0x6290, 0x7461, 0x645c, 0x747d, 0x6290, 0x6d98, 0x6290, 0x6290,
+	0x1078, 0x1328, 0x2100, 0x1079, 0x629b, 0x0f7f, 0x0c7f, 0x147f,
+	0x137f, 0x157f, 0x007c, 0x629f, 0x629f, 0x629f, 0x62d5, 0x1078,
+	0x1328, 0x0d7e, 0x20a1, 0x020b, 0x1078, 0x6567, 0x7810, 0x2068,
+	0x20a3, 0x2414, 0x20a3, 0x0018, 0x20a3, 0x0800, 0x683c, 0x20a2,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x6850, 0x20a2, 0x6854, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x60c3, 0x0018, 0x1078, 0x6c2d, 0x0d7f, 0x007c, 0x0d7e, 0x7818,
+	0x2068, 0x68a0, 0xa082, 0x007e, 0x0048, 0x62d2, 0xa085, 0x0001,
+	0x0d7f, 0x007c, 0xa006, 0x0078, 0x62d0, 0x0d7e, 0x20a1, 0x020b,
+	0x1078, 0x6567, 0x20a3, 0x0500, 0x20a3, 0x0000, 0x7810, 0xa0e8,
+	0x000f, 0x6808, 0x20a2, 0x680c, 0x20a2, 0x6810, 0x20a2, 0x6814,
+	0x20a2, 0x6818, 0x20a2, 0x681c, 0x20a2, 0x60c3, 0x0010, 0x1078,
+	0x6c2d, 0x0d7f, 0x007c, 0x6030, 0x609a, 0x1078, 0x6c2d, 0x007c,
+	0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3, 0x5200, 0x20a3, 0x0000,
+	0x0d7e, 0x2069, 0xa351, 0x6804, 0xd084, 0x0040, 0x6312, 0x6828,
+	0x20a3, 0x0000, 0x017e, 0x1078, 0x24fa, 0x21a2, 0x017f, 0x0d7f,
+	0x0078, 0x6317, 0x0d7f, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a9,
+	0x0004, 0x2099, 0xa305, 0x53a6, 0x20a9, 0x0004, 0x2099, 0xa301,
+	0x53a6, 0x7818, 0xa080, 0x0028, 0x2004, 0xa082, 0x007f, 0x0048,
+	0x6331, 0x2001, 0xa31a, 0x20a6, 0x2001, 0xa31b, 0x20a6, 0x0078,
+	0x6337, 0x20a3, 0x0000, 0x6030, 0xa084, 0x00ff, 0x20a2, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x001c, 0x1078, 0x6c2d, 0x007c,
+	0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3, 0x0500, 0x20a3, 0x0000,
+	0x7818, 0xa080, 0x0028, 0x2004, 0xa082, 0x007f, 0x0048, 0x6358,
+	0x2001, 0xa31a, 0x20a6, 0x2001, 0xa31b, 0x20a6, 0x0078, 0x635e,
+	0x20a3, 0x0000, 0x6030, 0xa084, 0x00ff, 0x20a2, 0x20a9, 0x0004,
+	0x2099, 0xa305, 0x53a6, 0x60c3, 0x0010, 0x1078, 0x6c2d, 0x007c,
+	0x20a1, 0x020b, 0x1078, 0x6567, 0x0c7e, 0x7818, 0x2060, 0x2001,
+	0x0000, 0x1078, 0x48a2, 0x0c7f, 0x7818, 0xa080, 0x0028, 0x2004,
+	0xa086, 0x007e, 0x00c0, 0x6383, 0x20a3, 0x0400, 0x620c, 0xc2b4,
+	0x620e, 0x0078, 0x6385, 0x20a3, 0x0300, 0x20a3, 0x0000, 0x7818,
+	0xa080, 0x0028, 0x2004, 0xa086, 0x007e, 0x00c0, 0x63d2, 0x2099,
+	0xa58c, 0x33a6, 0x9398, 0x33a6, 0x9398, 0x3304, 0xa084, 0x3fff,
+	0x20a2, 0x9398, 0x33a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x20a9, 0x0004, 0x2099, 0xa305, 0x53a6,
+	0x20a9, 0x0004, 0x2099, 0xa301, 0x53a6, 0x20a9, 0x0010, 0x20a3,
+	0x0000, 0x00f0, 0x63af, 0x2099, 0xa594, 0x3304, 0xc0dd, 0x20a2,
+	0x2001, 0xa371, 0x2004, 0xd0e4, 0x0040, 0x63ca, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x9398, 0x9398, 0x9398, 0x33a6, 0x20a9, 0x0004,
+	0x0078, 0x63cc, 0x20a9, 0x0007, 0x20a3, 0x0000, 0x00f0, 0x63cc,
+	0x0078, 0x63f2, 0x2099, 0xa58c, 0x20a9, 0x0008, 0x53a6, 0x20a9,
+	0x0004, 0x2099, 0xa305, 0x53a6, 0x20a9, 0x0004, 0x2099, 0xa301,
+	0x53a6, 0x20a9, 0x0008, 0x20a3, 0x0000, 0x00f0, 0x63e3, 0x20a9,
+	0x0008, 0x20a3, 0x0000, 0x00f0, 0x63e9, 0x2099, 0xa594, 0x20a9,
+	0x0008, 0x53a6, 0x20a9, 0x0008, 0x20a3, 0x0000, 0x00f0, 0x63f4,
+	0x20a9, 0x000a, 0x20a3, 0x0000, 0x00f0, 0x63fa, 0x60c3, 0x0074,
+	0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3,
+	0x2010, 0x20a3, 0x0014, 0x20a3, 0x0800, 0x20a3, 0x2000, 0xa006,
+	0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x0f7e, 0x2079, 0xa351,
+	0x7904, 0x0f7f, 0xd1ac, 0x00c0, 0x641f, 0xa085, 0x0020, 0xd1a4,
+	0x0040, 0x6424, 0xa085, 0x0010, 0xa085, 0x0002, 0x0d7e, 0x0078,
+	0x64ed, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014,
+	0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3,
+	0x5000, 0x0078, 0x6385, 0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3,
+	0x2110, 0x20a3, 0x0014, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3,
+	0x0014, 0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078, 0x65ef,
+	0x0078, 0x6466, 0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3, 0x0200,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0004,
+	0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3,
+	0x0100, 0x20a3, 0x0000, 0x20a3, 0x0003, 0x20a3, 0x2a00, 0x60c3,
+	0x0008, 0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078, 0x65f8,
+	0x20a3, 0x0200, 0x0078, 0x6385, 0x20a1, 0x020b, 0x1078, 0x65f8,
+	0x20a3, 0x0100, 0x20a3, 0x0000, 0x7828, 0xa005, 0x0040, 0x649b,
+	0x20a2, 0x0078, 0x649d, 0x20a3, 0x0003, 0x7810, 0x20a2, 0x60c3,
+	0x0008, 0x1078, 0x6c2d, 0x007c, 0x0d7e, 0x20a1, 0x020b, 0x1078,
+	0x65f8, 0x20a3, 0x0210, 0x20a3, 0x0014, 0x20a3, 0x0800, 0x7818,
+	0x2068, 0x6894, 0xa086, 0x0014, 0x00c0, 0x64ca, 0x6998, 0xa184,
+	0xc000, 0x00c0, 0x64c6, 0xd1ec, 0x0040, 0x64c2, 0x20a3, 0x2100,
+	0x0078, 0x64cc, 0x20a3, 0x0100, 0x0078, 0x64cc, 0x20a3, 0x0400,
+	0x0078, 0x64cc, 0x20a3, 0x0700, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a2, 0x0f7e, 0x2079, 0xa351, 0x7904, 0x0f7f, 0xd1ac,
+	0x00c0, 0x64dc, 0xa085, 0x0020, 0xd1a4, 0x0040, 0x64e1, 0xa085,
+	0x0010, 0x2009, 0xa373, 0x210c, 0xd184, 0x0040, 0x64eb, 0x699c,
+	0xd18c, 0x0040, 0x64ed, 0xa085, 0x0002, 0x027e, 0x2009, 0xa371,
+	0x210c, 0xd1e4, 0x0040, 0x64fb, 0xc0c5, 0xa094, 0x0030, 0xa296,
+	0x0010, 0x0040, 0x6505, 0xd1ec, 0x0040, 0x6505, 0xa094, 0x0030,
+	0xa296, 0x0010, 0x0040, 0x6505, 0xc0bd, 0x027f, 0x20a2, 0x20a2,
+	0x20a2, 0x60c3, 0x0014, 0x1078, 0x6c2d, 0x0d7f, 0x007c, 0x20a1,
+	0x020b, 0x1078, 0x65f8, 0x20a3, 0x0210, 0x20a3, 0x0014, 0x20a3,
+	0x0000, 0x20a3, 0x0100, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x1078, 0x6c2d, 0x007c,
+	0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3, 0x0200, 0x0078, 0x62fe,
+	0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3, 0x0100, 0x20a3, 0x0000,
+	0x20a3, 0x0003, 0x20a3, 0x2a00, 0x60c3, 0x0008, 0x1078, 0x6c2d,
+	0x007c, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x20a1, 0x020b, 0x1078,
+	0x65f8, 0x20a3, 0x0100, 0x20a3, 0x0000, 0x20a3, 0x000b, 0x20a3,
+	0x0000, 0x60c3, 0x0008, 0x1078, 0x6c2d, 0x007c, 0x027e, 0x037e,
+	0x047e, 0x2019, 0x3200, 0x2021, 0x0800, 0x0078, 0x656e, 0x027e,
+	0x037e, 0x047e, 0x2019, 0x2200, 0x2021, 0x0100, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2014, 0xa286, 0x007e,
+	0x00c0, 0x6581, 0xa385, 0x00ff, 0x20a2, 0x20a3, 0xfffe, 0x0078,
+	0x65b6, 0xa286, 0x007f, 0x00c0, 0x658d, 0x0d7e, 0xa385, 0x00ff,
+	0x20a2, 0x20a3, 0xfffd, 0x0078, 0x65a4, 0xd2bc, 0x0040, 0x65ac,
+	0xa286, 0x0080, 0x0d7e, 0x00c0, 0x659c, 0xa385, 0x00ff, 0x20a2,
+	0x20a3, 0xfffc, 0x0078, 0x65a4, 0xa2e8, 0xa434, 0x2d6c, 0x6810,
+	0xa305, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68,
+	0x2da6, 0x0d7f, 0x0078, 0x65ba, 0x0d7e, 0xa2e8, 0xa434, 0x2d6c,
+	0x6810, 0xa305, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000,
+	0x6230, 0x22a2, 0xa485, 0x0029, 0x20a2, 0x047f, 0x037f, 0x20a3,
+	0x0000, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000, 0x2fa2, 0x20a3,
+	0xffff, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x027f, 0x007c, 0x027e,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x20a3, 0x02ff, 0x2011, 0xfffc,
+	0x22a2, 0x0d7e, 0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6, 0x0d7f,
+	0x20a3, 0x2029, 0x20a3, 0x0000, 0x0078, 0x65c1, 0x20a3, 0x0100,
+	0x20a3, 0x0000, 0x20a3, 0xfc02, 0x20a3, 0x0000, 0x007c, 0x027e,
+	0x037e, 0x047e, 0x2019, 0x3300, 0x2021, 0x0800, 0x0078, 0x65ff,
+	0x027e, 0x037e, 0x047e, 0x2019, 0x2300, 0x2021, 0x0100, 0x20e1,
+	0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0xa092,
+	0x007e, 0x0048, 0x661c, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810,
+	0xa305, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68,
+	0x2da6, 0x0d7f, 0x0078, 0x662a, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c,
+	0x6810, 0xa305, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000,
+	0x6230, 0x22a2, 0xa485, 0x0098, 0x20a2, 0x20a3, 0x0000, 0x047f,
+	0x037f, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000, 0x7a08, 0x22a2,
+	0x2fa2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x027f, 0x007c, 0x0c7e,
+	0x0f7e, 0x6004, 0xa08a, 0x0085, 0x1048, 0x1328, 0xa08a, 0x008c,
+	0x10c8, 0x1328, 0x6118, 0x2178, 0x79a0, 0xd1bc, 0x0040, 0x665d,
+	0x7900, 0xd1f4, 0x0040, 0x6659, 0x7914, 0xa18c, 0x00ff, 0x0078,
+	0x6662, 0x2009, 0x0000, 0x0078, 0x6662, 0xa1f8, 0x293f, 0x2f0c,
+	0xa18c, 0x00ff, 0x2c78, 0x2061, 0x0100, 0x619a, 0xa082, 0x0085,
+	0x1079, 0x666d, 0x0f7f, 0x0c7f, 0x007c, 0x6676, 0x6681, 0x669c,
+	0x6674, 0x6674, 0x6674, 0x6676, 0x1078, 0x1328, 0x147e, 0x20a1,
+	0x020b, 0x1078, 0x66af, 0x60c3, 0x0000, 0x1078, 0x6c2d, 0x147f,
+	0x007c, 0x147e, 0x20a1, 0x020b, 0x1078, 0x66e3, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x7808, 0x20a2, 0x7810, 0x20a2, 0x20a3, 0x0000,
+	0x20a3, 0xffff, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x000c,
+	0x1078, 0x6c2d, 0x147f, 0x007c, 0x147e, 0x20a1, 0x020b, 0x1078,
+	0x6724, 0x20a3, 0x0003, 0x20a3, 0x0300, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x60c3, 0x0004, 0x1078, 0x6c2d, 0x147f, 0x007c, 0x027e,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004,
+	0xa092, 0x007e, 0x0048, 0x66ce, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c,
+	0x6810, 0xa085, 0x8100, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a,
+	0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x66dd, 0x0d7e, 0xa0e8,
+	0xa434, 0x2d6c, 0x6810, 0xa085, 0x8100, 0x20a2, 0x6814, 0x20a2,
+	0x0d7f, 0x20a3, 0x0000, 0x6230, 0x22a2, 0x20a3, 0x0009, 0x20a3,
+	0x0000, 0x0078, 0x65c1, 0x027e, 0x20e1, 0x9080, 0x20e1, 0x4000,
+	0x7818, 0xa080, 0x0028, 0x2004, 0xa092, 0x007e, 0x0048, 0x6702,
+	0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x8400, 0x20a2,
+	0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6, 0x0d7f,
+	0x0078, 0x6711, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085,
+	0x8400, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000, 0x6230,
+	0x22a2, 0x20a3, 0x0099, 0x20a3, 0x0000, 0x1078, 0x6c1c, 0x22a2,
+	0x20a3, 0x0000, 0x7a08, 0x22a2, 0x7a10, 0x22a2, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x027f, 0x007c, 0x027e, 0x20e1, 0x9080, 0x20e1,
+	0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0xa092, 0x007e, 0x0048,
+	0x6743, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x8500,
+	0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6,
+	0x0d7f, 0x0078, 0x6752, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810,
+	0xa085, 0x8500, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000,
+	0x6230, 0x22a2, 0x20a3, 0x0099, 0x20a3, 0x0000, 0x0078, 0x6715,
+	0x0c7e, 0x0f7e, 0x2c78, 0x7804, 0xa08a, 0x0040, 0x1048, 0x1328,
+	0xa08a, 0x0053, 0x10c8, 0x1328, 0x7918, 0x2160, 0x61a0, 0xd1bc,
+	0x0040, 0x6777, 0x6100, 0xd1f4, 0x0040, 0x6773, 0x6114, 0xa18c,
+	0x00ff, 0x0078, 0x677c, 0x2009, 0x0000, 0x0078, 0x677c, 0xa1e0,
+	0x293f, 0x2c0c, 0xa18c, 0x00ff, 0x2061, 0x0100, 0x619a, 0xa082,
+	0x0040, 0x1079, 0x6786, 0x0f7f, 0x0c7f, 0x007c, 0x679b, 0x68a9,
+	0x684a, 0x6a59, 0x6799, 0x6799, 0x6799, 0x6799, 0x6799, 0x6799,
+	0x6799, 0x6f5e, 0x6f6f, 0x6f80, 0x6f91, 0x6799, 0x748e, 0x6799,
+	0x6f4d, 0x1078, 0x1328, 0x0d7e, 0x157e, 0x147e, 0x780b, 0xffff,
+	0x20a1, 0x020b, 0x1078, 0x6806, 0x7910, 0x2168, 0x6948, 0x7922,
+	0x21a2, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x694c, 0xa184, 0x000f,
+	0x00c0, 0x67b6, 0x2001, 0x0005, 0x0078, 0x67c0, 0xd184, 0x0040,
+	0x67bd, 0x2001, 0x0004, 0x0078, 0x67c0, 0xa084, 0x0006, 0x8004,
+	0x017e, 0x2008, 0x7830, 0xa084, 0x00ff, 0x8007, 0xa105, 0x017f,
+	0x20a2, 0xd1ac, 0x0040, 0x67d0, 0x20a3, 0x0002, 0x0078, 0x67dc,
+	0xd1b4, 0x0040, 0x67d7, 0x20a3, 0x0001, 0x0078, 0x67dc, 0x20a3,
+	0x0000, 0x2230, 0x0078, 0x67de, 0x6a80, 0x6e7c, 0x20a9, 0x0008,
+	0xad80, 0x0017, 0x200c, 0x810f, 0x21a2, 0x8000, 0x00f0, 0x67e2,
+	0x22a2, 0x26a2, 0x60c3, 0x0020, 0x20e1, 0x9080, 0x6014, 0xa084,
+	0x0004, 0xa085, 0x0009, 0x6016, 0x2001, 0xa5c7, 0x2003, 0x07d0,
+	0x2001, 0xa5c6, 0x2003, 0x0009, 0x2001, 0xa5cc, 0x2003, 0x0002,
+	0x1078, 0x157e, 0x147f, 0x157f, 0x0d7f, 0x007c, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7a18, 0xa280, 0x0023, 0x2014, 0x8210, 0xa294,
+	0x00ff, 0x2202, 0x8217, 0x7818, 0xa080, 0x0028, 0x2004, 0xd0bc,
+	0x0040, 0x682c, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085,
+	0x0600, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68,
+	0x2da6, 0x0d7f, 0x0078, 0x683b, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c,
+	0x6810, 0xa085, 0x0600, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3,
+	0x0000, 0x6130, 0x21a2, 0x20a3, 0x0829, 0x20a3, 0x0000, 0x22a2,
+	0x20a3, 0x0000, 0x2fa2, 0x20a3, 0xffff, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x007c, 0x0d7e, 0x157e, 0x137e, 0x147e, 0x20a1, 0x020b,
+	0x1078, 0x686a, 0x7810, 0x2068, 0x6860, 0x20a2, 0x685c, 0x20a2,
+	0x6880, 0x20a2, 0x687c, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x60c3, 0x000c, 0x1078, 0x6c2d, 0x147f, 0x137f, 0x157f,
+	0x0d7f, 0x007c, 0x027e, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818,
+	0xa080, 0x0028, 0x2004, 0xd0bc, 0x0040, 0x6888, 0x0d7e, 0xa0e8,
+	0xa434, 0x2d6c, 0x6810, 0xa085, 0x0500, 0x20a2, 0x6814, 0x20a2,
+	0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x6897,
+	0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x0500, 0x20a2,
+	0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000, 0x6230, 0x22a2, 0x20a3,
+	0x0889, 0x20a3, 0x0000, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000,
+	0x7a08, 0x22a2, 0x2fa2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x027f,
+	0x007c, 0x0d7e, 0x157e, 0x137e, 0x147e, 0x7810, 0xa06d, 0x1078,
+	0x488f, 0x0040, 0x68bd, 0x684c, 0xa084, 0x2020, 0xa086, 0x2020,
+	0x00c0, 0x68bd, 0x7824, 0xc0cd, 0x7826, 0x20a1, 0x020b, 0x1078,
+	0x6a12, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x7810,
+	0xa084, 0xf000, 0x00c0, 0x68d4, 0x7810, 0xa084, 0x0700, 0x8007,
+	0x1079, 0x68dc, 0x0078, 0x68d7, 0xa006, 0x1079, 0x68dc, 0x147f,
+	0x137f, 0x157f, 0x0d7f, 0x007c, 0x68e6, 0x697e, 0x6989, 0x69b3,
+	0x69c7, 0x69e3, 0x69ee, 0x68e4, 0x1078, 0x1328, 0x017e, 0x037e,
+	0x694c, 0xa18c, 0x0003, 0x0040, 0x68f1, 0xa186, 0x0003, 0x00c0,
+	0x6900, 0x6b78, 0x7824, 0xd0cc, 0x0040, 0x68f7, 0xc3e5, 0x23a2,
+	0x6868, 0x20a2, 0x6864, 0x20a2, 0x037f, 0x017f, 0x0078, 0x69be,
+	0xa186, 0x0001, 0x10c0, 0x1328, 0x6b78, 0x7824, 0xd0cc, 0x0040,
+	0x690a, 0xc3e5, 0x23a2, 0x6868, 0x20a2, 0x6864, 0x20a2, 0x22a2,
+	0x6874, 0x20a2, 0x22a2, 0x687c, 0x20a2, 0x2009, 0x0018, 0xa384,
+	0x0300, 0x0040, 0x6978, 0xd3c4, 0x0040, 0x6920, 0x687c, 0xa108,
+	0xd3cc, 0x0040, 0x6925, 0x6874, 0xa108, 0x157e, 0x20a9, 0x000d,
+	0xad80, 0x0020, 0x201c, 0x831f, 0x23a2, 0x8000, 0x00f0, 0x692a,
+	0x157f, 0x22a2, 0x22a2, 0x22a2, 0xa184, 0x0003, 0x0040, 0x6978,
+	0x20a1, 0x020b, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x007e, 0x7818,
+	0xa080, 0x0028, 0x2004, 0xd0bc, 0x0040, 0x6958, 0x0d7e, 0xa0e8,
+	0xa434, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2, 0x6814, 0x20a2,
+	0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x6967,
+	0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2,
+	0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000, 0x6230, 0x22a2, 0x007f,
+	0x7b24, 0xd3cc, 0x0040, 0x6970, 0x20a3, 0x0889, 0x0078, 0x6972,
+	0x20a3, 0x0898, 0x20a2, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000,
+	0x61c2, 0x037f, 0x017f, 0x1078, 0x6c2d, 0x007c, 0x2011, 0x0008,
+	0x7824, 0xd0cc, 0x0040, 0x6985, 0xc2e5, 0x22a2, 0xa016, 0x0078,
+	0x69bc, 0x2011, 0x0302, 0x7824, 0xd0cc, 0x0040, 0x6990, 0xc2e5,
+	0x22a2, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x20a3, 0x0012, 0x22a2,
+	0x20a3, 0x0008, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x20a3, 0x7000,
+	0x20a3, 0x0500, 0x22a2, 0x20a3, 0x000a, 0x22a2, 0x22a2, 0x20a3,
+	0x2500, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x60c3, 0x0032,
+	0x1078, 0x6c2d, 0x007c, 0x2011, 0x0028, 0x7824, 0xd0cc, 0x0040,
+	0x69ba, 0xc2e5, 0x22a2, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x22a2,
+	0x22a2, 0x22a2, 0x60c3, 0x0018, 0x1078, 0x6c2d, 0x007c, 0x2011,
+	0x0100, 0x7824, 0xd0cc, 0x0040, 0x69ce, 0xc2e5, 0x22a2, 0xa016,
+	0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x20a3, 0x0008, 0x22a2,
+	0x7834, 0xa084, 0x00ff, 0x20a2, 0x22a2, 0x22a2, 0x60c3, 0x0020,
+	0x1078, 0x6c2d, 0x007c, 0x2011, 0x0008, 0x7824, 0xd0cc, 0x0040,
+	0x69ea, 0xc2e5, 0x22a2, 0xa016, 0x0078, 0x69bc, 0x037e, 0x7b10,
+	0xa384, 0xff00, 0x7812, 0xa384, 0x00ff, 0x8001, 0x00c0, 0x6a01,
+	0x7824, 0xd0cc, 0x0040, 0x69fd, 0xc2e5, 0x22a2, 0x037f, 0x0078,
+	0x69bc, 0x047e, 0x2021, 0x0800, 0x007e, 0x7824, 0xd0cc, 0x007f,
+	0x0040, 0x6a0b, 0xc4e5, 0x24a2, 0x047f, 0x22a2, 0x20a2, 0x037f,
+	0x0078, 0x69be, 0x027e, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818,
+	0xa080, 0x0028, 0x2004, 0xd0bc, 0x0040, 0x6a30, 0x0d7e, 0xa0e8,
+	0xa434, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2, 0x6814, 0x20a2,
+	0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x6a3f,
+	0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2,
+	0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000, 0x6230, 0x22a2, 0x7824,
+	0xd0cc, 0x0040, 0x6a47, 0x20a3, 0x0889, 0x0078, 0x6a49, 0x20a3,
+	0x0898, 0x20a3, 0x0000, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000,
+	0x7a08, 0x22a2, 0x2fa2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x027f,
+	0x007c, 0x0d7e, 0x157e, 0x137e, 0x147e, 0x017e, 0x037e, 0x7810,
+	0xa084, 0x0700, 0x8007, 0x1079, 0x6a6c, 0x037f, 0x017f, 0x147f,
+	0x137f, 0x157f, 0x0d7f, 0x007c, 0x6a74, 0x6a74, 0x6a76, 0x6a74,
+	0x6a74, 0x6a74, 0x6a9b, 0x6a74, 0x1078, 0x1328, 0x7910, 0xa18c,
+	0xf8ff, 0xa18d, 0x0600, 0x7912, 0x20a1, 0x020b, 0x2009, 0x0003,
+	0x1078, 0x6aa5, 0x0d7e, 0x2069, 0xa351, 0x6804, 0xd0bc, 0x0040,
+	0x6a90, 0x682c, 0xa084, 0x00ff, 0x8007, 0x20a2, 0x0078, 0x6a92,
+	0x20a3, 0x3f00, 0x0d7f, 0x22a2, 0x22a2, 0x22a2, 0x60c3, 0x0001,
+	0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x2009, 0x0003, 0x1078,
+	0x6aa5, 0x20a3, 0x7f00, 0x0078, 0x6a93, 0x027e, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0xd0bc, 0x0040,
+	0x6ac3, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810, 0xa085, 0x0100,
+	0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a, 0x2da6, 0x8d68, 0x2da6,
+	0x0d7f, 0x0078, 0x6ad2, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c, 0x6810,
+	0xa085, 0x0100, 0x20a2, 0x6814, 0x20a2, 0x0d7f, 0x20a3, 0x0000,
+	0x6230, 0x22a2, 0x20a3, 0x0888, 0xa18d, 0x0008, 0x21a2, 0x1078,
+	0x6c1c, 0x22a2, 0x20a3, 0x0000, 0x7a08, 0x22a2, 0x2fa2, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x027f, 0x007c, 0x0e7e, 0x0d7e, 0x0c7e,
+	0x057e, 0x047e, 0x037e, 0x2061, 0x0100, 0x2071, 0xa300, 0x6130,
+	0x7818, 0x2068, 0x68a0, 0x2028, 0xd0bc, 0x00c0, 0x6afc, 0x6910,
+	0x6a14, 0x6430, 0x0078, 0x6b00, 0x6910, 0x6a14, 0x7368, 0x746c,
+	0x781c, 0xa086, 0x0006, 0x0040, 0x6b5f, 0xd5bc, 0x0040, 0x6b10,
+	0xa185, 0x0100, 0x6062, 0x6266, 0x636a, 0x646e, 0x0078, 0x6b17,
+	0xa185, 0x0100, 0x6062, 0x6266, 0x606b, 0x0000, 0x646e, 0x6073,
+	0x0809, 0x6077, 0x0008, 0x688c, 0x8000, 0xa084, 0x00ff, 0x688e,
+	0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6082, 0x7808, 0x6086,
+	0x7810, 0x2070, 0x7014, 0x608a, 0x7010, 0x608e, 0x700c, 0x60c6,
+	0x7008, 0x60ca, 0x686c, 0x60ce, 0x60ab, 0x0036, 0x60af, 0x95d5,
+	0x60d7, 0x0000, 0xa582, 0x0080, 0x0048, 0x6b49, 0x6a00, 0xd2f4,
+	0x0040, 0x6b47, 0x6a14, 0xa294, 0x00ff, 0x0078, 0x6b49, 0x2011,
+	0x0000, 0x629e, 0x6017, 0x0016, 0x2009, 0x07d0, 0x60c4, 0xa084,
+	0xfff0, 0xa005, 0x0040, 0x6b56, 0x2009, 0x1b58, 0x1078, 0x595f,
+	0x037f, 0x047f, 0x057f, 0x0c7f, 0x0d7f, 0x0e7f, 0x007c, 0x7810,
+	0x2070, 0x704c, 0xa084, 0x0003, 0xa086, 0x0002, 0x0040, 0x6bb7,
+	0xd5bc, 0x0040, 0x6b73, 0xa185, 0x0100, 0x6062, 0x6266, 0x636a,
+	0x646e, 0x0078, 0x6b7a, 0xa185, 0x0100, 0x6062, 0x6266, 0x606b,
+	0x0000, 0x646e, 0x6073, 0x0880, 0x6077, 0x0008, 0x688c, 0x8000,
+	0xa084, 0x00ff, 0x688e, 0x8007, 0x607a, 0x607f, 0x0000, 0x2f00,
+	0x6086, 0x7808, 0x6082, 0x7060, 0x608a, 0x705c, 0x608e, 0x7080,
+	0x60c6, 0x707c, 0x60ca, 0x707c, 0x792c, 0xa108, 0x792e, 0x7080,
+	0x7928, 0xa109, 0x792a, 0x686c, 0x60ce, 0x60ab, 0x0036, 0x60af,
+	0x95d5, 0x60d7, 0x0000, 0xa582, 0x0080, 0x0048, 0x6bb2, 0x6a00,
+	0xd2f4, 0x0040, 0x6bb0, 0x6a14, 0xa294, 0x00ff, 0x0078, 0x6bb2,
+	0x2011, 0x0000, 0x629e, 0x6017, 0x0012, 0x0078, 0x6b4c, 0xd5bc,
+	0x0040, 0x6bc2, 0xa185, 0x0700, 0x6062, 0x6266, 0x636a, 0x646e,
+	0x0078, 0x6bc9, 0xa185, 0x0700, 0x6062, 0x6266, 0x606b, 0x0000,
+	0x646e, 0x1078, 0x488f, 0x0040, 0x6bdf, 0x0d7e, 0x7810, 0xa06d,
+	0x684c, 0x0d7f, 0xa084, 0x2020, 0xa086, 0x2020, 0x00c0, 0x6bdf,
+	0x7824, 0xc0cd, 0x7826, 0x6073, 0x0889, 0x0078, 0x6be1, 0x6073,
+	0x0898, 0x6077, 0x0000, 0x688c, 0x8000, 0xa084, 0x00ff, 0x688e,
+	0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6086, 0x7808, 0x6082,
+	0x7014, 0x608a, 0x7010, 0x608e, 0x700c, 0x60c6, 0x7008, 0x60ca,
+	0x686c, 0x60ce, 0x60ab, 0x0036, 0x60af, 0x95d5, 0x60d7, 0x0000,
+	0xa582, 0x0080, 0x0048, 0x6c0f, 0x6a00, 0xd2f4, 0x0040, 0x6c0d,
+	0x6a14, 0xa294, 0x00ff, 0x0078, 0x6c0f, 0x2011, 0x0000, 0x629e,
+	0x7824, 0xd0cc, 0x0040, 0x6c18, 0x6017, 0x0016, 0x0078, 0x6b4c,
+	0x6017, 0x0012, 0x0078, 0x6b4c, 0x7a18, 0xa280, 0x0023, 0x2014,
+	0x8210, 0xa294, 0x00ff, 0x2202, 0x8217, 0x007c, 0x0d7e, 0x2069,
+	0xa5ab, 0x6843, 0x0001, 0x0d7f, 0x007c, 0x20e1, 0x9080, 0x60a3,
+	0x0056, 0x60a7, 0x9575, 0x1078, 0x6c38, 0x1078, 0x594f, 0x007c,
+	0x007e, 0x6014, 0xa084, 0x0004, 0xa085, 0x0009, 0x6016, 0x007f,
+	0x007c, 0x007e, 0x0c7e, 0x2061, 0x0100, 0x6014, 0xa084, 0x0004,
+	0xa085, 0x0008, 0x6016, 0x0c7f, 0x007f, 0x007c, 0x0c7e, 0x0d7e,
+	0x017e, 0x027e, 0x2061, 0x0100, 0x2069, 0x0140, 0x6904, 0xa194,
+	0x4000, 0x0040, 0x6c89, 0x1078, 0x6c41, 0x6803, 0x1000, 0x6803,
+	0x0000, 0x0c7e, 0x2061, 0xa5ab, 0x6128, 0xa192, 0x00c8, 0x00c8,
+	0x6c76, 0x8108, 0x612a, 0x6124, 0x0c7f, 0x81ff, 0x0040, 0x6c84,
+	0x1078, 0x594f, 0x1078, 0x6c38, 0x0078, 0x6c84, 0x6124, 0xa1e5,
+	0x0000, 0x0040, 0x6c81, 0x1078, 0xa241, 0x2009, 0x0014, 0x1078,
+	0x756c, 0x0c7f, 0x0078, 0x6c84, 0x027f, 0x017f, 0x0d7f, 0x0c7f,
+	0x007c, 0x2001, 0xa5c7, 0x2004, 0xa005, 0x00c0, 0x6c84, 0x0c7e,
+	0x2061, 0xa5ab, 0x6128, 0xa192, 0x0003, 0x00c8, 0x6c76, 0x8108,
+	0x612a, 0x0c7f, 0x1078, 0x594f, 0x1078, 0x4171, 0x0078, 0x6c84,
+	0x0c7e, 0x0d7e, 0x0e7e, 0x017e, 0x027e, 0x1078, 0x5967, 0x2071,
+	0xa5ab, 0x713c, 0x81ff, 0x0040, 0x6cca, 0x2061, 0x0100, 0x2069,
+	0x0140, 0x6904, 0xa194, 0x4000, 0x0040, 0x6cd0, 0x6803, 0x1000,
+	0x6803, 0x0000, 0x037e, 0x2019, 0x0001, 0x1078, 0x6e6c, 0x037f,
+	0x713c, 0x2160, 0x1078, 0xa241, 0x2009, 0x004a, 0x1078, 0x756c,
+	0x0078, 0x6cca, 0x027f, 0x017f, 0x0e7f, 0x0d7f, 0x0c7f, 0x007c,
+	0x0078, 0x6cba, 0x0e7e, 0x0d7e, 0x0c7e, 0x067e, 0x057e, 0x047e,
+	0x007e, 0x127e, 0x2091, 0x8000, 0x6018, 0x2068, 0x6ca0, 0x2071,
+	0xa5ab, 0x7018, 0x2068, 0x8dff, 0x0040, 0x6cfc, 0x68a0, 0xa406,
+	0x0040, 0x6cee, 0x6854, 0x2068, 0x0078, 0x6ce3, 0x6010, 0x2060,
+	0x643c, 0x6540, 0x6e48, 0x2d60, 0x1078, 0x466a, 0x0040, 0x6cfc,
+	0x1078, 0x7045, 0xa085, 0x0001, 0x127f, 0x007f, 0x047f, 0x057f,
+	0x067f, 0x0c7f, 0x0d7f, 0x0e7f, 0x007c, 0x20a1, 0x020b, 0x1078,
+	0x6567, 0x20a3, 0x1200, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x781c,
+	0xa086, 0x0004, 0x00c0, 0x6d17, 0x6098, 0x0078, 0x6d18, 0x6030,
+	0x20a2, 0x7834, 0x20a2, 0x7838, 0x20a2, 0x20a9, 0x0010, 0xa006,
+	0x20a2, 0x00f0, 0x6d20, 0x20a2, 0x20a2, 0x60c3, 0x002c, 0x1078,
+	0x6c2d, 0x007c, 0x157e, 0x147e, 0x20a1, 0x020b, 0x1078, 0x6567,
+	0x20a3, 0x0f00, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x7808, 0x20a2,
+	0x60c3, 0x0008, 0x1078, 0x6c2d, 0x147f, 0x157f, 0x007c, 0x157e,
+	0x147e, 0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3, 0x0200, 0x20a3,
+	0x0000, 0x20a9, 0x0006, 0x2011, 0xa340, 0x2019, 0xa341, 0x23a6,
+	0x22a6, 0xa398, 0x0002, 0xa290, 0x0002, 0x00f0, 0x6d4f, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x001c, 0x1078, 0x6c2d, 0x147f,
+	0x157f, 0x007c, 0x157e, 0x147e, 0x017e, 0x027e, 0x20a1, 0x020b,
+	0x1078, 0x65cf, 0x1078, 0x65e6, 0x7810, 0xa080, 0x0000, 0x2004,
+	0xa080, 0x0015, 0x2098, 0x7808, 0xa088, 0x0002, 0x21a8, 0x53a6,
+	0xa080, 0x0004, 0x8003, 0x60c2, 0x1078, 0x6c2d, 0x027f, 0x017f,
+	0x147f, 0x157f, 0x007c, 0x157e, 0x147e, 0x20a1, 0x020b, 0x1078,
+	0x6567, 0x20a3, 0x6200, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x7808,
+	0x20a2, 0x60c3, 0x0008, 0x1078, 0x6c2d, 0x147f, 0x157f, 0x007c,
+	0x157e, 0x147e, 0x017e, 0x027e, 0x20a1, 0x020b, 0x1078, 0x6567,
+	0x7810, 0xa080, 0x0000, 0x2004, 0xa080, 0x0017, 0x2098, 0x7808,
+	0xa088, 0x0002, 0x21a8, 0x53a6, 0x8003, 0x60c2, 0x1078, 0x6c2d,
+	0x027f, 0x017f, 0x147f, 0x157f, 0x007c, 0x0e7e, 0x0c7e, 0x007e,
+	0x127e, 0x2091, 0x8000, 0x2071, 0xa5ab, 0x700c, 0x2060, 0x8cff,
+	0x0040, 0x6dd1, 0x1078, 0x8c3b, 0x00c0, 0x6dc8, 0x1078, 0x7a05,
+	0x600c, 0x007e, 0x1078, 0x753d, 0x1078, 0x7045, 0x0c7f, 0x0078,
+	0x6dbf, 0x700f, 0x0000, 0x700b, 0x0000, 0x127f, 0x007f, 0x0c7f,
+	0x0e7f, 0x007c, 0x127e, 0x157e, 0x0f7e, 0x0e7e, 0x0d7e, 0x0c7e,
+	0x027e, 0x017e, 0x007e, 0x2091, 0x8000, 0x2069, 0x0100, 0x2079,
+	0x0140, 0x2071, 0xa5ab, 0x7024, 0x2060, 0x8cff, 0x0040, 0x6e2a,
+	0x1078, 0x6c41, 0x68c3, 0x0000, 0x1078, 0x595a, 0x2009, 0x0013,
+	0x1078, 0x756c, 0x20a9, 0x01f4, 0x6824, 0xd094, 0x0040, 0x6e0d,
+	0x6827, 0x0004, 0x7804, 0xa084, 0x4000, 0x0040, 0x6e1f, 0x7803,
+	0x1000, 0x7803, 0x0000, 0x0078, 0x6e1f, 0xd084, 0x0040, 0x6e14,
+	0x6827, 0x0001, 0x0078, 0x6e16, 0x00f0, 0x6dfc, 0x7804, 0xa084,
+	0x1000, 0x0040, 0x6e1f, 0x7803, 0x0100, 0x7803, 0x0000, 0x6824,
+	0x007f, 0x017f, 0x027f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f, 0x157f,
+	0x127f, 0x007c, 0x2001, 0xa300, 0x2004, 0xa096, 0x0001, 0x0040,
+	0x6e62, 0xa096, 0x0004, 0x0040, 0x6e62, 0x6817, 0x0008, 0x68c3,
+	0x0000, 0x2011, 0x4129, 0x1078, 0x58d4, 0x20a9, 0x01f4, 0x6824,
+	0xd094, 0x0040, 0x6e50, 0x6827, 0x0004, 0x7804, 0xa084, 0x4000,
+	0x0040, 0x6e62, 0x7803, 0x1000, 0x7803, 0x0000, 0x0078, 0x6e62,
+	0xd084, 0x0040, 0x6e57, 0x6827, 0x0001, 0x0078, 0x6e59, 0x00f0,
+	0x6e3f, 0x7804, 0xa084, 0x1000, 0x0040, 0x6e62, 0x7803, 0x0100,
+	0x7803, 0x0000, 0x007f, 0x017f, 0x027f, 0x0c7f, 0x0d7f, 0x0e7f,
+	0x0f7f, 0x157f, 0x127f, 0x007c, 0x127e, 0x157e, 0x0f7e, 0x0e7e,
+	0x0d7e, 0x0c7e, 0x027e, 0x017e, 0x007e, 0x2091, 0x8000, 0x2069,
+	0x0100, 0x2079, 0x0140, 0x2071, 0xa5ab, 0x703c, 0x2060, 0x8cff,
+	0x0040, 0x6ee8, 0x6817, 0x0010, 0x2009, 0x00fa, 0x8109, 0x00c0,
+	0x6e86, 0x68c7, 0x0000, 0x68cb, 0x0008, 0x1078, 0x5967, 0x1078,
+	0x1f31, 0x047e, 0x057e, 0x2009, 0x017f, 0x212c, 0x200b, 0x00a5,
+	0x2021, 0x0169, 0x2404, 0xa084, 0x000f, 0xa086, 0x0004, 0x00c0,
+	0x6eb7, 0x68c7, 0x0000, 0x68cb, 0x0008, 0x0e7e, 0x0f7e, 0x2079,
+	0x0020, 0x2071, 0xa602, 0x6814, 0xa084, 0x0004, 0xa085, 0x0012,
+	0x6816, 0x7803, 0x0008, 0x7003, 0x0000, 0x0f7f, 0x0e7f, 0x250a,
+	0x057f, 0x047f, 0xa39d, 0x0000, 0x00c0, 0x6ec2, 0x2009, 0x0049,
+	0x1078, 0x756c, 0x20a9, 0x03e8, 0x6824, 0xd094, 0x0040, 0x6ed5,
+	0x6827, 0x0004, 0x7804, 0xa084, 0x4000, 0x0040, 0x6ee7, 0x7803,
+	0x1000, 0x7803, 0x0000, 0x0078, 0x6ee7, 0xd08c, 0x0040, 0x6edc,
+	0x6827, 0x0002, 0x0078, 0x6ede, 0x00f0, 0x6ec4, 0x7804, 0xa084,
+	0x1000, 0x0040, 0x6ee7, 0x7803, 0x0100, 0x7803, 0x0000, 0x6824,
+	0x007f, 0x017f, 0x027f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f, 0x157f,
+	0x127f, 0x007c, 0x0d7e, 0x127e, 0x2091, 0x8000, 0x2069, 0xa5ab,
+	0x6a06, 0x127f, 0x0d7f, 0x007c, 0x0d7e, 0x127e, 0x2091, 0x8000,
+	0x2069, 0xa5ab, 0x6a32, 0x127f, 0x0d7f, 0x007c, 0x0f7e, 0x0e7e,
+	0x0c7e, 0x067e, 0x007e, 0x127e, 0x2071, 0xa5ab, 0x7614, 0x2660,
+	0x2678, 0x2091, 0x8000, 0x8cff, 0x0040, 0x6f46, 0x601c, 0xa206,
+	0x00c0, 0x6f41, 0x7014, 0xac36, 0x00c0, 0x6f20, 0x660c, 0x7616,
+	0x7010, 0xac36, 0x00c0, 0x6f2e, 0x2c00, 0xaf36, 0x0040, 0x6f2c,
+	0x2f00, 0x7012, 0x0078, 0x6f2e, 0x7013, 0x0000, 0x660c, 0x067e,
+	0x2c00, 0xaf06, 0x0040, 0x6f37, 0x7e0e, 0x0078, 0x6f38, 0x2678,
+	0x600f, 0x0000, 0x1078, 0x8c01, 0x1078, 0x7045, 0x0c7f, 0x0078,
+	0x6f13, 0x2c78, 0x600c, 0x2060, 0x0078, 0x6f13, 0x127f, 0x007f,
+	0x067f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c, 0x157e, 0x147e, 0x20a1,
+	0x020b, 0x1078, 0x6806, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2,
+	0x20a2, 0x20a2, 0x20a3, 0x1000, 0x0078, 0x6fa0, 0x157e, 0x147e,
+	0x20a1, 0x020b, 0x1078, 0x6806, 0x7810, 0x20a2, 0xa006, 0x20a2,
+	0x20a2, 0x20a2, 0x20a2, 0x20a3, 0x4000, 0x0078, 0x6fa0, 0x157e,
+	0x147e, 0x20a1, 0x020b, 0x1078, 0x6806, 0x7810, 0x20a2, 0xa006,
+	0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x20a3, 0x2000, 0x0078, 0x6fa0,
+	0x157e, 0x147e, 0x20a1, 0x020b, 0x1078, 0x6806, 0x7810, 0x20a2,
+	0xa006, 0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x20a3, 0x0400, 0x0078,
+	0x6fa0, 0x157e, 0x147e, 0x20a1, 0x020b, 0x1078, 0x6806, 0x7810,
+	0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x20a3, 0x0200,
+	0x1078, 0x7050, 0x60c3, 0x0020, 0x1078, 0x6c2d, 0x147f, 0x157f,
+	0x007c, 0x127e, 0x0c7e, 0x2091, 0x8000, 0x2061, 0x0100, 0x6120,
+	0xd1b4, 0x00c0, 0x6fb8, 0xd1bc, 0x00c0, 0x7002, 0x0078, 0x7042,
+	0x2009, 0x017f, 0x200b, 0x00a1, 0x157e, 0x007e, 0x0d7e, 0x2069,
+	0x0140, 0x20a9, 0x001e, 0x2009, 0x0169, 0x6804, 0xa084, 0x4000,
+	0x0040, 0x6ff9, 0x6020, 0xd0b4, 0x0040, 0x6ff9, 0x6024, 0xd094,
+	0x00c0, 0x6ff9, 0x2104, 0xa084, 0x000f, 0xa086, 0x0004, 0x00c0,
+	0x6ff9, 0x00f0, 0x6fc5, 0x027e, 0x6198, 0xa18c, 0x00ff, 0x8107,
+	0x6130, 0xa18c, 0x00ff, 0xa10d, 0x6088, 0x628c, 0x618e, 0x608b,
+	0xbc91, 0x6043, 0x0001, 0x6043, 0x0000, 0x608a, 0x628e, 0x6024,
+	0xd094, 0x00c0, 0x6ff8, 0x6a04, 0xa294, 0x4000, 0x00c0, 0x6fef,
+	0x027f, 0x0d7f, 0x007f, 0x157f, 0x2009, 0x017f, 0x200b, 0x0000,
+	0x0078, 0x7042, 0x2009, 0x017f, 0x200b, 0x00a1, 0x157e, 0x007e,
+	0x0d7e, 0x2069, 0x0140, 0x20a9, 0x001e, 0x2009, 0x0169, 0x6804,
+	0xa084, 0x4000, 0x0040, 0x703b, 0x6020, 0xd0bc, 0x0040, 0x703b,
+	0x2104, 0xa084, 0x000f, 0xa086, 0x0004, 0x00c0, 0x703b, 0x00f0,
+	0x700f, 0x027e, 0x6164, 0xa18c, 0x00ff, 0x8107, 0x6130, 0xa18c,
+	0x00ff, 0xa10d, 0x6088, 0x628c, 0x608b, 0xbc91, 0x618e, 0x6043,
+	0x0001, 0x6043, 0x0000, 0x608a, 0x628e, 0x6a04, 0xa294, 0x4000,
+	0x00c0, 0x7035, 0x027f, 0x0d7f, 0x007f, 0x157f, 0x2009, 0x017f,
+	0x200b, 0x0000, 0x0c7f, 0x127f, 0x007c, 0x0e7e, 0x2071, 0xa5ab,
+	0x7020, 0xa005, 0x0040, 0x704e, 0x8001, 0x7022, 0x0e7f, 0x007c,
+	0x20a9, 0x0008, 0x20a2, 0x00f0, 0x7052, 0x20a2, 0x20a2, 0x007c,
+	0x0f7e, 0x0e7e, 0x0d7e, 0x0c7e, 0x077e, 0x067e, 0x007e, 0x127e,
+	0x2091, 0x8000, 0x2071, 0xa5ab, 0x7614, 0x2660, 0x2678, 0x2039,
+	0x0001, 0x87ff, 0x0040, 0x70f4, 0x8cff, 0x0040, 0x70f4, 0x601c,
+	0xa086, 0x0006, 0x00c0, 0x70ef, 0x88ff, 0x0040, 0x707f, 0x2800,
+	0xac06, 0x00c0, 0x70ef, 0x2039, 0x0000, 0x0078, 0x708a, 0x6018,
+	0xa206, 0x00c0, 0x70ef, 0x85ff, 0x0040, 0x708a, 0x6020, 0xa106,
+	0x00c0, 0x70ef, 0x7024, 0xac06, 0x00c0, 0x70ba, 0x2069, 0x0100,
+	0x68c0, 0xa005, 0x0040, 0x70b5, 0x1078, 0x595a, 0x6817, 0x0008,
+	0x68c3, 0x0000, 0x1078, 0x7188, 0x7027, 0x0000, 0x037e, 0x2069,
+	0x0140, 0x6b04, 0xa384, 0x1000, 0x0040, 0x70aa, 0x6803, 0x0100,
+	0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0040, 0x70b2,
+	0x6827, 0x0001, 0x037f, 0x0078, 0x70ba, 0x6003, 0x0009, 0x630a,
+	0x0078, 0x70ef, 0x7014, 0xac36, 0x00c0, 0x70c0, 0x660c, 0x7616,
+	0x7010, 0xac36, 0x00c0, 0x70ce, 0x2c00, 0xaf36, 0x0040, 0x70cc,
+	0x2f00, 0x7012, 0x0078, 0x70ce, 0x7013, 0x0000, 0x660c, 0x067e,
+	0x2c00, 0xaf06, 0x0040, 0x70d7, 0x7e0e, 0x0078, 0x70d8, 0x2678,
+	0x89ff, 0x00c0, 0x70e7, 0x600f, 0x0000, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x70e5, 0x1078, 0x9e70, 0x1078, 0x8c01, 0x1078,
+	0x7045, 0x88ff, 0x00c0, 0x70fe, 0x0c7f, 0x0078, 0x7069, 0x2c78,
+	0x600c, 0x2060, 0x0078, 0x7069, 0xa006, 0x127f, 0x007f, 0x067f,
+	0x077f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f, 0x007c, 0x6017, 0x0000,
+	0x0c7f, 0xa8c5, 0x0001, 0x0078, 0x70f5, 0x0f7e, 0x0e7e, 0x0d7e,
+	0x0c7e, 0x067e, 0x027e, 0x007e, 0x127e, 0x2091, 0x8000, 0x2071,
+	0xa5ab, 0x7638, 0x2660, 0x2678, 0x8cff, 0x0040, 0x7177, 0x601c,
+	0xa086, 0x0006, 0x00c0, 0x7172, 0x87ff, 0x0040, 0x7125, 0x2700,
+	0xac06, 0x00c0, 0x7172, 0x0078, 0x7130, 0x6018, 0xa206, 0x00c0,
+	0x7172, 0x85ff, 0x0040, 0x7130, 0x6020, 0xa106, 0x00c0, 0x7172,
+	0x703c, 0xac06, 0x00c0, 0x7142, 0x037e, 0x2019, 0x0001, 0x1078,
+	0x6e6c, 0x7033, 0x0000, 0x703f, 0x0000, 0x7043, 0x0000, 0x7047,
+	0x0000, 0x037f, 0x7038, 0xac36, 0x00c0, 0x7148, 0x660c, 0x763a,
+	0x7034, 0xac36, 0x00c0, 0x7156, 0x2c00, 0xaf36, 0x0040, 0x7154,
+	0x2f00, 0x7036, 0x0078, 0x7156, 0x7037, 0x0000, 0x660c, 0x067e,
+	0x2c00, 0xaf06, 0x0040, 0x715f, 0x7e0e, 0x0078, 0x7160, 0x2678,
+	0x600f, 0x0000, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x716a,
+	0x1078, 0x9e70, 0x1078, 0x8c01, 0x87ff, 0x00c0, 0x7181, 0x0c7f,
+	0x0078, 0x7114, 0x2c78, 0x600c, 0x2060, 0x0078, 0x7114, 0xa006,
+	0x127f, 0x007f, 0x027f, 0x067f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f,
+	0x007c, 0x6017, 0x0000, 0x0c7f, 0xa7bd, 0x0001, 0x0078, 0x7178,
+	0x0e7e, 0x2071, 0xa5ab, 0x2001, 0xa300, 0x2004, 0xa086, 0x0002,
+	0x00c0, 0x7196, 0x7007, 0x0005, 0x0078, 0x7198, 0x7007, 0x0000,
+	0x0e7f, 0x007c, 0x0f7e, 0x0e7e, 0x0c7e, 0x067e, 0x027e, 0x007e,
+	0x127e, 0x2091, 0x8000, 0x2071, 0xa5ab, 0x2c10, 0x7638, 0x2660,
+	0x2678, 0x8cff, 0x0040, 0x71d8, 0x2200, 0xac06, 0x00c0, 0x71d3,
+	0x7038, 0xac36, 0x00c0, 0x71b6, 0x660c, 0x763a, 0x7034, 0xac36,
+	0x00c0, 0x71c4, 0x2c00, 0xaf36, 0x0040, 0x71c2, 0x2f00, 0x7036,
+	0x0078, 0x71c4, 0x7037, 0x0000, 0x660c, 0x2c00, 0xaf06, 0x0040,
+	0x71cc, 0x7e0e, 0x0078, 0x71cd, 0x2678, 0x600f, 0x0000, 0xa085,
+	0x0001, 0x0078, 0x71d8, 0x2c78, 0x600c, 0x2060, 0x0078, 0x71a9,
+	0x127f, 0x007f, 0x027f, 0x067f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c,
+	0x0f7e, 0x0e7e, 0x0d7e, 0x0c7e, 0x067e, 0x007e, 0x127e, 0x2091,
+	0x8000, 0x2071, 0xa5ab, 0x760c, 0x2660, 0x2678, 0x8cff, 0x0040,
+	0x7279, 0x6018, 0xa080, 0x0028, 0x2004, 0xa206, 0x00c0, 0x7274,
+	0x7024, 0xac06, 0x00c0, 0x721f, 0x2069, 0x0100, 0x68c0, 0xa005,
+	0x0040, 0x724d, 0x1078, 0x6c41, 0x68c3, 0x0000, 0x1078, 0x7188,
+	0x7027, 0x0000, 0x037e, 0x2069, 0x0140, 0x6b04, 0xa384, 0x1000,
+	0x0040, 0x7216, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100,
+	0x6824, 0xd084, 0x0040, 0x721e, 0x6827, 0x0001, 0x037f, 0x700c,
+	0xac36, 0x00c0, 0x7225, 0x660c, 0x760e, 0x7008, 0xac36, 0x00c0,
+	0x7233, 0x2c00, 0xaf36, 0x0040, 0x7231, 0x2f00, 0x700a, 0x0078,
+	0x7233, 0x700b, 0x0000, 0x660c, 0x067e, 0x2c00, 0xaf06, 0x0040,
+	0x723c, 0x7e0e, 0x0078, 0x723d, 0x2678, 0x600f, 0x0000, 0x1078,
+	0x8c27, 0x00c0, 0x7251, 0x1078, 0x2839, 0x1078, 0x8c3b, 0x00c0,
+	0x726d, 0x1078, 0x7a05, 0x0078, 0x726d, 0x1078, 0x7188, 0x0078,
+	0x721f, 0x1078, 0x8c3b, 0x00c0, 0x7259, 0x1078, 0x7a05, 0x0078,
+	0x726d, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x726d, 0x601c,
+	0xa086, 0x0003, 0x00c0, 0x7281, 0x6837, 0x0103, 0x6b4a, 0x6847,
+	0x0000, 0x1078, 0x4982, 0x1078, 0x8bf4, 0x1078, 0x8c01, 0x1078,
+	0x7045, 0x0c7f, 0x0078, 0x71ee, 0x2c78, 0x600c, 0x2060, 0x0078,
+	0x71ee, 0x127f, 0x007f, 0x067f, 0x0c7f, 0x0d7f, 0x0e7f, 0x0f7f,
+	0x007c, 0x601c, 0xa086, 0x0006, 0x00c0, 0x726d, 0x1078, 0x9e70,
+	0x0078, 0x726d, 0x037e, 0x157e, 0x137e, 0x147e, 0x3908, 0xa006,
+	0xa190, 0x0020, 0x221c, 0xa39e, 0x260c, 0x00c0, 0x729b, 0x8210,
+	0x8000, 0x0078, 0x7292, 0xa005, 0x0040, 0x72a7, 0x20a9, 0x0020,
+	0x2198, 0x8211, 0xa282, 0x0020, 0x20c8, 0x20a0, 0x53a3, 0x147f,
+	0x137f, 0x157f, 0x037f, 0x007c, 0x0d7e, 0x20a1, 0x020b, 0x1078,
+	0x65f8, 0x20a3, 0x0200, 0x20a3, 0x0014, 0x60c3, 0x0014, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x2099, 0xa5a3, 0x20a9, 0x0004, 0x53a6,
+	0x20a3, 0x0004, 0x20a3, 0x7878, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x1078, 0x6c2d, 0x0d7f, 0x007c, 0x20a1, 0x020b, 0x1078, 0x65f8,
+	0x20a3, 0x0214, 0x20a3, 0x0018, 0x20a3, 0x0800, 0x7810, 0xa084,
+	0xff00, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x7810, 0xa084, 0x00ff, 0x20a2, 0x7828, 0x20a2,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0018, 0x1078, 0x6c2d,
+	0x007c, 0x0d7e, 0x017e, 0x2f68, 0x2009, 0x0035, 0x1078, 0x8ef5,
+	0x00c0, 0x7361, 0x20a1, 0x020b, 0x1078, 0x6567, 0x20a3, 0x1300,
+	0x20a3, 0x0000, 0x7828, 0x2068, 0x681c, 0xa086, 0x0003, 0x0040,
+	0x733d, 0x7818, 0xa080, 0x0028, 0x2014, 0xa286, 0x007e, 0x00c0,
+	0x7317, 0x20a3, 0x00ff, 0x20a3, 0xfffe, 0x0078, 0x7352, 0xa286,
+	0x007f, 0x00c0, 0x7321, 0x20a3, 0x00ff, 0x20a3, 0xfffd, 0x0078,
+	0x7352, 0xd2bc, 0x0040, 0x7337, 0xa286, 0x0080, 0x00c0, 0x732e,
+	0x20a3, 0x00ff, 0x20a3, 0xfffc, 0x0078, 0x7352, 0xa2e8, 0xa434,
+	0x2d6c, 0x6810, 0x20a2, 0x6814, 0x20a2, 0x0078, 0x7352, 0x20a3,
+	0x0000, 0x6098, 0x20a2, 0x0078, 0x7352, 0x7818, 0xa080, 0x0028,
+	0x2004, 0xa082, 0x007e, 0x0048, 0x734e, 0x0d7e, 0x2069, 0xa31a,
+	0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x7352, 0x20a3, 0x0000,
+	0x6030, 0x20a2, 0x7834, 0x20a2, 0x7838, 0x20a2, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x60c3, 0x000c, 0x1078, 0x6c2d, 0x017f, 0x0d7f,
+	0x007c, 0x7817, 0x0001, 0x7803, 0x0006, 0x017f, 0x0d7f, 0x007c,
+	0x0d7e, 0x027e, 0x7928, 0x2168, 0x691c, 0xa186, 0x0006, 0x0040,
+	0x738a, 0xa186, 0x0003, 0x0040, 0x73e5, 0xa186, 0x0005, 0x0040,
+	0x73c8, 0xa186, 0x0004, 0x0040, 0x73b8, 0xa186, 0x0008, 0x0040,
+	0x73d2, 0x7807, 0x0037, 0x7813, 0x1700, 0x1078, 0x7450, 0x027f,
+	0x0d7f, 0x007c, 0x1078, 0x740d, 0x2009, 0x4000, 0x6800, 0x0079,
+	0x7391, 0x73a4, 0x73b2, 0x73a6, 0x73b2, 0x73ad, 0x73a4, 0x73a4,
+	0x73b2, 0x73b2, 0x73b2, 0x73b2, 0x73a4, 0x73a4, 0x73a4, 0x73a4,
+	0x73a4, 0x73b2, 0x73a4, 0x73b2, 0x1078, 0x1328, 0x6824, 0xd0e4,
+	0x0040, 0x73ad, 0xd0cc, 0x0040, 0x73b0, 0xa00e, 0x0078, 0x73b2,
+	0x2009, 0x2000, 0x6828, 0x20a2, 0x682c, 0x20a2, 0x0078, 0x7403,
+	0x1078, 0x740d, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x2009, 0x4000,
+	0x6a00, 0xa286, 0x0002, 0x00c0, 0x73c6, 0xa00e, 0x0078, 0x7403,
+	0x1078, 0x740d, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x2009, 0x4000,
+	0x0078, 0x7403, 0x1078, 0x740d, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x2009, 0x4000, 0xa286, 0x0005, 0x0040, 0x73e2, 0xa286, 0x0002,
+	0x00c0, 0x73e3, 0xa00e, 0x0078, 0x7403, 0x1078, 0x740d, 0x6810,
+	0x2068, 0x697c, 0x6810, 0xa112, 0x6980, 0x6814, 0xa103, 0x20a2,
+	0x22a2, 0x7928, 0xa180, 0x0000, 0x2004, 0xa08e, 0x0002, 0x0040,
+	0x7401, 0xa08e, 0x0004, 0x0040, 0x7401, 0x2009, 0x4000, 0x0078,
+	0x7403, 0x2009, 0x0000, 0x21a2, 0x20a3, 0x0000, 0x60c3, 0x0018,
+	0x1078, 0x6c2d, 0x027f, 0x0d7f, 0x007c, 0x037e, 0x047e, 0x057e,
+	0x067e, 0x20a1, 0x020b, 0x1078, 0x65f8, 0xa006, 0x20a3, 0x0200,
+	0x20a2, 0x7934, 0x21a2, 0x7938, 0x21a2, 0x7818, 0xa080, 0x0028,
+	0x2004, 0xa092, 0x007e, 0x0048, 0x7433, 0x0d7e, 0x2069, 0xa31a,
+	0x2d2c, 0x8d68, 0x2d34, 0xa0e8, 0xa434, 0x2d6c, 0x6b10, 0x6c14,
+	0x0d7f, 0x0078, 0x7439, 0x2019, 0x0000, 0x6498, 0x2029, 0x0000,
+	0x6630, 0x7828, 0xa080, 0x0007, 0x2004, 0xa086, 0x0003, 0x00c0,
+	0x7447, 0x25a2, 0x26a2, 0x23a2, 0x24a2, 0x0078, 0x744b, 0x23a2,
+	0x24a2, 0x25a2, 0x26a2, 0x067f, 0x057f, 0x047f, 0x037f, 0x007c,
+	0x20a1, 0x020b, 0x1078, 0x65f8, 0x20a3, 0x0100, 0x20a3, 0x0000,
+	0x20a3, 0x0009, 0x7810, 0x20a2, 0x60c3, 0x0008, 0x1078, 0x6c2d,
+	0x007c, 0x20a1, 0x020b, 0x1078, 0x655e, 0x20a3, 0x1400, 0x20a3,
+	0x0000, 0x7834, 0x20a2, 0x7838, 0x20a2, 0x7828, 0x20a2, 0x782c,
+	0x20a2, 0x7830, 0xa084, 0x00ff, 0x8007, 0x20a2, 0x20a3, 0x0000,
+	0x60c3, 0x0010, 0x1078, 0x6c2d, 0x007c, 0x20a1, 0x020b, 0x1078,
+	0x65ef, 0x20a3, 0x0100, 0x20a3, 0x0000, 0x7828, 0x20a2, 0x7810,
+	0x20a2, 0x60c3, 0x0008, 0x1078, 0x6c2d, 0x007c, 0x147e, 0x20a1,
+	0x020b, 0x1078, 0x7499, 0x60c3, 0x0000, 0x1078, 0x6c2d, 0x147f,
+	0x007c, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028,
+	0x2004, 0xd0bc, 0x0040, 0x74b6, 0x0d7e, 0xa0e8, 0xa434, 0x2d6c,
+	0x6810, 0xa085, 0x0300, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xa31a,
+	0x2da6, 0x8d68, 0x2da6, 0x0d7f, 0x0078, 0x74be, 0x20a3, 0x0300,
+	0x6298, 0x22a2, 0x20a3, 0x0000, 0x6230, 0x22a2, 0x20a3, 0x0819,
+	0x20a3, 0x0000, 0x1078, 0x6c1c, 0x22a2, 0x20a3, 0x0000, 0x2fa2,
+	0x7a08, 0x22a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x007c, 0x2061,
+	0xaa00, 0x2a70, 0x7060, 0x7046, 0x704b, 0xaa00, 0x007c, 0x0e7e,
+	0x127e, 0x2071, 0xa300, 0x2091, 0x8000, 0x7544, 0xa582, 0x0010,
+	0x0048, 0x7509, 0x7048, 0x2060, 0x6000, 0xa086, 0x0000, 0x0040,
+	0x74f5, 0xace0, 0x0010, 0x7054, 0xac02, 0x00c8, 0x74f1, 0x0078,
+	0x74e4, 0x2061, 0xaa00, 0x0078, 0x74e4, 0x6003, 0x0008, 0x8529,
+	0x7546, 0xaca8, 0x0010, 0x7054, 0xa502, 0x00c8, 0x7505, 0x754a,
+	0xa085, 0x0001, 0x127f, 0x0e7f, 0x007c, 0x704b, 0xaa00, 0x0078,
+	0x7500, 0xa006, 0x0078, 0x7502, 0x0e7e, 0x2071, 0xa300, 0x7544,
+	0xa582, 0x0010, 0x0048, 0x753a, 0x7048, 0x2060, 0x6000, 0xa086,
+	0x0000, 0x0040, 0x7527, 0xace0, 0x0010, 0x7054, 0xac02, 0x00c8,
+	0x7523, 0x0078, 0x7516, 0x2061, 0xaa00, 0x0078, 0x7516, 0x6003,
+	0x0008, 0x8529, 0x7546, 0xaca8, 0x0010, 0x7054, 0xa502, 0x00c8,
+	0x7536, 0x754a, 0xa085, 0x0001, 0x0e7f, 0x007c, 0x704b, 0xaa00,
+	0x0078, 0x7532, 0xa006, 0x0078, 0x7534, 0xac82, 0xaa00, 0x1048,
+	0x1328, 0x2001, 0xa315, 0x2004, 0xac02, 0x10c8, 0x1328, 0xa006,
+	0x6006, 0x600a, 0x600e, 0x6012, 0x6016, 0x601a, 0x601f, 0x0000,
+	0x6003, 0x0000, 0x6022, 0x6026, 0x602a, 0x602e, 0x6032, 0x6036,
+	0x603a, 0x603e, 0x2061, 0xa300, 0x6044, 0x8000, 0x6046, 0xa086,
+	0x0001, 0x0040, 0x7564, 0x007c, 0x127e, 0x2091, 0x8000, 0x1078,
+	0x6109, 0x127f, 0x0078, 0x7563, 0x601c, 0xa084, 0x000f, 0x0079,
+	0x7571, 0x757a, 0x758b, 0x75a7, 0x75c3, 0x8f2d, 0x8f49, 0x8f65,
+	0x757a, 0x758b, 0xa186, 0x0013, 0x00c0, 0x7583, 0x1078, 0x6010,
+	0x1078, 0x6109, 0x007c, 0xa18e, 0x0047, 0x00c0, 0x758a, 0xa016,
+	0x1078, 0x15ec, 0x007c, 0x067e, 0x6000, 0xa0b2, 0x0010, 0x10c8,
+	0x1328, 0x1079, 0x7595, 0x067f, 0x007c, 0x75a5, 0x7891, 0x7a34,
+	0x75a5, 0x7ab8, 0x75df, 0x75a5, 0x75a5, 0x7823, 0x7e6d, 0x75a5,
+	0x75a5, 0x75a5, 0x75a5, 0x75a5, 0x75a5, 0x1078, 0x1328, 0x067e,
+	0x6000, 0xa0b2, 0x0010, 0x10c8, 0x1328, 0x1079, 0x75b1, 0x067f,
+	0x007c, 0x75c1, 0x8522, 0x75c1, 0x75c1, 0x75c1, 0x75c1, 0x75c1,
+	0x75c1, 0x84c5, 0x86a8, 0x75c1, 0x8552, 0x85d8, 0x8552, 0x85d8,
+	0x75c1, 0x1078, 0x1328, 0x067e, 0x6000, 0xa0b2, 0x0010, 0x10c8,
+	0x1328, 0x1079, 0x75cd, 0x067f, 0x007c, 0x75dd, 0x7eb4, 0x7f81,
+	0x80c6, 0x8242, 0x75dd, 0x75dd, 0x75dd, 0x7e8d, 0x846d, 0x8471,
+	0x75dd, 0x75dd, 0x75dd, 0x75dd, 0x84a1, 0x1078, 0x1328, 0xa1b6,
+	0x0015, 0x00c0, 0x75e7, 0x1078, 0x753d, 0x0078, 0x75ed, 0xa1b6,
+	0x0016, 0x10c0, 0x1328, 0x1078, 0x753d, 0x007c, 0x20a9, 0x000e,
+	0x2e98, 0x6010, 0x20a0, 0x53a3, 0x20a9, 0x0006, 0x3310, 0x3420,
+	0x9398, 0x94a0, 0x3318, 0x3428, 0x222e, 0x2326, 0xa290, 0x0002,
+	0xa5a8, 0x0002, 0xa398, 0x0002, 0xa4a0, 0x0002, 0x00f0, 0x75fc,
+	0x0e7e, 0x1078, 0x8a44, 0x0040, 0x7613, 0x6010, 0x2070, 0x7007,
+	0x0000, 0x7037, 0x0103, 0x0e7f, 0x1078, 0x753d, 0x007c, 0x0d7e,
+	0x037e, 0x7330, 0xa386, 0x0200, 0x00c0, 0x7624, 0x6018, 0x2068,
+	0x6813, 0x00ff, 0x6817, 0xfffd, 0x6010, 0xa005, 0x0040, 0x762e,
+	0x2068, 0x6807, 0x0000, 0x6837, 0x0103, 0x6b32, 0x1078, 0x753d,
+	0x037f, 0x0d7f, 0x007c, 0x017e, 0x20a9, 0x002a, 0xae80, 0x000c,
+	0x2098, 0x6010, 0xa080, 0x0002, 0x20a0, 0x53a3, 0x20a9, 0x002a,
+	0x6010, 0xa080, 0x0001, 0x2004, 0xa080, 0x0002, 0x20a0, 0x53a3,
+	0x0e7e, 0x6010, 0x2004, 0x2070, 0x7037, 0x0103, 0x0e7f, 0x1078,
+	0x753d, 0x017f, 0x007c, 0x0e7e, 0x0d7e, 0x603f, 0x0000, 0x2c68,
+	0x017e, 0x2009, 0x0035, 0x1078, 0x8ef5, 0x017f, 0x00c0, 0x766f,
+	0x027e, 0x6228, 0x2268, 0x027f, 0x2071, 0xa88c, 0x6b1c, 0xa386,
+	0x0003, 0x0040, 0x7673, 0xa386, 0x0006, 0x0040, 0x7677, 0x1078,
+	0x753d, 0x0078, 0x7679, 0x1078, 0x767c, 0x0078, 0x7679, 0x1078,
+	0x771e, 0x0d7f, 0x0e7f, 0x007c, 0x0f7e, 0x6810, 0x2078, 0xa186,
+	0x0015, 0x0040, 0x7705, 0xa18e, 0x0016, 0x00c0, 0x771c, 0x700c,
+	0xa084, 0xff00, 0xa086, 0x1700, 0x00c0, 0x76e0, 0x8fff, 0x0040,
+	0x771a, 0x6808, 0xa086, 0xffff, 0x00c0, 0x7709, 0x784c, 0xa084,
+	0x0060, 0xa086, 0x0020, 0x00c0, 0x76a7, 0x797c, 0x7810, 0xa106,
+	0x00c0, 0x7709, 0x7980, 0x7814, 0xa106, 0x00c0, 0x7709, 0x1078,
+	0x8bf4, 0x6830, 0x7852, 0x784c, 0xc0dc, 0xc0f4, 0xc0d4, 0x784e,
+	0x027e, 0xa00e, 0x6a14, 0x2001, 0x000a, 0x1078, 0x5a98, 0x7854,
+	0xa20a, 0x0048, 0x76bc, 0x8011, 0x7a56, 0x82ff, 0x027f, 0x00c0,
+	0x76c8, 0x0c7e, 0x2d60, 0x1078, 0x8832, 0x0c7f, 0x0078, 0x771a,
+	0x0c7e, 0x0d7e, 0x2f68, 0x6838, 0xd0fc, 0x00c0, 0x76d3, 0x1078,
+	0x4290, 0x0078, 0x76d5, 0x1078, 0x436e, 0x0d7f, 0x0c7f, 0x00c0,
+	0x7709, 0x0c7e, 0x2d60, 0x1078, 0x753d, 0x0c7f, 0x0078, 0x771a,
+	0x7008, 0xa086, 0x000b, 0x00c0, 0x76fa, 0x6018, 0x200c, 0xc1bc,
+	0x2102, 0x0c7e, 0x2d60, 0x7853, 0x0003, 0x6007, 0x0085, 0x6003,
+	0x000b, 0x601f, 0x0002, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0c7f,
+	0x0078, 0x771a, 0x700c, 0xa086, 0x2a00, 0x00c0, 0x7709, 0x2001,
+	0xa5a2, 0x2004, 0x683e, 0x0078, 0x771a, 0x1078, 0x7739, 0x0078,
+	0x771c, 0x8fff, 0x1040, 0x1328, 0x0c7e, 0x0d7e, 0x2d60, 0x2f68,
+	0x684b, 0x0003, 0x1078, 0x8726, 0x1078, 0x8bf4, 0x1078, 0x8c01,
+	0x0d7f, 0x0c7f, 0x1078, 0x753d, 0x0f7f, 0x007c, 0xa186, 0x0015,
+	0x00c0, 0x7728, 0x2001, 0xa5a2, 0x2004, 0x683e, 0x0078, 0x7736,
+	0xa18e, 0x0016, 0x00c0, 0x7738, 0x0c7e, 0x2d00, 0x2060, 0x1078,
+	0xa134, 0x1078, 0x5a41, 0x1078, 0x753d, 0x0c7f, 0x1078, 0x753d,
+	0x007c, 0x027e, 0x037e, 0x047e, 0x7228, 0x7c80, 0x7b7c, 0xd2f4,
+	0x0040, 0x7748, 0x2001, 0xa5a2, 0x2004, 0x683e, 0x0078, 0x77ac,
+	0x0c7e, 0x2d60, 0x1078, 0x874a, 0x0c7f, 0x6804, 0xa086, 0x0050,
+	0x00c0, 0x7760, 0x0c7e, 0x2d00, 0x2060, 0x6003, 0x0001, 0x6007,
+	0x0050, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0c7f, 0x0078, 0x77ac,
+	0x6800, 0xa086, 0x000f, 0x0040, 0x7782, 0x8fff, 0x1040, 0x1328,
+	0x6824, 0xd0dc, 0x00c0, 0x7782, 0x6800, 0xa086, 0x0004, 0x00c0,
+	0x7787, 0x784c, 0xd0ac, 0x0040, 0x7787, 0x784c, 0xc0dc, 0xc0f4,
+	0x784e, 0x7850, 0xc0f4, 0xc0fc, 0x7852, 0x2001, 0x0001, 0x682e,
+	0x0078, 0x77a6, 0x2001, 0x0007, 0x682e, 0x0078, 0x77a6, 0x784c,
+	0xd0b4, 0x00c0, 0x7794, 0xd0ac, 0x0040, 0x7782, 0x784c, 0xd0f4,
+	0x00c0, 0x7782, 0x0078, 0x7775, 0xd2ec, 0x00c0, 0x7782, 0x7024,
+	0xa306, 0x00c0, 0x779f, 0x7020, 0xa406, 0x0040, 0x7782, 0x7020,
+	0x6836, 0x7024, 0x683a, 0x2001, 0x0005, 0x682e, 0x1078, 0x8d2b,
+	0x1078, 0x6109, 0x0078, 0x77ae, 0x1078, 0x753d, 0x047f, 0x037f,
+	0x027f, 0x007c, 0x0e7e, 0x0d7e, 0x027e, 0x6034, 0x2068, 0x6a1c,
+	0xa286, 0x0007, 0x0040, 0x7806, 0xa286, 0x0002, 0x0040, 0x7806,
+	0xa286, 0x0000, 0x0040, 0x7806, 0x6808, 0x6338, 0xa306, 0x00c0,
+	0x7806, 0x2071, 0xa88c, 0xa186, 0x0015, 0x0040, 0x7800, 0xa18e,
+	0x0016, 0x00c0, 0x77e8, 0x6030, 0xa084, 0x00ff, 0xa086, 0x0001,
+	0x00c0, 0x77e8, 0x700c, 0xa086, 0x2a00, 0x00c0, 0x77e8, 0x6034,
+	0xa080, 0x0009, 0x200c, 0xc1dd, 0xc1f5, 0x2102, 0x0078, 0x7800,
+	0x0c7e, 0x6034, 0x2060, 0x6010, 0x2068, 0x1078, 0x8a44, 0x1040,
+	0x1328, 0x6853, 0x0003, 0x6007, 0x0085, 0x6003, 0x000b, 0x601f,
+	0x0002, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0c7f, 0x0078, 0x7806,
+	0x6034, 0x2068, 0x2001, 0xa5a2, 0x2004, 0x683e, 0x1078, 0x753d,
+	0x027f, 0x0d7f, 0x0e7f, 0x007c, 0x0d7e, 0x20a9, 0x000e, 0x2e98,
+	0x6010, 0x20a0, 0x53a3, 0xa1b6, 0x0015, 0x00c0, 0x7820, 0x6018,
+	0x2068, 0x7038, 0x680a, 0x703c, 0x680e, 0x6800, 0xc08d, 0x6802,
+	0x0d7f, 0x0078, 0x7608, 0x2100, 0xa1b2, 0x0044, 0x10c8, 0x1328,
+	0xa1b2, 0x0040, 0x00c8, 0x7888, 0x0079, 0x782e, 0x787c, 0x7870,
+	0x787c, 0x787c, 0x787c, 0x787c, 0x786e, 0x786e, 0x786e, 0x786e,
+	0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e,
+	0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e,
+	0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x787c, 0x786e, 0x787c,
+	0x787c, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x787c, 0x786e,
+	0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e,
+	0x787c, 0x787c, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e, 0x786e,
+	0x786e, 0x786e, 0x786e, 0x787c, 0x786e, 0x786e, 0x1078, 0x1328,
+	0x6003, 0x0001, 0x6106, 0x1078, 0x5c45, 0x127e, 0x2091, 0x8000,
+	0x1078, 0x6109, 0x127f, 0x007c, 0x6003, 0x0001, 0x6106, 0x1078,
+	0x5c45, 0x127e, 0x2091, 0x8000, 0x1078, 0x6109, 0x127f, 0x007c,
+	0x2600, 0x0079, 0x788b, 0x788f, 0x788f, 0x788f, 0x787c, 0x1078,
+	0x1328, 0x6004, 0xa0b2, 0x0044, 0x10c8, 0x1328, 0xa1b6, 0x0013,
+	0x00c0, 0x78a1, 0xa0b2, 0x0040, 0x00c8, 0x79fb, 0x2008, 0x0079,
+	0x7941, 0xa1b6, 0x0027, 0x00c0, 0x78fe, 0x1078, 0x6010, 0x6004,
+	0x1078, 0x8c27, 0x0040, 0x78be, 0x1078, 0x8c3b, 0x0040, 0x78f6,
+	0xa08e, 0x0021, 0x0040, 0x78fa, 0xa08e, 0x0022, 0x0040, 0x78f6,
+	0xa08e, 0x003d, 0x0040, 0x78fa, 0x0078, 0x78f1, 0x1078, 0x2839,
+	0x2001, 0x0007, 0x1078, 0x443f, 0x6018, 0xa080, 0x0028, 0x200c,
+	0x1078, 0x7a05, 0xa186, 0x007e, 0x00c0, 0x78d3, 0x2001, 0xa332,
+	0x2014, 0xc285, 0x2202, 0x017e, 0x027e, 0x037e, 0x2110, 0x2019,
+	0x0028, 0x1078, 0x5d53, 0x077e, 0x2039, 0x0000, 0x1078, 0x5c78,
+	0x0c7e, 0x6018, 0xa065, 0x0040, 0x78e7, 0x1078, 0x471b, 0x0c7f,
+	0x2c08, 0x1078, 0x9c38, 0x077f, 0x037f, 0x027f, 0x017f, 0x1078,
+	0x44bc, 0x1078, 0x753d, 0x1078, 0x6109, 0x007c, 0x1078, 0x7a05,
+	0x0078, 0x78f1, 0x1078, 0x7a28, 0x0078, 0x78f1, 0xa186, 0x0014,
+	0x00c0, 0x78f5, 0x1078, 0x6010, 0x1078, 0x2813, 0x1078, 0x8c27,
+	0x00c0, 0x791d, 0x1078, 0x2839, 0x6018, 0xa080, 0x0028, 0x200c,
+	0x1078, 0x7a05, 0xa186, 0x007e, 0x00c0, 0x791b, 0x2001, 0xa332,
+	0x200c, 0xc185, 0x2102, 0x0078, 0x78f1, 0x1078, 0x8c3b, 0x00c0,
+	0x7925, 0x1078, 0x7a05, 0x0078, 0x78f1, 0x6004, 0xa08e, 0x0032,
+	0x00c0, 0x7936, 0x0e7e, 0x0f7e, 0x2071, 0xa381, 0x2079, 0x0000,
+	0x1078, 0x2b56, 0x0f7f, 0x0e7f, 0x0078, 0x78f1, 0x6004, 0xa08e,
+	0x0021, 0x0040, 0x7921, 0xa08e, 0x0022, 0x1040, 0x7a05, 0x0078,
+	0x78f1, 0x7983, 0x7985, 0x7989, 0x798d, 0x7991, 0x7995, 0x7981,
+	0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981,
+	0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981,
+	0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981, 0x7999,
+	0x79ab, 0x7981, 0x79ad, 0x79ab, 0x7981, 0x7981, 0x7981, 0x7981,
+	0x7981, 0x79ab, 0x79ab, 0x7981, 0x7981, 0x7981, 0x7981, 0x7981,
+	0x7981, 0x7981, 0x7981, 0x79de, 0x79ab, 0x7981, 0x79a5, 0x7981,
+	0x7981, 0x7981, 0x79a7, 0x7981, 0x7981, 0x7981, 0x79ab, 0x7981,
+	0x7981, 0x1078, 0x1328, 0x0078, 0x79ab, 0x2001, 0x000b, 0x0078,
+	0x79b8, 0x2001, 0x0003, 0x0078, 0x79b8, 0x2001, 0x0005, 0x0078,
+	0x79b8, 0x2001, 0x0001, 0x0078, 0x79b8, 0x2001, 0x0009, 0x0078,
+	0x79b8, 0x1078, 0x6010, 0x6003, 0x0005, 0x2001, 0xa5a2, 0x2004,
+	0x603e, 0x1078, 0x6109, 0x0078, 0x79b7, 0x0078, 0x79ab, 0x0078,
+	0x79ab, 0x1078, 0x443f, 0x0078, 0x79f0, 0x1078, 0x6010, 0x6003,
+	0x0004, 0x2001, 0xa5a0, 0x2004, 0x6016, 0x1078, 0x6109, 0x007c,
+	0x1078, 0x443f, 0x1078, 0x6010, 0x2001, 0xa5a2, 0x2004, 0x603e,
+	0x6003, 0x0002, 0x037e, 0x2019, 0xa35c, 0x2304, 0xa084, 0xff00,
+	0x00c0, 0x79cf, 0x2019, 0xa5a0, 0x231c, 0x0078, 0x79d8, 0x8007,
+	0xa09a, 0x0004, 0x0048, 0x79ca, 0x8003, 0x801b, 0x831b, 0xa318,
+	0x6316, 0x037f, 0x1078, 0x6109, 0x0078, 0x79b7, 0x0e7e, 0x0f7e,
+	0x2071, 0xa381, 0x2079, 0x0000, 0x1078, 0x2b56, 0x0f7f, 0x0e7f,
+	0x1078, 0x6010, 0x1078, 0x753d, 0x1078, 0x6109, 0x0078, 0x79b7,
+	0x1078, 0x6010, 0x6003, 0x0002, 0x2001, 0xa5a0, 0x2004, 0x6016,
+	0x1078, 0x6109, 0x007c, 0x2600, 0x2008, 0x0079, 0x79ff, 0x7a03,
+	0x7a03, 0x7a03, 0x79f0, 0x1078, 0x1328, 0x0e7e, 0x1078, 0x8a44,
+	0x0040, 0x7a21, 0x6010, 0x2070, 0x7038, 0xd0fc, 0x0040, 0x7a21,
+	0x7007, 0x0000, 0x017e, 0x6004, 0xa08e, 0x0021, 0x0040, 0x7a23,
+	0xa08e, 0x003d, 0x0040, 0x7a23, 0x017f, 0x7037, 0x0103, 0x7033,
+	0x0100, 0x0e7f, 0x007c, 0x017f, 0x1078, 0x7a28, 0x0078, 0x7a21,
+	0x0e7e, 0xacf0, 0x0004, 0x2e74, 0x7000, 0x2070, 0x7037, 0x0103,
+	0x7023, 0x8001, 0x0e7f, 0x007c, 0x0d7e, 0x6618, 0x2668, 0x6804,
+	0xa084, 0x00ff, 0x0d7f, 0xa0b2, 0x000c, 0x10c8, 0x1328, 0x6604,
+	0xa6b6, 0x0043, 0x00c0, 0x7a48, 0x1078, 0x8e6d, 0x0078, 0x7aa7,
+	0x6604, 0xa6b6, 0x0033, 0x00c0, 0x7a51, 0x1078, 0x8e11, 0x0078,
+	0x7aa7, 0x6604, 0xa6b6, 0x0028, 0x00c0, 0x7a5a, 0x1078, 0x8c6a,
+	0x0078, 0x7aa7, 0x6604, 0xa6b6, 0x0029, 0x00c0, 0x7a63, 0x1078,
+	0x8c84, 0x0078, 0x7aa7, 0x6604, 0xa6b6, 0x001f, 0x00c0, 0x7a6c,
+	0x1078, 0x75ee, 0x0078, 0x7aa7, 0x6604, 0xa6b6, 0x0000, 0x00c0,
+	0x7a75, 0x1078, 0x780c, 0x0078, 0x7aa7, 0x6604, 0xa6b6, 0x0022,
+	0x00c0, 0x7a7e, 0x1078, 0x7617, 0x0078, 0x7aa7, 0x6604, 0xa6b6,
+	0x0035, 0x00c0, 0x7a87, 0x1078, 0x7653, 0x0078, 0x7aa7, 0x6604,
+	0xa6b6, 0x0039, 0x00c0, 0x7a90, 0x1078, 0x77b2, 0x0078, 0x7aa7,
+	0x6604, 0xa6b6, 0x003d, 0x00c0, 0x7a99, 0x1078, 0x7633, 0x0078,
+	0x7aa7, 0xa1b6, 0x0015, 0x00c0, 0x7aa1, 0x1079, 0x7aac, 0x0078,
+	0x7aa7, 0xa1b6, 0x0016, 0x00c0, 0x7aa8, 0x1079, 0x7bfd, 0x007c,
+	0x1078, 0x7583, 0x0078, 0x7aa7, 0x7ad0, 0x7ad3, 0x7ad0, 0x7b1e,
+	0x7ad0, 0x7b91, 0x7c09, 0x7ad0, 0x7ad0, 0x7bd5, 0x7ad0, 0x7beb,
+	0xa1b6, 0x0048, 0x0040, 0x7ac4, 0x20e1, 0x0005, 0x3d18, 0x3e20,
+	0x2c10, 0x1078, 0x15ec, 0x007c, 0x0e7e, 0xacf0, 0x0004, 0x2e74,
+	0x7000, 0x2070, 0x7037, 0x0103, 0x0e7f, 0x1078, 0x753d, 0x007c,
+	0x0005, 0x0005, 0x007c, 0x0e7e, 0x2071, 0xa300, 0x707c, 0xa086,
+	0x0074, 0x00c0, 0x7b07, 0x1078, 0x9c0c, 0x00c0, 0x7af9, 0x0d7e,
+	0x6018, 0x2068, 0x7030, 0xd08c, 0x0040, 0x7aec, 0x6800, 0xd0bc,
+	0x0040, 0x7aec, 0xc0c5, 0x6802, 0x1078, 0x7b0b, 0x0d7f, 0x2001,
+	0x0006, 0x1078, 0x443f, 0x1078, 0x2839, 0x1078, 0x753d, 0x0078,
+	0x7b09, 0x2001, 0x000a, 0x1078, 0x443f, 0x1078, 0x2839, 0x6003,
+	0x0001, 0x6007, 0x0001, 0x1078, 0x5c45, 0x0078, 0x7b09, 0x1078,
+	0x7b81, 0x0e7f, 0x007c, 0x6800, 0xd084, 0x0040, 0x7b1d, 0x2001,
+	0x0000, 0x1078, 0x442b, 0x2069, 0xa351, 0x6804, 0xd0a4, 0x0040,
+	0x7b1d, 0x2001, 0x0006, 0x1078, 0x4472, 0x007c, 0x0d7e, 0x2011,
+	0xa31f, 0x2204, 0xa086, 0x0074, 0x00c0, 0x7b7d, 0x6018, 0x2068,
+	0x6aa0, 0xa286, 0x007e, 0x00c0, 0x7b31, 0x1078, 0x7d17, 0x0078,
+	0x7b7f, 0x1078, 0x7d0d, 0x6018, 0x2068, 0xa080, 0x0028, 0x2014,
+	0xa286, 0x0080, 0x00c0, 0x7b55, 0x6813, 0x00ff, 0x6817, 0xfffc,
+	0x6010, 0xa005, 0x0040, 0x7b4b, 0x2068, 0x6807, 0x0000, 0x6837,
+	0x0103, 0x6833, 0x0200, 0x2001, 0x0006, 0x1078, 0x443f, 0x1078,
+	0x2839, 0x1078, 0x753d, 0x0078, 0x7b7f, 0x0e7e, 0x2071, 0xa332,
+	0x2e04, 0xd09c, 0x0040, 0x7b70, 0x2071, 0xa880, 0x7108, 0x720c,
+	0xa18c, 0x00ff, 0x00c0, 0x7b68, 0xa284, 0xff00, 0x0040, 0x7b70,
+	0x6018, 0x2070, 0x70a0, 0xd0bc, 0x00c0, 0x7b70, 0x7112, 0x7216,
+	0x0e7f, 0x2001, 0x0004, 0x1078, 0x443f, 0x6003, 0x0001, 0x6007,
+	0x0003, 0x1078, 0x5c45, 0x0078, 0x7b7f, 0x1078, 0x7b81, 0x0d7f,
+	0x007c, 0x2001, 0xa300, 0x2004, 0xa086, 0x0003, 0x0040, 0x7b8c,
+	0x2001, 0x0007, 0x1078, 0x443f, 0x1078, 0x2839, 0x1078, 0x753d,
+	0x007c, 0x0e7e, 0x2071, 0xa300, 0x707c, 0xa086, 0x0014, 0x00c0,
+	0x7bcf, 0x7000, 0xa086, 0x0003, 0x00c0, 0x7ba4, 0x6010, 0xa005,
+	0x00c0, 0x7ba4, 0x1078, 0x35f7, 0x0d7e, 0x6018, 0x2068, 0x1078,
+	0x457d, 0x1078, 0x7b0b, 0x0d7f, 0x1078, 0x7dba, 0x00c0, 0x7bcf,
+	0x0d7e, 0x6018, 0x2068, 0x6890, 0x0d7f, 0xa005, 0x0040, 0x7bcf,
+	0x2001, 0x0006, 0x1078, 0x443f, 0x0e7e, 0x6010, 0xa005, 0x0040,
+	0x7bc8, 0x2070, 0x7007, 0x0000, 0x7037, 0x0103, 0x7033, 0x0200,
+	0x0e7f, 0x1078, 0x2839, 0x1078, 0x753d, 0x0078, 0x7bd3, 0x1078,
+	0x7a05, 0x1078, 0x7b81, 0x0e7f, 0x007c, 0x2011, 0xa31f, 0x2204,
+	0xa086, 0x0014, 0x00c0, 0x7be8, 0x2001, 0x0002, 0x1078, 0x443f,
+	0x6003, 0x0001, 0x6007, 0x0001, 0x1078, 0x5c45, 0x0078, 0x7bea,
+	0x1078, 0x7b81, 0x007c, 0x2011, 0xa31f, 0x2204, 0xa086, 0x0004,
+	0x00c0, 0x7bfa, 0x2001, 0x0007, 0x1078, 0x443f, 0x1078, 0x753d,
+	0x0078, 0x7bfc, 0x1078, 0x7b81, 0x007c, 0x7ad0, 0x7c11, 0x7ad0,
+	0x7c4e, 0x7ad0, 0x7cc0, 0x7c09, 0x7ad0, 0x7ad0, 0x7cd5, 0x7ad0,
+	0x7ce8, 0x6604, 0xa6b6, 0x001e, 0x00c0, 0x7c10, 0x1078, 0x753d,
+	0x007c, 0x0d7e, 0x0c7e, 0x1078, 0x7cfb, 0x00c0, 0x7c27, 0x2001,
+	0x0000, 0x1078, 0x442b, 0x2001, 0x0002, 0x1078, 0x443f, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x1078, 0x5c45, 0x0078, 0x7c4b, 0x2009,
+	0xa88e, 0x2104, 0xa086, 0x0009, 0x00c0, 0x7c3c, 0x6018, 0x2068,
+	0x6840, 0xa084, 0x00ff, 0xa005, 0x0040, 0x7c49, 0x8001, 0x6842,
+	0x6017, 0x000a, 0x0078, 0x7c4b, 0x2009, 0xa88f, 0x2104, 0xa084,
+	0xff00, 0xa086, 0x1900, 0x00c0, 0x7c49, 0x1078, 0x753d, 0x0078,
+	0x7c4b, 0x1078, 0x7b81, 0x0c7f, 0x0d7f, 0x007c, 0x1078, 0x7d0a,
+	0x00c0, 0x7c62, 0x2001, 0x0000, 0x1078, 0x442b, 0x2001, 0x0002,
+	0x1078, 0x443f, 0x6003, 0x0001, 0x6007, 0x0002, 0x1078, 0x5c45,
+	0x0078, 0x7c8e, 0x1078, 0x7a05, 0x2009, 0xa88e, 0x2134, 0xa6b4,
+	0x00ff, 0xa686, 0x0005, 0x0040, 0x7c8f, 0xa686, 0x000b, 0x0040,
+	0x7c8c, 0x2009, 0xa88f, 0x2104, 0xa084, 0xff00, 0x00c0, 0x7c7c,
+	0xa686, 0x0009, 0x0040, 0x7c8f, 0xa086, 0x1900, 0x00c0, 0x7c8c,
+	0xa686, 0x0009, 0x0040, 0x7c8f, 0x2001, 0x0004, 0x1078, 0x443f,
+	0x1078, 0x753d, 0x0078, 0x7c8e, 0x1078, 0x7b81, 0x007c, 0x0d7e,
+	0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x7c9d, 0x6838, 0xd0fc,
+	0x0040, 0x7c9d, 0x0d7f, 0x0078, 0x7c8c, 0x6018, 0x2068, 0x6840,
+	0xa084, 0x00ff, 0xa005, 0x0040, 0x7cae, 0x8001, 0x6842, 0x6017,
+	0x000a, 0x6007, 0x0016, 0x0d7f, 0x0078, 0x7c8e, 0x68a0, 0xa086,
+	0x007e, 0x00c0, 0x7cbb, 0x0e7e, 0x2071, 0xa300, 0x1078, 0x41f5,
+	0x0e7f, 0x0078, 0x7cbd, 0x1078, 0x2813, 0x0d7f, 0x0078, 0x7c8c,
+	0x1078, 0x7d0a, 0x00c0, 0x7cd0, 0x2001, 0x0004, 0x1078, 0x443f,
+	0x6003, 0x0001, 0x6007, 0x0003, 0x1078, 0x5c45, 0x0078, 0x7cd4,
+	0x1078, 0x7a05, 0x1078, 0x7b81, 0x007c, 0x1078, 0x7d0a, 0x00c0,
+	0x7ce5, 0x2001, 0x0008, 0x1078, 0x443f, 0x6003, 0x0001, 0x6007,
+	0x0005, 0x1078, 0x5c45, 0x0078, 0x7ce7, 0x1078, 0x7b81, 0x007c,
+	0x1078, 0x7d0a, 0x00c0, 0x7cf8, 0x2001, 0x000a, 0x1078, 0x443f,
+	0x6003, 0x0001, 0x6007, 0x0001, 0x1078, 0x5c45, 0x0078, 0x7cfa,
+	0x1078, 0x7b81, 0x007c, 0x2009, 0xa88e, 0x2104, 0xa086, 0x0003,
+	0x00c0, 0x7d09, 0x2009, 0xa88f, 0x2104, 0xa084, 0xff00, 0xa086,
+	0x2a00, 0x007c, 0xa085, 0x0001, 0x007c, 0x0c7e, 0x017e, 0xac88,
+	0x0006, 0x2164, 0x1078, 0x4513, 0x017f, 0x0c7f, 0x007c, 0x0f7e,
+	0x0e7e, 0x0d7e, 0x037e, 0x017e, 0x6018, 0x2068, 0x2071, 0xa332,
+	0x2e04, 0xa085, 0x0003, 0x2072, 0x1078, 0x7d8b, 0x0040, 0x7d50,
+	0x2001, 0xa352, 0x2004, 0xd0a4, 0x0040, 0x7d39, 0xa006, 0x2020,
+	0x2009, 0x002a, 0x1078, 0x9ec0, 0x2001, 0xa30c, 0x200c, 0xc195,
+	0x2102, 0x2019, 0x002a, 0x2009, 0x0001, 0x1078, 0x27e2, 0x2071,
+	0xa300, 0x1078, 0x260d, 0x0c7e, 0x157e, 0x20a9, 0x0081, 0x2009,
+	0x007f, 0x1078, 0x2921, 0x8108, 0x00f0, 0x7d49, 0x157f, 0x0c7f,
+	0x1078, 0x7d0d, 0x6813, 0x00ff, 0x6817, 0xfffe, 0x2071, 0xa880,
+	0x2079, 0x0100, 0x2e04, 0xa084, 0x00ff, 0x2069, 0xa31a, 0x206a,
+	0x78e6, 0x007e, 0x8e70, 0x2e04, 0x2069, 0xa31b, 0x206a, 0x78ea,
+	0xa084, 0xff00, 0x017f, 0xa105, 0x2009, 0xa325, 0x200a, 0x2069,
+	0xa88e, 0x2071, 0xa59c, 0x6810, 0x2072, 0x6814, 0x7006, 0x6818,
+	0x700a, 0x681c, 0x700e, 0x1078, 0x8da9, 0x2001, 0x0006, 0x1078,
+	0x443f, 0x1078, 0x2839, 0x1078, 0x753d, 0x017f, 0x037f, 0x0d7f,
+	0x0e7f, 0x0f7f, 0x007c, 0x027e, 0x037e, 0x0e7e, 0x157e, 0x2019,
+	0xa325, 0x231c, 0x83ff, 0x0040, 0x7db5, 0x2071, 0xa880, 0x2e14,
+	0xa294, 0x00ff, 0x7004, 0xa084, 0xff00, 0xa205, 0xa306, 0x00c0,
+	0x7db5, 0x2011, 0xa896, 0xad98, 0x000a, 0x20a9, 0x0004, 0x1078,
+	0x7e55, 0x00c0, 0x7db5, 0x2011, 0xa89a, 0xad98, 0x0006, 0x20a9,
+	0x0004, 0x1078, 0x7e55, 0x00c0, 0x7db5, 0x157f, 0x0e7f, 0x037f,
+	0x027f, 0x007c, 0x0e7e, 0x2071, 0xa88c, 0x7004, 0xa086, 0x0014,
+	0x00c0, 0x7ddd, 0x7008, 0xa086, 0x0800, 0x00c0, 0x7ddd, 0x700c,
+	0xd0ec, 0x0040, 0x7ddb, 0xa084, 0x0f00, 0xa086, 0x0100, 0x00c0,
+	0x7ddb, 0x7024, 0xd0a4, 0x00c0, 0x7dd8, 0xd0ac, 0x0040, 0x7ddb,
+	0xa006, 0x0078, 0x7ddd, 0xa085, 0x0001, 0x0e7f, 0x007c, 0x0e7e,
+	0x0d7e, 0x0c7e, 0x077e, 0x057e, 0x047e, 0x027e, 0x007e, 0x127e,
+	0x2091, 0x8000, 0x2029, 0xa5b4, 0x252c, 0x2021, 0xa5ba, 0x2424,
+	0x2061, 0xaa00, 0x2071, 0xa300, 0x7244, 0x7060, 0xa202, 0x00c8,
+	0x7e43, 0x1078, 0x9ee5, 0x0040, 0x7e3b, 0x671c, 0xa786, 0x0001,
+	0x0040, 0x7e3b, 0xa786, 0x0007, 0x0040, 0x7e3b, 0x2500, 0xac06,
+	0x0040, 0x7e3b, 0x2400, 0xac06, 0x0040, 0x7e3b, 0x0c7e, 0x6000,
+	0xa086, 0x0004, 0x00c0, 0x7e16, 0x1078, 0x1749, 0xa786, 0x0008,
+	0x00c0, 0x7e25, 0x1078, 0x8c3b, 0x00c0, 0x7e25, 0x0c7f, 0x1078,
+	0x7a05, 0x1078, 0x8c01, 0x0078, 0x7e3b, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x7e38, 0xa786, 0x0003, 0x00c0, 0x7e4d, 0x6837,
+	0x0103, 0x6b4a, 0x6847, 0x0000, 0x1078, 0x4982, 0x1078, 0x8bf4,
+	0x1078, 0x8c01, 0x0c7f, 0xace0, 0x0010, 0x7054, 0xac02, 0x00c8,
+	0x7e43, 0x0078, 0x7df4, 0x127f, 0x007f, 0x027f, 0x047f, 0x057f,
+	0x077f, 0x0c7f, 0x0d7f, 0x0e7f, 0x007c, 0xa786, 0x0006, 0x00c0,
+	0x7e2f, 0x1078, 0x9e70, 0x0078, 0x7e38, 0x220c, 0x2304, 0xa106,
+	0x00c0, 0x7e60, 0x8210, 0x8318, 0x00f0, 0x7e55, 0xa006, 0x007c,
+	0x2304, 0xa102, 0x0048, 0x7e68, 0x2001, 0x0001, 0x0078, 0x7e6a,
+	0x2001, 0x0000, 0xa18d, 0x0001, 0x007c, 0x6004, 0xa08a, 0x0044,
+	0x10c8, 0x1328, 0x1078, 0x8c27, 0x0040, 0x7e7c, 0x1078, 0x8c3b,
+	0x0040, 0x7e89, 0x0078, 0x7e82, 0x1078, 0x2839, 0x1078, 0x8c3b,
+	0x0040, 0x7e89, 0x1078, 0x6010, 0x1078, 0x753d, 0x1078, 0x6109,
+	0x007c, 0x1078, 0x7a05, 0x0078, 0x7e82, 0xa182, 0x0040, 0x0079,
+	0x7e91, 0x7ea4, 0x7ea4, 0x7ea4, 0x7ea4, 0x7ea4, 0x7ea4, 0x7ea4,
+	0x7ea4, 0x7ea4, 0x7ea4, 0x7ea4, 0x7ea6, 0x7ea6, 0x7ea6, 0x7ea6,
+	0x7ea4, 0x7ea4, 0x7ea4, 0x7ea6, 0x1078, 0x1328, 0x600b, 0xffff,
+	0x6003, 0x0001, 0x6106, 0x1078, 0x5bf8, 0x127e, 0x2091, 0x8000,
+	0x1078, 0x6109, 0x127f, 0x007c, 0xa186, 0x0013, 0x00c0, 0x7ebd,
+	0x6004, 0xa082, 0x0040, 0x0079, 0x7f48, 0xa186, 0x0027, 0x00c0,
+	0x7edf, 0x1078, 0x6010, 0x1078, 0x2813, 0x0d7e, 0x6110, 0x2168,
+	0x1078, 0x8a44, 0x0040, 0x7ed9, 0x6837, 0x0103, 0x684b, 0x0029,
+	0x6847, 0x0000, 0x694c, 0xc1c5, 0x694e, 0x1078, 0x4982, 0x1078,
+	0x8bf4, 0x0d7f, 0x1078, 0x753d, 0x1078, 0x6109, 0x007c, 0xa186,
+	0x0014, 0x00c0, 0x7ee8, 0x6004, 0xa082, 0x0040, 0x0079, 0x7f10,
+	0xa186, 0x0046, 0x0040, 0x7ef4, 0xa186, 0x0045, 0x0040, 0x7ef4,
+	0xa186, 0x0047, 0x10c0, 0x1328, 0x2001, 0x0109, 0x2004, 0xd084,
+	0x0040, 0x7f0d, 0x127e, 0x2091, 0x2200, 0x007e, 0x017e, 0x027e,
+	0x1078, 0x5ad2, 0x027f, 0x017f, 0x007f, 0x127f, 0x6000, 0xa086,
+	0x0002, 0x00c0, 0x7f0d, 0x0078, 0x7f81, 0x1078, 0x7583, 0x007c,
+	0x7f25, 0x7f23, 0x7f23, 0x7f23, 0x7f23, 0x7f23, 0x7f23, 0x7f23,
+	0x7f23, 0x7f23, 0x7f23, 0x7f41, 0x7f41, 0x7f41, 0x7f41, 0x7f23,
+	0x7f41, 0x7f23, 0x7f41, 0x1078, 0x1328, 0x1078, 0x6010, 0x0d7e,
+	0x6110, 0x2168, 0x1078, 0x8a44, 0x0040, 0x7f3b, 0x6837, 0x0103,
+	0x684b, 0x0006, 0x6847, 0x0000, 0x6850, 0xc0ec, 0x6852, 0x1078,
+	0x4982, 0x1078, 0x8bf4, 0x0d7f, 0x1078, 0x753d, 0x1078, 0x6109,
+	0x007c, 0x1078, 0x6010, 0x1078, 0x753d, 0x1078, 0x6109, 0x007c,
+	0x7f5d, 0x7f5b, 0x7f5b, 0x7f5b, 0x7f5b, 0x7f5b, 0x7f5b, 0x7f5b,
+	0x7f5b, 0x7f5b, 0x7f5b, 0x7f6f, 0x7f6f, 0x7f6f, 0x7f6f, 0x7f5b,
+	0x7f7a, 0x7f5b, 0x7f6f, 0x1078, 0x1328, 0x1078, 0x6010, 0x2001,
+	0xa5a2, 0x2004, 0x603e, 0x6003, 0x0002, 0x1078, 0x6109, 0x6010,
+	0xa088, 0x0013, 0x2104, 0xa085, 0x0400, 0x200a, 0x007c, 0x1078,
+	0x6010, 0x2001, 0xa5a2, 0x2004, 0x603e, 0x6003, 0x000f, 0x1078,
+	0x6109, 0x007c, 0x1078, 0x6010, 0x1078, 0x753d, 0x1078, 0x6109,
+	0x007c, 0xa182, 0x0040, 0x0079, 0x7f85, 0x7f98, 0x7f98, 0x7f98,
+	0x7f98, 0x7f98, 0x7f9a, 0x8095, 0x80b7, 0x7f98, 0x7f98, 0x7f98,
+	0x7f98, 0x7f98, 0x7f98, 0x7f98, 0x7f98, 0x7f98, 0x7f98, 0x7f98,
+	0x1078, 0x1328, 0x0e7e, 0x0d7e, 0x603f, 0x0000, 0x2071, 0xa880,
+	0x7124, 0x610a, 0x2071, 0xa88c, 0x6110, 0x2168, 0x7614, 0xa6b4,
+	0x0fff, 0x86ff, 0x0040, 0x8058, 0xa68c, 0x0c00, 0x0040, 0x7fd1,
+	0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f, 0x0040, 0x7fcd, 0x684c,
+	0xd0ac, 0x0040, 0x7fcd, 0x6024, 0xd0dc, 0x00c0, 0x7fcd, 0x6850,
+	0xd0bc, 0x00c0, 0x7fcd, 0x7318, 0x6814, 0xa306, 0x00c0, 0x806f,
+	0x731c, 0x6810, 0xa306, 0x00c0, 0x806f, 0x7318, 0x6b62, 0x731c,
+	0x6b5e, 0xa68c, 0x00ff, 0xa186, 0x0002, 0x0040, 0x8004, 0xa186,
+	0x0028, 0x00c0, 0x7fe1, 0x1078, 0x8c15, 0x684b, 0x001c, 0x0078,
+	0x8006, 0xd6dc, 0x0040, 0x7ffd, 0x684b, 0x0015, 0x684c, 0xd0ac,
+	0x0040, 0x7ffb, 0x6914, 0x6a10, 0x2100, 0xa205, 0x0040, 0x7ffb,
+	0x7018, 0xa106, 0x00c0, 0x7ff8, 0x701c, 0xa206, 0x0040, 0x7ffb,
+	0x6962, 0x6a5e, 0xc6dc, 0x0078, 0x8006, 0xd6d4, 0x0040, 0x8004,
+	0x684b, 0x0007, 0x0078, 0x8006, 0x684b, 0x0000, 0x6837, 0x0103,
+	0x6e46, 0xa01e, 0xd6c4, 0x0040, 0x802f, 0xa686, 0x0100, 0x00c0,
+	0x801a, 0x2001, 0xa899, 0x2004, 0xa005, 0x00c0, 0x801a, 0xc6c4,
+	0x0078, 0x7fa9, 0x7328, 0x732c, 0x6b56, 0x83ff, 0x0040, 0x802f,
+	0xa38a, 0x0009, 0x0048, 0x8026, 0x2019, 0x0008, 0x037e, 0x2308,
+	0x2019, 0xa898, 0xad90, 0x0019, 0x1078, 0x8739, 0x037f, 0xd6cc,
+	0x0040, 0x8085, 0x7124, 0x695a, 0x81ff, 0x0040, 0x8085, 0xa192,
+	0x0021, 0x00c8, 0x8046, 0x2071, 0xa898, 0x831c, 0x2300, 0xae18,
+	0xad90, 0x001d, 0x1078, 0x8739, 0x0078, 0x8085, 0x6838, 0xd0fc,
+	0x0040, 0x804f, 0x2009, 0x0020, 0x695a, 0x0078, 0x803b, 0x0f7e,
+	0x2d78, 0x1078, 0x86d1, 0x0f7f, 0x1078, 0x8726, 0x0078, 0x8087,
+	0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f, 0x0040, 0x8075, 0x684c,
+	0xd0ac, 0x0040, 0x8075, 0x6024, 0xd0dc, 0x00c0, 0x8075, 0x6850,
+	0xd0bc, 0x00c0, 0x8075, 0x684c, 0xd0f4, 0x00c0, 0x8075, 0x1078,
+	0x8cfa, 0x0d7f, 0x0e7f, 0x0078, 0x8094, 0x684b, 0x0000, 0x6837,
+	0x0103, 0x6e46, 0x684c, 0xd0ac, 0x0040, 0x8085, 0x6810, 0x6914,
+	0xa115, 0x0040, 0x8085, 0x1078, 0x8233, 0x1078, 0x4982, 0x6218,
+	0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x1078, 0x8cc4, 0x0d7f, 0x0e7f,
+	0x00c0, 0x8094, 0x1078, 0x753d, 0x007c, 0x0f7e, 0x6003, 0x0003,
+	0x2079, 0xa88c, 0x7c04, 0x7b00, 0x7e0c, 0x7d08, 0x6010, 0x2078,
+	0x784c, 0xd0ac, 0x0040, 0x80a8, 0x6003, 0x0002, 0x0f7f, 0x007c,
+	0x7c12, 0x7b16, 0x7e0a, 0x7d0e, 0x0f7f, 0x603f, 0x0000, 0x2c10,
+	0x1078, 0x1cab, 0x1078, 0x5c64, 0x1078, 0x61d3, 0x007c, 0x2001,
+	0xa5a2, 0x2004, 0x603e, 0x6003, 0x0004, 0x6110, 0x20e1, 0x0005,
+	0x3d18, 0x3e20, 0x2c10, 0x1078, 0x15ec, 0x007c, 0xa182, 0x0040,
+	0x0079, 0x80ca, 0x80dd, 0x80dd, 0x80dd, 0x80dd, 0x80dd, 0x80df,
+	0x8182, 0x80dd, 0x80dd, 0x8198, 0x8209, 0x80dd, 0x80dd, 0x80dd,
+	0x80dd, 0x8218, 0x80dd, 0x80dd, 0x80dd, 0x1078, 0x1328, 0x077e,
+	0x0f7e, 0x0e7e, 0x0d7e, 0x2071, 0xa88c, 0x6110, 0x2178, 0x7614,
+	0xa6b4, 0x0fff, 0x7e46, 0x7f4c, 0xc7e5, 0x7f4e, 0x6218, 0x2268,
+	0x6a3c, 0x8211, 0x6a3e, 0x86ff, 0x0040, 0x817d, 0xa694, 0xff00,
+	0xa284, 0x0c00, 0x0040, 0x8100, 0x7018, 0x7862, 0x701c, 0x785e,
+	0xa284, 0x0300, 0x0040, 0x817d, 0x1078, 0x1381, 0x1040, 0x1328,
+	0x2d00, 0x784a, 0x7f4c, 0xc7cd, 0x7f4e, 0x6837, 0x0103, 0x7838,
+	0x683a, 0x783c, 0x683e, 0x7840, 0x6842, 0x6e46, 0xa68c, 0x0c00,
+	0x0040, 0x811e, 0x7318, 0x6b62, 0x731c, 0x6b5e, 0xa68c, 0x00ff,
+	0xa186, 0x0002, 0x0040, 0x813a, 0xa186, 0x0028, 0x00c0, 0x812c,
+	0x684b, 0x001c, 0x0078, 0x813c, 0xd6dc, 0x0040, 0x8133, 0x684b,
+	0x0015, 0x0078, 0x813c, 0xd6d4, 0x0040, 0x813a, 0x684b, 0x0007,
+	0x0078, 0x813c, 0x684b, 0x0000, 0x6f4e, 0x7850, 0x6852, 0x7854,
+	0x6856, 0xa01e, 0xd6c4, 0x0040, 0x815a, 0x7328, 0x732c, 0x6b56,
+	0x83ff, 0x0040, 0x815a, 0xa38a, 0x0009, 0x0048, 0x8151, 0x2019,
+	0x0008, 0x037e, 0x2308, 0x2019, 0xa898, 0xad90, 0x0019, 0x1078,
+	0x8739, 0x037f, 0xd6cc, 0x0040, 0x817d, 0x7124, 0x695a, 0x81ff,
+	0x0040, 0x817d, 0xa192, 0x0021, 0x00c8, 0x8171, 0x2071, 0xa898,
+	0x831c, 0x2300, 0xae18, 0xad90, 0x001d, 0x1078, 0x8739, 0x0078,
+	0x817d, 0x7838, 0xd0fc, 0x0040, 0x817a, 0x2009, 0x0020, 0x695a,
+	0x0078, 0x8166, 0x2d78, 0x1078, 0x86d1, 0x0d7f, 0x0e7f, 0x0f7f,
+	0x077f, 0x007c, 0x0f7e, 0x6003, 0x0003, 0x2079, 0xa88c, 0x7c04,
+	0x7b00, 0x7e0c, 0x7d08, 0x6010, 0x2078, 0x7c12, 0x7b16, 0x7e0a,
+	0x7d0e, 0x0f7f, 0x2c10, 0x1078, 0x1cab, 0x1078, 0x6c26, 0x007c,
+	0x0d7e, 0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f, 0x0040, 0x81a4,
+	0x2001, 0xa5a2, 0x2004, 0x603e, 0x6003, 0x0002, 0x1078, 0x60b8,
+	0x1078, 0x61d3, 0x6110, 0x2168, 0x694c, 0xd1e4, 0x0040, 0x8207,
+	0xd1cc, 0x0040, 0x81de, 0x6948, 0x6838, 0xd0fc, 0x0040, 0x81d6,
+	0x017e, 0x684c, 0x007e, 0x6850, 0x007e, 0xad90, 0x000d, 0xa198,
+	0x000d, 0x2009, 0x0020, 0x157e, 0x21a8, 0x2304, 0x2012, 0x8318,
+	0x8210, 0x00f0, 0x81c5, 0x157f, 0x007f, 0x6852, 0x007f, 0x684e,
+	0x017f, 0x2168, 0x1078, 0x13aa, 0x0078, 0x8201, 0x017e, 0x1078,
+	0x13aa, 0x0d7f, 0x1078, 0x8726, 0x0078, 0x8201, 0x6837, 0x0103,
+	0x6944, 0xa184, 0x00ff, 0xa0b6, 0x0002, 0x0040, 0x81fd, 0xa086,
+	0x0028, 0x00c0, 0x81ef, 0x684b, 0x001c, 0x0078, 0x81ff, 0xd1dc,
+	0x0040, 0x81f6, 0x684b, 0x0015, 0x0078, 0x81ff, 0xd1d4, 0x0040,
+	0x81fd, 0x684b, 0x0007, 0x0078, 0x81ff, 0x684b, 0x0000, 0x1078,
+	0x4982, 0x1078, 0x8cc4, 0x00c0, 0x8207, 0x1078, 0x753d, 0x0d7f,
+	0x007c, 0x2019, 0x0001, 0x1078, 0x6e6c, 0x6003, 0x0002, 0x2001,
+	0xa5a2, 0x2004, 0x603e, 0x1078, 0x60b8, 0x1078, 0x61d3, 0x007c,
+	0x1078, 0x60b8, 0x1078, 0x2813, 0x0d7e, 0x6110, 0x2168, 0x1078,
+	0x8a44, 0x0040, 0x822d, 0x6837, 0x0103, 0x684b, 0x0029, 0x6847,
+	0x0000, 0x1078, 0x4982, 0x1078, 0x8bf4, 0x0d7f, 0x1078, 0x753d,
+	0x1078, 0x61d3, 0x007c, 0x684b, 0x0015, 0xd1fc, 0x0040, 0x823f,
+	0x684b, 0x0007, 0x8002, 0x8000, 0x810a, 0xa189, 0x0000, 0x6962,
+	0x685e, 0x007c, 0xa182, 0x0040, 0x0079, 0x8246, 0x8259, 0x8259,
+	0x8259, 0x8259, 0x8259, 0x825b, 0x8259, 0x8333, 0x833f, 0x8259,
+	0x8259, 0x8259, 0x8259, 0x8259, 0x8259, 0x8259, 0x8259, 0x8259,
+	0x8259, 0x1078, 0x1328, 0x077e, 0x0f7e, 0x0e7e, 0x0d7e, 0x2071,
+	0xa88c, 0x6110, 0x2178, 0x7614, 0xa6b4, 0x0fff, 0x0f7e, 0x2c78,
+	0x1078, 0x4893, 0x0f7f, 0x0040, 0x827e, 0xa684, 0x00ff, 0x00c0,
+	0x827e, 0x6024, 0xd0f4, 0x00c0, 0x827a, 0x7808, 0xa086, 0x0000,
+	0x00c0, 0x827e, 0x1078, 0x8cfa, 0x0078, 0x832e, 0x7e46, 0x7f4c,
+	0xc7e5, 0x7f4e, 0x6218, 0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x86ff,
+	0x0040, 0x8323, 0xa694, 0xff00, 0xa284, 0x0c00, 0x0040, 0x8294,
+	0x7018, 0x7862, 0x701c, 0x785e, 0xa284, 0x0300, 0x0040, 0x8320,
+	0xa686, 0x0100, 0x00c0, 0x82a6, 0x2001, 0xa899, 0x2004, 0xa005,
+	0x00c0, 0x82a6, 0xc6c4, 0x7e46, 0x0078, 0x8287, 0x1078, 0x1381,
+	0x1040, 0x1328, 0x2d00, 0x784a, 0x7f4c, 0xa7bd, 0x0200, 0x7f4e,
+	0x6837, 0x0103, 0x7838, 0x683a, 0x783c, 0x683e, 0x7840, 0x6842,
+	0x6e46, 0xa68c, 0x0c00, 0x0040, 0x82c1, 0x7318, 0x6b62, 0x731c,
+	0x6b5e, 0xa68c, 0x00ff, 0xa186, 0x0002, 0x0040, 0x82dd, 0xa186,
+	0x0028, 0x00c0, 0x82cf, 0x684b, 0x001c, 0x0078, 0x82df, 0xd6dc,
+	0x0040, 0x82d6, 0x684b, 0x0015, 0x0078, 0x82df, 0xd6d4, 0x0040,
+	0x82dd, 0x684b, 0x0007, 0x0078, 0x82df, 0x684b, 0x0000, 0x6f4e,
+	0x7850, 0x6852, 0x7854, 0x6856, 0xa01e, 0xd6c4, 0x0040, 0x82fd,
+	0x7328, 0x732c, 0x6b56, 0x83ff, 0x0040, 0x82fd, 0xa38a, 0x0009,
+	0x0048, 0x82f4, 0x2019, 0x0008, 0x037e, 0x2308, 0x2019, 0xa898,
+	0xad90, 0x0019, 0x1078, 0x8739, 0x037f, 0xd6cc, 0x0040, 0x8320,
+	0x7124, 0x695a, 0x81ff, 0x0040, 0x8320, 0xa192, 0x0021, 0x00c8,
+	0x8314, 0x2071, 0xa898, 0x831c, 0x2300, 0xae18, 0xad90, 0x001d,
+	0x1078, 0x8739, 0x0078, 0x8320, 0x7838, 0xd0fc, 0x0040, 0x831d,
+	0x2009, 0x0020, 0x695a, 0x0078, 0x8309, 0x2d78, 0x1078, 0x86d1,
+	0xd6dc, 0x00c0, 0x8326, 0xa006, 0x0078, 0x832c, 0x2001, 0x0001,
+	0x2071, 0xa88c, 0x7218, 0x731c, 0x1078, 0x1645, 0x0d7f, 0x0e7f,
+	0x0f7f, 0x077f, 0x007c, 0x2001, 0xa5a2, 0x2004, 0x603e, 0x20e1,
+	0x0005, 0x3d18, 0x3e20, 0x2c10, 0x1078, 0x15ec, 0x007c, 0x2001,
+	0xa5a2, 0x2004, 0x603e, 0x0d7e, 0x6003, 0x0002, 0x6110, 0x2168,
+	0x694c, 0xd1e4, 0x0040, 0x846b, 0x603f, 0x0000, 0x0f7e, 0x2c78,
+	0x1078, 0x4893, 0x0f7f, 0x0040, 0x8385, 0x6814, 0x6910, 0xa115,
+	0x0040, 0x8385, 0x6a60, 0xa206, 0x00c0, 0x8362, 0x685c, 0xa106,
+	0x0040, 0x8385, 0x684c, 0xc0e4, 0x684e, 0x6847, 0x0000, 0x6863,
+	0x0000, 0x685f, 0x0000, 0x6024, 0xd0f4, 0x00c0, 0x837a, 0x697c,
+	0x6810, 0xa102, 0x603a, 0x6980, 0x6814, 0xa103, 0x6036, 0x6024,
+	0xc0f5, 0x6026, 0x0d7e, 0x6018, 0x2068, 0x683c, 0x8000, 0x683e,
+	0x0d7f, 0x1078, 0x8cfa, 0x0078, 0x846b, 0x694c, 0xd1cc, 0x0040,
+	0x8430, 0x6948, 0x6838, 0xd0fc, 0x0040, 0x83ea, 0x017e, 0x684c,
+	0x007e, 0x6850, 0x007e, 0x0f7e, 0x2178, 0x7944, 0xa184, 0x00ff,
+	0xa0b6, 0x0002, 0x0040, 0x83bf, 0xa086, 0x0028, 0x00c0, 0x83a6,
+	0x684b, 0x001c, 0x784b, 0x001c, 0x0078, 0x83ca, 0xd1dc, 0x0040,
+	0x83b6, 0x684b, 0x0015, 0x784b, 0x0015, 0x1078, 0x8ea5, 0x0040,
+	0x83b4, 0x7944, 0xc1dc, 0x7946, 0x0078, 0x83ca, 0xd1d4, 0x0040,
+	0x83bf, 0x684b, 0x0007, 0x784b, 0x0007, 0x0078, 0x83ca, 0x684c,
+	0xd0ac, 0x0040, 0x83ca, 0x6810, 0x6914, 0xa115, 0x0040, 0x83ca,
+	0x1078, 0x8233, 0x6848, 0x784a, 0x6860, 0x7862, 0x685c, 0x785e,
+	0xad90, 0x000d, 0xaf98, 0x000d, 0x2009, 0x0020, 0x157e, 0x21a8,
+	0x2304, 0x2012, 0x8318, 0x8210, 0x00f0, 0x83d8, 0x157f, 0x0f7f,
+	0x007f, 0x6852, 0x007f, 0x684e, 0x017f, 0x2168, 0x1078, 0x13aa,
+	0x0078, 0x8465, 0x017e, 0x0f7e, 0x2178, 0x7944, 0xa184, 0x00ff,
+	0xa0b6, 0x0002, 0x0040, 0x8417, 0xa086, 0x0028, 0x00c0, 0x83fe,
+	0x684b, 0x001c, 0x784b, 0x001c, 0x0078, 0x8422, 0xd1dc, 0x0040,
+	0x840e, 0x684b, 0x0015, 0x784b, 0x0015, 0x1078, 0x8ea5, 0x0040,
+	0x840c, 0x7944, 0xc1dc, 0x7946, 0x0078, 0x8422, 0xd1d4, 0x0040,
+	0x8417, 0x684b, 0x0007, 0x784b, 0x0007, 0x0078, 0x8422, 0x684c,
+	0xd0ac, 0x0040, 0x8422, 0x6810, 0x6914, 0xa115, 0x0040, 0x8422,
+	0x1078, 0x8233, 0x6860, 0x7862, 0x685c, 0x785e, 0x684c, 0x784e,
+	0x0f7f, 0x1078, 0x13aa, 0x0d7f, 0x1078, 0x8726, 0x0078, 0x8465,
+	0x6837, 0x0103, 0x6944, 0xa184, 0x00ff, 0xa0b6, 0x0002, 0x0040,
+	0x8456, 0xa086, 0x0028, 0x00c0, 0x8441, 0x684b, 0x001c, 0x0078,
+	0x8463, 0xd1dc, 0x0040, 0x844f, 0x684b, 0x0015, 0x1078, 0x8ea5,
+	0x0040, 0x844d, 0x6944, 0xc1dc, 0x6946, 0x0078, 0x8463, 0xd1d4,
+	0x0040, 0x8456, 0x684b, 0x0007, 0x0078, 0x8463, 0x684b, 0x0000,
+	0x684c, 0xd0ac, 0x0040, 0x8463, 0x6810, 0x6914, 0xa115, 0x0040,
+	0x8463, 0x1078, 0x8233, 0x1078, 0x4982, 0x1078, 0x8cc4, 0x00c0,
+	0x846b, 0x1078, 0x753d, 0x0d7f, 0x007c, 0x1078, 0x6010, 0x0078,
+	0x8473, 0x1078, 0x60b8, 0x1078, 0x8a44, 0x0040, 0x8492, 0x0d7e,
+	0x6110, 0x2168, 0x6837, 0x0103, 0x2009, 0xa30c, 0x210c, 0xd18c,
+	0x00c0, 0x849d, 0xd184, 0x00c0, 0x8499, 0x6108, 0x694a, 0xa18e,
+	0x0029, 0x00c0, 0x848d, 0x1078, 0xa181, 0x6847, 0x0000, 0x1078,
+	0x4982, 0x0d7f, 0x1078, 0x753d, 0x1078, 0x6109, 0x1078, 0x61d3,
+	0x007c, 0x684b, 0x0004, 0x0078, 0x848d, 0x684b, 0x0004, 0x0078,
+	0x848d, 0xa182, 0x0040, 0x0079, 0x84a5, 0x84b8, 0x84b8, 0x84b8,
+	0x84b8, 0x84b8, 0x84ba, 0x84b8, 0x84bd, 0x84b8, 0x84b8, 0x84b8,
+	0x84b8, 0x84b8, 0x84b8, 0x84b8, 0x84b8, 0x84b8, 0x84b8, 0x84b8,
+	0x1078, 0x1328, 0x1078, 0x753d, 0x007c, 0x007e, 0x027e, 0xa016,
+	0x1078, 0x15ec, 0x027f, 0x007f, 0x007c, 0xa182, 0x0085, 0x0079,
+	0x84c9, 0x84d2, 0x84d0, 0x84d0, 0x84de, 0x84d0, 0x84d0, 0x84d0,
+	0x1078, 0x1328, 0x6003, 0x0001, 0x6106, 0x1078, 0x5bf8, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x6109, 0x127f, 0x007c, 0x027e, 0x057e,
+	0x0d7e, 0x0e7e, 0x2071, 0xa880, 0x7224, 0x6212, 0x7220, 0x1078,
+	0x8a30, 0x0040, 0x8503, 0x2268, 0x6800, 0xa086, 0x0000, 0x0040,
+	0x8503, 0x6018, 0x6d18, 0xa52e, 0x00c0, 0x8503, 0x0c7e, 0x2d60,
+	0x1078, 0x874a, 0x0c7f, 0x0040, 0x8503, 0x6803, 0x0002, 0x6007,
+	0x0086, 0x0078, 0x8505, 0x6007, 0x0087, 0x6003, 0x0001, 0x1078,
+	0x5bf8, 0x1078, 0x6109, 0x0f7e, 0x2278, 0x1078, 0x4893, 0x0f7f,
+	0x0040, 0x851d, 0x6824, 0xd0ec, 0x0040, 0x851d, 0x0c7e, 0x2260,
+	0x603f, 0x0000, 0x1078, 0x8cfa, 0x0c7f, 0x0e7f, 0x0d7f, 0x057f,
+	0x027f, 0x007c, 0xa186, 0x0013, 0x00c0, 0x8533, 0x6004, 0xa08a,
+	0x0085, 0x1048, 0x1328, 0xa08a, 0x008c, 0x10c8, 0x1328, 0xa082,
+	0x0085, 0x0079, 0x8542, 0xa186, 0x0027, 0x0040, 0x853b, 0xa186,
+	0x0014, 0x10c0, 0x1328, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078,
+	0x6109, 0x007c, 0x8549, 0x854b, 0x854b, 0x8549, 0x8549, 0x8549,
+	0x8549, 0x1078, 0x1328, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078,
+	0x6109, 0x007c, 0xa186, 0x0013, 0x00c0, 0x855c, 0x6004, 0xa082,
+	0x0085, 0x2008, 0x0078, 0x8597, 0xa186, 0x0027, 0x00c0, 0x857f,
+	0x1078, 0x6010, 0x1078, 0x2813, 0x0d7e, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x8575, 0x6837, 0x0103, 0x6847, 0x0000, 0x684b,
+	0x0029, 0x1078, 0x4982, 0x1078, 0x8bf4, 0x0d7f, 0x1078, 0x753d,
+	0x1078, 0x6109, 0x007c, 0x1078, 0x7583, 0x0078, 0x857a, 0xa186,
+	0x0014, 0x00c0, 0x857b, 0x1078, 0x6010, 0x0d7e, 0x6010, 0x2068,
+	0x1078, 0x8a44, 0x0040, 0x8575, 0x6837, 0x0103, 0x6847, 0x0000,
+	0x684b, 0x0006, 0x6850, 0xc0ec, 0x6852, 0x0078, 0x8571, 0x0079,
+	0x8599, 0x85a2, 0x85a0, 0x85a0, 0x85a0, 0x85a0, 0x85a0, 0x85bd,
+	0x1078, 0x1328, 0x1078, 0x6010, 0x6030, 0xa08c, 0xff00, 0x810f,
+	0xa186, 0x0039, 0x0040, 0x85b0, 0xa186, 0x0035, 0x00c0, 0x85b4,
+	0x2001, 0xa5a0, 0x0078, 0x85b6, 0x2001, 0xa5a1, 0x2004, 0x6016,
+	0x6003, 0x000c, 0x1078, 0x6109, 0x007c, 0x1078, 0x6010, 0x6030,
+	0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0040, 0x85cb, 0xa186,
+	0x0035, 0x00c0, 0x85cf, 0x2001, 0xa5a0, 0x0078, 0x85d1, 0x2001,
+	0xa5a1, 0x2004, 0x6016, 0x6003, 0x000e, 0x1078, 0x6109, 0x007c,
+	0xa182, 0x008c, 0x00c8, 0x85e2, 0xa182, 0x0085, 0x0048, 0x85e2,
+	0x0079, 0x85e5, 0x1078, 0x7583, 0x007c, 0x85ec, 0x85ec, 0x85ec,
+	0x85ec, 0x85ee, 0x8643, 0x85ec, 0x1078, 0x1328, 0x0f7e, 0x2c78,
+	0x1078, 0x4893, 0x0f7f, 0x0040, 0x8601, 0x6030, 0xa08c, 0xff00,
+	0x810f, 0xa186, 0x0039, 0x0040, 0x865a, 0xa186, 0x0035, 0x0040,
+	0x865a, 0x0d7e, 0x1078, 0x8bf4, 0x1078, 0x8a44, 0x0040, 0x8625,
+	0x6010, 0x2068, 0x6837, 0x0103, 0x6850, 0xd0b4, 0x0040, 0x8616,
+	0x684b, 0x0006, 0xc0ec, 0x6852, 0x0078, 0x8621, 0xd0bc, 0x0040,
+	0x861d, 0x684b, 0x0002, 0x0078, 0x8621, 0x684b, 0x0005, 0x1078,
+	0x8cc0, 0x6847, 0x0000, 0x1078, 0x4982, 0x2c68, 0x1078, 0x74d7,
+	0x0040, 0x863e, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, 0xa88e,
+	0x210c, 0x6136, 0x2009, 0xa88f, 0x210c, 0x613a, 0x6918, 0x611a,
+	0x6920, 0x6122, 0x601f, 0x0001, 0x1078, 0x5bf8, 0x2d60, 0x1078,
+	0x753d, 0x0d7f, 0x007c, 0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f,
+	0x0040, 0x8680, 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0035,
+	0x0040, 0x865a, 0xa186, 0x001e, 0x0040, 0x865a, 0xa186, 0x0039,
+	0x00c0, 0x8680, 0x0d7e, 0x2c68, 0x1078, 0x8ef5, 0x00c0, 0x86a4,
+	0x1078, 0x74d7, 0x0040, 0x867d, 0x6106, 0x6003, 0x0001, 0x601f,
+	0x0001, 0x6918, 0x611a, 0x6928, 0x612a, 0x692c, 0x612e, 0x6930,
+	0xa18c, 0x00ff, 0x6132, 0x6934, 0x6136, 0x6938, 0x613a, 0x6920,
+	0x6122, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x2d60, 0x0078, 0x86a4,
+	0x0d7e, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x86a4, 0x6837,
+	0x0103, 0x6850, 0xd0b4, 0x0040, 0x8693, 0xc0ec, 0x6852, 0x684b,
+	0x0006, 0x0078, 0x869e, 0xd0bc, 0x0040, 0x869a, 0x684b, 0x0002,
+	0x0078, 0x869e, 0x684b, 0x0005, 0x1078, 0x8cc0, 0x6847, 0x0000,
+	0x1078, 0x4982, 0x1078, 0x8bf4, 0x0d7f, 0x1078, 0x753d, 0x007c,
+	0x017e, 0x0d7e, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x86b8,
+	0x6837, 0x0103, 0x684b, 0x0028, 0x6847, 0x0000, 0x1078, 0x4982,
+	0x0d7f, 0x017f, 0xa186, 0x0013, 0x0040, 0x86ca, 0xa186, 0x0014,
+	0x0040, 0x86ca, 0xa186, 0x0027, 0x0040, 0x86ca, 0x1078, 0x7583,
+	0x0078, 0x86d0, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078, 0x6109,
+	0x007c, 0x057e, 0x067e, 0x0d7e, 0x0f7e, 0x2029, 0x0001, 0xa182,
+	0x0101, 0x00c8, 0x86dd, 0x0078, 0x86df, 0x2009, 0x0100, 0x2130,
+	0x2069, 0xa898, 0x831c, 0x2300, 0xad18, 0x2009, 0x0020, 0xaf90,
+	0x001d, 0x1078, 0x8739, 0xa6b2, 0x0020, 0x7804, 0xa06d, 0x0040,
+	0x86f3, 0x1078, 0x13aa, 0x1078, 0x1381, 0x0040, 0x871d, 0x8528,
+	0x6837, 0x0110, 0x683b, 0x0000, 0x2d20, 0x7c06, 0xa68a, 0x003d,
+	0x00c8, 0x8709, 0x2608, 0xad90, 0x000f, 0x1078, 0x8739, 0x0078,
+	0x871d, 0xa6b2, 0x003c, 0x2009, 0x003c, 0x2d78, 0xad90, 0x000f,
+	0x1078, 0x8739, 0x0078, 0x86f3, 0x0f7f, 0x852f, 0xa5ad, 0x0003,
+	0x7d36, 0xa5ac, 0x0000, 0x0078, 0x8722, 0x0f7f, 0x852f, 0xa5ad,
+	0x0003, 0x7d36, 0x0d7f, 0x067f, 0x057f, 0x007c, 0x0f7e, 0x8dff,
+	0x0040, 0x8737, 0x6804, 0xa07d, 0x0040, 0x8735, 0x6807, 0x0000,
+	0x1078, 0x4982, 0x2f68, 0x0078, 0x872a, 0x1078, 0x4982, 0x0f7f,
+	0x007c, 0x157e, 0xa184, 0x0001, 0x0040, 0x873f, 0x8108, 0x810c,
+	0x21a8, 0x2304, 0x8007, 0x2012, 0x8318, 0x8210, 0x00f0, 0x8741,
+	0x157f, 0x007c, 0x067e, 0x127e, 0x2091, 0x8000, 0x2031, 0x0001,
+	0x601c, 0xa084, 0x000f, 0x1079, 0x8766, 0x127f, 0x067f, 0x007c,
+	0x127e, 0x2091, 0x8000, 0x067e, 0x2031, 0x0000, 0x601c, 0xa084,
+	0x000f, 0x1079, 0x8766, 0x067f, 0x127f, 0x007c, 0x8780, 0x876e,
+	0x877b, 0x879c, 0x876e, 0x877b, 0x879c, 0x877b, 0x1078, 0x1328,
+	0x037e, 0x2019, 0x0010, 0x1078, 0x9a6a, 0x601f, 0x0006, 0x6003,
+	0x0007, 0x037f, 0x007c, 0xa006, 0x007c, 0xa085, 0x0001, 0x007c,
+	0x0d7e, 0x86ff, 0x00c0, 0x8797, 0x6010, 0x2068, 0x1078, 0x8a44,
+	0x0040, 0x8799, 0xa00e, 0x2001, 0x0005, 0x1078, 0x4a60, 0x1078,
+	0x8cc0, 0x1078, 0x4982, 0x1078, 0x753d, 0xa085, 0x0001, 0x0d7f,
+	0x007c, 0xa006, 0x0078, 0x8797, 0x6000, 0xa08a, 0x0010, 0x10c8,
+	0x1328, 0x1079, 0x87a4, 0x007c, 0x87b4, 0x87d4, 0x87b6, 0x87f7,
+	0x87d0, 0x87b4, 0x877b, 0x8780, 0x8780, 0x877b, 0x877b, 0x877b,
+	0x877b, 0x877b, 0x877b, 0x877b, 0x1078, 0x1328, 0x86ff, 0x00c0,
+	0x87cd, 0x0d7e, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x87c2,
+	0x1078, 0x8cc0, 0x0d7f, 0x6007, 0x0085, 0x6003, 0x000b, 0x601f,
+	0x0002, 0x1078, 0x5bf8, 0x1078, 0x6109, 0xa085, 0x0001, 0x007c,
+	0x1078, 0x1749, 0x0078, 0x87b6, 0x0e7e, 0x2071, 0xa5ab, 0x7024,
+	0xac06, 0x00c0, 0x87dd, 0x1078, 0x6dda, 0x601c, 0xa084, 0x000f,
+	0xa086, 0x0006, 0x00c0, 0x87ef, 0x087e, 0x097e, 0x2049, 0x0001,
+	0x2c40, 0x1078, 0x7058, 0x097f, 0x087f, 0x0078, 0x87f1, 0x1078,
+	0x6cd2, 0x0e7f, 0x00c0, 0x87b6, 0x1078, 0x877b, 0x007c, 0x037e,
+	0x0e7e, 0x2071, 0xa5ab, 0x703c, 0xac06, 0x00c0, 0x8807, 0x2019,
+	0x0000, 0x1078, 0x6e6c, 0x0e7f, 0x037f, 0x0078, 0x87b6, 0x1078,
+	0x719a, 0x0e7f, 0x037f, 0x00c0, 0x87b6, 0x1078, 0x877b, 0x007c,
+	0x0c7e, 0x601c, 0xa084, 0x000f, 0x1079, 0x8818, 0x0c7f, 0x007c,
+	0x8827, 0x8895, 0x89cd, 0x8832, 0x8c01, 0x8827, 0x9a5b, 0x753d,
+	0x8895, 0x1078, 0x8c3b, 0x00c0, 0x8827, 0x1078, 0x7a05, 0x007c,
+	0x1078, 0x6010, 0x1078, 0x6109, 0x1078, 0x753d, 0x007c, 0x6017,
+	0x0001, 0x007c, 0x6010, 0xa080, 0x0019, 0x2c02, 0x6000, 0xa08a,
+	0x0010, 0x10c8, 0x1328, 0x1079, 0x883e, 0x007c, 0x884e, 0x8850,
+	0x8872, 0x8884, 0x8891, 0x884e, 0x8827, 0x8827, 0x8827, 0x8884,
+	0x8884, 0x884e, 0x884e, 0x884e, 0x884e, 0x888e, 0x1078, 0x1328,
+	0x0e7e, 0x6010, 0x2070, 0x7050, 0xc0b5, 0x7052, 0x2071, 0xa5ab,
+	0x7024, 0xac06, 0x0040, 0x886e, 0x1078, 0x6cd2, 0x6007, 0x0085,
+	0x6003, 0x000b, 0x601f, 0x0002, 0x2001, 0xa5a1, 0x2004, 0x6016,
+	0x1078, 0x5bf8, 0x1078, 0x6109, 0x0e7f, 0x007c, 0x6017, 0x0001,
+	0x0078, 0x886c, 0x0d7e, 0x6010, 0x2068, 0x6850, 0xc0b5, 0x6852,
+	0x0d7f, 0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x1078,
+	0x5bf8, 0x1078, 0x6109, 0x007c, 0x0d7e, 0x6017, 0x0001, 0x6010,
+	0x2068, 0x6850, 0xc0b5, 0x6852, 0x0d7f, 0x007c, 0x1078, 0x753d,
+	0x007c, 0x1078, 0x1749, 0x0078, 0x8872, 0x6000, 0xa08a, 0x0010,
+	0x10c8, 0x1328, 0x1079, 0x889d, 0x007c, 0x88ad, 0x882f, 0x88af,
+	0x88ad, 0x88af, 0x88af, 0x8828, 0x88ad, 0x8821, 0x8821, 0x88ad,
+	0x88ad, 0x88ad, 0x88ad, 0x88ad, 0x88ad, 0x1078, 0x1328, 0x0d7e,
+	0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x0d7f, 0xa08a, 0x000c,
+	0x10c8, 0x1328, 0x1079, 0x88bd, 0x007c, 0x88c9, 0x8971, 0x88cb,
+	0x890b, 0x88cb, 0x890b, 0x88cb, 0x88d8, 0x88c9, 0x890b, 0x88c9,
+	0x88f5, 0x1078, 0x1328, 0x6004, 0xa08e, 0x0016, 0x0040, 0x8906,
+	0xa08e, 0x0004, 0x0040, 0x8906, 0xa08e, 0x0002, 0x0040, 0x8906,
+	0x6004, 0x1078, 0x8c3b, 0x0040, 0x898c, 0xa08e, 0x0021, 0x0040,
+	0x8990, 0xa08e, 0x0022, 0x0040, 0x898c, 0xa08e, 0x003d, 0x0040,
+	0x8990, 0xa08e, 0x0039, 0x0040, 0x8994, 0xa08e, 0x0035, 0x0040,
+	0x8994, 0xa08e, 0x001e, 0x0040, 0x8908, 0xa08e, 0x0001, 0x00c0,
+	0x8904, 0x0d7e, 0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x0d7f,
+	0xa086, 0x0006, 0x0040, 0x8906, 0x1078, 0x2813, 0x1078, 0x7a05,
+	0x1078, 0x8c01, 0x007c, 0x0c7e, 0x0d7e, 0x6104, 0xa186, 0x0016,
+	0x0040, 0x8961, 0xa186, 0x0002, 0x00c0, 0x8934, 0x6018, 0x2068,
+	0x68a0, 0xd0bc, 0x00c0, 0x89b8, 0x6840, 0xa084, 0x00ff, 0xa005,
+	0x0040, 0x8934, 0x8001, 0x6842, 0x6013, 0x0000, 0x601f, 0x0007,
+	0x6017, 0x0398, 0x1078, 0x74d7, 0x0040, 0x8934, 0x2d00, 0x601a,
+	0x601f, 0x0001, 0x0078, 0x8961, 0x0d7f, 0x0c7f, 0x6004, 0xa08e,
+	0x0002, 0x00c0, 0x8952, 0x6018, 0xa080, 0x0028, 0x2004, 0xa086,
+	0x007e, 0x00c0, 0x8952, 0x2009, 0xa332, 0x2104, 0xc085, 0x200a,
+	0x0e7e, 0x2071, 0xa300, 0x1078, 0x41f5, 0x0e7f, 0x1078, 0x7a05,
+	0x0078, 0x8956, 0x1078, 0x7a05, 0x1078, 0x2813, 0x0e7e, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x2839, 0x127f, 0x0e7f, 0x1078, 0x8c01,
+	0x007c, 0x2001, 0x0002, 0x1078, 0x443f, 0x6003, 0x0001, 0x6007,
+	0x0002, 0x1078, 0x5c45, 0x1078, 0x6109, 0x0d7f, 0x0c7f, 0x0078,
+	0x8960, 0x0c7e, 0x0d7e, 0x6104, 0xa186, 0x0016, 0x0040, 0x8961,
+	0x6018, 0x2068, 0x6840, 0xa084, 0x00ff, 0xa005, 0x0040, 0x8934,
+	0x8001, 0x6842, 0x6003, 0x0001, 0x1078, 0x5c45, 0x1078, 0x6109,
+	0x0d7f, 0x0c7f, 0x0078, 0x8960, 0x1078, 0x7a05, 0x0078, 0x8908,
+	0x1078, 0x7a28, 0x0078, 0x8908, 0x0d7e, 0x2c68, 0x6104, 0x1078,
+	0x8ef5, 0x0d7f, 0x0040, 0x89a0, 0x1078, 0x753d, 0x0078, 0x89b7,
+	0x6004, 0x8007, 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032, 0x6007,
+	0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x6038, 0x600a, 0x2001,
+	0xa5a1, 0x2004, 0x6016, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x007c,
+	0x0d7f, 0x0c7f, 0x1078, 0x7a05, 0x1078, 0x2813, 0x0e7e, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x2839, 0x6013, 0x0000, 0x601f, 0x0007,
+	0x6017, 0x0398, 0x127f, 0x0e7f, 0x007c, 0x6000, 0xa08a, 0x0010,
+	0x10c8, 0x1328, 0x1079, 0x89d5, 0x007c, 0x89e5, 0x89e5, 0x89e5,
+	0x89e5, 0x89e5, 0x89e5, 0x89e5, 0x89e5, 0x89e5, 0x8827, 0x89e5,
+	0x882f, 0x89e7, 0x882f, 0x89f5, 0x89e5, 0x1078, 0x1328, 0x6004,
+	0xa086, 0x008b, 0x0040, 0x89f5, 0x6007, 0x008b, 0x6003, 0x000d,
+	0x1078, 0x5bf8, 0x1078, 0x6109, 0x007c, 0x1078, 0x8bf4, 0x1078,
+	0x8a44, 0x0040, 0x8a2d, 0x1078, 0x2813, 0x0d7e, 0x1078, 0x8a44,
+	0x0040, 0x8a0f, 0x6010, 0x2068, 0x6837, 0x0103, 0x684b, 0x0006,
+	0x6847, 0x0000, 0x6850, 0xc0ed, 0x6852, 0x1078, 0x4982, 0x2c68,
+	0x1078, 0x74d7, 0x0040, 0x8a1d, 0x6818, 0x601a, 0x0c7e, 0x2d60,
+	0x1078, 0x8c01, 0x0c7f, 0x0078, 0x8a1e, 0x2d60, 0x0d7f, 0x6013,
+	0x0000, 0x601f, 0x0001, 0x6007, 0x0001, 0x6003, 0x0001, 0x1078,
+	0x5c45, 0x1078, 0x6109, 0x0078, 0x8a2f, 0x1078, 0x8c01, 0x007c,
+	0xa284, 0x000f, 0x00c0, 0x8a41, 0xa282, 0xaa00, 0x0048, 0x8a41,
+	0x2001, 0xa315, 0x2004, 0xa202, 0x00c8, 0x8a41, 0xa085, 0x0001,
+	0x007c, 0xa006, 0x0078, 0x8a40, 0x027e, 0x0e7e, 0x2071, 0xa300,
+	0x6210, 0x7058, 0xa202, 0x0048, 0x8a56, 0x705c, 0xa202, 0x00c8,
+	0x8a56, 0xa085, 0x0001, 0x0e7f, 0x027f, 0x007c, 0xa006, 0x0078,
+	0x8a53, 0x0e7e, 0x0c7e, 0x037e, 0x007e, 0x127e, 0x2091, 0x8000,
+	0x2061, 0xaa00, 0x2071, 0xa300, 0x7344, 0x7060, 0xa302, 0x00c8,
+	0x8a83, 0x601c, 0xa206, 0x00c0, 0x8a7b, 0x1078, 0x8d66, 0x0040,
+	0x8a7b, 0x1078, 0x8c3b, 0x00c0, 0x8a77, 0x1078, 0x7a05, 0x0c7e,
+	0x1078, 0x753d, 0x0c7f, 0xace0, 0x0010, 0x7054, 0xac02, 0x00c8,
+	0x8a83, 0x0078, 0x8a64, 0x127f, 0x007f, 0x037f, 0x0c7f, 0x0e7f,
+	0x007c, 0x0e7e, 0x0c7e, 0x017e, 0xa188, 0xa434, 0x210c, 0x81ff,
+	0x0040, 0x8aa1, 0x2061, 0xaa00, 0x2071, 0xa300, 0x017e, 0x1078,
+	0x74d7, 0x017f, 0x0040, 0x8aa4, 0x611a, 0x1078, 0x2813, 0x1078,
+	0x753d, 0xa006, 0x0078, 0x8aa6, 0xa085, 0x0001, 0x017f, 0x0c7f,
+	0x0e7f, 0x007c, 0x0c7e, 0x057e, 0x127e, 0x2091, 0x8000, 0x0c7e,
+	0x1078, 0x74d7, 0x057f, 0x0040, 0x8ac3, 0x6612, 0x651a, 0x601f,
+	0x0003, 0x2009, 0x004b, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f,
+	0x057f, 0x0c7f, 0x007c, 0xa006, 0x0078, 0x8abf, 0x0c7e, 0x057e,
+	0x127e, 0x2091, 0x8000, 0x62a0, 0x0c7e, 0x1078, 0x74d7, 0x057f,
+	0x0040, 0x8af1, 0x6013, 0x0000, 0x651a, 0x601f, 0x0003, 0x0c7e,
+	0x2560, 0x1078, 0x471b, 0x0c7f, 0x1078, 0x5d53, 0x077e, 0x2039,
+	0x0000, 0x1078, 0x5c78, 0x2c08, 0x1078, 0x9c38, 0x077f, 0x2009,
+	0x004c, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f, 0x057f, 0x0c7f,
+	0x007c, 0xa006, 0x0078, 0x8aed, 0x0f7e, 0x0c7e, 0x047e, 0x0c7e,
+	0x1078, 0x74d7, 0x2c78, 0x0c7f, 0x0040, 0x8b0e, 0x7e12, 0x2c00,
+	0x781a, 0x781f, 0x0003, 0x2021, 0x0005, 0x1078, 0x8b4e, 0x2f60,
+	0x2009, 0x004d, 0x1078, 0x756c, 0xa085, 0x0001, 0x047f, 0x0c7f,
+	0x0f7f, 0x007c, 0x0f7e, 0x0c7e, 0x047e, 0x0c7e, 0x1078, 0x74d7,
+	0x2c78, 0x0c7f, 0x0040, 0x8b2c, 0x7e12, 0x2c00, 0x781a, 0x781f,
+	0x0003, 0x2021, 0x0005, 0x1078, 0x8b4e, 0x2f60, 0x2009, 0x004e,
+	0x1078, 0x756c, 0xa085, 0x0001, 0x047f, 0x0c7f, 0x0f7f, 0x007c,
+	0x0f7e, 0x0c7e, 0x047e, 0x0c7e, 0x1078, 0x74d7, 0x2c78, 0x0c7f,
+	0x0040, 0x8b4a, 0x7e12, 0x2c00, 0x781a, 0x781f, 0x0003, 0x2021,
+	0x0004, 0x1078, 0x8b4e, 0x2f60, 0x2009, 0x0052, 0x1078, 0x756c,
+	0xa085, 0x0001, 0x047f, 0x0c7f, 0x0f7f, 0x007c, 0x097e, 0x077e,
+	0x127e, 0x2091, 0x8000, 0x1078, 0x46a7, 0x0040, 0x8b5b, 0x2001,
+	0x8b53, 0x0078, 0x8b61, 0x1078, 0x466d, 0x0040, 0x8b6a, 0x2001,
+	0x8b5b, 0x007e, 0xa00e, 0x2400, 0x1078, 0x4a60, 0x1078, 0x4982,
+	0x007f, 0x007a, 0x2418, 0x1078, 0x5fa7, 0x62a0, 0x087e, 0x2041,
+	0x0001, 0x2039, 0x0001, 0x2608, 0x1078, 0x5d6d, 0x087f, 0x1078,
+	0x5c78, 0x2f08, 0x2648, 0x1078, 0x9c38, 0x613c, 0x81ff, 0x1040,
+	0x5e21, 0x127f, 0x077f, 0x097f, 0x007c, 0x0c7e, 0x127e, 0x2091,
+	0x8000, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040, 0x8b9e, 0x660a,
+	0x611a, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x001f, 0x1078,
+	0x756c, 0xa085, 0x0001, 0x127f, 0x0c7f, 0x007c, 0xa006, 0x0078,
+	0x8b9b, 0x0c7e, 0x127e, 0x2091, 0x8000, 0x0c7e, 0x1078, 0x74d7,
+	0x017f, 0x0040, 0x8bba, 0x660a, 0x611a, 0x601f, 0x0008, 0x2d00,
+	0x6012, 0x2009, 0x0021, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f,
+	0x0c7f, 0x007c, 0xa006, 0x0078, 0x8bb7, 0x0c7e, 0x127e, 0x2091,
+	0x8000, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040, 0x8bd6, 0x660a,
+	0x611a, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x003d, 0x1078,
+	0x756c, 0xa085, 0x0001, 0x127f, 0x0c7f, 0x007c, 0xa006, 0x0078,
+	0x8bd3, 0x0c7e, 0x127e, 0x2091, 0x8000, 0x0c7e, 0x1078, 0x74d7,
+	0x017f, 0x0040, 0x8bf1, 0x611a, 0x601f, 0x0001, 0x2d00, 0x6012,
+	0x2009, 0x0000, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f, 0x0c7f,
+	0x007c, 0xa006, 0x0078, 0x8bee, 0x027e, 0x0d7e, 0x6218, 0x2268,
+	0x6a3c, 0x82ff, 0x0040, 0x8bfe, 0x8211, 0x6a3e, 0x0d7f, 0x027f,
+	0x007c, 0x007e, 0x6000, 0xa086, 0x0000, 0x0040, 0x8c13, 0x6013,
+	0x0000, 0x601f, 0x0007, 0x2001, 0xa5a1, 0x2004, 0x6016, 0x1078,
+	0xa134, 0x603f, 0x0000, 0x007f, 0x007c, 0x067e, 0x0c7e, 0x0d7e,
+	0x2031, 0xa352, 0x2634, 0xd6e4, 0x0040, 0x8c23, 0x6618, 0x2660,
+	0x6e48, 0x1078, 0x461b, 0x0d7f, 0x0c7f, 0x067f, 0x007c, 0x007e,
+	0x017e, 0x6004, 0xa08e, 0x0002, 0x0040, 0x8c38, 0xa08e, 0x0003,
+	0x0040, 0x8c38, 0xa08e, 0x0004, 0x0040, 0x8c38, 0xa085, 0x0001,
+	0x017f, 0x007f, 0x007c, 0x007e, 0x0d7e, 0x6010, 0xa06d, 0x0040,
+	0x8c48, 0x6838, 0xd0fc, 0x0040, 0x8c48, 0xa006, 0x0078, 0x8c4a,
+	0xa085, 0x0001, 0x0d7f, 0x007f, 0x007c, 0x0c7e, 0x127e, 0x2091,
+	0x8000, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040, 0x8c67, 0x611a,
+	0x601f, 0x0001, 0x2d00, 0x6012, 0x1078, 0x2813, 0x2009, 0x0028,
+	0x1078, 0x756c, 0xa085, 0x0001, 0x127f, 0x0c7f, 0x007c, 0xa006,
+	0x0078, 0x8c64, 0xa186, 0x0015, 0x00c0, 0x8c7f, 0x2011, 0xa31f,
+	0x2204, 0xa086, 0x0074, 0x00c0, 0x8c7f, 0x1078, 0x7d0d, 0x6003,
+	0x0001, 0x6007, 0x0029, 0x1078, 0x5c45, 0x0078, 0x8c83, 0x1078,
+	0x7a05, 0x1078, 0x753d, 0x007c, 0xa186, 0x0016, 0x00c0, 0x8c8e,
+	0x2001, 0x0004, 0x1078, 0x443f, 0x0078, 0x8caf, 0xa186, 0x0015,
+	0x00c0, 0x8cb3, 0x2011, 0xa31f, 0x2204, 0xa086, 0x0014, 0x00c0,
+	0x8cb3, 0x0d7e, 0x6018, 0x2068, 0x1078, 0x457d, 0x0d7f, 0x1078,
+	0x7dba, 0x00c0, 0x8cb3, 0x0d7e, 0x6018, 0x2068, 0x6890, 0x0d7f,
+	0xa005, 0x0040, 0x8cb3, 0x2001, 0x0006, 0x1078, 0x443f, 0x1078,
+	0x7608, 0x0078, 0x8cb7, 0x1078, 0x7a05, 0x1078, 0x753d, 0x007c,
+	0x6848, 0xa086, 0x0005, 0x00c0, 0x8cbf, 0x1078, 0x8cc0, 0x007c,
+	0x6850, 0xc0ad, 0x6852, 0x007c, 0x0e7e, 0x2071, 0xa88c, 0x7014,
+	0xd0e4, 0x0040, 0x8cd5, 0x6013, 0x0000, 0x6003, 0x0001, 0x6007,
+	0x0050, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0e7f, 0x007c, 0x0c7e,
+	0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f, 0x0040, 0x8ce4, 0x601c,
+	0xa084, 0x000f, 0x1079, 0x8ce6, 0x0c7f, 0x007c, 0x8827, 0x8cf1,
+	0x8cf4, 0x8cf7, 0x9f00, 0x9f1c, 0x9f1f, 0x8827, 0x8827, 0x1078,
+	0x1328, 0x0005, 0x0005, 0x007c, 0x0005, 0x0005, 0x007c, 0x1078,
+	0x8cfa, 0x007c, 0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0040, 0x8d29,
+	0x1078, 0x74d7, 0x00c0, 0x8d0a, 0x2001, 0xa5a2, 0x2004, 0x783e,
+	0x0078, 0x8d29, 0x7818, 0x601a, 0x781c, 0xa086, 0x0003, 0x0040,
+	0x8d17, 0x7808, 0x6036, 0x2f00, 0x603a, 0x0078, 0x8d1b, 0x7808,
+	0x603a, 0x2f00, 0x6036, 0x602a, 0x601f, 0x0001, 0x6007, 0x0035,
+	0x6003, 0x0001, 0x7920, 0x6122, 0x1078, 0x5bf8, 0x1078, 0x6109,
+	0x2f60, 0x0f7f, 0x007c, 0x017e, 0x0f7e, 0x682c, 0x6032, 0xa08e,
+	0x0001, 0x0040, 0x8d3c, 0xa086, 0x0005, 0x0040, 0x8d40, 0xa006,
+	0x602a, 0x602e, 0x0078, 0x8d51, 0x6824, 0xc0f4, 0xc0d5, 0x6826,
+	0x6810, 0x2078, 0x787c, 0x6938, 0xa102, 0x7880, 0x6934, 0xa103,
+	0x00c8, 0x8d37, 0x6834, 0x602a, 0x6838, 0xa084, 0xfffc, 0x683a,
+	0x602e, 0x2d00, 0x6036, 0x6808, 0x603a, 0x6918, 0x611a, 0x6920,
+	0x6122, 0x601f, 0x0001, 0x6007, 0x0039, 0x6003, 0x0001, 0x1078,
+	0x5bf8, 0x6803, 0x0002, 0x0f7f, 0x017f, 0x007c, 0x007e, 0x017e,
+	0x6004, 0xa08e, 0x0034, 0x0040, 0x8d8b, 0xa08e, 0x0035, 0x0040,
+	0x8d8b, 0xa08e, 0x0036, 0x0040, 0x8d8b, 0xa08e, 0x0037, 0x0040,
+	0x8d8b, 0xa08e, 0x0038, 0x0040, 0x8d8b, 0xa08e, 0x0039, 0x0040,
+	0x8d8b, 0xa08e, 0x003a, 0x0040, 0x8d8b, 0xa08e, 0x003b, 0x0040,
+	0x8d8b, 0xa085, 0x0001, 0x017f, 0x007f, 0x007c, 0x0f7e, 0x2c78,
+	0x1078, 0x4893, 0x00c0, 0x8d98, 0xa085, 0x0001, 0x0078, 0x8da7,
+	0x6024, 0xd0f4, 0x00c0, 0x8da6, 0xc0f5, 0x6026, 0x6010, 0x2078,
+	0x7828, 0x603a, 0x782c, 0x6036, 0x1078, 0x1749, 0xa006, 0x0f7f,
+	0x007c, 0x007e, 0x017e, 0x027e, 0x037e, 0x0e7e, 0x2001, 0xa59c,
+	0x200c, 0x8000, 0x2014, 0x2001, 0x0032, 0x1078, 0x5a98, 0x2001,
+	0xa5a0, 0x82ff, 0x00c0, 0x8dbe, 0x2011, 0x0002, 0x2202, 0x2001,
+	0xa59e, 0x200c, 0x8000, 0x2014, 0x2071, 0xa58c, 0x711a, 0x721e,
+	0x2001, 0x0064, 0x1078, 0x5a98, 0x2001, 0xa5a1, 0x82ff, 0x00c0,
+	0x8dd3, 0x2011, 0x0002, 0x2202, 0x2009, 0xa5a2, 0xa280, 0x000a,
+	0x200a, 0x0e7f, 0x037f, 0x027f, 0x017f, 0x007f, 0x007c, 0x007e,
+	0x0e7e, 0x2001, 0xa5a0, 0x2003, 0x0028, 0x2001, 0xa5a1, 0x2003,
+	0x0014, 0x2071, 0xa58c, 0x701b, 0x0000, 0x701f, 0x07d0, 0x2001,
+	0xa5a2, 0x2003, 0x001e, 0x0e7f, 0x007f, 0x007c, 0x0c7e, 0x127e,
+	0x2091, 0x8000, 0x0c7e, 0x1078, 0x74d7, 0x017f, 0x0040, 0x8e0e,
+	0x611a, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x0033, 0x1078,
+	0x756c, 0xa085, 0x0001, 0x127f, 0x0c7f, 0x007c, 0xa006, 0x0078,
+	0x8e0b, 0x0d7e, 0x0e7e, 0x0f7e, 0x2071, 0xa300, 0xa186, 0x0015,
+	0x00c0, 0x8e40, 0x707c, 0xa086, 0x0018, 0x00c0, 0x8e40, 0x6010,
+	0x2068, 0x6a3c, 0xd2e4, 0x00c0, 0x8e34, 0x2c78, 0x1078, 0x62c6,
+	0x0040, 0x8e48, 0x7068, 0x6a50, 0xa206, 0x00c0, 0x8e3c, 0x706c,
+	0x6a54, 0xa206, 0x00c0, 0x8e3c, 0x6218, 0xa290, 0x0028, 0x2214,
+	0x2009, 0x0000, 0x1078, 0x285b, 0x1078, 0x7608, 0x0078, 0x8e44,
+	0x1078, 0x7a05, 0x1078, 0x753d, 0x0f7f, 0x0e7f, 0x0d7f, 0x007c,
+	0x704c, 0xa080, 0x293f, 0x2004, 0x6a54, 0xa206, 0x0040, 0x8e34,
+	0x0078, 0x8e3c, 0x0c7e, 0x127e, 0x2091, 0x8000, 0x0c7e, 0x1078,
+	0x74d7, 0x017f, 0x0040, 0x8e6a, 0x611a, 0x601f, 0x0001, 0x2d00,
+	0x6012, 0x2009, 0x0043, 0x1078, 0x756c, 0xa085, 0x0001, 0x127f,
+	0x0c7f, 0x007c, 0xa006, 0x0078, 0x8e67, 0x0d7e, 0x0e7e, 0x0f7e,
+	0x2071, 0xa300, 0xa186, 0x0015, 0x00c0, 0x8e93, 0x707c, 0xa086,
+	0x0004, 0x00c0, 0x8e93, 0x6010, 0xa0e8, 0x000f, 0x2c78, 0x1078,
+	0x62c6, 0x0040, 0x8e9b, 0x7068, 0x6a08, 0xa206, 0x00c0, 0x8e8f,
+	0x706c, 0x6a0c, 0xa206, 0x00c0, 0x8e8f, 0x1078, 0x2813, 0x1078,
+	0x7608, 0x0078, 0x8e97, 0x1078, 0x7a05, 0x1078, 0x753d, 0x0f7f,
+	0x0e7f, 0x0d7f, 0x007c, 0x704c, 0xa080, 0x293f, 0x2004, 0x6a0c,
+	0xa206, 0x0040, 0x8e8d, 0x0078, 0x8e8f, 0x017e, 0x027e, 0x684c,
+	0xd0ac, 0x0040, 0x8ebd, 0x6914, 0x6a10, 0x2100, 0xa205, 0x0040,
+	0x8ebd, 0x6860, 0xa106, 0x00c0, 0x8eb9, 0x685c, 0xa206, 0x0040,
+	0x8ebd, 0x6962, 0x6a5e, 0xa085, 0x0001, 0x027f, 0x017f, 0x007c,
+	0x0e7e, 0x127e, 0x2071, 0xa300, 0x2091, 0x8000, 0x7544, 0xa582,
+	0x0001, 0x0048, 0x8ef2, 0x7048, 0x2060, 0x6000, 0xa086, 0x0000,
+	0x0040, 0x8ede, 0xace0, 0x0010, 0x7054, 0xac02, 0x00c8, 0x8eda,
+	0x0078, 0x8ecd, 0x2061, 0xaa00, 0x0078, 0x8ecd, 0x6003, 0x0008,
+	0x8529, 0x7546, 0xaca8, 0x0010, 0x7054, 0xa502, 0x00c8, 0x8eee,
+	0x754a, 0xa085, 0x0001, 0x127f, 0x0e7f, 0x007c, 0x704b, 0xaa00,
+	0x0078, 0x8ee9, 0xa006, 0x0078, 0x8eeb, 0x0c7e, 0x027e, 0x017e,
+	0xa186, 0x0035, 0x0040, 0x8eff, 0x6a34, 0x0078, 0x8f00, 0x6a28,
+	0x1078, 0x8a30, 0x0040, 0x8f29, 0x2260, 0x611c, 0xa186, 0x0003,
+	0x0040, 0x8f0e, 0xa186, 0x0006, 0x00c0, 0x8f25, 0x6834, 0xa206,
+	0x0040, 0x8f1d, 0x6838, 0xa206, 0x00c0, 0x8f25, 0x6108, 0x6834,
+	0xa106, 0x00c0, 0x8f25, 0x0078, 0x8f22, 0x6008, 0x6938, 0xa106,
+	0x00c0, 0x8f25, 0x6018, 0x6918, 0xa106, 0x017f, 0x027f, 0x0c7f,
+	0x007c, 0xa085, 0x0001, 0x0078, 0x8f25, 0x067e, 0x6000, 0xa0b2,
+	0x0010, 0x10c8, 0x1328, 0x1079, 0x8f37, 0x067f, 0x007c, 0x8f47,
+	0x93bb, 0x94d3, 0x8f47, 0x8f47, 0x8f47, 0x8f47, 0x8f47, 0x8f81,
+	0x955e, 0x8f47, 0x8f47, 0x8f47, 0x8f47, 0x8f47, 0x8f47, 0x1078,
+	0x1328, 0x067e, 0x6000, 0xa0b2, 0x0010, 0x10c8, 0x1328, 0x1079,
+	0x8f53, 0x067f, 0x007c, 0x8f63, 0x99f6, 0x8f63, 0x8f63, 0x8f63,
+	0x8f63, 0x8f63, 0x8f63, 0x99b4, 0x9a44, 0x8f63, 0xa053, 0xa087,
+	0xa053, 0xa087, 0x8f63, 0x1078, 0x1328, 0x067e, 0x6000, 0xa0b2,
+	0x0010, 0x10c8, 0x1328, 0x1079, 0x8f6f, 0x067f, 0x007c, 0x8f7f,
+	0x969f, 0x976a, 0x9798, 0x9813, 0x8f7f, 0x9919, 0x98c1, 0x956a,
+	0x9988, 0x999e, 0x8f7f, 0x8f7f, 0x8f7f, 0x8f7f, 0x8f7f, 0x1078,
+	0x1328, 0xa1b2, 0x0044, 0x10c8, 0x1328, 0x2100, 0x0079, 0x8f88,
+	0x8fc8, 0x919a, 0x8fc8, 0x8fc8, 0x8fc8, 0x91a2, 0x8fc8, 0x8fc8,
+	0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8,
+	0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fca,
+	0x902d, 0x9038, 0x9081, 0x909c, 0x911b, 0x918b, 0x8fc8, 0x8fc8,
+	0x91a6, 0x8fc8, 0x8fc8, 0x91b5, 0x91bc, 0x8fc8, 0x8fc8, 0x8fc8,
+	0x8fc8, 0x8fc8, 0x91ea, 0x8fc8, 0x8fc8, 0x91f5, 0x8fc8, 0x8fc8,
+	0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x920a, 0x8fc8, 0x8fc8, 0x8fc8,
+	0x9291, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x8fc8, 0x9305,
+	0x1078, 0x1328, 0x1078, 0x4897, 0x00c0, 0x8fd7, 0x2001, 0xa332,
+	0x2004, 0xa084, 0x0009, 0xa086, 0x0008, 0x00c0, 0x8fdf, 0x6007,
+	0x0009, 0x602b, 0x0009, 0x6013, 0x0000, 0x0078, 0x9195, 0x1078,
+	0x4887, 0x0e7e, 0x0c7e, 0x037e, 0x027e, 0x017e, 0x6218, 0x2270,
+	0x72a0, 0x027e, 0x2019, 0x0029, 0x1078, 0x5d53, 0x077e, 0x2039,
+	0x0000, 0x1078, 0x5c78, 0x2c08, 0x1078, 0x9c38, 0x077f, 0x017f,
+	0x2e60, 0x1078, 0x471b, 0x017f, 0x027f, 0x037f, 0x0c7f, 0x0e7f,
+	0x6618, 0x0c7e, 0x2660, 0x1078, 0x4513, 0x0c7f, 0xa6b0, 0x0001,
+	0x2634, 0xa684, 0x00ff, 0xa082, 0x0006, 0x0048, 0x901f, 0x1078,
+	0x9b6c, 0x00c0, 0x907b, 0x1078, 0x9afd, 0x00c0, 0x901b, 0x6007,
+	0x0008, 0x0078, 0x9195, 0x6007, 0x0009, 0x0078, 0x9195, 0x1078,
+	0x9d45, 0x0040, 0x9029, 0x1078, 0x9b6c, 0x0040, 0x9013, 0x0078,
+	0x907b, 0x6013, 0x1900, 0x0078, 0x901b, 0x6106, 0x1078, 0x9aa8,
+	0x6007, 0x0006, 0x0078, 0x9195, 0x6007, 0x0007, 0x0078, 0x9195,
+	0x1078, 0xa0bf, 0x00c0, 0x9340, 0x0d7e, 0x6618, 0x2668, 0x6e04,
+	0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0040, 0x905d, 0xa686,
+	0x0004, 0x0040, 0x905d, 0x6e04, 0xa6b4, 0x00ff, 0xa686, 0x0006,
+	0x0040, 0x905d, 0xa686, 0x0004, 0x0040, 0x905d, 0xa686, 0x0005,
+	0x0040, 0x905d, 0x0d7f, 0x0078, 0x907b, 0x1078, 0x9bd2, 0x00c0,
+	0x9076, 0xa686, 0x0006, 0x00c0, 0x906f, 0x027e, 0x6218, 0xa290,
+	0x0028, 0x2214, 0x2009, 0x0000, 0x1078, 0x285b, 0x027f, 0x1078,
+	0x457d, 0x6007, 0x000a, 0x0d7f, 0x0078, 0x9195, 0x6007, 0x000b,
+	0x0d7f, 0x0078, 0x9195, 0x1078, 0x2813, 0x6007, 0x0001, 0x0078,
+	0x9195, 0x1078, 0xa0bf, 0x00c0, 0x9340, 0x6618, 0x0d7e, 0x2668,
+	0x6e04, 0x0d7f, 0xa686, 0x0707, 0x0040, 0x907b, 0x027e, 0x6218,
+	0xa290, 0x0028, 0x2214, 0x2009, 0x0000, 0x1078, 0x285b, 0x027f,
+	0x6007, 0x000c, 0x0078, 0x9195, 0x1078, 0x4897, 0x00c0, 0x90a9,
+	0x2001, 0xa332, 0x2004, 0xa084, 0x0009, 0xa086, 0x0008, 0x00c0,
+	0x90b1, 0x6007, 0x0009, 0x602b, 0x0009, 0x6013, 0x0000, 0x0078,
+	0x9195, 0x1078, 0x4887, 0x6618, 0xa6b0, 0x0001, 0x2634, 0xa684,
+	0x00ff, 0xa082, 0x0006, 0x0048, 0x90f5, 0xa6b4, 0xff00, 0x8637,
+	0xa686, 0x0004, 0x0040, 0x90c8, 0xa686, 0x0006, 0x00c0, 0x907b,
+	0x1078, 0x9be1, 0x00c0, 0x90d0, 0x6007, 0x000e, 0x0078, 0x9195,
+	0x047e, 0x6418, 0xa4a0, 0x0028, 0x2424, 0xa4a4, 0x00ff, 0x8427,
+	0x047e, 0x1078, 0x2813, 0x047f, 0x017e, 0xa006, 0x2009, 0xa352,
+	0x210c, 0xd1a4, 0x0040, 0x90ef, 0x2009, 0x0029, 0x1078, 0x9ec0,
+	0x6018, 0x0d7e, 0x2068, 0x6800, 0xc0e5, 0x6802, 0x0d7f, 0x017f,
+	0x047f, 0x6007, 0x0001, 0x0078, 0x9195, 0x2001, 0x0001, 0x1078,
+	0x442b, 0x157e, 0x017e, 0x027e, 0x037e, 0x20a9, 0x0004, 0x2019,
+	0xa305, 0x2011, 0xa890, 0x1078, 0x7e55, 0x037f, 0x027f, 0x017f,
+	0x157f, 0xa005, 0x0040, 0x9115, 0xa6b4, 0xff00, 0x8637, 0xa686,
+	0x0006, 0x0040, 0x90c8, 0x0078, 0x907b, 0x6013, 0x1900, 0x6007,
+	0x0009, 0x0078, 0x9195, 0x1078, 0x4897, 0x00c0, 0x9128, 0x2001,
+	0xa332, 0x2004, 0xa084, 0x0009, 0xa086, 0x0008, 0x00c0, 0x9130,
+	0x6007, 0x0009, 0x602b, 0x0009, 0x6013, 0x0000, 0x0078, 0x9195,
+	0x1078, 0x4887, 0x6618, 0xa6b0, 0x0001, 0x2634, 0xa684, 0x00ff,
+	0xa082, 0x0006, 0x0048, 0x9178, 0xa6b4, 0xff00, 0x8637, 0xa686,
+	0x0004, 0x0040, 0x9147, 0xa686, 0x0006, 0x00c0, 0x907b, 0x1078,
+	0x9c0c, 0x00c0, 0x9153, 0x1078, 0x9afd, 0x00c0, 0x9153, 0x6007,
+	0x0010, 0x0078, 0x9195, 0x047e, 0x6418, 0xa4a0, 0x0028, 0x2424,
+	0xa4a4, 0x00ff, 0x8427, 0x047e, 0x1078, 0x2813, 0x047f, 0x017e,
+	0xa006, 0x2009, 0xa352, 0x210c, 0xd1a4, 0x0040, 0x9172, 0x2009,
+	0x0029, 0x1078, 0x9ec0, 0x6018, 0x0d7e, 0x2068, 0x6800, 0xc0e5,
+	0x6802, 0x0d7f, 0x017f, 0x047f, 0x6007, 0x0001, 0x0078, 0x9195,
+	0x1078, 0x9d45, 0x0040, 0x9185, 0xa6b4, 0xff00, 0x8637, 0xa686,
+	0x0006, 0x0040, 0x9147, 0x0078, 0x907b, 0x6013, 0x1900, 0x6007,
+	0x0009, 0x0078, 0x9195, 0x1078, 0xa0bf, 0x00c0, 0x9340, 0x1078,
+	0x9343, 0x00c0, 0x907b, 0x6007, 0x0012, 0x6003, 0x0001, 0x1078,
+	0x5c45, 0x007c, 0x6007, 0x0001, 0x6003, 0x0001, 0x1078, 0x5c45,
+	0x0078, 0x9199, 0x6007, 0x0005, 0x0078, 0x919c, 0x1078, 0xa0bf,
+	0x00c0, 0x9340, 0x1078, 0x9343, 0x00c0, 0x907b, 0x6007, 0x0020,
+	0x6003, 0x0001, 0x1078, 0x5c45, 0x007c, 0x6007, 0x0023, 0x6003,
+	0x0001, 0x1078, 0x5c45, 0x007c, 0x1078, 0xa0bf, 0x00c0, 0x9340,
+	0x1078, 0x9343, 0x00c0, 0x907b, 0x017e, 0x027e, 0x2011, 0xa890,
+	0x2214, 0x2c08, 0x1078, 0x9e8c, 0x00c0, 0x91de, 0x2160, 0x6007,
+	0x0026, 0x6013, 0x1700, 0x2011, 0xa889, 0x2214, 0xa296, 0xffff,
+	0x00c0, 0x91e3, 0x6007, 0x0025, 0x0078, 0x91e3, 0x1078, 0x753d,
+	0x2160, 0x6007, 0x0025, 0x6003, 0x0001, 0x1078, 0x5c45, 0x027f,
+	0x017f, 0x007c, 0x6106, 0x1078, 0x9363, 0x6007, 0x002b, 0x0078,
+	0x9195, 0x6007, 0x002c, 0x0078, 0x9195, 0x1078, 0xa0bf, 0x00c0,
+	0x9340, 0x1078, 0x9343, 0x00c0, 0x907b, 0x6106, 0x1078, 0x9368,
+	0x00c0, 0x9206, 0x6007, 0x002e, 0x0078, 0x9195, 0x6007, 0x002f,
+	0x0078, 0x9195, 0x0e7e, 0x0d7e, 0x0c7e, 0x6018, 0xa080, 0x0001,
+	0x200c, 0xa184, 0x00ff, 0xa086, 0x0006, 0x0040, 0x9223, 0xa184,
+	0xff00, 0x8007, 0xa086, 0x0006, 0x0040, 0x9223, 0x0c7f, 0x0d7f,
+	0x0e7f, 0x0078, 0x919a, 0x2001, 0xa371, 0x2004, 0xd0e4, 0x0040,
+	0x928d, 0x2071, 0xa88c, 0x7010, 0x6036, 0x7014, 0x603a, 0x7108,
+	0x720c, 0x2001, 0xa352, 0x2004, 0xd0a4, 0x0040, 0x9241, 0x6018,
+	0x2068, 0x6810, 0xa106, 0x00c0, 0x9241, 0x6814, 0xa206, 0x0040,
+	0x9265, 0x2001, 0xa352, 0x2004, 0xd0ac, 0x00c0, 0x9281, 0x2069,
+	0xa300, 0x686c, 0xa206, 0x00c0, 0x9281, 0x6868, 0xa106, 0x00c0,
+	0x9281, 0x7210, 0x1078, 0x8a30, 0x0040, 0x9287, 0x1078, 0x9f31,
+	0x0040, 0x9287, 0x622a, 0x6007, 0x0036, 0x6003, 0x0001, 0x1078,
+	0x5bf8, 0x0c7f, 0x0d7f, 0x0e7f, 0x007c, 0x7214, 0xa286, 0xffff,
+	0x0040, 0x9277, 0x1078, 0x8a30, 0x0040, 0x9287, 0xa280, 0x0002,
+	0x2004, 0x7110, 0xa106, 0x00c0, 0x9287, 0x0078, 0x9252, 0x7210,
+	0x2c08, 0x1078, 0x9e8c, 0x2c10, 0x2160, 0x0040, 0x9287, 0x0078,
+	0x9252, 0x6007, 0x0037, 0x6013, 0x1500, 0x0078, 0x925d, 0x6007,
+	0x0037, 0x6013, 0x1700, 0x0078, 0x925d, 0x6007, 0x0012, 0x0078,
+	0x925d, 0x6018, 0xa080, 0x0001, 0x2004, 0xa084, 0xff00, 0x8007,
+	0xa086, 0x0006, 0x00c0, 0x919a, 0x0e7e, 0x0d7e, 0x0c7e, 0x2001,
+	0xa371, 0x2004, 0xd0e4, 0x0040, 0x92fd, 0x2069, 0xa300, 0x2071,
+	0xa88c, 0x7008, 0x6036, 0x720c, 0x623a, 0xa286, 0xffff, 0x00c0,
+	0x92ba, 0x7208, 0x0c7e, 0x2c08, 0x1078, 0x9e8c, 0x2c10, 0x0c7f,
+	0x0040, 0x92f1, 0x1078, 0x8a30, 0x0040, 0x92f1, 0x0c7e, 0x027e,
+	0x2260, 0x1078, 0x874a, 0x027f, 0x0c7f, 0x7118, 0xa18c, 0xff00,
+	0x810f, 0xa186, 0x0001, 0x0040, 0x92db, 0xa186, 0x0005, 0x0040,
+	0x92d5, 0xa186, 0x0007, 0x00c0, 0x92e5, 0xa280, 0x0004, 0x2004,
+	0xa005, 0x0040, 0x92e5, 0x057e, 0x7510, 0x7614, 0x1078, 0x9f46,
+	0x057f, 0x0c7f, 0x0d7f, 0x0e7f, 0x007c, 0x6007, 0x003b, 0x602b,
+	0x0009, 0x6013, 0x2a00, 0x6003, 0x0001, 0x1078, 0x5bf8, 0x0078,
+	0x92e1, 0x6007, 0x003b, 0x602b, 0x0009, 0x6013, 0x1700, 0x6003,
+	0x0001, 0x1078, 0x5bf8, 0x0078, 0x92e1, 0x6007, 0x003b, 0x602b,
+	0x000b, 0x6013, 0x0000, 0x0078, 0x925d, 0x0e7e, 0x027e, 0x1078,
+	0x4897, 0x0040, 0x933a, 0x1078, 0x4887, 0x1078, 0xa148, 0x00c0,
+	0x9338, 0x2071, 0xa300, 0x70c8, 0xc085, 0x70ca, 0x0f7e, 0x2079,
+	0x0100, 0x7294, 0xa284, 0x00ff, 0x706a, 0x78e6, 0xa284, 0xff00,
+	0x726c, 0xa205, 0x706e, 0x78ea, 0x0f7f, 0x70d3, 0x0000, 0x2001,
+	0xa352, 0x2004, 0xd0a4, 0x0040, 0x9331, 0x2011, 0xa5c4, 0x2013,
+	0x07d0, 0xd0ac, 0x00c0, 0x933a, 0x1078, 0x260d, 0x0078, 0x933a,
+	0x1078, 0xa178, 0x027f, 0x0e7f, 0x1078, 0x753d, 0x0078, 0x9199,
+	0x1078, 0x753d, 0x007c, 0x0d7e, 0x067e, 0x6618, 0x2668, 0x6e04,
+	0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0040, 0x9360, 0xa686,
+	0x0004, 0x0040, 0x9360, 0x6e04, 0xa6b4, 0x00ff, 0xa686, 0x0006,
+	0x0040, 0x9360, 0xa686, 0x0004, 0x0040, 0x9360, 0xa085, 0x0001,
+	0x067f, 0x0d7f, 0x007c, 0x0d7e, 0x1078, 0x9397, 0x0d7f, 0x007c,
+	0x0d7e, 0x1078, 0x93a6, 0x00c0, 0x9390, 0x680c, 0xa08c, 0xff00,
+	0x6820, 0xa084, 0x00ff, 0xa115, 0x6212, 0x6824, 0x602a, 0xd1e4,
+	0x0040, 0x937e, 0x2009, 0x0001, 0x0078, 0x938c, 0xd1ec, 0x0040,
+	0x9390, 0x6920, 0xa18c, 0x00ff, 0x6824, 0x1078, 0x24e3, 0x00c0,
+	0x9390, 0x2110, 0x2009, 0x0000, 0x1078, 0x285b, 0x0078, 0x9394,
+	0xa085, 0x0001, 0x0078, 0x9395, 0xa006, 0x0d7f, 0x007c, 0x2069,
+	0xa88d, 0x6800, 0xa082, 0x0010, 0x00c8, 0x93a4, 0x6013, 0x0000,
+	0xa085, 0x0001, 0x0078, 0x93a5, 0xa006, 0x007c, 0x6013, 0x0000,
+	0x2069, 0xa88c, 0x6808, 0xa084, 0xff00, 0xa086, 0x0800, 0x00c0,
+	0x93ba, 0x6800, 0xa084, 0x00ff, 0xa08e, 0x0014, 0x0040, 0x93ba,
+	0xa08e, 0x0010, 0x007c, 0x6004, 0xa0b2, 0x0044, 0x10c8, 0x1328,
+	0xa1b6, 0x0013, 0x00c0, 0x93c7, 0x2008, 0x0079, 0x93da, 0xa1b6,
+	0x0027, 0x0040, 0x93cf, 0xa1b6, 0x0014, 0x10c0, 0x1328, 0x2001,
+	0x0007, 0x1078, 0x4472, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078,
+	0x6109, 0x007c, 0x941a, 0x941c, 0x941a, 0x941a, 0x941a, 0x941c,
+	0x9424, 0x94ae, 0x9471, 0x94ae, 0x9485, 0x94ae, 0x9424, 0x94ae,
+	0x94a6, 0x94ae, 0x94a6, 0x94ae, 0x94ae, 0x941a, 0x941a, 0x941a,
+	0x941a, 0x941a, 0x941a, 0x941a, 0x941a, 0x941a, 0x941a, 0x941a,
+	0x941c, 0x941a, 0x94ae, 0x941a, 0x941a, 0x94ae, 0x941a, 0x94ae,
+	0x94ae, 0x941a, 0x941a, 0x941a, 0x941a, 0x94ae, 0x94ae, 0x941a,
+	0x94ae, 0x94ae, 0x941a, 0x941a, 0x941a, 0x941a, 0x941a, 0x941c,
+	0x94ae, 0x94ae, 0x941a, 0x941a, 0x94ae, 0x94ae, 0x941a, 0x941a,
+	0x941a, 0x941a, 0x1078, 0x1328, 0x1078, 0x6010, 0x6003, 0x0002,
+	0x1078, 0x6109, 0x0078, 0x94b4, 0x0f7e, 0x2079, 0xa351, 0x7804,
+	0x0f7f, 0xd0ac, 0x00c0, 0x94ae, 0x2001, 0x0000, 0x1078, 0x442b,
+	0x6018, 0xa080, 0x0004, 0x2004, 0xa086, 0x00ff, 0x0040, 0x94ae,
+	0x0c7e, 0x6018, 0x2060, 0x6000, 0xd0f4, 0x00c0, 0x9448, 0x6010,
+	0xa005, 0x0040, 0x9448, 0x0c7f, 0x1078, 0x35f7, 0x0078, 0x94ae,
+	0x0c7f, 0x2001, 0xa300, 0x2004, 0xa086, 0x0002, 0x00c0, 0x9457,
+	0x0f7e, 0x2079, 0xa300, 0x788c, 0x8000, 0x788e, 0x0f7f, 0x2001,
+	0x0002, 0x1078, 0x443f, 0x1078, 0x6010, 0x601f, 0x0001, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x1078, 0x5c45, 0x1078, 0x6109, 0x0c7e,
+	0x6118, 0x2160, 0x2009, 0x0001, 0x1078, 0x58e1, 0x0c7f, 0x0078,
+	0x94b4, 0x6618, 0x0d7e, 0x2668, 0x6e04, 0x0d7f, 0xa6b4, 0xff00,
+	0x8637, 0xa686, 0x0006, 0x0040, 0x94ae, 0xa686, 0x0004, 0x0040,
+	0x94ae, 0x2001, 0x0004, 0x0078, 0x94ac, 0x2001, 0xa300, 0x2004,
+	0xa086, 0x0003, 0x00c0, 0x948e, 0x1078, 0x35f7, 0x2001, 0x0006,
+	0x1078, 0x94b5, 0x6618, 0x0d7e, 0x2668, 0x6e04, 0x0d7f, 0xa6b4,
+	0xff00, 0x8637, 0xa686, 0x0006, 0x0040, 0x94ae, 0x2001, 0x0006,
+	0x0078, 0x94ac, 0x2001, 0x0004, 0x0078, 0x94ac, 0x2001, 0x0006,
+	0x1078, 0x94b5, 0x0078, 0x94ae, 0x1078, 0x4472, 0x1078, 0x6010,
+	0x1078, 0x753d, 0x1078, 0x6109, 0x007c, 0x017e, 0x0d7e, 0x6118,
+	0x2168, 0x6900, 0xd184, 0x0040, 0x94d0, 0x6104, 0xa18e, 0x000a,
+	0x00c0, 0x94c8, 0x699c, 0xd1a4, 0x00c0, 0x94c8, 0x2001, 0x0007,
+	0x1078, 0x443f, 0x2001, 0x0000, 0x1078, 0x442b, 0x1078, 0x2839,
+	0x0d7f, 0x017f, 0x007c, 0x0d7e, 0x6618, 0x2668, 0x6804, 0xa084,
+	0xff00, 0x8007, 0x0d7f, 0xa0b2, 0x000c, 0x10c8, 0x1328, 0xa1b6,
+	0x0015, 0x00c0, 0x94e7, 0x1079, 0x94ee, 0x0078, 0x94ed, 0xa1b6,
+	0x0016, 0x10c0, 0x1328, 0x1079, 0x94fa, 0x007c, 0x7ad0, 0x7ad0,
+	0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x9547, 0x9506, 0x7ad0, 0x7ad0,
+	0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0,
+	0x9547, 0x954f, 0x7ad0, 0x7ad0, 0x7ad0, 0x7ad0, 0x0f7e, 0x2079,
+	0xa351, 0x7804, 0xd0ac, 0x00c0, 0x952d, 0x6018, 0xa07d, 0x0040,
+	0x952d, 0x7800, 0xd0f4, 0x00c0, 0x9519, 0x7810, 0xa005, 0x00c0,
+	0x952d, 0x2001, 0x0000, 0x1078, 0x442b, 0x2001, 0x0002, 0x1078,
+	0x443f, 0x601f, 0x0001, 0x6003, 0x0001, 0x6007, 0x0002, 0x1078,
+	0x5c45, 0x1078, 0x6109, 0x0078, 0x9545, 0x2011, 0xa883, 0x2204,
+	0x8211, 0x220c, 0x1078, 0x24e3, 0x00c0, 0x9545, 0x0c7e, 0x1078,
+	0x4501, 0x0040, 0x9540, 0x0c7f, 0x1078, 0x753d, 0x0078, 0x9545,
+	0x1078, 0x4235, 0x0c7f, 0x1078, 0x753d, 0x0f7f, 0x007c, 0x6604,
+	0xa6b6, 0x001e, 0x00c0, 0x954e, 0x1078, 0x753d, 0x007c, 0x1078,
+	0x7d0a, 0x00c0, 0x955b, 0x6003, 0x0001, 0x6007, 0x0001, 0x1078,
+	0x5c45, 0x0078, 0x955d, 0x1078, 0x753d, 0x007c, 0x6004, 0xa08a,
+	0x0044, 0x10c8, 0x1328, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078,
+	0x6109, 0x007c, 0xa182, 0x0040, 0x0079, 0x956e, 0x9581, 0x9581,
+	0x9581, 0x9581, 0x9583, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581,
+	0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581,
+	0x9581, 0x1078, 0x1328, 0x0d7e, 0x0e7e, 0x0f7e, 0x157e, 0x047e,
+	0x027e, 0x6218, 0xa280, 0x002b, 0x2004, 0xa005, 0x0040, 0x9594,
+	0x2021, 0x0000, 0x1078, 0xa111, 0x6106, 0x2071, 0xa880, 0x7444,
+	0xa4a4, 0xff00, 0x0040, 0x95eb, 0xa486, 0x2000, 0x00c0, 0x95a6,
+	0x2009, 0x0001, 0x2011, 0x0200, 0x1078, 0x5a6d, 0x1078, 0x1381,
+	0x1040, 0x1328, 0x6003, 0x0007, 0x2d00, 0x6837, 0x010d, 0x6803,
+	0x0000, 0x683b, 0x0000, 0x6c5a, 0x2c00, 0x685e, 0x6008, 0x68b2,
+	0x6018, 0x2078, 0x78a0, 0x8007, 0x7130, 0x694a, 0x017e, 0xa084,
+	0xff00, 0x6846, 0x684f, 0x0000, 0x6857, 0x0036, 0x1078, 0x4982,
+	0x017f, 0xa486, 0x2000, 0x00c0, 0x95d3, 0x2019, 0x0017, 0x1078,
+	0x9e3b, 0x0078, 0x9645, 0xa486, 0x0400, 0x00c0, 0x95dd, 0x2019,
+	0x0002, 0x1078, 0x9dec, 0x0078, 0x9645, 0xa486, 0x0200, 0x00c0,
+	0x95e3, 0x1078, 0x9dd1, 0xa486, 0x1000, 0x00c0, 0x95e9, 0x1078,
+	0x9e20, 0x0078, 0x9645, 0x2069, 0xa62d, 0x6a00, 0xd284, 0x0040,
+	0x969b, 0xa284, 0x0300, 0x00c0, 0x9693, 0x6804, 0xa005, 0x0040,
+	0x9683, 0x2d78, 0x6003, 0x0007, 0x1078, 0x1366, 0x0040, 0x964c,
+	0x7800, 0xd08c, 0x00c0, 0x9607, 0x7804, 0x8001, 0x7806, 0x6013,
+	0x0000, 0x6803, 0x0000, 0x6837, 0x0116, 0x683b, 0x0000, 0x6008,
+	0x68b2, 0x2c00, 0x684a, 0x6018, 0x2078, 0x78a0, 0x8007, 0x7130,
+	0x6986, 0x6846, 0x6853, 0x003d, 0x7244, 0xa294, 0x0003, 0xa286,
+	0x0002, 0x00c0, 0x9627, 0x684f, 0x0040, 0x0078, 0x9631, 0xa286,
+	0x0001, 0x00c0, 0x962f, 0x684f, 0x0080, 0x0078, 0x9631, 0x684f,
+	0x0000, 0x20a9, 0x000a, 0x2001, 0xa890, 0xad90, 0x0015, 0x200c,
+	0x810f, 0x2112, 0x8000, 0x8210, 0x00f0, 0x9637, 0x200c, 0x6982,
+	0x8000, 0x200c, 0x697e, 0x1078, 0x4982, 0x027f, 0x047f, 0x157f,
+	0x0f7f, 0x0e7f, 0x0d7f, 0x007c, 0x6013, 0x0100, 0x6003, 0x0001,
+	0x6007, 0x0041, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0078, 0x9645,
+	0x2069, 0xa892, 0x2d04, 0xa084, 0xff00, 0xa086, 0x1200, 0x00c0,
+	0x9677, 0x2069, 0xa880, 0x686c, 0xa084, 0x00ff, 0x017e, 0x6110,
+	0xa18c, 0x0700, 0xa10d, 0x6112, 0x017f, 0x6003, 0x0001, 0x6007,
+	0x0043, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0078, 0x9645, 0x6013,
+	0x0200, 0x6003, 0x0001, 0x6007, 0x0041, 0x1078, 0x5bf8, 0x1078,
+	0x6109, 0x0078, 0x9645, 0x6013, 0x0300, 0x0078, 0x9689, 0x6013,
+	0x0100, 0x6003, 0x0001, 0x6007, 0x0041, 0x1078, 0x5bf8, 0x1078,
+	0x6109, 0x0078, 0x9645, 0x6013, 0x0500, 0x0078, 0x9689, 0x6013,
+	0x0600, 0x0078, 0x9658, 0x6013, 0x0200, 0x0078, 0x9658, 0xa186,
+	0x0013, 0x00c0, 0x96b1, 0x6004, 0xa08a, 0x0040, 0x1048, 0x1328,
+	0xa08a, 0x0053, 0x10c8, 0x1328, 0xa082, 0x0040, 0x2008, 0x0079,
+	0x9725, 0xa186, 0x0051, 0x0040, 0x96be, 0xa186, 0x0047, 0x00c0,
+	0x96d7, 0x6004, 0xa086, 0x0041, 0x0040, 0x96e5, 0x2001, 0x0109,
+	0x2004, 0xd084, 0x0040, 0x96e5, 0x127e, 0x2091, 0x2200, 0x007e,
+	0x017e, 0x027e, 0x1078, 0x5ad2, 0x027f, 0x017f, 0x007f, 0x127f,
+	0x6000, 0xa086, 0x0002, 0x00c0, 0x96e5, 0x0078, 0x976a, 0xa186,
+	0x0027, 0x0040, 0x96df, 0xa186, 0x0014, 0x10c0, 0x1328, 0x6004,
+	0xa082, 0x0040, 0x2008, 0x0079, 0x96e8, 0x1078, 0x7583, 0x007c,
+	0x96fb, 0x96fd, 0x96fd, 0x96fb, 0x96fb, 0x96fb, 0x96fb, 0x96fb,
+	0x96fb, 0x96fb, 0x96fb, 0x96fb, 0x96fb, 0x96fb, 0x96fb, 0x96fb,
+	0x96fb, 0x96fb, 0x96fb, 0x1078, 0x1328, 0x1078, 0x6010, 0x1078,
+	0x6109, 0x037e, 0x0d7e, 0x6010, 0xa06d, 0x0040, 0x9722, 0xad84,
+	0xf000, 0x0040, 0x9722, 0x6003, 0x0002, 0x6018, 0x2004, 0xd0bc,
+	0x00c0, 0x9722, 0x2019, 0x0004, 0x1078, 0x9e70, 0x6013, 0x0000,
+	0x6014, 0xa005, 0x00c0, 0x9720, 0x2001, 0xa5a1, 0x2004, 0x6016,
+	0x6003, 0x0007, 0x0d7f, 0x037f, 0x007c, 0x9738, 0x9757, 0x9741,
+	0x9764, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738,
+	0x9738, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738, 0x9738,
+	0x1078, 0x1328, 0x6010, 0xa088, 0x0013, 0x2104, 0xa085, 0x0400,
+	0x200a, 0x1078, 0x6010, 0x6010, 0xa080, 0x0013, 0x2004, 0xd0b4,
+	0x0040, 0x9752, 0x6003, 0x0007, 0x2009, 0x0043, 0x1078, 0x756c,
+	0x0078, 0x9754, 0x6003, 0x0002, 0x1078, 0x6109, 0x007c, 0x1078,
+	0x6010, 0x1078, 0xa0c6, 0x00c0, 0x9761, 0x1078, 0x5a41, 0x1078,
+	0x753d, 0x1078, 0x6109, 0x007c, 0x1078, 0x6010, 0x2009, 0x0041,
+	0x0078, 0x98c1, 0xa182, 0x0040, 0x0079, 0x976e, 0x9781, 0x9783,
+	0x9781, 0x9781, 0x9781, 0x9781, 0x9781, 0x9784, 0x9781, 0x9781,
+	0x9781, 0x9781, 0x9781, 0x9781, 0x9781, 0x9781, 0x9781, 0x978f,
+	0x9781, 0x1078, 0x1328, 0x007c, 0x6003, 0x0004, 0x6110, 0x20e1,
+	0x0005, 0x3d18, 0x3e20, 0x2c10, 0x1078, 0x15ec, 0x007c, 0x0d7e,
+	0x1078, 0x5a41, 0x0d7f, 0x1078, 0xa134, 0x1078, 0x753d, 0x007c,
+	0xa182, 0x0040, 0x0079, 0x979c, 0x97af, 0x97af, 0x97af, 0x97af,
+	0x97af, 0x97af, 0x97af, 0x97b1, 0x97af, 0x97b4, 0x97df, 0x97af,
+	0x97af, 0x97af, 0x97af, 0x97df, 0x97af, 0x97af, 0x97af, 0x1078,
+	0x1328, 0x1078, 0x7583, 0x007c, 0x1078, 0x60b8, 0x1078, 0x61d3,
+	0x6010, 0x0d7e, 0x2068, 0x684c, 0xd0fc, 0x0040, 0x97ca, 0xa08c,
+	0x0003, 0xa18e, 0x0002, 0x0040, 0x97d2, 0x2009, 0x0041, 0x0d7f,
+	0x0078, 0x98c1, 0x6003, 0x0007, 0x6017, 0x0000, 0x1078, 0x5a41,
+	0x0d7f, 0x007c, 0x1078, 0xa0c6, 0x0040, 0x97d8, 0x0d7f, 0x007c,
+	0x1078, 0x5a41, 0x1078, 0x753d, 0x0d7f, 0x0078, 0x97d1, 0x037e,
+	0x1078, 0x60b8, 0x1078, 0x61d3, 0x6010, 0x0d7e, 0x2068, 0x6018,
+	0x2004, 0xd0bc, 0x0040, 0x97ff, 0x684c, 0xa084, 0x0003, 0xa086,
+	0x0002, 0x0040, 0x97fb, 0x687c, 0x632c, 0xa31a, 0x632e, 0x6880,
+	0x6328, 0xa31b, 0x632a, 0x6003, 0x0002, 0x0078, 0x9810, 0x2019,
+	0x0004, 0x1078, 0x9e70, 0x6014, 0xa005, 0x00c0, 0x980c, 0x2001,
+	0xa5a1, 0x2004, 0x8003, 0x6016, 0x6013, 0x0000, 0x6003, 0x0007,
+	0x0d7f, 0x037f, 0x007c, 0xa186, 0x0013, 0x00c0, 0x9821, 0x6004,
+	0xa086, 0x0042, 0x10c0, 0x1328, 0x1078, 0x6010, 0x1078, 0x6109,
+	0x007c, 0xa186, 0x0027, 0x0040, 0x9829, 0xa186, 0x0014, 0x00c0,
+	0x9839, 0x6004, 0xa086, 0x0042, 0x10c0, 0x1328, 0x2001, 0x0007,
+	0x1078, 0x4472, 0x1078, 0x6010, 0x1078, 0x8c01, 0x1078, 0x6109,
+	0x007c, 0xa182, 0x0040, 0x0079, 0x983d, 0x9850, 0x9850, 0x9850,
+	0x9850, 0x9850, 0x9850, 0x9850, 0x9852, 0x985e, 0x9850, 0x9850,
+	0x9850, 0x9850, 0x9850, 0x9850, 0x9850, 0x9850, 0x9850, 0x9850,
+	0x1078, 0x1328, 0x037e, 0x047e, 0x20e1, 0x0005, 0x3d18, 0x3e20,
+	0x2c10, 0x1078, 0x15ec, 0x047f, 0x037f, 0x007c, 0x6010, 0x0d7e,
+	0x2068, 0x6810, 0x6a14, 0x6118, 0x210c, 0xd1bc, 0x0040, 0x987d,
+	0x6124, 0xd1f4, 0x00c0, 0x987d, 0x007e, 0x047e, 0x057e, 0x6c7c,
+	0xa422, 0x6d80, 0x2200, 0xa52b, 0x602c, 0xa420, 0x642e, 0x6028,
+	0xa529, 0x652a, 0x057f, 0x047f, 0x007f, 0xa20d, 0x00c0, 0x9891,
+	0x684c, 0xd0fc, 0x0040, 0x9889, 0x2009, 0x0041, 0x0d7f, 0x0078,
+	0x98c1, 0x6003, 0x0007, 0x6017, 0x0000, 0x1078, 0x5a41, 0x0d7f,
+	0x007c, 0x007e, 0x0f7e, 0x2c78, 0x1078, 0x4893, 0x0f7f, 0x007f,
+	0x0040, 0x989e, 0x6003, 0x0002, 0x0d7f, 0x007c, 0x2009, 0xa30d,
+	0x210c, 0xd19c, 0x0040, 0x98a8, 0x6003, 0x0007, 0x0078, 0x98aa,
+	0x6003, 0x0006, 0x1078, 0x98b0, 0x1078, 0x5a43, 0x0d7f, 0x007c,
+	0xd2fc, 0x0040, 0x98bc, 0x8002, 0x8000, 0x8212, 0xa291, 0x0000,
+	0x2009, 0x0009, 0x0078, 0x98be, 0x2009, 0x0015, 0x6a6a, 0x6866,
+	0x007c, 0xa182, 0x0040, 0x0048, 0x98c7, 0x0079, 0x98d4, 0xa186,
+	0x0013, 0x0040, 0x98cf, 0xa186, 0x0014, 0x10c0, 0x1328, 0x6024,
+	0xd0dc, 0x1040, 0x1328, 0x007c, 0x98e7, 0x98ee, 0x98fa, 0x9906,
+	0x98e7, 0x98e7, 0x98e7, 0x9915, 0x98e7, 0x98e9, 0x98e9, 0x98e7,
+	0x98e7, 0x98e7, 0x98e7, 0x98e7, 0x98e7, 0x98e7, 0x98e7, 0x1078,
+	0x1328, 0x6024, 0xd0dc, 0x1040, 0x1328, 0x007c, 0x6003, 0x0001,
+	0x6106, 0x1078, 0x5bf8, 0x127e, 0x2091, 0x8000, 0x1078, 0x6109,
+	0x127f, 0x007c, 0x6003, 0x0001, 0x6106, 0x1078, 0x5bf8, 0x127e,
+	0x2091, 0x8000, 0x1078, 0x6109, 0x127f, 0x007c, 0x6003, 0x0003,
+	0x6106, 0x2c10, 0x1078, 0x1cab, 0x127e, 0x2091, 0x8000, 0x1078,
+	0x5c64, 0x1078, 0x61d3, 0x127f, 0x007c, 0xa016, 0x1078, 0x15ec,
+	0x007c, 0x127e, 0x2091, 0x8000, 0x037e, 0x0d7e, 0xa182, 0x0040,
+	0x1079, 0x9926, 0x0d7f, 0x037f, 0x127f, 0x007c, 0x9936, 0x9938,
+	0x994d, 0x996c, 0x9936, 0x9936, 0x9936, 0x9984, 0x9936, 0x9936,
+	0x9936, 0x9936, 0x9936, 0x9936, 0x9936, 0x9936, 0x1078, 0x1328,
+	0x6010, 0x2068, 0x684c, 0xd0fc, 0x0040, 0x9962, 0xa09c, 0x0003,
+	0xa39e, 0x0003, 0x0040, 0x9962, 0x6003, 0x0001, 0x6106, 0x1078,
+	0x5bf8, 0x1078, 0x6109, 0x0078, 0x9987, 0x6010, 0x2068, 0x684c,
+	0xd0fc, 0x0040, 0x9962, 0xa09c, 0x0003, 0xa39e, 0x0003, 0x0040,
+	0x9962, 0x6003, 0x0001, 0x6106, 0x1078, 0x5bf8, 0x1078, 0x6109,
+	0x0078, 0x9987, 0x6013, 0x0000, 0x6017, 0x0000, 0x2019, 0x0004,
+	0x1078, 0x9e70, 0x0078, 0x9987, 0x6010, 0x2068, 0x684c, 0xd0fc,
+	0x0040, 0x9962, 0xa09c, 0x0003, 0xa39e, 0x0003, 0x0040, 0x9962,
+	0x6003, 0x0003, 0x6106, 0x2c10, 0x1078, 0x1cab, 0x1078, 0x5c64,
+	0x1078, 0x61d3, 0x0078, 0x9987, 0xa016, 0x1078, 0x15ec, 0x007c,
+	0x1078, 0x6010, 0x6110, 0x81ff, 0x0040, 0x9999, 0x0d7e, 0x2168,
+	0x1078, 0xa181, 0x037e, 0x2019, 0x0029, 0x1078, 0x9e70, 0x037f,
+	0x0d7f, 0x1078, 0x8c01, 0x1078, 0x6109, 0x007c, 0x1078, 0x60b8,
+	0x6110, 0x81ff, 0x0040, 0x99af, 0x0d7e, 0x2168, 0x1078, 0xa181,
+	0x037e, 0x2019, 0x0029, 0x1078, 0x9e70, 0x037f, 0x0d7f, 0x1078,
+	0x8c01, 0x1078, 0x61d3, 0x007c, 0xa182, 0x0085, 0x0079, 0x99b8,
+	0x99c1, 0x99bf, 0x99bf, 0x99cd, 0x99bf, 0x99bf, 0x99bf, 0x1078,
+	0x1328, 0x6003, 0x000b, 0x6106, 0x1078, 0x5bf8, 0x127e, 0x2091,
+	0x8000, 0x1078, 0x6109, 0x127f, 0x007c, 0x027e, 0x0e7e, 0x1078,
+	0xa0bf, 0x0040, 0x99d7, 0x1078, 0x753d, 0x0078, 0x99f3, 0x2071,
+	0xa880, 0x7224, 0x6212, 0x7220, 0x1078, 0x9d10, 0x0040, 0x99e4,
+	0x6007, 0x0086, 0x0078, 0x99ed, 0x6007, 0x0087, 0x7224, 0xa296,
+	0xffff, 0x00c0, 0x99ed, 0x6007, 0x0086, 0x6003, 0x0001, 0x1078,
+	0x5bf8, 0x1078, 0x6109, 0x0e7f, 0x027f, 0x007c, 0xa186, 0x0013,
+	0x00c0, 0x9a07, 0x6004, 0xa08a, 0x0085, 0x1048, 0x1328, 0xa08a,
+	0x008c, 0x10c8, 0x1328, 0xa082, 0x0085, 0x0079, 0x9a1e, 0xa186,
+	0x0027, 0x0040, 0x9a13, 0xa186, 0x0014, 0x0040, 0x9a13, 0x1078,
+	0x7583, 0x0078, 0x9a1d, 0x2001, 0x0007, 0x1078, 0x4472, 0x1078,
+	0x6010, 0x1078, 0x8c01, 0x1078, 0x6109, 0x007c, 0x9a25, 0x9a27,
+	0x9a27, 0x9a25, 0x9a25, 0x9a25, 0x9a25, 0x1078, 0x1328, 0x1078,
+	0x6010, 0x1078, 0x8c01, 0x1078, 0x6109, 0x007c, 0xa182, 0x0085,
+	0x1048, 0x1328, 0xa182, 0x008c, 0x10c8, 0x1328, 0xa182, 0x0085,
+	0x0079, 0x9a3a, 0x9a41, 0x9a41, 0x9a41, 0x9a43, 0x9a41, 0x9a41,
+	0x9a41, 0x1078, 0x1328, 0x007c, 0xa186, 0x0013, 0x0040, 0x9a54,
+	0xa186, 0x0014, 0x0040, 0x9a54, 0xa186, 0x0027, 0x0040, 0x9a54,
+	0x1078, 0x7583, 0x0078, 0x9a5a, 0x1078, 0x6010, 0x1078, 0x8c01,
+	0x1078, 0x6109, 0x007c, 0x037e, 0x1078, 0xa134, 0x603f, 0x0000,
+	0x2019, 0x000b, 0x1078, 0x9a6a, 0x601f, 0x0006, 0x6003, 0x0007,
+	0x037f, 0x007c, 0x127e, 0x037e, 0x2091, 0x8000, 0x087e, 0x2c40,
+	0x097e, 0x2049, 0x0000, 0x1078, 0x7058, 0x097f, 0x087f, 0x00c0,
+	0x9aa5, 0x077e, 0x2c38, 0x1078, 0x7105, 0x077f, 0x00c0, 0x9aa5,
+	0x6000, 0xa086, 0x0000, 0x0040, 0x9aa5, 0x601c, 0xa086, 0x0007,
+	0x0040, 0x9aa5, 0x0d7e, 0x6000, 0xa086, 0x0004, 0x00c0, 0x9a96,
+	0x1078, 0xa134, 0x601f, 0x0007, 0x1078, 0x1749, 0x6010, 0x2068,
+	0x1078, 0x8a44, 0x0040, 0x9a9e, 0x1078, 0x9e70, 0x0d7f, 0x6013,
+	0x0000, 0x1078, 0xa134, 0x601f, 0x0007, 0x037f, 0x127f, 0x007c,
+	0x0f7e, 0x0c7e, 0x037e, 0x157e, 0x2079, 0xa880, 0x7938, 0x783c,
+	0x1078, 0x24e3, 0x00c0, 0x9af6, 0x017e, 0x0c7e, 0x1078, 0x4501,
+	0x00c0, 0x9af6, 0x2011, 0xa890, 0xac98, 0x000a, 0x20a9, 0x0004,
+	0x1078, 0x7e55, 0x00c0, 0x9af6, 0x017f, 0x027f, 0x027e, 0x017e,
+	0x2019, 0x0029, 0x1078, 0x71e0, 0x1078, 0x5d53, 0x077e, 0x2039,
+	0x0000, 0x1078, 0x5c78, 0x077f, 0x017f, 0x077e, 0x2039, 0x0000,
+	0x1078, 0x9c38, 0x077f, 0x1078, 0x471b, 0x027e, 0x6204, 0xa294,
+	0xff00, 0x8217, 0xa286, 0x0006, 0x0040, 0x9aea, 0xa286, 0x0004,
+	0x00c0, 0x9aed, 0x62a0, 0x1078, 0x28d5, 0x027f, 0x017f, 0x1078,
+	0x4235, 0x6612, 0x6516, 0xa006, 0x0078, 0x9af8, 0x0c7f, 0x017f,
+	0x157f, 0x037f, 0x0c7f, 0x0f7f, 0x007c, 0x0c7e, 0x0d7e, 0x0e7e,
+	0x017e, 0x2009, 0xa31f, 0x2104, 0xa086, 0x0074, 0x00c0, 0x9b60,
+	0x2069, 0xa88e, 0x690c, 0xa182, 0x0100, 0x0048, 0x9b50, 0x6908,
+	0xa184, 0x8000, 0x0040, 0x9b5c, 0x6018, 0x2070, 0x7010, 0xa084,
+	0x00ff, 0x0040, 0x9b1f, 0x7000, 0xd0f4, 0x0040, 0x9b23, 0xa184,
+	0x0800, 0x0040, 0x9b5c, 0x6910, 0xa18a, 0x0001, 0x0048, 0x9b54,
+	0x6914, 0x2069, 0xa8ae, 0x6904, 0x81ff, 0x00c0, 0x9b48, 0x690c,
+	0xa182, 0x0100, 0x0048, 0x9b50, 0x6908, 0x81ff, 0x00c0, 0x9b4c,
+	0x6910, 0xa18a, 0x0001, 0x0048, 0x9b54, 0x6918, 0xa18a, 0x0001,
+	0x0048, 0x9b5c, 0x0078, 0x9b66, 0x6013, 0x0100, 0x0078, 0x9b62,
+	0x6013, 0x0300, 0x0078, 0x9b62, 0x6013, 0x0500, 0x0078, 0x9b62,
+	0x6013, 0x0700, 0x0078, 0x9b62, 0x6013, 0x0900, 0x0078, 0x9b62,
+	0x6013, 0x0b00, 0x0078, 0x9b62, 0x6013, 0x0f00, 0x0078, 0x9b62,
+	0x6013, 0x2d00, 0xa085, 0x0001, 0x0078, 0x9b67, 0xa006, 0x017f,
+	0x0e7f, 0x0d7f, 0x0c7f, 0x007c, 0x0c7e, 0x0d7e, 0x027e, 0x037e,
+	0x157e, 0x6218, 0x2268, 0x6b04, 0xa394, 0x00ff, 0xa286, 0x0006,
+	0x0040, 0x9b90, 0xa286, 0x0004, 0x0040, 0x9b90, 0xa394, 0xff00,
+	0x8217, 0xa286, 0x0006, 0x0040, 0x9b90, 0xa286, 0x0004, 0x0040,
+	0x9b90, 0x0c7e, 0x2d60, 0x1078, 0x4513, 0x0c7f, 0x0078, 0x9bcb,
+	0x2011, 0xa896, 0xad98, 0x000a, 0x20a9, 0x0004, 0x1078, 0x7e55,
+	0x00c0, 0x9bcc, 0x2011, 0xa89a, 0xad98, 0x0006, 0x20a9, 0x0004,
+	0x1078, 0x7e55, 0x00c0, 0x9bcc, 0x047e, 0x017e, 0x6aa0, 0xa294,
+	0x00ff, 0x8227, 0xa006, 0x2009, 0xa352, 0x210c, 0xd1a4, 0x0040,
+	0x9bb8, 0x2009, 0x0029, 0x1078, 0x9ec0, 0x6800, 0xc0e5, 0x6802,
+	0x2019, 0x0029, 0x1078, 0x5d53, 0x077e, 0x2039, 0x0000, 0x1078,
+	0x5c78, 0x2c08, 0x1078, 0x9c38, 0x077f, 0x2001, 0x0007, 0x1078,
+	0x4472, 0x017f, 0x047f, 0xa006, 0x157f, 0x037f, 0x027f, 0x0d7f,
+	0x0c7f, 0x007c, 0x0d7e, 0x2069, 0xa88e, 0x6800, 0xa086, 0x0800,
+	0x0040, 0x9bde, 0x6013, 0x0000, 0x0078, 0x9bdf, 0xa006, 0x0d7f,
+	0x007c, 0x0c7e, 0x0f7e, 0x017e, 0x027e, 0x037e, 0x157e, 0x2079,
+	0xa88c, 0x7930, 0x7834, 0x1078, 0x24e3, 0x00c0, 0x9c05, 0x1078,
+	0x4501, 0x00c0, 0x9c05, 0x2011, 0xa890, 0xac98, 0x000a, 0x20a9,
+	0x0004, 0x1078, 0x7e55, 0x00c0, 0x9c05, 0x2011, 0xa894, 0xac98,
+	0x0006, 0x20a9, 0x0004, 0x1078, 0x7e55, 0x157f, 0x037f, 0x027f,
+	0x017f, 0x0f7f, 0x0c7f, 0x007c, 0x0c7e, 0x007e, 0x017e, 0x027e,
+	0x037e, 0x157e, 0x2011, 0xa883, 0x2204, 0x8211, 0x220c, 0x1078,
+	0x24e3, 0x00c0, 0x9c31, 0x1078, 0x4501, 0x00c0, 0x9c31, 0x2011,
+	0xa896, 0xac98, 0x000a, 0x20a9, 0x0004, 0x1078, 0x7e55, 0x00c0,
+	0x9c31, 0x2011, 0xa89a, 0xac98, 0x0006, 0x20a9, 0x0004, 0x1078,
+	0x7e55, 0x157f, 0x037f, 0x027f, 0x017f, 0x007f, 0x0c7f, 0x007c,
+	0x0e7e, 0x0c7e, 0x087e, 0x077e, 0x067e, 0x057e, 0x047e, 0x027e,
+	0x127e, 0x2091, 0x8000, 0x2740, 0x2029, 0xa5b4, 0x252c, 0x2021,
+	0xa5ba, 0x2424, 0x2061, 0xaa00, 0x2071, 0xa300, 0x7644, 0x7060,
+	0x81ff, 0x0040, 0x9c59, 0x8001, 0xa602, 0x00c8, 0x9cc3, 0x0078,
+	0x9c5c, 0xa606, 0x0040, 0x9cc3, 0x2100, 0xac06, 0x0040, 0x9cb9,
+	0x1078, 0x9ee5, 0x0040, 0x9cb9, 0x671c, 0xa786, 0x0001, 0x0040,
+	0x9cde, 0xa786, 0x0004, 0x0040, 0x9cde, 0xa786, 0x0007, 0x0040,
+	0x9cb9, 0x2500, 0xac06, 0x0040, 0x9cb9, 0x2400, 0xac06, 0x0040,
+	0x9cb9, 0x1078, 0x9ef9, 0x00c0, 0x9cb9, 0x88ff, 0x0040, 0x9c84,
+	0x6020, 0xa906, 0x00c0, 0x9cb9, 0x0d7e, 0x6000, 0xa086, 0x0004,
+	0x00c0, 0x9c8e, 0x017e, 0x1078, 0x1749, 0x017f, 0xa786, 0x0008,
+	0x00c0, 0x9c9d, 0x1078, 0x8c3b, 0x00c0, 0x9c9d, 0x1078, 0x7a05,
+	0x0d7f, 0x1078, 0x8c01, 0x0078, 0x9cb9, 0x6010, 0x2068, 0x1078,
+	0x8a44, 0x0040, 0x9cb6, 0xa786, 0x0003, 0x00c0, 0x9ccd, 0x6837,
+	0x0103, 0x6b4a, 0x6847, 0x0000, 0x1078, 0xa181, 0x017e, 0x1078,
+	0x8cb8, 0x1078, 0x4982, 0x017f, 0x1078, 0x8bf4, 0x0d7f, 0x1078,
+	0x8c01, 0xace0, 0x0010, 0x2001, 0xa315, 0x2004, 0xac02, 0x00c8,
+	0x9cc3, 0x0078, 0x9c4c, 0x127f, 0x027f, 0x047f, 0x057f, 0x067f,
+	0x077f, 0x087f, 0x0c7f, 0x0e7f, 0x007c, 0xa786, 0x0006, 0x00c0,
+	0x9ca7, 0xa386, 0x0005, 0x0040, 0x9cdb, 0x1078, 0xa181, 0x1078,
+	0x9e70, 0x0078, 0x9cb6, 0x0d7f, 0x0078, 0x9cb9, 0x1078, 0x9ef9,
+	0x00c0, 0x9cb9, 0x81ff, 0x0040, 0x9cb9, 0xa180, 0x0001, 0x2004,
+	0xa086, 0x0018, 0x0040, 0x9cf3, 0xa180, 0x0001, 0x2004, 0xa086,
+	0x002d, 0x00c0, 0x9cb9, 0x6000, 0xa086, 0x0002, 0x00c0, 0x9cb9,
+	0x1078, 0x8c27, 0x0040, 0x9d04, 0x1078, 0x8c3b, 0x00c0, 0x9cb9,
+	0x1078, 0x7a05, 0x0078, 0x9d0c, 0x1078, 0x2839, 0x1078, 0x8c3b,
+	0x00c0, 0x9d0c, 0x1078, 0x7a05, 0x1078, 0x8c01, 0x0078, 0x9cb9,
+	0x0c7e, 0x0e7e, 0x017e, 0x2c08, 0x2170, 0x1078, 0x9e8c, 0x017f,
+	0x0040, 0x9d1f, 0x601c, 0xa084, 0x000f, 0x1079, 0x9d22, 0x0e7f,
+	0x0c7f, 0x007c, 0x9d2a, 0x9d2a, 0x9d2a, 0x9d2a, 0x9d2a, 0x9d2a,
+	0x9d2c, 0x9d2a, 0xa006, 0x007c, 0x047e, 0x017e, 0x7018, 0xa080,
+	0x0028, 0x2024, 0xa4a4, 0x00ff, 0x8427, 0x2c00, 0x2009, 0x0020,
+	0x1078, 0x9ec0, 0x017f, 0x047f, 0x037e, 0x2019, 0x0002, 0x1078,
+	0x9a6a, 0x037f, 0xa085, 0x0001, 0x007c, 0x2001, 0x0001, 0x1078,
+	0x442b, 0x157e, 0x017e, 0x027e, 0x037e, 0x20a9, 0x0004, 0x2019,
+	0xa305, 0x2011, 0xa896, 0x1078, 0x7e55, 0x037f, 0x027f, 0x017f,
+	0x157f, 0xa005, 0x007c, 0x0f7e, 0x0e7e, 0x0c7e, 0x087e, 0x077e,
+	0x067e, 0x027e, 0x127e, 0x2091, 0x8000, 0x2740, 0x2061, 0xaa00,
+	0x2079, 0x0001, 0x8fff, 0x0040, 0x9dc3, 0x2071, 0xa300, 0x7644,
+	0x7060, 0x8001, 0xa602, 0x00c8, 0x9dc3, 0x88ff, 0x0040, 0x9d7e,
+	0x2800, 0xac06, 0x00c0, 0x9db9, 0x2079, 0x0000, 0x1078, 0x9ee5,
+	0x0040, 0x9db9, 0x2400, 0xac06, 0x0040, 0x9db9, 0x671c, 0xa786,
+	0x0006, 0x00c0, 0x9db9, 0xa786, 0x0007, 0x0040, 0x9db9, 0x88ff,
+	0x00c0, 0x9d9d, 0x6018, 0xa206, 0x00c0, 0x9db9, 0x85ff, 0x0040,
+	0x9d9d, 0x6020, 0xa106, 0x00c0, 0x9db9, 0x0d7e, 0x6000, 0xa086,
+	0x0004, 0x00c0, 0x9da9, 0x1078, 0xa134, 0x601f, 0x0007, 0x1078,
+	0x1749, 0x6010, 0x2068, 0x1078, 0x8a44, 0x0040, 0x9db3, 0x047e,
+	0x1078, 0x9e70, 0x047f, 0x0d7f, 0x1078, 0x8c01, 0x88ff, 0x00c0,
+	0x9dcd, 0xace0, 0x0010, 0x2001, 0xa315, 0x2004, 0xac02, 0x00c8,
+	0x9dc3, 0x0078, 0x9d6a, 0xa006, 0x127f, 0x027f, 0x067f, 0x077f,
+	0x087f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c, 0xa8c5, 0x0001, 0x0078,
+	0x9dc4, 0x077e, 0x057e, 0x087e, 0x2041, 0x0000, 0x2029, 0x0001,
+	0x2c20, 0x2019, 0x0002, 0x6218, 0x097e, 0x2049, 0x0000, 0x1078,
+	0x7058, 0x097f, 0x087f, 0x2039, 0x0000, 0x1078, 0x7105, 0x1078,
+	0x9d5b, 0x057f, 0x077f, 0x007c, 0x027e, 0x047e, 0x057e, 0x077e,
+	0x0c7e, 0x157e, 0x2c20, 0x2128, 0x20a9, 0x007f, 0x2009, 0x0000,
+	0x017e, 0x037e, 0x1078, 0x4501, 0x00c0, 0x9e14, 0x2c10, 0x057e,
+	0x087e, 0x2041, 0x0000, 0x2508, 0x2029, 0x0001, 0x097e, 0x2049,
+	0x0000, 0x1078, 0x7058, 0x097f, 0x087f, 0x2039, 0x0000, 0x1078,
+	0x7105, 0x1078, 0x9d5b, 0x057f, 0x037f, 0x017f, 0x8108, 0x00f0,
+	0x9df8, 0x157f, 0x0c7f, 0x077f, 0x057f, 0x047f, 0x027f, 0x007c,
+	0x077e, 0x057e, 0x6218, 0x087e, 0x2041, 0x0000, 0x2029, 0x0001,
+	0x2019, 0x0048, 0x097e, 0x2049, 0x0000, 0x1078, 0x7058, 0x097f,
+	0x087f, 0x2039, 0x0000, 0x1078, 0x7105, 0x2c20, 0x1078, 0x9d5b,
+	0x057f, 0x077f, 0x007c, 0x027e, 0x047e, 0x057e, 0x077e, 0x0c7e,
+	0x157e, 0x2c20, 0x20a9, 0x007f, 0x2009, 0x0000, 0x017e, 0x037e,
+	0x1078, 0x4501, 0x00c0, 0x9e64, 0x2c10, 0x087e, 0x2041, 0x0000,
+	0x2828, 0x047e, 0x2021, 0x0001, 0x1078, 0xa111, 0x047f, 0x097e,
+	0x2049, 0x0000, 0x1078, 0x7058, 0x097f, 0x087f, 0x2039, 0x0000,
+	0x1078, 0x7105, 0x1078, 0x9d5b, 0x037f, 0x017f, 0x8108, 0x00f0,
+	0x9e46, 0x157f, 0x0c7f, 0x077f, 0x057f, 0x047f, 0x027f, 0x007c,
+	0x017e, 0x0f7e, 0xad82, 0xca00, 0x0048, 0x9e89, 0xad82, 0xffff,
+	0x00c8, 0x9e89, 0x6800, 0xa07d, 0x0040, 0x9e86, 0x6803, 0x0000,
+	0x6b52, 0x1078, 0x4982, 0x2f68, 0x0078, 0x9e7a, 0x6b52, 0x1078,
+	0x4982, 0x0f7f, 0x017f, 0x007c, 0x0e7e, 0x047e, 0x037e, 0x2061,
+	0xaa00, 0x2071, 0xa300, 0x7444, 0x7060, 0x8001, 0xa402, 0x00c8,
+	0x9ebb, 0x2100, 0xac06, 0x0040, 0x9ead, 0x6000, 0xa086, 0x0000,
+	0x0040, 0x9ead, 0x6008, 0xa206, 0x00c0, 0x9ead, 0x6018, 0xa1a0,
+	0x0006, 0x2424, 0xa406, 0x0040, 0x9eb7, 0xace0, 0x0010, 0x2001,
+	0xa315, 0x2004, 0xac02, 0x00c8, 0x9ebb, 0x0078, 0x9e91, 0xa085,
+	0x0001, 0x0078, 0x9ebc, 0xa006, 0x037f, 0x047f, 0x0e7f, 0x007c,
+	0x0d7e, 0x007e, 0x1078, 0x1381, 0x007f, 0x1040, 0x1328, 0x6837,
+	0x010d, 0x685e, 0x027e, 0x2010, 0x1078, 0x8a30, 0x2001, 0x0000,
+	0x0040, 0x9ed6, 0x2200, 0xa080, 0x0008, 0x2004, 0x027f, 0x684a,
+	0x6956, 0x6c46, 0x684f, 0x0000, 0xa006, 0x68b2, 0x6802, 0x683a,
+	0x685a, 0x1078, 0x4982, 0x0d7f, 0x007c, 0x6700, 0xa786, 0x0000,
+	0x0040, 0x9ef8, 0xa786, 0x0001, 0x0040, 0x9ef8, 0xa786, 0x000a,
+	0x0040, 0x9ef8, 0xa786, 0x0009, 0x0040, 0x9ef8, 0xa085, 0x0001,
+	0x007c, 0x0e7e, 0x6018, 0x2070, 0x70a0, 0xa206, 0x0e7f, 0x007c,
+	0x017e, 0x6004, 0xa08e, 0x001e, 0x00c0, 0x9f1a, 0x8007, 0x6130,
+	0xa18c, 0x00ff, 0xa105, 0x6032, 0x6007, 0x0085, 0x6003, 0x000b,
+	0x601f, 0x0005, 0x2001, 0xa5a1, 0x2004, 0x6016, 0x1078, 0x5bf8,
+	0x1078, 0x6109, 0x017f, 0x007c, 0x0005, 0x0005, 0x007c, 0x6024,
+	0xd0e4, 0x0040, 0x9f30, 0xd0cc, 0x0040, 0x9f2a, 0x1078, 0x8cfa,
+	0x0078, 0x9f30, 0x1078, 0xa134, 0x1078, 0x5a41, 0x1078, 0x753d,
+	0x007c, 0xa280, 0x0007, 0x2004, 0xa084, 0x000f, 0x0079, 0x9f38,
+	0x9f41, 0x9f41, 0x9f41, 0x9f43, 0x9f41, 0x9f43, 0x9f43, 0x9f41,
+	0x9f43, 0xa006, 0x007c, 0xa085, 0x0001, 0x007c, 0xa280, 0x0007,
+	0x2004, 0xa084, 0x000f, 0x0079, 0x9f4d, 0x9f56, 0x9f56, 0x9f56,
+	0x9f56, 0x9f56, 0x9f56, 0x9f61, 0x9f56, 0x9f56, 0x6007, 0x003b,
+	0x602b, 0x0009, 0x6013, 0x2a00, 0x6003, 0x0001, 0x1078, 0x5bf8,
+	0x007c, 0x0c7e, 0x2260, 0x1078, 0xa134, 0x603f, 0x0000, 0x6024,
+	0xc0f4, 0xc0cc, 0x6026, 0x0c7f, 0x0d7e, 0x2268, 0xa186, 0x0007,
+	0x00c0, 0x9fc2, 0x6810, 0xa005, 0x0040, 0x9f7f, 0xa080, 0x0013,
+	0x2004, 0xd0fc, 0x00c0, 0x9f7f, 0x0d7f, 0x0078, 0x9f56, 0x6007,
+	0x003a, 0x6003, 0x0001, 0x1078, 0x5bf8, 0x1078, 0x6109, 0x0c7e,
+	0x2d60, 0x6100, 0xa186, 0x0002, 0x00c0, 0xa050, 0x6010, 0xa005,
+	0x00c0, 0x9f99, 0x6000, 0xa086, 0x0007, 0x10c0, 0x1328, 0x0078,
+	0xa050, 0xa08c, 0xf000, 0x00c0, 0x9fa5, 0x0078, 0x9fa5, 0x2068,
+	0x6800, 0xa005, 0x00c0, 0x9f9f, 0x2d00, 0xa080, 0x0013, 0x2004,
+	0xa084, 0x0003, 0xa086, 0x0002, 0x00c0, 0x9fbe, 0x6010, 0x2068,
+	0x684c, 0xc0dc, 0xc0f4, 0x684e, 0x6850, 0xc0f4, 0xc0fc, 0x6852,
+	0x2009, 0x0043, 0x1078, 0x98c1, 0x0078, 0xa050, 0x2009, 0x0041,
+	0x0078, 0xa04a, 0xa186, 0x0005, 0x00c0, 0xa009, 0x6810, 0xa080,
+	0x0013, 0x2004, 0xd0bc, 0x00c0, 0x9fd0, 0x0d7f, 0x0078, 0x9f56,
+	0xd0b4, 0x0040, 0x9fd8, 0xd0fc, 0x1040, 0x1328, 0x0078, 0x9f72,
+	0x6007, 0x003a, 0x6003, 0x0001, 0x1078, 0x5bf8, 0x1078, 0x6109,
+	0x0c7e, 0x2d60, 0x6100, 0xa186, 0x0002, 0x0040, 0x9feb, 0xa186,
+	0x0004, 0x00c0, 0xa050, 0x2071, 0xa5e1, 0x7000, 0xa086, 0x0003,
+	0x00c0, 0x9ff8, 0x7004, 0xac06, 0x00c0, 0x9ff8, 0x7003, 0x0000,
+	0x6810, 0xa080, 0x0013, 0x200c, 0xc1f4, 0xc1dc, 0x2102, 0x8000,
+	0x200c, 0xc1f4, 0xc1fc, 0xc1bc, 0x2102, 0x2009, 0x0042, 0x0078,
+	0xa04a, 0x037e, 0x0d7e, 0x0d7e, 0x1078, 0x1381, 0x037f, 0x1040,
+	0x1328, 0x6837, 0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b,
+	0x0000, 0x6b5e, 0x6857, 0x0045, 0x2c00, 0x6862, 0x6034, 0x6872,
+	0x2360, 0x6024, 0xc0dd, 0x6026, 0x6018, 0xa080, 0x0028, 0x2004,
+	0xa084, 0x00ff, 0x8007, 0x6320, 0x6b4a, 0x6846, 0x684f, 0x0000,
+	0x6d6a, 0x6e66, 0x686f, 0x0001, 0x1078, 0x4982, 0x2019, 0x0045,
+	0x6008, 0x2068, 0x1078, 0x9a6a, 0x2d00, 0x600a, 0x601f, 0x0006,
+	0x6003, 0x0007, 0x6017, 0x0000, 0x603f, 0x0000, 0x0d7f, 0x037f,
+	0x0078, 0xa051, 0x603f, 0x0000, 0x6003, 0x0007, 0x1078, 0x98c1,
+	0x0c7f, 0x0d7f, 0x007c, 0xa186, 0x0013, 0x00c0, 0xa05d, 0x6004,
+	0xa082, 0x0085, 0x2008, 0x0079, 0xa077, 0xa186, 0x0027, 0x00c0,
+	0xa070, 0x1078, 0x6010, 0x037e, 0x0d7e, 0x6010, 0x2068, 0x2019,
+	0x0004, 0x1078, 0x9e70, 0x0d7f, 0x037f, 0x1078, 0x6109, 0x007c,
+	0xa186, 0x0014, 0x0040, 0xa061, 0x1078, 0x7583, 0x007c, 0xa080,
+	0xa07e, 0xa07e, 0xa07e, 0xa07e, 0xa07e, 0xa080, 0x1078, 0x1328,
+	0x1078, 0x6010, 0x6003, 0x000c, 0x1078, 0x6109, 0x007c, 0xa182,
+	0x008c, 0x00c8, 0xa091, 0xa182, 0x0085, 0x0048, 0xa091, 0x0079,
+	0xa094, 0x1078, 0x7583, 0x007c, 0xa09b, 0xa09b, 0xa09b, 0xa09b,
+	0xa09d, 0xa0bc, 0xa09b, 0x1078, 0x1328, 0x0d7e, 0x2c68, 0x1078,
+	0x74d7, 0x0040, 0xa0b7, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009,
+	0xa88e, 0x210c, 0x6136, 0x2009, 0xa88f, 0x210c, 0x613a, 0x600b,
+	0xffff, 0x6918, 0x611a, 0x601f, 0x0004, 0x1078, 0x5bf8, 0x2d60,
+	0x1078, 0x753d, 0x0d7f, 0x007c, 0x1078, 0x753d, 0x007c, 0x0e7e,
+	0x6018, 0x2070, 0x7000, 0xd0ec, 0x0e7f, 0x007c, 0x6010, 0xa080,
+	0x0013, 0x200c, 0xd1ec, 0x0040, 0xa110, 0x2001, 0xa371, 0x2004,
+	0xd0ec, 0x0040, 0xa110, 0x6003, 0x0002, 0x6024, 0xc0e5, 0x6026,
+	0xd1ac, 0x0040, 0xa0ee, 0x0f7e, 0x2c78, 0x1078, 0x488f, 0x0f7f,
+	0x0040, 0xa0ee, 0x2001, 0xa5a2, 0x2004, 0x603e, 0x2009, 0xa371,
+	0x210c, 0xd1f4, 0x00c0, 0xa10e, 0x0078, 0xa100, 0x2009, 0xa371,
+	0x210c, 0xd1f4, 0x0040, 0xa0fa, 0x6024, 0xc0e4, 0x6026, 0xa006,
+	0x0078, 0xa110, 0x2001, 0xa5a2, 0x200c, 0x8103, 0xa100, 0x603e,
+	0x6018, 0xa088, 0x002b, 0x2104, 0xa005, 0x0040, 0xa10b, 0xa088,
+	0x0003, 0x0078, 0xa103, 0x2c0a, 0x600f, 0x0000, 0xa085, 0x0001,
+	0x007c, 0x017e, 0x0c7e, 0x0e7e, 0x6120, 0xa2f0, 0x002b, 0x2e04,
+	0x2060, 0x8cff, 0x0040, 0xa130, 0x84ff, 0x00c0, 0xa123, 0x6020,
+	0xa106, 0x00c0, 0xa12b, 0x600c, 0x2072, 0x1078, 0x5a41, 0x1078,
+	0x753d, 0x0078, 0xa12d, 0xacf0, 0x0003, 0x2e64, 0x0078, 0xa119,
+	0x0e7f, 0x0c7f, 0x017f, 0x007c, 0x0d7e, 0x6018, 0xa0e8, 0x002b,
+	0x2d04, 0xa005, 0x0040, 0xa146, 0xac06, 0x0040, 0xa144, 0x2d04,
+	0xa0e8, 0x0003, 0x0078, 0xa138, 0x600c, 0x206a, 0x0d7f, 0x007c,
+	0x027e, 0x037e, 0x157e, 0x2011, 0xa325, 0x2204, 0xa084, 0x00ff,
+	0x2019, 0xa88e, 0x2334, 0xa636, 0x00c0, 0xa174, 0x8318, 0x2334,
+	0x2204, 0xa084, 0xff00, 0xa636, 0x00c0, 0xa174, 0x2011, 0xa890,
+	0x6018, 0xa098, 0x000a, 0x20a9, 0x0004, 0x1078, 0x7e55, 0x00c0,
+	0xa174, 0x2011, 0xa894, 0x6018, 0xa098, 0x0006, 0x20a9, 0x0004,
+	0x1078, 0x7e55, 0x00c0, 0xa174, 0x157f, 0x037f, 0x027f, 0x007c,
+	0x0e7e, 0x2071, 0xa300, 0x1078, 0x41f5, 0x1078, 0x260d, 0x0e7f,
+	0x007c, 0x0e7e, 0x6018, 0x2070, 0x7000, 0xd0fc, 0x0040, 0xa18a,
+	0x1078, 0xa18c, 0x0e7f, 0x007c, 0x6850, 0xc0e5, 0x6852, 0x007c,
+	0x0e7e, 0x0c7e, 0x077e, 0x067e, 0x057e, 0x047e, 0x027e, 0x017e,
+	0x127e, 0x2091, 0x8000, 0x2029, 0xa5b4, 0x252c, 0x2021, 0xa5ba,
+	0x2424, 0x2061, 0xaa00, 0x2071, 0xa300, 0x7644, 0x7060, 0xa606,
+	0x0040, 0xa1e4, 0x671c, 0xa786, 0x0001, 0x0040, 0xa1b3, 0xa786,
+	0x0008, 0x00c0, 0xa1da, 0x2500, 0xac06, 0x0040, 0xa1da, 0x2400,
+	0xac06, 0x0040, 0xa1da, 0x1078, 0x9ee5, 0x0040, 0xa1da, 0x1078,
+	0x9ef9, 0x00c0, 0xa1da, 0x6000, 0xa086, 0x0004, 0x00c0, 0xa1cc,
+	0x017e, 0x1078, 0x1749, 0x017f, 0x1078, 0x8c27, 0x00c0, 0xa1d2,
+	0x1078, 0x2839, 0x1078, 0x8c3b, 0x00c0, 0xa1d8, 0x1078, 0x7a05,
+	0x1078, 0x8c01, 0xace0, 0x0010, 0x2001, 0xa315, 0x2004, 0xac02,
+	0x00c8, 0xa1e4, 0x0078, 0xa1a3, 0x127f, 0x017f, 0x027f, 0x047f,
+	0x057f, 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x007c, 0x127e, 0x007e,
+	0x0e7e, 0x2091, 0x8000, 0x2071, 0xa340, 0xd5a4, 0x0040, 0xa1fb,
+	0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa201, 0x7030, 0x8000,
+	0x7032, 0xd5ac, 0x0040, 0xa208, 0x2071, 0xa34a, 0x1078, 0xa237,
+	0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091,
+	0x8000, 0x2071, 0xa340, 0xd5a4, 0x0040, 0xa219, 0x7034, 0x8000,
+	0x7036, 0xd5b4, 0x0040, 0xa21f, 0x7030, 0x8000, 0x7032, 0xd5ac,
+	0x0040, 0xa226, 0x2071, 0xa34a, 0x1078, 0xa237, 0x0e7f, 0x007f,
+	0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071,
+	0xa342, 0x1078, 0xa237, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x2e04,
+	0x8000, 0x2072, 0x00c8, 0xa240, 0x8e70, 0x2e04, 0x8000, 0x2072,
+	0x007c, 0x0e7e, 0x2071, 0xa340, 0x1078, 0xa237, 0x0e7f, 0x007c,
+	0x0e7e, 0x2071, 0xa344, 0x1078, 0xa237, 0x0e7f, 0x007c, 0x0001,
+	0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100,
+	0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0x6286
+};
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2100tp_length01 = 0x9260;
+#else
+unsigned short risc_code_length01 = 0x9260;
+#endif
+
diff -urN linux-2.4.16/drivers/scsi/ql2200_fw.h lia64-2.4/drivers/scsi/ql2200_fw.h
--- linux-2.4.16/drivers/scsi/ql2200_fw.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/ql2200_fw.h	Mon Jul 23 14:12:06 2001
@@ -0,0 +1,5179 @@
+/************************************************************************
+ *									*
+ *               --- ISP2200 Initiator/Target Firmware ---              *
+ *             with Fabric (Public Loop), Point-point, and              *
+ *             expanded LUN addressing for FCTAPE                       *
+ *									*
+ ************************************************************************
+  Copyright (C) 2000,2001 Qlogic Corporation 
+  (www.qlogic.com)
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+ ************************************************************************/
+/*
+ *	Firmware Version 2.01.34 (18:00 Jun 05, 2001)
+ */
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2200tp_version = 2*1024+1;
+#else
+unsigned short risc_code_version = 2*1024+1;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned char fw2200tp_version_str[] = {2,1,34};
+#else
+unsigned char firmware_version[] = {2,1,34};
+#endif
+
+#ifdef UNIQUE_FW_NAME
+#define fw2200tp_VERSION_STRING "2.01.34"
+#else
+#define FW_VERSION_STRING "2.01.34"
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2200tp_addr01 = 0x1000 ;
+#else
+unsigned short risc_code_addr01 = 0x1000 ;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2200tp_code01[] = { 
+#else
+unsigned short risc_code01[] = { 
+#endif
+	0x0470, 0x0000, 0x0000, 0xa019, 0x0000, 0x0002, 0x0001, 0x0022,
+	0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030,
+	0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
+	0x5449, 0x4f4e, 0x2049, 0x5350, 0x3232, 0x3030, 0x2046, 0x6972,
+	0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
+	0x322e, 0x3031, 0x2e33, 0x3420, 0x2020, 0x2020, 0x2400, 0x20c1,
+	0x0005, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, 0xb5ff, 0x2091,
+	0x2000, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x2843,
+	0x2051, 0xb100, 0x2a70, 0x2029, 0xe800, 0x2031, 0xffff, 0x2039,
+	0xe7e9, 0x2021, 0x0200, 0x0804, 0x144d, 0x20a1, 0xb019, 0xa00e,
+	0x20a9, 0x07e7, 0x41a4, 0x3400, 0x755e, 0x7662, 0x775a, 0x7466,
+	0x746a, 0x20a1, 0xb800, 0x7160, 0x810d, 0x810d, 0x810d, 0x810d,
+	0xa18c, 0x000f, 0x2001, 0x000b, 0xa112, 0xa00e, 0x21a8, 0x41a4,
+	0x3400, 0x8211, 0x1dd8, 0x7160, 0x3400, 0xa102, 0x0120, 0x0218,
+	0x20a8, 0xa00e, 0x41a4, 0x3800, 0xd08c, 0x01d8, 0x2009, 0xb100,
+	0x810d, 0x810d, 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0001,
+	0xa112, 0x20a1, 0x1000, 0xa00e, 0x21a8, 0x41a4, 0x8211, 0x1de0,
+	0x2009, 0xb100, 0x3400, 0xa102, 0x0120, 0x0218, 0x20a8, 0xa00e,
+	0x41a4, 0x080c, 0x1400, 0x080c, 0x1617, 0x080c, 0x17b0, 0x080c,
+	0x1ebd, 0x080c, 0x4a74, 0x080c, 0x828d, 0x080c, 0x15a0, 0x080c,
+	0x2d8c, 0x080c, 0x5b8b, 0x080c, 0x51aa, 0x080c, 0x668a, 0x080c,
+	0x23ea, 0x080c, 0x68d4, 0x080c, 0x6194, 0x080c, 0x22de, 0x080c,
+	0x23b8, 0x2091, 0x3009, 0x7823, 0x0000, 0x1004, 0x10c5, 0x7820,
+	0xa086, 0x0002, 0x1150, 0x7823, 0x4000, 0x0e04, 0x10bd, 0x781b,
+	0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000,
+	0x2a70, 0x7000, 0xa08e, 0x0003, 0x1158, 0x080c, 0x3d97, 0x080c,
+	0x2db3, 0x080c, 0x5bd9, 0x080c, 0x5359, 0x080c, 0x66b4, 0x0c80,
+	0x000b, 0x0c98, 0x10e4, 0x10e5, 0x1207, 0x10e2, 0x12d0, 0x13fd,
+	0x13fe, 0x13ff, 0x080c, 0x14fa, 0x0005, 0x0126, 0x00f6, 0x2091,
+	0x8000, 0x7000, 0xa086, 0x0001, 0x1904, 0x11d5, 0x080c, 0x156d,
+	0x080c, 0x58d5, 0x0150, 0x080c, 0x58fb, 0x15a0, 0x2079, 0x0100,
+	0x7828, 0xa085, 0x1800, 0x782a, 0x0468, 0x080c, 0x5816, 0x7000,
+	0xa086, 0x0001, 0x1904, 0x11d5, 0x7088, 0xa086, 0x0028, 0x1904,
+	0x11d5, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100, 0x7827,
+	0xffff, 0x7a28, 0xa295, 0x1e2f, 0x7a2a, 0x2011, 0x57ea, 0x080c,
+	0x6742, 0x2011, 0x57f7, 0x080c, 0x6742, 0x2011, 0x494f, 0x080c,
+	0x6742, 0x2011, 0x8030, 0x2019, 0x0000, 0x7087, 0x0000, 0x080c,
+	0x1d33, 0x00e8, 0x080c, 0x4305, 0x2079, 0x0100, 0x7844, 0xa005,
+	0x1904, 0x11d5, 0x2011, 0x494f, 0x080c, 0x6742, 0x2011, 0x57f7,
+	0x080c, 0x6742, 0x080c, 0x1d33, 0x2001, 0xb38d, 0x2004, 0x780e,
+	0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, 0x8010, 0x73c8, 0x080c,
+	0x3d5b, 0x7238, 0xc284, 0x723a, 0x2001, 0xb10c, 0x200c, 0xc1ac,
+	0x2102, 0x080c, 0x7c1d, 0x2011, 0x0004, 0x080c, 0x9870, 0x080c,
+	0x50bf, 0x080c, 0x58d5, 0x0158, 0x080c, 0x4a5d, 0x0140, 0x7087,
+	0x0001, 0x70c3, 0x0000, 0x080c, 0x44a2, 0x0804, 0x11d5, 0x080c,
+	0x517b, 0x0120, 0x7a0c, 0xc2b4, 0x7a0e, 0x0050, 0x080c, 0x9c16,
+	0x70d0, 0xd09c, 0x1128, 0x709c, 0xa005, 0x0110, 0x080c, 0x4a3b,
+	0x70db, 0x0000, 0x70d7, 0x0000, 0x72d0, 0x080c, 0x58d5, 0x1178,
+	0x2011, 0x0000, 0x0016, 0x080c, 0x27c4, 0x2019, 0xb38f, 0x211a,
+	0x001e, 0x704f, 0xffff, 0x7053, 0x00ef, 0x7073, 0x0000, 0x2079,
+	0xb152, 0x7804, 0xd0ac, 0x0108, 0xc295, 0x72d2, 0x080c, 0x58d5,
+	0x0118, 0xa296, 0x0004, 0x0508, 0x2011, 0x0001, 0x080c, 0x9870,
+	0x7097, 0x0000, 0x709b, 0xffff, 0x7003, 0x0002, 0x00fe, 0x080c,
+	0x2991, 0x2011, 0x0005, 0x080c, 0x7d52, 0x080c, 0x6e9e, 0x080c,
+	0x58d5, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x27c4,
+	0x61e2, 0x001e, 0x00ce, 0x012e, 0x00d0, 0x7097, 0x0000, 0x709b,
+	0xffff, 0x7003, 0x0002, 0x2011, 0x0005, 0x080c, 0x7d52, 0x080c,
+	0x6e9e, 0x080c, 0x58d5, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016,
+	0x080c, 0x27c4, 0x61e2, 0x001e, 0x00ce, 0x00fe, 0x012e, 0x0005,
+	0x00c6, 0x080c, 0x58d5, 0x1118, 0x20a9, 0x0100, 0x0010, 0x20a9,
+	0x0082, 0x080c, 0x58d5, 0x1118, 0x2009, 0x0000, 0x0010, 0x2009,
+	0x007e, 0x0016, 0x0026, 0x0036, 0x2110, 0x0026, 0x2019, 0x0029,
+	0x080c, 0x7f67, 0x002e, 0x080c, 0xaf53, 0x003e, 0x002e, 0x001e,
+	0x080c, 0x2c6e, 0x8108, 0x1f04, 0x11e9, 0x00ce, 0x706f, 0x0000,
+	0x7070, 0xa084, 0x00ff, 0x7072, 0x709f, 0x0000, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x7000, 0xa086, 0x0002, 0x1904, 0x12ce, 0x7098,
+	0xa086, 0xffff, 0x0130, 0x080c, 0x2991, 0x080c, 0x6e9e, 0x0804,
+	0x12ce, 0x70d0, 0xd0ac, 0x1110, 0xd09c, 0x0540, 0xd084, 0x0530,
+	0x0006, 0x0016, 0x2001, 0x0103, 0x2009, 0xb38d, 0x210c, 0x2102,
+	0x001e, 0x000e, 0xd08c, 0x01d0, 0x70d4, 0xa086, 0xffff, 0x0190,
+	0x080c, 0x2af0, 0x080c, 0x6e9e, 0x70d0, 0xd094, 0x1904, 0x12ce,
+	0x2011, 0x0001, 0x2019, 0x0000, 0x080c, 0x2b26, 0x080c, 0x6e9e,
+	0x0804, 0x12ce, 0x70d8, 0xa005, 0x1904, 0x12ce, 0x7094, 0xa005,
+	0x1904, 0x12ce, 0x70d0, 0xd0a4, 0x0118, 0xd0b4, 0x0904, 0x12ce,
+	0x080c, 0x517b, 0x1904, 0x12ce, 0x2001, 0xb153, 0x2004, 0xd0ac,
+	0x01c8, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016,
+	0x080c, 0x4e21, 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, 0x8108,
+	0x1f04, 0x125f, 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, 0x015e,
+	0x0804, 0x12ce, 0x0006, 0x0016, 0x2001, 0x0103, 0x2009, 0xb38d,
+	0x210c, 0x2102, 0x001e, 0x000e, 0xa006, 0x2009, 0x0700, 0x20a9,
+	0x0002, 0x20a1, 0xb3c7, 0x40a1, 0x706c, 0x8007, 0x7170, 0x810f,
+	0x20a9, 0x0002, 0x40a1, 0x2009, 0x0000, 0x080c, 0x14e0, 0x2001,
+	0x0000, 0x810f, 0x20a9, 0x0002, 0x40a1, 0xa006, 0x2009, 0x0200,
+	0x20a9, 0x0002, 0x20a1, 0xb3d7, 0x40a1, 0x7030, 0xc08c, 0x7032,
+	0x7003, 0x0003, 0x709b, 0xffff, 0x080c, 0x1566, 0xa006, 0x080c,
+	0x269e, 0x080c, 0x3dcd, 0x00f6, 0x2079, 0x0100, 0x080c, 0x58fb,
+	0x0150, 0x080c, 0x58d5, 0x7828, 0x0118, 0xa084, 0xe1ff, 0x0010,
+	0xa084, 0xffdf, 0x782a, 0x00fe, 0x2001, 0xb3da, 0x2004, 0xa086,
+	0x0005, 0x1120, 0x2011, 0x0000, 0x080c, 0x7d52, 0x2011, 0x0000,
+	0x080c, 0x7d5c, 0x080c, 0x6e9e, 0x080c, 0x6f5b, 0x012e, 0x0005,
+	0x0016, 0x0046, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2079, 0x0100,
+	0x2009, 0xb133, 0x2104, 0xa005, 0x1110, 0x080c, 0x27f0, 0x2009,
+	0x00f7, 0x080c, 0x4a24, 0x7940, 0xa18c, 0x0010, 0x7942, 0x7924,
+	0xd1b4, 0x0110, 0x7827, 0x0040, 0xd19c, 0x0110, 0x7827, 0x0008,
+	0x0006, 0x0036, 0x0156, 0x7954, 0xd1ac, 0x1904, 0x133e, 0x080c,
+	0x58e7, 0x0158, 0x080c, 0x58fb, 0x1128, 0x2001, 0xb39e, 0x2003,
+	0x0000, 0x0070, 0x080c, 0x58dd, 0x0dc0, 0x2001, 0xb39e, 0x2003,
+	0xaaaa, 0x2001, 0xb39f, 0x2003, 0x0001, 0x080c, 0x5816, 0x0058,
+	0x080c, 0x58d5, 0x0140, 0x2009, 0x00f8, 0x080c, 0x4a24, 0x7843,
+	0x0090, 0x7843, 0x0010, 0x20a9, 0x09c4, 0x7820, 0xd09c, 0x1138,
+	0x080c, 0x58d5, 0x0138, 0x7824, 0xd0ac, 0x1904, 0x13e4, 0x1f04,
+	0x131d, 0x0070, 0x7824, 0x080c, 0x58f1, 0x0118, 0xd0ac, 0x1904,
+	0x13e4, 0xa084, 0x1800, 0x0d98, 0x7003, 0x0001, 0x0804, 0x13e4,
+	0x2001, 0x0001, 0x080c, 0x269e, 0x0804, 0x13f3, 0x7850, 0xa084,
+	0x0180, 0x7852, 0x782f, 0x0020, 0x20a9, 0x0046, 0x1d04, 0x1346,
+	0x2091, 0x6000, 0x1f04, 0x1346, 0x7850, 0xa084, 0x0180, 0xa085,
+	0x0400, 0x7852, 0x782f, 0x0000, 0x080c, 0x58e7, 0x0158, 0x080c,
+	0x58fb, 0x1128, 0x2001, 0xb39e, 0x2003, 0x0000, 0x0070, 0x080c,
+	0x58dd, 0x0dc0, 0x2001, 0xb39e, 0x2003, 0xaaaa, 0x2001, 0xb39f,
+	0x2003, 0x0001, 0x080c, 0x5816, 0x0020, 0x2009, 0x00f8, 0x080c,
+	0x4a24, 0x20a9, 0x000e, 0xe000, 0x1f04, 0x1373, 0x7850, 0xa084,
+	0x0180, 0xa085, 0x1400, 0x7852, 0x080c, 0x58d5, 0x0120, 0x7843,
+	0x0090, 0x7843, 0x0010, 0x2021, 0xe678, 0x2019, 0xea60, 0x7820,
+	0xd09c, 0x1558, 0x080c, 0x58d5, 0x05b8, 0x7824, 0xd0ac, 0x1904,
+	0x13e4, 0x080c, 0x58fb, 0x1508, 0x0046, 0x2021, 0x0190, 0x8421,
+	0x1df0, 0x004e, 0x8421, 0x11c8, 0x7827, 0x0048, 0x20a9, 0x01f4,
+	0x1d04, 0x13a0, 0x2091, 0x6000, 0x1f04, 0x13a0, 0x7824, 0xa084,
+	0x0068, 0x15a8, 0x2001, 0xb39e, 0x2003, 0xaaaa, 0x2001, 0xb39f,
+	0x2003, 0x0001, 0x7003, 0x0001, 0x0478, 0x8319, 0x1980, 0x2009,
+	0xb133, 0x2104, 0x8000, 0x200a, 0xa084, 0xfff0, 0x0120, 0x200b,
+	0x0000, 0x080c, 0x27f0, 0x00d8, 0x080c, 0x58e7, 0x1140, 0xa4a2,
+	0x0064, 0x1128, 0x080c, 0x58ac, 0x7003, 0x0001, 0x00a8, 0x7827,
+	0x1800, 0xe000, 0xe000, 0x7824, 0x080c, 0x58f1, 0x0110, 0xd0ac,
+	0x1158, 0xa084, 0x1800, 0x09c8, 0x7003, 0x0001, 0x0028, 0x2001,
+	0x0001, 0x080c, 0x269e, 0x0048, 0x2001, 0xb133, 0x2003, 0x0000,
+	0x7827, 0x0048, 0x7828, 0xc09d, 0x782a, 0x7850, 0xa084, 0x0180,
+	0xa085, 0x0400, 0x7852, 0x015e, 0x003e, 0x000e, 0x080c, 0x153d,
+	0x012e, 0x00fe, 0x004e, 0x001e, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x2a70, 0x2001, 0xb39e, 0x2003, 0x0000, 0x7087, 0x0000, 0x2009,
+	0x0100, 0x2104, 0xa082, 0x0002, 0x0218, 0x704f, 0xffff, 0x0010,
+	0x704f, 0x0000, 0x7057, 0xffff, 0x706f, 0x0000, 0x7073, 0x0000,
+	0x080c, 0x9c16, 0x2061, 0xb38e, 0x6003, 0x0909, 0x6007, 0x0000,
+	0x600b, 0x8800, 0x600f, 0x0200, 0x6013, 0x00ff, 0x6017, 0x0003,
+	0x601b, 0x0000, 0x601f, 0x07d0, 0x2061, 0xb396, 0x6003, 0x8000,
+	0x6007, 0x0000, 0x600b, 0x0000, 0x600f, 0x0200, 0x6013, 0x00ff,
+	0x6017, 0x0000, 0x601b, 0x0001, 0x601f, 0x0000, 0x2061, 0xb3b8,
+	0x6003, 0x514c, 0x6007, 0x4f47, 0x600b, 0x4943, 0x600f, 0x2020,
+	0x2001, 0xb127, 0x2003, 0x0000, 0x0005, 0x04a0, 0x2011, 0x0000,
+	0x81ff, 0x0570, 0xa186, 0x0001, 0x1148, 0x2031, 0x8fff, 0x2039,
+	0xd001, 0x2021, 0x0100, 0x2029, 0xd000, 0x00e8, 0xa186, 0x0002,
+	0x1118, 0x2011, 0x0000, 0x00b8, 0xa186, 0x0005, 0x1118, 0x2011,
+	0x0001, 0x0088, 0xa186, 0x0009, 0x1118, 0x2011, 0x0002, 0x0058,
+	0xa186, 0x000a, 0x1118, 0x2011, 0x0002, 0x0028, 0xa186, 0x0055,
+	0x1110, 0x2011, 0x0003, 0x3800, 0xa084, 0xfffc, 0xa205, 0x20c0,
+	0x0804, 0x104d, 0xa00e, 0x2011, 0x0003, 0x2019, 0x1489, 0x0804,
+	0x14da, 0x2019, 0xaaaa, 0x2061, 0xffff, 0x2c14, 0x2362, 0xe000,
+	0xe000, 0x2c04, 0xa306, 0x2262, 0x1110, 0xc1b5, 0xc1a5, 0x2011,
+	0x0000, 0x2019, 0x149c, 0x04f0, 0x2019, 0xaaaa, 0x2061, 0xffff,
+	0x2c14, 0x2362, 0xe000, 0xe000, 0x2c1c, 0x2061, 0x7fff, 0xe000,
+	0xe000, 0x2c04, 0x2061, 0xffff, 0x2262, 0xa306, 0x0110, 0xc18d,
+	0x0008, 0xc185, 0x2011, 0x0002, 0x2019, 0x14b7, 0x0418, 0x2061,
+	0xffff, 0x2019, 0xaaaa, 0x2c14, 0x2362, 0xe000, 0xe000, 0x2c04,
+	0x2262, 0xa306, 0x1180, 0x2c14, 0x2362, 0xe000, 0xe000, 0x2c1c,
+	0x2061, 0x7fff, 0x2c04, 0x2061, 0xffff, 0x2262, 0xa306, 0x1110,
+	0xc195, 0x0008, 0xc19d, 0x2011, 0x0001, 0x2019, 0x14d8, 0x0010,
+	0x0804, 0x144e, 0x3800, 0xa084, 0xfffc, 0xa205, 0x20c0, 0x0837,
+	0x2011, 0x0000, 0x080c, 0x4e21, 0x1178, 0x6004, 0xa0c4, 0x00ff,
+	0xa8c6, 0x0006, 0x0128, 0xa0c4, 0xff00, 0xa8c6, 0x0600, 0x1120,
+	0xa186, 0x0080, 0x0108, 0x8210, 0x8108, 0xa186, 0x0100, 0x1d50,
+	0x2208, 0x0005, 0x2091, 0x8000, 0x0e04, 0x14fc, 0x0006, 0x0016,
+	0x2079, 0x0000, 0x7818, 0xd084, 0x1de8, 0x001e, 0x792e, 0x000e,
+	0x782a, 0x000e, 0x7826, 0x3900, 0x783a, 0x7823, 0x8002, 0x781b,
+	0x0001, 0x2091, 0x5000, 0x0126, 0x0156, 0x0146, 0x20a9, 0x0010,
+	0x20a1, 0xb4fc, 0x2091, 0x2000, 0x40a1, 0x20a9, 0x0010, 0x2091,
+	0x2200, 0x40a1, 0x20a9, 0x0010, 0x2091, 0x2400, 0x40a1, 0x20a9,
+	0x0010, 0x2091, 0x2600, 0x40a1, 0x20a9, 0x0010, 0x2091, 0x2800,
+	0x40a1, 0x014e, 0x015e, 0x012e, 0x2079, 0xb100, 0x7803, 0x0005,
+	0x2091, 0x4080, 0x04c9, 0x0cf8, 0x0005, 0x0006, 0x080c, 0x1588,
+	0x1518, 0x00f6, 0x2079, 0xb123, 0x2f04, 0x8000, 0x207a, 0xa082,
+	0x000f, 0x0258, 0xa006, 0x207a, 0x2079, 0xb125, 0x2f04, 0xa084,
+	0x0001, 0xa086, 0x0001, 0x207a, 0x0070, 0x2079, 0xb125, 0x2f7c,
+	0x8fff, 0x1128, 0x2001, 0x0c03, 0x2003, 0x0040, 0x0020, 0x2001,
+	0x0c03, 0x2003, 0x00c0, 0x00fe, 0x000e, 0x0005, 0x0409, 0x1120,
+	0x2001, 0x0c03, 0x2003, 0x0080, 0x0005, 0x00d1, 0x1120, 0x2001,
+	0x0c03, 0x2003, 0x0040, 0x0005, 0x0006, 0x0091, 0x1178, 0x2001,
+	0x0c03, 0x2003, 0x0040, 0x2009, 0x0fff, 0x00a1, 0x2001, 0x0c03,
+	0x2003, 0x0080, 0x2009, 0x0fff, 0x0069, 0x0c88, 0x000e, 0x0005,
+	0x00c6, 0x2061, 0x0c00, 0x2c04, 0xa084, 0x00ff, 0xa086, 0x00aa,
+	0x00ce, 0x0005, 0x0156, 0x0126, 0xa18c, 0x0fff, 0x21a8, 0x1d04,
+	0x1597, 0x2091, 0x6000, 0x1f04, 0x1597, 0x012e, 0x015e, 0x0005,
+	0x2071, 0xb100, 0x715c, 0x712e, 0x2021, 0x0001, 0xa190, 0x0030,
+	0xa298, 0x0030, 0x0240, 0x7060, 0xa302, 0x1228, 0x220a, 0x2208,
+	0x2310, 0x8420, 0x0ca8, 0x3800, 0xd08c, 0x0148, 0x7060, 0xa086,
+	0xb100, 0x0128, 0x7063, 0xb100, 0x2011, 0x1000, 0x0c48, 0x200b,
+	0x0000, 0x74ae, 0x74b2, 0x0005, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x2071, 0xb100, 0x70b0, 0xa0ea, 0x0010, 0x0268, 0x8001, 0x70b2,
+	0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, 0x0000,
+	0x012e, 0x00ee, 0x0005, 0xa06e, 0x0cd8, 0x00e6, 0x2071, 0xb100,
+	0x0126, 0x2091, 0x8000, 0x70b0, 0x8001, 0x0260, 0x70b2, 0x702c,
+	0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, 0x012e,
+	0x00ee, 0x0005, 0xa06e, 0x0cd8, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x2071, 0xb100, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0, 0x8000,
+	0x70b2, 0x012e, 0x00ee, 0x0005, 0x8dff, 0x0138, 0x6804, 0x6807,
+	0x0000, 0x0006, 0x0c49, 0x00de, 0x0cb8, 0x0005, 0x00e6, 0x2071,
+	0xb100, 0x70b0, 0xa08a, 0x0010, 0xa00d, 0x00ee, 0x0005, 0x00e6,
+	0x2071, 0xb408, 0x7007, 0x0000, 0x701b, 0x0000, 0x701f, 0x0000,
+	0x2071, 0x0000, 0x7010, 0xa085, 0x8004, 0x7012, 0x00ee, 0x0005,
+	0x00e6, 0x2270, 0x700b, 0x0000, 0x2071, 0xb408, 0x7018, 0xa088,
+	0xb411, 0x220a, 0x8000, 0xa084, 0x0007, 0x701a, 0x7004, 0xa005,
+	0x1128, 0x00f6, 0x2079, 0x0010, 0x0081, 0x00fe, 0x00ee, 0x0005,
+	0x00e6, 0x2071, 0xb408, 0x7004, 0xa005, 0x1128, 0x00f6, 0x2079,
+	0x0010, 0x0019, 0x00fe, 0x00ee, 0x0005, 0x7000, 0x0002, 0x1653,
+	0x16b7, 0x16d4, 0x16d4, 0x7018, 0x711c, 0xa106, 0x1118, 0x7007,
+	0x0000, 0x0005, 0x00d6, 0xa180, 0xb411, 0x2004, 0x700a, 0x2068,
+	0x8108, 0xa18c, 0x0007, 0x711e, 0x7803, 0x0026, 0x6824, 0x7832,
+	0x6828, 0x7836, 0x682c, 0x783a, 0x6830, 0x783e, 0x6810, 0x700e,
+	0x680c, 0x7016, 0x6804, 0x00de, 0xd084, 0x0120, 0x7007, 0x0001,
+	0x0029, 0x0005, 0x7007, 0x0002, 0x00b1, 0x0005, 0x0016, 0x0026,
+	0x710c, 0x2011, 0x0040, 0xa182, 0x0040, 0x1210, 0x2110, 0xa006,
+	0x700e, 0x7212, 0x8203, 0x7822, 0x7803, 0x0020, 0x7803, 0x0041,
+	0x002e, 0x001e, 0x0005, 0x0016, 0x0026, 0x0136, 0x0146, 0x0156,
+	0x7014, 0x2098, 0x20a1, 0x0014, 0x7803, 0x0026, 0x710c, 0x2011,
+	0x0040, 0xa182, 0x0040, 0x1210, 0x2110, 0xa006, 0x700e, 0x22a8,
+	0x53a6, 0x8203, 0x7822, 0x7803, 0x0020, 0x3300, 0x7016, 0x7803,
+	0x0001, 0x015e, 0x014e, 0x013e, 0x002e, 0x001e, 0x0005, 0x0136,
+	0x0146, 0x0156, 0x2099, 0xb1fa, 0x20a1, 0x0018, 0x20a9, 0x0008,
+	0x53a3, 0x7803, 0x0020, 0x0126, 0x2091, 0x8000, 0x7803, 0x0041,
+	0x7007, 0x0003, 0x7000, 0xc084, 0x7002, 0x700b, 0xb1f5, 0x012e,
+	0x015e, 0x014e, 0x013e, 0x0005, 0x0136, 0x0146, 0x0156, 0x2001,
+	0xb229, 0x209c, 0x20a1, 0x0014, 0x7803, 0x0026, 0x2001, 0xb22a,
+	0x20ac, 0x53a6, 0x2099, 0xb22b, 0x20a1, 0x0018, 0x20a9, 0x0008,
+	0x53a3, 0x7803, 0x0020, 0x0126, 0x2091, 0x8000, 0x7803, 0x0001,
+	0x7007, 0x0004, 0x7000, 0xc08c, 0x7002, 0x700b, 0xb226, 0x012e,
+	0x015e, 0x014e, 0x013e, 0x0005, 0x0016, 0x00e6, 0x2071, 0xb408,
+	0x00f6, 0x2079, 0x0010, 0x7904, 0x7803, 0x0002, 0xd1fc, 0x0120,
+	0xa18c, 0x0700, 0x7004, 0x0023, 0x00fe, 0x00ee, 0x001e, 0x0005,
+	0x164d, 0x1717, 0x1745, 0x176f, 0x179f, 0x1716, 0x0cf8, 0xa18c,
+	0x0700, 0x1528, 0x0136, 0x0146, 0x0156, 0x7014, 0x20a0, 0x2099,
+	0x0014, 0x7803, 0x0040, 0x7010, 0x20a8, 0x53a5, 0x3400, 0x7016,
+	0x015e, 0x014e, 0x013e, 0x700c, 0xa005, 0x0570, 0x7830, 0x7832,
+	0x7834, 0x7836, 0x080c, 0x167e, 0x0005, 0x7008, 0xa080, 0x0002,
+	0x2003, 0x0100, 0x7007, 0x0000, 0x080c, 0x164d, 0x0005, 0x7008,
+	0xa080, 0x0002, 0x2003, 0x0200, 0x0ca8, 0xa18c, 0x0700, 0x1150,
+	0x700c, 0xa005, 0x0188, 0x7830, 0x7832, 0x7834, 0x7836, 0x080c,
+	0x1693, 0x0005, 0x7008, 0xa080, 0x0002, 0x2003, 0x0200, 0x7007,
+	0x0000, 0x080c, 0x164d, 0x0005, 0x00d6, 0x7008, 0x2068, 0x7830,
+	0x6826, 0x7834, 0x682a, 0x7838, 0x682e, 0x783c, 0x6832, 0x680b,
+	0x0100, 0x00de, 0x7007, 0x0000, 0x080c, 0x164d, 0x0005, 0xa18c,
+	0x0700, 0x1540, 0x0136, 0x0146, 0x0156, 0x2001, 0xb1f8, 0x2004,
+	0xa080, 0x000d, 0x20a0, 0x2099, 0x0014, 0x7803, 0x0040, 0x20a9,
+	0x0020, 0x53a5, 0x2001, 0xb1fa, 0x2004, 0xd0bc, 0x0148, 0x2001,
+	0xb203, 0x2004, 0xa080, 0x000d, 0x20a0, 0x20a9, 0x0020, 0x53a5,
+	0x015e, 0x014e, 0x013e, 0x7007, 0x0000, 0x080c, 0x5c70, 0x080c,
+	0x164d, 0x0005, 0x2011, 0x8003, 0x080c, 0x3d5b, 0x0cf8, 0xa18c,
+	0x0700, 0x1148, 0x2001, 0xb228, 0x2003, 0x0100, 0x7007, 0x0000,
+	0x080c, 0x164d, 0x0005, 0x2011, 0x8004, 0x080c, 0x3d5b, 0x0cf8,
+	0x0126, 0x2091, 0x2200, 0x2079, 0x0030, 0x2071, 0xb419, 0x7003,
+	0x0000, 0x700f, 0xb41f, 0x7013, 0xb41f, 0x780f, 0x00f6, 0x7803,
+	0x0004, 0x012e, 0x0005, 0x6934, 0xa184, 0x0007, 0x0002, 0x17cf,
+	0x180d, 0x17cf, 0x17cf, 0x17cf, 0x17f5, 0x17dc, 0x17d3, 0xa085,
+	0x0001, 0x0804, 0x1827, 0x684c, 0xd0bc, 0x0dc8, 0x6860, 0x682e,
+	0x685c, 0x682a, 0x6858, 0x04c8, 0xa18c, 0x00ff, 0xa186, 0x001e,
+	0x1d70, 0x684c, 0xd0bc, 0x0d58, 0x6860, 0x682e, 0x685c, 0x682a,
+	0x6804, 0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080,
+	0x21f9, 0x2005, 0x6832, 0x6858, 0x0440, 0xa18c, 0x00ff, 0xa186,
+	0x0015, 0x19a8, 0x684c, 0xd0ac, 0x0990, 0x6804, 0x681a, 0xa080,
+	0x000d, 0x2004, 0xa084, 0x000f, 0xa080, 0x21f9, 0x2005, 0x6832,
+	0xa006, 0x682e, 0x682a, 0x6858, 0x0080, 0x684c, 0xd0ac, 0x0904,
+	0x17cf, 0xa006, 0x682e, 0x682a, 0x6858, 0xa18c, 0x000f, 0xa188,
+	0x21f9, 0x210d, 0x6932, 0x2d08, 0x691a, 0x6826, 0x684c, 0xc0dd,
+	0x684e, 0xa006, 0x680a, 0x697c, 0x6912, 0x6980, 0x6916, 0x0005,
+	0x20e1, 0x0007, 0x20e1, 0x2000, 0x2001, 0x020a, 0x2004, 0x82ff,
+	0x01a8, 0xa280, 0x0004, 0x00d6, 0x206c, 0x684c, 0xd0dc, 0x1150,
+	0x080c, 0x17c3, 0x0138, 0x00de, 0xa280, 0x0000, 0x2003, 0x0002,
+	0xa016, 0x0020, 0x6808, 0x8000, 0x680a, 0x00de, 0x0126, 0x0046,
+	0x0036, 0x0026, 0x2091, 0x2200, 0x002e, 0x003e, 0x004e, 0x7000,
+	0xa005, 0x01d0, 0x710c, 0x220a, 0x8108, 0x230a, 0x8108, 0x240a,
+	0x8108, 0xa182, 0xb43a, 0x0210, 0x2009, 0xb41f, 0x710e, 0x7010,
+	0xa102, 0xa082, 0x0009, 0x0118, 0xa080, 0x001b, 0x1118, 0x2009,
+	0x0138, 0x200a, 0x012e, 0x0005, 0x7206, 0x2001, 0x186a, 0x0006,
+	0x2260, 0x0804, 0x1987, 0x0126, 0x0026, 0x0036, 0x00c6, 0x0006,
+	0x2091, 0x2200, 0x000e, 0x004e, 0x003e, 0x002e, 0x00d6, 0x00c6,
+	0x2460, 0x6110, 0x2168, 0x6a62, 0x6b5e, 0xa005, 0x0904, 0x18cc,
+	0x6808, 0xa005, 0x0904, 0x1903, 0x7000, 0xa005, 0x1108, 0x0488,
+	0x700c, 0x7110, 0xa106, 0x1904, 0x190b, 0x7004, 0xa406, 0x1548,
+	0x2001, 0x0005, 0x2004, 0xd08c, 0x0168, 0x0046, 0x080c, 0x1a86,
+	0x004e, 0x2460, 0x6010, 0xa080, 0x0002, 0x2004, 0xa005, 0x0904,
+	0x1903, 0x0c10, 0x2001, 0x0207, 0x2004, 0xd09c, 0x1d48, 0x7804,
+	0xa084, 0x6000, 0x0120, 0xa086, 0x6000, 0x0108, 0x0c08, 0x7818,
+	0x6812, 0x781c, 0x6816, 0x7803, 0x0004, 0x7003, 0x0000, 0x7004,
+	0x2060, 0x6100, 0xa18e, 0x0004, 0x1904, 0x190b, 0x2009, 0x0048,
+	0x080c, 0x831a, 0x0804, 0x190b, 0x6808, 0xa005, 0x05a0, 0x7000,
+	0xa005, 0x0588, 0x700c, 0x7110, 0xa106, 0x1118, 0x7004, 0xa406,
+	0x1550, 0x2001, 0x0005, 0x2004, 0xd08c, 0x0160, 0x0046, 0x080c,
+	0x1a86, 0x004e, 0x2460, 0x6010, 0xa080, 0x0002, 0x2004, 0xa005,
+	0x01d0, 0x0c28, 0x2001, 0x0207, 0x2004, 0xd09c, 0x1d50, 0x2001,
+	0x0005, 0x2004, 0xd08c, 0x1d50, 0x7804, 0xa084, 0x6000, 0x0118,
+	0xa086, 0x6000, 0x19f0, 0x7818, 0x6812, 0x781c, 0x6816, 0x7803,
+	0x0004, 0x7003, 0x0000, 0x6100, 0xa18e, 0x0004, 0x1120, 0x2009,
+	0x0048, 0x080c, 0x831a, 0x00ce, 0x00de, 0x012e, 0x0005, 0x00f6,
+	0x00e6, 0x0026, 0x0036, 0x0046, 0x0056, 0x2071, 0xb419, 0x7000,
+	0xa086, 0x0000, 0x0904, 0x1965, 0x7004, 0xac06, 0x15c0, 0x2079,
+	0x0030, 0x7000, 0xa086, 0x0003, 0x0590, 0x7804, 0xd0fc, 0x1560,
+	0x2001, 0x0207, 0x2004, 0xd09c, 0x1dc0, 0x7804, 0xd0fc, 0x1520,
+	0x080c, 0x1db4, 0x0026, 0x0056, 0x7803, 0x0004, 0x7804, 0xd0ac,
+	0x1de8, 0x7803, 0x0002, 0x7803, 0x0009, 0x7003, 0x0003, 0x7007,
+	0x0000, 0x005e, 0x002e, 0x2001, 0x015d, 0x2003, 0x0000, 0x080c,
+	0x58d5, 0x1118, 0x080c, 0x5957, 0x0050, 0x2001, 0x0160, 0x2502,
+	0x2001, 0x0138, 0x2202, 0x0018, 0x080c, 0x1a86, 0x0800, 0x0156,
+	0x20a9, 0x0009, 0x2009, 0xb41f, 0x2104, 0xac06, 0x1108, 0x200a,
+	0xa188, 0x0003, 0x1f04, 0x195c, 0x015e, 0x005e, 0x004e, 0x003e,
+	0x002e, 0x00ee, 0x00fe, 0x0005, 0x700c, 0x7110, 0xa106, 0x0904,
+	0x19f7, 0x2104, 0x7006, 0x2060, 0x8108, 0x211c, 0x8108, 0x2124,
+	0x8108, 0xa182, 0xb43a, 0x0210, 0x2009, 0xb41f, 0x7112, 0x700c,
+	0xa106, 0x1128, 0x080c, 0x27c4, 0x2001, 0x0138, 0x2102, 0x8cff,
+	0x0598, 0x6010, 0x2068, 0x2d58, 0x6828, 0xa406, 0x1590, 0x682c,
+	0xa306, 0x1578, 0x7004, 0x2060, 0x6020, 0xc0d4, 0x6022, 0x684c,
+	0xd0f4, 0x0128, 0x6817, 0xffff, 0x6813, 0xffff, 0x00e8, 0x6850,
+	0xd0f4, 0x1130, 0x7803, 0x0004, 0x6810, 0x781a, 0x6814, 0x781e,
+	0x6824, 0x2050, 0x6818, 0x2060, 0x6830, 0x2040, 0x6034, 0xa0cc,
+	0x000f, 0x2009, 0x0011, 0x080c, 0x19fa, 0x0120, 0x2009, 0x0001,
+	0x080c, 0x19fa, 0x2d58, 0x0005, 0x080c, 0x1d11, 0x0904, 0x196c,
+	0x0cd0, 0x6020, 0xd0f4, 0x11e0, 0xd0d4, 0x01b8, 0x6038, 0xa402,
+	0x6034, 0xa303, 0x0108, 0x1288, 0x643a, 0x6336, 0x6c2a, 0x6b2e,
+	0x0046, 0x0036, 0x2400, 0x6c7c, 0xa402, 0x6812, 0x2300, 0x6b80,
+	0xa303, 0x6816, 0x003e, 0x004e, 0x0018, 0x080c, 0x9ba8, 0x09e0,
+	0x601c, 0xa08e, 0x0008, 0x0904, 0x1992, 0xa08e, 0x000a, 0x0904,
+	0x1992, 0x2001, 0xb174, 0x2004, 0xd0b4, 0x1120, 0x6817, 0xffff,
+	0x6813, 0xffff, 0x080c, 0x2219, 0x1938, 0x0804, 0x1992, 0x7003,
+	0x0000, 0x0005, 0x8aff, 0x0904, 0x1a60, 0xa03e, 0x2730, 0x6850,
+	0xd0fc, 0x11b8, 0xd0f4, 0x1528, 0x00d6, 0x2805, 0xac68, 0x2900,
+	0x0002, 0x1a4a, 0x1a2f, 0x1a2f, 0x1a4a, 0x1a4a, 0x1a43, 0x1a4a,
+	0x1a2f, 0x1a4a, 0x1a34, 0x1a34, 0x1a4a, 0x1a4a, 0x1a4a, 0x1a3b,
+	0x1a34, 0x7803, 0x0004, 0xc0fc, 0x6852, 0x6b6c, 0x6a70, 0x6d1c,
+	0x6c20, 0x00d6, 0xd99c, 0x0548, 0x2805, 0xac68, 0x6f08, 0x6e0c,
+	0x0420, 0xc0f4, 0x6852, 0x6b6c, 0x6a70, 0x00d6, 0x0428, 0x6b08,
+	0x6a0c, 0x6d00, 0x6c04, 0x00c8, 0x6b10, 0x6a14, 0x6d00, 0x6c04,
+	0x6f08, 0x6e0c, 0x0090, 0x00de, 0x00d6, 0x6834, 0xa084, 0x00ff,
+	0xa086, 0x001e, 0x1138, 0x00de, 0x080c, 0x21bb, 0x1904, 0x19fa,
+	0xa00e, 0x00b0, 0x00de, 0x080c, 0x14fa, 0x7b22, 0x7a26, 0x7d32,
+	0x7c36, 0x7f3a, 0x7e3e, 0x7902, 0x7000, 0x8000, 0x7002, 0x00de,
+	0x6828, 0xa300, 0x682a, 0x682c, 0xa201, 0x682e, 0x080c, 0x21bb,
+	0x0005, 0x080c, 0x14fa, 0x080c, 0x1e70, 0x7004, 0x2060, 0x00d6,
+	0x6010, 0x2068, 0x7003, 0x0000, 0x080c, 0x1d48, 0x080c, 0x986a,
+	0x0170, 0x6808, 0x8001, 0x680a, 0x697c, 0x6912, 0x6980, 0x6916,
+	0x682b, 0xffff, 0x682f, 0xffff, 0x6850, 0xc0bd, 0x6852, 0x00de,
+	0x080c, 0x955c, 0x0804, 0x1c7c, 0x080c, 0x14fa, 0x0126, 0x2091,
+	0x2200, 0x0006, 0x0016, 0x2b68, 0x6818, 0x2060, 0x7904, 0x7803,
+	0x0002, 0xa184, 0x0700, 0x1978, 0xa184, 0x0003, 0xa086, 0x0003,
+	0x0d58, 0x7000, 0x0002, 0x1aa3, 0x1aa9, 0x1bb0, 0x1c57, 0x1c6b,
+	0x1aa3, 0x1aa3, 0x1aa3, 0x7804, 0xd09c, 0x1904, 0x1c7c, 0x080c,
+	0x14fa, 0x8001, 0x7002, 0xd1bc, 0x11a0, 0xd19c, 0x1904, 0x1b3b,
+	0xd1dc, 0x1178, 0x8aff, 0x0904, 0x1b3b, 0x2009, 0x0001, 0x080c,
+	0x19fa, 0x0904, 0x1c7c, 0x2009, 0x0001, 0x080c, 0x19fa, 0x0804,
+	0x1c7c, 0x7803, 0x0004, 0x7003, 0x0000, 0xd1bc, 0x1904, 0x1b1b,
+	0x0026, 0x0036, 0x7c20, 0x7d24, 0x7e30, 0x7f34, 0x7818, 0x6812,
+	0x781c, 0x6816, 0x2001, 0x0201, 0x2004, 0xa005, 0x0140, 0x7808,
+	0xd0ec, 0x1128, 0x7803, 0x0009, 0x7003, 0x0004, 0x0010, 0x080c,
+	0x1c80, 0x6b28, 0x6a2c, 0x2400, 0x686e, 0xa31a, 0x2500, 0x6872,
+	0xa213, 0x6b2a, 0x6a2e, 0x00c6, 0x7004, 0x2060, 0x6020, 0xd0f4,
+	0x1110, 0x633a, 0x6236, 0x00ce, 0x003e, 0x002e, 0x6e1e, 0x6f22,
+	0x080c, 0x21d1, 0x2a00, 0x6826, 0x2c00, 0x681a, 0x2800, 0x6832,
+	0x6850, 0xc0fd, 0x6852, 0x6808, 0x8001, 0x680a, 0x1148, 0x684c,
+	0xd0e4, 0x0130, 0x7004, 0x2060, 0x2009, 0x0048, 0x080c, 0x831a,
+	0x7000, 0xa086, 0x0004, 0x0904, 0x1c7c, 0x7003, 0x0000, 0x080c,
+	0x196c, 0x0804, 0x1c7c, 0x0056, 0x7d0c, 0xd5bc, 0x1110, 0x080c,
+	0xafbf, 0x005e, 0x080c, 0x1d48, 0x00f6, 0x7004, 0x2078, 0x080c,
+	0x5177, 0x0118, 0x7820, 0xc0f5, 0x7822, 0x00fe, 0x682b, 0xffff,
+	0x682f, 0xffff, 0x6808, 0x8001, 0x680a, 0x697c, 0x791a, 0x6980,
+	0x791e, 0x0804, 0x1c7c, 0x7004, 0x00c6, 0x2060, 0x6020, 0x00ce,
+	0xd0f4, 0x0120, 0x6808, 0x8001, 0x680a, 0x0420, 0x7818, 0x6812,
+	0x7a1c, 0x6a16, 0xd19c, 0x0160, 0xa205, 0x0150, 0x7004, 0xa080,
+	0x0007, 0x2004, 0xa084, 0xfffd, 0xa086, 0x0008, 0x1904, 0x1ac1,
+	0x684c, 0xc0f5, 0x684e, 0x7814, 0xa005, 0x1180, 0x7003, 0x0000,
+	0x6808, 0x8001, 0x680a, 0x1130, 0x7004, 0x2060, 0x2009, 0x0048,
+	0x080c, 0x831a, 0x080c, 0x196c, 0x0804, 0x1c7c, 0x7818, 0x6812,
+	0x781c, 0x6816, 0x7814, 0x7908, 0xa18c, 0x0fff, 0xa192, 0x0841,
+	0x1a04, 0x1a63, 0xa188, 0x0007, 0x8114, 0x8214, 0x8214, 0xa10a,
+	0x8104, 0x8004, 0x8004, 0xa20a, 0x810b, 0x810b, 0x810b, 0x080c,
+	0x1dd7, 0x7803, 0x0004, 0x780f, 0xffff, 0x7803, 0x0001, 0x7804,
+	0xd0fc, 0x0de8, 0x7803, 0x0002, 0x7803, 0x0004, 0x780f, 0x00f6,
+	0x7004, 0x7007, 0x0000, 0x2060, 0x2009, 0x0048, 0x080c, 0x831a,
+	0x080c, 0x1e09, 0x0938, 0x7908, 0xd1ec, 0x1118, 0x2009, 0x0009,
+	0x0010, 0x2009, 0x0019, 0x7902, 0x7003, 0x0003, 0x0804, 0x1c7c,
+	0x8001, 0x7002, 0xd194, 0x01a8, 0x7804, 0xd0fc, 0x1904, 0x1c4a,
+	0xd09c, 0x0130, 0x7804, 0xd0fc, 0x1904, 0x1a8e, 0xd09c, 0x11a8,
+	0x8aff, 0x0904, 0x1c7c, 0x2009, 0x0001, 0x080c, 0x19fa, 0x0804,
+	0x1c7c, 0xa184, 0x0888, 0x1148, 0x8aff, 0x0904, 0x1c7c, 0x2009,
+	0x0001, 0x080c, 0x19fa, 0x0804, 0x1c7c, 0x7818, 0x6812, 0x7a1c,
+	0x6a16, 0xa205, 0x0904, 0x1b58, 0x7803, 0x0004, 0x7003, 0x0000,
+	0xd1bc, 0x1904, 0x1c2d, 0x6834, 0xa084, 0x00ff, 0xa086, 0x0029,
+	0x1118, 0xd19c, 0x1904, 0x1b58, 0x0026, 0x0036, 0x7c20, 0x7d24,
+	0x7e30, 0x7f34, 0x7818, 0x6812, 0x781c, 0x6816, 0x2001, 0x0201,
+	0x2004, 0xa005, 0x0140, 0x7808, 0xd0ec, 0x1128, 0x7803, 0x0009,
+	0x7003, 0x0004, 0x0020, 0x0016, 0x080c, 0x1c80, 0x001e, 0x6b28,
+	0x6a2c, 0x080c, 0x21d1, 0x00d6, 0x2805, 0xac68, 0x6034, 0xd09c,
+	0x1128, 0x6808, 0xa31a, 0x680c, 0xa213, 0x0020, 0x6810, 0xa31a,
+	0x6814, 0xa213, 0x00de, 0xd194, 0x0904, 0x1ae3, 0x2a00, 0x6826,
+	0x2c00, 0x681a, 0x2800, 0x6832, 0x6808, 0x8001, 0x680a, 0x6b2a,
+	0x6a2e, 0x003e, 0x002e, 0x0804, 0x1b6a, 0x0056, 0x7d0c, 0x080c,
+	0xafbf, 0x005e, 0x080c, 0x1d48, 0x00f6, 0x7004, 0x2078, 0x080c,
+	0x5177, 0x0118, 0x7820, 0xc0f5, 0x7822, 0x00fe, 0x682b, 0xffff,
+	0x682f, 0xffff, 0x6808, 0x8001, 0x680a, 0x697c, 0x791a, 0x6980,
+	0x791e, 0x0490, 0x7804, 0xd09c, 0x0904, 0x1a8e, 0x7c20, 0x7824,
+	0xa405, 0x1904, 0x1a8e, 0x7803, 0x0002, 0x0804, 0x1bd5, 0x7803,
+	0x0004, 0x7003, 0x0000, 0x7004, 0xa00d, 0x0150, 0x6808, 0x8001,
+	0x680a, 0x1130, 0x7004, 0x2060, 0x2009, 0x0048, 0x080c, 0x831a,
+	0x080c, 0x196c, 0x0088, 0x7803, 0x0004, 0x7003, 0x0000, 0x7004,
+	0x2060, 0x6010, 0xa005, 0x0da0, 0x2068, 0x6808, 0x8000, 0x680a,
+	0x6c28, 0x6b2c, 0x080c, 0x1987, 0x001e, 0x000e, 0x012e, 0x0005,
+	0x700c, 0x7110, 0xa106, 0x0904, 0x1d05, 0x7004, 0x0016, 0x210c,
+	0xa106, 0x001e, 0x0904, 0x1d05, 0x00d6, 0x00c6, 0x216c, 0x2d00,
+	0xa005, 0x0904, 0x1d03, 0x6820, 0xd0d4, 0x1904, 0x1d03, 0x6810,
+	0x2068, 0x6850, 0xd0fc, 0x0558, 0x8108, 0x2104, 0x6b2c, 0xa306,
+	0x1904, 0x1d03, 0x8108, 0x2104, 0x6a28, 0xa206, 0x1904, 0x1d03,
+	0x6850, 0xc0fc, 0xc0f5, 0x6852, 0x686c, 0x7822, 0x6870, 0x7826,
+	0x681c, 0x7832, 0x6820, 0x7836, 0x6818, 0x2060, 0x6034, 0xd09c,
+	0x0150, 0x6830, 0x2005, 0x00d6, 0xac68, 0x6808, 0x783a, 0x680c,
+	0x783e, 0x00de, 0x04d0, 0xa006, 0x783a, 0x783e, 0x04b0, 0x8108,
+	0x2104, 0xa005, 0x15c0, 0x6b2c, 0xa306, 0x15a8, 0x8108, 0x2104,
+	0xa005, 0x1588, 0x6a28, 0xa206, 0x1570, 0x6850, 0xc0f5, 0x6852,
+	0x6830, 0x2005, 0x6918, 0xa160, 0xa180, 0x000d, 0x2004, 0xd09c,
+	0x1170, 0x6008, 0x7822, 0x686e, 0x600c, 0x7826, 0x6872, 0x6000,
+	0x7832, 0x6004, 0x7836, 0xa006, 0x783a, 0x783e, 0x0070, 0x6010,
+	0x7822, 0x686e, 0x6014, 0x7826, 0x6872, 0x6000, 0x7832, 0x6004,
+	0x7836, 0x6008, 0x783a, 0x600c, 0x783e, 0x6810, 0x781a, 0x6814,
+	0x781e, 0x7803, 0x0011, 0x00ce, 0x00de, 0x0005, 0x2011, 0x0201,
+	0x2009, 0x003c, 0x2204, 0xa005, 0x1118, 0x8109, 0x1dd8, 0x0005,
+	0x0005, 0x0ca1, 0x01e0, 0x7908, 0xd1ec, 0x1160, 0x080c, 0x1e09,
+	0x0148, 0x7803, 0x0009, 0x7904, 0xd1fc, 0x0de8, 0x7803, 0x0006,
+	0x0c29, 0x0168, 0x780c, 0xd0a4, 0x1150, 0x7007, 0x0000, 0x080c,
+	0x1e09, 0x0140, 0x7803, 0x0019, 0x7003, 0x0003, 0x0018, 0x00c1,
+	0xa085, 0x0001, 0x0005, 0x0126, 0x2091, 0x2200, 0x7000, 0xa086,
+	0x0003, 0x1160, 0x700c, 0x7110, 0xa106, 0x0140, 0x080c, 0x2835,
+	0x20e1, 0x9028, 0x700f, 0xb41f, 0x7013, 0xb41f, 0x012e, 0x0005,
+	0x00c6, 0x080c, 0x58d5, 0x1570, 0x2001, 0x0160, 0x2003, 0x0000,
+	0x2001, 0x0138, 0x2003, 0x0000, 0x2011, 0x00c8, 0xe000, 0xe000,
+	0x8211, 0x1de0, 0x080c, 0x1daa, 0x700c, 0x7110, 0xa106, 0x0190,
+	0x2104, 0xa005, 0x0130, 0x2060, 0x6010, 0x2060, 0x6008, 0x8001,
+	0x600a, 0xa188, 0x0003, 0xa182, 0xb43a, 0x0210, 0x2009, 0xb41f,
+	0x7112, 0x0c50, 0x0066, 0x2031, 0x0000, 0x080c, 0x5957, 0x006e,
+	0x00ce, 0x0005, 0x04c9, 0x080c, 0x2835, 0x20e1, 0x9028, 0x700c,
+	0x7110, 0xa106, 0x01d0, 0x2104, 0xa005, 0x0130, 0x2060, 0x6010,
+	0x2060, 0x6008, 0x8001, 0x600a, 0xa188, 0x0003, 0xa182, 0xb43a,
+	0x0210, 0x2009, 0xb41f, 0x7112, 0x700c, 0xa106, 0x1d40, 0x080c,
+	0x27c4, 0x2001, 0x0138, 0x2102, 0x0c10, 0x2001, 0x015d, 0x200c,
+	0x810a, 0x2102, 0x2001, 0x0160, 0x2502, 0x2001, 0x0138, 0x2202,
+	0x00ce, 0x0005, 0x080c, 0x2835, 0x20e1, 0x9028, 0x2001, 0x015d,
+	0x200c, 0x810a, 0x2102, 0x0005, 0x2001, 0x0138, 0x2014, 0x2003,
+	0x0000, 0x2001, 0x0160, 0x202c, 0x2003, 0x0000, 0x080c, 0x58d5,
+	0x1108, 0x0005, 0x2021, 0xb015, 0x2001, 0x0141, 0x201c, 0xd3dc,
+	0x1168, 0x2001, 0x0109, 0x201c, 0xa39c, 0x0048, 0x1138, 0x2001,
+	0x0111, 0x201c, 0x83ff, 0x1110, 0x8421, 0x1d70, 0x0005, 0x00e6,
+	0x2071, 0x0200, 0x7808, 0xa084, 0xf000, 0xa10d, 0x08a9, 0x2019,
+	0x5000, 0x8319, 0x0168, 0x2001, 0xb43a, 0x2004, 0xa086, 0x0000,
+	0x0138, 0x2001, 0x0021, 0xd0fc, 0x0da0, 0x080c, 0x205e, 0x0c78,
+	0x20e1, 0x7000, 0x7324, 0x7420, 0x7028, 0x7028, 0x7426, 0x7037,
+	0x0001, 0x810f, 0x712e, 0x702f, 0x0100, 0x7037, 0x0008, 0x7326,
+	0x7422, 0x2001, 0x0160, 0x2502, 0x2001, 0x0138, 0x2202, 0x00ee,
+	0x0005, 0x0026, 0x2001, 0x015d, 0x200c, 0x810a, 0x2102, 0x7908,
+	0xa18c, 0x0fff, 0xa182, 0x0ffd, 0x0210, 0x2009, 0x0000, 0xa190,
+	0x0007, 0xa294, 0x1ff8, 0x8214, 0x8214, 0x8214, 0x2001, 0x020a,
+	0x82ff, 0x0140, 0x20e1, 0x6000, 0x200c, 0x200c, 0x200c, 0x200c,
+	0x8211, 0x1dd0, 0x20e1, 0x7000, 0x200c, 0x200c, 0x7003, 0x0000,
+	0x20e1, 0x6000, 0x2001, 0x0208, 0x200c, 0x2001, 0x0209, 0x2004,
+	0xa106, 0x0158, 0x080c, 0x1d06, 0x0130, 0x7908, 0xd1ec, 0x1128,
+	0x790c, 0xd1a4, 0x0960, 0x080c, 0x1d48, 0xa006, 0x002e, 0x0005,
+	0x00f6, 0x00e6, 0x0016, 0x0026, 0x2071, 0xb419, 0x2079, 0x0030,
+	0x2011, 0x0050, 0x7000, 0xa086, 0x0000, 0x01a8, 0x8211, 0x0188,
+	0x2001, 0x0005, 0x2004, 0xd08c, 0x0dc8, 0x7904, 0xa18c, 0x0780,
+	0x0016, 0x080c, 0x1a86, 0x001e, 0x81ff, 0x1118, 0x2011, 0x0050,
+	0x0c48, 0xa085, 0x0001, 0x002e, 0x001e, 0x00ee, 0x00fe, 0x0005,
+	0x7803, 0x0004, 0x2009, 0x0064, 0x7804, 0xd0ac, 0x0904, 0x1ebc,
+	0x8109, 0x1dd0, 0x2009, 0x0100, 0x210c, 0xa18a, 0x0003, 0x0a0c,
+	0x14fa, 0x080c, 0x2165, 0x00e6, 0x00f6, 0x2071, 0xb408, 0x2079,
+	0x0010, 0x7004, 0xa086, 0x0000, 0x0538, 0x7800, 0x0006, 0x7820,
+	0x0006, 0x7830, 0x0006, 0x7834, 0x0006, 0x7838, 0x0006, 0x783c,
+	0x0006, 0x7803, 0x0004, 0xe000, 0xe000, 0x2079, 0x0030, 0x7804,
+	0xd0ac, 0x190c, 0x14fa, 0x2079, 0x0010, 0x000e, 0x783e, 0x000e,
+	0x783a, 0x000e, 0x7836, 0x000e, 0x7832, 0x000e, 0x7822, 0x000e,
+	0x7802, 0x00fe, 0x00ee, 0x0030, 0x00fe, 0x00ee, 0x7804, 0xd0ac,
+	0x190c, 0x14fa, 0x080c, 0x6f5b, 0x0005, 0x00e6, 0x2071, 0xb43a,
+	0x7003, 0x0000, 0x00ee, 0x0005, 0x00d6, 0xa280, 0x0004, 0x206c,
+	0x694c, 0xd1dc, 0x1904, 0x1f3a, 0x6934, 0xa184, 0x0007, 0x0002,
+	0x1ed8, 0x1f25, 0x1ed8, 0x1ed8, 0x1ed8, 0x1f0c, 0x1eeb, 0x1eda,
+	0x080c, 0x14fa, 0x684c, 0xd0b4, 0x0904, 0x2022, 0x6860, 0x682e,
+	0x6816, 0x685c, 0x682a, 0x6812, 0x687c, 0x680a, 0x6880, 0x680e,
+	0x6958, 0x0804, 0x1f2d, 0x6834, 0xa084, 0x00ff, 0xa086, 0x001e,
+	0x1d38, 0x684c, 0xd0b4, 0x0904, 0x2022, 0x6860, 0x682e, 0x6816,
+	0x685c, 0x682a, 0x6812, 0x687c, 0x680a, 0x6880, 0x680e, 0x6804,
+	0x681a, 0xa080, 0x000d, 0x2004, 0xa084, 0x000f, 0xa080, 0x21f9,
+	0x2005, 0x6832, 0x6958, 0x0450, 0xa18c, 0x00ff, 0xa186, 0x0015,
+	0x1548, 0x684c, 0xd0b4, 0x0904, 0x2022, 0x6804, 0x681a, 0xa080,
+	0x000d, 0x2004, 0xa084, 0x000f, 0xa080, 0x21f9, 0x2005, 0x6832,
+	0x6958, 0xa006, 0x682e, 0x682a, 0x0088, 0x684c, 0xd0b4, 0x0904,
+	0x1a61, 0x6958, 0xa006, 0x682e, 0x682a, 0x2d00, 0x681a, 0x6834,
+	0xa084, 0x000f, 0xa080, 0x21f9, 0x2005, 0x6832, 0x6926, 0x684c,
+	0xc0dd, 0x684e, 0x00de, 0x0005, 0x00f6, 0x2079, 0x0020, 0x7804,
+	0xd0fc, 0x190c, 0x205e, 0x00e6, 0x00d6, 0x2071, 0xb43a, 0x7000,
+	0xa005, 0x1904, 0x1fa2, 0x00c6, 0x7206, 0xa280, 0x0004, 0x205c,
+	0x7004, 0x2068, 0x7803, 0x0004, 0x6818, 0x00d6, 0x2068, 0x686c,
+	0x7812, 0x6890, 0x00f6, 0x20e1, 0x9040, 0x2079, 0x0200, 0x781a,
+	0x2079, 0x0100, 0x8004, 0x78d6, 0x00fe, 0x00de, 0x2b68, 0x6824,
+	0x2050, 0x6818, 0x2060, 0x6830, 0x2040, 0x6034, 0xa0cc, 0x000f,
+	0x6908, 0x791a, 0x7116, 0x680c, 0x781e, 0x701a, 0xa006, 0x700e,
+	0x7012, 0x7004, 0x692c, 0x6814, 0xa106, 0x1120, 0x6928, 0x6810,
+	0xa106, 0x0158, 0x0036, 0x0046, 0x6b14, 0x6c10, 0x080c, 0x2219,
+	0x004e, 0x003e, 0x0110, 0x00ce, 0x00a8, 0x8aff, 0x1120, 0x00ce,
+	0xa085, 0x0001, 0x0078, 0x0126, 0x2091, 0x8000, 0x2079, 0x0020,
+	0x2009, 0x0001, 0x0059, 0x0118, 0x2009, 0x0001, 0x0039, 0x012e,
+	0x00ce, 0xa006, 0x00de, 0x00ee, 0x00fe, 0x0005, 0x0076, 0x0066,
+	0x0056, 0x0046, 0x0036, 0x0026, 0x8aff, 0x0904, 0x201b, 0x700c,
+	0x7214, 0xa23a, 0x7010, 0x7218, 0xa203, 0x0a04, 0x201a, 0xa705,
+	0x0904, 0x201a, 0xa03e, 0x2730, 0x6850, 0xd0fc, 0x11a8, 0x00d6,
+	0x2805, 0xac68, 0x2900, 0x0002, 0x1ffd, 0x1fe2, 0x1fe2, 0x1ffd,
+	0x1ffd, 0x1ff6, 0x1ffd, 0x1fe2, 0x1ffd, 0x1fe7, 0x1fe7, 0x1ffd,
+	0x1ffd, 0x1ffd, 0x1fee, 0x1fe7, 0xc0fc, 0x6852, 0x6b6c, 0x6a70,
+	0x6d1c, 0x6c20, 0xd99c, 0x0528, 0x00d6, 0x2805, 0xac68, 0x6f08,
+	0x6e0c, 0x00f0, 0x6b08, 0x6a0c, 0x6d00, 0x6c04, 0x00c8, 0x6b10,
+	0x6a14, 0x6d00, 0x6c04, 0x6f08, 0x6e0c, 0x0090, 0x00de, 0x00d6,
+	0x6834, 0xa084, 0x00ff, 0xa086, 0x001e, 0x1138, 0x00de, 0x080c,
+	0x21bb, 0x1904, 0x1fac, 0xa00e, 0x00f0, 0x00de, 0x080c, 0x14fa,
+	0x00de, 0x7b22, 0x7a26, 0x7d32, 0x7c36, 0x7f3a, 0x7e3e, 0x7902,
+	0x7000, 0x8000, 0x7002, 0x6828, 0xa300, 0x682a, 0x682c, 0xa201,
+	0x682e, 0x700c, 0xa300, 0x700e, 0x7010, 0xa201, 0x7012, 0x080c,
+	0x21bb, 0x0008, 0xa006, 0x002e, 0x003e, 0x004e, 0x005e, 0x006e,
+	0x007e, 0x0005, 0x080c, 0x14fa, 0x0026, 0x2001, 0x0105, 0x2003,
+	0x0010, 0x20e1, 0x9040, 0x7803, 0x0004, 0x7003, 0x0000, 0x7004,
+	0x2060, 0x00d6, 0x6010, 0x2068, 0x080c, 0x986a, 0x0118, 0x6850,
+	0xc0bd, 0x6852, 0x601c, 0xa086, 0x0006, 0x1180, 0x2061, 0x0100,
+	0x62c8, 0x2001, 0x00fa, 0x8001, 0x1df0, 0x60c8, 0xa206, 0x1dc0,
+	0x60c4, 0x686a, 0x60c8, 0x6866, 0x7004, 0x2060, 0x00de, 0x080c,
+	0x955c, 0x20e1, 0x9040, 0x080c, 0x7f2b, 0x2011, 0x0000, 0x080c,
+	0x7d5c, 0x080c, 0x6f5b, 0x002e, 0x0804, 0x2118, 0x0126, 0x2091,
+	0x2400, 0x0006, 0x0016, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x2079,
+	0x0020, 0x2071, 0xb43a, 0x2b68, 0x6818, 0x2060, 0x7904, 0x7803,
+	0x0002, 0xa184, 0x0700, 0x1904, 0x2024, 0x7000, 0x0002, 0x2118,
+	0x207b, 0x20eb, 0x2116, 0x8001, 0x7002, 0xd19c, 0x1170, 0x8aff,
+	0x05d0, 0x2009, 0x0001, 0x080c, 0x1fa6, 0x0904, 0x2118, 0x2009,
+	0x0001, 0x080c, 0x1fa6, 0x0804, 0x2118, 0x7803, 0x0004, 0xd194,
+	0x0148, 0x6850, 0xc0fc, 0x6852, 0x8aff, 0x11d8, 0x684c, 0xc0f5,
+	0x684e, 0x00b8, 0x0026, 0x0036, 0x6b28, 0x6a2c, 0x7820, 0x686e,
+	0xa31a, 0x7824, 0x6872, 0xa213, 0x7830, 0x681e, 0x7834, 0x6822,
+	0x6b2a, 0x6a2e, 0x003e, 0x002e, 0x080c, 0x21d1, 0x6850, 0xc0fd,
+	0x6852, 0x2a00, 0x6826, 0x2c00, 0x681a, 0x2800, 0x6832, 0x7003,
+	0x0000, 0x0804, 0x2118, 0x00f6, 0x0026, 0x781c, 0x0006, 0x7818,
+	0x0006, 0x2079, 0x0100, 0x7a14, 0xa284, 0x0184, 0xa085, 0x0012,
+	0x7816, 0x0036, 0x2019, 0x1000, 0x8319, 0x090c, 0x14fa, 0x7820,
+	0xd0bc, 0x1dd0, 0x003e, 0x79c8, 0x000e, 0xa102, 0x001e, 0x0006,
+	0x0016, 0x79c4, 0x000e, 0xa103, 0x78c6, 0x000e, 0x78ca, 0xa284,
+	0x0184, 0xa085, 0x0012, 0x7816, 0x002e, 0x00fe, 0x7803, 0x0008,
+	0x7003, 0x0000, 0x0468, 0x8001, 0x7002, 0xd194, 0x0168, 0x7804,
+	0xd0fc, 0x1904, 0x206e, 0xd19c, 0x11f8, 0x8aff, 0x0508, 0x2009,
+	0x0001, 0x080c, 0x1fa6, 0x00e0, 0x0026, 0x0036, 0x6b28, 0x6a2c,
+	0x080c, 0x21d1, 0x00d6, 0x2805, 0xac68, 0x6034, 0xd09c, 0x1128,
+	0x6808, 0xa31a, 0x680c, 0xa213, 0x0020, 0x6810, 0xa31a, 0x6814,
+	0xa213, 0x00de, 0x0804, 0x209e, 0x0804, 0x209a, 0x080c, 0x14fa,
+	0x00ce, 0x00de, 0x00ee, 0x00fe, 0x001e, 0x000e, 0x012e, 0x0005,
+	0x00f6, 0x00e6, 0x2071, 0xb43a, 0x7000, 0xa086, 0x0000, 0x05d0,
+	0x2079, 0x0020, 0x0016, 0x2009, 0x0207, 0x210c, 0xd194, 0x0198,
+	0x2009, 0x020c, 0x210c, 0xa184, 0x0003, 0x0168, 0x080c, 0xaffa,
+	0x2001, 0x0133, 0x2004, 0xa005, 0x090c, 0x14fa, 0x20e1, 0x9040,
+	0x2001, 0x020c, 0x2102, 0x2009, 0x0206, 0x2104, 0x2009, 0x0203,
+	0x210c, 0xa106, 0x1110, 0x20e1, 0x9040, 0x7804, 0xd0fc, 0x09d8,
+	0x080c, 0x205e, 0x7000, 0xa086, 0x0000, 0x19a8, 0x001e, 0x7803,
+	0x0004, 0x7804, 0xd0ac, 0x1de8, 0x20e1, 0x9040, 0x7803, 0x0002,
+	0x7003, 0x0000, 0x00ee, 0x00fe, 0x0005, 0x0026, 0x00c6, 0x00d6,
+	0x00e6, 0x00f6, 0x2071, 0xb43a, 0x2079, 0x0020, 0x7000, 0xa086,
+	0x0000, 0x0540, 0x7004, 0x2060, 0x6010, 0x2068, 0x080c, 0x986a,
+	0x0158, 0x6850, 0xc0b5, 0x6852, 0x680c, 0x7a1c, 0xa206, 0x1120,
+	0x6808, 0x7a18, 0xa206, 0x01e0, 0x2001, 0x0105, 0x2003, 0x0010,
+	0x20e1, 0x9040, 0x7803, 0x0004, 0x7003, 0x0000, 0x7004, 0x2060,
+	0x080c, 0x955c, 0x20e1, 0x9040, 0x080c, 0x7f2b, 0x2011, 0x0000,
+	0x080c, 0x7d5c, 0x00fe, 0x00ee, 0x00de, 0x00ce, 0x002e, 0x0005,
+	0x6810, 0x6a14, 0xa205, 0x1d00, 0x684c, 0xc0dc, 0x684e, 0x2c10,
+	0x080c, 0x1ec4, 0x2001, 0x0105, 0x2003, 0x0010, 0x20e1, 0x9040,
+	0x7803, 0x0004, 0x7003, 0x0000, 0x2069, 0xb3d9, 0x6833, 0x0000,
+	0x683f, 0x0000, 0x08f8, 0x8840, 0x2805, 0xa005, 0x1170, 0x6004,
+	0xa005, 0x0168, 0x681a, 0x2060, 0x6034, 0xa084, 0x000f, 0xa080,
+	0x21f9, 0x2045, 0x88ff, 0x090c, 0x14fa, 0x8a51, 0x0005, 0x2050,
+	0x0005, 0x8a50, 0x8841, 0x2805, 0xa005, 0x1190, 0x2c00, 0xad06,
+	0x0120, 0x6000, 0xa005, 0x1108, 0x2d00, 0x2060, 0x681a, 0x6034,
+	0xa084, 0x000f, 0xa080, 0x2209, 0x2045, 0x88ff, 0x090c, 0x14fa,
+	0x0005, 0x0000, 0x0011, 0x0015, 0x0019, 0x001d, 0x0021, 0x0025,
+	0x0029, 0x0000, 0x000f, 0x0015, 0x001b, 0x0021, 0x0027, 0x0000,
+	0x0000, 0x0000, 0x21ee, 0x21ea, 0x0000, 0x0000, 0x21f8, 0x0000,
+	0x21ee, 0x0000, 0x21f5, 0x21f2, 0x0000, 0x0000, 0x0000, 0x21f8,
+	0x21f5, 0x0000, 0x21f0, 0x21f0, 0x0000, 0x0000, 0x21f8, 0x0000,
+	0x21f0, 0x0000, 0x21f6, 0x21f6, 0x0000, 0x0000, 0x0000, 0x21f8,
+	0x21f6, 0x00a6, 0x0096, 0x0086, 0x6b2e, 0x6c2a, 0x6858, 0xa055,
+	0x0904, 0x22aa, 0x2d60, 0x6034, 0xa0cc, 0x000f, 0xa9c0, 0x21f9,
+	0xa986, 0x0007, 0x0130, 0xa986, 0x000e, 0x0118, 0xa986, 0x000f,
+	0x1120, 0x605c, 0xa422, 0x6060, 0xa31a, 0x2805, 0xa045, 0x1140,
+	0x0310, 0x0804, 0x22aa, 0x6004, 0xa065, 0x0904, 0x22aa, 0x0c18,
+	0x2805, 0xa005, 0x01a8, 0xac68, 0xd99c, 0x1128, 0x6808, 0xa422,
+	0x680c, 0xa31b, 0x0020, 0x6810, 0xa422, 0x6814, 0xa31b, 0x0620,
+	0x2300, 0xa405, 0x0150, 0x8a51, 0x0904, 0x22aa, 0x8840, 0x0c40,
+	0x6004, 0xa065, 0x0904, 0x22aa, 0x0830, 0x8a51, 0x0904, 0x22aa,
+	0x8840, 0x2805, 0xa005, 0x1158, 0x6004, 0xa065, 0x0904, 0x22aa,
+	0x6034, 0xa0cc, 0x000f, 0xa9c0, 0x21f9, 0x2805, 0x2040, 0x2b68,
+	0x6850, 0xc0fc, 0x6852, 0x0458, 0x8422, 0x8420, 0x831a, 0xa399,
+	0x0000, 0x00d6, 0x2b68, 0x6c6e, 0x6b72, 0x00de, 0xd99c, 0x1168,
+	0x6908, 0x2400, 0xa122, 0x690c, 0x2300, 0xa11b, 0x0a0c, 0x14fa,
+	0x6800, 0xa420, 0x6804, 0xa319, 0x0060, 0x6910, 0x2400, 0xa122,
+	0x6914, 0x2300, 0xa11b, 0x0a0c, 0x14fa, 0x6800, 0xa420, 0x6804,
+	0xa319, 0x2b68, 0x6c1e, 0x6b22, 0x6850, 0xc0fd, 0x6852, 0x2c00,
+	0x681a, 0x2800, 0x6832, 0x2a00, 0x6826, 0x000e, 0x000e, 0x000e,
+	0xa006, 0x0028, 0x008e, 0x009e, 0x00ae, 0xa085, 0x0001, 0x0005,
+	0x2001, 0x0005, 0x2004, 0xa084, 0x0007, 0x0002, 0x22be, 0x22bf,
+	0x22c2, 0x22c5, 0x22ca, 0x22cd, 0x22d2, 0x22d7, 0x0005, 0x080c,
+	0x205e, 0x0005, 0x080c, 0x1a86, 0x0005, 0x080c, 0x1a86, 0x080c,
+	0x205e, 0x0005, 0x080c, 0x16fc, 0x0005, 0x080c, 0x205e, 0x080c,
+	0x16fc, 0x0005, 0x080c, 0x1a86, 0x080c, 0x16fc, 0x0005, 0x080c,
+	0x1a86, 0x080c, 0x205e, 0x080c, 0x16fc, 0x0005, 0x0126, 0x2091,
+	0x2600, 0x2079, 0x0200, 0x2071, 0xb680, 0x2069, 0xb100, 0x2009,
+	0x0004, 0x7912, 0x7817, 0x0004, 0x080c, 0x26d1, 0x781b, 0x0002,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x20a9, 0x0080, 0x782f, 0x0000,
+	0x1f04, 0x22f6, 0x20e1, 0x9080, 0x783b, 0x001f, 0x20e1, 0x8700,
+	0x012e, 0x0005, 0x0126, 0x2091, 0x2600, 0x781c, 0xd0a4, 0x190c,
+	0x23b5, 0xa084, 0x0007, 0x0002, 0x2326, 0x2314, 0x2317, 0x231a,
+	0x231f, 0x2321, 0x2323, 0x2325, 0x080c, 0x619d, 0x0078, 0x080c,
+	0x61dc, 0x0060, 0x080c, 0x619d, 0x080c, 0x61dc, 0x0038, 0x0041,
+	0x0028, 0x0031, 0x0018, 0x0021, 0x0008, 0x0011, 0x012e, 0x0005,
+	0x0006, 0x0016, 0x0026, 0x080c, 0xaffa, 0x7930, 0xa184, 0x0003,
+	0x0170, 0x2001, 0xb3e8, 0x2004, 0xa005, 0x0130, 0x2001, 0x0133,
+	0x2004, 0xa005, 0x090c, 0x14fa, 0x20e1, 0x9040, 0x04a0, 0xa184,
+	0x0030, 0x01e0, 0x6a00, 0xa286, 0x0003, 0x1108, 0x00a0, 0x080c,
+	0x58d5, 0x1178, 0x2001, 0xb39f, 0x2003, 0x0001, 0x2001, 0xb100,
+	0x2003, 0x0001, 0xa085, 0x0001, 0x080c, 0x5919, 0x080c, 0x5816,
+	0x0010, 0x080c, 0x4992, 0x20e1, 0x9010, 0x00a8, 0xa184, 0x00c0,
+	0x0168, 0x00e6, 0x0036, 0x0046, 0x0056, 0x2071, 0xb419, 0x080c,
+	0x1d48, 0x005e, 0x004e, 0x003e, 0x00ee, 0x0028, 0xa184, 0x0300,
+	0x0110, 0x20e1, 0x9020, 0x7932, 0x002e, 0x001e, 0x000e, 0x0005,
+	0x0016, 0x00e6, 0x00f6, 0x2071, 0xb100, 0x7128, 0x2001, 0xb391,
+	0x2102, 0x2001, 0xb399, 0x2102, 0xa182, 0x0211, 0x1218, 0x2009,
+	0x0008, 0x0400, 0xa182, 0x0259, 0x1218, 0x2009, 0x0007, 0x00d0,
+	0xa182, 0x02c1, 0x1218, 0x2009, 0x0006, 0x00a0, 0xa182, 0x0349,
+	0x1218, 0x2009, 0x0005, 0x0070, 0xa182, 0x0421, 0x1218, 0x2009,
+	0x0004, 0x0040, 0xa182, 0x0581, 0x1218, 0x2009, 0x0003, 0x0010,
+	0x2009, 0x0002, 0x2079, 0x0200, 0x7912, 0x7817, 0x0004, 0x080c,
+	0x26d1, 0x00fe, 0x00ee, 0x001e, 0x0005, 0x7938, 0x080c, 0x14fa,
+	0x0126, 0x2091, 0x2800, 0x2061, 0x0100, 0x2071, 0xb100, 0x6024,
+	0x6026, 0x6053, 0x0030, 0x080c, 0x2710, 0x6050, 0xa084, 0xfe7f,
+	0x6052, 0x2009, 0x00ef, 0x6132, 0x6136, 0x080c, 0x2720, 0x60e7,
+	0x0000, 0x61ea, 0x60e3, 0x0008, 0x604b, 0xf7f7, 0x6043, 0x0000,
+	0x602f, 0x0080, 0x602f, 0x0000, 0x6007, 0x0e9f, 0x601b, 0x001e,
+	0x600f, 0x00ff, 0x2001, 0xb38d, 0x2003, 0x00ff, 0x602b, 0x002f,
+	0x012e, 0x0005, 0x2001, 0xb131, 0x2003, 0x0000, 0x2001, 0xb130,
+	0x2003, 0x0001, 0x0005, 0x0126, 0x2091, 0x2800, 0x0006, 0x0016,
+	0x0026, 0x6124, 0xa184, 0x1e2c, 0x1118, 0xa184, 0x0007, 0x002a,
+	0xa195, 0x0004, 0xa284, 0x0007, 0x0002, 0x2427, 0x240d, 0x2410,
+	0x2413, 0x2418, 0x241a, 0x241e, 0x2422, 0x080c, 0x68e7, 0x00b8,
+	0x080c, 0x69c2, 0x00a0, 0x080c, 0x69c2, 0x080c, 0x68e7, 0x0078,
+	0x0099, 0x0068, 0x080c, 0x68e7, 0x0079, 0x0048, 0x080c, 0x69c2,
+	0x0059, 0x0028, 0x080c, 0x69c2, 0x080c, 0x68e7, 0x0029, 0x002e,
+	0x001e, 0x000e, 0x012e, 0x0005, 0x6124, 0xd19c, 0x1904, 0x263f,
+	0x080c, 0x58d5, 0x0578, 0x7000, 0xa086, 0x0003, 0x0198, 0x6024,
+	0xa084, 0x1800, 0x0178, 0x080c, 0x58fb, 0x0118, 0x080c, 0x58e7,
+	0x1148, 0x6027, 0x0020, 0x6043, 0x0000, 0x2001, 0xb39e, 0x2003,
+	0xaaaa, 0x0458, 0x080c, 0x58fb, 0x15d0, 0x6024, 0xa084, 0x1800,
+	0x1108, 0x04a8, 0x2001, 0xb39e, 0x2003, 0xaaaa, 0x2001, 0xb39f,
+	0x2003, 0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0x080c, 0x5816,
+	0x0804, 0x263f, 0xd1ac, 0x1518, 0x6024, 0xd0dc, 0x1170, 0xd0e4,
+	0x1188, 0xd0d4, 0x11a0, 0xd0cc, 0x0130, 0x7088, 0xa086, 0x0028,
+	0x1110, 0x080c, 0x5a64, 0x0804, 0x263f, 0x2001, 0xb39f, 0x2003,
+	0x0000, 0x0048, 0x2001, 0xb39f, 0x2003, 0x0002, 0x0020, 0x080c,
+	0x59d7, 0x0804, 0x263f, 0x080c, 0x5b04, 0x0804, 0x263f, 0xd1ac,
+	0x0904, 0x2587, 0x080c, 0x58d5, 0x11d8, 0x6027, 0x0020, 0x0006,
+	0x0026, 0x0036, 0x080c, 0x58f1, 0x1170, 0x2001, 0xb39f, 0x2003,
+	0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0x080c, 0x5816, 0x003e,
+	0x002e, 0x000e, 0x0005, 0x003e, 0x002e, 0x000e, 0x080c, 0x58ac,
+	0x0016, 0x0046, 0x00c6, 0x644c, 0xa486, 0xf0f0, 0x1138, 0x2061,
+	0x0100, 0x644a, 0x6043, 0x0090, 0x6043, 0x0010, 0x74ca, 0xa48c,
+	0xff00, 0x7034, 0xd084, 0x0178, 0xa186, 0xf800, 0x1160, 0x7038,
+	0xd084, 0x1148, 0xc085, 0x703a, 0x0036, 0x2418, 0x2011, 0x8016,
+	0x080c, 0x3d5b, 0x003e, 0xa196, 0xff00, 0x05b8, 0x7050, 0xa084,
+	0x00ff, 0x810f, 0xa116, 0x0588, 0x7130, 0xd184, 0x1570, 0x2011,
+	0xb153, 0x2214, 0xd2ec, 0x0138, 0xc18d, 0x7132, 0x2011, 0xb153,
+	0x2214, 0xd2ac, 0x1510, 0x6240, 0xa294, 0x0010, 0x0130, 0x6248,
+	0xa294, 0xff00, 0xa296, 0xff00, 0x01c0, 0x7030, 0xd08c, 0x0904,
+	0x2552, 0x7034, 0xd08c, 0x1140, 0x2001, 0xb10c, 0x200c, 0xd1ac,
+	0x1904, 0x2552, 0xc1ad, 0x2102, 0x0036, 0x73c8, 0x2011, 0x8013,
+	0x080c, 0x3d5b, 0x003e, 0x0804, 0x2552, 0x7034, 0xd08c, 0x1140,
+	0x2001, 0xb10c, 0x200c, 0xd1ac, 0x1904, 0x2552, 0xc1ad, 0x2102,
+	0x0036, 0x73c8, 0x2011, 0x8013, 0x080c, 0x3d5b, 0x003e, 0x7130,
+	0xc185, 0x7132, 0x2011, 0xb153, 0x220c, 0xd1a4, 0x01d0, 0x0016,
+	0x2009, 0x0001, 0x2011, 0x0100, 0x080c, 0x688d, 0x2019, 0x000e,
+	0x080c, 0xac2b, 0xa484, 0x00ff, 0xa080, 0x2c8c, 0x200d, 0xa18c,
+	0xff00, 0x810f, 0x8127, 0xa006, 0x2009, 0x000e, 0x080c, 0xacae,
+	0x001e, 0xd1ac, 0x1148, 0x0016, 0x2009, 0x0000, 0x2019, 0x0004,
+	0x080c, 0x2b46, 0x001e, 0x0070, 0x0156, 0x20a9, 0x007f, 0x2009,
+	0x0000, 0x080c, 0x4e21, 0x1110, 0x080c, 0x4a80, 0x8108, 0x1f04,
+	0x2549, 0x015e, 0x00ce, 0x004e, 0x2011, 0x0003, 0x080c, 0x7d52,
+	0x2011, 0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41, 0x080c, 0x67b6,
+	0x0036, 0x2019, 0x0000, 0x080c, 0x7cc4, 0x003e, 0x60e3, 0x0000,
+	0x001e, 0x2001, 0xb100, 0x2014, 0xa296, 0x0004, 0x1128, 0xd19c,
+	0x1118, 0x6228, 0xc29d, 0x622a, 0x2003, 0x0001, 0x2001, 0xb122,
+	0x2003, 0x0000, 0x6027, 0x0020, 0x080c, 0x58fb, 0x1140, 0x0016,
+	0x2009, 0x07d0, 0x2011, 0x57f7, 0x080c, 0x67c8, 0x001e, 0xd194,
+	0x0904, 0x263f, 0x0016, 0x6220, 0xd2b4, 0x0904, 0x25f0, 0x080c,
+	0x67b6, 0x080c, 0x7a8c, 0x6027, 0x0004, 0x00f6, 0x2019, 0xb3e2,
+	0x2304, 0xa07d, 0x0570, 0x7804, 0xa086, 0x0032, 0x1550, 0x00d6,
+	0x00c6, 0x00e6, 0x2069, 0x0140, 0x618c, 0x6288, 0x7818, 0x608e,
+	0x7808, 0x608a, 0x6043, 0x0002, 0x2001, 0x0003, 0x8001, 0x1df0,
+	0x6043, 0x0000, 0x6803, 0x1000, 0x6803, 0x0000, 0x618e, 0x628a,
+	0x080c, 0x6dc1, 0x080c, 0x6e9e, 0x7810, 0x2070, 0x7037, 0x0103,
+	0x2f60, 0x080c, 0x82eb, 0x00ee, 0x00ce, 0x00de, 0x00fe, 0x001e,
+	0x0005, 0x00fe, 0x00d6, 0x2069, 0x0140, 0x6804, 0xa084, 0x4000,
+	0x0120, 0x6803, 0x1000, 0x6803, 0x0000, 0x00de, 0x00c6, 0x2061,
+	0xb3d9, 0x6028, 0xa09a, 0x00c8, 0x1238, 0x8000, 0x602a, 0x00ce,
+	0x080c, 0x7a7f, 0x0804, 0x263e, 0x2019, 0xb3e2, 0x2304, 0xa065,
+	0x0120, 0x2009, 0x0027, 0x080c, 0x831a, 0x00ce, 0x0804, 0x263e,
+	0xd2bc, 0x0904, 0x263e, 0x080c, 0x67c3, 0x6014, 0xa084, 0x0184,
+	0xa085, 0x0010, 0x6016, 0x6027, 0x0004, 0x00d6, 0x2069, 0x0140,
+	0x6804, 0xa084, 0x4000, 0x0120, 0x6803, 0x1000, 0x6803, 0x0000,
+	0x00de, 0x00c6, 0x2061, 0xb3d9, 0x6044, 0xa09a, 0x00c8, 0x12f0,
+	0x8000, 0x6046, 0x603c, 0x00ce, 0xa005, 0x0540, 0x2009, 0x07d0,
+	0x080c, 0x67bb, 0xa080, 0x0007, 0x2004, 0xa086, 0x0006, 0x1138,
+	0x6114, 0xa18c, 0x0184, 0xa18d, 0x0012, 0x6116, 0x00b8, 0x6114,
+	0xa18c, 0x0184, 0xa18d, 0x0016, 0x6116, 0x0080, 0x0036, 0x2019,
+	0x0001, 0x080c, 0x7cc4, 0x003e, 0x2019, 0xb3e8, 0x2304, 0xa065,
+	0x0120, 0x2009, 0x004f, 0x080c, 0x831a, 0x00ce, 0x001e, 0xd19c,
+	0x0904, 0x269a, 0x7034, 0xd0ac, 0x1560, 0x0016, 0x0156, 0x6027,
+	0x0008, 0x602f, 0x0020, 0x20a9, 0x0006, 0x1d04, 0x264d, 0x2091,
+	0x6000, 0x1f04, 0x264d, 0x602f, 0x0000, 0x6150, 0xa185, 0x1400,
+	0x6052, 0x20a9, 0x0366, 0x1d04, 0x265b, 0x2091, 0x6000, 0x6020,
+	0xd09c, 0x1130, 0x015e, 0x6152, 0x001e, 0x6027, 0x0008, 0x0490,
+	0x080c, 0x27e0, 0x1f04, 0x265b, 0x015e, 0x6152, 0x001e, 0x6027,
+	0x0008, 0x0016, 0x6028, 0xc09c, 0x602a, 0x2011, 0x0003, 0x080c,
+	0x7d52, 0x2011, 0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41, 0x080c,
+	0x67b6, 0x0036, 0x2019, 0x0000, 0x080c, 0x7cc4, 0x003e, 0x60e3,
+	0x0000, 0x080c, 0xafd9, 0x080c, 0xaff4, 0xa085, 0x0001, 0x080c,
+	0x5919, 0x2001, 0xb100, 0x2003, 0x0004, 0x6027, 0x0008, 0x080c,
+	0x12d0, 0x001e, 0xa18c, 0xffd0, 0x6126, 0x0005, 0x0006, 0x0016,
+	0x0026, 0x00e6, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2071, 0xb100,
+	0x71c0, 0x70c2, 0xa116, 0x01f0, 0x81ff, 0x0128, 0x2011, 0x8011,
+	0x080c, 0x3d5b, 0x00b8, 0x2011, 0x8012, 0x080c, 0x3d5b, 0x2001,
+	0xb172, 0x2004, 0xd0fc, 0x1170, 0x0036, 0x00c6, 0x080c, 0x276b,
+	0x2061, 0x0100, 0x2019, 0x0028, 0x2009, 0x0000, 0x080c, 0x2b46,
+	0x00ce, 0x003e, 0x012e, 0x00fe, 0x00ee, 0x002e, 0x001e, 0x000e,
+	0x0005, 0x00c6, 0x00f6, 0x0006, 0x0026, 0x2061, 0x0100, 0xa190,
+	0x26e4, 0x2205, 0x60f2, 0x2011, 0x26f1, 0x2205, 0x60ee, 0x002e,
+	0x000e, 0x00fe, 0x00ce, 0x0005, 0x0840, 0x0840, 0x0840, 0x0580,
+	0x0420, 0x0348, 0x02c0, 0x0258, 0x0210, 0x01a8, 0x01a8, 0x01a8,
+	0x01a8, 0x0140, 0x00f8, 0x00d0, 0x00b0, 0x00a0, 0x2028, 0xa18c,
+	0x00ff, 0x2130, 0xa094, 0xff00, 0x1110, 0x81ff, 0x0118, 0x080c,
+	0x646d, 0x0038, 0xa080, 0x2c8c, 0x200d, 0xa18c, 0xff00, 0x810f,
+	0xa006, 0x0005, 0xa080, 0x2c8c, 0x200d, 0xa18c, 0x00ff, 0x0005,
+	0x00d6, 0x2069, 0x0140, 0x2001, 0xb114, 0x2003, 0x00ef, 0x20a9,
+	0x0010, 0xa006, 0x6852, 0x6856, 0x1f04, 0x271b, 0x00de, 0x0005,
+	0x0006, 0x00d6, 0x0026, 0x2069, 0x0140, 0x2001, 0xb114, 0x2102,
+	0x8114, 0x8214, 0x8214, 0x8214, 0x20a9, 0x0010, 0x6853, 0x0000,
+	0xa006, 0x82ff, 0x1128, 0xa184, 0x000f, 0xa080, 0xb008, 0x2005,
+	0x6856, 0x8211, 0x1f04, 0x2730, 0x002e, 0x00de, 0x000e, 0x0005,
+	0x00c6, 0x2061, 0xb100, 0x6030, 0x0110, 0xc09d, 0x0008, 0xc09c,
+	0x6032, 0x00ce, 0x0005, 0x0156, 0x00d6, 0x0026, 0x0016, 0x0006,
+	0x2069, 0x0140, 0x6980, 0xa116, 0x0180, 0xa112, 0x1230, 0x8212,
+	0x8210, 0x22a8, 0x2001, 0x0402, 0x0018, 0x22a8, 0x2001, 0x0404,
+	0x680e, 0x1f04, 0x2760, 0x680f, 0x0000, 0x000e, 0x001e, 0x002e,
+	0x00de, 0x015e, 0x0005, 0x2001, 0xb153, 0x2004, 0xd0c4, 0x0150,
+	0xd0a4, 0x0140, 0xa006, 0x0046, 0x2020, 0x2009, 0x002e, 0x080c,
+	0xacae, 0x004e, 0x0005, 0x00f6, 0x0016, 0x0026, 0x2079, 0x0140,
+	0x78c4, 0xd0dc, 0x0548, 0xa084, 0x0700, 0xa08e, 0x0300, 0x1520,
+	0x2011, 0x0000, 0x2009, 0x0002, 0x2300, 0xa080, 0x0020, 0x2018,
+	0x2300, 0x080c, 0x68b3, 0x2011, 0x0030, 0x2200, 0x8007, 0xa085,
+	0x004c, 0x78c2, 0x2009, 0x0204, 0x210c, 0x2200, 0xa100, 0x2009,
+	0x0138, 0x200a, 0x080c, 0x58d5, 0x1118, 0x2009, 0xb38f, 0x200a,
+	0x002e, 0x001e, 0x00fe, 0x0005, 0x78c3, 0x0000, 0x0cc8, 0x0126,
+	0x2091, 0x2800, 0x0006, 0x0016, 0x0026, 0x2001, 0x0170, 0x200c,
+	0x8000, 0x2014, 0xa184, 0x0003, 0x0110, 0x0804, 0x1a84, 0x002e,
+	0x001e, 0x000e, 0x012e, 0x0005, 0x0006, 0x2001, 0x0100, 0x2004,
+	0xa082, 0x0005, 0x000e, 0x0268, 0x2001, 0x0170, 0x200c, 0xa18c,
+	0x00ff, 0xa18e, 0x004c, 0x1128, 0x200c, 0xa18c, 0xff00, 0x810f,
+	0x0010, 0x2009, 0x0000, 0x2001, 0x0204, 0x2004, 0xa108, 0x0005,
+	0x0006, 0x0156, 0x00f6, 0x2079, 0x0100, 0x20a9, 0x000a, 0x7854,
+	0xd08c, 0x1110, 0x1f04, 0x27e7, 0x00fe, 0x015e, 0x000e, 0x0005,
+	0x0016, 0x00c6, 0x0006, 0x2061, 0x0100, 0x6030, 0x0006, 0x6048,
+	0x0006, 0x60e4, 0x0006, 0x60e8, 0x0006, 0x6050, 0x0006, 0x60f0,
+	0x0006, 0x60ec, 0x0006, 0x600c, 0x0006, 0x6004, 0x0006, 0x6028,
+	0x0006, 0x60e0, 0x0006, 0x602f, 0x0100, 0x602f, 0x0000, 0xe000,
+	0xe000, 0xe000, 0xe000, 0x602f, 0x0040, 0x602f, 0x0000, 0x000e,
+	0x60e2, 0x000e, 0x602a, 0x000e, 0x6006, 0x000e, 0x600e, 0x000e,
+	0x60ee, 0x000e, 0x60f2, 0x000e, 0x6052, 0x000e, 0x60ea, 0x000e,
+	0x60e6, 0x000e, 0x604a, 0x000e, 0x6032, 0x6036, 0x2008, 0x080c,
+	0x2720, 0x000e, 0x00ce, 0x001e, 0x0005, 0x2009, 0x0171, 0x2104,
+	0xd0dc, 0x0140, 0x2009, 0x0170, 0x2104, 0x200b, 0x0080, 0xe000,
+	0xe000, 0x200a, 0x0005, 0x28d3, 0x28d7, 0x28db, 0x28e1, 0x28e7,
+	0x28ed, 0x28f3, 0x28fb, 0x2903, 0x2909, 0x290f, 0x2917, 0x291f,
+	0x2927, 0x292f, 0x2939, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2945, 0x2945, 0x294b, 0x294b, 0x2952,
+	0x2952, 0x2959, 0x2959, 0x2962, 0x2962, 0x2969, 0x2969, 0x2972,
+	0x2972, 0x297b, 0x297b, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986, 0x2986,
+	0x2986, 0x2986, 0x2986, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943, 0x2943,
+	0x2943, 0x2943, 0x2943, 0x0106, 0x0006, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c, 0x23f3, 0x0804,
+	0x298e, 0x0106, 0x0006, 0x080c, 0x23f3, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x22b0, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c,
+	0x22b0, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c, 0x23f3, 0x080c,
+	0x22b0, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c, 0x23f3, 0x080c,
+	0x22b0, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c, 0x2302, 0x0804,
+	0x298e, 0x0106, 0x0006, 0x080c, 0x2302, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x23f3, 0x080c, 0x2302, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x23f3, 0x080c, 0x2302, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x22b0, 0x080c, 0x2302, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x22b0, 0x080c, 0x2302, 0x0804, 0x298e, 0x0106,
+	0x0006, 0x080c, 0x23f3, 0x080c, 0x22b0, 0x080c, 0x2302, 0x0804,
+	0x298e, 0x0106, 0x0006, 0x080c, 0x23f3, 0x080c, 0x22b0, 0x080c,
+	0x2302, 0x0804, 0x298e, 0xe000, 0x0cf0, 0x0106, 0x0006, 0x080c,
+	0x27af, 0x0804, 0x298e, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c,
+	0x23f3, 0x04e0, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c, 0x22b0,
+	0x04a8, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c, 0x23f3, 0x080c,
+	0x22b0, 0x0460, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c, 0x2302,
+	0x0428, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c, 0x23f3, 0x080c,
+	0x2302, 0x00e0, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c, 0x22b0,
+	0x080c, 0x2302, 0x0098, 0x0106, 0x0006, 0x080c, 0x27af, 0x080c,
+	0x23f3, 0x080c, 0x22b0, 0x080c, 0x2302, 0x0040, 0x20d1, 0x0000,
+	0x20d1, 0x0001, 0x20d1, 0x0000, 0x080c, 0x14fa, 0x000e, 0x010e,
+	0x000d, 0x00c6, 0x0026, 0x0046, 0x2021, 0x0000, 0x080c, 0x517b,
+	0x1904, 0x2a6e, 0x72d0, 0x2001, 0xb39e, 0x2004, 0xa005, 0x1110,
+	0xd29c, 0x0148, 0xd284, 0x1138, 0xd2bc, 0x1904, 0x2a6e, 0x080c,
+	0x2a72, 0x0804, 0x2a6e, 0xd2cc, 0x1904, 0x2a6e, 0x080c, 0x58d5,
+	0x1120, 0x709b, 0xffff, 0x0804, 0x2a6e, 0xd294, 0x0120, 0x709b,
+	0xffff, 0x0804, 0x2a6e, 0x2001, 0xb114, 0x203c, 0x7284, 0xd284,
+	0x0904, 0x2a10, 0xd28c, 0x1904, 0x2a10, 0x0036, 0x7398, 0xa38e,
+	0xffff, 0x1110, 0x2019, 0x0001, 0x8314, 0xa2e0, 0xb7c0, 0x2c04,
+	0xa38c, 0x0001, 0x0120, 0xa084, 0xff00, 0x8007, 0x0010, 0xa084,
+	0x00ff, 0xa70e, 0x0560, 0xa08e, 0x0000, 0x0548, 0xa08e, 0x00ff,
+	0x1150, 0x7230, 0xd284, 0x1538, 0x7284, 0xc28d, 0x7286, 0x709b,
+	0xffff, 0x003e, 0x0428, 0x2009, 0x0000, 0x080c, 0x26f6, 0x080c,
+	0x4dc5, 0x11b8, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1150,
+	0x7030, 0xd08c, 0x0118, 0x6000, 0xd0bc, 0x0120, 0x080c, 0x2a85,
+	0x0140, 0x0028, 0x080c, 0x2bb4, 0x080c, 0x2ab3, 0x0110, 0x8318,
+	0x0818, 0x739a, 0x0010, 0x709b, 0xffff, 0x003e, 0x0804, 0x2a6e,
+	0xa780, 0x2c8c, 0x203d, 0xa7bc, 0xff00, 0x873f, 0x2041, 0x007e,
+	0x7098, 0xa096, 0xffff, 0x1120, 0x2009, 0x0000, 0x28a8, 0x0050,
+	0xa812, 0x0220, 0x2008, 0xa802, 0x20a8, 0x0020, 0x709b, 0xffff,
+	0x0804, 0x2a6e, 0x2700, 0x0156, 0x0016, 0xa106, 0x05a0, 0xc484,
+	0x080c, 0x4e21, 0x0120, 0x080c, 0x4dc5, 0x15a8, 0x0008, 0xc485,
+	0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1130, 0x7030, 0xd08c,
+	0x01e8, 0x6000, 0xd0bc, 0x11d0, 0x7284, 0xd28c, 0x0188, 0x6004,
+	0xa084, 0x00ff, 0xa082, 0x0006, 0x02b0, 0xd484, 0x1118, 0x080c,
+	0x4de4, 0x0028, 0x080c, 0x2c41, 0x0170, 0x080c, 0x2c6e, 0x0058,
+	0x080c, 0x2bb4, 0x080c, 0x2ab3, 0x0170, 0x0028, 0x080c, 0x2c41,
+	0x0110, 0x0419, 0x0140, 0x001e, 0x8108, 0x015e, 0x1f04, 0x2a2a,
+	0x709b, 0xffff, 0x0018, 0x001e, 0x015e, 0x719a, 0x004e, 0x002e,
+	0x00ce, 0x0005, 0x00c6, 0x0016, 0x709b, 0x0001, 0x2009, 0x007e,
+	0x080c, 0x4dc5, 0x1138, 0x080c, 0x2bb4, 0x04a9, 0x0118, 0x70d0,
+	0xc0bd, 0x70d2, 0x001e, 0x00ce, 0x0005, 0x0016, 0x0076, 0x00d6,
+	0x00c6, 0x2c68, 0x2001, 0xb157, 0x2004, 0xa084, 0x00ff, 0x6842,
+	0x080c, 0x9ae4, 0x01d8, 0x2d00, 0x601a, 0x080c, 0x9c35, 0x601f,
+	0x0001, 0x2001, 0x0000, 0x080c, 0x4d63, 0x2001, 0x0000, 0x080c,
+	0x4d75, 0x0126, 0x2091, 0x8000, 0x7094, 0x8000, 0x7096, 0x012e,
+	0x2009, 0x0004, 0x080c, 0x831a, 0xa085, 0x0001, 0x00ce, 0x00de,
+	0x007e, 0x001e, 0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x2c68,
+	0x2001, 0xb157, 0x2004, 0xa084, 0x00ff, 0x6842, 0x080c, 0x9ae4,
+	0x0550, 0x2d00, 0x601a, 0x6800, 0xc0c4, 0x6802, 0x68a0, 0xa086,
+	0x007e, 0x0140, 0x6804, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1110,
+	0x080c, 0x2b73, 0x080c, 0x9c35, 0x601f, 0x0001, 0x2001, 0x0000,
+	0x080c, 0x4d63, 0x2001, 0x0002, 0x080c, 0x4d75, 0x0126, 0x2091,
+	0x8000, 0x7094, 0x8000, 0x7096, 0x012e, 0x2009, 0x0002, 0x080c,
+	0x831a, 0xa085, 0x0001, 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005,
+	0x00c6, 0x0026, 0x2009, 0x0080, 0x080c, 0x4dc5, 0x1120, 0x0031,
+	0x0110, 0x70d7, 0xffff, 0x002e, 0x00ce, 0x0005, 0x0016, 0x0076,
+	0x00d6, 0x00c6, 0x2c68, 0x080c, 0x8295, 0x01d8, 0x2d00, 0x601a,
+	0x080c, 0x9c35, 0x601f, 0x0001, 0x2001, 0x0000, 0x080c, 0x4d63,
+	0x2001, 0x0002, 0x080c, 0x4d75, 0x0126, 0x2091, 0x8000, 0x70d8,
+	0x8000, 0x70da, 0x012e, 0x2009, 0x0002, 0x080c, 0x831a, 0xa085,
+	0x0001, 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005, 0x00c6, 0x00d6,
+	0x0126, 0x2091, 0x8000, 0x2009, 0x007f, 0x080c, 0x4dc5, 0x1190,
+	0x2c68, 0x080c, 0x8295, 0x0170, 0x2d00, 0x601a, 0x6312, 0x601f,
+	0x0001, 0x620a, 0x080c, 0x9c35, 0x2009, 0x0022, 0x080c, 0x831a,
+	0xa085, 0x0001, 0x012e, 0x00de, 0x00ce, 0x0005, 0x00e6, 0x00c6,
+	0x0066, 0x0036, 0x0026, 0x080c, 0x6b41, 0x080c, 0x6aeb, 0x080c,
+	0x8cc4, 0x2130, 0x81ff, 0x0128, 0x20a9, 0x007e, 0x2009, 0x0000,
+	0x0020, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x080c, 0x4e21,
+	0x1120, 0x080c, 0x501c, 0x080c, 0x4a80, 0x001e, 0x8108, 0x1f04,
+	0x2b5d, 0x86ff, 0x1110, 0x080c, 0x11d8, 0x002e, 0x003e, 0x006e,
+	0x00ce, 0x00ee, 0x0005, 0x00e6, 0x00c6, 0x0036, 0x0026, 0x0016,
+	0x6218, 0x2270, 0x72a0, 0x0026, 0x2019, 0x0029, 0x080c, 0x6b35,
+	0x0076, 0x2039, 0x0000, 0x080c, 0x6a6b, 0x2c08, 0x080c, 0xaa51,
+	0x007e, 0x001e, 0x2e60, 0x080c, 0x501c, 0x6210, 0x6314, 0x080c,
+	0x4a80, 0x6212, 0x6316, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee,
+	0x0005, 0x00e6, 0x0006, 0x6018, 0xa080, 0x0028, 0x2004, 0xa086,
+	0x0080, 0x0150, 0x2071, 0xb100, 0x7094, 0xa005, 0x0110, 0x8001,
+	0x7096, 0x000e, 0x00ee, 0x0005, 0x2071, 0xb100, 0x70d8, 0xa005,
+	0x0dc0, 0x8001, 0x70da, 0x0ca8, 0x6000, 0xc08c, 0x6002, 0x0005,
+	0x00f6, 0x00e6, 0x00c6, 0x0036, 0x0026, 0x0016, 0x0156, 0x2178,
+	0x81ff, 0x1118, 0x20a9, 0x0001, 0x0098, 0x2001, 0xb153, 0x2004,
+	0xd0c4, 0x0150, 0xd0a4, 0x0140, 0xa006, 0x0046, 0x2020, 0x2009,
+	0x002d, 0x080c, 0xacae, 0x004e, 0x20a9, 0x00ff, 0x2011, 0x0000,
+	0x0026, 0xa28e, 0x007e, 0x0904, 0x2c20, 0xa28e, 0x007f, 0x0904,
+	0x2c20, 0xa28e, 0x0080, 0x05e0, 0xa288, 0xb235, 0x210c, 0x81ff,
+	0x05b8, 0x8fff, 0x1148, 0x2001, 0xb3bd, 0x0006, 0x2003, 0x0001,
+	0x04d9, 0x000e, 0x2003, 0x0000, 0x00c6, 0x2160, 0x2001, 0x0001,
+	0x080c, 0x5185, 0x00ce, 0x2019, 0x0029, 0x080c, 0x6b35, 0x0076,
+	0x2039, 0x0000, 0x080c, 0x6a6b, 0x00c6, 0x0026, 0x2160, 0x6204,
+	0xa294, 0x00ff, 0xa286, 0x0006, 0x1118, 0x6007, 0x0404, 0x0028,
+	0x2001, 0x0004, 0x8007, 0xa215, 0x6206, 0x002e, 0x00ce, 0x0016,
+	0x2c08, 0x080c, 0xaa51, 0x001e, 0x007e, 0x2160, 0x080c, 0x501c,
+	0x002e, 0x8210, 0x1f04, 0x2bd8, 0x015e, 0x001e, 0x002e, 0x003e,
+	0x00ce, 0x00ee, 0x00fe, 0x0005, 0x0046, 0x0026, 0x0016, 0x2001,
+	0xb153, 0x2004, 0xd0c4, 0x0148, 0xd0a4, 0x0138, 0xa006, 0x2220,
+	0x8427, 0x2009, 0x0029, 0x080c, 0xacae, 0x001e, 0x002e, 0x004e,
+	0x0005, 0x0016, 0x0026, 0x0036, 0x00c6, 0x7284, 0x82ff, 0x01f8,
+	0x2011, 0xb153, 0x2214, 0xd2ac, 0x11d0, 0x2100, 0x080c, 0x270a,
+	0x81ff, 0x01b8, 0x2019, 0x0001, 0x8314, 0xa2e0, 0xb7c0, 0x2c04,
+	0xd384, 0x0120, 0xa084, 0xff00, 0x8007, 0x0010, 0xa084, 0x00ff,
+	0xa116, 0x0138, 0xa096, 0x00ff, 0x0110, 0x8318, 0x0c68, 0xa085,
+	0x0001, 0x00ce, 0x003e, 0x002e, 0x001e, 0x0005, 0x0016, 0x00c6,
+	0x0126, 0x2091, 0x8000, 0xa180, 0xb235, 0x2004, 0xa065, 0x0158,
+	0x0016, 0x00c6, 0x2061, 0xb4e4, 0x001e, 0x611a, 0x080c, 0x2b73,
+	0x001e, 0x080c, 0x4de4, 0x012e, 0x00ce, 0x001e, 0x0005, 0x2001,
+	0xb134, 0x2004, 0xd0cc, 0x0005, 0x7eef, 0x7de8, 0x7ce4, 0x80e2,
+	0x7be1, 0x80e0, 0x80dc, 0x80da, 0x7ad9, 0x80d6, 0x80d5, 0x80d4,
+	0x80d3, 0x80d2, 0x80d1, 0x79ce, 0x78cd, 0x80cc, 0x80cb, 0x80ca,
+	0x80c9, 0x80c7, 0x80c6, 0x77c5, 0x76c3, 0x80bc, 0x80ba, 0x75b9,
+	0x80b6, 0x74b5, 0x73b4, 0x72b3, 0x80b2, 0x80b1, 0x80ae, 0x71ad,
+	0x80ac, 0x70ab, 0x6faa, 0x6ea9, 0x80a7, 0x6da6, 0x6ca5, 0x6ba3,
+	0x6a9f, 0x699e, 0x689d, 0x809b, 0x8098, 0x6797, 0x6690, 0x658f,
+	0x6488, 0x6384, 0x6282, 0x8081, 0x8080, 0x617c, 0x607a, 0x8079,
+	0x5f76, 0x8075, 0x8074, 0x8073, 0x8072, 0x8071, 0x806e, 0x5e6d,
+	0x806c, 0x5d6b, 0x5c6a, 0x5b69, 0x8067, 0x5a66, 0x5965, 0x5863,
+	0x575c, 0x565a, 0x5559, 0x8056, 0x8055, 0x5454, 0x5353, 0x5252,
+	0x5151, 0x504e, 0x4f4d, 0x804c, 0x804b, 0x4e4a, 0x4d49, 0x8047,
+	0x4c46, 0x8045, 0x8043, 0x803c, 0x803a, 0x8039, 0x8036, 0x4b35,
+	0x8034, 0x4a33, 0x4932, 0x4831, 0x802e, 0x472d, 0x462c, 0x452b,
+	0x442a, 0x4329, 0x4227, 0x8026, 0x8025, 0x4123, 0x401f, 0x3f1e,
+	0x3e1d, 0x3d1b, 0x3c18, 0x8017, 0x8010, 0x3b0f, 0x3a08, 0x8004,
+	0x3902, 0x8001, 0x8000, 0x8000, 0x3800, 0x3700, 0x3600, 0x8000,
+	0x3500, 0x8000, 0x8000, 0x8000, 0x3400, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x3300, 0x3200, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x3100, 0x3000, 0x8000, 0x8000, 0x2f00,
+	0x8000, 0x2e00, 0x2d00, 0x2c00, 0x8000, 0x8000, 0x8000, 0x2b00,
+	0x8000, 0x2a00, 0x2900, 0x2800, 0x8000, 0x2700, 0x2600, 0x2500,
+	0x2400, 0x2300, 0x2200, 0x8000, 0x8000, 0x2100, 0x2000, 0x1f00,
+	0x1e00, 0x1d00, 0x1c00, 0x8000, 0x8000, 0x1b00, 0x1a00, 0x8000,
+	0x1900, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x1800,
+	0x8000, 0x1700, 0x1600, 0x1500, 0x8000, 0x1400, 0x1300, 0x1200,
+	0x1100, 0x1000, 0x0f00, 0x8000, 0x8000, 0x0e00, 0x0d00, 0x0c00,
+	0x0b00, 0x0a00, 0x0900, 0x8000, 0x8000, 0x0800, 0x0700, 0x8000,
+	0x0600, 0x8000, 0x8000, 0x8000, 0x0500, 0x0400, 0x0300, 0x8000,
+	0x0200, 0x8000, 0x8000, 0x8000, 0x0100, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x0000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x2071, 0xb182, 0x7003, 0x0002,
+	0xa006, 0x7012, 0x7016, 0x703a, 0x703e, 0x7033, 0xb192, 0x7037,
+	0xb192, 0x7007, 0x0001, 0x2061, 0xb1d2, 0x6003, 0x0002, 0x0005,
+	0x1004, 0x2db2, 0x0e04, 0x2db2, 0x2071, 0xb182, 0x2b78, 0x7818,
+	0xd084, 0x1140, 0x2a60, 0x7820, 0xa08e, 0x0069, 0x1904, 0x2e97,
+	0x0804, 0x2e30, 0x0005, 0x2071, 0xb182, 0x7004, 0x0002, 0x2dbb,
+	0x2dbc, 0x2dc5, 0x2dd6, 0x0005, 0x1004, 0x2dc4, 0x0e04, 0x2dc4,
+	0x2b78, 0x7818, 0xd084, 0x01e8, 0x0005, 0x2b78, 0x2061, 0xb1d2,
+	0x6008, 0xa08e, 0x0100, 0x0128, 0xa086, 0x0200, 0x0904, 0x2e91,
+	0x0005, 0x7014, 0x2068, 0x2a60, 0x7018, 0x0807, 0x7010, 0x2068,
+	0x6834, 0xa086, 0x0103, 0x0108, 0x0005, 0x2a60, 0x2b78, 0x7018,
+	0x0807, 0x2a60, 0x7820, 0xa08a, 0x0040, 0x1210, 0x61c0, 0x0042,
+	0x2100, 0xa08a, 0x003f, 0x1a04, 0x2e8e, 0x61c0, 0x0804, 0x2e30,
+	0x2e72, 0x2e9d, 0x2ea5, 0x2ea9, 0x2eb1, 0x2eb7, 0x2ebb, 0x2ec7,
+	0x2eca, 0x2ed4, 0x2ed7, 0x2e8e, 0x2e8e, 0x2e8e, 0x2eda, 0x2e8e,
+	0x2ee9, 0x2f00, 0x2f17, 0x2f8e, 0x2f93, 0x2fbc, 0x300d, 0x301e,
+	0x303d, 0x3075, 0x307f, 0x308c, 0x309f, 0x30c0, 0x30c9, 0x30ff,
+	0x3105, 0x2e8e, 0x312e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e,
+	0x3135, 0x313f, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e,
+	0x2e8e, 0x2e8e, 0x3147, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e,
+	0x3159, 0x3161, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e,
+	0x0002, 0x318b, 0x31df, 0x323a, 0x324d, 0x2e8e, 0x3267, 0x368e,
+	0x40ba, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e,
+	0x2e8e, 0x2ed4, 0x2ed7, 0x3690, 0x2e8e, 0x369d, 0x414a, 0x41a5,
+	0x4209, 0x2e8e, 0x4268, 0x428e, 0x42ad, 0x42df, 0x2e8e, 0x2e8e,
+	0x2e8e, 0x36a1, 0x3842, 0x385c, 0x387a, 0x38db, 0x393b, 0x3946,
+	0x397e, 0x398d, 0x399c, 0x399f, 0x39c2, 0x3a0c, 0x3a84, 0x3a91,
+	0x3b92, 0x3cb2, 0x3cdb, 0x3dd9, 0x3dfb, 0x3e07, 0x3e40, 0x3f04,
+	0x2e8e, 0x2e8e, 0x2e8e, 0x2e8e, 0x3f6c, 0x3f87, 0x3ff9, 0x40ab,
+	0x713c, 0x0000, 0x2021, 0x4000, 0x080c, 0x3d38, 0x0126, 0x2091,
+	0x8000, 0x0e04, 0x2e7e, 0x7818, 0xd084, 0x0110, 0x012e, 0x0cb0,
+	0x7c22, 0x7926, 0x7a2a, 0x7b2e, 0x781b, 0x0001, 0x2091, 0x4080,
+	0x7007, 0x0001, 0x2091, 0x5000, 0x012e, 0x0005, 0x2021, 0x4001,
+	0x0c18, 0x2021, 0x4002, 0x0c00, 0x2021, 0x4003, 0x08e8, 0x2021,
+	0x4005, 0x08d0, 0x2021, 0x4006, 0x08b8, 0xa02e, 0x2520, 0x7b28,
+	0x7a2c, 0x7824, 0x7930, 0x0804, 0x3d45, 0x7823, 0x0004, 0x7824,
+	0x0807, 0xa02e, 0x2520, 0x7b28, 0x7a2c, 0x7824, 0x7930, 0x0804,
+	0x3d48, 0x7924, 0x7828, 0x2114, 0x200a, 0x0804, 0x2e72, 0x7924,
+	0x2114, 0x0804, 0x2e72, 0x2099, 0x0009, 0x20a1, 0x0009, 0x20a9,
+	0x0007, 0x53a3, 0x7924, 0x7a28, 0x7b2c, 0x0804, 0x2e72, 0x7824,
+	0x2060, 0x0090, 0x2009, 0x0002, 0x2011, 0x0001, 0x2019, 0x0022,
+	0x783b, 0x0017, 0x0804, 0x2e72, 0x7d38, 0x7c3c, 0x0840, 0x7d38,
+	0x7c3c, 0x0888, 0x2061, 0x1000, 0xe10c, 0xa006, 0x2c15, 0xa200,
+	0x8c60, 0x8109, 0x1dd8, 0x2010, 0xa005, 0x0904, 0x2e72, 0x0804,
+	0x2e94, 0x2069, 0xb152, 0x7824, 0x7930, 0xa11a, 0x1a04, 0x2e9a,
+	0x8019, 0x0904, 0x2e9a, 0x684a, 0x6942, 0x782c, 0x6852, 0x7828,
+	0x6856, 0xa006, 0x685a, 0x685e, 0x080c, 0x5ba6, 0x0804, 0x2e72,
+	0x2069, 0xb152, 0x7824, 0x7934, 0xa11a, 0x1a04, 0x2e9a, 0x8019,
+	0x0904, 0x2e9a, 0x684e, 0x6946, 0x782c, 0x6862, 0x7828, 0x6866,
+	0xa006, 0x686a, 0x686e, 0x080c, 0x523e, 0x0804, 0x2e72, 0xa02e,
+	0x2520, 0x81ff, 0x1904, 0x2e97, 0x7924, 0x7b28, 0x7a2c, 0x20a9,
+	0x0005, 0x20a1, 0xb189, 0x41a1, 0x080c, 0x3d04, 0x0904, 0x2e97,
+	0x2009, 0x0020, 0x080c, 0x3d45, 0x701b, 0x2f2f, 0x0005, 0x6834,
+	0x2008, 0xa084, 0x00ff, 0xa096, 0x0011, 0x0120, 0xa096, 0x0019,
+	0x1904, 0x2e97, 0x810f, 0xa18c, 0x00ff, 0x0904, 0x2e97, 0x710e,
+	0x700c, 0x8001, 0x0528, 0x700e, 0x080c, 0x3d04, 0x0904, 0x2e97,
+	0x2009, 0x0020, 0x2061, 0xb1d2, 0x6224, 0x6328, 0x642c, 0x6530,
+	0xa290, 0x0040, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000,
+	0x080c, 0x3d45, 0x701b, 0x2f5d, 0x0005, 0x6834, 0xa084, 0x00ff,
+	0xa096, 0x0002, 0x0120, 0xa096, 0x000a, 0x1904, 0x2e97, 0x08c0,
+	0x7010, 0x2068, 0x6838, 0xc0fd, 0x683a, 0x080c, 0x4cc1, 0x1128,
+	0x7007, 0x0003, 0x701b, 0x2f77, 0x0005, 0x080c, 0x5344, 0x0126,
+	0x2091, 0x8000, 0x20a9, 0x0005, 0x2099, 0xb189, 0x530a, 0x2100,
+	0xa210, 0xa399, 0x0000, 0xa4a1, 0x0000, 0xa5a9, 0x0000, 0xad80,
+	0x000d, 0x2009, 0x0020, 0x012e, 0x0804, 0x3d48, 0x61a8, 0x7824,
+	0x60aa, 0x0804, 0x2e72, 0x2091, 0x8000, 0x7823, 0x4000, 0x7827,
+	0x4953, 0x782b, 0x5020, 0x782f, 0x2020, 0x2009, 0x017f, 0x2104,
+	0x7832, 0x3f00, 0x7836, 0x2061, 0x0100, 0x6200, 0x2061, 0x0200,
+	0x603c, 0x8007, 0xa205, 0x783a, 0x2009, 0x04fd, 0x2104, 0x783e,
+	0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2071, 0x0010,
+	0x20c1, 0x00f0, 0x0804, 0x0427, 0x81ff, 0x1904, 0x2e97, 0x7924,
+	0x810f, 0xa18c, 0x00ff, 0x080c, 0x4e21, 0x1904, 0x2e9a, 0x7e38,
+	0xa684, 0x3fff, 0xa082, 0x4000, 0x0210, 0x0804, 0x2e9a, 0x7c28,
+	0x7d2c, 0x080c, 0x4fe3, 0xd28c, 0x1118, 0x080c, 0x4f8e, 0x0010,
+	0x080c, 0x4fbc, 0x1518, 0x2061, 0xb800, 0x0126, 0x2091, 0x8000,
+	0x6000, 0xa086, 0x0000, 0x0148, 0x6010, 0xa06d, 0x0130, 0x683c,
+	0xa406, 0x1118, 0x6840, 0xa506, 0x0150, 0x012e, 0xace0, 0x0018,
+	0x2001, 0xb116, 0x2004, 0xac02, 0x1a04, 0x2e97, 0x0c30, 0x080c,
+	0x955c, 0x012e, 0x0904, 0x2e97, 0x0804, 0x2e72, 0xa00e, 0x2001,
+	0x0005, 0x080c, 0x5344, 0x0126, 0x2091, 0x8000, 0x080c, 0x9ae0,
+	0x080c, 0x5271, 0x012e, 0x0804, 0x2e72, 0x81ff, 0x1904, 0x2e97,
+	0x080c, 0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4ee3, 0x0904, 0x2e97,
+	0x080c, 0x4fef, 0x0904, 0x2e97, 0x0804, 0x2e72, 0x81ff, 0x1904,
+	0x2e97, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x080c, 0x505b, 0x0904,
+	0x2e97, 0x2019, 0x0005, 0x7924, 0x080c, 0x500a, 0x0904, 0x2e97,
+	0x7828, 0xa08a, 0x1000, 0x1a04, 0x2e9a, 0x8003, 0x800b, 0x810b,
+	0xa108, 0x080c, 0x674e, 0x0804, 0x2e72, 0x0126, 0x2091, 0x8000,
+	0x81ff, 0x0118, 0x2009, 0x0001, 0x0450, 0x2029, 0x00ff, 0x644c,
+	0x2400, 0xa506, 0x01f8, 0x2508, 0x080c, 0x4e21, 0x11d8, 0x080c,
+	0x505b, 0x1128, 0x2009, 0x0002, 0x62b0, 0x2518, 0x00c0, 0x2019,
+	0x0004, 0xa00e, 0x080c, 0x500a, 0x1118, 0x2009, 0x0006, 0x0078,
+	0x7824, 0xa08a, 0x1000, 0x1270, 0x8003, 0x800b, 0x810b, 0xa108,
+	0x080c, 0x674e, 0x8529, 0x1ae0, 0x012e, 0x0804, 0x2e72, 0x012e,
+	0x0804, 0x2e97, 0x012e, 0x0804, 0x2e9a, 0x080c, 0x3d19, 0x0904,
+	0x2e9a, 0x080c, 0x4f49, 0x080c, 0x4fe3, 0x0804, 0x2e72, 0x81ff,
+	0x1904, 0x2e97, 0x080c, 0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4f3a,
+	0x080c, 0x4fe3, 0x0804, 0x2e72, 0x81ff, 0x1904, 0x2e97, 0x080c,
+	0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4fbe, 0x0904, 0x2e97, 0x080c,
+	0x4d05, 0x080c, 0x4f87, 0x080c, 0x4fe3, 0x0804, 0x2e72, 0x080c,
+	0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4ee3, 0x0904, 0x2e97, 0x62a0,
+	0x2019, 0x0005, 0x00c6, 0x080c, 0x501c, 0x2061, 0x0000, 0x080c,
+	0x6b35, 0x0076, 0x2039, 0x0000, 0x080c, 0x6a6b, 0x2009, 0x0000,
+	0x080c, 0xaa51, 0x007e, 0x00ce, 0x080c, 0x4fe3, 0x0804, 0x2e72,
+	0x080c, 0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4fe3, 0x2208, 0x0804,
+	0x2e72, 0x0156, 0x00d6, 0x00e6, 0x2069, 0xb214, 0x6810, 0x6914,
+	0xa10a, 0x1210, 0x2009, 0x0000, 0x6816, 0x2011, 0x0000, 0x2019,
+	0x0000, 0x20a9, 0x007e, 0x2069, 0xb235, 0x2d04, 0xa075, 0x0130,
+	0x704c, 0x0071, 0xa210, 0x7080, 0x0059, 0xa318, 0x8d68, 0x1f04,
+	0x30dd, 0x2300, 0xa218, 0x00ee, 0x00de, 0x015e, 0x0804, 0x2e72,
+	0x00f6, 0x0016, 0xa07d, 0x0140, 0x2001, 0x0000, 0x8000, 0x2f0c,
+	0x81ff, 0x0110, 0x2178, 0x0cd0, 0x001e, 0x00fe, 0x0005, 0x2069,
+	0xb214, 0x6910, 0x62ac, 0x0804, 0x2e72, 0x81ff, 0x1904, 0x2e97,
+	0x614c, 0xa190, 0x2c8c, 0x2215, 0xa294, 0x00ff, 0x636c, 0x83ff,
+	0x0108, 0x6270, 0x67d0, 0xd79c, 0x0118, 0x2031, 0x0001, 0x0090,
+	0xd7ac, 0x0118, 0x2031, 0x0003, 0x0068, 0xd7a4, 0x0118, 0x2031,
+	0x0002, 0x0040, 0x080c, 0x58d5, 0x1118, 0x2031, 0x0004, 0x0010,
+	0x2031, 0x0000, 0x7e3a, 0x7f3e, 0x0804, 0x2e72, 0x613c, 0x6240,
+	0x2019, 0xb3b5, 0x231c, 0x0804, 0x2e72, 0x0126, 0x2091, 0x8000,
+	0x6134, 0xa006, 0x2010, 0x2018, 0x012e, 0x0804, 0x2e72, 0x080c,
+	0x3d29, 0x0904, 0x2e9a, 0x6244, 0x6338, 0x0804, 0x2e72, 0x613c,
+	0x6240, 0x7824, 0x603e, 0x7b28, 0x6342, 0x2069, 0xb152, 0x831f,
+	0xa305, 0x6816, 0x782c, 0x2069, 0xb3b5, 0x2d1c, 0x206a, 0x0804,
+	0x2e72, 0x0126, 0x2091, 0x8000, 0x7824, 0x6036, 0x012e, 0x0804,
+	0x2e72, 0x7838, 0xa005, 0x01a8, 0x7828, 0xa025, 0x0904, 0x2e9a,
+	0x782c, 0xa02d, 0x0904, 0x2e9a, 0xa00e, 0x080c, 0x4e21, 0x1120,
+	0x6244, 0x6338, 0x6446, 0x653a, 0xa186, 0x00ff, 0x0190, 0x8108,
+	0x0ca0, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x7828, 0xa00d, 0x0904,
+	0x2e9a, 0x782c, 0xa005, 0x0904, 0x2e9a, 0x6244, 0x6146, 0x6338,
+	0x603a, 0x0804, 0x2e72, 0x2001, 0xb100, 0x2004, 0xa086, 0x0003,
+	0x1904, 0x2e97, 0x00c6, 0x2061, 0x0100, 0x7924, 0x810f, 0xa18c,
+	0x00ff, 0xa196, 0x00ff, 0x1130, 0x2001, 0xb114, 0x2004, 0xa085,
+	0xff00, 0x0078, 0xa182, 0x007f, 0x16a0, 0xa188, 0x2c8c, 0x210d,
+	0xa18c, 0x00ff, 0x2001, 0xb114, 0x2004, 0xa116, 0x0550, 0x810f,
+	0xa105, 0x0126, 0x2091, 0x8000, 0x0006, 0x080c, 0x8295, 0x000e,
+	0x01e0, 0x601a, 0x600b, 0xbc09, 0x601f, 0x0001, 0x080c, 0x3d04,
+	0x01d8, 0x6837, 0x0000, 0x7007, 0x0003, 0x6833, 0x0000, 0x6838,
+	0xc0fd, 0x683a, 0x701b, 0x3233, 0x2d00, 0x6012, 0x2009, 0x0032,
+	0x080c, 0x831a, 0x012e, 0x00ce, 0x0005, 0x012e, 0x00ce, 0x0804,
+	0x2e97, 0x00ce, 0x0804, 0x2e9a, 0x080c, 0x82eb, 0x0cb0, 0x2001,
+	0xb100, 0x2004, 0xa086, 0x0003, 0x1904, 0x2e97, 0x00c6, 0x2061,
+	0x0100, 0x7924, 0x810f, 0xa18c, 0x00ff, 0xa196, 0x00ff, 0x1130,
+	0x2001, 0xb114, 0x2004, 0xa085, 0xff00, 0x0078, 0xa182, 0x007f,
+	0x16a0, 0xa188, 0x2c8c, 0x210d, 0xa18c, 0x00ff, 0x2001, 0xb114,
+	0x2004, 0xa116, 0x0550, 0x810f, 0xa105, 0x0126, 0x2091, 0x8000,
+	0x0006, 0x080c, 0x8295, 0x000e, 0x01e0, 0x601a, 0x600b, 0xbc05,
+	0x601f, 0x0001, 0x080c, 0x3d04, 0x01d8, 0x6837, 0x0000, 0x7007,
+	0x0003, 0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x701b, 0x3233,
+	0x2d00, 0x6012, 0x2009, 0x0032, 0x080c, 0x831a, 0x012e, 0x00ce,
+	0x0005, 0x012e, 0x00ce, 0x0804, 0x2e97, 0x00ce, 0x0804, 0x2e9a,
+	0x080c, 0x82eb, 0x0cb0, 0x6830, 0xa086, 0x0100, 0x0904, 0x2e97,
+	0x0804, 0x2e72, 0x2061, 0xb464, 0x0126, 0x2091, 0x8000, 0x6000,
+	0xd084, 0x0140, 0x6104, 0x6208, 0x2019, 0xb111, 0x231c, 0x012e,
+	0x0804, 0x2e72, 0x012e, 0x0804, 0x2e9a, 0x81ff, 0x1904, 0x2e97,
+	0x080c, 0x58d5, 0x0904, 0x2e97, 0x0126, 0x2091, 0x8000, 0x6244,
+	0x6064, 0xa202, 0x0248, 0xa085, 0x0001, 0x080c, 0x2740, 0x080c,
+	0x44a2, 0x012e, 0x0804, 0x2e72, 0x012e, 0x0804, 0x2e9a, 0x0126,
+	0x2091, 0x8000, 0x7824, 0xa084, 0x0007, 0x0002, 0x3279, 0x3282,
+	0x3289, 0x3276, 0x3276, 0x3276, 0x3276, 0x3276, 0x012e, 0x0804,
+	0x2e9a, 0x2009, 0x0114, 0x2104, 0xa085, 0x0800, 0x200a, 0x080c,
+	0x33f2, 0x0070, 0x2009, 0x010b, 0x200b, 0x0010, 0x080c, 0x33f2,
+	0x0038, 0x81ff, 0x0128, 0x012e, 0x2021, 0x400b, 0x0804, 0x2e74,
+	0x0086, 0x0096, 0x00a6, 0x00b6, 0x00c6, 0x00d6, 0x00e6, 0x00f6,
+	0x2009, 0x0101, 0x210c, 0x0016, 0x2001, 0x0138, 0x200c, 0x2003,
+	0x0001, 0x0016, 0x2001, 0x007a, 0x2034, 0x2001, 0x007b, 0x202c,
+	0xa006, 0x2048, 0x2050, 0x2058, 0x080c, 0x3633, 0x080c, 0x359d,
+	0xa03e, 0x2720, 0x00f6, 0x00e6, 0x00c6, 0x2d60, 0x2071, 0xb43a,
+	0x2079, 0x0020, 0x00d6, 0x2069, 0x0000, 0x6824, 0xd0b4, 0x0140,
+	0x2001, 0x007d, 0x2004, 0x783e, 0x2001, 0x007c, 0x2004, 0x783a,
+	0x00de, 0x2011, 0x0001, 0x080c, 0x3549, 0x080c, 0x3549, 0x00ce,
+	0x00ee, 0x00fe, 0x080c, 0x3498, 0x080c, 0x3571, 0x080c, 0x34ee,
+	0x080c, 0x3457, 0x080c, 0x3488, 0x00f6, 0x2079, 0x0100, 0x7824,
+	0xd094, 0x0530, 0x7814, 0xa084, 0x0184, 0xa085, 0x0010, 0x7816,
+	0x2079, 0x0140, 0x080c, 0x33d0, 0x1110, 0x00fe, 0x0430, 0x7804,
+	0xd0dc, 0x0dc0, 0x2079, 0x0100, 0x7827, 0x0086, 0x7814, 0xa084,
+	0x0184, 0xa085, 0x0032, 0x7816, 0x080c, 0x33d0, 0x1110, 0x00fe,
+	0x00a0, 0x7824, 0xd0bc, 0x0dc0, 0x7827, 0x0080, 0xa026, 0x7c16,
+	0x7824, 0xd0ac, 0x0130, 0x8b58, 0x080c, 0x33da, 0x00fe, 0x0804,
+	0x339a, 0x00fe, 0x080c, 0x33d0, 0x1150, 0x8948, 0x2001, 0x007a,
+	0x2602, 0x2001, 0x007b, 0x2502, 0x080c, 0x33da, 0x0088, 0x87ff,
+	0x0140, 0x2001, 0x0201, 0x2004, 0xa005, 0x1904, 0x32d4, 0x8739,
+	0x0038, 0x2001, 0xb419, 0x2004, 0xa086, 0x0000, 0x1904, 0x32d4,
+	0x2001, 0x0033, 0x2003, 0x00f6, 0x8631, 0x1208, 0x8529, 0x2500,
+	0xa605, 0x0904, 0x339a, 0x7824, 0xd0bc, 0x0128, 0x2900, 0xaa05,
+	0xab05, 0x1904, 0x339a, 0x6033, 0x000d, 0x2001, 0x0030, 0x2003,
+	0x0004, 0x7824, 0xd0ac, 0x1148, 0x2001, 0xb419, 0x2003, 0x0003,
+	0x2001, 0x0030, 0x2003, 0x0009, 0x0040, 0x6027, 0x0001, 0x2001,
+	0x0075, 0x2004, 0xa005, 0x0108, 0x6026, 0x2c00, 0x601a, 0x20e1,
+	0x9040, 0x2d00, 0x681a, 0x6833, 0x000d, 0x7824, 0xd0a4, 0x1180,
+	0x6827, 0x0000, 0x00c6, 0x20a9, 0x0004, 0x2061, 0x0020, 0x6003,
+	0x0008, 0x2001, 0x0203, 0x2004, 0x1f04, 0x336f, 0x00ce, 0x0040,
+	0x6827, 0x0001, 0x2001, 0x0074, 0x2004, 0xa005, 0x0108, 0x6826,
+	0x00f6, 0x00c6, 0x2079, 0x0100, 0x2061, 0x0020, 0x7827, 0x0002,
+	0x2001, 0x0072, 0x2004, 0xa084, 0xfff8, 0x601a, 0x0006, 0x2001,
+	0x0073, 0x2004, 0x601e, 0x78c6, 0x000e, 0x78ca, 0x00ce, 0x00fe,
+	0x0804, 0x32b2, 0x2061, 0x0100, 0x6027, 0x0002, 0x001e, 0x61e2,
+	0x001e, 0x6106, 0x7824, 0xa084, 0x0003, 0xa086, 0x0002, 0x0188,
+	0x20e1, 0x9028, 0x6050, 0xa084, 0xf7ef, 0x6052, 0x602f, 0x0000,
+	0x602c, 0xc0ac, 0x602e, 0x604b, 0xf7f7, 0x6043, 0x0090, 0x6043,
+	0x0010, 0x2908, 0x2a10, 0x2b18, 0x2b00, 0xaa05, 0xa905, 0x00fe,
+	0x00ee, 0x00de, 0x00ce, 0x00be, 0x00ae, 0x009e, 0x008e, 0x1118,
+	0x012e, 0x0804, 0x2e72, 0x012e, 0x2021, 0x400c, 0x0804, 0x2e74,
+	0xa085, 0x0001, 0x1d04, 0x33d9, 0x2091, 0x6000, 0x8420, 0xa486,
+	0x0064, 0x0005, 0x2001, 0x0105, 0x2003, 0x0010, 0x2001, 0x0030,
+	0x2003, 0x0004, 0x2001, 0x0020, 0x2003, 0x0004, 0x2001, 0xb419,
+	0x2003, 0x0000, 0x2001, 0xb43a, 0x2003, 0x0000, 0x20e1, 0xf000,
+	0xa026, 0x0005, 0x00f6, 0x2079, 0x0100, 0x2001, 0xb114, 0x200c,
+	0x7932, 0x7936, 0x080c, 0x2720, 0x7850, 0xa084, 0x0980, 0xa085,
+	0x0030, 0x7852, 0x2019, 0x01f4, 0x8319, 0x1df0, 0xa084, 0x0980,
+	0x7852, 0x782c, 0xc0ad, 0x782e, 0x20a9, 0x0046, 0x1d04, 0x340e,
+	0x2091, 0x6000, 0x1f04, 0x340e, 0x7850, 0xa085, 0x0400, 0x7852,
+	0x2001, 0x0009, 0x2004, 0xa084, 0x0003, 0xa086, 0x0001, 0x1118,
+	0x782c, 0xc0ac, 0x782e, 0x784b, 0xf7f7, 0x7843, 0x0090, 0x7843,
+	0x0010, 0x20a9, 0x000e, 0xe000, 0x1f04, 0x342b, 0x7850, 0xa085,
+	0x1400, 0x7852, 0x2019, 0x61a8, 0x7854, 0xe000, 0xe000, 0xd08c,
+	0x1110, 0x8319, 0x1dc8, 0x7827, 0x0048, 0x7850, 0xa085, 0x0400,
+	0x7852, 0x7843, 0x0040, 0x2019, 0x01f4, 0xe000, 0xe000, 0x8319,
+	0x1de0, 0x2001, 0x0140, 0x2003, 0x0100, 0x7827, 0x0020, 0x7843,
+	0x0000, 0x2003, 0x0000, 0x7827, 0x0048, 0x00fe, 0x0005, 0x7824,
+	0xd0ac, 0x11c8, 0x00f6, 0x00e6, 0x2071, 0xb419, 0x2079, 0x0030,
+	0x2001, 0x0201, 0x2004, 0xa005, 0x0160, 0x7000, 0xa086, 0x0000,
+	0x1140, 0x0051, 0xd0bc, 0x0108, 0x8738, 0x7003, 0x0003, 0x7803,
+	0x0019, 0x00ee, 0x00fe, 0x0005, 0x780c, 0xa08c, 0x0070, 0x0178,
+	0x2009, 0x007a, 0x260a, 0x2009, 0x007b, 0x250a, 0xd0b4, 0x0108,
+	0x8a50, 0xd0ac, 0x0108, 0x8948, 0xd0a4, 0x0108, 0x8b58, 0x0005,
+	0x00f6, 0x2079, 0x0200, 0x781c, 0xd084, 0x0140, 0x20e1, 0x0007,
+	0x20e1, 0x2000, 0x2001, 0x020a, 0x2004, 0x0ca8, 0x00fe, 0x0005,
+	0x00e6, 0x2071, 0x0100, 0x2009, 0xb114, 0x210c, 0x716e, 0x7063,
+	0x0100, 0x7166, 0x719e, 0x706b, 0x0000, 0x7073, 0x0809, 0x7077,
+	0x0008, 0x7078, 0xa080, 0x0100, 0x707a, 0x7080, 0x8000, 0x7082,
+	0x7087, 0xaaaa, 0xa006, 0x708a, 0x708e, 0x707e, 0x70d6, 0x70ab,
+	0x0036, 0x70af, 0x95d5, 0x7027, 0x0080, 0x7014, 0xa084, 0x0184,
+	0xa085, 0x0032, 0x7016, 0x080c, 0x3571, 0x080c, 0x33d0, 0x1110,
+	0x8421, 0x0028, 0x7024, 0xd0bc, 0x0db0, 0x7027, 0x0080, 0x00f6,
+	0x00e6, 0x2071, 0xb419, 0x2079, 0x0030, 0x00d6, 0x2069, 0x0000,
+	0x6824, 0xd0b4, 0x0120, 0x683c, 0x783e, 0x6838, 0x783a, 0x00de,
+	0x2011, 0x0011, 0x080c, 0x3549, 0x2011, 0x0001, 0x080c, 0x3549,
+	0x00ee, 0x00fe, 0x7017, 0x0000, 0x00ee, 0x0005, 0x00f6, 0x00e6,
+	0x2071, 0xb419, 0x2079, 0x0030, 0x7904, 0xd1fc, 0x0904, 0x3546,
+	0x7803, 0x0002, 0xa026, 0xd19c, 0x1904, 0x3542, 0x7000, 0x0002,
+	0x3546, 0x3504, 0x3528, 0x3542, 0xd1bc, 0x1150, 0xd1dc, 0x1150,
+	0x8001, 0x7002, 0x2011, 0x0001, 0x04e1, 0x05c0, 0x04d1, 0x04b0,
+	0x780f, 0x0000, 0x7820, 0x7924, 0x7803, 0x0004, 0x7822, 0x7926,
+	0x2001, 0x0201, 0x200c, 0x81ff, 0x0de8, 0x080c, 0x3474, 0x2009,
+	0x0001, 0x7808, 0xd0ec, 0x0110, 0x2009, 0x0011, 0x7902, 0x00f0,
+	0x8001, 0x7002, 0xa184, 0x0880, 0x1138, 0x7804, 0xd0fc, 0x1940,
+	0x2011, 0x0001, 0x00b1, 0x0090, 0x6030, 0xa092, 0x0004, 0xa086,
+	0x0009, 0x1120, 0x6000, 0x601a, 0x2011, 0x0025, 0x6232, 0xd1dc,
+	0x1988, 0x0870, 0x7803, 0x0004, 0x7003, 0x0000, 0x00ee, 0x00fe,
+	0x0005, 0x6024, 0xa005, 0x0520, 0x8001, 0x6026, 0x6018, 0x6130,
+	0xa140, 0x2804, 0x7832, 0x8840, 0x2804, 0x7836, 0x8840, 0x2804,
+	0x7822, 0x8840, 0x2804, 0x7826, 0x8840, 0x7a02, 0x7000, 0x8000,
+	0x7002, 0x6018, 0xa802, 0xa08a, 0x0029, 0x1138, 0x6018, 0xa080,
+	0x0001, 0x2004, 0x601a, 0x2001, 0x000d, 0x6032, 0xa085, 0x0001,
+	0x0005, 0x00f6, 0x00e6, 0x00c6, 0x2071, 0xb43a, 0x2079, 0x0020,
+	0x7904, 0xd1fc, 0x01f0, 0x7803, 0x0002, 0x2d60, 0xa026, 0x7000,
+	0x0002, 0x3599, 0x3584, 0x3590, 0x8001, 0x7002, 0xd19c, 0x1188,
+	0x2011, 0x0001, 0x080c, 0x3549, 0x0160, 0x080c, 0x3549, 0x0048,
+	0x8001, 0x7002, 0x7804, 0xd0fc, 0x1d30, 0x2011, 0x0001, 0x080c,
+	0x3549, 0x00ce, 0x00ee, 0x00fe, 0x0005, 0x00f6, 0x00e6, 0x00c6,
+	0x2061, 0x0200, 0x601b, 0x0004, 0x2061, 0x0100, 0x60cf, 0x0400,
+	0x6004, 0xc0ac, 0xa085, 0x0200, 0x6006, 0x2001, 0x0074, 0x2004,
+	0xa005, 0x01f8, 0x2038, 0x2001, 0x0076, 0x2024, 0x2001, 0x0077,
+	0x201c, 0x080c, 0x3d04, 0x6833, 0x000d, 0x6f26, 0x2d00, 0x681a,
+	0xa78a, 0x0007, 0x0220, 0x2138, 0x2009, 0x0007, 0x0010, 0x2708,
+	0xa03e, 0x6818, 0xa080, 0x000d, 0x04a1, 0x1d90, 0x2d00, 0x681a,
+	0x0088, 0x080c, 0x3d04, 0x6833, 0x000d, 0x2070, 0x6827, 0x0001,
+	0x2d00, 0x681a, 0x2001, 0x0076, 0x2004, 0x2072, 0x2001, 0x0077,
+	0x2004, 0x7006, 0x2061, 0x0020, 0x2079, 0x0100, 0x6013, 0x0400,
+	0x20e1, 0x9040, 0x2001, 0x0072, 0x2004, 0xa084, 0xfff8, 0x700a,
+	0x601a, 0x0006, 0x2001, 0x0073, 0x2004, 0x700e, 0x601e, 0x78c6,
+	0x000e, 0x78ca, 0xa006, 0x603a, 0x603e, 0x00ce, 0x00ee, 0x00fe,
+	0x0005, 0x00e6, 0x2071, 0x0010, 0x20a0, 0x2099, 0x0014, 0x7003,
+	0x0026, 0x7432, 0x7336, 0xa006, 0x703a, 0x703e, 0x810b, 0x810b,
+	0x21a8, 0x810b, 0x7122, 0x7003, 0x0041, 0x7004, 0xd0fc, 0x0de8,
+	0x7003, 0x0002, 0x7003, 0x0040, 0x53a5, 0x7430, 0x7334, 0x87ff,
+	0x0180, 0x00c6, 0x00d6, 0x2d60, 0x00c6, 0x080c, 0x3d04, 0x00ce,
+	0x6018, 0x2070, 0x2d00, 0x7006, 0x601a, 0x00de, 0x00ce, 0xa085,
+	0x0001, 0x00ee, 0x0005, 0x00e6, 0x2001, 0x0075, 0x2004, 0xa005,
+	0x0508, 0x2038, 0x2001, 0x0078, 0x2024, 0x2001, 0x0079, 0x201c,
+	0x080c, 0x3d04, 0x2d60, 0x6833, 0x000d, 0x6f26, 0x2d00, 0x681a,
+	0xa78a, 0x0007, 0x0220, 0x2138, 0x2009, 0x0007, 0x0010, 0x2708,
+	0xa03e, 0x6818, 0xa080, 0x000d, 0x080c, 0x3601, 0x1d88, 0x2d00,
+	0x681a, 0x00e0, 0x080c, 0x3d04, 0x2d60, 0x6033, 0x000d, 0x2070,
+	0x6027, 0x0001, 0x2c00, 0x601a, 0x2001, 0x0078, 0x2004, 0x2072,
+	0x2001, 0x0079, 0x2004, 0x7006, 0x2001, 0x0072, 0x2004, 0xa084,
+	0xfff8, 0x700a, 0x2001, 0x0073, 0x2004, 0x700e, 0x2001, 0x0030,
+	0x2003, 0x0004, 0x7824, 0xd0ac, 0x1178, 0x2001, 0x0101, 0x200c,
+	0xc1ed, 0x2102, 0x6027, 0x0000, 0x2001, 0xb419, 0x2003, 0x0003,
+	0x2001, 0x0030, 0x2003, 0x0009, 0x00ee, 0x0005, 0x0804, 0x2e72,
+	0x0126, 0x2091, 0x8000, 0x20a9, 0x0012, 0x2001, 0xb140, 0x20a0,
+	0xa006, 0x40a4, 0x012e, 0x0804, 0x2e72, 0x7d38, 0x7c3c, 0x0804,
+	0x2f19, 0x080c, 0x3d04, 0x0904, 0x2e97, 0x080c, 0x58d5, 0x0110,
+	0x080c, 0x4a65, 0x2009, 0x001c, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38,
+	0x080c, 0x3d45, 0x701b, 0x36b5, 0x0005, 0xade8, 0x000d, 0x6800,
+	0xa005, 0x0904, 0x2e9a, 0x6804, 0xd0ac, 0x0118, 0xd0a4, 0x0904,
+	0x2e9a, 0xd094, 0x00c6, 0x2061, 0x0100, 0x6104, 0x0138, 0x6200,
+	0xa292, 0x0005, 0x0218, 0xa18c, 0xffdf, 0x0010, 0xa18d, 0x0020,
+	0x6106, 0x00ce, 0xd08c, 0x00c6, 0x2061, 0x0100, 0x6104, 0x0118,
+	0xa18d, 0x0010, 0x0010, 0xa18c, 0xffef, 0x6106, 0x00ce, 0x2009,
+	0x0100, 0x210c, 0xa18a, 0x0002, 0x0268, 0xd084, 0x0158, 0x6a28,
+	0xa28a, 0x007f, 0x1a04, 0x2e9a, 0xa288, 0x2c8c, 0x210d, 0xa18c,
+	0x00ff, 0x6156, 0xd0dc, 0x0130, 0x6828, 0xa08a, 0x007f, 0x1a04,
+	0x2e9a, 0x604e, 0x6808, 0xa08a, 0x0100, 0x0a04, 0x2e9a, 0xa08a,
+	0x0841, 0x1a04, 0x2e9a, 0xa084, 0x0007, 0x1904, 0x2e9a, 0x680c,
+	0xa005, 0x0904, 0x2e9a, 0x6810, 0xa005, 0x0904, 0x2e9a, 0x6848,
+	0x6940, 0xa10a, 0x1a04, 0x2e9a, 0x8001, 0x0904, 0x2e9a, 0x684c,
+	0x6944, 0xa10a, 0x1a04, 0x2e9a, 0x8001, 0x0904, 0x2e9a, 0x6804,
+	0xd0fc, 0x0560, 0x080c, 0x3d04, 0x0904, 0x2e97, 0x2009, 0x0014,
+	0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0xa290, 0x0038, 0xa399, 0x0000,
+	0x080c, 0x3d45, 0x701b, 0x3735, 0x0005, 0xade8, 0x000d, 0x20a9,
+	0x0014, 0x2d98, 0x2069, 0xb16e, 0x2da0, 0x53a3, 0x7010, 0xa0e8,
+	0x000d, 0x2001, 0xb172, 0x200c, 0xd1e4, 0x0140, 0x00c6, 0x2061,
+	0x0100, 0x6004, 0xa085, 0x0b00, 0x6006, 0x00ce, 0x2009, 0xb3b0,
+	0x200b, 0x0000, 0x2001, 0xb174, 0x2004, 0xd0ac, 0x0158, 0x7824,
+	0x200a, 0x2009, 0x017f, 0x200a, 0x3200, 0xa084, 0x003f, 0xa085,
+	0x3020, 0x2090, 0x20a9, 0x001c, 0x2d98, 0x2069, 0xb152, 0x2da0,
+	0x53a3, 0x6814, 0xa08c, 0x00ff, 0x613e, 0x8007, 0xa084, 0x00ff,
+	0x6042, 0x080c, 0x5ba6, 0x080c, 0x51d5, 0x080c, 0x523e, 0x6000,
+	0xa086, 0x0000, 0x1904, 0x382c, 0x6808, 0x602a, 0x080c, 0x2378,
+	0x0006, 0x2001, 0x0100, 0x2004, 0xa082, 0x0005, 0x000e, 0x0268,
+	0x2009, 0x0170, 0x200b, 0x0080, 0xe000, 0xe000, 0x200b, 0x0000,
+	0x0036, 0x6b08, 0x080c, 0x277b, 0x003e, 0x6818, 0x691c, 0x6a20,
+	0x6b24, 0x8007, 0x810f, 0x8217, 0x831f, 0x6016, 0x611a, 0x621e,
+	0x6322, 0x6c04, 0xd4f4, 0x0148, 0x6830, 0x6934, 0x6a38, 0x6b3c,
+	0x8007, 0x810f, 0x8217, 0x831f, 0x0010, 0xa084, 0xf0ff, 0x6006,
+	0x610a, 0x620e, 0x6312, 0x8007, 0x810f, 0x8217, 0x831f, 0x20a9,
+	0x0004, 0x20a1, 0xb3bf, 0x40a1, 0x080c, 0x67ea, 0x6904, 0xd1fc,
+	0x0520, 0x00c6, 0x2009, 0x0000, 0x20a9, 0x0001, 0x6b70, 0xd384,
+	0x01c8, 0x0020, 0x839d, 0x12b0, 0x3508, 0x8109, 0x080c, 0x6135,
+	0x6878, 0x6016, 0x6874, 0x2008, 0xa084, 0xff00, 0x8007, 0x600a,
+	0xa184, 0x00ff, 0x6006, 0x8108, 0x1118, 0x6003, 0x0003, 0x0010,
+	0x6003, 0x0001, 0x1f04, 0x37ca, 0x00ce, 0x2069, 0xb152, 0x2001,
+	0xb39e, 0x6a80, 0xa294, 0x0030, 0xa28e, 0x0000, 0x0170, 0xa28e,
+	0x0010, 0x0118, 0xa28e, 0x0020, 0x0140, 0x2003, 0xaaaa, 0x080c,
+	0x27c4, 0x2001, 0xb38f, 0x2102, 0x0008, 0x2102, 0x00c6, 0x2061,
+	0x0100, 0x602f, 0x0040, 0x602f, 0x0000, 0x00ce, 0x080c, 0x58d5,
+	0x0128, 0x080c, 0x3f5e, 0x0110, 0x080c, 0x2740, 0x60c4, 0xa005,
+	0x01b0, 0x6003, 0x0001, 0x2009, 0x3816, 0x00c0, 0x080c, 0x58d5,
+	0x1158, 0x2011, 0x57ea, 0x080c, 0x6742, 0x2001, 0xb39f, 0x2003,
+	0x0000, 0x080c, 0x5816, 0x0040, 0x080c, 0x4992, 0x0028, 0x6003,
+	0x0004, 0x2009, 0x382c, 0x0010, 0x0804, 0x2e72, 0x2001, 0x0100,
+	0x2004, 0xa082, 0x0005, 0x0258, 0x2001, 0x0170, 0x2004, 0xa084,
+	0x00ff, 0xa086, 0x004c, 0x1118, 0x2091, 0x309d, 0x0817, 0x2091,
+	0x301d, 0x0817, 0x6000, 0xa086, 0x0000, 0x0904, 0x2e97, 0x2069,
+	0xb152, 0x7830, 0x6842, 0x7834, 0x6846, 0x6804, 0xd0fc, 0x0118,
+	0x2009, 0x0030, 0x0010, 0x2009, 0x001c, 0x2d00, 0x7a2c, 0x7b28,
+	0x7c3c, 0x7d38, 0x0804, 0x3d48, 0xa006, 0x080c, 0x2740, 0x81ff,
+	0x1904, 0x2e97, 0x080c, 0x58d5, 0x1178, 0x2001, 0xb39f, 0x2003,
+	0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0xa085, 0x0001, 0x080c,
+	0x5919, 0x080c, 0x5816, 0x0020, 0x080c, 0x4a65, 0x080c, 0x4992,
+	0x0804, 0x2e72, 0x81ff, 0x1904, 0x2e97, 0x080c, 0x58d5, 0x1110,
+	0x0804, 0x2e97, 0x6184, 0x81ff, 0x0198, 0x703f, 0x0000, 0x2001,
+	0xb7c0, 0x2009, 0x0040, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x3d48, 0x701b, 0x2e70, 0x012e, 0x0005,
+	0x703f, 0x0001, 0x00d6, 0x2069, 0xb7c0, 0x20a9, 0x0040, 0x20a1,
+	0xb7c0, 0x2019, 0xffff, 0x43a4, 0x654c, 0xa588, 0x2c8c, 0x210d,
+	0xa18c, 0x00ff, 0x216a, 0xa00e, 0x2011, 0x0002, 0x2100, 0xa506,
+	0x01a8, 0x080c, 0x4e21, 0x1190, 0x6014, 0x821c, 0x0238, 0xa398,
+	0xb7c0, 0xa085, 0xff00, 0x8007, 0x201a, 0x0038, 0xa398, 0xb7c0,
+	0x2324, 0xa4a4, 0xff00, 0xa405, 0x201a, 0x8210, 0x8108, 0xa182,
+	0x0080, 0x1208, 0x0c18, 0x8201, 0x8007, 0x2d0c, 0xa105, 0x206a,
+	0x00de, 0x20a9, 0x0040, 0x20a1, 0xb7c0, 0x2099, 0xb7c0, 0x080c,
+	0x4a04, 0x0804, 0x3887, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x00c6,
+	0x080c, 0x3d04, 0x00ce, 0x1120, 0x2009, 0x0002, 0x0804, 0x2e97,
+	0x2001, 0xb153, 0x2004, 0xd0b4, 0x0550, 0x7824, 0xa084, 0xff00,
+	0xa08e, 0x7e00, 0x0520, 0xa08e, 0x7f00, 0x0508, 0xa08e, 0x8000,
+	0x01f0, 0x6000, 0xd08c, 0x11d8, 0x6004, 0xa084, 0x00ff, 0xa086,
+	0x0006, 0x11a8, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x080c,
+	0x99e8, 0x1120, 0x2009, 0x0003, 0x0804, 0x2e97, 0x7007, 0x0003,
+	0x701b, 0x3913, 0x0005, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x20a9,
+	0x002b, 0x2c98, 0xade8, 0x0002, 0x2da0, 0x53a3, 0x20a9, 0x0004,
+	0xac80, 0x0006, 0x2098, 0xad80, 0x0006, 0x20a0, 0x080c, 0x4a04,
+	0x20a9, 0x0004, 0xac80, 0x000a, 0x2098, 0xad80, 0x000a, 0x20a0,
+	0x080c, 0x4a04, 0x2d00, 0x2009, 0x002b, 0x7a2c, 0x7b28, 0x7c3c,
+	0x7d38, 0x0804, 0x3d48, 0x81ff, 0x1904, 0x2e97, 0x080c, 0x3d19,
+	0x0904, 0x2e9a, 0x080c, 0x4ff8, 0x0804, 0x2e72, 0x81ff, 0x1904,
+	0x2e97, 0x7828, 0xa08a, 0x1000, 0x1a04, 0x2e9a, 0x080c, 0x3d29,
+	0x0904, 0x2e9a, 0x080c, 0x505b, 0x0904, 0x2e97, 0x2019, 0x0004,
+	0xa00e, 0x080c, 0x500a, 0x7924, 0x810f, 0x7a28, 0x0011, 0x0804,
+	0x2e72, 0xa186, 0x00ff, 0x0110, 0x0071, 0x0060, 0x2029, 0x007e,
+	0x2061, 0xb100, 0x644c, 0x2400, 0xa506, 0x0110, 0x2508, 0x0019,
+	0x8529, 0x1ec8, 0x0005, 0x080c, 0x4e21, 0x1138, 0x2200, 0x8003,
+	0x800b, 0x810b, 0xa108, 0x080c, 0x674e, 0x0005, 0x81ff, 0x1904,
+	0x2e97, 0x080c, 0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4ee3, 0x0904,
+	0x2e97, 0x080c, 0x5001, 0x0804, 0x2e72, 0x81ff, 0x1904, 0x2e97,
+	0x080c, 0x3d19, 0x0904, 0x2e9a, 0x080c, 0x4ee3, 0x0904, 0x2e97,
+	0x080c, 0x4fef, 0x0804, 0x2e72, 0x6100, 0x0804, 0x2e72, 0x080c,
+	0x3d29, 0x0904, 0x2e9a, 0x2001, 0xb100, 0x2004, 0xa086, 0x0003,
+	0x1904, 0x2e97, 0x00d6, 0xace8, 0x000a, 0x7924, 0xd184, 0x0110,
+	0xace8, 0x0006, 0x680c, 0x8007, 0x783e, 0x6808, 0x8007, 0x783a,
+	0x6b04, 0x831f, 0x6a00, 0x8217, 0x00de, 0x6100, 0xa18c, 0x0200,
+	0x0804, 0x2e72, 0x7824, 0xa09c, 0x00ff, 0xa39a, 0x0003, 0x1a04,
+	0x2e97, 0x624c, 0xa294, 0x00ff, 0xa084, 0xff00, 0x8007, 0xa206,
+	0x1150, 0x2001, 0xb140, 0x2009, 0x000c, 0x7a2c, 0x7b28, 0x7c3c,
+	0x7d38, 0x0804, 0x3d48, 0x81ff, 0x1904, 0x2e97, 0x080c, 0x3d29,
+	0x0904, 0x2e9a, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1904,
+	0x2e97, 0x00c6, 0x080c, 0x3d04, 0x00ce, 0x0904, 0x2e97, 0x6837,
+	0x0000, 0x6838, 0xc0fd, 0x683a, 0x080c, 0x9994, 0x0904, 0x2e97,
+	0x7007, 0x0003, 0x701b, 0x39fd, 0x0005, 0x6830, 0xa086, 0x0100,
+	0x0904, 0x2e97, 0xad80, 0x000e, 0x2009, 0x000c, 0x7a2c, 0x7b28,
+	0x7c3c, 0x7d38, 0x0804, 0x3d48, 0xa006, 0x080c, 0x2740, 0x7824,
+	0xa084, 0x00ff, 0xa086, 0x00ff, 0x0118, 0x81ff, 0x1904, 0x2e97,
+	0x080c, 0x58d5, 0x0110, 0x080c, 0x4a65, 0x7828, 0xa08a, 0x1000,
+	0x1a04, 0x2e9a, 0x7924, 0xa18c, 0xff00, 0x810f, 0xa186, 0x00ff,
+	0x0138, 0xa182, 0x007f, 0x1a04, 0x2e9a, 0x2100, 0x080c, 0x270a,
+	0x0026, 0x00c6, 0x0126, 0x2091, 0x8000, 0x2061, 0xb3ec, 0x601b,
+	0x0000, 0x601f, 0x0000, 0x080c, 0x58d5, 0x1178, 0x2001, 0xb39f,
+	0x2003, 0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0xa085, 0x0001,
+	0x080c, 0x5919, 0x080c, 0x5816, 0x0430, 0x2011, 0x0003, 0x080c,
+	0x7d52, 0x2011, 0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41, 0x080c,
+	0x67b6, 0x0036, 0x2019, 0x0000, 0x080c, 0x7cc4, 0x003e, 0x2061,
+	0x0100, 0x2001, 0xb114, 0x2004, 0xa084, 0x00ff, 0x810f, 0xa105,
+	0x604a, 0x6043, 0x0090, 0x6043, 0x0010, 0x2009, 0x002d, 0x2011,
+	0x49c9, 0x080c, 0x67c8, 0x7924, 0xa18c, 0xff00, 0x810f, 0x080c,
+	0x58d5, 0x1110, 0x2009, 0x00ff, 0x7a28, 0x080c, 0x3961, 0x012e,
+	0x00ce, 0x002e, 0x0804, 0x2e72, 0x7924, 0xa18c, 0xff00, 0x810f,
+	0x00c6, 0x080c, 0x4dc5, 0x2c08, 0x00ce, 0x1904, 0x2e9a, 0x0804,
+	0x2e72, 0x81ff, 0x0120, 0x2009, 0x0001, 0x0804, 0x2e97, 0x60d0,
+	0xd0ac, 0x1130, 0xd09c, 0x1120, 0x2009, 0x0005, 0x0804, 0x2e97,
+	0x080c, 0x3d04, 0x1120, 0x2009, 0x0002, 0x0804, 0x2e97, 0x7924,
+	0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x080c, 0x3d45, 0x701b, 0x3ab1,
+	0x0005, 0x2009, 0x0080, 0x080c, 0x4e21, 0x1130, 0x6004, 0xa084,
+	0x00ff, 0xa086, 0x0006, 0x0120, 0x2021, 0x400a, 0x0804, 0x2e74,
+	0x00d6, 0xade8, 0x000d, 0x6900, 0x6a08, 0x6b0c, 0x6c10, 0x6d14,
+	0x6e18, 0x6820, 0xa0be, 0x0100, 0x0904, 0x3b28, 0xa0be, 0x0112,
+	0x0904, 0x3b28, 0xa0be, 0x0113, 0x0904, 0x3b28, 0xa0be, 0x0114,
+	0x0904, 0x3b28, 0xa0be, 0x0117, 0x0904, 0x3b28, 0xa0be, 0x011a,
+	0x0904, 0x3b28, 0xa0be, 0x011c, 0x0904, 0x3b28, 0xa0be, 0x0121,
+	0x05b0, 0xa0be, 0x0131, 0x0598, 0xa0be, 0x0171, 0x05c8, 0xa0be,
+	0x0173, 0x05b0, 0xa0be, 0x01a1, 0x1120, 0x6830, 0x8007, 0x6832,
+	0x04a8, 0xa0be, 0x0212, 0x0540, 0xa0be, 0x0213, 0x0528, 0xa0be,
+	0x0214, 0x01b0, 0xa0be, 0x0217, 0x0168, 0xa0be, 0x021a, 0x1120,
+	0x6838, 0x8007, 0x683a, 0x00e0, 0xa0be, 0x0300, 0x01c8, 0x00de,
+	0x0804, 0x2e9a, 0xad80, 0x0010, 0x20a9, 0x0007, 0x080c, 0x3b6e,
+	0xad80, 0x000e, 0x20a9, 0x0001, 0x080c, 0x3b6e, 0x0048, 0xad80,
+	0x000c, 0x080c, 0x3b7c, 0x0050, 0xad80, 0x000e, 0x080c, 0x3b7c,
+	0xad80, 0x000c, 0x20a9, 0x0001, 0x080c, 0x3b6e, 0x00c6, 0x080c,
+	0x3d04, 0x0568, 0x6838, 0xc0fd, 0x683a, 0x6837, 0x0119, 0x6853,
+	0x0000, 0x684f, 0x0020, 0x685b, 0x0001, 0x810b, 0x697e, 0x6883,
+	0x0000, 0x6a86, 0x6b8a, 0x6c8e, 0x6d92, 0x6996, 0x689b, 0x0000,
+	0x00ce, 0x00de, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x6823,
+	0x0000, 0x6804, 0x2068, 0x080c, 0x99b0, 0x1120, 0x2009, 0x0003,
+	0x0804, 0x2e97, 0x7007, 0x0003, 0x701b, 0x3b65, 0x0005, 0x00ce,
+	0x00de, 0x2009, 0x0002, 0x0804, 0x2e97, 0x6820, 0xa086, 0x8001,
+	0x1904, 0x2e72, 0x2009, 0x0004, 0x0804, 0x2e97, 0x0016, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x290a, 0x8108, 0x280a, 0x8108,
+	0x1f04, 0x3b70, 0x001e, 0x0005, 0x0016, 0x00a6, 0x00b6, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x2054, 0x8000, 0x205c, 0x2b0a,
+	0x8108, 0x2a0a, 0x8108, 0x290a, 0x8108, 0x280a, 0x00be, 0x00ae,
+	0x001e, 0x0005, 0x81ff, 0x0120, 0x2009, 0x0001, 0x0804, 0x2e97,
+	0x7924, 0x2140, 0xa18c, 0xff00, 0x810f, 0x60d0, 0xd0ac, 0x1120,
+	0xa182, 0x0080, 0x0a04, 0x2e9a, 0xa182, 0x00ff, 0x1a04, 0x2e9a,
+	0x7a2c, 0x7b28, 0x606c, 0xa306, 0x1140, 0x6070, 0xa24e, 0x0904,
+	0x2e9a, 0xa9cc, 0xff00, 0x0904, 0x2e9a, 0x00c6, 0x080c, 0x3c52,
+	0x2c68, 0x00ce, 0x0538, 0xa0c6, 0x4000, 0x1180, 0x00c6, 0x0006,
+	0x2d60, 0x2009, 0x0000, 0x080c, 0x50bc, 0x1108, 0xc185, 0x6000,
+	0xd0bc, 0x0108, 0xc18d, 0x000e, 0x00ce, 0x0088, 0xa0c6, 0x4007,
+	0x1110, 0x2408, 0x0060, 0xa0c6, 0x4008, 0x1118, 0x2708, 0x2610,
+	0x0030, 0xa0c6, 0x4009, 0x1108, 0x0010, 0x2001, 0x4006, 0x2020,
+	0x0804, 0x2e74, 0x2d00, 0x7022, 0x0016, 0x00b6, 0x00c6, 0x00e6,
+	0x2c70, 0x080c, 0x8295, 0x05d8, 0x2d00, 0x601a, 0x080c, 0x9c35,
+	0x2e58, 0x00ee, 0x00e6, 0x00c6, 0x080c, 0x3d04, 0x00ce, 0x2b70,
+	0x1150, 0x080c, 0x82eb, 0x00ee, 0x00ce, 0x00be, 0x001e, 0x2009,
+	0x0002, 0x0804, 0x2e97, 0x6837, 0x0000, 0x683b, 0x0000, 0x2d00,
+	0x6012, 0x6833, 0x0000, 0x6838, 0xc0fd, 0xd88c, 0x0108, 0xc0f5,
+	0x683a, 0x0126, 0x2091, 0x8000, 0x080c, 0x2b73, 0x012e, 0x601f,
+	0x0001, 0x2001, 0x0000, 0x080c, 0x4d63, 0x2001, 0x0002, 0x080c,
+	0x4d75, 0x2009, 0x0002, 0x080c, 0x831a, 0xa085, 0x0001, 0x00ee,
+	0x00ce, 0x00be, 0x001e, 0x1120, 0x2009, 0x0003, 0x0804, 0x2e97,
+	0x7007, 0x0003, 0x701b, 0x3c35, 0x0005, 0x6830, 0xa086, 0x0100,
+	0x7020, 0x2060, 0x1138, 0x2009, 0x0004, 0x6204, 0xa294, 0x00ff,
+	0x0804, 0x2e97, 0x2009, 0x0000, 0x6838, 0xd0f4, 0x1904, 0x2e72,
+	0x080c, 0x50bc, 0x1108, 0xc185, 0x6000, 0xd0bc, 0x0108, 0xc18d,
+	0x0804, 0x2e72, 0x00e6, 0x00d6, 0x2029, 0x0000, 0x2001, 0xb134,
+	0x2004, 0xd0ac, 0x0138, 0x2021, 0x0000, 0x20a9, 0x00ff, 0x2071,
+	0xb235, 0x0030, 0x2021, 0x0080, 0x20a9, 0x007f, 0x2071, 0xb2b5,
+	0x2e04, 0xa005, 0x1130, 0x2100, 0xa406, 0x1570, 0x2428, 0xc5fd,
+	0x0458, 0x2068, 0x6f10, 0x2700, 0xa306, 0x11b0, 0x6e14, 0x2600,
+	0xa206, 0x1190, 0x2400, 0xa106, 0x1160, 0x2d60, 0xd884, 0x0568,
+	0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1538, 0x2001, 0x4000,
+	0x0428, 0x2001, 0x4007, 0x0410, 0x2400, 0xa106, 0x1168, 0x6e14,
+	0x87ff, 0x1138, 0x86ff, 0x09d0, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x19a8, 0x2001, 0x4008, 0x0090, 0x8420, 0x8e70, 0x1f04, 0x3c68,
+	0x85ff, 0x1130, 0x2001, 0x4009, 0x0048, 0x2001, 0x0001, 0x0030,
+	0x080c, 0x4dc5, 0x1dd0, 0x6312, 0x6216, 0xa006, 0xa005, 0x00de,
+	0x00ee, 0x0005, 0x81ff, 0x1904, 0x2e97, 0x080c, 0x3d04, 0x0904,
+	0x2e97, 0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x7824, 0xa005,
+	0x0904, 0x2e9a, 0xa096, 0x00ff, 0x0120, 0xa092, 0x0004, 0x1a04,
+	0x2e9a, 0x2010, 0x2d18, 0x080c, 0x2b26, 0x0904, 0x2e97, 0x7007,
+	0x0003, 0x701b, 0x3cd4, 0x0005, 0x6830, 0xa086, 0x0100, 0x0904,
+	0x2e97, 0x0804, 0x2e72, 0x7924, 0xa18c, 0xff00, 0x810f, 0x60d0,
+	0xd0ac, 0x1120, 0xa182, 0x0080, 0x0a04, 0x2e9a, 0xa182, 0x00ff,
+	0x1a04, 0x2e9a, 0x0126, 0x2091, 0x8000, 0x080c, 0x989a, 0x1188,
+	0xa190, 0xb235, 0x2204, 0xa065, 0x0160, 0x080c, 0x4a80, 0x2001,
+	0xb134, 0x2004, 0xd0ac, 0x0110, 0x6017, 0x0000, 0x012e, 0x0804,
+	0x2e72, 0x012e, 0x0804, 0x2e97, 0x080c, 0x15dd, 0x0188, 0xa006,
+	0x6802, 0x7010, 0xa005, 0x1120, 0x2d00, 0x7012, 0x7016, 0x0030,
+	0x7014, 0x6802, 0x2060, 0x2d00, 0x6006, 0x7016, 0xad80, 0x000d,
+	0x0005, 0x7924, 0x810f, 0xa18c, 0x00ff, 0x080c, 0x4e21, 0x1130,
+	0x7e28, 0xa684, 0x3fff, 0xa082, 0x4000, 0x0208, 0xa066, 0x8cff,
+	0x0005, 0x7e24, 0x860f, 0xa18c, 0x00ff, 0x080c, 0x4e21, 0x1128,
+	0xa6b4, 0x00ff, 0xa682, 0x4000, 0x0208, 0xa066, 0x8cff, 0x0005,
+	0x0016, 0x7110, 0x81ff, 0x0128, 0x2168, 0x6904, 0x080c, 0x15f4,
+	0x0cc8, 0x7112, 0x7116, 0x001e, 0x0005, 0x2031, 0x0001, 0x0010,
+	0x2031, 0x0000, 0x2061, 0xb1d2, 0x6606, 0x6112, 0x600e, 0x6226,
+	0x632a, 0x642e, 0x6532, 0x2c10, 0x080c, 0x1628, 0x7007, 0x0002,
+	0x701b, 0x2e72, 0x0005, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2079,
+	0x0000, 0x2001, 0xb190, 0x2004, 0xa005, 0x1168, 0x0e04, 0x3d73,
+	0x7818, 0xd084, 0x1140, 0x7a22, 0x7b26, 0x7c2a, 0x781b, 0x0001,
+	0x2091, 0x4080, 0x0408, 0x0016, 0x00c6, 0x00e6, 0x2071, 0xb182,
+	0x7138, 0xa182, 0x0010, 0x0218, 0x7030, 0x2060, 0x0078, 0x7030,
+	0xa0e0, 0x0004, 0xac82, 0xb1d2, 0x0210, 0x2061, 0xb192, 0x2c00,
+	0x7032, 0x81ff, 0x1108, 0x7036, 0x8108, 0x713a, 0x2262, 0x6306,
+	0x640a, 0x00ee, 0x00ce, 0x001e, 0x012e, 0x00fe, 0x0005, 0x00e6,
+	0x2071, 0xb182, 0x7038, 0xa005, 0x0570, 0x0126, 0x2091, 0x8000,
+	0x0e04, 0x3dca, 0x00f6, 0x2079, 0x0000, 0x7818, 0xd084, 0x1508,
+	0x00c6, 0x7034, 0x2060, 0x2c04, 0x7822, 0x6004, 0x7826, 0x6008,
+	0x782a, 0x781b, 0x0001, 0x2091, 0x4080, 0x7038, 0x8001, 0x703a,
+	0xa005, 0x1130, 0x7033, 0xb192, 0x7037, 0xb192, 0x00ce, 0x0048,
+	0xac80, 0x0004, 0xa0fa, 0xb1d2, 0x0210, 0x2001, 0xb192, 0x7036,
+	0x00ce, 0x00fe, 0x012e, 0x00ee, 0x0005, 0x0026, 0x2001, 0xb153,
+	0x2004, 0xd0c4, 0x0120, 0x2011, 0x8014, 0x080c, 0x3d5b, 0x002e,
+	0x0005, 0x81ff, 0x1904, 0x2e97, 0x0126, 0x2091, 0x8000, 0x6030,
+	0xc08d, 0xc085, 0xc0ac, 0x6032, 0x080c, 0x58d5, 0x1178, 0x2001,
+	0xb39f, 0x2003, 0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0xa085,
+	0x0001, 0x080c, 0x5919, 0x080c, 0x5816, 0x0010, 0x080c, 0x4992,
+	0x012e, 0x0804, 0x2e72, 0x7824, 0x2008, 0xa18c, 0xfffd, 0x1128,
+	0x61dc, 0xa10d, 0x61de, 0x0804, 0x2e72, 0x0804, 0x2e9a, 0x81ff,
+	0x1904, 0x2e97, 0x6000, 0xa086, 0x0003, 0x1904, 0x2e97, 0x2001,
+	0xb153, 0x2004, 0xd0ac, 0x1904, 0x2e97, 0x080c, 0x3d29, 0x0904,
+	0x2e9a, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1120, 0x7828,
+	0xa005, 0x0904, 0x2e72, 0x00c6, 0x080c, 0x3d04, 0x00ce, 0x0904,
+	0x2e97, 0x6837, 0x0000, 0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a,
+	0x080c, 0x9a79, 0x0904, 0x2e97, 0x7007, 0x0003, 0x701b, 0x3e39,
+	0x0005, 0x6830, 0xa086, 0x0100, 0x0904, 0x2e97, 0x0804, 0x2e72,
+	0x2001, 0xb100, 0x2004, 0xa086, 0x0003, 0x1904, 0x2e97, 0x7f24,
+	0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x080c, 0x3d04, 0x0904, 0x2e97,
+	0x2009, 0x0000, 0x2031, 0x0000, 0x7023, 0x0000, 0x702f, 0x0000,
+	0xad80, 0x0005, 0x7026, 0x20a0, 0x080c, 0x4e21, 0x1904, 0x3eb3,
+	0x6004, 0xa0c4, 0x00ff, 0xa8c6, 0x0006, 0x0130, 0xa0c4, 0xff00,
+	0xa8c6, 0x0600, 0x1904, 0x3eb3, 0x2001, 0xb153, 0x2004, 0xd0ac,
+	0x1128, 0x080c, 0x50bc, 0x1110, 0xd79c, 0x05e8, 0xd794, 0x1110,
+	0xd784, 0x0158, 0xac80, 0x0006, 0x2098, 0x3400, 0x20a9, 0x0004,
+	0x53a3, 0x080c, 0x3b7c, 0xd794, 0x0148, 0xac80, 0x000a, 0x2098,
+	0x3400, 0x20a9, 0x0004, 0x53a3, 0x080c, 0x3b7c, 0x21a2, 0xd794,
+	0x01d8, 0xac80, 0x0000, 0x2098, 0x94a0, 0x20a9, 0x0002, 0x53a3,
+	0xac80, 0x0003, 0x20a6, 0x94a0, 0xac80, 0x0004, 0x2098, 0x3400,
+	0x20a9, 0x0002, 0x53a3, 0x080c, 0x3b6e, 0xac80, 0x0026, 0x2098,
+	0x20a9, 0x0002, 0x53a3, 0x0008, 0x94a0, 0xd794, 0x0110, 0xa6b0,
+	0x000b, 0xa6b0, 0x0005, 0x8108, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x0118, 0xa186, 0x0100, 0x0040, 0xd78c, 0x0120, 0xa186, 0x0100,
+	0x0170, 0x0018, 0xa186, 0x007e, 0x0150, 0xd794, 0x0118, 0xa686,
+	0x0020, 0x0010, 0xa686, 0x0028, 0x0150, 0x0804, 0x3e5c, 0x86ff,
+	0x1120, 0x7120, 0x810b, 0x0804, 0x2e72, 0x702f, 0x0001, 0x711e,
+	0x7020, 0xa600, 0x7022, 0x772a, 0x2061, 0xb1d2, 0x6007, 0x0000,
+	0x6612, 0x7024, 0x600e, 0x6226, 0x632a, 0x642e, 0x6532, 0x2c10,
+	0x080c, 0x1628, 0x7007, 0x0002, 0x701b, 0x3eef, 0x0005, 0x702c,
+	0xa005, 0x1170, 0x711c, 0x7024, 0x20a0, 0x7728, 0x2031, 0x0000,
+	0x2061, 0xb1d2, 0x6224, 0x6328, 0x642c, 0x6530, 0x0804, 0x3e5c,
+	0x7120, 0x810b, 0x0804, 0x2e72, 0x2029, 0x007e, 0x7924, 0x7a28,
+	0x7b2c, 0x7c38, 0xa184, 0xff00, 0x8007, 0xa0e2, 0x0020, 0x0a04,
+	0x2e9a, 0xa502, 0x0a04, 0x2e9a, 0xa184, 0x00ff, 0xa0e2, 0x0020,
+	0x0a04, 0x2e9a, 0xa502, 0x0a04, 0x2e9a, 0xa284, 0xff00, 0x8007,
+	0xa0e2, 0x0020, 0x0a04, 0x2e9a, 0xa502, 0x0a04, 0x2e9a, 0xa284,
+	0x00ff, 0xa0e2, 0x0020, 0x0a04, 0x2e9a, 0xa502, 0x0a04, 0x2e9a,
+	0xa384, 0xff00, 0x8007, 0xa0e2, 0x0020, 0x0a04, 0x2e9a, 0xa502,
+	0x0a04, 0x2e9a, 0xa384, 0x00ff, 0xa0e2, 0x0020, 0x0a04, 0x2e9a,
+	0xa502, 0x0a04, 0x2e9a, 0xa484, 0xff00, 0x8007, 0xa0e2, 0x0020,
+	0x0a04, 0x2e9a, 0xa502, 0x0a04, 0x2e9a, 0xa484, 0x00ff, 0xa0e2,
+	0x0020, 0x0a04, 0x2e9a, 0xa502, 0x0a04, 0x2e9a, 0x2061, 0xb3b8,
+	0x6102, 0x6206, 0x630a, 0x640e, 0x0804, 0x2e72, 0x0006, 0x2001,
+	0xb153, 0x2004, 0xd0cc, 0x000e, 0x0005, 0x0006, 0x2001, 0xb172,
+	0x2004, 0xd0bc, 0x000e, 0x0005, 0x6164, 0x7a24, 0x6300, 0x82ff,
+	0x1118, 0x7926, 0x0804, 0x2e72, 0x83ff, 0x1904, 0x2e9a, 0x2001,
+	0xfff0, 0xa200, 0x1a04, 0x2e9a, 0x2019, 0xffff, 0x6068, 0xa302,
+	0xa200, 0x0a04, 0x2e9a, 0x7926, 0x6266, 0x0804, 0x2e72, 0x2001,
+	0xb100, 0x2004, 0xa086, 0x0003, 0x1904, 0x2e97, 0x7c28, 0x7d24,
+	0x7e38, 0x7f2c, 0x080c, 0x3d04, 0x0904, 0x2e97, 0x2009, 0x0000,
+	0x2019, 0x0000, 0x7023, 0x0000, 0x702f, 0x0000, 0xad80, 0x0003,
+	0x7026, 0x20a0, 0xa1e0, 0xb235, 0x2c64, 0x8cff, 0x01b8, 0x6004,
+	0xa084, 0x00ff, 0xa086, 0x0006, 0x0130, 0x6004, 0xa084, 0xff00,
+	0xa086, 0x0600, 0x1158, 0x6014, 0x20a2, 0x94a0, 0x6010, 0x8007,
+	0xa105, 0x8007, 0x20a2, 0x94a0, 0xa398, 0x0002, 0x8108, 0xa182,
+	0x00ff, 0x0120, 0xa386, 0x002a, 0x0148, 0x08e0, 0x83ff, 0x1120,
+	0x7120, 0x810c, 0x0804, 0x2e72, 0x702f, 0x0001, 0x711e, 0x7020,
+	0xa300, 0x7022, 0x2061, 0xb1d2, 0x6007, 0x0000, 0x6312, 0x7024,
+	0x600e, 0x6426, 0x652a, 0x662e, 0x6732, 0x2c10, 0x080c, 0x1628,
+	0x7007, 0x0002, 0x701b, 0x3fe5, 0x0005, 0x702c, 0xa005, 0x1168,
+	0x711c, 0x7024, 0x20a0, 0x2019, 0x0000, 0x2061, 0xb1d2, 0x6424,
+	0x6528, 0x662c, 0x6730, 0x0804, 0x3fa2, 0x7120, 0x810c, 0x0804,
+	0x2e72, 0x81ff, 0x1904, 0x2e97, 0x60d0, 0xd0ac, 0x1118, 0xd09c,
+	0x0904, 0x2e97, 0x080c, 0x3d04, 0x0904, 0x2e97, 0x7924, 0x7a2c,
+	0x7b28, 0x7c3c, 0x7d38, 0x080c, 0x3d45, 0x701b, 0x4010, 0x0005,
+	0x00d6, 0xade8, 0x000d, 0x6828, 0xa0be, 0x7000, 0x0148, 0xa0be,
+	0x7100, 0x0130, 0xa0be, 0x7200, 0x0118, 0x00de, 0x0804, 0x2e9a,
+	0x6820, 0x6924, 0x080c, 0x26f6, 0x1510, 0x080c, 0x4dc5, 0x11f8,
+	0x7122, 0x6612, 0x6516, 0x6e18, 0x00c6, 0x080c, 0x3d04, 0x01b8,
+	0x080c, 0x3d04, 0x01a0, 0x00ce, 0x00de, 0x6837, 0x0000, 0x6838,
+	0xc0fd, 0x683a, 0x6823, 0x0000, 0x6804, 0x2068, 0x080c, 0x99cc,
+	0x0904, 0x2e97, 0x7007, 0x0003, 0x701b, 0x404a, 0x0005, 0x00de,
+	0x0804, 0x2e97, 0x7120, 0x080c, 0x2c6e, 0x6820, 0xa086, 0x8001,
+	0x0904, 0x2e97, 0x2d00, 0x701e, 0x6804, 0xa080, 0x0002, 0x0006,
+	0x20a9, 0x002a, 0x2098, 0x20a0, 0x080c, 0x4a04, 0x000e, 0xade8,
+	0x000d, 0x6a08, 0x6b0c, 0x6c10, 0x6d14, 0x2061, 0xb1d2, 0x6007,
+	0x0000, 0x6e00, 0x6f28, 0xa7c6, 0x7000, 0x1108, 0x0018, 0xa7c6,
+	0x7100, 0x1140, 0xa6c2, 0x0004, 0x0a04, 0x2e9a, 0x2009, 0x0004,
+	0x0804, 0x3d48, 0xa7c6, 0x7200, 0x1904, 0x2e9a, 0xa6c2, 0x0054,
+	0x0a04, 0x2e9a, 0x600e, 0x6013, 0x002a, 0x6226, 0x632a, 0x642e,
+	0x6532, 0x2c10, 0x080c, 0x1628, 0x7007, 0x0002, 0x701b, 0x4091,
+	0x0005, 0x701c, 0x2068, 0x6804, 0xa080, 0x0001, 0x2004, 0xa080,
+	0x0002, 0x0006, 0x20a9, 0x002a, 0x2098, 0x20a0, 0x080c, 0x4a04,
+	0x000e, 0x2009, 0x002a, 0x2061, 0xb1d2, 0x6224, 0x6328, 0x642c,
+	0x6530, 0x0804, 0x3d48, 0x81ff, 0x1904, 0x2e97, 0x080c, 0x3d19,
+	0x0904, 0x2e9a, 0x080c, 0x4ee3, 0x0904, 0x2e97, 0x080c, 0x5013,
+	0x0804, 0x2e72, 0x7824, 0xd084, 0x0904, 0x38db, 0x080c, 0x3d29,
+	0x0904, 0x2e9a, 0x00c6, 0x080c, 0x3d04, 0x00ce, 0x1120, 0x2009,
+	0x0002, 0x0804, 0x2e97, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006,
+	0x0128, 0xa08e, 0x0004, 0x0110, 0xa08e, 0x0005, 0x1580, 0x2001,
+	0xb153, 0x2004, 0xd0b4, 0x0904, 0x3917, 0x7824, 0xa084, 0xff00,
+	0xa08e, 0x7e00, 0x0904, 0x3917, 0xa08e, 0x7f00, 0x0904, 0x3917,
+	0xa08e, 0x8000, 0x0904, 0x3917, 0x6000, 0xd08c, 0x1904, 0x3917,
+	0x6837, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x080c, 0x99e8, 0x1120,
+	0x2009, 0x0003, 0x0804, 0x2e97, 0x7007, 0x0003, 0x701b, 0x4101,
+	0x0005, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x0804, 0x3917, 0x2009,
+	0xb130, 0x210c, 0x81ff, 0x0120, 0x2009, 0x0001, 0x0804, 0x2e97,
+	0x2001, 0xb100, 0x2004, 0xa086, 0x0003, 0x0120, 0x2009, 0x0007,
+	0x0804, 0x2e97, 0x2001, 0xb153, 0x2004, 0xd0ac, 0x0120, 0x2009,
+	0x0008, 0x0804, 0x2e97, 0x609c, 0xd0a4, 0x1118, 0xd0ac, 0x1904,
+	0x3917, 0x6837, 0x0000, 0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a,
+	0x080c, 0x9a79, 0x1120, 0x2009, 0x0003, 0x0804, 0x2e97, 0x7007,
+	0x0003, 0x701b, 0x413c, 0x0005, 0x6830, 0xa086, 0x0100, 0x1120,
+	0x2009, 0x0004, 0x0804, 0x2e97, 0x080c, 0x3d29, 0x0904, 0x2e9a,
+	0x0804, 0x40d7, 0x81ff, 0x2009, 0x0001, 0x1904, 0x2e97, 0x6000,
+	0xa086, 0x0003, 0x2009, 0x0007, 0x1904, 0x2e97, 0x2001, 0xb153,
+	0x2004, 0xd0ac, 0x2009, 0x0008, 0x1904, 0x2e97, 0x080c, 0x3d29,
+	0x0904, 0x2e9a, 0x6004, 0xa084, 0x00ff, 0xa086, 0x0006, 0x2009,
+	0x0009, 0x1904, 0x2e97, 0x00c6, 0x080c, 0x3d04, 0x00ce, 0x2009,
+	0x0002, 0x0904, 0x2e97, 0x6837, 0x0000, 0x6833, 0x0000, 0x6838,
+	0xc0fd, 0x683a, 0x7928, 0xa194, 0xff00, 0xa18c, 0x00ff, 0xa006,
+	0x82ff, 0x1128, 0xc0ed, 0x6952, 0x792c, 0x6956, 0x0048, 0xa28e,
+	0x0100, 0x1904, 0x2e9a, 0xc0e5, 0x6853, 0x0000, 0x6857, 0x0000,
+	0x683e, 0x080c, 0x9c36, 0x2009, 0x0003, 0x0904, 0x2e97, 0x7007,
+	0x0003, 0x701b, 0x419c, 0x0005, 0x6830, 0xa086, 0x0100, 0x2009,
+	0x0004, 0x0904, 0x2e97, 0x0804, 0x2e72, 0x81ff, 0x2009, 0x0001,
+	0x1904, 0x2e97, 0x6000, 0xa086, 0x0003, 0x2009, 0x0007, 0x1904,
+	0x2e97, 0x080c, 0x3d29, 0x0904, 0x2e9a, 0x6004, 0xa084, 0x00ff,
+	0xa086, 0x0006, 0x2009, 0x0009, 0x1904, 0x2e97, 0x00c6, 0x080c,
+	0x3d04, 0x00ce, 0x2009, 0x0002, 0x0904, 0x2e97, 0xad80, 0x000f,
+	0x2009, 0x0008, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x080c, 0x3d45,
+	0x701b, 0x41d3, 0x0005, 0x00d6, 0xade8, 0x000f, 0x6800, 0xa086,
+	0x0500, 0x1140, 0x6804, 0xa005, 0x1128, 0x6808, 0xa084, 0xff00,
+	0x1108, 0x0018, 0x00de, 0x1904, 0x2e9a, 0x00de, 0x6837, 0x0000,
+	0x6833, 0x0000, 0x6838, 0xc0fd, 0x683a, 0x00c6, 0x080c, 0x3d29,
+	0x1118, 0x00ce, 0x0804, 0x2e9a, 0x080c, 0x9c85, 0x2009, 0x0003,
+	0x00ce, 0x0904, 0x2e97, 0x7007, 0x0003, 0x701b, 0x4200, 0x0005,
+	0x6830, 0xa086, 0x0100, 0x2009, 0x0004, 0x0904, 0x2e97, 0x0804,
+	0x2e72, 0x81ff, 0x0120, 0x2009, 0x0001, 0x0804, 0x2e97, 0x6000,
+	0xa086, 0x0003, 0x0120, 0x2009, 0x0007, 0x0804, 0x2e97, 0x7e24,
+	0x860f, 0xa18c, 0x00ff, 0xa6b4, 0x00ff, 0x080c, 0x4e21, 0x1904,
+	0x2e9a, 0xa186, 0x007f, 0x0150, 0x6004, 0xa084, 0x00ff, 0xa086,
+	0x0006, 0x0120, 0x2009, 0x0009, 0x0804, 0x2e97, 0x00c6, 0x080c,
+	0x3d04, 0x00ce, 0x1120, 0x2009, 0x0002, 0x0804, 0x2e97, 0x6837,
+	0x0000, 0x6838, 0xc0fd, 0x683a, 0x080c, 0x9a03, 0x1120, 0x2009,
+	0x0003, 0x0804, 0x2e97, 0x7007, 0x0003, 0x701b, 0x4248, 0x0005,
+	0x6808, 0x8007, 0xa086, 0x0100, 0x1120, 0x2009, 0x0004, 0x0804,
+	0x2e97, 0x68b0, 0x6836, 0x6810, 0x8007, 0xa084, 0x00ff, 0x808e,
+	0x6814, 0x8007, 0xa084, 0x00ff, 0x8086, 0xa080, 0x0002, 0xa108,
+	0xad80, 0x0004, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x0804, 0x3d48,
+	0x080c, 0x3d04, 0x1120, 0x2009, 0x0002, 0x0804, 0x2e97, 0x7924,
+	0xa194, 0xff00, 0xa18c, 0x00ff, 0x8217, 0x82ff, 0x0110, 0x0804,
+	0x2e9a, 0x2009, 0x001a, 0x7a2c, 0x7b28, 0x7c3c, 0x7d38, 0x080c,
+	0x3d45, 0x701b, 0x4284, 0x0005, 0xad80, 0x000d, 0x2098, 0x20a9,
+	0x001a, 0x20a1, 0xb3bf, 0x53a3, 0x0804, 0x2e72, 0x080c, 0x3d04,
+	0x1120, 0x2009, 0x0002, 0x0804, 0x2e97, 0x7924, 0xa194, 0xff00,
+	0xa18c, 0x00ff, 0x8217, 0x82ff, 0x0110, 0x0804, 0x2e9a, 0x2099,
+	0xb3bf, 0x20a0, 0x20a9, 0x001a, 0x53a3, 0x2009, 0x001a, 0x7a2c,
+	0x7b28, 0x7c3c, 0x7d38, 0x0804, 0x3d48, 0x7824, 0xa08a, 0x1000,
+	0x1a04, 0x2e9a, 0x0126, 0x2091, 0x8000, 0x8003, 0x800b, 0x810b,
+	0xa108, 0x00c6, 0x2061, 0xb3ec, 0x6142, 0x00ce, 0x012e, 0x0804,
+	0x2e72, 0x00c6, 0x080c, 0x58d5, 0x1188, 0x2001, 0xb39f, 0x2003,
+	0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0xa085, 0x0001, 0x080c,
+	0x5919, 0x080c, 0x5816, 0x080c, 0x14fa, 0x0038, 0x2061, 0xb100,
+	0x6030, 0xc09d, 0x6032, 0x080c, 0x4992, 0x00ce, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x00c6, 0x2061, 0xb3ec, 0x7924, 0x6152, 0x614e,
+	0x6057, 0x0000, 0x604b, 0x0009, 0x7838, 0x606a, 0x783c, 0x6066,
+	0x7828, 0x6062, 0x782c, 0x605e, 0x2061, 0xb3a0, 0x2001, 0xb401,
+	0x600e, 0x6013, 0x0001, 0x6017, 0x0002, 0x6007, 0x0000, 0x6037,
+	0x0000, 0x00ce, 0x012e, 0x0804, 0x2e72, 0x0126, 0x00c6, 0x00e6,
+	0x2061, 0x0100, 0x2071, 0xb100, 0x6044, 0xd0a4, 0x11b0, 0xd084,
+	0x0118, 0x080c, 0x447c, 0x0068, 0xd08c, 0x0118, 0x080c, 0x439d,
+	0x0040, 0xd094, 0x0118, 0x080c, 0x436e, 0x0018, 0xd09c, 0x0108,
+	0x0061, 0x00ee, 0x00ce, 0x012e, 0x0005, 0x0016, 0x6128, 0xd19c,
+	0x1110, 0xc19d, 0x612a, 0x001e, 0x0ca0, 0x624c, 0xa286, 0xf0f0,
+	0x1150, 0x6048, 0xa086, 0xf0f0, 0x0130, 0x624a, 0x6043, 0x0090,
+	0x6043, 0x0010, 0x0490, 0xa294, 0xff00, 0xa296, 0xf700, 0x0178,
+	0x7134, 0xd1a4, 0x1160, 0x6240, 0xa295, 0x0100, 0x6242, 0xa294,
+	0x0010, 0x0128, 0x2009, 0x00f7, 0x080c, 0x4a24, 0x00f0, 0x6040,
+	0xa084, 0x0010, 0xa085, 0x0140, 0x6042, 0x6043, 0x0000, 0x7077,
+	0x0000, 0x7093, 0x0001, 0x70b7, 0x0000, 0x70d3, 0x0000, 0x2009,
+	0xb7c0, 0x200b, 0x0000, 0x7087, 0x0000, 0x707b, 0x000a, 0x2009,
+	0x000a, 0x2011, 0x4948, 0x080c, 0x67c8, 0x0005, 0x0156, 0x2001,
+	0xb174, 0x2004, 0xd08c, 0x0110, 0x704f, 0xffff, 0x7078, 0xa005,
+	0x1510, 0x2011, 0x4948, 0x080c, 0x6742, 0x6040, 0xa094, 0x0010,
+	0xa285, 0x0020, 0x6042, 0x20a9, 0x00c8, 0x6044, 0xd08c, 0x1168,
+	0x1f04, 0x4385, 0x6242, 0x708b, 0x0000, 0x6040, 0xa094, 0x0010,
+	0xa285, 0x0080, 0x6042, 0x6242, 0x0030, 0x6242, 0x708b, 0x0000,
+	0x707f, 0x0000, 0x0000, 0x015e, 0x0005, 0x707c, 0xa08a, 0x0003,
+	0x1210, 0x0023, 0x0010, 0x080c, 0x14fa, 0x0005, 0x43a9, 0x43f9,
+	0x447b, 0x00f6, 0x707f, 0x0001, 0x20e1, 0xa000, 0xe000, 0x20e1,
+	0x8700, 0x080c, 0x2378, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2079,
+	0xb600, 0x207b, 0x2200, 0x7807, 0x00ef, 0x780b, 0x0000, 0x780f,
+	0x00ef, 0x7813, 0x0138, 0x7817, 0x0000, 0x781b, 0x0000, 0x781f,
+	0x0000, 0x7823, 0xffff, 0x7827, 0xffff, 0x782b, 0x0000, 0x782f,
+	0x0000, 0x2079, 0xb60c, 0x207b, 0x1101, 0x7807, 0x0000, 0x2099,
+	0xb105, 0x20a1, 0xb60e, 0x20a9, 0x0004, 0x53a3, 0x2079, 0xb612,
+	0x207b, 0x0000, 0x7807, 0x0000, 0x2099, 0xb600, 0x20a1, 0x020b,
+	0x20a9, 0x0014, 0x53a6, 0x60c3, 0x000c, 0x600f, 0x0000, 0x080c,
+	0x4979, 0x00fe, 0x7083, 0x0000, 0x6043, 0x0008, 0x6043, 0x0000,
+	0x0005, 0x00d6, 0x7080, 0x7083, 0x0000, 0xa025, 0x0904, 0x4463,
+	0x6020, 0xd0b4, 0x1904, 0x4461, 0x7190, 0x81ff, 0x0904, 0x4451,
+	0xa486, 0x000c, 0x1904, 0x445c, 0xa480, 0x0018, 0x8004, 0x20a8,
+	0x2011, 0xb680, 0x2019, 0xb600, 0x220c, 0x2304, 0xa106, 0x11b8,
+	0x8210, 0x8318, 0x1f04, 0x4414, 0x6043, 0x0004, 0x608b, 0xbc94,
+	0x608f, 0xf0f0, 0x6043, 0x0006, 0x707f, 0x0002, 0x708b, 0x0002,
+	0x2009, 0x07d0, 0x2011, 0x494f, 0x080c, 0x67c8, 0x0490, 0x2069,
+	0xb680, 0x6930, 0xa18e, 0x1101, 0x1538, 0x6834, 0xa005, 0x1520,
+	0x6900, 0xa18c, 0x00ff, 0x1118, 0x6804, 0xa005, 0x0190, 0x2011,
+	0xb68e, 0x2019, 0xb105, 0x20a9, 0x0004, 0x220c, 0x2304, 0xa102,
+	0x0230, 0x1190, 0x8210, 0x8318, 0x1f04, 0x4445, 0x0068, 0x7093,
+	0x0000, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xb680, 0x20a1,
+	0x020b, 0x20a9, 0x0014, 0x53a6, 0x6043, 0x0008, 0x6043, 0x0000,
+	0x0010, 0x00de, 0x0005, 0x6040, 0xa085, 0x0100, 0x6042, 0x6020,
+	0xd0b4, 0x1db8, 0x60c3, 0x000c, 0x2011, 0xb3e3, 0x2013, 0x0000,
+	0x7083, 0x0000, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7, 0x9575,
+	0x080c, 0x7a83, 0x0c30, 0x0005, 0x7088, 0xa08a, 0x001d, 0x1210,
+	0x0023, 0x0010, 0x080c, 0x14fa, 0x0005, 0x44af, 0x44be, 0x44e6,
+	0x44ff, 0x4523, 0x454b, 0x456f, 0x45a0, 0x45c4, 0x45ec, 0x4623,
+	0x464b, 0x4667, 0x467d, 0x469d, 0x46b0, 0x46b8, 0x46e5, 0x4709,
+	0x4731, 0x4755, 0x4786, 0x47c3, 0x47f2, 0x480e, 0x484d, 0x486d,
+	0x4886, 0x4887, 0x00c6, 0x2061, 0xb100, 0x6003, 0x0007, 0x2061,
+	0x0100, 0x6004, 0xa084, 0xfff9, 0x6006, 0x00ce, 0x0005, 0x608b,
+	0xbc94, 0x608f, 0xf0f0, 0x6043, 0x0002, 0x708b, 0x0001, 0x2009,
+	0x07d0, 0x2011, 0x494f, 0x080c, 0x67c8, 0x0005, 0x00f6, 0x7080,
+	0xa086, 0x0014, 0x1508, 0x6043, 0x0000, 0x6020, 0xd0b4, 0x11e0,
+	0x2079, 0xb680, 0x7a30, 0xa296, 0x1102, 0x11a0, 0x7834, 0xa005,
+	0x1188, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110, 0x70b7,
+	0x0001, 0x2011, 0x494f, 0x080c, 0x6742, 0x708b, 0x0010, 0x080c,
+	0x46b8, 0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x0003,
+	0x6043, 0x0004, 0x2011, 0x494f, 0x080c, 0x6742, 0x080c, 0x4a0c,
+	0x20a3, 0x1102, 0x20a3, 0x0000, 0x20a9, 0x000a, 0x20a3, 0x0000,
+	0x1f04, 0x44f6, 0x60c3, 0x0014, 0x080c, 0x4979, 0x0005, 0x00f6,
+	0x7080, 0xa005, 0x01f0, 0x2011, 0x494f, 0x080c, 0x6742, 0xa086,
+	0x0014, 0x11a8, 0x2079, 0xb680, 0x7a30, 0xa296, 0x1102, 0x1178,
+	0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0xa005,
+	0x1110, 0x70b7, 0x0001, 0x708b, 0x0004, 0x0029, 0x0010, 0x080c,
+	0x4992, 0x00fe, 0x0005, 0x708b, 0x0005, 0x080c, 0x4a0c, 0x20a3,
+	0x1103, 0x20a3, 0x0000, 0x3430, 0x2011, 0xb68e, 0x080c, 0x4a5d,
+	0x1160, 0x7074, 0xa005, 0x1148, 0x714c, 0xa186, 0xffff, 0x0128,
+	0x080c, 0x4913, 0x0110, 0x080c, 0x4a3b, 0x20a9, 0x0008, 0x2298,
+	0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014,
+	0x080c, 0x4979, 0x0005, 0x00f6, 0x7080, 0xa005, 0x01f0, 0x2011,
+	0x494f, 0x080c, 0x6742, 0xa086, 0x0014, 0x11a8, 0x2079, 0xb680,
+	0x7a30, 0xa296, 0x1103, 0x1178, 0x7834, 0xa005, 0x1160, 0x7a38,
+	0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110, 0x70b7, 0x0001, 0x708b,
+	0x0006, 0x0029, 0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b,
+	0x0007, 0x080c, 0x4a0c, 0x20a3, 0x1104, 0x20a3, 0x0000, 0x3430,
+	0x2011, 0xb68e, 0x080c, 0x4a5d, 0x11a8, 0x7074, 0xa005, 0x1190,
+	0x7154, 0xa186, 0xffff, 0x0170, 0xa180, 0x2c8c, 0x200d, 0xa18c,
+	0xff00, 0x810f, 0x080c, 0x4913, 0x0128, 0x080c, 0x3f65, 0x0110,
+	0x080c, 0x2740, 0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, 0x4979, 0x0005,
+	0x00f6, 0x7080, 0xa005, 0x01f0, 0x2011, 0x494f, 0x080c, 0x6742,
+	0xa086, 0x0014, 0x11a8, 0x2079, 0xb680, 0x7a30, 0xa296, 0x1104,
+	0x1178, 0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4,
+	0xa005, 0x1110, 0x70b7, 0x0001, 0x708b, 0x0008, 0x0029, 0x0010,
+	0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x0009, 0x080c, 0x4a0c,
+	0x20a3, 0x1105, 0x20a3, 0x0100, 0x3430, 0x080c, 0x4a5d, 0x1150,
+	0x7074, 0xa005, 0x1138, 0x080c, 0x4888, 0x1170, 0xa085, 0x0001,
+	0x080c, 0x2740, 0x20a9, 0x0008, 0x2099, 0xb68e, 0x26a0, 0x53a6,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, 0x4979,
+	0x0010, 0x080c, 0x44a2, 0x0005, 0x00f6, 0x7080, 0xa005, 0x0588,
+	0x2011, 0x494f, 0x080c, 0x6742, 0xa086, 0x0014, 0x1540, 0x2079,
+	0xb680, 0x7a30, 0xa296, 0x1105, 0x1510, 0x7834, 0x2011, 0x0100,
+	0xa21e, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110,
+	0x70b7, 0x0001, 0x708b, 0x000a, 0x00b1, 0x0098, 0xa005, 0x1178,
+	0x7a38, 0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110, 0x70b7, 0x0001,
+	0x7087, 0x0000, 0x708b, 0x000e, 0x080c, 0x469d, 0x0010, 0x080c,
+	0x4992, 0x00fe, 0x0005, 0x708b, 0x000b, 0x2011, 0xb60e, 0x22a0,
+	0x20a9, 0x0040, 0x2019, 0xffff, 0x43a4, 0x20a9, 0x0002, 0x2009,
+	0x0000, 0x41a4, 0x080c, 0x4a0c, 0x20a3, 0x1106, 0x20a3, 0x0000,
+	0x080c, 0x4a5d, 0x0118, 0x2013, 0x0000, 0x0020, 0x7050, 0xa085,
+	0x0100, 0x2012, 0x2298, 0x20a9, 0x0042, 0x53a6, 0x60c3, 0x0084,
+	0x080c, 0x4979, 0x0005, 0x00f6, 0x7080, 0xa005, 0x01b0, 0x2011,
+	0x494f, 0x080c, 0x6742, 0xa086, 0x0084, 0x1168, 0x2079, 0xb680,
+	0x7a30, 0xa296, 0x1106, 0x1138, 0x7834, 0xa005, 0x1120, 0x708b,
+	0x000c, 0x0029, 0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b,
+	0x000d, 0x080c, 0x4a0c, 0x20a3, 0x1107, 0x20a3, 0x0000, 0x2099,
+	0xb68e, 0x20a9, 0x0040, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x60c3, 0x0084, 0x080c, 0x4979, 0x0005, 0x00f6, 0x7080, 0xa005,
+	0x01d0, 0x2011, 0x494f, 0x080c, 0x6742, 0xa086, 0x0084, 0x1188,
+	0x2079, 0xb680, 0x7a30, 0xa296, 0x1107, 0x1158, 0x7834, 0xa005,
+	0x1140, 0x7087, 0x0001, 0x080c, 0x49fe, 0x708b, 0x000e, 0x0029,
+	0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x000f, 0x7083,
+	0x0000, 0x608b, 0xbc85, 0x608f, 0xb5b5, 0x6043, 0x0005, 0x6043,
+	0x0004, 0x2009, 0x07d0, 0x2011, 0x494f, 0x080c, 0x6736, 0x0005,
+	0x7080, 0xa005, 0x0120, 0x2011, 0x494f, 0x080c, 0x6742, 0x0005,
+	0x708b, 0x0011, 0x080c, 0x4a5d, 0x1188, 0x716c, 0x81ff, 0x0170,
+	0x2009, 0x0000, 0x7070, 0xa084, 0x00ff, 0x080c, 0x26f6, 0xa186,
+	0x0080, 0x0120, 0x2011, 0xb68e, 0x080c, 0x4913, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x2099, 0xb680, 0x20a1, 0x020b, 0x7480, 0xa480,
+	0x0018, 0xa080, 0x0007, 0xa084, 0x03f8, 0x8004, 0x20a8, 0x53a6,
+	0x60c3, 0x0014, 0x080c, 0x4979, 0x0005, 0x00f6, 0x7080, 0xa005,
+	0x01f0, 0x2011, 0x494f, 0x080c, 0x6742, 0xa086, 0x0014, 0x11a8,
+	0x2079, 0xb680, 0x7a30, 0xa296, 0x1103, 0x1178, 0x7834, 0xa005,
+	0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110, 0x70b7,
+	0x0001, 0x708b, 0x0012, 0x0029, 0x0010, 0x080c, 0x4992, 0x00fe,
+	0x0005, 0x708b, 0x0013, 0x080c, 0x4a18, 0x20a3, 0x1103, 0x20a3,
+	0x0000, 0x3430, 0x2011, 0xb68e, 0x080c, 0x4a5d, 0x1160, 0x7074,
+	0xa005, 0x1148, 0x714c, 0xa186, 0xffff, 0x0128, 0x080c, 0x4913,
+	0x0110, 0x080c, 0x4a3b, 0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, 0x4979,
+	0x0005, 0x00f6, 0x7080, 0xa005, 0x01f0, 0x2011, 0x494f, 0x080c,
+	0x6742, 0xa086, 0x0014, 0x11a8, 0x2079, 0xb680, 0x7a30, 0xa296,
+	0x1104, 0x1178, 0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128,
+	0x70b4, 0xa005, 0x1110, 0x70b7, 0x0001, 0x708b, 0x0014, 0x0029,
+	0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x0015, 0x080c,
+	0x4a18, 0x20a3, 0x1104, 0x20a3, 0x0000, 0x3430, 0x2011, 0xb68e,
+	0x080c, 0x4a5d, 0x11a8, 0x7074, 0xa005, 0x1190, 0x7154, 0xa186,
+	0xffff, 0x0170, 0xa180, 0x2c8c, 0x200d, 0xa18c, 0xff00, 0x810f,
+	0x080c, 0x4913, 0x0128, 0x080c, 0x3f65, 0x0110, 0x080c, 0x2740,
+	0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x60c3, 0x0014, 0x080c, 0x4979, 0x0005, 0x00f6, 0x7080,
+	0xa005, 0x05b8, 0x2011, 0x494f, 0x080c, 0x6742, 0xa086, 0x0014,
+	0x1570, 0x2079, 0xb680, 0x7a30, 0xa296, 0x1105, 0x1540, 0x7834,
+	0x2011, 0x0100, 0xa21e, 0x1148, 0x7a38, 0xd2fc, 0x0128, 0x70b4,
+	0xa005, 0x1110, 0x70b7, 0x0001, 0x0060, 0xa005, 0x11c0, 0x7a38,
+	0xd2fc, 0x0128, 0x70b4, 0xa005, 0x1110, 0x70b7, 0x0001, 0x7087,
+	0x0000, 0x7a38, 0xd2f4, 0x0138, 0x2001, 0xb174, 0x2004, 0xd0a4,
+	0x1110, 0x70d3, 0x0008, 0x708b, 0x0016, 0x0029, 0x0010, 0x080c,
+	0x4992, 0x00fe, 0x0005, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099,
+	0xb680, 0x20a1, 0x020b, 0x20a9, 0x000e, 0x53a6, 0x3430, 0x2011,
+	0xb68e, 0x708b, 0x0017, 0x080c, 0x4a5d, 0x1150, 0x7074, 0xa005,
+	0x1138, 0x080c, 0x4888, 0x1170, 0xa085, 0x0001, 0x080c, 0x2740,
+	0x20a9, 0x0008, 0x2099, 0xb68e, 0x26a0, 0x53a6, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, 0x4979, 0x0010, 0x080c,
+	0x44a2, 0x0005, 0x00f6, 0x7080, 0xa005, 0x01b0, 0x2011, 0x494f,
+	0x080c, 0x6742, 0xa086, 0x0084, 0x1168, 0x2079, 0xb680, 0x7a30,
+	0xa296, 0x1106, 0x1138, 0x7834, 0xa005, 0x1120, 0x708b, 0x0018,
+	0x0029, 0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x0019,
+	0x080c, 0x4a18, 0x20a3, 0x1106, 0x20a3, 0x0000, 0x3430, 0x2099,
+	0xb68e, 0x2039, 0xb60e, 0x27a0, 0x20a9, 0x0040, 0x53a3, 0x080c,
+	0x4a5d, 0x11e8, 0x2728, 0x2514, 0x8207, 0xa084, 0x00ff, 0x8000,
+	0x2018, 0xa294, 0x00ff, 0x8007, 0xa205, 0x202a, 0x7050, 0x2310,
+	0x8214, 0xa2a0, 0xb60e, 0x2414, 0xa38c, 0x0001, 0x0118, 0xa294,
+	0xff00, 0x0018, 0xa294, 0x00ff, 0x8007, 0xa215, 0x2222, 0x2798,
+	0x26a0, 0x20a9, 0x0040, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x60c3, 0x0084, 0x080c, 0x4979, 0x0005, 0x00f6, 0x7080, 0xa005,
+	0x01d0, 0x2011, 0x494f, 0x080c, 0x6742, 0xa086, 0x0084, 0x1188,
+	0x2079, 0xb680, 0x7a30, 0xa296, 0x1107, 0x1158, 0x7834, 0xa005,
+	0x1140, 0x7087, 0x0001, 0x080c, 0x49fe, 0x708b, 0x001a, 0x0029,
+	0x0010, 0x080c, 0x4992, 0x00fe, 0x0005, 0x708b, 0x001b, 0x20e1,
+	0x9080, 0x20e1, 0x4000, 0x2099, 0xb680, 0x20a1, 0x020b, 0x7480,
+	0xa480, 0x0018, 0xa080, 0x0007, 0xa084, 0x03f8, 0x8004, 0x20a8,
+	0x53a6, 0x60c3, 0x0084, 0x080c, 0x4979, 0x0005, 0x0005, 0x0005,
+	0x0086, 0x0096, 0x2029, 0xb153, 0x252c, 0x20a9, 0x0008, 0x2041,
+	0xb60e, 0x28a0, 0x2099, 0xb68e, 0x53a3, 0x20a9, 0x0008, 0x2011,
+	0x0007, 0xd5d4, 0x0110, 0x2011, 0x0000, 0x2800, 0xa200, 0x200c,
+	0xa1a6, 0xffff, 0x1148, 0xd5d4, 0x0110, 0x8210, 0x0008, 0x8211,
+	0x1f04, 0x489d, 0x0804, 0x490b, 0x82ff, 0x1160, 0xd5d4, 0x0120,
+	0xa1a6, 0x3fff, 0x0d90, 0x0020, 0xa1a6, 0x3fff, 0x0904, 0x490b,
+	0xa18d, 0xc000, 0x20a9, 0x0010, 0x2019, 0x0001, 0xd5d4, 0x0110,
+	0x2019, 0x0010, 0x2120, 0xd5d4, 0x0110, 0x8423, 0x0008, 0x8424,
+	0x1240, 0xd5d4, 0x0110, 0x8319, 0x0008, 0x8318, 0x1f04, 0x48c3,
+	0x04d0, 0x23a8, 0x2021, 0x0001, 0x8426, 0x8425, 0x1f04, 0x48d5,
+	0x2328, 0x8529, 0xa2be, 0x0007, 0x0158, 0x0006, 0x2039, 0x0007,
+	0x2200, 0xa73a, 0x000e, 0x27a8, 0xa5a8, 0x0010, 0x1f04, 0x48e4,
+	0x754e, 0xa5c8, 0x2c8c, 0x292d, 0xa5ac, 0x00ff, 0x7572, 0x6532,
+	0x6536, 0x0016, 0x2508, 0x080c, 0x2720, 0x001e, 0x60e7, 0x0000,
+	0x65ea, 0x2018, 0x2304, 0xa405, 0x201a, 0x7077, 0x0001, 0x26a0,
+	0x2898, 0x20a9, 0x0008, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0xa085, 0x0001, 0x0028, 0xa006, 0x0018, 0xa006, 0x080c, 0x14fa,
+	0x009e, 0x008e, 0x0005, 0x2118, 0x2021, 0x0000, 0x2001, 0x0007,
+	0xa39a, 0x0010, 0x0218, 0x8420, 0x8001, 0x0cd0, 0x2118, 0x84ff,
+	0x0120, 0xa39a, 0x0010, 0x8421, 0x1de0, 0x2021, 0x0001, 0x83ff,
+	0x0118, 0x8423, 0x8319, 0x1de8, 0xa238, 0x2704, 0xa42c, 0x11b8,
+	0xa405, 0x203a, 0x714e, 0xa1a0, 0x2c8c, 0x242d, 0xa5ac, 0x00ff,
+	0x7572, 0x6532, 0x6536, 0x0016, 0x2508, 0x080c, 0x2720, 0x001e,
+	0x60e7, 0x0000, 0x65ea, 0x7077, 0x0001, 0xa084, 0x0000, 0x0005,
+	0x00e6, 0x2071, 0xb100, 0x707b, 0x0000, 0x00ee, 0x0005, 0x00e6,
+	0x00f6, 0x2079, 0x0100, 0x2071, 0x0140, 0x080c, 0x7a8c, 0x7004,
+	0xa084, 0x4000, 0x0120, 0x7003, 0x1000, 0x7003, 0x0000, 0x0126,
+	0x2091, 0x8000, 0x2071, 0xb122, 0x2073, 0x0000, 0x7840, 0x0026,
+	0x0016, 0x2009, 0x00f7, 0x080c, 0x4a24, 0x001e, 0xa094, 0x0010,
+	0xa285, 0x0080, 0x7842, 0x7a42, 0x002e, 0x012e, 0x00fe, 0x00ee,
+	0x0005, 0x0126, 0x2091, 0x8000, 0x2011, 0xb3e3, 0x2013, 0x0000,
+	0x7083, 0x0000, 0x012e, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7,
+	0x9575, 0x080c, 0x7a83, 0x2009, 0x07d0, 0x2011, 0x494f, 0x080c,
+	0x67c8, 0x0005, 0x0016, 0x0026, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x2011, 0x0003, 0x080c, 0x7d52, 0x2011, 0x0002, 0x080c, 0x7d5c,
+	0x080c, 0x7c41, 0x080c, 0x67b6, 0x0036, 0x2019, 0x0000, 0x080c,
+	0x7cc4, 0x003e, 0x2009, 0x00f7, 0x080c, 0x4a24, 0x2061, 0xb3ec,
+	0x601b, 0x0000, 0x601f, 0x0000, 0x2061, 0xb100, 0x6003, 0x0001,
+	0x2061, 0x0100, 0x6043, 0x0090, 0x6043, 0x0010, 0x2009, 0x002d,
+	0x2011, 0x49c9, 0x080c, 0x6736, 0x012e, 0x00ce, 0x002e, 0x001e,
+	0x0005, 0x00e6, 0x0006, 0x0126, 0x2091, 0x8000, 0x2071, 0x0100,
+	0x080c, 0x7a8c, 0x2071, 0x0140, 0x7004, 0xa084, 0x4000, 0x0120,
+	0x7003, 0x1000, 0x7003, 0x0000, 0x080c, 0x58dd, 0x01a8, 0x080c,
+	0x58fb, 0x1190, 0x2001, 0xb39e, 0x2003, 0xaaaa, 0x0016, 0x080c,
+	0x27c4, 0x2001, 0xb38f, 0x2102, 0x001e, 0x2001, 0xb39f, 0x2003,
+	0x0000, 0x080c, 0x5816, 0x0030, 0x2001, 0x0001, 0x080c, 0x269e,
+	0x080c, 0x4992, 0x012e, 0x000e, 0x00ee, 0x0005, 0x20a9, 0x0040,
+	0x20a1, 0xb7c0, 0x2099, 0xb68e, 0x3304, 0x8007, 0x20a2, 0x9398,
+	0x94a0, 0x1f04, 0x4a04, 0x0005, 0x20e1, 0x9080, 0x20e1, 0x4000,
+	0x2099, 0xb600, 0x20a1, 0x020b, 0x20a9, 0x000c, 0x53a6, 0x0005,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xb680, 0x20a1, 0x020b,
+	0x20a9, 0x000c, 0x53a6, 0x0005, 0x00c6, 0x0006, 0x2061, 0x0100,
+	0x810f, 0x2001, 0xb130, 0x2004, 0xa005, 0x1138, 0x2001, 0xb114,
+	0x2004, 0xa084, 0x00ff, 0xa105, 0x0010, 0xa185, 0x00f7, 0x604a,
+	0x000e, 0x00ce, 0x0005, 0x0016, 0x0046, 0x2001, 0xb153, 0x2004,
+	0xd0a4, 0x0158, 0xa006, 0x2020, 0x2009, 0x002a, 0x080c, 0xacae,
+	0x2001, 0xb10c, 0x200c, 0xc195, 0x2102, 0x2019, 0x002a, 0x2009,
+	0x0000, 0x080c, 0x2b46, 0x004e, 0x001e, 0x0005, 0x080c, 0x4992,
+	0x708b, 0x0000, 0x7083, 0x0000, 0x0005, 0x0006, 0x2001, 0xb10c,
+	0x2004, 0xd09c, 0x0100, 0x000e, 0x0005, 0x0006, 0x0016, 0x0126,
+	0x2091, 0x8000, 0x2001, 0x0101, 0x200c, 0xa18d, 0x0006, 0x2102,
+	0x012e, 0x001e, 0x000e, 0x0005, 0x0156, 0x20a9, 0x00ff, 0x2009,
+	0xb235, 0xa006, 0x200a, 0x8108, 0x1f04, 0x4a7a, 0x015e, 0x0005,
+	0x00d6, 0x0036, 0x0156, 0x0136, 0x0146, 0x2069, 0xb152, 0xa006,
+	0x6002, 0x6007, 0x0707, 0x600a, 0x600e, 0x6012, 0xa198, 0x2c8c,
+	0x231d, 0xa39c, 0x00ff, 0x6316, 0x20a9, 0x0004, 0xac98, 0x0006,
+	0x23a0, 0x40a4, 0x20a9, 0x0004, 0xac98, 0x000a, 0x23a0, 0x40a4,
+	0x603e, 0x6042, 0x604e, 0x6052, 0x6056, 0x605a, 0x605e, 0x6062,
+	0x6066, 0x606a, 0x606e, 0x6072, 0x6076, 0x607a, 0x607e, 0x6082,
+	0x6086, 0x608a, 0x608e, 0x6092, 0x6096, 0x609a, 0x609e, 0x60ae,
+	0x61a2, 0x00d6, 0x60a4, 0xa06d, 0x0110, 0x080c, 0x15f4, 0x60a7,
+	0x0000, 0x60a8, 0xa06d, 0x0110, 0x080c, 0x15f4, 0x60ab, 0x0000,
+	0x00de, 0xa006, 0x604a, 0x6810, 0x603a, 0x680c, 0x6046, 0x6814,
+	0xa084, 0x00ff, 0x6042, 0x014e, 0x013e, 0x015e, 0x003e, 0x00de,
+	0x0005, 0x0126, 0x2091, 0x8000, 0x6944, 0x6e48, 0xa684, 0x3fff,
+	0xa082, 0x4000, 0x1a04, 0x4b8f, 0xa18c, 0xff00, 0x810f, 0xa182,
+	0x00ff, 0x1a04, 0x4b94, 0x2001, 0xb10c, 0x2004, 0xa084, 0x0003,
+	0x01c0, 0x2001, 0xb10c, 0x2004, 0xd084, 0x1904, 0x4b77, 0xa188,
+	0xb235, 0x2104, 0xa065, 0x0904, 0x4b77, 0x6004, 0xa084, 0x00ff,
+	0xa08e, 0x0006, 0x1904, 0x4b77, 0x6000, 0xd0c4, 0x0904, 0x4b77,
+	0x0068, 0xa188, 0xb235, 0x2104, 0xa065, 0x0904, 0x4b5b, 0x6004,
+	0xa084, 0x00ff, 0xa08e, 0x0006, 0x1904, 0x4b60, 0x60a4, 0xa00d,
+	0x0118, 0x080c, 0x5046, 0x05d0, 0x60a8, 0xa00d, 0x0188, 0x080c,
+	0x5091, 0x1170, 0x694c, 0xd1fc, 0x1118, 0x080c, 0x4d56, 0x0448,
+	0x080c, 0x4d18, 0x694c, 0xd1ec, 0x1520, 0x080c, 0x4f3a, 0x0408,
+	0x694c, 0xa184, 0xa000, 0x0178, 0xd1ec, 0x0140, 0xd1fc, 0x0118,
+	0x080c, 0x4f49, 0x0028, 0x080c, 0x4f49, 0x0028, 0xd1fc, 0x0118,
+	0x080c, 0x4d18, 0x0070, 0x6050, 0xa00d, 0x0130, 0x2d00, 0x200a,
+	0x6803, 0x0000, 0x6052, 0x0028, 0x2d00, 0x6052, 0x604e, 0x6803,
+	0x0000, 0x080c, 0x6a13, 0xa006, 0x012e, 0x0005, 0x2001, 0x0005,
+	0x2009, 0x0000, 0x04e8, 0x2001, 0x0028, 0x2009, 0x0000, 0x04c0,
+	0xa082, 0x0006, 0x12a0, 0x2001, 0xb134, 0x2004, 0xd0ac, 0x1160,
+	0x60a0, 0xd0bc, 0x1148, 0x6100, 0xd1fc, 0x0904, 0x4b16, 0x2001,
+	0x0029, 0x2009, 0x1000, 0x0420, 0x2001, 0x0028, 0x00a8, 0x2009,
+	0xb10c, 0x210c, 0xd18c, 0x0118, 0x2001, 0x0004, 0x0068, 0xd184,
+	0x0118, 0x2001, 0x0004, 0x0040, 0x2001, 0x0029, 0x6100, 0xd1fc,
+	0x0118, 0x2009, 0x1000, 0x0060, 0x2009, 0x0000, 0x0048, 0x2001,
+	0x0029, 0x2009, 0x0000, 0x0020, 0x2001, 0x0029, 0x2009, 0x0000,
+	0xa005, 0x012e, 0x0005, 0x00e6, 0x0126, 0x2091, 0x8000, 0x6844,
+	0x8007, 0xa084, 0x00ff, 0x2008, 0xa182, 0x00ff, 0x1a04, 0x4bee,
+	0xa188, 0xb235, 0x2104, 0xa065, 0x01c0, 0x6004, 0xa084, 0x00ff,
+	0xa08e, 0x0006, 0x11a8, 0x2c70, 0x080c, 0x8295, 0x05e8, 0x2e00,
+	0x601a, 0x2d00, 0x6012, 0x600b, 0xffff, 0x601f, 0x000a, 0x2009,
+	0x0003, 0x080c, 0x831a, 0xa006, 0x0460, 0x2001, 0x0028, 0x0440,
+	0xa082, 0x0006, 0x1298, 0x2001, 0xb134, 0x2004, 0xd0ac, 0x1158,
+	0x60a0, 0xd0bc, 0x1140, 0x6100, 0xd1fc, 0x09e8, 0x2001, 0x0029,
+	0x2009, 0x1000, 0x00a8, 0x2001, 0x0028, 0x0090, 0x2009, 0xb10c,
+	0x210c, 0xd18c, 0x0118, 0x2001, 0x0004, 0x0050, 0xd184, 0x0118,
+	0x2001, 0x0004, 0x0028, 0x2001, 0x0029, 0x0010, 0x2001, 0x0029,
+	0xa005, 0x012e, 0x00ee, 0x0005, 0x2001, 0x002c, 0x0cc8, 0x00f6,
+	0x00e6, 0x0126, 0x2091, 0x8000, 0x2011, 0x0000, 0x2079, 0xb100,
+	0x6944, 0xa18c, 0xff00, 0x810f, 0xa182, 0x00ff, 0x1a04, 0x4cbc,
+	0x2001, 0xb10c, 0x2004, 0xa084, 0x0003, 0x1904, 0x4caa, 0x080c,
+	0x4e21, 0x1180, 0x6004, 0xa084, 0x00ff, 0xa082, 0x0006, 0x1250,
+	0x2001, 0xb134, 0x2004, 0xd0ac, 0x1904, 0x4ca5, 0x60a0, 0xd0bc,
+	0x1904, 0x4ca5, 0x6864, 0xa0c6, 0x006f, 0x0118, 0x2008, 0x0804,
+	0x4c6e, 0x6968, 0x2140, 0xa18c, 0xff00, 0x810f, 0x78d0, 0xd0ac,
+	0x1118, 0xa182, 0x0080, 0x06d0, 0xa182, 0x00ff, 0x16b8, 0x6a70,
+	0x6b6c, 0x786c, 0xa306, 0x1160, 0x7870, 0xa24e, 0x1118, 0x2208,
+	0x2310, 0x0460, 0xa9cc, 0xff00, 0x1118, 0x2208, 0x2310, 0x0430,
+	0x080c, 0x3c52, 0x2c70, 0x0550, 0x2009, 0x0000, 0x2011, 0x0000,
+	0xa0c6, 0x4000, 0x1160, 0x0006, 0x2e60, 0x080c, 0x50bc, 0x1108,
+	0xc185, 0x7000, 0xd0bc, 0x0108, 0xc18d, 0x000e, 0x0088, 0xa0c6,
+	0x4007, 0x1110, 0x2408, 0x0060, 0xa0c6, 0x4008, 0x1118, 0x2708,
+	0x2610, 0x0030, 0xa0c6, 0x4009, 0x1108, 0x0010, 0x2001, 0x4006,
+	0x6866, 0x696a, 0x6a6e, 0x2001, 0x0030, 0x0450, 0x080c, 0x8295,
+	0x1138, 0x2001, 0x4005, 0x2009, 0x0003, 0x2011, 0x0000, 0x0c80,
+	0x2e00, 0x601a, 0x080c, 0x9c35, 0x2d00, 0x6012, 0x601f, 0x0001,
+	0x6838, 0xd88c, 0x0108, 0xc0f5, 0x683a, 0x0126, 0x2091, 0x8000,
+	0x080c, 0x2b73, 0x012e, 0x2001, 0x0000, 0x080c, 0x4d63, 0x2001,
+	0x0002, 0x080c, 0x4d75, 0x2009, 0x0002, 0x080c, 0x831a, 0xa006,
+	0xa005, 0x012e, 0x00ee, 0x00fe, 0x0005, 0x2001, 0x0028, 0x2009,
+	0x0000, 0x0cb0, 0x2009, 0xb10c, 0x210c, 0xd18c, 0x0118, 0x2001,
+	0x0004, 0x0038, 0xd184, 0x0118, 0x2001, 0x0004, 0x0010, 0x2001,
+	0x0029, 0x2009, 0x0000, 0x0c20, 0x2001, 0x0029, 0x2009, 0x0000,
+	0x08f8, 0x6944, 0x6e48, 0xa684, 0x3fff, 0xa082, 0x4000, 0x16b8,
+	0xa18c, 0xff00, 0x810f, 0xa182, 0x00ff, 0x12e0, 0xa188, 0xb235,
+	0x2104, 0xa065, 0x01b8, 0x6004, 0xa084, 0x00ff, 0xa08e, 0x0006,
+	0x11b0, 0x684c, 0xd0ec, 0x0120, 0x080c, 0x4f49, 0x04c9, 0x0030,
+	0x04b9, 0x684c, 0xd0fc, 0x0110, 0x080c, 0x4f3a, 0x080c, 0x4f87,
+	0xa006, 0x00c8, 0x2001, 0x0028, 0x2009, 0x0000, 0x00a0, 0xa082,
+	0x0006, 0x1240, 0x6100, 0xd1fc, 0x0d20, 0x2001, 0x0029, 0x2009,
+	0x1000, 0x0048, 0x2001, 0x0029, 0x2009, 0x0000, 0x0020, 0x2001,
+	0x0029, 0x2009, 0x0000, 0xa005, 0x0005, 0x0126, 0x2091, 0x8000,
+	0x6050, 0xa00d, 0x0138, 0x2d00, 0x200a, 0x6803, 0x0000, 0x6052,
+	0x012e, 0x0005, 0x2d00, 0x6052, 0x604e, 0x6803, 0x0000, 0x0cc0,
+	0x0126, 0x2091, 0x8000, 0x604c, 0xa005, 0x0170, 0x00e6, 0x2071,
+	0xb3d9, 0x7004, 0xa086, 0x0002, 0x0168, 0x00ee, 0x604c, 0x6802,
+	0x2d00, 0x604e, 0x012e, 0x0005, 0x2d00, 0x6052, 0x604e, 0x6803,
+	0x0000, 0x0cc0, 0x701c, 0xac06, 0x1d80, 0x604c, 0x2070, 0x7000,
+	0x6802, 0x2d00, 0x7002, 0x00ee, 0x012e, 0x0005, 0x0126, 0x2091,
+	0x8000, 0x604c, 0xa06d, 0x0130, 0x6800, 0xa005, 0x1108, 0x6052,
+	0x604e, 0xad05, 0x012e, 0x0005, 0x604c, 0xa06d, 0x0130, 0x6800,
+	0xa005, 0x1108, 0x6052, 0x604e, 0xad05, 0x0005, 0x6803, 0x0000,
+	0x6084, 0xa00d, 0x0120, 0x2d00, 0x200a, 0x6086, 0x0005, 0x2d00,
+	0x6086, 0x6082, 0x0cd8, 0x0126, 0x00c6, 0x0026, 0x2091, 0x8000,
+	0x6218, 0x2260, 0x6200, 0xa005, 0x0110, 0xc285, 0x0008, 0xc284,
+	0x6202, 0x002e, 0x00ce, 0x012e, 0x0005, 0x0126, 0x00c6, 0x2091,
+	0x8000, 0x6218, 0x2260, 0x6204, 0x0006, 0xa086, 0x0006, 0x1180,
+	0x609c, 0xd0ac, 0x0168, 0x2001, 0xb153, 0x2004, 0xd0a4, 0x0140,
+	0xa284, 0xff00, 0x8007, 0xa086, 0x0007, 0x1110, 0x2011, 0x0600,
+	0x000e, 0xa294, 0xff00, 0xa215, 0x6206, 0x0006, 0xa086, 0x0006,
+	0x1128, 0x6290, 0x82ff, 0x1110, 0x080c, 0x14fa, 0x000e, 0x00ce,
+	0x012e, 0x0005, 0x0126, 0x00c6, 0x2091, 0x8000, 0x6218, 0x2260,
+	0x6204, 0x0006, 0xa086, 0x0006, 0x1178, 0x609c, 0xd0a4, 0x0160,
+	0x2001, 0xb153, 0x2004, 0xd0ac, 0x1138, 0xa284, 0x00ff, 0xa086,
+	0x0007, 0x1110, 0x2011, 0x0006, 0x000e, 0xa294, 0x00ff, 0x8007,
+	0xa215, 0x6206, 0x00ce, 0x012e, 0x0005, 0x0026, 0xa182, 0x00ff,
+	0x0218, 0xa085, 0x0001, 0x00b0, 0xa190, 0xb235, 0x2204, 0xa065,
+	0x1180, 0x0016, 0x00d6, 0x080c, 0x15c4, 0x2d60, 0x00de, 0x001e,
+	0x0d80, 0x2c00, 0x2012, 0x60a7, 0x0000, 0x60ab, 0x0000, 0x080c,
+	0x4a80, 0xa006, 0x002e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0026,
+	0xa182, 0x00ff, 0x0218, 0xa085, 0x0001, 0x0480, 0x00d6, 0xa190,
+	0xb235, 0x2204, 0xa06d, 0x0540, 0x2013, 0x0000, 0x00d6, 0x00c6,
+	0x2d60, 0x60a4, 0xa06d, 0x0110, 0x080c, 0x15f4, 0x60a8, 0xa06d,
+	0x0110, 0x080c, 0x15f4, 0x00ce, 0x00de, 0x00d6, 0x00c6, 0x68ac,
+	0x2060, 0x8cff, 0x0168, 0x600c, 0x0006, 0x6010, 0x2068, 0x080c,
+	0x986a, 0x0110, 0x080c, 0x1604, 0x080c, 0x82eb, 0x00ce, 0x0c88,
+	0x00ce, 0x00de, 0x080c, 0x15f4, 0x00de, 0xa006, 0x002e, 0x012e,
+	0x0005, 0x0016, 0xa182, 0x00ff, 0x0218, 0xa085, 0x0001, 0x0030,
+	0xa188, 0xb235, 0x2104, 0xa065, 0x0dc0, 0xa006, 0x001e, 0x0005,
+	0x00d6, 0x0156, 0x0136, 0x0146, 0x600b, 0x0000, 0x600f, 0x0000,
+	0x6000, 0xc08c, 0x6002, 0x080c, 0x58d5, 0x1538, 0x60a0, 0xa086,
+	0x007e, 0x2069, 0xb690, 0x0130, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x11e0, 0x0098, 0x2d04, 0xd0e4, 0x01c0, 0x00d6, 0x2069, 0xb68e,
+	0x00c6, 0x2061, 0xb3b1, 0x6810, 0x2062, 0x6814, 0x6006, 0x6818,
+	0x600a, 0x681c, 0x600e, 0x00ce, 0x00de, 0x8d69, 0x2d04, 0x2069,
+	0x0140, 0x6886, 0x2069, 0xb100, 0x68a2, 0x2069, 0xb68e, 0x6808,
+	0x605e, 0x6810, 0x6062, 0x6138, 0xa10a, 0x0208, 0x603a, 0x6814,
+	0x6066, 0x2099, 0xb696, 0xac88, 0x000a, 0x21a0, 0x20a9, 0x0004,
+	0x53a3, 0x2099, 0xb69a, 0xac88, 0x0006, 0x21a0, 0x20a9, 0x0004,
+	0x53a3, 0x2069, 0xb6ae, 0x6808, 0x606a, 0x690c, 0x616e, 0x6810,
+	0x6072, 0x6818, 0x6076, 0x60a0, 0xa086, 0x007e, 0x1120, 0x2069,
+	0xb68e, 0x690c, 0x616e, 0xa182, 0x0211, 0x1218, 0x2009, 0x0008,
+	0x0400, 0xa182, 0x0259, 0x1218, 0x2009, 0x0007, 0x00d0, 0xa182,
+	0x02c1, 0x1218, 0x2009, 0x0006, 0x00a0, 0xa182, 0x0349, 0x1218,
+	0x2009, 0x0005, 0x0070, 0xa182, 0x0421, 0x1218, 0x2009, 0x0004,
+	0x0040, 0xa182, 0x0581, 0x1218, 0x2009, 0x0003, 0x0010, 0x2009,
+	0x0002, 0x6192, 0x014e, 0x013e, 0x015e, 0x00de, 0x0005, 0x0016,
+	0x0026, 0x00e6, 0x2071, 0xb68d, 0x2e04, 0x6896, 0x2071, 0xb68e,
+	0x7004, 0x689a, 0x701c, 0x689e, 0x6a00, 0x2009, 0xb172, 0x210c,
+	0xd0bc, 0x0120, 0xd1ec, 0x0110, 0xc2ad, 0x0008, 0xc2ac, 0xd0c4,
+	0x0120, 0xd1e4, 0x0110, 0xc2bd, 0x0008, 0xc2bc, 0x6a02, 0x00ee,
+	0x002e, 0x001e, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4,
+	0xa06d, 0x01c0, 0x6900, 0x81ff, 0x1540, 0x6a04, 0xa282, 0x0010,
+	0x1648, 0xad88, 0x0004, 0x20a9, 0x0010, 0x2104, 0xa086, 0xffff,
+	0x0128, 0x8108, 0x1f04, 0x4ef5, 0x080c, 0x14fa, 0x260a, 0x8210,
+	0x6a06, 0x0098, 0x080c, 0x15dd, 0x01a8, 0x2d00, 0x60a6, 0x6803,
+	0x0000, 0xad88, 0x0004, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108,
+	0x1f04, 0x4f0d, 0x6807, 0x0001, 0x6e12, 0xa085, 0x0001, 0x012e,
+	0x00de, 0x0005, 0xa006, 0x0cd8, 0x0126, 0x2091, 0x8000, 0x00d6,
+	0x60a4, 0xa00d, 0x01a0, 0x2168, 0x6800, 0xa005, 0x1160, 0x080c,
+	0x5046, 0x1168, 0x200b, 0xffff, 0x6804, 0xa08a, 0x0002, 0x0218,
+	0x8001, 0x6806, 0x0020, 0x080c, 0x15f4, 0x60a7, 0x0000, 0x00de,
+	0x012e, 0x0005, 0x0126, 0x2091, 0x8000, 0x080c, 0x50a4, 0x0010,
+	0x080c, 0x4d05, 0x080c, 0x4fbe, 0x1dd8, 0x080c, 0x4f87, 0x012e,
+	0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a8, 0xa06d, 0x01c0,
+	0x6950, 0x81ff, 0x1540, 0x6a54, 0xa282, 0x0010, 0x1670, 0xad88,
+	0x0018, 0x20a9, 0x0010, 0x2104, 0xa086, 0xffff, 0x0128, 0x8108,
+	0x1f04, 0x4f5b, 0x080c, 0x14fa, 0x260a, 0x8210, 0x6a56, 0x0098,
+	0x080c, 0x15dd, 0x01d0, 0x2d00, 0x60aa, 0x6853, 0x0000, 0xad88,
+	0x0018, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108, 0x1f04, 0x4f73,
+	0x6857, 0x0001, 0x6e62, 0x0010, 0x080c, 0x4d56, 0x0089, 0x1de0,
+	0xa085, 0x0001, 0x012e, 0x00de, 0x0005, 0xa006, 0x0cd8, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6a13, 0x012e, 0x0005, 0xa01e, 0x0010,
+	0x2019, 0x0001, 0xa00e, 0x0126, 0x2091, 0x8000, 0x604c, 0x2068,
+	0x6000, 0xd0dc, 0x1170, 0x8dff, 0x01e8, 0x83ff, 0x0120, 0x6848,
+	0xa606, 0x0158, 0x0030, 0x683c, 0xa406, 0x1118, 0x6840, 0xa506,
+	0x0120, 0x2d08, 0x6800, 0x2068, 0x0c70, 0x6a00, 0x604c, 0xad06,
+	0x1110, 0x624e, 0x0018, 0xa180, 0x0000, 0x2202, 0x82ff, 0x1110,
+	0x6152, 0x8dff, 0x012e, 0x0005, 0xa01e, 0x0010, 0x2019, 0x0001,
+	0xa00e, 0x6080, 0x2068, 0x8dff, 0x01e8, 0x83ff, 0x0120, 0x6848,
+	0xa606, 0x0158, 0x0030, 0x683c, 0xa406, 0x1118, 0x6840, 0xa506,
+	0x0120, 0x2d08, 0x6800, 0x2068, 0x0c70, 0x6a00, 0x6080, 0xad06,
+	0x1110, 0x6282, 0x0018, 0xa180, 0x0000, 0x2202, 0x82ff, 0x1110,
+	0x6186, 0x8dff, 0x0005, 0xa016, 0x080c, 0x5040, 0x1110, 0x2011,
+	0x0001, 0x080c, 0x508b, 0x1110, 0xa295, 0x0002, 0x0005, 0x080c,
+	0x50bc, 0x0118, 0x080c, 0x9928, 0x0010, 0xa085, 0x0001, 0x0005,
+	0x080c, 0x50bc, 0x0118, 0x080c, 0x98b8, 0x0010, 0xa085, 0x0001,
+	0x0005, 0x080c, 0x50bc, 0x0118, 0x080c, 0x990b, 0x0010, 0xa085,
+	0x0001, 0x0005, 0x080c, 0x50bc, 0x0118, 0x080c, 0x98d4, 0x0010,
+	0xa085, 0x0001, 0x0005, 0x080c, 0x50bc, 0x0118, 0x080c, 0x9944,
+	0x0010, 0xa085, 0x0001, 0x0005, 0x0126, 0x0006, 0x00d6, 0x2091,
+	0x8000, 0x6080, 0xa06d, 0x01a0, 0x6800, 0x0006, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x080c, 0x9ada, 0x0006, 0x6000, 0xd0fc,
+	0x0110, 0x080c, 0xaf4f, 0x000e, 0x080c, 0x5271, 0x000e, 0x0c50,
+	0x6083, 0x0000, 0x6087, 0x0000, 0x00de, 0x000e, 0x012e, 0x0005,
+	0x60a4, 0xa00d, 0x1118, 0xa085, 0x0001, 0x0005, 0x00e6, 0x2170,
+	0x7000, 0xa005, 0x1168, 0x20a9, 0x0010, 0xae88, 0x0004, 0x2104,
+	0xa606, 0x0130, 0x8108, 0x1f04, 0x504f, 0xa085, 0x0001, 0x0008,
+	0xa006, 0x00ee, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4,
+	0xa06d, 0x1128, 0x080c, 0x15dd, 0x01a0, 0x2d00, 0x60a6, 0x6803,
+	0x0001, 0x6807, 0x0000, 0xad88, 0x0004, 0x20a9, 0x0010, 0x200b,
+	0xffff, 0x8108, 0x1f04, 0x506f, 0xa085, 0x0001, 0x012e, 0x00de,
+	0x0005, 0xa006, 0x0cd8, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4,
+	0xa06d, 0x0130, 0x60a7, 0x0000, 0x080c, 0x15f4, 0xa085, 0x0001,
+	0x012e, 0x00de, 0x0005, 0x60a8, 0xa00d, 0x1118, 0xa085, 0x0001,
+	0x0005, 0x00e6, 0x2170, 0x7050, 0xa005, 0x1160, 0x20a9, 0x0010,
+	0xae88, 0x0018, 0x2104, 0xa606, 0x0128, 0x8108, 0x1f04, 0x509a,
+	0xa085, 0x0001, 0x00ee, 0x0005, 0x0126, 0x2091, 0x8000, 0x0c19,
+	0x1188, 0x200b, 0xffff, 0x00d6, 0x60a8, 0x2068, 0x6854, 0xa08a,
+	0x0002, 0x0218, 0x8001, 0x6856, 0x0020, 0x080c, 0x15f4, 0x60ab,
+	0x0000, 0x00de, 0x012e, 0x0005, 0x609c, 0xd0a4, 0x0005, 0x00f6,
+	0x080c, 0x58d5, 0x01b0, 0x71b4, 0x81ff, 0x1198, 0x71d0, 0xd19c,
+	0x0180, 0x2001, 0x007e, 0xa080, 0xb235, 0x2004, 0xa07d, 0x0148,
+	0x7804, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1118, 0x7800, 0xc0ed,
+	0x7802, 0x2079, 0xb152, 0x7804, 0xd0a4, 0x01e8, 0x0156, 0x00c6,
+	0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x080c, 0x4e21, 0x1168,
+	0x6004, 0xa084, 0xff00, 0x8007, 0xa096, 0x0004, 0x0118, 0xa086,
+	0x0006, 0x1118, 0x6000, 0xc0ed, 0x6002, 0x001e, 0x8108, 0x1f04,
+	0x50e4, 0x00ce, 0x015e, 0x080c, 0x517b, 0x0120, 0x2001, 0xb3b4,
+	0x200c, 0x0038, 0x2079, 0xb152, 0x7804, 0xd0a4, 0x0130, 0x2009,
+	0x07d0, 0x2011, 0x510f, 0x080c, 0x67c8, 0x00fe, 0x0005, 0x2011,
+	0x510f, 0x080c, 0x6742, 0x080c, 0x517b, 0x01f0, 0x2001, 0xb2b3,
+	0x2004, 0xa080, 0x0000, 0x200c, 0xc1ec, 0x2102, 0x2001, 0xb153,
+	0x2004, 0xd0a4, 0x0130, 0x2009, 0x07d0, 0x2011, 0x510f, 0x080c,
+	0x67c8, 0x00e6, 0x2071, 0xb100, 0x706f, 0x0000, 0x7073, 0x0000,
+	0x080c, 0x2991, 0x00ee, 0x04b0, 0x0156, 0x00c6, 0x20a9, 0x007f,
+	0x2009, 0x0000, 0x0016, 0x080c, 0x4e21, 0x1530, 0x6000, 0xd0ec,
+	0x0518, 0x0046, 0x62a0, 0xa294, 0x00ff, 0x8227, 0xa006, 0x2009,
+	0x0029, 0x080c, 0xacae, 0x6000, 0xc0e5, 0xc0ec, 0x6002, 0x6004,
+	0xa084, 0x00ff, 0xa085, 0x0700, 0x6006, 0x2019, 0x0029, 0x080c,
+	0x6b35, 0x0076, 0x2039, 0x0000, 0x080c, 0x6a6b, 0x2009, 0x0000,
+	0x080c, 0xaa51, 0x007e, 0x004e, 0x001e, 0x8108, 0x1f04, 0x513a,
+	0x00ce, 0x015e, 0x0005, 0x00c6, 0x6018, 0x2060, 0x6000, 0xc0ec,
+	0x6002, 0x00ce, 0x0005, 0x7818, 0x2004, 0xd0ac, 0x0005, 0x7818,
+	0x2004, 0xd0bc, 0x0005, 0x00f6, 0x2001, 0xb2b3, 0x2004, 0xa07d,
+	0x0110, 0x7800, 0xd0ec, 0x00fe, 0x0005, 0x0126, 0x0026, 0x2091,
+	0x8000, 0x6200, 0xa005, 0x0110, 0xc2fd, 0x0008, 0xc2fc, 0x6202,
+	0x002e, 0x012e, 0x0005, 0x2011, 0xb134, 0x2204, 0xd0cc, 0x0138,
+	0x2001, 0xb3b2, 0x200c, 0x2011, 0x51a0, 0x080c, 0x67c8, 0x0005,
+	0x2011, 0x51a0, 0x080c, 0x6742, 0x2011, 0xb134, 0x2204, 0xc0cc,
+	0x2012, 0x0005, 0x2071, 0xb214, 0x7003, 0x0001, 0x7007, 0x0000,
+	0x7013, 0x0000, 0x7017, 0x0000, 0x701b, 0x0000, 0x701f, 0x0000,
+	0x700b, 0x0000, 0x704b, 0x0001, 0x704f, 0x0000, 0x705b, 0x0020,
+	0x705f, 0x0040, 0x707f, 0x0000, 0x2071, 0xb37d, 0x7003, 0xb214,
+	0x7007, 0x0000, 0x700b, 0x0000, 0x700f, 0xb35d, 0x7013, 0x0020,
+	0x7017, 0x0040, 0x7037, 0x0000, 0x0005, 0x0016, 0x00e6, 0x2071,
+	0xb335, 0xa00e, 0x7186, 0x718a, 0x7097, 0x0001, 0x2001, 0xb153,
+	0x2004, 0xd0fc, 0x1150, 0x2001, 0xb153, 0x2004, 0xa00e, 0xd09c,
+	0x0108, 0x8108, 0x7102, 0x0804, 0x523b, 0x2001, 0xb172, 0x200c,
+	0xa184, 0x000f, 0x2009, 0xb173, 0x210c, 0x0002, 0x51e3, 0x5216,
+	0x521d, 0x5227, 0x522c, 0x51e3, 0x51e3, 0x51e3, 0x5206, 0x51e3,
+	0x51e3, 0x51e3, 0x51e3, 0x51e3, 0x51e3, 0x51e3, 0x7003, 0x0004,
+	0x0136, 0x0146, 0x0156, 0x2099, 0xb176, 0x20a1, 0xb386, 0x20a9,
+	0x0004, 0x53a3, 0x015e, 0x014e, 0x013e, 0x0428, 0x708f, 0x0005,
+	0x7007, 0x0122, 0x2001, 0x0002, 0x0030, 0x708f, 0x0002, 0x7007,
+	0x0121, 0x2001, 0x0003, 0x7002, 0x7097, 0x0001, 0x0088, 0x7007,
+	0x0122, 0x2001, 0x0002, 0x0020, 0x7007, 0x0121, 0x2001, 0x0003,
+	0x7002, 0xa006, 0x7096, 0x708e, 0xa184, 0xff00, 0x8007, 0x709a,
+	0xa184, 0x00ff, 0x7092, 0x00ee, 0x001e, 0x0005, 0x00e6, 0x2071,
+	0xb214, 0x684c, 0xa005, 0x1130, 0x7028, 0xc085, 0x702a, 0xa085,
+	0x0001, 0x0428, 0x6a60, 0x7236, 0x6b64, 0x733a, 0x6868, 0x703e,
+	0x7076, 0x686c, 0x7042, 0x707a, 0x684c, 0x702e, 0x6844, 0x7032,
+	0x2009, 0x000d, 0x200a, 0x700b, 0x0000, 0x8007, 0x8006, 0x8006,
+	0xa08c, 0x003f, 0xa084, 0xffc0, 0xa210, 0x2100, 0xa319, 0x726e,
+	0x7372, 0x7028, 0xc084, 0x702a, 0x7007, 0x0001, 0xa006, 0x00ee,
+	0x0005, 0x0156, 0x00e6, 0x0026, 0x6838, 0xd0fc, 0x1904, 0x52ca,
+	0x6804, 0xa00d, 0x0188, 0x00d6, 0x2071, 0xb100, 0xa016, 0x702c,
+	0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e,
+	0x70b0, 0xa200, 0x70b2, 0x00de, 0x2071, 0xb214, 0x701c, 0xa005,
+	0x1904, 0x52da, 0x20a9, 0x0032, 0x0f04, 0x52d8, 0x0e04, 0x5294,
+	0x2071, 0xb335, 0x7200, 0x82ff, 0x05d8, 0x6934, 0xa186, 0x0103,
+	0x1904, 0x52e8, 0x6948, 0x6844, 0xa105, 0x1540, 0x2009, 0x8020,
+	0x2200, 0x0002, 0x52d8, 0x52af, 0x5300, 0x530c, 0x52d8, 0x2071,
+	0x0000, 0x20a9, 0x0032, 0x0f04, 0x52d8, 0x7018, 0xd084, 0x1dd8,
+	0x7122, 0x683c, 0x7026, 0x6840, 0x702a, 0x701b, 0x0001, 0x2091,
+	0x4080, 0x2071, 0xb100, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0,
+	0x8000, 0x70b2, 0x002e, 0x00ee, 0x015e, 0x0005, 0x6844, 0xa086,
+	0x0100, 0x1130, 0x6868, 0xa005, 0x1118, 0x2009, 0x8020, 0x0880,
+	0x2071, 0xb214, 0x2d08, 0x206b, 0x0000, 0x7010, 0x8000, 0x7012,
+	0x7018, 0xa06d, 0x711a, 0x0110, 0x6902, 0x0008, 0x711e, 0x0c10,
+	0xa18c, 0x00ff, 0xa186, 0x0017, 0x0130, 0xa186, 0x001e, 0x0118,
+	0xa18e, 0x001f, 0x1d28, 0x684c, 0xd0cc, 0x0d10, 0x6850, 0xa084,
+	0x00ff, 0xa086, 0x0001, 0x19e0, 0x2009, 0x8021, 0x0804, 0x52a8,
+	0x7084, 0x8008, 0xa092, 0x001e, 0x1a98, 0x7186, 0xae90, 0x0003,
+	0xa210, 0x683c, 0x2012, 0x0078, 0x7084, 0x8008, 0xa092, 0x000f,
+	0x1a38, 0x7186, 0xae90, 0x0003, 0x8003, 0xa210, 0x683c, 0x2012,
+	0x8210, 0x6840, 0x2012, 0x7088, 0xa10a, 0x0a04, 0x52c1, 0x718c,
+	0x7084, 0xa10a, 0x0a04, 0x52c1, 0x2071, 0x0000, 0x7018, 0xd084,
+	0x1904, 0x52c1, 0x2071, 0xb335, 0x7000, 0xa086, 0x0002, 0x1150,
+	0x080c, 0x558b, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091, 0x4080,
+	0x0804, 0x52c1, 0x080c, 0x55b5, 0x2071, 0x0000, 0x701b, 0x0001,
+	0x2091, 0x4080, 0x0804, 0x52c1, 0x0006, 0x684c, 0x0006, 0x6837,
+	0x0103, 0x20a9, 0x001c, 0xad80, 0x0011, 0x20a0, 0x2001, 0x0000,
+	0x40a4, 0x000e, 0xa084, 0x00ff, 0x684e, 0x000e, 0x684a, 0x6952,
+	0x0005, 0x2071, 0xb214, 0x7004, 0x0002, 0x5367, 0x5378, 0x5576,
+	0x5577, 0x5584, 0x558a, 0x5368, 0x5567, 0x54fd, 0x5553, 0x0005,
+	0x0126, 0x2091, 0x8000, 0x0e04, 0x5377, 0x2009, 0x000d, 0x7030,
+	0x200a, 0x2091, 0x4080, 0x7007, 0x0001, 0x700b, 0x0000, 0x012e,
+	0x2069, 0xb3ec, 0x683c, 0xa005, 0x03f8, 0x11f0, 0x0126, 0x2091,
+	0x8000, 0x2069, 0x0000, 0x6934, 0x2001, 0xb220, 0x2004, 0xa10a,
+	0x0170, 0x0e04, 0x539b, 0x2069, 0x0000, 0x6818, 0xd084, 0x1158,
+	0x2009, 0x8040, 0x6922, 0x681b, 0x0001, 0x2091, 0x4080, 0x2069,
+	0xb3ec, 0x683f, 0xffff, 0x012e, 0x2069, 0xb100, 0x6844, 0x6964,
+	0xa102, 0x2069, 0xb335, 0x688a, 0x6984, 0x701c, 0xa06d, 0x0120,
+	0x81ff, 0x0904, 0x53f1, 0x00a0, 0x81ff, 0x0904, 0x54b7, 0x2071,
+	0xb335, 0x7184, 0x7088, 0xa10a, 0x1258, 0x7190, 0x2071, 0xb3ec,
+	0x7038, 0xa005, 0x0128, 0x1b04, 0x54b7, 0x713a, 0x0804, 0x54b7,
+	0x2071, 0xb335, 0x718c, 0x0126, 0x2091, 0x8000, 0x7084, 0xa10a,
+	0x0a04, 0x54d2, 0x0e04, 0x5473, 0x2071, 0x0000, 0x7018, 0xd084,
+	0x1904, 0x5473, 0x2001, 0xffff, 0x2071, 0xb3ec, 0x703a, 0x2071,
+	0xb335, 0x7000, 0xa086, 0x0002, 0x1150, 0x080c, 0x558b, 0x2071,
+	0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0804, 0x5473, 0x080c,
+	0x55b5, 0x2071, 0x0000, 0x701b, 0x0001, 0x2091, 0x4080, 0x0804,
+	0x5473, 0x2071, 0xb335, 0x7000, 0xa005, 0x0904, 0x5499, 0x6934,
+	0xa186, 0x0103, 0x1904, 0x5476, 0x684c, 0xd0bc, 0x1904, 0x5499,
+	0x6948, 0x6844, 0xa105, 0x1904, 0x548e, 0x2009, 0x8020, 0x2071,
+	0xb335, 0x7000, 0x0002, 0x5499, 0x5459, 0x5431, 0x5443, 0x5410,
+	0x0136, 0x0146, 0x0156, 0x2099, 0xb176, 0x20a1, 0xb386, 0x20a9,
+	0x0004, 0x53a3, 0x015e, 0x014e, 0x013e, 0x2071, 0xb37d, 0xad80,
+	0x000f, 0x700e, 0x7013, 0x0002, 0x7007, 0x0002, 0x700b, 0x0000,
+	0x2e10, 0x080c, 0x1628, 0x2071, 0xb214, 0x7007, 0x0009, 0x0804,
+	0x54b7, 0x7084, 0x8008, 0xa092, 0x001e, 0x1a04, 0x54b7, 0xae90,
+	0x0003, 0xa210, 0x683c, 0x2012, 0x7186, 0x2071, 0xb214, 0x080c,
+	0x560c, 0x0804, 0x54b7, 0x7084, 0x8008, 0xa092, 0x000f, 0x1a04,
+	0x54b7, 0xae90, 0x0003, 0x8003, 0xa210, 0x683c, 0x2012, 0x8210,
+	0x6840, 0x2012, 0x7186, 0x2071, 0xb214, 0x080c, 0x560c, 0x0804,
+	0x54b7, 0x0126, 0x2091, 0x8000, 0x0e04, 0x5473, 0x2071, 0x0000,
+	0x7018, 0xd084, 0x1180, 0x7122, 0x683c, 0x7026, 0x6840, 0x702a,
+	0x701b, 0x0001, 0x2091, 0x4080, 0x012e, 0x2071, 0xb214, 0x080c,
+	0x560c, 0x0804, 0x54b7, 0x012e, 0x0804, 0x54b7, 0xa18c, 0x00ff,
+	0xa186, 0x0017, 0x0130, 0xa186, 0x001e, 0x0118, 0xa18e, 0x001f,
+	0x11c0, 0x684c, 0xd0cc, 0x01a8, 0x6850, 0xa084, 0x00ff, 0xa086,
+	0x0001, 0x1178, 0x2009, 0x8021, 0x0804, 0x5407, 0x6844, 0xa086,
+	0x0100, 0x1138, 0x6868, 0xa005, 0x1120, 0x2009, 0x8020, 0x0804,
+	0x5407, 0x2071, 0xb214, 0x080c, 0x561e, 0x01c8, 0x2071, 0xb214,
+	0x700f, 0x0001, 0x6934, 0xa184, 0x00ff, 0xa086, 0x0003, 0x1130,
+	0x810f, 0xa18c, 0x00ff, 0x8101, 0x0108, 0x710e, 0x7007, 0x0003,
+	0x080c, 0x5637, 0x7050, 0xa086, 0x0100, 0x0904, 0x5577, 0x0126,
+	0x2091, 0x8000, 0x2071, 0xb214, 0x7008, 0xa086, 0x0001, 0x1180,
+	0x0e04, 0x54d0, 0x2009, 0x000d, 0x7030, 0x200a, 0x2091, 0x4080,
+	0x700b, 0x0000, 0x7004, 0xa086, 0x0006, 0x1110, 0x7007, 0x0001,
+	0x012e, 0x0005, 0x2071, 0xb214, 0x080c, 0x561e, 0x0518, 0x2071,
+	0xb335, 0x7084, 0x700a, 0x20a9, 0x0020, 0x2099, 0xb336, 0x20a1,
+	0xb35d, 0x53a3, 0x7087, 0x0000, 0x2071, 0xb214, 0x2069, 0xb37d,
+	0x706c, 0x6826, 0x7070, 0x682a, 0x7074, 0x682e, 0x7078, 0x6832,
+	0x2d10, 0x080c, 0x1628, 0x7007, 0x0008, 0x2001, 0xffff, 0x2071,
+	0xb3ec, 0x703a, 0x012e, 0x0804, 0x54b7, 0x2069, 0xb37d, 0x6808,
+	0xa08e, 0x0000, 0x0904, 0x5552, 0xa08e, 0x0200, 0x0904, 0x5550,
+	0xa08e, 0x0100, 0x1904, 0x5552, 0x0126, 0x2091, 0x8000, 0x0e04,
+	0x554e, 0x2069, 0x0000, 0x6818, 0xd084, 0x15c0, 0x702c, 0x7130,
+	0x8108, 0xa102, 0x0230, 0xa00e, 0x7034, 0x706e, 0x7038, 0x7072,
+	0x0048, 0x706c, 0xa080, 0x0040, 0x706e, 0x1220, 0x7070, 0xa081,
+	0x0000, 0x7072, 0x7132, 0x6936, 0x700b, 0x0000, 0x2001, 0xb35a,
+	0x2004, 0xa005, 0x1190, 0x6934, 0x2069, 0xb335, 0x689c, 0x699e,
+	0x2069, 0xb3ec, 0xa102, 0x1118, 0x683c, 0xa005, 0x1368, 0x2001,
+	0xb35b, 0x200c, 0x810d, 0x693e, 0x0038, 0x2009, 0x8040, 0x6922,
+	0x681b, 0x0001, 0x2091, 0x4080, 0x7007, 0x0001, 0x012e, 0x0010,
+	0x7007, 0x0005, 0x0005, 0x2001, 0xb37f, 0x2004, 0xa08e, 0x0100,
+	0x1128, 0x7007, 0x0001, 0x080c, 0x560c, 0x0005, 0xa08e, 0x0000,
+	0x0de0, 0xa08e, 0x0200, 0x1dc8, 0x7007, 0x0005, 0x0005, 0x701c,
+	0xa06d, 0x0158, 0x080c, 0x561e, 0x0140, 0x7007, 0x0003, 0x080c,
+	0x5637, 0x7050, 0xa086, 0x0100, 0x0110, 0x0005, 0x0005, 0x7050,
+	0xa09e, 0x0100, 0x1118, 0x7007, 0x0004, 0x0030, 0xa086, 0x0200,
+	0x1110, 0x7007, 0x0005, 0x0005, 0x080c, 0x55da, 0x7006, 0x080c,
+	0x560c, 0x0005, 0x0005, 0x00e6, 0x0156, 0x2071, 0xb335, 0x7184,
+	0x81ff, 0x0500, 0xa006, 0x7086, 0xae80, 0x0003, 0x2071, 0x0000,
+	0x21a8, 0x2014, 0x7226, 0x8000, 0x0f04, 0x55af, 0x2014, 0x722a,
+	0x8000, 0x0f04, 0x55af, 0x2014, 0x722e, 0x8000, 0x0f04, 0x55af,
+	0x2014, 0x723a, 0x8000, 0x0f04, 0x55af, 0x2014, 0x723e, 0xa180,
+	0x8030, 0x7022, 0x015e, 0x00ee, 0x0005, 0x00e6, 0x0156, 0x2071,
+	0xb335, 0x7184, 0x81ff, 0x01d8, 0xa006, 0x7086, 0xae80, 0x0003,
+	0x2071, 0x0000, 0x21a8, 0x2014, 0x7226, 0x8000, 0x2014, 0x722a,
+	0x8000, 0x0f04, 0x55d1, 0x2014, 0x723a, 0x8000, 0x2014, 0x723e,
+	0x0018, 0x2001, 0x8020, 0x0010, 0x2001, 0x8042, 0x7022, 0x015e,
+	0x00ee, 0x0005, 0x702c, 0x7130, 0x8108, 0xa102, 0x0230, 0xa00e,
+	0x7034, 0x706e, 0x7038, 0x7072, 0x0048, 0x706c, 0xa080, 0x0040,
+	0x706e, 0x1220, 0x7070, 0xa081, 0x0000, 0x7072, 0x7132, 0x700c,
+	0x8001, 0x700e, 0x1180, 0x0126, 0x2091, 0x8000, 0x0e04, 0x5606,
+	0x2001, 0x000d, 0x2102, 0x2091, 0x4080, 0x2001, 0x0001, 0x700b,
+	0x0000, 0x012e, 0x0005, 0x2001, 0x0007, 0x0005, 0x2001, 0x0006,
+	0x700b, 0x0001, 0x012e, 0x0005, 0x701c, 0xa06d, 0x0170, 0x0126,
+	0x2091, 0x8000, 0x7010, 0x8001, 0x7012, 0x2d04, 0x701e, 0xa005,
+	0x1108, 0x701a, 0x012e, 0x080c, 0x15f4, 0x0005, 0x2019, 0x000d,
+	0x2304, 0x230c, 0xa10e, 0x0130, 0x2304, 0x230c, 0xa10e, 0x0110,
+	0xa006, 0x0060, 0x732c, 0x8319, 0x7130, 0xa102, 0x1118, 0x2300,
+	0xa005, 0x0020, 0x0210, 0xa302, 0x0008, 0x8002, 0x0005, 0x2d00,
+	0x7026, 0xa080, 0x000d, 0x7056, 0x7053, 0x0000, 0x0126, 0x2091,
+	0x8000, 0x2009, 0xb408, 0x2104, 0xc08d, 0x200a, 0x012e, 0x080c,
+	0x1640, 0x0005, 0x7088, 0xa08a, 0x0029, 0x1220, 0xa082, 0x001d,
+	0x0033, 0x0010, 0x080c, 0x14fa, 0x6027, 0x1e00, 0x0005, 0x573d,
+	0x56c0, 0x56d6, 0x5711, 0x5730, 0x5762, 0x5774, 0x56d6, 0x574e,
+	0x5664, 0x5692, 0x5663, 0x0005, 0x00d6, 0x2069, 0x0200, 0x6804,
+	0xa005, 0x1180, 0x6808, 0xa005, 0x1518, 0x708b, 0x0028, 0x2069,
+	0xb3be, 0x2d04, 0x7002, 0x080c, 0x59d7, 0x6028, 0xa085, 0x0600,
+	0x602a, 0x00b0, 0x708b, 0x0028, 0x2069, 0xb3be, 0x2d04, 0x7002,
+	0x6028, 0xa085, 0x0600, 0x602a, 0x00e6, 0x0036, 0x0046, 0x0056,
+	0x2071, 0xb419, 0x080c, 0x1d48, 0x005e, 0x004e, 0x003e, 0x00ee,
+	0x00de, 0x0005, 0x00d6, 0x2069, 0x0200, 0x6804, 0xa005, 0x1180,
+	0x6808, 0xa005, 0x1518, 0x708b, 0x0028, 0x2069, 0xb3be, 0x2d04,
+	0x7002, 0x080c, 0x5a64, 0x6028, 0xa085, 0x0600, 0x602a, 0x00b0,
+	0x708b, 0x0028, 0x2069, 0xb3be, 0x2d04, 0x7002, 0x6028, 0xa085,
+	0x0600, 0x602a, 0x00e6, 0x0036, 0x0046, 0x0056, 0x2071, 0xb419,
+	0x080c, 0x1d48, 0x005e, 0x004e, 0x003e, 0x00ee, 0x00de, 0x0005,
+	0x6803, 0x0090, 0x6124, 0xd1e4, 0x1180, 0x080c, 0x57df, 0xd1d4,
+	0x1150, 0xd1dc, 0x1128, 0xd1cc, 0x0140, 0x708b, 0x0020, 0x0028,
+	0x708b, 0x001d, 0x0010, 0x708b, 0x001f, 0x0005, 0x6803, 0x0088,
+	0x6124, 0xd1cc, 0x1580, 0xd1dc, 0x1558, 0xd1e4, 0x1530, 0xa184,
+	0x1e00, 0x1570, 0x60e3, 0x0001, 0x600c, 0xc0b4, 0x600e, 0x080c,
+	0x5905, 0x0156, 0x6803, 0x0100, 0x20a9, 0x0014, 0x6804, 0xd0dc,
+	0x1118, 0x1f04, 0x56ee, 0x0048, 0x20a9, 0x0014, 0x6803, 0x0080,
+	0x6804, 0xd0d4, 0x1130, 0x1f04, 0x56f8, 0x080c, 0x5926, 0x015e,
+	0x0078, 0x015e, 0x708b, 0x0028, 0x0058, 0x708b, 0x001e, 0x0040,
+	0x708b, 0x001d, 0x0028, 0x708b, 0x0020, 0x0010, 0x708b, 0x001f,
+	0x0005, 0x60e3, 0x0001, 0x600c, 0xc0b4, 0x600e, 0x080c, 0x5905,
+	0x6803, 0x0080, 0x6124, 0xd1d4, 0x1180, 0xd1dc, 0x1158, 0xd1e4,
+	0x1130, 0xa184, 0x1e00, 0x1158, 0x708b, 0x0028, 0x0040, 0x708b,
+	0x001e, 0x0028, 0x708b, 0x001d, 0x0010, 0x708b, 0x001f, 0x0005,
+	0x6803, 0x00a0, 0x6124, 0xd1dc, 0x1128, 0xd1e4, 0x0128, 0x708b,
+	0x001e, 0x0010, 0x708b, 0x001d, 0x0005, 0x080c, 0x5809, 0x6124,
+	0xd1dc, 0x1158, 0x080c, 0x57df, 0xd1d4, 0x1128, 0xd1e4, 0x0128,
+	0x708b, 0x001e, 0x0010, 0x708b, 0x001f, 0x0005, 0x6803, 0x00a0,
+	0x6124, 0xd1d4, 0x1160, 0xd1cc, 0x1150, 0xd1dc, 0x1128, 0xd1e4,
+	0x0140, 0x708b, 0x001e, 0x0028, 0x708b, 0x001d, 0x0010, 0x708b,
+	0x0021, 0x0005, 0x080c, 0x5809, 0x6124, 0xd1d4, 0x1150, 0xd1dc,
+	0x1128, 0xd1e4, 0x0140, 0x708b, 0x001e, 0x0028, 0x708b, 0x001d,
+	0x0010, 0x708b, 0x001f, 0x0005, 0x6803, 0x0090, 0x6124, 0xd1d4,
+	0x1178, 0xd1cc, 0x1150, 0xd1dc, 0x1128, 0xd1e4, 0x0158, 0x708b,
+	0x001e, 0x0040, 0x708b, 0x001d, 0x0028, 0x708b, 0x0020, 0x0010,
+	0x708b, 0x001f, 0x0005, 0x0016, 0x00c6, 0x00d6, 0x00e6, 0x0126,
+	0x2061, 0x0100, 0x2069, 0x0140, 0x2071, 0xb100, 0x2091, 0x8000,
+	0x080c, 0x58d5, 0x11e8, 0x2001, 0xb10c, 0x200c, 0xd1b4, 0x01c0,
+	0xc1b4, 0x2102, 0x6027, 0x0200, 0xe000, 0xe000, 0x6024, 0xd0cc,
+	0x0158, 0x6803, 0x00a0, 0x2001, 0xb39f, 0x2003, 0x0001, 0x2001,
+	0xb100, 0x2003, 0x0001, 0x0428, 0x6028, 0xc0cd, 0x602a, 0x0408,
+	0x080c, 0x58f1, 0x0150, 0x080c, 0x58e7, 0x1138, 0x2001, 0x0001,
+	0x080c, 0x269e, 0x080c, 0x58ac, 0x00a0, 0x080c, 0x5806, 0x0178,
+	0x2001, 0x0001, 0x080c, 0x269e, 0x7088, 0xa086, 0x001e, 0x0120,
+	0x7088, 0xa086, 0x0022, 0x1118, 0x708b, 0x0025, 0x0010, 0x708b,
+	0x0021, 0x012e, 0x00ee, 0x00de, 0x00ce, 0x001e, 0x0005, 0x0016,
+	0x0026, 0x2009, 0x0064, 0x2011, 0x57ea, 0x080c, 0x6736, 0x002e,
+	0x001e, 0x0005, 0x00e6, 0x00f6, 0x0016, 0x080c, 0x7a8c, 0x2071,
+	0xb100, 0x080c, 0x578b, 0x001e, 0x00fe, 0x00ee, 0x0005, 0x2001,
+	0xb100, 0x2004, 0xa086, 0x0004, 0x0140, 0x2001, 0xb39e, 0x2003,
+	0xaaaa, 0x2001, 0xb39f, 0x2003, 0x0000, 0x0005, 0x6020, 0xd09c,
+	0x0005, 0x6803, 0x00c0, 0x0156, 0x20a9, 0x002d, 0x1d04, 0x580e,
+	0x2091, 0x6000, 0x1f04, 0x580e, 0x015e, 0x0005, 0x00c6, 0x00d6,
+	0x00e6, 0x2061, 0x0100, 0x2069, 0x0140, 0x2071, 0xb100, 0x2001,
+	0xb39f, 0x200c, 0xa186, 0x0000, 0x0158, 0xa186, 0x0001, 0x0158,
+	0xa186, 0x0002, 0x0158, 0xa186, 0x0003, 0x0158, 0x0804, 0x589a,
+	0x708b, 0x0022, 0x0040, 0x708b, 0x0021, 0x0028, 0x708b, 0x0023,
+	0x0020, 0x708b, 0x0024, 0x6043, 0x0000, 0x60e3, 0x0000, 0x6887,
+	0x0001, 0x2001, 0x0001, 0x080c, 0x274b, 0x0026, 0x2011, 0x0003,
+	0x080c, 0x7d52, 0x2011, 0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41,
+	0x080c, 0x67b6, 0x0036, 0x2019, 0x0000, 0x080c, 0x7cc4, 0x003e,
+	0x002e, 0x7000, 0xa08e, 0x0004, 0x0118, 0x602b, 0x0028, 0x0010,
+	0x602b, 0x0020, 0x0156, 0x0126, 0x2091, 0x8000, 0x20a9, 0x0005,
+	0x6024, 0xd0ac, 0x0118, 0x012e, 0x015e, 0x04d0, 0x6800, 0xa084,
+	0x00a0, 0xc0bd, 0x6802, 0x6904, 0xd1d4, 0x1130, 0x6803, 0x0100,
+	0x1f04, 0x5868, 0x080c, 0x5926, 0x012e, 0x015e, 0x080c, 0x58e7,
+	0x01a8, 0x6044, 0xa005, 0x0168, 0x6050, 0x0006, 0xa085, 0x0020,
+	0x6052, 0x080c, 0x5926, 0xa006, 0x8001, 0x1df0, 0x000e, 0x6052,
+	0x0028, 0x6804, 0xd0d4, 0x1110, 0x080c, 0x5926, 0x2001, 0xb39f,
+	0x2003, 0x0004, 0x080c, 0x564a, 0x080c, 0x58e7, 0x0148, 0x6804,
+	0xd0d4, 0x1130, 0xd0dc, 0x1100, 0x2001, 0xb39f, 0x2003, 0x0000,
+	0x00ee, 0x00de, 0x00ce, 0x0005, 0x00c6, 0x00d6, 0x00e6, 0x2061,
+	0x0100, 0x2069, 0x0140, 0x2071, 0xb100, 0x2001, 0xb39e, 0x2003,
+	0x0000, 0x2001, 0xb38f, 0x2003, 0x0000, 0x708b, 0x0000, 0x60e3,
+	0x0000, 0x6887, 0x0000, 0x2001, 0x0000, 0x080c, 0x274b, 0x6803,
+	0x0000, 0x6043, 0x0090, 0x6043, 0x0010, 0x6027, 0xffff, 0x602b,
+	0x182f, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x0006, 0x2001, 0xb39e,
+	0x2004, 0xa086, 0xaaaa, 0x000e, 0x0005, 0x0006, 0x2001, 0xb172,
+	0x2004, 0xa084, 0x0030, 0xa086, 0x0000, 0x000e, 0x0005, 0x0006,
+	0x2001, 0xb172, 0x2004, 0xa084, 0x0030, 0xa086, 0x0030, 0x000e,
+	0x0005, 0x0006, 0x2001, 0xb172, 0x2004, 0xa084, 0x0030, 0xa086,
+	0x0010, 0x000e, 0x0005, 0x0006, 0x2001, 0xb172, 0x2004, 0xa084,
+	0x0030, 0xa086, 0x0020, 0x000e, 0x0005, 0x2001, 0xb10c, 0x2004,
+	0xd0a4, 0x0170, 0x080c, 0x276b, 0x0036, 0x0016, 0x2009, 0x0000,
+	0x2019, 0x0028, 0x080c, 0x2b46, 0x001e, 0x003e, 0xa006, 0x0009,
+	0x0005, 0x00e6, 0x2071, 0xb10c, 0x2e04, 0x0118, 0xa085, 0x0010,
+	0x0010, 0xa084, 0xffef, 0x2072, 0x00ee, 0x0005, 0x6050, 0x0006,
+	0x60f0, 0x0006, 0x60ec, 0x0006, 0x600c, 0x0006, 0x6004, 0x0006,
+	0x6028, 0x0006, 0x602f, 0x0100, 0x602f, 0x0000, 0x602f, 0x0040,
+	0x602f, 0x0000, 0x000e, 0x602a, 0x000e, 0x6006, 0x000e, 0x600e,
+	0x000e, 0x60ee, 0x000e, 0x60f2, 0x60e3, 0x0000, 0x6887, 0x0001,
+	0x2001, 0x0001, 0x080c, 0x274b, 0x6800, 0xa084, 0x00a0, 0xc0bd,
+	0x6802, 0x6803, 0x00a0, 0x000e, 0x6052, 0x6050, 0x0005, 0x0156,
+	0x0016, 0x0026, 0x0036, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100,
+	0x2069, 0x0140, 0x2071, 0xb100, 0x6020, 0xa084, 0x0080, 0x0138,
+	0x2001, 0xb10c, 0x200c, 0xc1bd, 0x2102, 0x0804, 0x59cf, 0x2001,
+	0xb10c, 0x200c, 0xc1bc, 0x2102, 0x6028, 0xa084, 0xe1ff, 0x602a,
+	0x6027, 0x0200, 0x6803, 0x0090, 0x20a9, 0x0384, 0x6024, 0xd0cc,
+	0x1518, 0x1d04, 0x597e, 0x2091, 0x6000, 0x1f04, 0x597e, 0x2011,
+	0x0003, 0x080c, 0x7d52, 0x2011, 0x0002, 0x080c, 0x7d5c, 0x080c,
+	0x7c41, 0x080c, 0x67b6, 0x2019, 0x0000, 0x080c, 0x7cc4, 0x6803,
+	0x00a0, 0x2001, 0xb39f, 0x2003, 0x0001, 0x2001, 0xb100, 0x2003,
+	0x0001, 0xa085, 0x0001, 0x0458, 0x86ff, 0x1110, 0x080c, 0x1daa,
+	0x60e3, 0x0000, 0x2001, 0xb38f, 0x2004, 0x080c, 0x274b, 0x60e2,
+	0x6803, 0x0080, 0x20a9, 0x0384, 0x6027, 0x1e00, 0x2009, 0x1e00,
+	0xe000, 0x6024, 0xa10c, 0x0138, 0x1d04, 0x59b4, 0x2091, 0x6000,
+	0x1f04, 0x59b4, 0x0820, 0x6028, 0xa085, 0x1e00, 0x602a, 0x70a0,
+	0xa005, 0x1118, 0x6887, 0x0001, 0x0008, 0x6886, 0xa006, 0x00ee,
+	0x00de, 0x00ce, 0x003e, 0x002e, 0x001e, 0x015e, 0x0005, 0x0156,
+	0x0016, 0x0026, 0x0036, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100,
+	0x2071, 0xb100, 0x2069, 0x0140, 0x6020, 0xa084, 0x00c0, 0x0120,
+	0x6884, 0xa005, 0x1904, 0x5a2b, 0x6803, 0x0088, 0x60e3, 0x0000,
+	0x6887, 0x0000, 0x2001, 0x0000, 0x080c, 0x274b, 0x2069, 0x0200,
+	0x6804, 0xa005, 0x1118, 0x6808, 0xa005, 0x01c0, 0x6028, 0xa084,
+	0xfbff, 0x602a, 0x6027, 0x0400, 0x2069, 0xb3be, 0x7000, 0x206a,
+	0x708b, 0x0026, 0x7003, 0x0001, 0x20a9, 0x0002, 0x1d04, 0x5a0e,
+	0x2091, 0x6000, 0x1f04, 0x5a0e, 0x0804, 0x5a5c, 0x2069, 0x0140,
+	0x20a9, 0x0384, 0x6027, 0x1e00, 0x2009, 0x1e00, 0xe000, 0x6024,
+	0xa10c, 0x0530, 0xa084, 0x1a00, 0x1518, 0x1d04, 0x5a1a, 0x2091,
+	0x6000, 0x1f04, 0x5a1a, 0x2011, 0x0003, 0x080c, 0x7d52, 0x2011,
+	0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41, 0x080c, 0x67b6, 0x2019,
+	0x0000, 0x080c, 0x7cc4, 0x6803, 0x00a0, 0x2001, 0xb39f, 0x2003,
+	0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0xa085, 0x0001, 0x00a0,
+	0x6803, 0x0080, 0x2069, 0x0140, 0x60e3, 0x0000, 0x70a0, 0xa005,
+	0x1118, 0x6887, 0x0001, 0x0008, 0x6886, 0x2001, 0xb38f, 0x2004,
+	0x080c, 0x274b, 0x60e2, 0xa006, 0x00ee, 0x00de, 0x00ce, 0x003e,
+	0x002e, 0x001e, 0x015e, 0x0005, 0x0156, 0x0016, 0x0026, 0x0036,
+	0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100, 0x2071, 0xb100, 0x6020,
+	0xa084, 0x00c0, 0x01f0, 0x2011, 0x0003, 0x080c, 0x7d52, 0x2011,
+	0x0002, 0x080c, 0x7d5c, 0x080c, 0x7c41, 0x080c, 0x67b6, 0x2019,
+	0x0000, 0x080c, 0x7cc4, 0x2069, 0x0140, 0x6803, 0x00a0, 0x2001,
+	0xb39f, 0x2003, 0x0001, 0x2001, 0xb100, 0x2003, 0x0001, 0x0804,
+	0x5afc, 0x2001, 0xb10c, 0x200c, 0xd1b4, 0x1150, 0xc1b5, 0x2102,
+	0x080c, 0x57df, 0x2069, 0x0140, 0x6803, 0x0080, 0x60e3, 0x0000,
+	0x2069, 0x0200, 0x6804, 0xa005, 0x1118, 0x6808, 0xa005, 0x01b8,
+	0x6028, 0xa084, 0xfdff, 0x602a, 0x6027, 0x0200, 0x2069, 0xb3be,
+	0x7000, 0x206a, 0x708b, 0x0027, 0x7003, 0x0001, 0x20a9, 0x0002,
+	0x1d04, 0x5ab8, 0x2091, 0x6000, 0x1f04, 0x5ab8, 0x04e8, 0x6027,
+	0x1e00, 0x2009, 0x1e00, 0xe000, 0x6024, 0xa10c, 0x01c8, 0xa084,
+	0x1c00, 0x11b0, 0x1d04, 0x5abf, 0x0006, 0x0016, 0x00c6, 0x00d6,
+	0x00e6, 0x080c, 0x66b4, 0x00ee, 0x00de, 0x00ce, 0x001e, 0x000e,
+	0x00e6, 0x2071, 0xb3ec, 0x7018, 0x00ee, 0xa005, 0x1d00, 0x01e0,
+	0x0026, 0x2011, 0x57ea, 0x080c, 0x6742, 0x002e, 0x2069, 0x0140,
+	0x60e3, 0x0000, 0x70a0, 0xa005, 0x1118, 0x6887, 0x0001, 0x0008,
+	0x6886, 0x2001, 0xb38f, 0x2004, 0x080c, 0x274b, 0x60e2, 0x2001,
+	0xb10c, 0x200c, 0xc1b4, 0x2102, 0x00ee, 0x00de, 0x00ce, 0x003e,
+	0x002e, 0x001e, 0x015e, 0x0005, 0x0156, 0x0016, 0x0026, 0x0036,
+	0x0046, 0x00c6, 0x00e6, 0x2061, 0x0100, 0x2071, 0xb100, 0x7130,
+	0xd184, 0x1180, 0x2011, 0xb153, 0x2214, 0xd2ec, 0x0138, 0xc18d,
+	0x7132, 0x2011, 0xb153, 0x2214, 0xd2ac, 0x1120, 0x7030, 0xd08c,
+	0x0904, 0x5b69, 0x7130, 0xc185, 0x7132, 0x2011, 0xb153, 0x220c,
+	0xd1a4, 0x0530, 0x0016, 0x2009, 0x0001, 0x2011, 0x0100, 0x080c,
+	0x688d, 0x2019, 0x000e, 0x080c, 0xac2b, 0x0156, 0x20a9, 0x007f,
+	0x2009, 0x0000, 0xa186, 0x007e, 0x0170, 0xa186, 0x0080, 0x0158,
+	0x080c, 0x4e21, 0x1140, 0x8127, 0xa006, 0x0016, 0x2009, 0x000e,
+	0x080c, 0xacae, 0x001e, 0x8108, 0x1f04, 0x5b3a, 0x015e, 0x001e,
+	0xd1ac, 0x1148, 0x0016, 0x2009, 0x0000, 0x2019, 0x0004, 0x080c,
+	0x2b46, 0x001e, 0x0070, 0x0156, 0x20a9, 0x007f, 0x2009, 0x0000,
+	0x080c, 0x4e21, 0x1110, 0x080c, 0x4a80, 0x8108, 0x1f04, 0x5b60,
+	0x015e, 0x2011, 0x0003, 0x080c, 0x7d52, 0x2011, 0x0002, 0x080c,
+	0x7d5c, 0x080c, 0x7c41, 0x080c, 0x67b6, 0x0036, 0x2019, 0x0000,
+	0x080c, 0x7cc4, 0x003e, 0x60e3, 0x0000, 0x2001, 0xb100, 0x2003,
+	0x0001, 0x080c, 0x5816, 0x00ee, 0x00ce, 0x004e, 0x003e, 0x002e,
+	0x001e, 0x015e, 0x0005, 0x2071, 0xb1e2, 0x7003, 0x0000, 0x7007,
+	0x0000, 0x700f, 0x0000, 0x702b, 0x0001, 0x704f, 0x0000, 0x7053,
+	0x0001, 0x705f, 0x0020, 0x7063, 0x0040, 0x7083, 0x0000, 0x708b,
+	0x0000, 0x708f, 0x0001, 0x70bf, 0x0000, 0x0005, 0x00e6, 0x2071,
+	0xb1e2, 0x6848, 0xa005, 0x1130, 0x7028, 0xc085, 0x702a, 0xa085,
+	0x0001, 0x0428, 0x6a50, 0x7236, 0x6b54, 0x733a, 0x6858, 0x703e,
+	0x707a, 0x685c, 0x7042, 0x707e, 0x6848, 0x702e, 0x6840, 0x7032,
+	0x2009, 0x000c, 0x200a, 0x8007, 0x8006, 0x8006, 0xa08c, 0x003f,
+	0xa084, 0xffc0, 0xa210, 0x2100, 0xa319, 0x7272, 0x7376, 0x7028,
+	0xc084, 0x702a, 0x7007, 0x0001, 0x700f, 0x0000, 0xa006, 0x00ee,
+	0x0005, 0x2b78, 0x2071, 0xb1e2, 0x7004, 0x0043, 0x700c, 0x0002,
+	0x5be5, 0x5bdc, 0x5bdc, 0x5bdc, 0x5bdc, 0x0005, 0x5c3b, 0x5c3c,
+	0x5c6e, 0x5c6f, 0x5c39, 0x5cbd, 0x5cc2, 0x5cf3, 0x5cf4, 0x5d0f,
+	0x5d10, 0x5d11, 0x5d12, 0x5d13, 0x5d14, 0x5dca, 0x5df1, 0x700c,
+	0x0002, 0x5bfe, 0x5c39, 0x5c39, 0x5c3a, 0x5c3a, 0x7830, 0x7930,
+	0xa106, 0x0120, 0x7830, 0x7930, 0xa106, 0x1510, 0x7030, 0xa10a,
+	0x01f8, 0x1210, 0x712c, 0xa10a, 0xa18a, 0x0002, 0x12d0, 0x080c,
+	0x15c4, 0x01b0, 0x2d00, 0x705a, 0x7063, 0x0040, 0x2001, 0x0003,
+	0x7057, 0x0000, 0x0126, 0x0006, 0x2091, 0x8000, 0x2009, 0xb408,
+	0x2104, 0xc085, 0x200a, 0x000e, 0x700e, 0x012e, 0x080c, 0x1640,
+	0x0005, 0x080c, 0x15c4, 0x0de0, 0x2d00, 0x705a, 0x080c, 0x15c4,
+	0x1108, 0x0c10, 0x2d00, 0x7086, 0x7063, 0x0080, 0x2001, 0x0004,
+	0x08f8, 0x0005, 0x0005, 0x0005, 0x700c, 0x0002, 0x5c43, 0x5c46,
+	0x5c54, 0x5c6d, 0x5c6d, 0x080c, 0x5bf7, 0x0005, 0x0126, 0x8001,
+	0x700e, 0x7058, 0x0006, 0x080c, 0x611c, 0x0120, 0x2091, 0x8000,
+	0x080c, 0x5bf7, 0x00de, 0x0048, 0x0126, 0x8001, 0x700e, 0x080c,
+	0x611c, 0x7058, 0x2068, 0x7084, 0x705a, 0x6803, 0x0000, 0x6807,
+	0x0000, 0x6834, 0xa084, 0x00ff, 0xa08a, 0x003a, 0x1218, 0x00db,
+	0x012e, 0x0005, 0x012e, 0x080c, 0x5d15, 0x0005, 0x0005, 0x0005,
+	0x00e6, 0x2071, 0xb1e2, 0x700c, 0x0002, 0x5c7a, 0x5c7a, 0x5c7a,
+	0x5c7c, 0x5c7f, 0x00ee, 0x0005, 0x700f, 0x0001, 0x0010, 0x700f,
+	0x0002, 0x00ee, 0x0005, 0x5d15, 0x5d15, 0x5d31, 0x5d15, 0x5eae,
+	0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d31, 0x5ef0, 0x5f33,
+	0x5f7c, 0x5f90, 0x5d15, 0x5d15, 0x5d4d, 0x5d31, 0x5d15, 0x5d15,
+	0x5da7, 0x6039, 0x6054, 0x5d15, 0x5d4d, 0x5d15, 0x5d15, 0x5d15,
+	0x5d15, 0x5d9d, 0x6054, 0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d15,
+	0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d61, 0x5d15, 0x5d15, 0x5d15,
+	0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x613a, 0x5d15,
+	0x5d15, 0x5d15, 0x5d15, 0x5d15, 0x5d76, 0x7020, 0x2068, 0x080c,
+	0x15f4, 0x0005, 0x700c, 0x0002, 0x5cc9, 0x5ccc, 0x5cda, 0x5cf2,
+	0x5cf2, 0x080c, 0x5bf7, 0x0005, 0x0126, 0x8001, 0x700e, 0x7058,
+	0x0006, 0x080c, 0x611c, 0x0120, 0x2091, 0x8000, 0x080c, 0x5bf7,
+	0x00de, 0x0048, 0x0126, 0x8001, 0x700e, 0x080c, 0x611c, 0x7058,
+	0x2068, 0x7084, 0x705a, 0x6803, 0x0000, 0x6807, 0x0000, 0x6834,
+	0xa084, 0x00ff, 0xa08a, 0x001a, 0x1218, 0x003b, 0x012e, 0x0005,
+	0x012e, 0x0419, 0x0005, 0x0005, 0x0005, 0x5d15, 0x5d31, 0x5e9a,
+	0x5d15, 0x5d31, 0x5d15, 0x5d31, 0x5d31, 0x5d15, 0x5d31, 0x5e9a,
+	0x5d31, 0x5d31, 0x5d31, 0x5d31, 0x5d31, 0x5d15, 0x5d31, 0x5e9a,
+	0x5d15, 0x5d15, 0x5d31, 0x5d15, 0x5d15, 0x5d15, 0x5d31, 0x0005,
+	0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x7007, 0x0001, 0x6838,
+	0xa084, 0x00ff, 0xc0d5, 0x683a, 0x0126, 0x2091, 0x8000, 0x080c,
+	0x5271, 0x012e, 0x0005, 0x7007, 0x0001, 0x6838, 0xa084, 0x00ff,
+	0xc0e5, 0x683a, 0x0126, 0x2091, 0x8000, 0x080c, 0x5271, 0x012e,
+	0x0005, 0x7007, 0x0001, 0x6838, 0xa084, 0x00ff, 0xc0ed, 0x683a,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x5271, 0x012e, 0x0005, 0x7007,
+	0x0001, 0x6838, 0xa084, 0x00ff, 0xc0dd, 0x683a, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x5271, 0x012e, 0x0005, 0x6834, 0x8007, 0xa084,
+	0x00ff, 0x0988, 0x8001, 0x1120, 0x7007, 0x0001, 0x0804, 0x5e5a,
+	0x7007, 0x0006, 0x7012, 0x2d00, 0x7016, 0x701a, 0x704b, 0x5e5a,
+	0x0005, 0x6834, 0x8007, 0xa084, 0x00ff, 0x0904, 0x5d23, 0x8001,
+	0x1120, 0x7007, 0x0001, 0x0804, 0x5e77, 0x7007, 0x0006, 0x7012,
+	0x2d00, 0x7016, 0x701a, 0x704b, 0x5e77, 0x0005, 0x6834, 0x8007,
+	0xa084, 0x00ff, 0xa086, 0x0001, 0x1904, 0x5d23, 0x7007, 0x0001,
+	0x2009, 0xb130, 0x210c, 0x81ff, 0x11a8, 0x6838, 0xa084, 0x00ff,
+	0x683a, 0x6853, 0x0000, 0x080c, 0x4bf7, 0x1108, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x6837, 0x0139, 0x684a, 0x6952, 0x080c, 0x5271,
+	0x012e, 0x0ca0, 0x2001, 0x0028, 0x0c90, 0x684c, 0xa084, 0x00c0,
+	0xa086, 0x00c0, 0x1120, 0x7007, 0x0001, 0x0804, 0x606c, 0x2d00,
+	0x7016, 0x701a, 0x20a9, 0x0004, 0xa080, 0x0024, 0x2098, 0x20a1,
+	0xb20d, 0x53a3, 0x6858, 0x7012, 0xa082, 0x0401, 0x1a04, 0x5d3f,
+	0x6a84, 0xa28a, 0x0002, 0x1a04, 0x5d3f, 0x82ff, 0x1138, 0x6888,
+	0x698c, 0xa105, 0x0118, 0x2001, 0x5e2d, 0x0018, 0xa280, 0x5e23,
+	0x2005, 0x70c6, 0x7010, 0xa015, 0x0904, 0x5e0f, 0x080c, 0x15c4,
+	0x1118, 0x7007, 0x000f, 0x0005, 0x2d00, 0x7022, 0x70c4, 0x2060,
+	0x2c05, 0x6836, 0xe004, 0xad00, 0x7096, 0xe008, 0xa20a, 0x1210,
+	0xa00e, 0x2200, 0x7112, 0xe20c, 0x8003, 0x800b, 0xa296, 0x0004,
+	0x0108, 0xa108, 0x719a, 0x810b, 0x719e, 0xae90, 0x0022, 0x080c,
+	0x1628, 0x7090, 0xa08e, 0x0100, 0x0170, 0xa086, 0x0200, 0x0118,
+	0x7007, 0x0010, 0x0005, 0x7020, 0x2068, 0x080c, 0x15f4, 0x7014,
+	0x2068, 0x0804, 0x5d3f, 0x7020, 0x2068, 0x7018, 0x6802, 0x6807,
+	0x0000, 0x2d08, 0x2068, 0x6906, 0x711a, 0x0804, 0x5dca, 0x7014,
+	0x2068, 0x7007, 0x0001, 0x6884, 0xa005, 0x1128, 0x6888, 0x698c,
+	0xa105, 0x0108, 0x00b1, 0x6834, 0xa084, 0x00ff, 0xa086, 0x001e,
+	0x0904, 0x606c, 0x04b8, 0x5e25, 0x5e29, 0x0002, 0x0011, 0x0007,
+	0x0004, 0x000a, 0x000f, 0x0005, 0x0006, 0x000a, 0x0011, 0x0005,
+	0x0004, 0x00f6, 0x00e6, 0x00c6, 0x0076, 0x0066, 0x6f88, 0x6e8c,
+	0x6804, 0x2060, 0xacf0, 0x0021, 0xacf8, 0x0027, 0x2009, 0x0005,
+	0x700c, 0x7816, 0x7008, 0x7812, 0x7004, 0x7806, 0x7000, 0x7802,
+	0x7e0e, 0x7f0a, 0x8109, 0x0128, 0xaef2, 0x0004, 0xaffa, 0x0006,
+	0x0c78, 0x6004, 0xa065, 0x1d30, 0x006e, 0x007e, 0x00ce, 0x00ee,
+	0x00fe, 0x0005, 0x2009, 0xb130, 0x210c, 0x81ff, 0x1198, 0x6838,
+	0xa084, 0x00ff, 0x683a, 0x080c, 0x4ad9, 0x1108, 0x0005, 0x080c,
+	0x5344, 0x0126, 0x2091, 0x8000, 0x080c, 0x9ada, 0x080c, 0x5271,
+	0x012e, 0x0ca0, 0x2001, 0x0028, 0x2009, 0x0000, 0x0c80, 0x2009,
+	0xb130, 0x210c, 0x81ff, 0x11b0, 0x6858, 0xa005, 0x01c0, 0x6838,
+	0xa084, 0x00ff, 0x683a, 0x6853, 0x0000, 0x080c, 0x4b9b, 0x1108,
+	0x0005, 0x0126, 0x2091, 0x8000, 0x684a, 0x6952, 0x080c, 0x5271,
+	0x012e, 0x0cb0, 0x2001, 0x0028, 0x2009, 0x0000, 0x0c90, 0x2001,
+	0x0000, 0x0c78, 0x7018, 0x6802, 0x2d08, 0x2068, 0x6906, 0x711a,
+	0x7010, 0x8001, 0x7012, 0x0118, 0x7007, 0x0006, 0x0030, 0x7014,
+	0x2068, 0x7007, 0x0001, 0x7048, 0x080f, 0x0005, 0x7007, 0x0001,
+	0x6944, 0x810f, 0xa18c, 0x00ff, 0x6848, 0xa084, 0x00ff, 0x20a9,
+	0x0001, 0xa096, 0x0001, 0x01b0, 0x2009, 0x0000, 0x20a9, 0x00ff,
+	0xa096, 0x0002, 0x0178, 0xa005, 0x11f0, 0x6944, 0x810f, 0xa18c,
+	0x00ff, 0x080c, 0x4e21, 0x11b8, 0x0066, 0x6e50, 0x080c, 0x4f1c,
+	0x006e, 0x0088, 0x0046, 0x2011, 0xb10c, 0x2224, 0xc484, 0x2412,
+	0x004e, 0x00c6, 0x080c, 0x4e21, 0x1110, 0x080c, 0x507b, 0x8108,
+	0x1f04, 0x5eda, 0x00ce, 0x684c, 0xd084, 0x1118, 0x080c, 0x15f4,
+	0x0005, 0x0126, 0x2091, 0x8000, 0x080c, 0x5271, 0x012e, 0x0005,
+	0x0126, 0x2091, 0x8000, 0x7007, 0x0001, 0x2001, 0xb153, 0x2004,
+	0xd0a4, 0x0580, 0x2061, 0xb464, 0x6100, 0xd184, 0x0178, 0x6858,
+	0xa084, 0x00ff, 0x1550, 0x6000, 0xd084, 0x0520, 0x6004, 0xa005,
+	0x1538, 0x6003, 0x0000, 0x600b, 0x0000, 0x00c8, 0x2011, 0x0001,
+	0x6860, 0xa005, 0x1110, 0x2001, 0x001e, 0x8000, 0x6016, 0x6858,
+	0xa084, 0x00ff, 0x0178, 0x6006, 0x6858, 0x8007, 0xa084, 0x00ff,
+	0x0148, 0x600a, 0x6858, 0x8000, 0x1108, 0xc28d, 0x6202, 0x012e,
+	0x0804, 0x610b, 0x012e, 0x0804, 0x6105, 0x012e, 0x0804, 0x60ff,
+	0x012e, 0x0804, 0x6102, 0x0126, 0x2091, 0x8000, 0x7007, 0x0001,
+	0x2001, 0xb153, 0x2004, 0xd0a4, 0x05e0, 0x2061, 0xb464, 0x6000,
+	0xd084, 0x05b8, 0x6204, 0x6308, 0xd08c, 0x1530, 0x6c48, 0xa484,
+	0x0003, 0x0170, 0x6958, 0xa18c, 0x00ff, 0x8001, 0x1120, 0x2100,
+	0xa210, 0x0620, 0x0028, 0x8001, 0x1508, 0x2100, 0xa212, 0x02f0,
+	0xa484, 0x000c, 0x0188, 0x6958, 0x810f, 0xa18c, 0x00ff, 0xa082,
+	0x0004, 0x1120, 0x2100, 0xa318, 0x0288, 0x0030, 0xa082, 0x0004,
+	0x1168, 0x2100, 0xa31a, 0x0250, 0x6860, 0xa005, 0x0110, 0x8000,
+	0x6016, 0x6206, 0x630a, 0x012e, 0x0804, 0x610b, 0x012e, 0x0804,
+	0x6108, 0x012e, 0x0804, 0x6105, 0x0126, 0x2091, 0x8000, 0x7007,
+	0x0001, 0x2061, 0xb464, 0x6300, 0xd38c, 0x1120, 0x6308, 0x8318,
+	0x0220, 0x630a, 0x012e, 0x0804, 0x6119, 0x012e, 0x0804, 0x6108,
+	0x0126, 0x00c6, 0x2091, 0x8000, 0x7007, 0x0001, 0x684c, 0xd0ac,
+	0x0148, 0x00c6, 0x2061, 0xb464, 0x6000, 0xa084, 0xfcff, 0x6002,
+	0x00ce, 0x0448, 0x6858, 0xa005, 0x05d0, 0x685c, 0xa065, 0x0598,
+	0x2001, 0xb130, 0x2004, 0xa005, 0x0118, 0x080c, 0x9a2b, 0x0068,
+	0x6013, 0x0400, 0x6057, 0x0000, 0x694c, 0xd1a4, 0x0110, 0x6950,
+	0x6156, 0x2009, 0x0041, 0x080c, 0x831a, 0x6958, 0xa18c, 0xff00,
+	0xa186, 0x2000, 0x1140, 0x0026, 0x2009, 0x0000, 0x2011, 0xfdff,
+	0x080c, 0x688d, 0x002e, 0x684c, 0xd0c4, 0x0148, 0x2061, 0xb464,
+	0x6000, 0xd08c, 0x1120, 0x6008, 0x8000, 0x0208, 0x600a, 0x00ce,
+	0x012e, 0x0804, 0x610b, 0x00ce, 0x012e, 0x0804, 0x6105, 0x6954,
+	0xa186, 0x002e, 0x0d40, 0xa186, 0x002d, 0x0d28, 0xa186, 0x0045,
+	0x0510, 0xa186, 0x002a, 0x1130, 0x2001, 0xb10c, 0x200c, 0xc194,
+	0x2102, 0x08c8, 0xa186, 0x0020, 0x0170, 0xa186, 0x0029, 0x1d18,
+	0x6944, 0xa18c, 0xff00, 0x810f, 0x080c, 0x4e21, 0x1960, 0x6000,
+	0xc0e4, 0x6002, 0x0840, 0x685c, 0xa065, 0x09a8, 0x2001, 0xb3b5,
+	0x2004, 0x6016, 0x0800, 0x685c, 0xa065, 0x0968, 0x00e6, 0x6860,
+	0xa075, 0x2001, 0xb130, 0x2004, 0xa005, 0x0150, 0x080c, 0x9a2b,
+	0x8eff, 0x0118, 0x2e60, 0x080c, 0x9a2b, 0x00ee, 0x0804, 0x5fcb,
+	0x6020, 0xc0dc, 0xc0d5, 0x6022, 0x2e60, 0x6007, 0x003a, 0x6870,
+	0xa005, 0x0130, 0x6007, 0x003b, 0x6874, 0x602a, 0x6878, 0x6012,
+	0x6003, 0x0001, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x00ee, 0x0804,
+	0x5fcb, 0x2061, 0xb464, 0x6000, 0xd084, 0x0190, 0xd08c, 0x1904,
+	0x6119, 0x0126, 0x2091, 0x8000, 0x6204, 0x8210, 0x0220, 0x6206,
+	0x012e, 0x0804, 0x6119, 0x012e, 0x6853, 0x0016, 0x0804, 0x6112,
+	0x6853, 0x0007, 0x0804, 0x6112, 0x6834, 0x8007, 0xa084, 0x00ff,
+	0x1118, 0x080c, 0x5d23, 0x0078, 0x2030, 0x8001, 0x1120, 0x7007,
+	0x0001, 0x0051, 0x0040, 0x7007, 0x0006, 0x7012, 0x2d00, 0x7016,
+	0x701a, 0x704b, 0x606c, 0x0005, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x2009, 0xb130, 0x210c, 0x81ff, 0x1904, 0x60e7, 0x2009, 0xb10c,
+	0x210c, 0xd194, 0x1904, 0x60ef, 0x6848, 0x2070, 0xae82, 0xb800,
+	0x0a04, 0x60db, 0x2001, 0xb116, 0x2004, 0xae02, 0x1a04, 0x60db,
+	0x2061, 0xb464, 0x6100, 0xa184, 0x0301, 0xa086, 0x0001, 0x15a8,
+	0x711c, 0xa186, 0x0006, 0x15b0, 0x7018, 0xa005, 0x0904, 0x60e7,
+	0x2004, 0xd0e4, 0x1904, 0x60ea, 0x7020, 0xd0dc, 0x1904, 0x60f2,
+	0x6853, 0x0000, 0x6803, 0x0000, 0x2d08, 0x7010, 0xa005, 0x1158,
+	0x7112, 0x684c, 0xd0f4, 0x1904, 0x60f5, 0x2e60, 0x080c, 0x67f8,
+	0x012e, 0x00ee, 0x0005, 0x2068, 0x6800, 0xa005, 0x1de0, 0x6902,
+	0x2168, 0x684c, 0xd0f4, 0x15c8, 0x012e, 0x00ee, 0x0005, 0x012e,
+	0x00ee, 0x6853, 0x0006, 0x0804, 0x6112, 0xd184, 0x0dc0, 0xd1c4,
+	0x11a8, 0x00b8, 0x6944, 0xa18c, 0xff00, 0x810f, 0x080c, 0x4e21,
+	0x11c8, 0x6000, 0xd0e4, 0x11b0, 0x711c, 0xa186, 0x0007, 0x1118,
+	0x6853, 0x0002, 0x0088, 0x6853, 0x0008, 0x0070, 0x6853, 0x000e,
+	0x0058, 0x6853, 0x0017, 0x0040, 0x6853, 0x0035, 0x0028, 0x6853,
+	0x0028, 0x0010, 0x6853, 0x0029, 0x012e, 0x00ee, 0x0418, 0x6853,
+	0x002a, 0x0cd0, 0x6853, 0x0045, 0x0cb8, 0x2e60, 0x2019, 0x0002,
+	0x6017, 0x0014, 0x080c, 0xa8af, 0x012e, 0x00ee, 0x0005, 0x2009,
+	0x003e, 0x0058, 0x2009, 0x0004, 0x0040, 0x2009, 0x0006, 0x0028,
+	0x2009, 0x0016, 0x0010, 0x2009, 0x0001, 0x6854, 0xa084, 0xff00,
+	0xa105, 0x6856, 0x0126, 0x2091, 0x8000, 0x080c, 0x5271, 0x012e,
+	0x0005, 0x080c, 0x15f4, 0x0005, 0x702c, 0x7130, 0x8108, 0xa102,
+	0x0230, 0xa00e, 0x7034, 0x7072, 0x7038, 0x7076, 0x0058, 0x7070,
+	0xa080, 0x0040, 0x7072, 0x1230, 0x7074, 0xa081, 0x0000, 0x7076,
+	0xa085, 0x0001, 0x7932, 0x7132, 0x0005, 0x00d6, 0x080c, 0x67ef,
+	0x00de, 0x0005, 0x00d6, 0x00c6, 0x0036, 0x0026, 0x0016, 0x7007,
+	0x0001, 0x6a44, 0xa282, 0x0004, 0x1a04, 0x6185, 0xd284, 0x0170,
+	0x6a4c, 0xa290, 0xb235, 0x2204, 0xa065, 0x6004, 0x05e0, 0x8007,
+	0xa084, 0x00ff, 0xa084, 0x0006, 0x1108, 0x04a8, 0x2c10, 0x080c,
+	0x8295, 0x1118, 0x080c, 0x9ae4, 0x05a0, 0x621a, 0x6844, 0x0002,
+	0x6164, 0x6169, 0x616c, 0x6172, 0x2019, 0x0002, 0x080c, 0xac2b,
+	0x0060, 0x080c, 0xabc2, 0x0048, 0x2019, 0x0002, 0x6950, 0x080c,
+	0xabdd, 0x0018, 0x6950, 0x080c, 0xabc2, 0x080c, 0x82eb, 0x6857,
+	0x0000, 0x0126, 0x2091, 0x8000, 0x080c, 0x5271, 0x012e, 0x001e,
+	0x002e, 0x003e, 0x00ce, 0x00de, 0x0005, 0x6857, 0x0006, 0x0c88,
+	0x6857, 0x0002, 0x0c70, 0x6857, 0x0005, 0x0c58, 0x6857, 0x0004,
+	0x0c40, 0x6857, 0x0007, 0x0c28, 0x00d6, 0x2011, 0x0004, 0x2204,
+	0xa085, 0x8002, 0x2012, 0x00de, 0x0005, 0x20e1, 0x0002, 0x3d08,
+	0x20e1, 0x2000, 0x3d00, 0xa084, 0x7000, 0x0118, 0xa086, 0x1000,
+	0x1570, 0x20e1, 0x0000, 0x3d00, 0xa094, 0xff00, 0x8217, 0xa084,
+	0xf000, 0xa086, 0x3000, 0x1160, 0xa184, 0xff00, 0x8007, 0xa086,
+	0x0008, 0x11e8, 0x080c, 0x2c87, 0x11d0, 0x080c, 0x63bf, 0x0098,
+	0x20e1, 0x0004, 0x3d60, 0xd1bc, 0x1108, 0x3e60, 0xac84, 0x0007,
+	0x1170, 0xac82, 0xb800, 0x0258, 0x6858, 0xac02, 0x1240, 0x2009,
+	0x0047, 0x080c, 0x831a, 0x7a1c, 0xd284, 0x1938, 0x0005, 0xa016,
+	0x080c, 0x1828, 0x0cc0, 0x0cd8, 0x781c, 0xd08c, 0x0500, 0x0156,
+	0x0136, 0x0146, 0x20e1, 0x3000, 0x3d20, 0x3e28, 0xa584, 0x0076,
+	0x1530, 0xa484, 0x7000, 0xa086, 0x1000, 0x11a8, 0x080c, 0x623a,
+	0x01f0, 0x20e1, 0x3000, 0x7828, 0x7828, 0x080c, 0x6256, 0x014e,
+	0x013e, 0x015e, 0x2009, 0xb3e1, 0x2104, 0xa005, 0x1108, 0x0005,
+	0x080c, 0x6e9e, 0x0ce0, 0xa484, 0x7000, 0x1518, 0x0499, 0x01b8,
+	0x7000, 0xa084, 0xff00, 0xa086, 0x8100, 0x0d18, 0x0080, 0xd5a4,
+	0x0158, 0x080c, 0x1db4, 0x20e1, 0x9010, 0x2001, 0x0160, 0x2502,
+	0x2001, 0x0138, 0x2202, 0x0048, 0x00e9, 0x6883, 0x0000, 0x080c,
+	0xafa5, 0x20e1, 0x3000, 0x7828, 0x7828, 0x014e, 0x013e, 0x015e,
+	0x08b0, 0x0081, 0x1130, 0x7000, 0xa084, 0xff00, 0xa086, 0x8100,
+	0x1d70, 0x080c, 0xafa5, 0x20e1, 0x3000, 0x7828, 0x7828, 0x080c,
+	0x6630, 0x0c58, 0xa484, 0x01ff, 0x6882, 0xa005, 0x0160, 0xa080,
+	0x001f, 0xa084, 0x03f8, 0x80ac, 0x20e1, 0x1000, 0x2ea0, 0x2099,
+	0x020a, 0x53a5, 0x0005, 0x20a9, 0x000c, 0x20e1, 0x1000, 0x2ea0,
+	0x2099, 0x020a, 0x53a5, 0xa085, 0x0001, 0x0ca0, 0x7000, 0xa084,
+	0xff00, 0xa08c, 0xf000, 0x8007, 0xa196, 0x0000, 0x1118, 0x0804,
+	0x64c4, 0x0005, 0xa196, 0x2000, 0x1148, 0x6900, 0xa18e, 0x0001,
+	0x1118, 0x080c, 0x4305, 0x0ca8, 0x0039, 0x0c98, 0xa196, 0x8000,
+	0x1d80, 0x080c, 0x6570, 0x0c68, 0x00c6, 0x6a80, 0x82ff, 0x0904,
+	0x63b9, 0x7110, 0xa18c, 0xff00, 0x810f, 0xa196, 0x0001, 0x0120,
+	0xa196, 0x0023, 0x1904, 0x63b9, 0xa08e, 0x0023, 0x1570, 0x080c,
+	0x660b, 0x0904, 0x63b9, 0x7124, 0x610a, 0x7030, 0xa08e, 0x0200,
+	0x1150, 0x7034, 0xa005, 0x1904, 0x63b9, 0x2009, 0x0015, 0x080c,
+	0x831a, 0x0804, 0x63b9, 0xa08e, 0x0214, 0x0118, 0xa08e, 0x0210,
+	0x1130, 0x2009, 0x0015, 0x080c, 0x831a, 0x0804, 0x63b9, 0xa08e,
+	0x0100, 0x1904, 0x63b9, 0x7034, 0xa005, 0x1904, 0x63b9, 0x2009,
+	0x0016, 0x080c, 0x831a, 0x0804, 0x63b9, 0xa08e, 0x0022, 0x1904,
+	0x63b9, 0x7030, 0xa08e, 0x0300, 0x1580, 0x68d0, 0xd0a4, 0x0528,
+	0xc0b5, 0x68d2, 0x7100, 0xa18c, 0x00ff, 0x696e, 0x7004, 0x6872,
+	0x00f6, 0x2079, 0x0100, 0x79e6, 0x78ea, 0x0006, 0xa084, 0x00ff,
+	0x0016, 0x2008, 0x080c, 0x2720, 0x7932, 0x7936, 0x001e, 0x000e,
+	0x00fe, 0x080c, 0x26f6, 0x694e, 0x703c, 0x00e6, 0x2071, 0x0140,
+	0x7086, 0x2071, 0xb100, 0x70a2, 0x00ee, 0x7034, 0xa005, 0x1904,
+	0x63b9, 0x2009, 0x0017, 0x0804, 0x637f, 0xa08e, 0x0400, 0x1158,
+	0x7034, 0xa005, 0x1904, 0x63b9, 0x68d0, 0xc0a5, 0x68d2, 0x2009,
+	0x0030, 0x0804, 0x637f, 0xa08e, 0x0500, 0x1140, 0x7034, 0xa005,
+	0x1904, 0x63b9, 0x2009, 0x0018, 0x0804, 0x637f, 0xa08e, 0x2010,
+	0x1120, 0x2009, 0x0019, 0x0804, 0x637f, 0xa08e, 0x2110, 0x1120,
+	0x2009, 0x001a, 0x0804, 0x637f, 0xa08e, 0x5200, 0x1140, 0x7034,
+	0xa005, 0x1904, 0x63b9, 0x2009, 0x001b, 0x0804, 0x637f, 0xa08e,
+	0x5000, 0x1140, 0x7034, 0xa005, 0x1904, 0x63b9, 0x2009, 0x001c,
+	0x0804, 0x637f, 0xa08e, 0x1300, 0x1120, 0x2009, 0x0034, 0x0804,
+	0x637f, 0xa08e, 0x1200, 0x1140, 0x7034, 0xa005, 0x1904, 0x63b9,
+	0x2009, 0x0024, 0x0804, 0x637f, 0xa08c, 0xff00, 0xa18e, 0x2400,
+	0x1118, 0x2009, 0x002d, 0x04d8, 0xa08c, 0xff00, 0xa18e, 0x5300,
+	0x1118, 0x2009, 0x002a, 0x0498, 0xa08e, 0x0f00, 0x1118, 0x2009,
+	0x0020, 0x0468, 0xa08e, 0x5300, 0x1108, 0x00d8, 0xa08e, 0x6104,
+	0x11c0, 0x2011, 0xb68d, 0x8208, 0x2204, 0xa082, 0x0004, 0x20a8,
+	0x95ac, 0x95ac, 0x2011, 0x8015, 0x211c, 0x8108, 0x0046, 0x2124,
+	0x080c, 0x3d5b, 0x004e, 0x8108, 0x1f04, 0x6362, 0x2009, 0x0023,
+	0x0070, 0xa08e, 0x6000, 0x1118, 0x2009, 0x003f, 0x0040, 0xa08e,
+	0x7800, 0x1118, 0x2009, 0x0045, 0x0010, 0x2009, 0x001d, 0x0016,
+	0x2011, 0xb683, 0x2204, 0x8211, 0x220c, 0x080c, 0x26f6, 0x1598,
+	0x080c, 0x4dc5, 0x1580, 0x6612, 0x6516, 0x86ff, 0x01e8, 0x001e,
+	0x0016, 0xa186, 0x0017, 0x1158, 0x686c, 0xa606, 0x11a8, 0x6870,
+	0xa506, 0xa084, 0xff00, 0x1180, 0x6000, 0xc0f5, 0x6002, 0xa186,
+	0x0046, 0x1150, 0x686c, 0xa606, 0x1138, 0x6870, 0xa506, 0xa084,
+	0xff00, 0x1110, 0x001e, 0x0068, 0x00c6, 0x080c, 0x8295, 0x0168,
+	0x001e, 0x611a, 0x601f, 0x0004, 0x7120, 0x610a, 0x001e, 0x080c,
+	0x831a, 0x00ce, 0x0005, 0x001e, 0x0ce0, 0x00ce, 0x0ce0, 0x00c6,
+	0x0046, 0x080c, 0x6413, 0x1904, 0x6410, 0xa28e, 0x0033, 0x11e8,
+	0x080c, 0x660b, 0x0904, 0x6410, 0x7124, 0x610a, 0x7030, 0xa08e,
+	0x0200, 0x1140, 0x7034, 0xa005, 0x15d8, 0x2009, 0x0015, 0x080c,
+	0x831a, 0x04b0, 0xa08e, 0x0100, 0x1598, 0x7034, 0xa005, 0x1580,
+	0x2009, 0x0016, 0x080c, 0x831a, 0x0458, 0xa28e, 0x0032, 0x1540,
+	0x7030, 0xa08e, 0x1400, 0x1520, 0x2009, 0x0038, 0x0016, 0x2011,
+	0xb683, 0x2204, 0x8211, 0x220c, 0x080c, 0x26f6, 0x11c0, 0x080c,
+	0x4dc5, 0x11a8, 0x6612, 0x6516, 0x00c6, 0x080c, 0x8295, 0x0170,
+	0x001e, 0x611a, 0x080c, 0x9c35, 0x601f, 0x0004, 0x7120, 0x610a,
+	0x001e, 0x080c, 0x831a, 0x080c, 0x6e9e, 0x0010, 0x00ce, 0x001e,
+	0x004e, 0x00ce, 0x0005, 0x00f6, 0x00d6, 0x0026, 0x0016, 0x0136,
+	0x0146, 0x0156, 0x3c00, 0x0006, 0x2079, 0x0030, 0x2069, 0x0200,
+	0x080c, 0x1e48, 0x1590, 0x080c, 0x1d06, 0x05e0, 0x04f1, 0x1130,
+	0x7908, 0xa18c, 0x1fff, 0xa182, 0x0011, 0x1688, 0x20a9, 0x000c,
+	0x20e1, 0x0000, 0x2ea0, 0x2099, 0x020a, 0x53a5, 0x20e1, 0x2000,
+	0x2001, 0x020a, 0x2004, 0x7a0c, 0x7808, 0xa080, 0x0007, 0xa084,
+	0x1ff8, 0x0419, 0x1120, 0xa08a, 0x0140, 0x1a0c, 0x14fa, 0x80ac,
+	0x20e1, 0x6000, 0x2099, 0x020a, 0x53a5, 0x20e1, 0x7000, 0x6828,
+	0x6828, 0x7803, 0x0004, 0xa294, 0x0070, 0x000e, 0x20e0, 0x015e,
+	0x014e, 0x013e, 0x001e, 0x002e, 0x00de, 0x00fe, 0x0005, 0xa016,
+	0x080c, 0x1828, 0xa085, 0x0001, 0x0c80, 0x0006, 0x2001, 0x0111,
+	0x2004, 0xa084, 0x0003, 0x000e, 0x0005, 0x0046, 0x00e6, 0x00d6,
+	0x2028, 0x2130, 0xa696, 0x00ff, 0x1198, 0xa596, 0xfffd, 0x1120,
+	0x2009, 0x007f, 0x0804, 0x64bf, 0xa596, 0xfffe, 0x1118, 0x2009,
+	0x007e, 0x04e8, 0xa596, 0xfffc, 0x1118, 0x2009, 0x0080, 0x04b8,
+	0x2011, 0x0000, 0x2019, 0xb134, 0x231c, 0xd3ac, 0x0138, 0x2021,
+	0x0000, 0x20a9, 0x00ff, 0x2071, 0xb235, 0x0030, 0x2021, 0x0081,
+	0x20a9, 0x007e, 0x2071, 0xb2b6, 0x2e1c, 0x83ff, 0x1128, 0x82ff,
+	0x1198, 0x2410, 0xc2fd, 0x0080, 0x2368, 0x6f10, 0x0006, 0x2100,
+	0xa706, 0x000e, 0x6b14, 0x1120, 0xa346, 0x1110, 0x2408, 0x0078,
+	0x87ff, 0x1110, 0x83ff, 0x0d58, 0x8420, 0x8e70, 0x1f04, 0x649c,
+	0x82ff, 0x1118, 0xa085, 0x0001, 0x0018, 0xc2fc, 0x2208, 0xa006,
+	0x00de, 0x00ee, 0x004e, 0x0005, 0xa084, 0x0007, 0x000a, 0x0005,
+	0x64d0, 0x64d0, 0x64d0, 0x661d, 0x64d0, 0x64d1, 0x64e6, 0x655b,
+	0x0005, 0x7110, 0xd1bc, 0x0188, 0x7120, 0x2160, 0xac8c, 0x0007,
+	0x1160, 0xac8a, 0xb800, 0x0248, 0x6858, 0xac02, 0x1230, 0x7124,
+	0x610a, 0x2009, 0x0046, 0x080c, 0x831a, 0x0005, 0x00c6, 0x7110,
+	0xd1bc, 0x1904, 0x6539, 0x2011, 0xb683, 0x2204, 0x8211, 0x220c,
+	0x080c, 0x26f6, 0x1904, 0x6539, 0x080c, 0x4dc5, 0x1904, 0x6539,
+	0x6612, 0x6516, 0x6000, 0xd0ec, 0x15e0, 0x6204, 0xa294, 0xff00,
+	0x8217, 0xa286, 0x0006, 0x0160, 0x080c, 0x58d5, 0x11d0, 0x6204,
+	0xa294, 0x00ff, 0xa286, 0x0006, 0x11a0, 0xa295, 0x0600, 0x6206,
+	0x00c6, 0x080c, 0x8295, 0x001e, 0x0530, 0x611a, 0x601f, 0x0006,
+	0x7120, 0x610a, 0x7130, 0x6152, 0x2009, 0x0044, 0x080c, 0x831a,
+	0x00c0, 0x00c6, 0x080c, 0x8295, 0x001e, 0x0198, 0x611a, 0x601f,
+	0x0004, 0x7120, 0x610a, 0xa286, 0x0004, 0x1118, 0x6007, 0x0005,
+	0x0010, 0x6007, 0x0001, 0x6003, 0x0001, 0x080c, 0x6a3c, 0x080c,
+	0x6e9e, 0x00ce, 0x0005, 0x2001, 0xb10d, 0x2004, 0xd0ec, 0x0120,
+	0x2011, 0x8049, 0x080c, 0x3d5b, 0x00c6, 0x080c, 0x9ae4, 0x001e,
+	0x0d80, 0x611a, 0x601f, 0x0006, 0x7120, 0x610a, 0x7130, 0x6152,
+	0x6013, 0x0300, 0x6003, 0x0001, 0x6007, 0x0041, 0x080c, 0x69f6,
+	0x080c, 0x6e9e, 0x08f0, 0x7110, 0xd1bc, 0x0188, 0x7020, 0x2060,
+	0xac84, 0x0007, 0x1160, 0xac82, 0xb800, 0x0248, 0x6858, 0xac02,
+	0x1230, 0x7124, 0x610a, 0x2009, 0x0045, 0x080c, 0x831a, 0x0005,
+	0x0006, 0x080c, 0x2c87, 0x000e, 0x1168, 0x7110, 0xa18c, 0xff00,
+	0x810f, 0xa18e, 0x0000, 0x1130, 0xa084, 0x000f, 0xa08a, 0x0006,
+	0x1208, 0x000b, 0x0005, 0x6589, 0x658a, 0x6589, 0x6589, 0x65f3,
+	0x65ff, 0x0005, 0x7110, 0xd1bc, 0x0120, 0x702c, 0xd084, 0x0904,
+	0x65f2, 0x700c, 0x7108, 0x080c, 0x26f6, 0x1904, 0x65f2, 0x080c,
+	0x4dc5, 0x1904, 0x65f2, 0x6612, 0x6516, 0x6204, 0x7110, 0xd1bc,
+	0x01f8, 0xa28c, 0x00ff, 0xa186, 0x0004, 0x0118, 0xa186, 0x0006,
+	0x15c8, 0x00c6, 0x080c, 0x660b, 0x00ce, 0x0904, 0x65f2, 0x00c6,
+	0x080c, 0x8295, 0x001e, 0x05f0, 0x611a, 0x080c, 0x9c35, 0x601f,
+	0x0002, 0x7120, 0x610a, 0x2009, 0x0088, 0x080c, 0x831a, 0x0490,
+	0xa28c, 0x00ff, 0xa186, 0x0006, 0x0160, 0xa186, 0x0004, 0x0148,
+	0xa294, 0xff00, 0x8217, 0xa286, 0x0004, 0x0118, 0xa286, 0x0006,
+	0x1188, 0x00c6, 0x080c, 0x8295, 0x001e, 0x01e0, 0x611a, 0x080c,
+	0x9c35, 0x601f, 0x0005, 0x7120, 0x610a, 0x2009, 0x0088, 0x080c,
+	0x831a, 0x0080, 0x00c6, 0x080c, 0x8295, 0x001e, 0x0158, 0x611a,
+	0x080c, 0x9c35, 0x601f, 0x0004, 0x7120, 0x610a, 0x2009, 0x0001,
+	0x080c, 0x831a, 0x0005, 0x7110, 0xd1bc, 0x0140, 0x00a1, 0x0130,
+	0x7124, 0x610a, 0x2009, 0x0089, 0x080c, 0x831a, 0x0005, 0x7110,
+	0xd1bc, 0x0140, 0x0041, 0x0130, 0x7124, 0x610a, 0x2009, 0x008a,
+	0x080c, 0x831a, 0x0005, 0x7020, 0x2060, 0xac84, 0x0007, 0x1158,
+	0xac82, 0xb800, 0x0240, 0x2001, 0xb116, 0x2004, 0xac02, 0x1218,
+	0xa085, 0x0001, 0x0005, 0xa006, 0x0ce8, 0x7110, 0xd1bc, 0x1178,
+	0x7024, 0x2060, 0xac84, 0x0007, 0x1150, 0xac82, 0xb800, 0x0238,
+	0x6858, 0xac02, 0x1220, 0x2009, 0x0051, 0x080c, 0x831a, 0x0005,
+	0x2031, 0x0105, 0x0069, 0x0005, 0x2031, 0x0206, 0x0049, 0x0005,
+	0x2031, 0x0207, 0x0029, 0x0005, 0x2031, 0x0213, 0x0009, 0x0005,
+	0x00c6, 0x00d6, 0x00f6, 0x7000, 0xa084, 0xf000, 0xa086, 0xc000,
+	0x05b0, 0x080c, 0x8295, 0x0598, 0x0066, 0x00c6, 0x0046, 0x2011,
+	0xb683, 0x2204, 0x8211, 0x220c, 0x080c, 0x26f6, 0x1580, 0x080c,
+	0x4dc5, 0x1568, 0x6612, 0x6516, 0x2c00, 0x004e, 0x00ce, 0x601a,
+	0x080c, 0x9c35, 0x080c, 0x15dd, 0x01f0, 0x2d00, 0x6056, 0x6803,
+	0x0000, 0x6837, 0x0000, 0x6c3a, 0xadf8, 0x000f, 0x20a9, 0x000e,
+	0x2fa0, 0x2e98, 0x53a3, 0x006e, 0x6612, 0x6007, 0x003e, 0x601f,
+	0x0001, 0x6003, 0x0001, 0x080c, 0x6a3c, 0x080c, 0x6e9e, 0x00fe,
+	0x00de, 0x00ce, 0x0005, 0x080c, 0x82eb, 0x006e, 0x0cc0, 0x004e,
+	0x00ce, 0x0cc8, 0x2071, 0xb3ec, 0x7003, 0x0003, 0x700f, 0x0361,
+	0xa006, 0x701a, 0x7012, 0x7017, 0xb800, 0x7007, 0x0000, 0x7026,
+	0x702b, 0x7a99, 0x7032, 0x7037, 0x7af9, 0x703b, 0xffff, 0x703f,
+	0xffff, 0x7042, 0x7047, 0x42c1, 0x704a, 0x705b, 0x67d1, 0x2001,
+	0xb3a0, 0x2003, 0x0003, 0x2001, 0xb3a2, 0x2003, 0x0100, 0x3a00,
+	0xa084, 0x0005, 0x706e, 0x0005, 0x2071, 0xb3ec, 0x1d04, 0x6731,
+	0x2091, 0x6000, 0x700c, 0x8001, 0x700e, 0x1518, 0x700f, 0x0361,
+	0x7007, 0x0001, 0x0126, 0x2091, 0x8000, 0x7040, 0xa00d, 0x0128,
+	0x8109, 0x7142, 0x1110, 0x7044, 0x080f, 0x00c6, 0x2061, 0xb100,
+	0x6034, 0x00ce, 0xd0cc, 0x0180, 0x3a00, 0xa084, 0x0005, 0x726c,
+	0xa216, 0x0150, 0x706e, 0x2011, 0x8043, 0x2018, 0x080c, 0x3d5b,
+	0x0018, 0x0126, 0x2091, 0x8000, 0x7024, 0xa00d, 0x0188, 0x7020,
+	0x8001, 0x7022, 0x1168, 0x7023, 0x0009, 0x8109, 0x7126, 0xa186,
+	0x03e8, 0x1110, 0x7028, 0x080f, 0x81ff, 0x1110, 0x7028, 0x080f,
+	0x7030, 0xa00d, 0x0158, 0x702c, 0x8001, 0x702e, 0x1138, 0x702f,
+	0x0009, 0x8109, 0x7132, 0x1110, 0x7034, 0x080f, 0x7038, 0xa005,
+	0x0118, 0x0310, 0x8001, 0x703a, 0x703c, 0xa005, 0x0118, 0x0310,
+	0x8001, 0x703e, 0x704c, 0xa00d, 0x0168, 0x7048, 0x8001, 0x704a,
+	0x1148, 0x704b, 0x0009, 0x8109, 0x714e, 0x1120, 0x7150, 0x714e,
+	0x7058, 0x080f, 0x7018, 0xa00d, 0x0158, 0x7008, 0x8001, 0x700a,
+	0x1138, 0x700b, 0x0009, 0x8109, 0x711a, 0x1110, 0x701c, 0x080f,
+	0x012e, 0x7004, 0x0002, 0x6757, 0x6758, 0x6770, 0x00e6, 0x2071,
+	0xb3ec, 0x7018, 0xa005, 0x1120, 0x711a, 0x721e, 0x700b, 0x0009,
+	0x00ee, 0x0005, 0x00e6, 0x0006, 0x2071, 0xb3ec, 0x701c, 0xa206,
+	0x1110, 0x701a, 0x701e, 0x000e, 0x00ee, 0x0005, 0x00e6, 0x2071,
+	0xb3ec, 0x6088, 0xa102, 0x0208, 0x618a, 0x00ee, 0x0005, 0x0005,
+	0x7110, 0x080c, 0x4e21, 0x1158, 0x6088, 0x8001, 0x0240, 0x608a,
+	0x1130, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e, 0x012e, 0x8108,
+	0xa182, 0x00ff, 0x0218, 0xa00e, 0x7007, 0x0002, 0x7112, 0x0005,
+	0x7014, 0x2060, 0x0126, 0x2091, 0x8000, 0x603c, 0xa005, 0x0128,
+	0x8001, 0x603e, 0x1110, 0x080c, 0x9b23, 0x6014, 0xa005, 0x0500,
+	0x8001, 0x6016, 0x11e8, 0x611c, 0xa186, 0x0003, 0x0118, 0xa186,
+	0x0006, 0x11a0, 0x6010, 0x2068, 0x6854, 0xa08a, 0x199a, 0x0270,
+	0xa082, 0x1999, 0x6856, 0xa08a, 0x199a, 0x0210, 0x2001, 0x1999,
+	0x8003, 0x800b, 0x810b, 0xa108, 0x6116, 0x0010, 0x080c, 0x9617,
+	0x012e, 0xac88, 0x0018, 0x7116, 0x2001, 0xe800, 0xa102, 0x0220,
+	0x7017, 0xb800, 0x7007, 0x0000, 0x0005, 0x00e6, 0x2071, 0xb3ec,
+	0x7027, 0x07d0, 0x7023, 0x0009, 0x00ee, 0x0005, 0x2001, 0xb3f5,
+	0x2003, 0x0000, 0x0005, 0x00e6, 0x2071, 0xb3ec, 0x7132, 0x702f,
+	0x0009, 0x00ee, 0x0005, 0x2011, 0xb3f8, 0x2013, 0x0000, 0x0005,
+	0x00e6, 0x2071, 0xb3ec, 0x711a, 0x721e, 0x700b, 0x0009, 0x00ee,
+	0x0005, 0x00c6, 0x0026, 0x7054, 0x8000, 0x7056, 0x2061, 0xb3a0,
+	0x6008, 0xa086, 0x0000, 0x0158, 0x7068, 0x6032, 0x7064, 0x602e,
+	0x7060, 0x602a, 0x705c, 0x6026, 0x2c10, 0x080c, 0x1628, 0x002e,
+	0x00ce, 0x0005, 0x00c6, 0x2061, 0xb464, 0x00ce, 0x0005, 0xa184,
+	0x000f, 0x8003, 0x8003, 0x8003, 0xa080, 0xb464, 0x2060, 0x0005,
+	0x6854, 0xa08a, 0x199a, 0x0210, 0x2001, 0x1999, 0xa005, 0x1150,
+	0x00c6, 0x2061, 0xb464, 0x6014, 0x00ce, 0xa005, 0x1138, 0x2001,
+	0x001e, 0x0020, 0xa08e, 0xffff, 0x1108, 0xa006, 0x8003, 0x800b,
+	0x810b, 0xa108, 0x6116, 0x684c, 0xa08c, 0x00c0, 0xa18e, 0x00c0,
+	0x05b0, 0xd0b4, 0x1138, 0xd0bc, 0x1528, 0x2009, 0x0006, 0x080c,
+	0x6868, 0x0005, 0xd0fc, 0x0130, 0xa084, 0x0003, 0x0118, 0xa086,
+	0x0003, 0x15c0, 0x6020, 0xd0d4, 0x0130, 0xc0d4, 0x6022, 0x6860,
+	0x602a, 0x685c, 0x602e, 0x2009, 0xb174, 0x2104, 0xd084, 0x0128,
+	0x2009, 0x0042, 0x080c, 0x831a, 0x0005, 0x2009, 0x0043, 0x080c,
+	0x831a, 0x0005, 0xd0fc, 0x0130, 0xa084, 0x0003, 0x0118, 0xa086,
+	0x0003, 0x11c0, 0x2009, 0x0042, 0x080c, 0x831a, 0x0005, 0xd0fc,
+	0x0150, 0xa084, 0x0003, 0xa08e, 0x0002, 0x0138, 0x2009, 0x0041,
+	0x080c, 0x831a, 0x0005, 0x0051, 0x0ce8, 0x2009, 0x0043, 0x080c,
+	0x831a, 0x0cc0, 0x2009, 0x0004, 0x0019, 0x0005, 0x2009, 0x0001,
+	0x00d6, 0x6010, 0xa0ec, 0xf000, 0x01f0, 0x2068, 0x6952, 0x6800,
+	0x6012, 0xa186, 0x0001, 0x1188, 0x694c, 0xa18c, 0x8100, 0xa18e,
+	0x8100, 0x1158, 0x00c6, 0x2061, 0xb464, 0x6200, 0xd28c, 0x1120,
+	0x6204, 0x8210, 0x0208, 0x6206, 0x00ce, 0x080c, 0x5271, 0x6010,
+	0xa06d, 0x190c, 0x67f8, 0x00de, 0x0005, 0x0156, 0x00c6, 0x2061,
+	0xb464, 0x6000, 0x81ff, 0x0110, 0xa205, 0x0008, 0xa204, 0x6002,
+	0x00ce, 0x015e, 0x0005, 0x6800, 0xd08c, 0x1138, 0x6808, 0xa005,
+	0x0120, 0x8001, 0x680a, 0xa085, 0x0001, 0x0005, 0x20a9, 0x0010,
+	0xa006, 0x8004, 0x8086, 0x818e, 0x1208, 0xa200, 0x1f04, 0x68aa,
+	0x8086, 0x818e, 0x0005, 0x0156, 0x20a9, 0x0010, 0xa005, 0x01b8,
+	0xa11a, 0x12a8, 0x8213, 0x818d, 0x0228, 0xa11a, 0x1220, 0x1f04,
+	0x68ba, 0x0028, 0xa11a, 0x2308, 0x8210, 0x1f04, 0x68ba, 0x0006,
+	0x3200, 0xa084, 0xefff, 0x2080, 0x000e, 0x015e, 0x0005, 0x0006,
+	0x3200, 0xa085, 0x1000, 0x0cb8, 0x0126, 0x2091, 0x2800, 0x2079,
+	0xb3d9, 0x012e, 0x00d6, 0x2069, 0xb3d9, 0x6803, 0x0005, 0x2069,
+	0x0004, 0x2d04, 0xa085, 0x8001, 0x206a, 0x00de, 0x0005, 0x00c6,
+	0x6027, 0x0001, 0x7804, 0xa084, 0x0007, 0x0002, 0x68f8, 0x6919,
+	0x696c, 0x68fe, 0x6919, 0x68f8, 0x68f6, 0x68f6, 0x080c, 0x14fa,
+	0x080c, 0x67b6, 0x080c, 0x6e9e, 0x00ce, 0x0005, 0x62c0, 0x82ff,
+	0x1110, 0x00ce, 0x0005, 0x2011, 0x494f, 0x080c, 0x6742, 0x7828,
+	0xa092, 0x00c8, 0x1228, 0x8000, 0x782a, 0x080c, 0x4989, 0x0c88,
+	0x080c, 0x494f, 0x7807, 0x0003, 0x7827, 0x0000, 0x782b, 0x0000,
+	0x0c40, 0x080c, 0x67b6, 0x3c00, 0x0006, 0x2011, 0x0209, 0x20e1,
+	0x4000, 0x2214, 0x000e, 0x20e0, 0x82ff, 0x0178, 0x62c0, 0x82ff,
+	0x1160, 0x782b, 0x0000, 0x7824, 0xa065, 0x090c, 0x14fa, 0x2009,
+	0x0013, 0x080c, 0x831a, 0x00ce, 0x0005, 0x3900, 0xa082, 0xb51c,
+	0x1210, 0x080c, 0x8000, 0x00c6, 0x7824, 0xa065, 0x090c, 0x14fa,
+	0x7804, 0xa086, 0x0004, 0x0904, 0x69ac, 0x7828, 0xa092, 0x2710,
+	0x1230, 0x8000, 0x782a, 0x00ce, 0x080c, 0x7a7f, 0x0c20, 0x6104,
+	0xa186, 0x0003, 0x1188, 0x00e6, 0x2071, 0xb100, 0x70dc, 0x00ee,
+	0xd08c, 0x0150, 0x00c6, 0x00e6, 0x2061, 0x0100, 0x2071, 0xb100,
+	0x080c, 0x4992, 0x00ee, 0x00ce, 0x080c, 0xafee, 0x2009, 0x0014,
+	0x080c, 0x831a, 0x00ce, 0x0838, 0x2001, 0xb3f5, 0x2003, 0x0000,
+	0x62c0, 0x82ff, 0x1160, 0x782b, 0x0000, 0x7824, 0xa065, 0x090c,
+	0x14fa, 0x2009, 0x0013, 0x080c, 0x836e, 0x00ce, 0x0005, 0x00c6,
+	0x00d6, 0x3900, 0xa082, 0xb51c, 0x1210, 0x080c, 0x8000, 0x7824,
+	0xa005, 0x090c, 0x14fa, 0x781c, 0xa06d, 0x090c, 0x14fa, 0x6800,
+	0xc0dc, 0x6802, 0x7924, 0x2160, 0x080c, 0x82eb, 0x693c, 0x81ff,
+	0x090c, 0x14fa, 0x8109, 0x693e, 0x6854, 0xa015, 0x0110, 0x7a1e,
+	0x0010, 0x7918, 0x791e, 0x7807, 0x0000, 0x7827, 0x0000, 0x00de,
+	0x00ce, 0x080c, 0x6e9e, 0x0888, 0x6104, 0xa186, 0x0002, 0x0128,
+	0xa186, 0x0004, 0x0110, 0x0804, 0x6945, 0x7808, 0xac06, 0x0904,
+	0x6945, 0x080c, 0x6dc1, 0x080c, 0x6a3c, 0x00ce, 0x080c, 0x6e9e,
+	0x0804, 0x6933, 0x00c6, 0x6027, 0x0002, 0x62c8, 0x60c4, 0xa205,
+	0x1178, 0x793c, 0xa1e5, 0x0000, 0x0130, 0x2009, 0x0049, 0x080c,
+	0x831a, 0x00ce, 0x0005, 0x2011, 0xb3f8, 0x2013, 0x0000, 0x0cc8,
+	0x3908, 0xa192, 0xb51c, 0x1210, 0x080c, 0x8000, 0x793c, 0x81ff,
+	0x0d90, 0x793c, 0xa188, 0x0007, 0x210c, 0xa18e, 0x0006, 0x1138,
+	0x6014, 0xa084, 0x0184, 0xa085, 0x0012, 0x6016, 0x0c10, 0x6014,
+	0xa084, 0x0184, 0xa085, 0x0016, 0x6016, 0x08d8, 0x0006, 0x0016,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x600f, 0x0000, 0x2c08, 0x2061,
+	0xb3d9, 0x6020, 0x8000, 0x6022, 0x6010, 0xa005, 0x0148, 0xa080,
+	0x0003, 0x2102, 0x6112, 0x012e, 0x00ce, 0x001e, 0x000e, 0x0005,
+	0x6116, 0x6112, 0x0cc0, 0x00d6, 0x2069, 0xb3d9, 0x6000, 0xd0d4,
+	0x0168, 0x6820, 0x8000, 0x6822, 0xa086, 0x0001, 0x1110, 0x2c00,
+	0x681e, 0x6804, 0xa084, 0x0007, 0x0804, 0x6ea4, 0xc0d5, 0x6002,
+	0x6818, 0xa005, 0x0158, 0x6056, 0x605b, 0x0000, 0x0006, 0x2c00,
+	0x681a, 0x00de, 0x685a, 0x2069, 0xb3d9, 0x0c18, 0x6056, 0x605a,
+	0x2c00, 0x681a, 0x681e, 0x08e8, 0x0006, 0x0016, 0x00c6, 0x0126,
+	0x2091, 0x8000, 0x600f, 0x0000, 0x2c08, 0x2061, 0xb3d9, 0x6020,
+	0x8000, 0x6022, 0x6008, 0xa005, 0x0148, 0xa080, 0x0003, 0x2102,
+	0x610a, 0x012e, 0x00ce, 0x001e, 0x000e, 0x0005, 0x610e, 0x610a,
+	0x0cc0, 0x00c6, 0x600f, 0x0000, 0x2c08, 0x2061, 0xb3d9, 0x6034,
+	0xa005, 0x0130, 0xa080, 0x0003, 0x2102, 0x6136, 0x00ce, 0x0005,
+	0x613a, 0x6136, 0x0cd8, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0076,
+	0x0066, 0x0026, 0x0016, 0x0006, 0x0126, 0x2071, 0xb3d9, 0x7638,
+	0x2660, 0x2678, 0x2091, 0x8000, 0x8cff, 0x0904, 0x6ad7, 0x6018,
+	0xa080, 0x0028, 0x2004, 0xa206, 0x1904, 0x6ad2, 0x87ff, 0x0120,
+	0x6050, 0xa106, 0x1904, 0x6ad2, 0x703c, 0xac06, 0x1170, 0x0036,
+	0x2019, 0x0001, 0x080c, 0x7cc4, 0x7033, 0x0000, 0x703f, 0x0000,
+	0x7043, 0x0000, 0x7047, 0x0000, 0x003e, 0x7038, 0xac36, 0x1110,
+	0x660c, 0x763a, 0x7034, 0xac36, 0x1140, 0x2c00, 0xaf36, 0x0118,
+	0x2f00, 0x7036, 0x0010, 0x7037, 0x0000, 0x660c, 0x0066, 0x2c00,
+	0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000, 0x080c,
+	0x986a, 0x0198, 0x6010, 0x2068, 0x601c, 0xa086, 0x0003, 0x1510,
+	0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c, 0x9ada, 0x080c,
+	0xaf46, 0x080c, 0x5271, 0x080c, 0x9a1f, 0x080c, 0x9a2b, 0x00ce,
+	0x0804, 0x6a7c, 0x2c78, 0x600c, 0x2060, 0x0804, 0x6a7c, 0x012e,
+	0x000e, 0x001e, 0x002e, 0x006e, 0x007e, 0x00ce, 0x00de, 0x00ee,
+	0x00fe, 0x0005, 0x601c, 0xa086, 0x0006, 0x19d0, 0x080c, 0xaf46,
+	0x080c, 0xac5f, 0x0c10, 0x0006, 0x0066, 0x00c6, 0x00d6, 0x00f6,
+	0x2031, 0x0000, 0x0126, 0x2091, 0x8000, 0x2079, 0xb3d9, 0x7838,
+	0xa065, 0x0558, 0x600c, 0x0006, 0x600f, 0x0000, 0x783c, 0xac06,
+	0x1170, 0x0036, 0x2019, 0x0001, 0x080c, 0x7cc4, 0x7833, 0x0000,
+	0x783f, 0x0000, 0x7843, 0x0000, 0x7847, 0x0000, 0x003e, 0x080c,
+	0x986a, 0x0178, 0x6010, 0x2068, 0x601c, 0xa086, 0x0003, 0x11b0,
+	0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c, 0x5271, 0x080c,
+	0x9a1f, 0x080c, 0x9a2b, 0x000e, 0x0898, 0x7e3a, 0x7e36, 0x012e,
+	0x00fe, 0x00de, 0x00ce, 0x006e, 0x000e, 0x0005, 0x601c, 0xa086,
+	0x0006, 0x1d30, 0x080c, 0xac5f, 0x0c60, 0x0016, 0x0026, 0x0086,
+	0x2041, 0x0000, 0x0099, 0x080c, 0x6bf7, 0x008e, 0x002e, 0x001e,
+	0x0005, 0x00f6, 0x0126, 0x2079, 0xb3d9, 0x2091, 0x8000, 0x080c,
+	0x6c84, 0x080c, 0x6cf6, 0x012e, 0x00fe, 0x0005, 0x00f6, 0x00e6,
+	0x00d6, 0x00c6, 0x0066, 0x0016, 0x0006, 0x0126, 0x2091, 0x8000,
+	0x2071, 0xb3d9, 0x7614, 0x2660, 0x2678, 0x8cff, 0x0904, 0x6bd3,
+	0x6018, 0xa080, 0x0028, 0x2004, 0xa206, 0x1904, 0x6bce, 0x88ff,
+	0x0120, 0x6050, 0xa106, 0x1904, 0x6bce, 0x7024, 0xac06, 0x1538,
+	0x2069, 0x0100, 0x68c0, 0xa005, 0x01f0, 0x080c, 0x67b6, 0x080c,
+	0x7a8c, 0x68c3, 0x0000, 0x080c, 0x7f1b, 0x7027, 0x0000, 0x0036,
+	0x2069, 0x0140, 0x6b04, 0xa384, 0x1000, 0x0120, 0x6803, 0x0100,
+	0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0110, 0x6827,
+	0x0001, 0x003e, 0x0020, 0x6003, 0x0009, 0x630a, 0x04b8, 0x7014,
+	0xac36, 0x1110, 0x660c, 0x7616, 0x7010, 0xac36, 0x1140, 0x2c00,
+	0xaf36, 0x0118, 0x2f00, 0x7012, 0x0010, 0x7013, 0x0000, 0x660c,
+	0x0066, 0x2c00, 0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f,
+	0x0000, 0x6010, 0x2068, 0x080c, 0x986a, 0x0188, 0x601c, 0xa086,
+	0x0003, 0x1510, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c,
+	0x9ada, 0x080c, 0xaf46, 0x080c, 0x5271, 0x080c, 0x9a1f, 0x080c,
+	0x9a2b, 0x080c, 0x7dfb, 0x00ce, 0x0804, 0x6b5d, 0x2c78, 0x600c,
+	0x2060, 0x0804, 0x6b5d, 0x012e, 0x000e, 0x001e, 0x006e, 0x00ce,
+	0x00de, 0x00ee, 0x00fe, 0x0005, 0x601c, 0xa086, 0x0006, 0x1128,
+	0x080c, 0xaf46, 0x080c, 0xac5f, 0x0c10, 0x601c, 0xa086, 0x0002,
+	0x1128, 0x6004, 0xa086, 0x0085, 0x0968, 0x08c8, 0x601c, 0xa086,
+	0x0005, 0x19a8, 0x6004, 0xa086, 0x0085, 0x0d50, 0x0880, 0x00c6,
+	0x0006, 0x0126, 0x2091, 0x8000, 0xa280, 0xb235, 0x2004, 0xa065,
+	0x0904, 0x6c80, 0x00f6, 0x00e6, 0x00d6, 0x0066, 0x2071, 0xb3d9,
+	0x6654, 0x7018, 0xac06, 0x1108, 0x761a, 0x701c, 0xac06, 0x1130,
+	0x86ff, 0x1118, 0x7018, 0x701e, 0x0008, 0x761e, 0x6058, 0xa07d,
+	0x0108, 0x7e56, 0xa6ed, 0x0000, 0x0110, 0x2f00, 0x685a, 0x6057,
+	0x0000, 0x605b, 0x0000, 0x6000, 0xc0d4, 0xc0dc, 0x6002, 0x080c,
+	0x4d4c, 0x0904, 0x6c7c, 0x7624, 0x86ff, 0x05e8, 0xa680, 0x0004,
+	0x2004, 0xad06, 0x15c0, 0x00d6, 0x2069, 0x0100, 0x68c0, 0xa005,
+	0x0548, 0x080c, 0x67b6, 0x080c, 0x7a8c, 0x68c3, 0x0000, 0x080c,
+	0x7f1b, 0x7027, 0x0000, 0x0036, 0x2069, 0x0140, 0x6b04, 0xa384,
+	0x1000, 0x0120, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100,
+	0x6824, 0xd084, 0x0110, 0x6827, 0x0001, 0x003e, 0x00de, 0x00c6,
+	0x603c, 0xa005, 0x0110, 0x8001, 0x603e, 0x2660, 0x080c, 0x9a2b,
+	0x00ce, 0x0048, 0x00de, 0x00c6, 0x2660, 0x6003, 0x0009, 0x630a,
+	0x00ce, 0x0804, 0x6c27, 0x8dff, 0x0158, 0x6837, 0x0103, 0x6b4a,
+	0x6847, 0x0000, 0x080c, 0x9ada, 0x080c, 0xaf46, 0x080c, 0x5271,
+	0x080c, 0x7dfb, 0x0804, 0x6c27, 0x006e, 0x00de, 0x00ee, 0x00fe,
+	0x012e, 0x000e, 0x00ce, 0x0005, 0x0006, 0x0066, 0x00c6, 0x00d6,
+	0x2031, 0x0000, 0x7814, 0xa065, 0x0904, 0x6cd6, 0x600c, 0x0006,
+	0x600f, 0x0000, 0x7824, 0xac06, 0x1540, 0x2069, 0x0100, 0x68c0,
+	0xa005, 0x01f0, 0x080c, 0x67b6, 0x080c, 0x7a8c, 0x68c3, 0x0000,
+	0x080c, 0x7f1b, 0x7827, 0x0000, 0x0036, 0x2069, 0x0140, 0x6b04,
+	0xa384, 0x1000, 0x0120, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069,
+	0x0100, 0x6824, 0xd084, 0x0110, 0x6827, 0x0001, 0x003e, 0x0028,
+	0x6003, 0x0009, 0x630a, 0x2c30, 0x00b0, 0x6010, 0x2068, 0x080c,
+	0x986a, 0x0168, 0x601c, 0xa086, 0x0003, 0x11b8, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x080c, 0x5271, 0x080c, 0x9a1f, 0x080c,
+	0x9a2b, 0x080c, 0x7dfb, 0x000e, 0x0804, 0x6c8b, 0x7e16, 0x7e12,
+	0x00de, 0x00ce, 0x006e, 0x000e, 0x0005, 0x601c, 0xa086, 0x0006,
+	0x1118, 0x080c, 0xac5f, 0x0c58, 0x601c, 0xa086, 0x0002, 0x1128,
+	0x6004, 0xa086, 0x0085, 0x09d0, 0x0c10, 0x601c, 0xa086, 0x0005,
+	0x19f0, 0x6004, 0xa086, 0x0085, 0x0d60, 0x08c8, 0x0006, 0x0066,
+	0x00c6, 0x00d6, 0x7818, 0xa065, 0x0904, 0x6d5c, 0x6054, 0x0006,
+	0x6057, 0x0000, 0x605b, 0x0000, 0x6000, 0xc0d4, 0xc0dc, 0x6002,
+	0x080c, 0x4d4c, 0x0904, 0x6d59, 0x7e24, 0x86ff, 0x05e8, 0xa680,
+	0x0004, 0x2004, 0xad06, 0x15c0, 0x00d6, 0x2069, 0x0100, 0x68c0,
+	0xa005, 0x0548, 0x080c, 0x67b6, 0x080c, 0x7a8c, 0x68c3, 0x0000,
+	0x080c, 0x7f1b, 0x7827, 0x0000, 0x0036, 0x2069, 0x0140, 0x6b04,
+	0xa384, 0x1000, 0x0120, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069,
+	0x0100, 0x6824, 0xd084, 0x0110, 0x6827, 0x0001, 0x003e, 0x00de,
+	0x00c6, 0x603c, 0xa005, 0x0110, 0x8001, 0x603e, 0x2660, 0x080c,
+	0x9a2b, 0x00ce, 0x0048, 0x00de, 0x00c6, 0x2660, 0x6003, 0x0009,
+	0x630a, 0x00ce, 0x0804, 0x6d08, 0x8dff, 0x0138, 0x6837, 0x0103,
+	0x6b4a, 0x6847, 0x0000, 0x080c, 0x5271, 0x080c, 0x7dfb, 0x0804,
+	0x6d08, 0x000e, 0x0804, 0x6cfb, 0x781e, 0x781a, 0x00de, 0x00ce,
+	0x006e, 0x000e, 0x0005, 0x00e6, 0x00d6, 0x0066, 0x6000, 0xd0dc,
+	0x0188, 0x604c, 0xa06d, 0x0170, 0x6848, 0xa606, 0x1158, 0x2071,
+	0xb3d9, 0x7024, 0xa035, 0x0130, 0xa080, 0x0004, 0x2004, 0xad06,
+	0x1108, 0x0021, 0x006e, 0x00de, 0x00ee, 0x0005, 0x00f6, 0x2079,
+	0x0100, 0x78c0, 0xa005, 0x1138, 0x00c6, 0x2660, 0x6003, 0x0009,
+	0x630a, 0x00ce, 0x04a0, 0x080c, 0x7a8c, 0x78c3, 0x0000, 0x080c,
+	0x7f1b, 0x7027, 0x0000, 0x0036, 0x2079, 0x0140, 0x7b04, 0xa384,
+	0x1000, 0x0120, 0x7803, 0x0100, 0x7803, 0x0000, 0x2079, 0x0100,
+	0x7824, 0xd084, 0x0110, 0x7827, 0x0001, 0x080c, 0x7f1b, 0x003e,
+	0x080c, 0x4d4c, 0x00c6, 0x603c, 0xa005, 0x0110, 0x8001, 0x603e,
+	0x2660, 0x080c, 0x82eb, 0x00ce, 0x6837, 0x0103, 0x6b4a, 0x6847,
+	0x0000, 0x080c, 0x9ada, 0x080c, 0x5271, 0x080c, 0x7dfb, 0x00fe,
+	0x0005, 0x00e6, 0x00c6, 0x2071, 0xb3d9, 0x7004, 0xa084, 0x0007,
+	0x0002, 0x6dd3, 0x6dd6, 0x6dec, 0x6e05, 0x6e3e, 0x6dd3, 0x6dd1,
+	0x6dd1, 0x080c, 0x14fa, 0x00ce, 0x00ee, 0x0005, 0x7024, 0xa065,
+	0x0148, 0x7020, 0x8001, 0x7022, 0x600c, 0xa015, 0x0150, 0x7216,
+	0x600f, 0x0000, 0x7007, 0x0000, 0x7027, 0x0000, 0x00ce, 0x00ee,
+	0x0005, 0x7216, 0x7212, 0x0cb0, 0x6018, 0x2060, 0x080c, 0x4d4c,
+	0x6000, 0xc0dc, 0x6002, 0x7020, 0x8001, 0x7022, 0x0120, 0x6054,
+	0xa015, 0x0140, 0x721e, 0x7007, 0x0000, 0x7027, 0x0000, 0x00ce,
+	0x00ee, 0x0005, 0x7218, 0x721e, 0x0cb0, 0x7024, 0xa065, 0x0598,
+	0x700c, 0xac06, 0x1160, 0x080c, 0x7dfb, 0x600c, 0xa015, 0x0120,
+	0x720e, 0x600f, 0x0000, 0x0428, 0x720e, 0x720a, 0x0410, 0x7014,
+	0xac06, 0x1160, 0x080c, 0x7dfb, 0x600c, 0xa015, 0x0120, 0x7216,
+	0x600f, 0x0000, 0x00b0, 0x7216, 0x7212, 0x0098, 0x6018, 0x2060,
+	0x080c, 0x4d4c, 0x6000, 0xc0dc, 0x6002, 0x080c, 0x7dfb, 0x701c,
+	0xa065, 0x0138, 0x6054, 0xa015, 0x0110, 0x721e, 0x0010, 0x7218,
+	0x721e, 0x7027, 0x0000, 0x00ce, 0x00ee, 0x0005, 0x7024, 0xa065,
+	0x0140, 0x080c, 0x7dfb, 0x600c, 0xa015, 0x0150, 0x720e, 0x600f,
+	0x0000, 0x080c, 0x7f1b, 0x7027, 0x0000, 0x00ce, 0x00ee, 0x0005,
+	0x720e, 0x720a, 0x0cb0, 0x00d6, 0x2069, 0xb3d9, 0x6830, 0xa084,
+	0x0003, 0x0002, 0x6e60, 0x6e62, 0x6e86, 0x6e5e, 0x080c, 0x14fa,
+	0x00de, 0x0005, 0x00c6, 0x6840, 0xa086, 0x0001, 0x01b8, 0x683c,
+	0xa065, 0x0130, 0x600c, 0xa015, 0x0170, 0x6a3a, 0x600f, 0x0000,
+	0x6833, 0x0000, 0x683f, 0x0000, 0x2011, 0xb3f8, 0x2013, 0x0000,
+	0x00ce, 0x00de, 0x0005, 0x683a, 0x6836, 0x0c90, 0x6843, 0x0000,
+	0x6838, 0xa065, 0x0d68, 0x6003, 0x0003, 0x0c50, 0x00c6, 0x6843,
+	0x0000, 0x6847, 0x0000, 0x683c, 0xa065, 0x0168, 0x600c, 0xa015,
+	0x0130, 0x6a3a, 0x600f, 0x0000, 0x683f, 0x0000, 0x0020, 0x683f,
+	0x0000, 0x683a, 0x6836, 0x00ce, 0x00de, 0x0005, 0x00d6, 0x2069,
+	0xb3d9, 0x6804, 0xa084, 0x0007, 0x0002, 0x6eaf, 0x6f4b, 0x6f4b,
+	0x6f4b, 0x6f4b, 0x6f4d, 0x6ead, 0x6ead, 0x080c, 0x14fa, 0x6820,
+	0xa005, 0x1110, 0x00de, 0x0005, 0x00c6, 0x680c, 0xa065, 0x0150,
+	0x6807, 0x0004, 0x6826, 0x682b, 0x0000, 0x080c, 0x6f9b, 0x00ce,
+	0x00de, 0x0005, 0x6814, 0xa065, 0x0150, 0x6807, 0x0001, 0x6826,
+	0x682b, 0x0000, 0x080c, 0x6f9b, 0x00ce, 0x00de, 0x0005, 0x00e6,
+	0x0036, 0x6a1c, 0xa2f5, 0x0000, 0x0904, 0x6f47, 0x704c, 0xa00d,
+	0x0118, 0x7088, 0xa005, 0x01a0, 0x7054, 0xa075, 0x0120, 0xa20e,
+	0x0904, 0x6f47, 0x0028, 0x6818, 0xa20e, 0x0904, 0x6f47, 0x2070,
+	0x704c, 0xa00d, 0x0d88, 0x7088, 0xa005, 0x1d70, 0x2e00, 0x681e,
+	0x733c, 0x7038, 0xa302, 0x1e40, 0x080c, 0x82c2, 0x0904, 0x6f47,
+	0x8318, 0x733e, 0x6112, 0x2e10, 0x621a, 0xa180, 0x0014, 0x2004,
+	0xa084, 0x00ff, 0x605a, 0xa180, 0x0014, 0x2003, 0x0000, 0xa180,
+	0x0015, 0x2004, 0xa08a, 0x199a, 0x0210, 0x2001, 0x1999, 0x8003,
+	0x801b, 0x831b, 0xa318, 0x6316, 0x003e, 0x00f6, 0x2c78, 0x71a0,
+	0x2001, 0xb134, 0x2004, 0xd0ac, 0x1110, 0xd1bc, 0x0150, 0x7100,
+	0xd1f4, 0x0120, 0x7114, 0xa18c, 0x00ff, 0x0040, 0x2009, 0x0000,
+	0x0028, 0xa1e0, 0x2c8c, 0x2c0d, 0xa18c, 0x00ff, 0x2061, 0x0100,
+	0x619a, 0x080c, 0x75c4, 0x7300, 0xc3dd, 0x7302, 0x6807, 0x0002,
+	0x2f18, 0x6b26, 0x682b, 0x0000, 0x781f, 0x0003, 0x7803, 0x0001,
+	0x7807, 0x0040, 0x00fe, 0x00ee, 0x00ce, 0x00de, 0x0005, 0x003e,
+	0x00ee, 0x00ce, 0x0cd0, 0x00de, 0x0005, 0x00c6, 0x680c, 0xa065,
+	0x0138, 0x6807, 0x0004, 0x6826, 0x682b, 0x0000, 0x080c, 0x6f9b,
+	0x00ce, 0x00de, 0x0005, 0x00f6, 0x00d6, 0x2069, 0xb3d9, 0x6830,
+	0xa086, 0x0000, 0x11c0, 0x2001, 0xb10c, 0x200c, 0xd1bc, 0x1550,
+	0x6838, 0xa07d, 0x0180, 0x6833, 0x0001, 0x683e, 0x6847, 0x0000,
+	0x0126, 0x00f6, 0x2091, 0x2400, 0x002e, 0x080c, 0x1f3c, 0x1130,
+	0x012e, 0x080c, 0x78fd, 0x00de, 0x00fe, 0x0005, 0x012e, 0xe000,
+	0x6843, 0x0000, 0x7803, 0x0002, 0x780c, 0xa015, 0x0140, 0x6a3a,
+	0x780f, 0x0000, 0x6833, 0x0000, 0x683f, 0x0000, 0x0c60, 0x683a,
+	0x6836, 0x0cc0, 0xc1bc, 0x2102, 0x0066, 0x2031, 0x0001, 0x080c,
+	0x5957, 0x006e, 0x0868, 0x601c, 0xa084, 0x000f, 0x000b, 0x0005,
+	0x6fa9, 0x6fae, 0x7465, 0x7581, 0x6fae, 0x7465, 0x7581, 0x6fa9,
+	0x6fae, 0x080c, 0x6dc1, 0x080c, 0x6e9e, 0x0005, 0x0156, 0x0136,
+	0x0146, 0x00c6, 0x00f6, 0x6004, 0xa08a, 0x0080, 0x1a0c, 0x14fa,
+	0x6118, 0x2178, 0x79a0, 0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110,
+	0xd1bc, 0x0150, 0x7900, 0xd1f4, 0x0120, 0x7914, 0xa18c, 0x00ff,
+	0x0040, 0x2009, 0x0000, 0x0028, 0xa1f8, 0x2c8c, 0x2f0d, 0xa18c,
+	0x00ff, 0x2c78, 0x2061, 0x0100, 0x619a, 0xa08a, 0x0040, 0x1a04,
+	0x7022, 0x0033, 0x00fe, 0x00ce, 0x014e, 0x013e, 0x015e, 0x0005,
+	0x70d1, 0x711c, 0x7149, 0x7216, 0x7244, 0x724c, 0x7272, 0x7283,
+	0x7294, 0x729c, 0x72b2, 0x729c, 0x730c, 0x7283, 0x732d, 0x7335,
+	0x7294, 0x7335, 0x7346, 0x7020, 0x7020, 0x7020, 0x7020, 0x7020,
+	0x7020, 0x7020, 0x7020, 0x7020, 0x7020, 0x7020, 0x7b6d, 0x7b92,
+	0x7ba7, 0x7bca, 0x7beb, 0x7272, 0x7020, 0x7272, 0x729c, 0x7020,
+	0x7149, 0x7216, 0x7020, 0x801d, 0x729c, 0x7020, 0x803d, 0x729c,
+	0x7020, 0x7294, 0x70ca, 0x7035, 0x7020, 0x8062, 0x80d7, 0x81ae,
+	0x7020, 0x81bf, 0x726d, 0x81db, 0x7020, 0x7c00, 0x8236, 0x7020,
+	0x080c, 0x14fa, 0x2100, 0x0033, 0x00fe, 0x00ce, 0x014e, 0x013e,
+	0x015e, 0x0005, 0x7033, 0x7033, 0x7033, 0x7069, 0x7087, 0x709d,
+	0x7033, 0x7033, 0x7033, 0x080c, 0x14fa, 0x00d6, 0x20a1, 0x020b,
+	0x080c, 0x7363, 0x7810, 0x2068, 0x20a3, 0x2414, 0x20a3, 0x0018,
+	0x20a3, 0x0800, 0x683c, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x6850, 0x20a2, 0x6854, 0x20a2,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0018, 0x080c, 0x7a79,
+	0x00de, 0x0005, 0x00d6, 0x7818, 0x2068, 0x68a0, 0x2069, 0xb100,
+	0x6ad0, 0xd2ac, 0x1110, 0xd0bc, 0x0110, 0xa085, 0x0001, 0x00de,
+	0x0005, 0x00d6, 0x20a1, 0x020b, 0x080c, 0x7363, 0x20a3, 0x0500,
+	0x20a3, 0x0000, 0x7810, 0xa0e8, 0x000f, 0x6808, 0x20a2, 0x680c,
+	0x20a2, 0x6810, 0x20a2, 0x6814, 0x20a2, 0x6818, 0x20a2, 0x681c,
+	0x20a2, 0x60c3, 0x0010, 0x080c, 0x7a79, 0x00de, 0x0005, 0x0156,
+	0x0146, 0x20a1, 0x020b, 0x080c, 0x7363, 0x20a3, 0x7800, 0x20a3,
+	0x0000, 0x7808, 0x8007, 0x20a2, 0x20a3, 0x0000, 0x60c3, 0x0008,
+	0x080c, 0x7a79, 0x014e, 0x015e, 0x0005, 0x0156, 0x0146, 0x20a1,
+	0x020b, 0x080c, 0x73ff, 0x20a3, 0x0200, 0x20a3, 0x0000, 0x20a3,
+	0xdf10, 0x20a3, 0x0034, 0x2099, 0xb105, 0x20a9, 0x0004, 0x53a6,
+	0x2099, 0xb101, 0x20a9, 0x0004, 0x53a6, 0x2099, 0xb3bf, 0x20a9,
+	0x001a, 0x3304, 0x8007, 0x20a2, 0x9398, 0x1f04, 0x70b9, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x004c, 0x080c, 0x7a79, 0x014e,
+	0x015e, 0x0005, 0x2001, 0xb114, 0x2004, 0x609a, 0x080c, 0x7a79,
+	0x0005, 0x20a1, 0x020b, 0x080c, 0x7363, 0x20a3, 0x5200, 0x20a3,
+	0x0000, 0x00d6, 0x2069, 0xb152, 0x6804, 0xd084, 0x0150, 0x6828,
+	0x20a3, 0x0000, 0x0016, 0x080c, 0x270a, 0x21a2, 0x001e, 0x00de,
+	0x0028, 0x00de, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a9, 0x0004,
+	0x2099, 0xb105, 0x53a6, 0x20a9, 0x0004, 0x2099, 0xb101, 0x53a6,
+	0x2001, 0xb134, 0x2004, 0xd0ac, 0x1138, 0x7818, 0xa080, 0x0028,
+	0x2004, 0xa082, 0x007f, 0x0238, 0x2001, 0xb11b, 0x20a6, 0x2001,
+	0xb11c, 0x20a6, 0x0040, 0x20a3, 0x0000, 0x2001, 0xb114, 0x2004,
+	0xa084, 0x00ff, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3,
+	0x001c, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c, 0x7363,
+	0x20a3, 0x0500, 0x20a3, 0x0000, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x1138, 0x7818, 0xa080, 0x0028, 0x2004, 0xa082, 0x007f, 0x0238,
+	0x2001, 0xb11b, 0x20a6, 0x2001, 0xb11c, 0x20a6, 0x0040, 0x20a3,
+	0x0000, 0x2001, 0xb114, 0x2004, 0xa084, 0x00ff, 0x20a2, 0x20a9,
+	0x0004, 0x2099, 0xb105, 0x53a6, 0x60c3, 0x0010, 0x080c, 0x7a79,
+	0x0005, 0x20a1, 0x020b, 0x080c, 0x7363, 0x00c6, 0x7818, 0x2060,
+	0x2001, 0x0000, 0x080c, 0x5185, 0x00ce, 0x7818, 0xa080, 0x0028,
+	0x2004, 0xa086, 0x007e, 0x1130, 0x20a3, 0x0400, 0x620c, 0xc2b4,
+	0x620e, 0x0010, 0x20a3, 0x0300, 0x20a3, 0x0000, 0x7818, 0xa080,
+	0x0028, 0x2004, 0xa086, 0x007e, 0x1904, 0x71d8, 0x2001, 0xb134,
+	0x2004, 0xd0a4, 0x01c8, 0x2099, 0xb38e, 0x33a6, 0x9398, 0x20a3,
+	0x0000, 0x9398, 0x3304, 0xa084, 0x2000, 0x20a2, 0x9398, 0x33a6,
+	0x9398, 0x20a3, 0x0000, 0x9398, 0x2001, 0x2710, 0x20a2, 0x9398,
+	0x33a6, 0x9398, 0x33a6, 0x00d0, 0x2099, 0xb38e, 0x33a6, 0x9398,
+	0x33a6, 0x9398, 0x3304, 0x080c, 0x58d5, 0x1118, 0xa084, 0x37ff,
+	0x0010, 0xa084, 0x3fff, 0x20a2, 0x9398, 0x33a6, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a9, 0x0004,
+	0x2099, 0xb105, 0x53a6, 0x20a9, 0x0004, 0x2099, 0xb101, 0x53a6,
+	0x20a9, 0x0008, 0x20a3, 0x0000, 0x1f04, 0x71b2, 0x20a9, 0x0008,
+	0x20a3, 0x0000, 0x1f04, 0x71b8, 0x2099, 0xb396, 0x3304, 0xc0dd,
+	0x20a2, 0x2001, 0xb172, 0x2004, 0xd0e4, 0x0158, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x9398, 0x9398, 0x9398, 0x33a6, 0x20a9, 0x0004,
+	0x0010, 0x20a9, 0x0007, 0x20a3, 0x0000, 0x1f04, 0x71d3, 0x0468,
+	0x2001, 0xb134, 0x2004, 0xd0a4, 0x0140, 0x2001, 0xb38f, 0x2004,
+	0x60e3, 0x0000, 0x080c, 0x274b, 0x60e2, 0x2099, 0xb38e, 0x20a9,
+	0x0008, 0x53a6, 0x20a9, 0x0004, 0x2099, 0xb105, 0x53a6, 0x20a9,
+	0x0004, 0x2099, 0xb101, 0x53a6, 0x20a9, 0x0008, 0x20a3, 0x0000,
+	0x1f04, 0x71f6, 0x20a9, 0x0008, 0x20a3, 0x0000, 0x1f04, 0x71fc,
+	0x2099, 0xb396, 0x20a9, 0x0008, 0x53a6, 0x20a9, 0x0008, 0x20a3,
+	0x0000, 0x1f04, 0x7207, 0x20a9, 0x000a, 0x20a3, 0x0000, 0x1f04,
+	0x720d, 0x60c3, 0x0074, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b,
+	0x080c, 0x7363, 0x20a3, 0x2010, 0x20a3, 0x0014, 0x20a3, 0x0800,
+	0x20a3, 0x2000, 0xa006, 0x20a2, 0x20a2, 0x20a2, 0x20a2, 0x20a2,
+	0x00f6, 0x2079, 0xb152, 0x7904, 0x00fe, 0xd1ac, 0x1110, 0xa085,
+	0x0020, 0xd1a4, 0x0110, 0xa085, 0x0010, 0xa085, 0x0002, 0x00d6,
+	0x0804, 0x72ee, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3,
+	0x0014, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c, 0x7363,
+	0x20a3, 0x5000, 0x0804, 0x7164, 0x20a1, 0x020b, 0x080c, 0x7363,
+	0x20a3, 0x2110, 0x20a3, 0x0014, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x60c3, 0x0014, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c,
+	0x73f7, 0x0020, 0x20a1, 0x020b, 0x080c, 0x73ff, 0x20a3, 0x0200,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0004,
+	0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c, 0x73ff, 0x20a3,
+	0x0100, 0x20a3, 0x0000, 0x20a3, 0x0003, 0x20a3, 0x2a00, 0x60c3,
+	0x0008, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c, 0x73ff,
+	0x20a3, 0x0200, 0x0804, 0x7164, 0x20a1, 0x020b, 0x080c, 0x73ff,
+	0x20a3, 0x0100, 0x20a3, 0x0000, 0x7828, 0xa005, 0x0110, 0x20a2,
+	0x0010, 0x20a3, 0x0003, 0x7810, 0x20a2, 0x60c3, 0x0008, 0x080c,
+	0x7a79, 0x0005, 0x00d6, 0x20a1, 0x020b, 0x080c, 0x73ff, 0x20a3,
+	0x0210, 0x20a3, 0x0014, 0x20a3, 0x0800, 0x7818, 0x2068, 0x6894,
+	0xa086, 0x0014, 0x1178, 0x6998, 0xa184, 0xc000, 0x1140, 0xd1ec,
+	0x0118, 0x20a3, 0x2100, 0x0040, 0x20a3, 0x0100, 0x0028, 0x20a3,
+	0x0400, 0x0010, 0x20a3, 0x0700, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a2, 0x00f6, 0x2079, 0xb152, 0x7904, 0x00fe, 0xd1ac,
+	0x1110, 0xa085, 0x0020, 0xd1a4, 0x0110, 0xa085, 0x0010, 0x2009,
+	0xb174, 0x210c, 0xd184, 0x1110, 0xa085, 0x0002, 0x0026, 0x2009,
+	0xb172, 0x210c, 0xd1e4, 0x0130, 0xc0c5, 0xa094, 0x0030, 0xa296,
+	0x0010, 0x0140, 0xd1ec, 0x0130, 0xa094, 0x0030, 0xa296, 0x0010,
+	0x0108, 0xc0bd, 0x002e, 0x20a2, 0x20a2, 0x20a2, 0x60c3, 0x0014,
+	0x080c, 0x7a79, 0x00de, 0x0005, 0x20a1, 0x020b, 0x080c, 0x73ff,
+	0x20a3, 0x0210, 0x20a3, 0x0014, 0x20a3, 0x0000, 0x20a3, 0x0100,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x60c3, 0x0014, 0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c,
+	0x73ff, 0x20a3, 0x0200, 0x0804, 0x70d7, 0x20a1, 0x020b, 0x080c,
+	0x73ff, 0x20a3, 0x0100, 0x20a3, 0x0000, 0x20a3, 0x0003, 0x20a3,
+	0x2a00, 0x60c3, 0x0008, 0x080c, 0x7a79, 0x0005, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x20a1, 0x020b, 0x080c, 0x73ff, 0x20a3, 0x0100,
+	0x20a3, 0x0000, 0x20a3, 0x000b, 0x20a3, 0x0000, 0x60c3, 0x0008,
+	0x080c, 0x7a79, 0x0005, 0x0026, 0x0036, 0x0046, 0x2019, 0x3200,
+	0x2021, 0x0800, 0x0038, 0x0026, 0x0036, 0x0046, 0x2019, 0x2200,
+	0x2021, 0x0100, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080,
+	0x0028, 0x2014, 0xa286, 0x007e, 0x11a0, 0xa385, 0x00ff, 0x20a2,
+	0x20a3, 0xfffe, 0x20a3, 0x0000, 0x2011, 0xb114, 0x2214, 0x2001,
+	0xb39e, 0x2004, 0xa005, 0x0118, 0x2011, 0xb11c, 0x2214, 0x22a2,
+	0x04d0, 0xa286, 0x007f, 0x1138, 0x00d6, 0xa385, 0x00ff, 0x20a2,
+	0x20a3, 0xfffd, 0x00c8, 0x2001, 0xb134, 0x2004, 0xd0ac, 0x1110,
+	0xd2bc, 0x01c8, 0xa286, 0x0080, 0x00d6, 0x1130, 0xa385, 0x00ff,
+	0x20a2, 0x20a3, 0xfffc, 0x0040, 0xa2e8, 0xb235, 0x2d6c, 0x6810,
+	0xa305, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xb11b, 0x2da6, 0x8d68,
+	0x2da6, 0x00de, 0x0080, 0x00d6, 0xa2e8, 0xb235, 0x2d6c, 0x6810,
+	0xa305, 0x20a2, 0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011,
+	0xb114, 0x2214, 0x22a2, 0xa485, 0x0029, 0x20a2, 0x004e, 0x003e,
+	0x20a3, 0x0000, 0x080c, 0x7a68, 0x22a2, 0x20a3, 0x0000, 0x2fa2,
+	0x20a3, 0xffff, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x002e, 0x0005,
+	0x0026, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x20a3, 0x02ff, 0x2011,
+	0xfffc, 0x22a2, 0x00d6, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6,
+	0x00de, 0x20a3, 0x2029, 0x20a3, 0x0000, 0x08e0, 0x20a3, 0x0100,
+	0x20a3, 0x0000, 0x20a3, 0xfc02, 0x20a3, 0x0000, 0x0005, 0x0026,
+	0x0036, 0x0046, 0x2019, 0x3300, 0x2021, 0x0800, 0x0038, 0x0026,
+	0x0036, 0x0046, 0x2019, 0x2300, 0x2021, 0x0100, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134,
+	0x2214, 0xd2ac, 0x1118, 0xa092, 0x007e, 0x02d8, 0x00d6, 0xa0e8,
+	0xb235, 0x2d6c, 0x6810, 0xa305, 0x20a2, 0x6814, 0x20a2, 0x6810,
+	0xa005, 0x1140, 0x6814, 0xa005, 0x1128, 0x20a3, 0x00ff, 0x20a3,
+	0xfffe, 0x0028, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de,
+	0x0080, 0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa305, 0x20a2,
+	0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114, 0x2214,
+	0x22a2, 0xa485, 0x0098, 0x20a2, 0x20a3, 0x0000, 0x004e, 0x003e,
+	0x080c, 0x7a68, 0x22a2, 0x20a3, 0x0000, 0x7a08, 0x22a2, 0x2fa2,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x002e, 0x0005, 0x080c, 0x7a68,
+	0x22a2, 0x20a3, 0x0000, 0x7a08, 0x22a2, 0x7810, 0x20a2, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x002e, 0x0005, 0x00c6, 0x00f6, 0x6004,
+	0xa08a, 0x0085, 0x0a0c, 0x14fa, 0xa08a, 0x008c, 0x1a0c, 0x14fa,
+	0x6118, 0x2178, 0x79a0, 0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110,
+	0xd1bc, 0x0150, 0x7900, 0xd1f4, 0x0120, 0x7914, 0xa18c, 0x00ff,
+	0x0040, 0x2009, 0x0000, 0x0028, 0xa1f8, 0x2c8c, 0x2f0d, 0xa18c,
+	0x00ff, 0x2c78, 0x2061, 0x0100, 0x619a, 0xa082, 0x0085, 0x001b,
+	0x00fe, 0x00ce, 0x0005, 0x749c, 0x74a6, 0x74c1, 0x749a, 0x749a,
+	0x749a, 0x749c, 0x080c, 0x14fa, 0x0146, 0x20a1, 0x020b, 0x04a1,
+	0x60c3, 0x0000, 0x080c, 0x7a79, 0x014e, 0x0005, 0x0146, 0x20a1,
+	0x020b, 0x080c, 0x750d, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x7808,
+	0x20a2, 0x7810, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0xffff, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x000c, 0x080c, 0x7a79, 0x014e,
+	0x0005, 0x0146, 0x20a1, 0x020b, 0x080c, 0x7547, 0x20a3, 0x0003,
+	0x20a3, 0x0300, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0004,
+	0x080c, 0x7a79, 0x014e, 0x0005, 0x0026, 0x20e1, 0x9080, 0x20e1,
+	0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134, 0x2214,
+	0xd2ac, 0x1118, 0xa092, 0x007e, 0x0288, 0x00d6, 0xa0e8, 0xb235,
+	0x2d6c, 0x6810, 0xa085, 0x8100, 0x20a2, 0x6814, 0x20a2, 0x2069,
+	0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0088, 0x00d6, 0xa0e8,
+	0xb235, 0x2d6c, 0x6810, 0xa085, 0x8100, 0x20a2, 0x6814, 0x20a2,
+	0x00de, 0x20a3, 0x0000, 0x2011, 0xb114, 0x2214, 0x22a2, 0x20a3,
+	0x0009, 0x20a3, 0x0000, 0x0804, 0x73ca, 0x0026, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134,
+	0x2214, 0xd2ac, 0x1118, 0xa092, 0x007e, 0x0288, 0x00d6, 0xa0e8,
+	0xb235, 0x2d6c, 0x6810, 0xa085, 0x8400, 0x20a2, 0x6814, 0x20a2,
+	0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0088, 0x00d6,
+	0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x8400, 0x20a2, 0x6814,
+	0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114, 0x2214, 0x22a2,
+	0x2001, 0x0099, 0x20a2, 0x20a3, 0x0000, 0x0804, 0x7456, 0x0026,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004,
+	0x2011, 0xb134, 0x2214, 0xd2ac, 0x1118, 0xa092, 0x007e, 0x0288,
+	0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x8500, 0x20a2,
+	0x6814, 0x20a2, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de,
+	0x0088, 0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x8500,
+	0x20a2, 0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114,
+	0x2214, 0x22a2, 0x2001, 0x0099, 0x20a2, 0x20a3, 0x0000, 0x0804,
+	0x7456, 0x00c6, 0x00f6, 0x2c78, 0x7804, 0xa08a, 0x0040, 0x0a0c,
+	0x14fa, 0xa08a, 0x0053, 0x1a0c, 0x14fa, 0x7918, 0x2160, 0x61a0,
+	0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110, 0xd1bc, 0x0150, 0x6100,
+	0xd1f4, 0x0120, 0x6114, 0xa18c, 0x00ff, 0x0040, 0x2009, 0x0000,
+	0x0028, 0xa1e0, 0x2c8c, 0x2c0d, 0xa18c, 0x00ff, 0x2061, 0x0100,
+	0x619a, 0xa082, 0x0040, 0x001b, 0x00fe, 0x00ce, 0x0005, 0x75c4,
+	0x76d0, 0x766d, 0x7872, 0x75c2, 0x75c2, 0x75c2, 0x75c2, 0x75c2,
+	0x75c2, 0x75c2, 0x7db4, 0x7dc4, 0x7dd4, 0x7de4, 0x75c2, 0x81ec,
+	0x75c2, 0x7da3, 0x080c, 0x14fa, 0x00d6, 0x0156, 0x0146, 0x780b,
+	0xffff, 0x20a1, 0x020b, 0x080c, 0x7624, 0x7910, 0x2168, 0x6948,
+	0x7952, 0x21a2, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x694c, 0xa184,
+	0x000f, 0x1118, 0x2001, 0x0005, 0x0040, 0xd184, 0x0118, 0x2001,
+	0x0004, 0x0018, 0xa084, 0x0006, 0x8004, 0x0016, 0x2008, 0x7858,
+	0xa084, 0x00ff, 0x8007, 0xa105, 0x001e, 0x20a2, 0xd1ac, 0x0118,
+	0x20a3, 0x0002, 0x0048, 0xd1b4, 0x0118, 0x20a3, 0x0001, 0x0020,
+	0x20a3, 0x0000, 0x2230, 0x0010, 0x6a80, 0x6e7c, 0x20a9, 0x0008,
+	0x0136, 0xad88, 0x0017, 0x2198, 0x20a1, 0x021b, 0x53a6, 0x013e,
+	0x20a1, 0x020b, 0x22a2, 0x26a2, 0x60c3, 0x0020, 0x20e1, 0x9080,
+	0x6014, 0xa084, 0x0004, 0xa085, 0x0009, 0x6016, 0x2001, 0xb3f5,
+	0x2003, 0x07d0, 0x2001, 0xb3f4, 0x2003, 0x0009, 0x080c, 0x17c3,
+	0x014e, 0x015e, 0x00de, 0x0005, 0x20e1, 0x9080, 0x20e1, 0x4000,
+	0x7a18, 0xa280, 0x0023, 0x2014, 0x8210, 0xa294, 0x00ff, 0x2202,
+	0x8217, 0x7818, 0xa080, 0x0028, 0x2004, 0x2019, 0xb134, 0x231c,
+	0xd3ac, 0x1110, 0xd0bc, 0x0188, 0x00d6, 0xa0e8, 0xb235, 0x2d6c,
+	0x6810, 0xa085, 0x0600, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xb11b,
+	0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0088, 0x00d6, 0xa0e8, 0xb235,
+	0x2d6c, 0x6810, 0xa085, 0x0600, 0x20a2, 0x6814, 0x20a2, 0x00de,
+	0x20a3, 0x0000, 0x2009, 0xb114, 0x210c, 0x21a2, 0x20a3, 0x0829,
+	0x20a3, 0x0000, 0x22a2, 0x20a3, 0x0000, 0x2fa2, 0x20a3, 0xffff,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x0005, 0x00d6, 0x0156, 0x0136,
+	0x0146, 0x20a1, 0x020b, 0x00c1, 0x7810, 0x2068, 0x6860, 0x20a2,
+	0x685c, 0x20a2, 0x6880, 0x20a2, 0x687c, 0x20a2, 0xa006, 0x20a2,
+	0x20a2, 0x20a2, 0x20a2, 0x60c3, 0x000c, 0x080c, 0x7a79, 0x014e,
+	0x013e, 0x015e, 0x00de, 0x0005, 0x0026, 0x20e1, 0x9080, 0x20e1,
+	0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134, 0x2214,
+	0xd2ac, 0x1110, 0xd0bc, 0x0188, 0x00d6, 0xa0e8, 0xb235, 0x2d6c,
+	0x6810, 0xa085, 0x0500, 0x20a2, 0x6814, 0x20a2, 0x2069, 0xb11b,
+	0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0088, 0x00d6, 0xa0e8, 0xb235,
+	0x2d6c, 0x6810, 0xa085, 0x0500, 0x20a2, 0x6814, 0x20a2, 0x00de,
+	0x20a3, 0x0000, 0x2011, 0xb114, 0x2214, 0x22a2, 0x20a3, 0x0889,
+	0x20a3, 0x0000, 0x080c, 0x7a68, 0x22a2, 0x20a3, 0x0000, 0x7a08,
+	0x22a2, 0x2fa2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x002e, 0x0005,
+	0x00d6, 0x0156, 0x0136, 0x0146, 0x7810, 0xa0ec, 0xf000, 0x0168,
+	0xa06d, 0x080c, 0x5173, 0x0148, 0x684c, 0xa084, 0x2020, 0xa086,
+	0x2020, 0x1118, 0x7820, 0xc0cd, 0x7822, 0x20a1, 0x020b, 0x080c,
+	0x7828, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x7810,
+	0xa084, 0xf000, 0x1130, 0x7810, 0xa084, 0x0700, 0x8007, 0x0043,
+	0x0010, 0xa006, 0x002b, 0x014e, 0x013e, 0x015e, 0x00de, 0x0005,
+	0x770a, 0x779f, 0x77a8, 0x77d1, 0x77e4, 0x77ff, 0x7808, 0x7708,
+	0x080c, 0x14fa, 0x0016, 0x0036, 0x694c, 0xa18c, 0x0003, 0x0118,
+	0xa186, 0x0003, 0x1170, 0x6b78, 0x7820, 0xd0cc, 0x0108, 0xc3e5,
+	0x23a2, 0x6868, 0x20a2, 0x6864, 0x20a2, 0x003e, 0x001e, 0x0804,
+	0x77db, 0xa186, 0x0001, 0x190c, 0x14fa, 0x6b78, 0x7820, 0xd0cc,
+	0x0108, 0xc3e5, 0x23a2, 0x6868, 0x20a2, 0x6864, 0x20a2, 0x22a2,
+	0x6874, 0x20a2, 0x22a2, 0x687c, 0x20a2, 0x2009, 0x0018, 0xa384,
+	0x0300, 0x0904, 0x7799, 0xd3c4, 0x0110, 0x687c, 0xa108, 0xd3cc,
+	0x0110, 0x6874, 0xa108, 0x0156, 0x20a9, 0x000d, 0xad80, 0x0020,
+	0x201c, 0x831f, 0x23a2, 0x8000, 0x1f04, 0x7748, 0x015e, 0x22a2,
+	0x22a2, 0x22a2, 0xa184, 0x0003, 0x0904, 0x7799, 0x20a1, 0x020b,
+	0x20e1, 0x9080, 0x20e1, 0x4000, 0x0006, 0x7818, 0xa080, 0x0028,
+	0x2004, 0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110, 0xd0bc, 0x0188,
+	0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2,
+	0x6814, 0x20a2, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de,
+	0x0088, 0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0700,
+	0x20a2, 0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114,
+	0x2214, 0x22a2, 0x000e, 0x7b20, 0xd3cc, 0x0118, 0x20a3, 0x0889,
+	0x0010, 0x20a3, 0x0898, 0x20a2, 0x080c, 0x7a68, 0x22a2, 0x20a3,
+	0x0000, 0x61c2, 0x003e, 0x001e, 0x080c, 0x7a79, 0x0005, 0x2011,
+	0x0008, 0x7820, 0xd0cc, 0x0108, 0xc2e5, 0x22a2, 0xa016, 0x0488,
+	0x2011, 0x0302, 0x7820, 0xd0cc, 0x0108, 0xc2e5, 0x22a2, 0xa016,
+	0x22a2, 0x22a2, 0x22a2, 0x20a3, 0x0012, 0x22a2, 0x20a3, 0x0008,
+	0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x20a3, 0x7000, 0x20a3, 0x0500,
+	0x22a2, 0x20a3, 0x000a, 0x22a2, 0x22a2, 0x20a3, 0x2500, 0x22a2,
+	0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x60c3, 0x0032, 0x080c, 0x7a79,
+	0x0005, 0x2011, 0x0028, 0x7820, 0xd0cc, 0x0108, 0xc2e5, 0x22a2,
+	0xa016, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x22a2, 0x60c3,
+	0x0018, 0x080c, 0x7a79, 0x0005, 0x2011, 0x0100, 0x7820, 0xd0cc,
+	0x0108, 0xc2e5, 0x22a2, 0xa016, 0x22a2, 0x22a2, 0x22a2, 0x22a2,
+	0x22a2, 0x20a3, 0x0008, 0x22a2, 0x7854, 0xa084, 0x00ff, 0x20a2,
+	0x22a2, 0x22a2, 0x60c3, 0x0020, 0x080c, 0x7a79, 0x0005, 0x2011,
+	0x0008, 0x7820, 0xd0cc, 0x0108, 0xc2e5, 0x22a2, 0xa016, 0x0888,
+	0x0036, 0x7b10, 0xa384, 0xff00, 0x7812, 0xa384, 0x00ff, 0x8001,
+	0x1138, 0x7820, 0xd0cc, 0x0108, 0xc2e5, 0x22a2, 0x003e, 0x0808,
+	0x0046, 0x2021, 0x0800, 0x0006, 0x7820, 0xd0cc, 0x000e, 0x0108,
+	0xc4e5, 0x24a2, 0x004e, 0x22a2, 0x20a2, 0x003e, 0x0804, 0x77db,
+	0x0026, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028,
+	0x2004, 0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110, 0xd0bc, 0x0188,
+	0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0700, 0x20a2,
+	0x6814, 0x20a2, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de,
+	0x0088, 0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0700,
+	0x20a2, 0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114,
+	0x2214, 0x22a2, 0x7820, 0xd0cc, 0x0118, 0x20a3, 0x0889, 0x0010,
+	0x20a3, 0x0898, 0x20a3, 0x0000, 0x080c, 0x7a68, 0x22a2, 0x20a3,
+	0x0000, 0x7a08, 0x22a2, 0x2fa2, 0x20a3, 0x0000, 0x20a3, 0x0000,
+	0x002e, 0x0005, 0x00d6, 0x0156, 0x0136, 0x0146, 0x0016, 0x0036,
+	0x7810, 0xa084, 0x0700, 0x8007, 0x003b, 0x003e, 0x001e, 0x014e,
+	0x013e, 0x015e, 0x00de, 0x0005, 0x788c, 0x788c, 0x788e, 0x788c,
+	0x788c, 0x788c, 0x78b0, 0x788c, 0x080c, 0x14fa, 0x7910, 0xa18c,
+	0xf8ff, 0xa18d, 0x0600, 0x7912, 0x20a1, 0x020b, 0x2009, 0x0003,
+	0x00f9, 0x00d6, 0x2069, 0xb152, 0x6804, 0xd0bc, 0x0130, 0x682c,
+	0xa084, 0x00ff, 0x8007, 0x20a2, 0x0010, 0x20a3, 0x3f00, 0x00de,
+	0x22a2, 0x22a2, 0x22a2, 0x60c3, 0x0001, 0x080c, 0x7a79, 0x0005,
+	0x20a1, 0x020b, 0x2009, 0x0003, 0x0019, 0x20a3, 0x7f00, 0x0c80,
+	0x0026, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x7818, 0xa080, 0x0028,
+	0x2004, 0x2011, 0xb134, 0x2214, 0xd2ac, 0x1110, 0xd0bc, 0x0188,
+	0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0100, 0x20a2,
+	0x6814, 0x20a2, 0x2069, 0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de,
+	0x0088, 0x00d6, 0xa0e8, 0xb235, 0x2d6c, 0x6810, 0xa085, 0x0100,
+	0x20a2, 0x6814, 0x20a2, 0x00de, 0x20a3, 0x0000, 0x2011, 0xb114,
+	0x2214, 0x22a2, 0x20a3, 0x0888, 0xa18d, 0x0008, 0x21a2, 0x080c,
+	0x7a68, 0x22a2, 0x20a3, 0x0000, 0x7a08, 0x22a2, 0x2fa2, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x002e, 0x0005, 0x00e6, 0x00d6, 0x00c6,
+	0x0056, 0x0046, 0x0036, 0x2061, 0x0100, 0x2071, 0xb100, 0x7150,
+	0x7818, 0x2068, 0x68a0, 0x2028, 0x76d0, 0xd6ac, 0x1130, 0xd0bc,
+	0x1120, 0x6910, 0x6a14, 0x7450, 0x0020, 0x6910, 0x6a14, 0x736c,
+	0x7470, 0x781c, 0xa0be, 0x0006, 0x0904, 0x79b3, 0xa0be, 0x000a,
+	0x15e8, 0xa185, 0x0200, 0x6062, 0x6266, 0x636a, 0x646e, 0x6073,
+	0x2029, 0x6077, 0x0000, 0x688c, 0x8000, 0xa084, 0x00ff, 0x688e,
+	0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6082, 0x7808, 0x6086,
+	0x7810, 0x2070, 0x7014, 0x608a, 0x7010, 0x608e, 0x700c, 0x60c6,
+	0x7008, 0x60ca, 0x686c, 0x60ce, 0x60af, 0x95d5, 0x60d7, 0x0000,
+	0x609f, 0x0000, 0x080c, 0x8287, 0x2009, 0x07d0, 0x60c4, 0xa084,
+	0xfff0, 0xa005, 0x0110, 0x2009, 0x1b58, 0x080c, 0x67bb, 0x003e,
+	0x004e, 0x005e, 0x00ce, 0x00de, 0x00ee, 0x0005, 0x70d0, 0xd0ac,
+	0x1110, 0xd5bc, 0x0138, 0xa185, 0x0100, 0x6062, 0x6266, 0x636a,
+	0x646e, 0x0038, 0xa185, 0x0100, 0x6062, 0x6266, 0x606b, 0x0000,
+	0x646e, 0x6073, 0x0809, 0x6077, 0x0008, 0x688c, 0x8000, 0xa084,
+	0x00ff, 0x688e, 0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6082,
+	0x7808, 0x6086, 0x7810, 0x2070, 0x7014, 0x608a, 0x7010, 0x608e,
+	0x700c, 0x60c6, 0x7008, 0x60ca, 0x686c, 0x60ce, 0x60af, 0x95d5,
+	0x60d7, 0x0000, 0xa582, 0x0080, 0x0248, 0x6a00, 0xd2f4, 0x0120,
+	0x6a14, 0xa294, 0x00ff, 0x0010, 0x2011, 0x0000, 0x629e, 0x080c,
+	0x8287, 0x2009, 0x07d0, 0x60c4, 0xa084, 0xfff0, 0xa005, 0x0110,
+	0x2009, 0x1b58, 0x080c, 0x67bb, 0x003e, 0x004e, 0x005e, 0x00ce,
+	0x00de, 0x00ee, 0x0005, 0x7810, 0x2070, 0x704c, 0xa084, 0x0003,
+	0xa086, 0x0002, 0x0904, 0x7a09, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x1110, 0xd5bc, 0x0138, 0xa185, 0x0100, 0x6062, 0x6266, 0x636a,
+	0x646e, 0x0038, 0xa185, 0x0100, 0x6062, 0x6266, 0x606b, 0x0000,
+	0x646e, 0x6073, 0x0880, 0x6077, 0x0008, 0x688c, 0x8000, 0xa084,
+	0x00ff, 0x688e, 0x8007, 0x607a, 0x7834, 0x607e, 0x2f00, 0x6086,
+	0x7808, 0x6082, 0x7060, 0x608a, 0x705c, 0x608e, 0x7080, 0x60c6,
+	0x707c, 0x60ca, 0x707c, 0x792c, 0xa108, 0x792e, 0x7080, 0x7928,
+	0xa109, 0x792a, 0x686c, 0x60ce, 0x60af, 0x95d5, 0x60d7, 0x0000,
+	0xa582, 0x0080, 0x0248, 0x6a00, 0xd2f4, 0x0120, 0x6a14, 0xa294,
+	0x00ff, 0x0010, 0x2011, 0x0000, 0x629e, 0x080c, 0x8284, 0x0804,
+	0x79a1, 0x2001, 0xb134, 0x2004, 0xd0ac, 0x1110, 0xd5bc, 0x0138,
+	0xa185, 0x0700, 0x6062, 0x6266, 0x636a, 0x646e, 0x0038, 0xa185,
+	0x0700, 0x6062, 0x6266, 0x606b, 0x0000, 0x646e, 0x080c, 0x5173,
+	0x0180, 0x00d6, 0x7810, 0xa06d, 0x684c, 0x00de, 0xa084, 0x2020,
+	0xa086, 0x2020, 0x1130, 0x7820, 0xc0cd, 0x7822, 0x6073, 0x0889,
+	0x0010, 0x6073, 0x0898, 0x6077, 0x0000, 0x688c, 0x8000, 0xa084,
+	0x00ff, 0x688e, 0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6086,
+	0x7808, 0x6082, 0x7014, 0x608a, 0x7010, 0x608e, 0x700c, 0x60c6,
+	0x7008, 0x60ca, 0x686c, 0x60ce, 0x60af, 0x95d5, 0x60d7, 0x0000,
+	0xa582, 0x0080, 0x0248, 0x6a00, 0xd2f4, 0x0120, 0x6a14, 0xa294,
+	0x00ff, 0x0010, 0x2011, 0x0000, 0x629e, 0x7820, 0xd0cc, 0x0120,
+	0x080c, 0x8287, 0x0804, 0x79a1, 0x080c, 0x8284, 0x0804, 0x79a1,
+	0x7a18, 0xa280, 0x0023, 0x2014, 0x8210, 0xa294, 0x00ff, 0x2202,
+	0x8217, 0x0005, 0x00d6, 0x2069, 0xb3d9, 0x6843, 0x0001, 0x00de,
+	0x0005, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7, 0x9575, 0x0019,
+	0x080c, 0x67ad, 0x0005, 0x0006, 0x6014, 0xa084, 0x0004, 0xa085,
+	0x0009, 0x6016, 0x000e, 0x0005, 0x0006, 0x00c6, 0x2061, 0x0100,
+	0x6014, 0xa084, 0x0004, 0xa085, 0x0008, 0x6016, 0x00ce, 0x000e,
+	0x0005, 0x00c6, 0x00d6, 0x0016, 0x0026, 0x2061, 0x0100, 0x2069,
+	0x0140, 0x080c, 0x58d5, 0x1198, 0x2001, 0xb3f5, 0x2004, 0xa005,
+	0x15b8, 0x0066, 0x2031, 0x0001, 0x080c, 0x5957, 0x006e, 0x1118,
+	0x080c, 0x67ad, 0x0468, 0x00c6, 0x2061, 0xb3d9, 0x00d8, 0x6904,
+	0xa194, 0x4000, 0x0550, 0x0881, 0x6803, 0x1000, 0x6803, 0x0000,
+	0x00c6, 0x2061, 0xb3d9, 0x6128, 0xa192, 0x00c8, 0x1258, 0x8108,
+	0x612a, 0x6124, 0x00ce, 0x81ff, 0x0198, 0x080c, 0x67ad, 0x080c,
+	0x7a83, 0x0070, 0x6124, 0xa1e5, 0x0000, 0x0140, 0x080c, 0xafee,
+	0x2009, 0x0014, 0x080c, 0x831a, 0x080c, 0x67b6, 0x00ce, 0x0000,
+	0x002e, 0x001e, 0x00de, 0x00ce, 0x0005, 0x2001, 0xb3f5, 0x2004,
+	0xa005, 0x1db0, 0x00c6, 0x2061, 0xb3d9, 0x6128, 0xa192, 0x0003,
+	0x1e08, 0x8108, 0x612a, 0x00ce, 0x080c, 0x67ad, 0x080c, 0x4992,
+	0x0c38, 0x00c6, 0x00d6, 0x00e6, 0x0016, 0x0026, 0x080c, 0x67c3,
+	0x2071, 0xb3d9, 0x713c, 0x81ff, 0x0590, 0x2061, 0x0100, 0x2069,
+	0x0140, 0x080c, 0x58d5, 0x11a8, 0x0036, 0x2019, 0x0002, 0x080c,
+	0x7cc4, 0x003e, 0x713c, 0x2160, 0x080c, 0xafee, 0x2009, 0x004a,
+	0x080c, 0x831a, 0x0066, 0x2031, 0x0001, 0x080c, 0x5957, 0x006e,
+	0x00b0, 0x6904, 0xa194, 0x4000, 0x01c0, 0x6803, 0x1000, 0x6803,
+	0x0000, 0x0036, 0x2019, 0x0001, 0x080c, 0x7cc4, 0x003e, 0x713c,
+	0x2160, 0x080c, 0xafee, 0x2009, 0x004a, 0x080c, 0x831a, 0x002e,
+	0x001e, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x0c58, 0x00e6, 0x00d6,
+	0x00c6, 0x0066, 0x0056, 0x0046, 0x0006, 0x0126, 0x2091, 0x8000,
+	0x6018, 0x2068, 0x6ca0, 0x2071, 0xb3d9, 0x7018, 0x2068, 0x8dff,
+	0x0198, 0x68a0, 0xa406, 0x0118, 0x6854, 0x2068, 0x0cc0, 0x6010,
+	0x2060, 0x643c, 0x6540, 0x6648, 0x2d60, 0x080c, 0x4f8e, 0x0120,
+	0x080c, 0x7dfb, 0xa085, 0x0001, 0x012e, 0x000e, 0x004e, 0x005e,
+	0x006e, 0x00ce, 0x00de, 0x00ee, 0x0005, 0x20a1, 0x020b, 0x080c,
+	0x7363, 0x20a3, 0x1200, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x781c,
+	0xa086, 0x0004, 0x1110, 0x6098, 0x0018, 0x2001, 0xb114, 0x2004,
+	0x20a2, 0x7834, 0x20a2, 0x7838, 0x20a2, 0x20a9, 0x0010, 0xa006,
+	0x20a2, 0x1f04, 0x7b88, 0x20a2, 0x20a2, 0x60c3, 0x002c, 0x080c,
+	0x7a79, 0x0005, 0x0156, 0x0146, 0x20a1, 0x020b, 0x080c, 0x7363,
+	0x20a3, 0x0f00, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x7808, 0x20a2,
+	0x60c3, 0x0008, 0x080c, 0x7a79, 0x014e, 0x015e, 0x0005, 0x0156,
+	0x0146, 0x20a1, 0x020b, 0x080c, 0x73ff, 0x20a3, 0x0200, 0x20a3,
+	0x0000, 0x20a9, 0x0006, 0x2011, 0xb140, 0x2019, 0xb141, 0x23a6,
+	0x22a6, 0xa398, 0x0002, 0xa290, 0x0002, 0x1f04, 0x7bb7, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x60c3, 0x001c, 0x080c, 0x7a79, 0x014e,
+	0x015e, 0x0005, 0x0156, 0x0146, 0x0016, 0x0026, 0x20a1, 0x020b,
+	0x080c, 0x73d8, 0x080c, 0x73ee, 0x7810, 0xa080, 0x0000, 0x2004,
+	0xa080, 0x0015, 0x2098, 0x7808, 0xa088, 0x0002, 0x21a8, 0x53a6,
+	0xa080, 0x0004, 0x8003, 0x60c2, 0x080c, 0x7a79, 0x002e, 0x001e,
+	0x014e, 0x015e, 0x0005, 0x0156, 0x0146, 0x20a1, 0x020b, 0x080c,
+	0x7363, 0x20a3, 0x6200, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x7808,
+	0x20a2, 0x60c3, 0x0008, 0x080c, 0x7a79, 0x014e, 0x015e, 0x0005,
+	0x0156, 0x0146, 0x0016, 0x0026, 0x20a1, 0x020b, 0x080c, 0x7363,
+	0x7810, 0xa080, 0x0000, 0x2004, 0xa080, 0x0017, 0x2098, 0x7808,
+	0xa088, 0x0002, 0x21a8, 0x53a6, 0x8003, 0x60c2, 0x080c, 0x7a79,
+	0x002e, 0x001e, 0x014e, 0x015e, 0x0005, 0x00e6, 0x00c6, 0x0006,
+	0x0126, 0x2091, 0x8000, 0x2071, 0xb3d9, 0x700c, 0x2060, 0x8cff,
+	0x0178, 0x080c, 0x9a66, 0x1110, 0x080c, 0x8890, 0x600c, 0x0006,
+	0x080c, 0x9c2d, 0x080c, 0x82eb, 0x080c, 0x7dfb, 0x00ce, 0x0c78,
+	0x700f, 0x0000, 0x700b, 0x0000, 0x012e, 0x000e, 0x00ce, 0x00ee,
+	0x0005, 0x0126, 0x0156, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0026,
+	0x0016, 0x0006, 0x2091, 0x8000, 0x2069, 0x0100, 0x2079, 0x0140,
+	0x2071, 0xb3d9, 0x7024, 0x2060, 0x8cff, 0x05a0, 0x080c, 0x7a8c,
+	0x68c3, 0x0000, 0x080c, 0x67b6, 0x2009, 0x0013, 0x080c, 0x831a,
+	0x20a9, 0x01f4, 0x6824, 0xd094, 0x0158, 0x6827, 0x0004, 0x7804,
+	0xa084, 0x4000, 0x01a0, 0x7803, 0x1000, 0x7803, 0x0000, 0x0078,
+	0xd084, 0x0118, 0x6827, 0x0001, 0x0010, 0x1f04, 0x7c62, 0x7804,
+	0xa084, 0x1000, 0x0120, 0x7803, 0x0100, 0x7803, 0x0000, 0x6824,
+	0x000e, 0x001e, 0x002e, 0x00ce, 0x00de, 0x00ee, 0x00fe, 0x015e,
+	0x012e, 0x0005, 0x2001, 0xb100, 0x2004, 0xa096, 0x0001, 0x0550,
+	0xa096, 0x0004, 0x0538, 0x6817, 0x0008, 0x68c3, 0x0000, 0x2011,
+	0x494f, 0x080c, 0x6742, 0x20a9, 0x01f4, 0x6824, 0xd094, 0x0158,
+	0x6827, 0x0004, 0x7804, 0xa084, 0x4000, 0x01a0, 0x7803, 0x1000,
+	0x7803, 0x0000, 0x0078, 0xd084, 0x0118, 0x6827, 0x0001, 0x0010,
+	0x1f04, 0x7c9d, 0x7804, 0xa084, 0x1000, 0x0120, 0x7803, 0x0100,
+	0x7803, 0x0000, 0x000e, 0x001e, 0x002e, 0x00ce, 0x00de, 0x00ee,
+	0x00fe, 0x015e, 0x012e, 0x0005, 0x0126, 0x0156, 0x00f6, 0x00e6,
+	0x00d6, 0x00c6, 0x0026, 0x0016, 0x0006, 0x2091, 0x8000, 0x2069,
+	0x0100, 0x2079, 0x0140, 0x2071, 0xb3d9, 0x703c, 0x2060, 0x8cff,
+	0x0904, 0x7d48, 0x6814, 0xa084, 0x0002, 0x0904, 0x7d48, 0x68af,
+	0x95f5, 0x6817, 0x0010, 0x2009, 0x00fa, 0x8109, 0x1df0, 0x68c7,
+	0x0000, 0x68cb, 0x0008, 0x080c, 0x67c3, 0x080c, 0x2120, 0x0046,
+	0x2009, 0x017f, 0x200b, 0x00a5, 0x2021, 0x0169, 0x2404, 0xa084,
+	0x000f, 0xa086, 0x0004, 0x1500, 0x68af, 0x95f5, 0x68c7, 0x0000,
+	0x68cb, 0x0008, 0x00e6, 0x00f6, 0x2079, 0x0020, 0x2071, 0xb43a,
+	0x6814, 0xa084, 0x0184, 0xa085, 0x0012, 0x6816, 0x7803, 0x0008,
+	0x7003, 0x0000, 0x00fe, 0x00ee, 0xa386, 0x0002, 0x1128, 0x7884,
+	0xa005, 0x1110, 0x7887, 0x0001, 0x2001, 0xb3b0, 0x2004, 0x200a,
+	0x004e, 0xa39d, 0x0000, 0x1120, 0x2009, 0x0049, 0x080c, 0x831a,
+	0x20a9, 0x03e8, 0x6824, 0xd094, 0x0158, 0x6827, 0x0004, 0x7804,
+	0xa084, 0x4000, 0x01a0, 0x7803, 0x1000, 0x7803, 0x0000, 0x0078,
+	0xd08c, 0x0118, 0x6827, 0x0002, 0x0010, 0x1f04, 0x7d2a, 0x7804,
+	0xa084, 0x1000, 0x0120, 0x7803, 0x0100, 0x7803, 0x0000, 0x6824,
+	0x000e, 0x001e, 0x002e, 0x00ce, 0x00de, 0x00ee, 0x00fe, 0x015e,
+	0x012e, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x2069, 0xb3d9,
+	0x6a06, 0x012e, 0x00de, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000,
+	0x2069, 0xb3d9, 0x6a32, 0x012e, 0x00de, 0x0005, 0x00f6, 0x00e6,
+	0x00c6, 0x0066, 0x0006, 0x0126, 0x2071, 0xb3d9, 0x7614, 0x2660,
+	0x2678, 0x2091, 0x8000, 0x8cff, 0x0538, 0x601c, 0xa206, 0x1500,
+	0x7014, 0xac36, 0x1110, 0x660c, 0x7616, 0x7010, 0xac36, 0x1140,
+	0x2c00, 0xaf36, 0x0118, 0x2f00, 0x7012, 0x0010, 0x7013, 0x0000,
+	0x660c, 0x0066, 0x2c00, 0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678,
+	0x600f, 0x0000, 0x080c, 0x9a2b, 0x080c, 0x7dfb, 0x00ce, 0x08d8,
+	0x2c78, 0x600c, 0x2060, 0x08b8, 0x012e, 0x000e, 0x006e, 0x00ce,
+	0x00ee, 0x00fe, 0x0005, 0x0156, 0x0146, 0x20a1, 0x020b, 0x080c,
+	0x7624, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2, 0x20a2,
+	0x20a3, 0x1000, 0x0804, 0x7df3, 0x0156, 0x0146, 0x20a1, 0x020b,
+	0x080c, 0x7624, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a3, 0x4000, 0x0478, 0x0156, 0x0146, 0x20a1, 0x020b,
+	0x080c, 0x7624, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a3, 0x2000, 0x00f8, 0x0156, 0x0146, 0x20a1, 0x020b,
+	0x080c, 0x7624, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a3, 0x0400, 0x0078, 0x0156, 0x0146, 0x20a1, 0x020b,
+	0x080c, 0x7624, 0x7810, 0x20a2, 0xa006, 0x20a2, 0x20a2, 0x20a2,
+	0x20a2, 0x20a3, 0x0200, 0x0089, 0x60c3, 0x0020, 0x080c, 0x7a79,
+	0x014e, 0x015e, 0x0005, 0x00e6, 0x2071, 0xb3d9, 0x7020, 0xa005,
+	0x0110, 0x8001, 0x7022, 0x00ee, 0x0005, 0x20a9, 0x0008, 0x20a2,
+	0x1f04, 0x7e07, 0x20a2, 0x20a2, 0x0005, 0x00f6, 0x00e6, 0x00d6,
+	0x00c6, 0x0076, 0x0066, 0x0006, 0x0126, 0x2091, 0x8000, 0x2071,
+	0xb3d9, 0x7614, 0x2660, 0x2678, 0x2039, 0x0001, 0x87ff, 0x0904,
+	0x7e97, 0x8cff, 0x0904, 0x7e97, 0x601c, 0xa086, 0x0006, 0x1904,
+	0x7e92, 0x88ff, 0x0138, 0x2800, 0xac06, 0x1904, 0x7e92, 0x2039,
+	0x0000, 0x0050, 0x6018, 0xa206, 0x1904, 0x7e92, 0x85ff, 0x0120,
+	0x6050, 0xa106, 0x1904, 0x7e92, 0x7024, 0xac06, 0x1538, 0x2069,
+	0x0100, 0x68c0, 0xa005, 0x01f0, 0x080c, 0x67b6, 0x6817, 0x0008,
+	0x68c3, 0x0000, 0x080c, 0x7f1b, 0x7027, 0x0000, 0x0036, 0x2069,
+	0x0140, 0x6b04, 0xa384, 0x1000, 0x0120, 0x6803, 0x0100, 0x6803,
+	0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0110, 0x6827, 0x0001,
+	0x003e, 0x0020, 0x6003, 0x0009, 0x630a, 0x0460, 0x7014, 0xac36,
+	0x1110, 0x660c, 0x7616, 0x7010, 0xac36, 0x1140, 0x2c00, 0xaf36,
+	0x0118, 0x2f00, 0x7012, 0x0010, 0x7013, 0x0000, 0x660c, 0x0066,
+	0x2c00, 0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x89ff, 0x1158,
+	0x600f, 0x0000, 0x6010, 0x2068, 0x080c, 0x986a, 0x0110, 0x080c,
+	0xac5f, 0x080c, 0x9a2b, 0x080c, 0x7dfb, 0x88ff, 0x1190, 0x00ce,
+	0x0804, 0x7e1e, 0x2c78, 0x600c, 0x2060, 0x0804, 0x7e1e, 0xa006,
+	0x012e, 0x000e, 0x006e, 0x007e, 0x00ce, 0x00de, 0x00ee, 0x00fe,
+	0x0005, 0x6017, 0x0000, 0x00ce, 0xa8c5, 0x0001, 0x0c88, 0x00f6,
+	0x00e6, 0x00d6, 0x00c6, 0x0066, 0x0026, 0x0006, 0x0126, 0x2091,
+	0x8000, 0x2071, 0xb3d9, 0x7638, 0x2660, 0x2678, 0x8cff, 0x0904,
+	0x7f0b, 0x601c, 0xa086, 0x0006, 0x1904, 0x7f06, 0x87ff, 0x0128,
+	0x2700, 0xac06, 0x1904, 0x7f06, 0x0040, 0x6018, 0xa206, 0x15f0,
+	0x85ff, 0x0118, 0x6050, 0xa106, 0x15c8, 0x703c, 0xac06, 0x1170,
+	0x0036, 0x2019, 0x0001, 0x080c, 0x7cc4, 0x7033, 0x0000, 0x703f,
+	0x0000, 0x7043, 0x0000, 0x7047, 0x0000, 0x003e, 0x7038, 0xac36,
+	0x1110, 0x660c, 0x763a, 0x7034, 0xac36, 0x1140, 0x2c00, 0xaf36,
+	0x0118, 0x2f00, 0x7036, 0x0010, 0x7037, 0x0000, 0x660c, 0x0066,
+	0x2c00, 0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000,
+	0x6010, 0x2068, 0x080c, 0x986a, 0x0110, 0x080c, 0xac5f, 0x080c,
+	0x9a2b, 0x87ff, 0x1190, 0x00ce, 0x0804, 0x7eb6, 0x2c78, 0x600c,
+	0x2060, 0x0804, 0x7eb6, 0xa006, 0x012e, 0x000e, 0x002e, 0x006e,
+	0x00ce, 0x00de, 0x00ee, 0x00fe, 0x0005, 0x6017, 0x0000, 0x00ce,
+	0xa7bd, 0x0001, 0x0c88, 0x00e6, 0x2071, 0xb3d9, 0x2001, 0xb100,
+	0x2004, 0xa086, 0x0002, 0x1118, 0x7007, 0x0005, 0x0010, 0x7007,
+	0x0000, 0x00ee, 0x0005, 0x00f6, 0x00e6, 0x00c6, 0x0066, 0x0026,
+	0x0006, 0x0126, 0x2091, 0x8000, 0x2071, 0xb3d9, 0x2c10, 0x7638,
+	0x2660, 0x2678, 0x8cff, 0x0518, 0x2200, 0xac06, 0x11e0, 0x7038,
+	0xac36, 0x1110, 0x660c, 0x763a, 0x7034, 0xac36, 0x1140, 0x2c00,
+	0xaf36, 0x0118, 0x2f00, 0x7036, 0x0010, 0x7037, 0x0000, 0x660c,
+	0x2c00, 0xaf06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000,
+	0xa085, 0x0001, 0x0020, 0x2c78, 0x600c, 0x2060, 0x08d8, 0x012e,
+	0x000e, 0x002e, 0x006e, 0x00ce, 0x00ee, 0x00fe, 0x0005, 0x00f6,
+	0x00e6, 0x00d6, 0x00c6, 0x0066, 0x0006, 0x0126, 0x2091, 0x8000,
+	0x2071, 0xb3d9, 0x760c, 0x2660, 0x2678, 0x8cff, 0x0904, 0x7ff1,
+	0x6018, 0xa080, 0x0028, 0x2004, 0xa206, 0x1904, 0x7fec, 0x7024,
+	0xac06, 0x1508, 0x2069, 0x0100, 0x68c0, 0xa005, 0x0904, 0x7fc8,
+	0x080c, 0x7a8c, 0x68c3, 0x0000, 0x080c, 0x7f1b, 0x7027, 0x0000,
+	0x0036, 0x2069, 0x0140, 0x6b04, 0xa384, 0x1000, 0x0120, 0x6803,
+	0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0110,
+	0x6827, 0x0001, 0x003e, 0x700c, 0xac36, 0x1110, 0x660c, 0x760e,
+	0x7008, 0xac36, 0x1140, 0x2c00, 0xaf36, 0x0118, 0x2f00, 0x700a,
+	0x0010, 0x700b, 0x0000, 0x660c, 0x0066, 0x2c00, 0xaf06, 0x0110,
+	0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000, 0x080c, 0x9a55, 0x1158,
+	0x080c, 0x2b99, 0x080c, 0x9a66, 0x11f0, 0x080c, 0x8890, 0x00d8,
+	0x080c, 0x7f1b, 0x08c0, 0x080c, 0x9a66, 0x1118, 0x080c, 0x8890,
+	0x0090, 0x6010, 0x2068, 0x080c, 0x986a, 0x0168, 0x601c, 0xa086,
+	0x0003, 0x11f8, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c,
+	0x5271, 0x080c, 0x9a1f, 0x080c, 0x9c2d, 0x080c, 0x9a2b, 0x080c,
+	0x7dfb, 0x00ce, 0x0804, 0x7f75, 0x2c78, 0x600c, 0x2060, 0x0804,
+	0x7f75, 0x012e, 0x000e, 0x006e, 0x00ce, 0x00de, 0x00ee, 0x00fe,
+	0x0005, 0x601c, 0xa086, 0x0006, 0x1d30, 0x080c, 0xac5f, 0x0c18,
+	0x0036, 0x0156, 0x0136, 0x0146, 0x3908, 0xa006, 0xa190, 0x0020,
+	0x221c, 0xa39e, 0x2990, 0x1118, 0x8210, 0x8000, 0x0cc8, 0xa005,
+	0x0138, 0x20a9, 0x0020, 0x2198, 0xa110, 0x22a0, 0x22c8, 0x53a3,
+	0x014e, 0x013e, 0x015e, 0x003e, 0x0005, 0x00d6, 0x20a1, 0x020b,
+	0x080c, 0x73ff, 0x20a3, 0x0200, 0x20a3, 0x0014, 0x60c3, 0x0014,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x2099, 0xb3b8, 0x20a9, 0x0004,
+	0x53a6, 0x20a3, 0x0004, 0x20a3, 0x7878, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x080c, 0x7a79, 0x00de, 0x0005, 0x20a1, 0x020b, 0x080c,
+	0x73ff, 0x20a3, 0x0214, 0x20a3, 0x0018, 0x20a3, 0x0800, 0x7810,
+	0xa084, 0xff00, 0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x20a3, 0x0000, 0x7810, 0xa084, 0x00ff, 0x20a2, 0x7828,
+	0x20a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0018, 0x080c,
+	0x7a79, 0x0005, 0x00d6, 0x0016, 0x2f68, 0x2009, 0x0035, 0x080c,
+	0x9d16, 0x1904, 0x80d0, 0x20a1, 0x020b, 0x080c, 0x7363, 0x20a3,
+	0x1300, 0x20a3, 0x0000, 0x7828, 0x2068, 0x681c, 0xa086, 0x0003,
+	0x0580, 0x7818, 0xa080, 0x0028, 0x2014, 0x2001, 0xb134, 0x2004,
+	0xd0ac, 0x11d0, 0xa286, 0x007e, 0x1128, 0x20a3, 0x00ff, 0x20a3,
+	0xfffe, 0x04b8, 0xa286, 0x007f, 0x1128, 0x20a3, 0x00ff, 0x20a3,
+	0xfffd, 0x0478, 0xd2bc, 0x0180, 0xa286, 0x0080, 0x1128, 0x20a3,
+	0x00ff, 0x20a3, 0xfffc, 0x0428, 0xa2e8, 0xb235, 0x2d6c, 0x6810,
+	0x20a2, 0x6814, 0x20a2, 0x00e8, 0x20a3, 0x0000, 0x6098, 0x20a2,
+	0x00c0, 0x2001, 0xb134, 0x2004, 0xd0ac, 0x1138, 0x7818, 0xa080,
+	0x0028, 0x2004, 0xa082, 0x007e, 0x0240, 0x00d6, 0x2069, 0xb11b,
+	0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0020, 0x20a3, 0x0000, 0x6034,
+	0x20a2, 0x7834, 0x20a2, 0x7838, 0x20a2, 0x20a3, 0x0000, 0x20a3,
+	0x0000, 0x60c3, 0x000c, 0x080c, 0x7a79, 0x001e, 0x00de, 0x0005,
+	0x7817, 0x0001, 0x7803, 0x0006, 0x001e, 0x00de, 0x0005, 0x00d6,
+	0x0026, 0x7928, 0x2168, 0x691c, 0xa186, 0x0006, 0x01c0, 0xa186,
+	0x0003, 0x0904, 0x8146, 0xa186, 0x0005, 0x0904, 0x812f, 0xa186,
+	0x0004, 0x05b8, 0xa186, 0x0008, 0x0904, 0x8137, 0x7807, 0x0037,
+	0x7813, 0x1700, 0x080c, 0x81ae, 0x002e, 0x00de, 0x0005, 0x080c,
+	0x816a, 0x2009, 0x4000, 0x6800, 0x0002, 0x8110, 0x811b, 0x8112,
+	0x811b, 0x8117, 0x8110, 0x8110, 0x811b, 0x811b, 0x811b, 0x811b,
+	0x8110, 0x8110, 0x8110, 0x8110, 0x8110, 0x811b, 0x8110, 0x811b,
+	0x080c, 0x14fa, 0x6820, 0xd0e4, 0x0110, 0xd0cc, 0x0110, 0xa00e,
+	0x0010, 0x2009, 0x2000, 0x6828, 0x20a2, 0x682c, 0x20a2, 0x0804,
+	0x8160, 0x080c, 0x816a, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x2009,
+	0x4000, 0x6a00, 0xa286, 0x0002, 0x1108, 0xa00e, 0x0488, 0x04d1,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x2009, 0x4000, 0x0448, 0x0491,
+	0x20a3, 0x0000, 0x20a3, 0x0000, 0x2009, 0x4000, 0xa286, 0x0005,
+	0x0118, 0xa286, 0x0002, 0x1108, 0xa00e, 0x00d0, 0x0419, 0x6810,
+	0x2068, 0x697c, 0x6810, 0xa112, 0x6980, 0x6814, 0xa103, 0x20a2,
+	0x22a2, 0x7928, 0xa180, 0x0000, 0x2004, 0xa08e, 0x0002, 0x0130,
+	0xa08e, 0x0004, 0x0118, 0x2009, 0x4000, 0x0010, 0x2009, 0x0000,
+	0x21a2, 0x20a3, 0x0000, 0x60c3, 0x0018, 0x080c, 0x7a79, 0x002e,
+	0x00de, 0x0005, 0x0036, 0x0046, 0x0056, 0x0066, 0x20a1, 0x020b,
+	0x080c, 0x73ff, 0xa006, 0x20a3, 0x0200, 0x20a2, 0x7934, 0x21a2,
+	0x7938, 0x21a2, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134,
+	0x2214, 0xd2ac, 0x1118, 0xa092, 0x007e, 0x0268, 0x00d6, 0x2069,
+	0xb11b, 0x2d2c, 0x8d68, 0x2d34, 0xa0e8, 0xb235, 0x2d6c, 0x6b10,
+	0x6c14, 0x00de, 0x0030, 0x2019, 0x0000, 0x6498, 0x2029, 0x0000,
+	0x6634, 0x7828, 0xa080, 0x0007, 0x2004, 0xa086, 0x0003, 0x1128,
+	0x25a2, 0x26a2, 0x23a2, 0x24a2, 0x0020, 0x23a2, 0x24a2, 0x25a2,
+	0x26a2, 0x006e, 0x005e, 0x004e, 0x003e, 0x0005, 0x20a1, 0x020b,
+	0x080c, 0x73ff, 0x20a3, 0x0100, 0x20a3, 0x0000, 0x20a3, 0x0009,
+	0x7810, 0x20a2, 0x60c3, 0x0008, 0x080c, 0x7a79, 0x0005, 0x20a1,
+	0x020b, 0x080c, 0x735b, 0x20a3, 0x1400, 0x20a3, 0x0000, 0x7834,
+	0x20a2, 0x7838, 0x20a2, 0x7828, 0x20a2, 0x782c, 0x20a2, 0x7830,
+	0xa084, 0x00ff, 0x8007, 0x20a2, 0x20a3, 0x0000, 0x60c3, 0x0010,
+	0x080c, 0x7a79, 0x0005, 0x20a1, 0x020b, 0x080c, 0x73f7, 0x20a3,
+	0x0100, 0x20a3, 0x0000, 0x7828, 0x20a2, 0x7810, 0x20a2, 0x60c3,
+	0x0008, 0x080c, 0x7a79, 0x0005, 0x0146, 0x20a1, 0x020b, 0x0031,
+	0x60c3, 0x0000, 0x080c, 0x7a79, 0x014e, 0x0005, 0x20e1, 0x9080,
+	0x20e1, 0x4000, 0x7818, 0xa080, 0x0028, 0x2004, 0x2011, 0xb134,
+	0x2214, 0xd2ac, 0x1110, 0xd0bc, 0x0188, 0x00d6, 0xa0e8, 0xb235,
+	0x2d6c, 0x6810, 0xa085, 0x0300, 0x20a2, 0x6814, 0x20a2, 0x2069,
+	0xb11b, 0x2da6, 0x8d68, 0x2da6, 0x00de, 0x0078, 0x00d6, 0xa0e8,
+	0xb235, 0x2d6c, 0x6810, 0xa085, 0x0300, 0x20a2, 0x6814, 0x20a2,
+	0x00de, 0x20a3, 0x0000, 0x6234, 0x22a2, 0x20a3, 0x0819, 0x20a3,
+	0x0000, 0x080c, 0x7a68, 0x22a2, 0x20a3, 0x0000, 0x2fa2, 0x7a08,
+	0x22a2, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x0005, 0x20a1, 0x020b,
+	0x0079, 0x7910, 0x21a2, 0x20a3, 0x0000, 0x60c3, 0x0000, 0x20e1,
+	0x9080, 0x60a7, 0x9575, 0x080c, 0x7a83, 0x080c, 0x67ad, 0x0005,
+	0x0156, 0x0136, 0x0036, 0x00d6, 0x00e6, 0x20e1, 0x9080, 0x20e1,
+	0x4000, 0x7854, 0x2068, 0xadf0, 0x000f, 0x7210, 0xa296, 0x00c0,
+	0xa294, 0xfffd, 0x7212, 0x7214, 0xa294, 0x0300, 0x7216, 0x7100,
+	0xa194, 0x00ff, 0x7308, 0xa384, 0x00ff, 0xa08d, 0xc200, 0x7102,
+	0xa384, 0xff00, 0xa215, 0x720a, 0x7004, 0x720c, 0x700e, 0x7206,
+	0x20a9, 0x000a, 0x2e98, 0x53a6, 0x60a3, 0x0035, 0x6a38, 0xa294,
+	0x7000, 0xa286, 0x3000, 0x0110, 0x60a3, 0x0037, 0x00ee, 0x00de,
+	0x003e, 0x013e, 0x015e, 0x0005, 0x2009, 0x0092, 0x0010, 0x2009,
+	0x0096, 0x60ab, 0x0036, 0x6116, 0x0005, 0x2061, 0xb800, 0x2a70,
+	0x7064, 0x7046, 0x704b, 0xb800, 0x0005, 0x00e6, 0x0126, 0x2071,
+	0xb100, 0x2091, 0x8000, 0x7544, 0xa582, 0x0010, 0x0608, 0x7048,
+	0x2060, 0x6000, 0xa086, 0x0000, 0x0148, 0xace0, 0x0018, 0x7058,
+	0xac02, 0x1208, 0x0cb0, 0x2061, 0xb800, 0x0c98, 0x6003, 0x0008,
+	0x8529, 0x7546, 0xaca8, 0x0018, 0x7058, 0xa502, 0x1230, 0x754a,
+	0xa085, 0x0001, 0x012e, 0x00ee, 0x0005, 0x704b, 0xb800, 0x0cc0,
+	0xa006, 0x0cc0, 0x00e6, 0x2071, 0xb100, 0x7544, 0xa582, 0x0010,
+	0x0600, 0x7048, 0x2060, 0x6000, 0xa086, 0x0000, 0x0148, 0xace0,
+	0x0018, 0x7058, 0xac02, 0x1208, 0x0cb0, 0x2061, 0xb800, 0x0c98,
+	0x6003, 0x0008, 0x8529, 0x7546, 0xaca8, 0x0018, 0x7058, 0xa502,
+	0x1228, 0x754a, 0xa085, 0x0001, 0x00ee, 0x0005, 0x704b, 0xb800,
+	0x0cc8, 0xa006, 0x0cc8, 0xac82, 0xb800, 0x0a0c, 0x14fa, 0x2001,
+	0xb116, 0x2004, 0xac02, 0x1a0c, 0x14fa, 0xa006, 0x6006, 0x600a,
+	0x600e, 0x6012, 0x6016, 0x601a, 0x601f, 0x0000, 0x6003, 0x0000,
+	0x6052, 0x6056, 0x6022, 0x6026, 0x602a, 0x602e, 0x6032, 0x6036,
+	0x603a, 0x603e, 0x2061, 0xb100, 0x6044, 0x8000, 0x6046, 0xa086,
+	0x0001, 0x0108, 0x0005, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e,
+	0x012e, 0x0cc0, 0x601c, 0xa084, 0x000f, 0x0002, 0x8329, 0x8338,
+	0x8353, 0x836e, 0x9d43, 0x9d5e, 0x9d79, 0x8329, 0x8338, 0x8329,
+	0x8389, 0xa186, 0x0013, 0x1128, 0x080c, 0x6dc1, 0x080c, 0x6e9e,
+	0x0005, 0xa18e, 0x0047, 0x1118, 0xa016, 0x080c, 0x1828, 0x0005,
+	0x0066, 0x6000, 0xa0b2, 0x0010, 0x1a0c, 0x14fa, 0x0013, 0x006e,
+	0x0005, 0x8351, 0x8722, 0x88ca, 0x8351, 0x893f, 0x8442, 0x8351,
+	0x8351, 0x86b4, 0x8d40, 0x8351, 0x8351, 0x8351, 0x8351, 0x8351,
+	0x8351, 0x080c, 0x14fa, 0x0066, 0x6000, 0xa0b2, 0x0010, 0x1a0c,
+	0x14fa, 0x0013, 0x006e, 0x0005, 0x836c, 0x935a, 0x836c, 0x836c,
+	0x836c, 0x836c, 0x836c, 0x836c, 0x9305, 0x94c0, 0x836c, 0x9387,
+	0x93fe, 0x9387, 0x93fe, 0x836c, 0x080c, 0x14fa, 0x0066, 0x6000,
+	0xa0b2, 0x0010, 0x1a0c, 0x14fa, 0x0013, 0x006e, 0x0005, 0x8387,
+	0x8d81, 0x8e47, 0x8f75, 0x90cf, 0x8387, 0x8387, 0x8387, 0x8d5b,
+	0x92b5, 0x92b8, 0x8387, 0x8387, 0x8387, 0x8387, 0x92e2, 0x080c,
+	0x14fa, 0x0066, 0x6000, 0xa0b2, 0x0010, 0x1a0c, 0x14fa, 0x0013,
+	0x006e, 0x0005, 0x83a2, 0x83a2, 0x83a2, 0x83c5, 0x8418, 0x83a2,
+	0x83a2, 0x83a2, 0x83a4, 0x83a2, 0x83a2, 0x83a2, 0x83a2, 0x83a2,
+	0x83a2, 0x83a2, 0x080c, 0x14fa, 0xa186, 0x0003, 0x190c, 0x14fa,
+	0x00d6, 0x6003, 0x0003, 0x6106, 0x6010, 0x2068, 0x684f, 0x0040,
+	0x687c, 0x680a, 0x6880, 0x680e, 0x6813, 0x0000, 0x6817, 0x0000,
+	0x00de, 0x2c10, 0x080c, 0x1ec4, 0x080c, 0x6a59, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x6f5b, 0x012e, 0x0005, 0xa182, 0x0047, 0x0002,
+	0x83d1, 0x83d1, 0x83d3, 0x83f2, 0x83d1, 0x83d1, 0x83d1, 0x83d1,
+	0x8404, 0x080c, 0x14fa, 0x00d6, 0x0016, 0x080c, 0x6e53, 0x080c,
+	0x6f5b, 0x6003, 0x0004, 0x6110, 0x2168, 0x6854, 0x8003, 0x800b,
+	0x810b, 0xa108, 0x6116, 0x684f, 0x0020, 0x685c, 0x685a, 0x6874,
+	0x687e, 0x6878, 0x6882, 0x6897, 0x0000, 0x689b, 0x0000, 0x001e,
+	0x00de, 0x0005, 0x080c, 0x6e53, 0x00d6, 0x6110, 0x2168, 0x080c,
+	0x986a, 0x0120, 0x684b, 0x0006, 0x080c, 0x5271, 0x00de, 0x080c,
+	0x82eb, 0x080c, 0x6f5b, 0x0005, 0x080c, 0x6e53, 0x080c, 0x2b73,
+	0x00d6, 0x6110, 0x2168, 0x080c, 0x986a, 0x0120, 0x684b, 0x0029,
+	0x080c, 0x5271, 0x00de, 0x080c, 0x82eb, 0x080c, 0x6f5b, 0x0005,
+	0xa182, 0x0047, 0x0002, 0x8426, 0x8435, 0x8424, 0x8424, 0x8424,
+	0x8424, 0x8424, 0x8424, 0x8424, 0x080c, 0x14fa, 0x00d6, 0x6010,
+	0x2068, 0x684c, 0xc0f4, 0x684e, 0x00de, 0x20e1, 0x0005, 0x3d18,
+	0x3e20, 0x2c10, 0x080c, 0x1828, 0x0005, 0x00d6, 0x6110, 0x2168,
+	0x684b, 0x0000, 0x6853, 0x0000, 0x080c, 0x5271, 0x00de, 0x080c,
+	0x82eb, 0x0005, 0xa1b6, 0x0015, 0x1118, 0x080c, 0x82eb, 0x0030,
+	0xa1b6, 0x0016, 0x190c, 0x14fa, 0x080c, 0x82eb, 0x0005, 0x20a9,
+	0x000e, 0x2e98, 0x6010, 0x20a0, 0x53a3, 0x20a9, 0x0006, 0x3310,
+	0x3420, 0x9398, 0x94a0, 0x3318, 0x3428, 0x222e, 0x2326, 0xa290,
+	0x0002, 0xa5a8, 0x0002, 0xa398, 0x0002, 0xa4a0, 0x0002, 0x1f04,
+	0x845d, 0x00e6, 0x080c, 0x986a, 0x0130, 0x6010, 0x2070, 0x7007,
+	0x0000, 0x7037, 0x0103, 0x00ee, 0x080c, 0x82eb, 0x0005, 0x00d6,
+	0x0036, 0x7330, 0xa386, 0x0200, 0x1130, 0x6018, 0x2068, 0x6813,
+	0x00ff, 0x6817, 0xfffd, 0x6010, 0xa005, 0x0130, 0x2068, 0x6807,
+	0x0000, 0x6837, 0x0103, 0x6b32, 0x080c, 0x82eb, 0x003e, 0x00de,
+	0x0005, 0x0016, 0x20a9, 0x002a, 0xae80, 0x000c, 0x2098, 0x6010,
+	0xa080, 0x0002, 0x20a0, 0x53a3, 0x20a9, 0x002a, 0x6010, 0xa080,
+	0x0001, 0x2004, 0xa080, 0x0002, 0x20a0, 0x53a3, 0x00e6, 0x6010,
+	0x2004, 0x2070, 0x7037, 0x0103, 0x00ee, 0x080c, 0x82eb, 0x001e,
+	0x0005, 0x0016, 0x2009, 0x0000, 0x7030, 0xa086, 0x0100, 0x0140,
+	0x7038, 0xa084, 0x00ff, 0x808e, 0x703c, 0xa084, 0x00ff, 0x8086,
+	0xa080, 0x0004, 0xa108, 0x21a8, 0xae80, 0x000c, 0x2098, 0x6010,
+	0xa080, 0x0002, 0x20a0, 0x080c, 0x4a04, 0x00e6, 0x080c, 0x986a,
+	0x0140, 0x6010, 0x2070, 0x7007, 0x0000, 0x7034, 0x70b2, 0x7037,
+	0x0103, 0x00ee, 0x080c, 0x82eb, 0x001e, 0x0005, 0x00e6, 0x00d6,
+	0x603f, 0x0000, 0x2c68, 0x0016, 0x2009, 0x0035, 0x080c, 0x9d16,
+	0x001e, 0x1168, 0x0026, 0x6228, 0x2268, 0x002e, 0x2071, 0xb68c,
+	0x6b1c, 0xa386, 0x0003, 0x0130, 0xa386, 0x0006, 0x0128, 0x080c,
+	0x82eb, 0x0020, 0x0031, 0x0010, 0x080c, 0x85ba, 0x00de, 0x00ee,
+	0x0005, 0x00f6, 0x6810, 0x2078, 0xa186, 0x0015, 0x0904, 0x85a3,
+	0xa18e, 0x0016, 0x1904, 0x85b8, 0x700c, 0xa084, 0xff00, 0xa086,
+	0x1700, 0x1904, 0x8582, 0x8fff, 0x1138, 0x6800, 0xa086, 0x000f,
+	0x0904, 0x8566, 0x0804, 0x85b6, 0x6808, 0xa086, 0xffff, 0x1904,
+	0x85a5, 0x784c, 0xa084, 0x0060, 0xa086, 0x0020, 0x1150, 0x797c,
+	0x7810, 0xa106, 0x1904, 0x85a5, 0x7980, 0x7814, 0xa106, 0x1904,
+	0x85a5, 0x080c, 0x9a1f, 0x6858, 0x7852, 0x784c, 0xc0dc, 0xc0f4,
+	0xc0d4, 0x784e, 0x0026, 0xa00e, 0x6a14, 0x2001, 0x000a, 0x080c,
+	0x68b3, 0x7854, 0xa20a, 0x0208, 0x8011, 0x7a56, 0x82ff, 0x002e,
+	0x1138, 0x00c6, 0x2d60, 0x080c, 0x963b, 0x00ce, 0x0804, 0x85b6,
+	0x00c6, 0x00d6, 0x2f68, 0x6838, 0xd0fc, 0x1118, 0x080c, 0x4ad9,
+	0x0010, 0x080c, 0x4cc1, 0x00de, 0x00ce, 0x1904, 0x85a5, 0x00c6,
+	0x2d60, 0x080c, 0x82eb, 0x00ce, 0x0804, 0x85b6, 0x00c6, 0x080c,
+	0x9ae4, 0x0190, 0x6013, 0x0000, 0x6818, 0x601a, 0x080c, 0x9c35,
+	0x601f, 0x0003, 0x6904, 0x00c6, 0x2d60, 0x080c, 0x82eb, 0x00ce,
+	0x080c, 0x831a, 0x00ce, 0x04d0, 0x2001, 0xb3b7, 0x2004, 0x683e,
+	0x00ce, 0x04a0, 0x7008, 0xa086, 0x000b, 0x11a0, 0x6018, 0x200c,
+	0xc1bc, 0x2102, 0x00c6, 0x2d60, 0x7853, 0x0003, 0x6007, 0x0085,
+	0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6, 0x080c, 0x6e9e,
+	0x00ce, 0x00e0, 0x700c, 0xa086, 0x2a00, 0x1138, 0x2001, 0xb3b7,
+	0x2004, 0x683e, 0x0098, 0x0471, 0x0098, 0x8fff, 0x090c, 0x14fa,
+	0x00c6, 0x00d6, 0x2d60, 0x2f68, 0x684b, 0x0003, 0x080c, 0x952f,
+	0x080c, 0x9a1f, 0x080c, 0x9a2b, 0x00de, 0x00ce, 0x080c, 0x82eb,
+	0x00fe, 0x0005, 0xa186, 0x0015, 0x1128, 0x2001, 0xb3b7, 0x2004,
+	0x683e, 0x0068, 0xa18e, 0x0016, 0x1160, 0x00c6, 0x2d00, 0x2060,
+	0x080c, 0xaf00, 0x080c, 0x6866, 0x080c, 0x82eb, 0x00ce, 0x080c,
+	0x82eb, 0x0005, 0x0026, 0x0036, 0x0046, 0x7228, 0x7c80, 0x7b7c,
+	0xd2f4, 0x0130, 0x2001, 0xb3b7, 0x2004, 0x683e, 0x0804, 0x8634,
+	0x00c6, 0x2d60, 0x080c, 0x954f, 0x00ce, 0x6804, 0xa086, 0x0050,
+	0x1168, 0x00c6, 0x2d00, 0x2060, 0x6003, 0x0001, 0x6007, 0x0050,
+	0x080c, 0x69f6, 0x080c, 0x6e9e, 0x00ce, 0x04f0, 0x6800, 0xa086,
+	0x000f, 0x01c8, 0x8fff, 0x090c, 0x14fa, 0x6820, 0xd0dc, 0x1198,
+	0x6800, 0xa086, 0x0004, 0x1198, 0x784c, 0xd0ac, 0x0180, 0x784c,
+	0xc0dc, 0xc0f4, 0x784e, 0x7850, 0xc0f4, 0xc0fc, 0x7852, 0x2001,
+	0x0001, 0x682e, 0x00e0, 0x2001, 0x0007, 0x682e, 0x00c0, 0x784c,
+	0xd0b4, 0x1130, 0xd0ac, 0x0db8, 0x784c, 0xd0f4, 0x1da0, 0x0c38,
+	0xd2ec, 0x1d88, 0x7024, 0xa306, 0x1118, 0x7020, 0xa406, 0x0d58,
+	0x7020, 0x6836, 0x7024, 0x683a, 0x2001, 0x0005, 0x682e, 0x080c,
+	0x9b71, 0x080c, 0x6e9e, 0x0010, 0x080c, 0x82eb, 0x004e, 0x003e,
+	0x002e, 0x0005, 0x00e6, 0x00d6, 0x0026, 0x6034, 0x2068, 0x6a1c,
+	0xa286, 0x0007, 0x0904, 0x8698, 0xa286, 0x0002, 0x0904, 0x8698,
+	0xa286, 0x0000, 0x0904, 0x8698, 0x6808, 0x6338, 0xa306, 0x1904,
+	0x8698, 0x2071, 0xb68c, 0xa186, 0x0015, 0x05e0, 0xa18e, 0x0016,
+	0x1190, 0x6030, 0xa084, 0x00ff, 0xa086, 0x0001, 0x1160, 0x700c,
+	0xa086, 0x2a00, 0x1140, 0x6034, 0xa080, 0x0008, 0x200c, 0xc1dd,
+	0xc1f5, 0x2102, 0x0438, 0x00c6, 0x6034, 0x2060, 0x6104, 0xa186,
+	0x004b, 0x01a0, 0xa186, 0x004c, 0x0188, 0xa186, 0x004d, 0x0170,
+	0xa186, 0x004e, 0x0158, 0xa186, 0x0052, 0x0140, 0x6010, 0x2068,
+	0x080c, 0x986a, 0x090c, 0x14fa, 0x6853, 0x0003, 0x6007, 0x0085,
+	0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6, 0x080c, 0x6e9e,
+	0x00ce, 0x0030, 0x6034, 0x2070, 0x2001, 0xb3b7, 0x2004, 0x703e,
+	0x080c, 0x82eb, 0x002e, 0x00de, 0x00ee, 0x0005, 0x00d6, 0x20a9,
+	0x000e, 0x2e98, 0x6010, 0x20a0, 0x53a3, 0xa1b6, 0x0015, 0x1148,
+	0x6018, 0x2068, 0x7038, 0x680a, 0x703c, 0x680e, 0x6800, 0xc08d,
+	0x6802, 0x00de, 0x0804, 0x8469, 0x2100, 0xa1b2, 0x0080, 0x1a0c,
+	0x14fa, 0xa1b2, 0x0040, 0x1a04, 0x8718, 0x0002, 0x870c, 0x8700,
+	0x870c, 0x870c, 0x870c, 0x870c, 0x86fe, 0x86fe, 0x86fe, 0x86fe,
+	0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe,
+	0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe,
+	0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x870c, 0x86fe, 0x870c,
+	0x870c, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x870c, 0x86fe,
+	0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe,
+	0x870c, 0x870c, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe, 0x86fe,
+	0x86fe, 0x86fe, 0x86fe, 0x870c, 0x86fe, 0x86fe, 0x080c, 0x14fa,
+	0x6003, 0x0001, 0x6106, 0x080c, 0x6a3c, 0x0126, 0x2091, 0x8000,
+	0x080c, 0x6e9e, 0x012e, 0x0005, 0x6003, 0x0001, 0x6106, 0x080c,
+	0x6a3c, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e, 0x012e, 0x0005,
+	0x2600, 0x0002, 0x870c, 0x870c, 0x8720, 0x870c, 0x870c, 0x8720,
+	0x080c, 0x14fa, 0x6004, 0xa0b2, 0x0080, 0x1a0c, 0x14fa, 0xa1b6,
+	0x0013, 0x0904, 0x87c2, 0xa1b6, 0x0027, 0x1904, 0x8788, 0x080c,
+	0x6dc1, 0x6004, 0x080c, 0x9a55, 0x0188, 0x080c, 0x9a66, 0x0904,
+	0x8782, 0xa08e, 0x0021, 0x0904, 0x8785, 0xa08e, 0x0022, 0x0904,
+	0x8782, 0xa08e, 0x003d, 0x0904, 0x8785, 0x04a8, 0x080c, 0x2b99,
+	0x2001, 0x0007, 0x080c, 0x4d75, 0x6018, 0xa080, 0x0028, 0x200c,
+	0x080c, 0x8890, 0xa186, 0x007e, 0x1148, 0x2001, 0xb134, 0x2014,
+	0xc285, 0x080c, 0x58d5, 0x1108, 0xc2ad, 0x2202, 0x0016, 0x0026,
+	0x0036, 0x2110, 0x2019, 0x0028, 0x080c, 0x6b35, 0x0076, 0x2039,
+	0x0000, 0x080c, 0x6a6b, 0x00c6, 0x6018, 0xa065, 0x0110, 0x080c,
+	0x501c, 0x00ce, 0x2c08, 0x080c, 0xaa51, 0x007e, 0x003e, 0x002e,
+	0x001e, 0x080c, 0x4de4, 0x080c, 0x9c2d, 0x080c, 0x82eb, 0x080c,
+	0x6e9e, 0x0005, 0x080c, 0x8890, 0x0cb0, 0x080c, 0x88be, 0x0c98,
+	0xa186, 0x0014, 0x1db0, 0x080c, 0x6dc1, 0x080c, 0x2b73, 0x080c,
+	0x9a55, 0x1188, 0x080c, 0x2b99, 0x6018, 0xa080, 0x0028, 0x200c,
+	0x080c, 0x8890, 0xa186, 0x007e, 0x1128, 0x2001, 0xb134, 0x200c,
+	0xc185, 0x2102, 0x08c0, 0x080c, 0x9a66, 0x1118, 0x080c, 0x8890,
+	0x0890, 0x6004, 0xa08e, 0x0032, 0x1158, 0x00e6, 0x00f6, 0x2071,
+	0xb182, 0x2079, 0x0000, 0x080c, 0x2e97, 0x00fe, 0x00ee, 0x0818,
+	0x6004, 0xa08e, 0x0021, 0x0d50, 0xa08e, 0x0022, 0x090c, 0x8890,
+	0x0804, 0x877b, 0xa0b2, 0x0040, 0x1a04, 0x8885, 0x2008, 0x0002,
+	0x880a, 0x880b, 0x880e, 0x8811, 0x8814, 0x8817, 0x8808, 0x8808,
+	0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808,
+	0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808,
+	0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x881a, 0x8829,
+	0x8808, 0x882b, 0x8829, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808,
+	0x8829, 0x8829, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808, 0x8808,
+	0x8808, 0x8808, 0x8865, 0x8829, 0x8808, 0x8825, 0x8808, 0x8808,
+	0x8808, 0x8826, 0x8808, 0x8808, 0x8808, 0x8829, 0x885c, 0x8808,
+	0x080c, 0x14fa, 0x00f0, 0x2001, 0x000b, 0x0460, 0x2001, 0x0003,
+	0x0448, 0x2001, 0x0005, 0x0430, 0x2001, 0x0001, 0x0418, 0x2001,
+	0x0009, 0x0400, 0x080c, 0x6dc1, 0x6003, 0x0005, 0x2001, 0xb3b7,
+	0x2004, 0x603e, 0x080c, 0x6e9e, 0x00a0, 0x0018, 0x0010, 0x080c,
+	0x4d75, 0x0804, 0x8876, 0x080c, 0x6dc1, 0x2001, 0xb3b5, 0x2004,
+	0x6016, 0x2001, 0xb3b7, 0x2004, 0x603e, 0x6003, 0x0004, 0x080c,
+	0x6e9e, 0x0005, 0x080c, 0x4d75, 0x080c, 0x6dc1, 0x6003, 0x0002,
+	0x2001, 0xb3b7, 0x2004, 0x603e, 0x0036, 0x2019, 0xb15d, 0x2304,
+	0xa084, 0xff00, 0x1120, 0x2001, 0xb3b5, 0x201c, 0x0040, 0x8007,
+	0xa09a, 0x0004, 0x0ec0, 0x8003, 0x801b, 0x831b, 0xa318, 0x6316,
+	0x003e, 0x080c, 0x6e9e, 0x08e8, 0x080c, 0x6dc1, 0x080c, 0x9c2d,
+	0x080c, 0x82eb, 0x080c, 0x6e9e, 0x08a0, 0x00e6, 0x00f6, 0x2071,
+	0xb182, 0x2079, 0x0000, 0x080c, 0x2e97, 0x00fe, 0x00ee, 0x080c,
+	0x6dc1, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0818, 0x080c, 0x6dc1,
+	0x2001, 0xb3b7, 0x2004, 0x603e, 0x6003, 0x0002, 0x2001, 0xb3b5,
+	0x2004, 0x6016, 0x080c, 0x6e9e, 0x0005, 0x2600, 0x2008, 0x0002,
+	0x888e, 0x888e, 0x888e, 0x8876, 0x8876, 0x888e, 0x080c, 0x14fa,
+	0x00e6, 0x0026, 0x0016, 0x080c, 0x986a, 0x0508, 0x6010, 0x2070,
+	0x7034, 0xa086, 0x0139, 0x1148, 0x2001, 0x0030, 0x2009, 0x0000,
+	0x2011, 0x4005, 0x080c, 0x9ce4, 0x0090, 0x7038, 0xd0fc, 0x0178,
+	0x7007, 0x0000, 0x0016, 0x6004, 0xa08e, 0x0021, 0x0160, 0xa08e,
+	0x003d, 0x0148, 0x001e, 0x7037, 0x0103, 0x7033, 0x0100, 0x001e,
+	0x002e, 0x00ee, 0x0005, 0x001e, 0x0009, 0x0cc8, 0x00e6, 0xacf0,
+	0x0004, 0x2e74, 0x7000, 0x2070, 0x7037, 0x0103, 0x7023, 0x8001,
+	0x00ee, 0x0005, 0x00d6, 0x6618, 0x2668, 0x6804, 0xa084, 0x00ff,
+	0x00de, 0xa0b2, 0x000c, 0x1a0c, 0x14fa, 0x6604, 0xa6b6, 0x0043,
+	0x1120, 0x080c, 0x9ca0, 0x0804, 0x892f, 0x6604, 0xa6b6, 0x0033,
+	0x1120, 0x080c, 0x9c50, 0x0804, 0x892f, 0x6604, 0xa6b6, 0x0028,
+	0x1120, 0x080c, 0x9a96, 0x0804, 0x892f, 0x6604, 0xa6b6, 0x0029,
+	0x1118, 0x080c, 0x9aad, 0x04d8, 0x6604, 0xa6b6, 0x001f, 0x1118,
+	0x080c, 0x844f, 0x04a0, 0x6604, 0xa6b6, 0x0000, 0x1118, 0x080c,
+	0x869e, 0x0468, 0x6604, 0xa6b6, 0x0022, 0x1118, 0x080c, 0x8477,
+	0x0430, 0x6604, 0xa6b6, 0x0035, 0x1118, 0x080c, 0x84de, 0x00f8,
+	0x6604, 0xa6b6, 0x0039, 0x1118, 0x080c, 0x863a, 0x00c0, 0x6604,
+	0xa6b6, 0x003d, 0x1118, 0x080c, 0x8491, 0x0088, 0x6604, 0xa6b6,
+	0x0044, 0x1118, 0x080c, 0x84b1, 0x0050, 0xa1b6, 0x0015, 0x1110,
+	0x0053, 0x0028, 0xa1b6, 0x0016, 0x1118, 0x0804, 0x8aeb, 0x0005,
+	0x080c, 0x8331, 0x0ce0, 0x8956, 0x8959, 0x8956, 0x899b, 0x8956,
+	0x8a78, 0x8af9, 0x8956, 0x8956, 0x8ac7, 0x8956, 0x8adb, 0xa1b6,
+	0x0048, 0x0140, 0x20e1, 0x0005, 0x3d18, 0x3e20, 0x2c10, 0x080c,
+	0x1828, 0x0005, 0x00e6, 0xacf0, 0x0004, 0x2e74, 0x7000, 0x2070,
+	0x7037, 0x0103, 0x00ee, 0x080c, 0x82eb, 0x0005, 0xe000, 0xe000,
+	0x0005, 0x00e6, 0x2071, 0xb100, 0x7080, 0xa086, 0x0074, 0x1530,
+	0x080c, 0xaa28, 0x11b0, 0x00d6, 0x6018, 0x2068, 0x7030, 0xd08c,
+	0x0128, 0x6800, 0xd0bc, 0x0110, 0xc0c5, 0x6802, 0x00d9, 0x00de,
+	0x2001, 0x0006, 0x080c, 0x4d75, 0x080c, 0x2b99, 0x080c, 0x82eb,
+	0x0078, 0x2001, 0x000a, 0x080c, 0x4d75, 0x080c, 0x2b99, 0x6003,
+	0x0001, 0x6007, 0x0001, 0x080c, 0x6a3c, 0x0010, 0x080c, 0x8a69,
+	0x00ee, 0x0005, 0x6800, 0xd084, 0x0168, 0x2001, 0x0000, 0x080c,
+	0x4d63, 0x2069, 0xb152, 0x6804, 0xd0a4, 0x0120, 0x2001, 0x0006,
+	0x080c, 0x4da2, 0x0005, 0x00d6, 0x2011, 0xb120, 0x2204, 0xa086,
+	0x0074, 0x1904, 0x8a66, 0x6018, 0x2068, 0x6aa0, 0xa286, 0x007e,
+	0x1120, 0x080c, 0x8bf7, 0x0804, 0x8a09, 0x080c, 0x8bed, 0x6018,
+	0x2068, 0xa080, 0x0028, 0x2014, 0xa286, 0x0080, 0x11c0, 0x6813,
+	0x00ff, 0x6817, 0xfffc, 0x6010, 0xa005, 0x0138, 0x2068, 0x6807,
+	0x0000, 0x6837, 0x0103, 0x6833, 0x0200, 0x2001, 0x0006, 0x080c,
+	0x4d75, 0x080c, 0x2b99, 0x080c, 0x82eb, 0x0804, 0x8a67, 0x00e6,
+	0x2071, 0xb134, 0x2e04, 0xd09c, 0x0188, 0x2071, 0xb680, 0x7108,
+	0x720c, 0xa18c, 0x00ff, 0x1118, 0xa284, 0xff00, 0x0138, 0x6018,
+	0x2070, 0x70a0, 0xd0bc, 0x1110, 0x7112, 0x7216, 0x00ee, 0x6010,
+	0xa005, 0x0198, 0x2068, 0x6838, 0xd0f4, 0x0178, 0x6834, 0xa084,
+	0x00ff, 0xa086, 0x0039, 0x1958, 0x2001, 0x0000, 0x2009, 0x0000,
+	0x2011, 0x4000, 0x080c, 0x9ce4, 0x0840, 0x2001, 0x0004, 0x080c,
+	0x4d75, 0x6003, 0x0001, 0x6007, 0x0003, 0x080c, 0x6a3c, 0x0804,
+	0x8a67, 0x685c, 0xd0e4, 0x01d8, 0x080c, 0x9be0, 0x080c, 0x58d5,
+	0x0118, 0xd0dc, 0x1904, 0x89c5, 0x2011, 0xb134, 0x2204, 0xc0ad,
+	0x2012, 0x2001, 0xb38f, 0x2004, 0x00f6, 0x2079, 0x0100, 0x78e3,
+	0x0000, 0x080c, 0x274b, 0x78e2, 0x00fe, 0x0804, 0x89c5, 0x080c,
+	0x9c16, 0x2011, 0xb134, 0x2204, 0xc0a5, 0x2012, 0x0006, 0x080c,
+	0xab41, 0x000e, 0x1904, 0x89c5, 0xc0b5, 0x2012, 0x2001, 0x0000,
+	0x080c, 0x4d63, 0x00c6, 0x2009, 0x00ef, 0x00f6, 0x2079, 0x0100,
+	0x79ea, 0x7932, 0x7936, 0x00fe, 0x080c, 0x2720, 0x00f6, 0x2079,
+	0xb100, 0x7972, 0x2100, 0x2009, 0x0000, 0x080c, 0x26f6, 0x794e,
+	0x00fe, 0x8108, 0x080c, 0x4dc5, 0x2c00, 0x00ce, 0x1904, 0x89c5,
+	0x601a, 0x2001, 0x0002, 0x080c, 0x4d75, 0x601f, 0x0001, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x080c, 0x6a3c, 0x0008, 0x0011, 0x00de,
+	0x0005, 0x2001, 0xb100, 0x2004, 0xa086, 0x0003, 0x0120, 0x2001,
+	0x0007, 0x080c, 0x4d75, 0x080c, 0x2b99, 0x080c, 0x82eb, 0x0005,
+	0x00e6, 0x0026, 0x0016, 0x2071, 0xb100, 0x7080, 0xa086, 0x0014,
+	0x15f0, 0x7000, 0xa086, 0x0003, 0x1128, 0x6010, 0xa005, 0x1110,
+	0x080c, 0x3dcd, 0x00d6, 0x6018, 0x2068, 0x080c, 0x4ebf, 0x080c,
+	0x898a, 0x00de, 0x080c, 0x8ca6, 0x1550, 0x00d6, 0x6018, 0x2068,
+	0x6890, 0x00de, 0xa005, 0x0518, 0x2001, 0x0006, 0x080c, 0x4d75,
+	0x00e6, 0x6010, 0xa075, 0x01a8, 0x7034, 0xa084, 0x00ff, 0xa086,
+	0x0039, 0x1148, 0x2001, 0x0000, 0x2009, 0x0000, 0x2011, 0x4000,
+	0x080c, 0x9ce4, 0x0030, 0x7007, 0x0000, 0x7037, 0x0103, 0x7033,
+	0x0200, 0x00ee, 0x080c, 0x2b99, 0x080c, 0x82eb, 0x0020, 0x080c,
+	0x8890, 0x080c, 0x8a69, 0x001e, 0x002e, 0x00ee, 0x0005, 0x2011,
+	0xb120, 0x2204, 0xa086, 0x0014, 0x1158, 0x2001, 0x0002, 0x080c,
+	0x4d75, 0x6003, 0x0001, 0x6007, 0x0001, 0x080c, 0x6a3c, 0x0010,
+	0x080c, 0x8a69, 0x0005, 0x2011, 0xb120, 0x2204, 0xa086, 0x0004,
+	0x1138, 0x2001, 0x0007, 0x080c, 0x4d75, 0x080c, 0x82eb, 0x0010,
+	0x080c, 0x8a69, 0x0005, 0x000b, 0x0005, 0x8956, 0x8b00, 0x8956,
+	0x8b34, 0x8956, 0x8ba9, 0x8af9, 0x8956, 0x8956, 0x8bbc, 0x8956,
+	0x8bcc, 0x6604, 0xa6b6, 0x001e, 0x1110, 0x080c, 0x82eb, 0x0005,
+	0x00d6, 0x00c6, 0x080c, 0x8bdc, 0x1178, 0x2001, 0x0000, 0x080c,
+	0x4d63, 0x2001, 0x0002, 0x080c, 0x4d75, 0x6003, 0x0001, 0x6007,
+	0x0002, 0x080c, 0x6a3c, 0x00e8, 0x2009, 0xb68e, 0x2104, 0xa086,
+	0x0009, 0x1160, 0x6018, 0x2068, 0x6840, 0xa084, 0x00ff, 0xa005,
+	0x0170, 0x8001, 0x6842, 0x6017, 0x000a, 0x0058, 0x2009, 0xb68f,
+	0x2104, 0xa084, 0xff00, 0xa086, 0x1900, 0x1108, 0x08d0, 0x080c,
+	0x8a69, 0x00ce, 0x00de, 0x0005, 0x080c, 0x8bea, 0x00d6, 0x2069,
+	0xb39e, 0x2d04, 0xa005, 0x0168, 0x6018, 0x2068, 0x68a0, 0xa086,
+	0x007e, 0x1138, 0x2069, 0xb11c, 0x2d04, 0x8000, 0x206a, 0x00de,
+	0x0010, 0x00de, 0x0078, 0x2001, 0x0000, 0x080c, 0x4d63, 0x2001,
+	0x0002, 0x080c, 0x4d75, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c,
+	0x6a3c, 0x0428, 0x080c, 0x8890, 0x2009, 0xb68e, 0x2134, 0xa6b4,
+	0x00ff, 0xa686, 0x0005, 0x01e0, 0xa686, 0x000b, 0x01b0, 0x2009,
+	0xb68f, 0x2104, 0xa084, 0xff00, 0x1118, 0xa686, 0x0009, 0x0180,
+	0xa086, 0x1900, 0x1150, 0xa686, 0x0009, 0x0150, 0x2001, 0x0004,
+	0x080c, 0x4d75, 0x080c, 0x82eb, 0x0010, 0x080c, 0x8a69, 0x0005,
+	0x00d6, 0x6010, 0x2068, 0x080c, 0x986a, 0x0128, 0x6838, 0xd0fc,
+	0x0110, 0x00de, 0x0c90, 0x6018, 0x2068, 0x6840, 0xa084, 0x00ff,
+	0xa005, 0x0140, 0x8001, 0x6842, 0x6017, 0x000a, 0x6007, 0x0016,
+	0x00de, 0x0c28, 0x68a0, 0xa086, 0x007e, 0x1138, 0x00e6, 0x2071,
+	0xb100, 0x080c, 0x4a3b, 0x00ee, 0x0010, 0x080c, 0x2b73, 0x00de,
+	0x08a0, 0x080c, 0x8bea, 0x1158, 0x2001, 0x0004, 0x080c, 0x4d75,
+	0x6003, 0x0001, 0x6007, 0x0003, 0x080c, 0x6a3c, 0x0020, 0x080c,
+	0x8890, 0x080c, 0x8a69, 0x0005, 0x0469, 0x1158, 0x2001, 0x0008,
+	0x080c, 0x4d75, 0x6003, 0x0001, 0x6007, 0x0005, 0x080c, 0x6a3c,
+	0x0010, 0x080c, 0x8a69, 0x0005, 0x00e9, 0x1158, 0x2001, 0x000a,
+	0x080c, 0x4d75, 0x6003, 0x0001, 0x6007, 0x0001, 0x080c, 0x6a3c,
+	0x0010, 0x080c, 0x8a69, 0x0005, 0x2009, 0xb68e, 0x2104, 0xa086,
+	0x0003, 0x1138, 0x2009, 0xb68f, 0x2104, 0xa084, 0xff00, 0xa086,
+	0x2a00, 0x0005, 0xa085, 0x0001, 0x0005, 0x00c6, 0x0016, 0xac88,
+	0x0006, 0x2164, 0x080c, 0x4e30, 0x001e, 0x00ce, 0x0005, 0x00f6,
+	0x00e6, 0x00d6, 0x0036, 0x0016, 0x6018, 0x2068, 0x2071, 0xb134,
+	0x2e04, 0xa085, 0x0003, 0x2072, 0x080c, 0x8c7b, 0x0560, 0x2009,
+	0xb134, 0x2104, 0xc0cd, 0x200a, 0x2001, 0xb153, 0x2004, 0xd0a4,
+	0x0158, 0xa006, 0x2020, 0x2009, 0x002a, 0x080c, 0xacae, 0x2001,
+	0xb10c, 0x200c, 0xc195, 0x2102, 0x2019, 0x002a, 0x2009, 0x0001,
+	0x080c, 0x2b46, 0x2071, 0xb100, 0x080c, 0x2991, 0x00c6, 0x0156,
+	0x20a9, 0x0081, 0x2009, 0x007f, 0x080c, 0x2c6e, 0x8108, 0x1f04,
+	0x8c2c, 0x015e, 0x00ce, 0x080c, 0x8bed, 0x6813, 0x00ff, 0x6817,
+	0xfffe, 0x2071, 0xb680, 0x2079, 0x0100, 0x2e04, 0xa084, 0x00ff,
+	0x2069, 0xb11b, 0x206a, 0x78e6, 0x0006, 0x8e70, 0x2e04, 0x2069,
+	0xb11c, 0x206a, 0x78ea, 0x7832, 0x7836, 0x2010, 0xa084, 0xff00,
+	0x001e, 0xa105, 0x2009, 0xb127, 0x200a, 0x2200, 0xa084, 0x00ff,
+	0x2008, 0x080c, 0x2720, 0x080c, 0x58d5, 0x0170, 0x2069, 0xb68e,
+	0x2071, 0xb3b1, 0x6810, 0x2072, 0x6814, 0x7006, 0x6818, 0x700a,
+	0x681c, 0x700e, 0x080c, 0x9be0, 0x0040, 0x2001, 0x0006, 0x080c,
+	0x4d75, 0x080c, 0x2b99, 0x080c, 0x82eb, 0x001e, 0x003e, 0x00de,
+	0x00ee, 0x00fe, 0x0005, 0x0026, 0x0036, 0x00e6, 0x0156, 0x2019,
+	0xb127, 0x231c, 0x83ff, 0x01e8, 0x2071, 0xb680, 0x2e14, 0xa294,
+	0x00ff, 0x7004, 0xa084, 0xff00, 0xa205, 0xa306, 0x1190, 0x2011,
+	0xb696, 0xad98, 0x000a, 0x20a9, 0x0004, 0x080c, 0x8d2b, 0x1148,
+	0x2011, 0xb69a, 0xad98, 0x0006, 0x20a9, 0x0004, 0x080c, 0x8d2b,
+	0x1100, 0x015e, 0x00ee, 0x003e, 0x002e, 0x0005, 0x00e6, 0x2071,
+	0xb68c, 0x7004, 0xa086, 0x0014, 0x11a8, 0x7008, 0xa086, 0x0800,
+	0x1188, 0x700c, 0xd0ec, 0x0160, 0xa084, 0x0f00, 0xa086, 0x0100,
+	0x1138, 0x7024, 0xd0a4, 0x1110, 0xd0ac, 0x0110, 0xa006, 0x0010,
+	0xa085, 0x0001, 0x00ee, 0x0005, 0x00e6, 0x00d6, 0x00c6, 0x0076,
+	0x0056, 0x0046, 0x0026, 0x0006, 0x0126, 0x2091, 0x8000, 0x2029,
+	0xb3e2, 0x252c, 0x2021, 0xb3e8, 0x2424, 0x2061, 0xb800, 0x2071,
+	0xb100, 0x7244, 0x7064, 0xa202, 0x16f0, 0x080c, 0xacd6, 0x05a0,
+	0x671c, 0xa786, 0x0001, 0x0580, 0xa786, 0x0007, 0x0568, 0x2500,
+	0xac06, 0x0550, 0x2400, 0xac06, 0x0538, 0x00c6, 0x6000, 0xa086,
+	0x0004, 0x1110, 0x080c, 0x190f, 0xa786, 0x0008, 0x1148, 0x080c,
+	0x9a66, 0x1130, 0x00ce, 0x080c, 0x8890, 0x080c, 0x9a2b, 0x00a0,
+	0x6010, 0x2068, 0x080c, 0x986a, 0x0160, 0xa786, 0x0003, 0x11e8,
+	0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c, 0x5271, 0x080c,
+	0x9a1f, 0x080c, 0x9a2b, 0x00ce, 0xace0, 0x0018, 0x7058, 0xac02,
+	0x1210, 0x0804, 0x8cd9, 0x012e, 0x000e, 0x002e, 0x004e, 0x005e,
+	0x007e, 0x00ce, 0x00de, 0x00ee, 0x0005, 0xa786, 0x0006, 0x1d00,
+	0x080c, 0xac5f, 0x0c30, 0x220c, 0x2304, 0xa106, 0x1130, 0x8210,
+	0x8318, 0x1f04, 0x8d2b, 0xa006, 0x0005, 0x2304, 0xa102, 0x0218,
+	0x2001, 0x0001, 0x0010, 0x2001, 0x0000, 0xa18d, 0x0001, 0x0005,
+	0x6004, 0xa08a, 0x0080, 0x1a0c, 0x14fa, 0x080c, 0x9a55, 0x0120,
+	0x080c, 0x9a66, 0x0168, 0x0028, 0x080c, 0x2b99, 0x080c, 0x9a66,
+	0x0138, 0x080c, 0x6dc1, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005,
+	0x080c, 0x8890, 0x0cb0, 0xa182, 0x0040, 0x0002, 0x8d71, 0x8d71,
+	0x8d71, 0x8d71, 0x8d71, 0x8d71, 0x8d71, 0x8d71, 0x8d71, 0x8d71,
+	0x8d71, 0x8d73, 0x8d73, 0x8d73, 0x8d73, 0x8d71, 0x8d71, 0x8d71,
+	0x8d73, 0x080c, 0x14fa, 0x600b, 0xffff, 0x6003, 0x0001, 0x6106,
+	0x080c, 0x69f6, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e, 0x012e,
+	0x0005, 0xa186, 0x0013, 0x1128, 0x6004, 0xa082, 0x0040, 0x0804,
+	0x8e0d, 0xa186, 0x0027, 0x11e8, 0x080c, 0x6dc1, 0x080c, 0x2b73,
+	0x00d6, 0x6110, 0x2168, 0x080c, 0x986a, 0x0168, 0x6837, 0x0103,
+	0x684b, 0x0029, 0x6847, 0x0000, 0x694c, 0xc1c5, 0x694e, 0x080c,
+	0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c, 0x82eb, 0x080c, 0x6e9e,
+	0x0005, 0xa186, 0x0014, 0x1120, 0x6004, 0xa082, 0x0040, 0x0428,
+	0xa186, 0x0046, 0x0138, 0xa186, 0x0045, 0x0120, 0xa186, 0x0047,
+	0x190c, 0x14fa, 0x2001, 0x0109, 0x2004, 0xd084, 0x0198, 0x0126,
+	0x2091, 0x2800, 0x0006, 0x0016, 0x0026, 0x080c, 0x68e7, 0x002e,
+	0x001e, 0x000e, 0x012e, 0xe000, 0x6000, 0xa086, 0x0002, 0x1110,
+	0x0804, 0x8e47, 0x080c, 0x8331, 0x0005, 0x0002, 0x8deb, 0x8de9,
+	0x8de9, 0x8de9, 0x8de9, 0x8de9, 0x8de9, 0x8de9, 0x8de9, 0x8de9,
+	0x8de9, 0x8e06, 0x8e06, 0x8e06, 0x8e06, 0x8de9, 0x8e06, 0x8de9,
+	0x8e06, 0x080c, 0x14fa, 0x080c, 0x6dc1, 0x00d6, 0x6110, 0x2168,
+	0x080c, 0x986a, 0x0168, 0x6837, 0x0103, 0x684b, 0x0006, 0x6847,
+	0x0000, 0x6850, 0xc0ec, 0x6852, 0x080c, 0x5271, 0x080c, 0x9a1f,
+	0x00de, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x6dc1,
+	0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005, 0x0002, 0x8e23, 0x8e21,
+	0x8e21, 0x8e21, 0x8e21, 0x8e21, 0x8e21, 0x8e21, 0x8e21, 0x8e21,
+	0x8e21, 0x8e35, 0x8e35, 0x8e35, 0x8e35, 0x8e21, 0x8e40, 0x8e21,
+	0x8e35, 0x080c, 0x14fa, 0x080c, 0x6dc1, 0x2001, 0xb3b7, 0x2004,
+	0x603e, 0x6003, 0x0002, 0x080c, 0x6e9e, 0x6010, 0xa088, 0x0013,
+	0x2104, 0xa085, 0x0400, 0x200a, 0x0005, 0x080c, 0x6dc1, 0x2001,
+	0xb3b7, 0x2004, 0x603e, 0x6003, 0x000f, 0x080c, 0x6e9e, 0x0005,
+	0x080c, 0x6dc1, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005, 0xa182,
+	0x0040, 0x0002, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5f,
+	0x8f37, 0x8f66, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d,
+	0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x8e5d, 0x080c, 0x14fa, 0x00e6,
+	0x00d6, 0x603f, 0x0000, 0x2071, 0xb680, 0x7124, 0x610a, 0x2071,
+	0xb68c, 0x6110, 0x2168, 0x7614, 0xa6b4, 0x0fff, 0x86ff, 0x0904,
+	0x8f03, 0xa68c, 0x0c00, 0x01e8, 0x00f6, 0x2c78, 0x080c, 0x5177,
+	0x00fe, 0x0198, 0x684c, 0xd0ac, 0x0180, 0x6020, 0xd0dc, 0x1168,
+	0x6850, 0xd0bc, 0x1150, 0x7318, 0x6814, 0xa306, 0x1904, 0x8f15,
+	0x731c, 0x6810, 0xa306, 0x1904, 0x8f15, 0x7318, 0x6b62, 0x731c,
+	0x6b5e, 0xa68c, 0x00ff, 0xa186, 0x0002, 0x0518, 0xa186, 0x0028,
+	0x1128, 0x080c, 0x9a44, 0x684b, 0x001c, 0x00e8, 0xd6dc, 0x01a0,
+	0x684b, 0x0015, 0x684c, 0xd0ac, 0x0170, 0x6914, 0x6a10, 0x2100,
+	0xa205, 0x0148, 0x7018, 0xa106, 0x1118, 0x701c, 0xa206, 0x0118,
+	0x6962, 0x6a5e, 0xc6dc, 0x0038, 0xd6d4, 0x0118, 0x684b, 0x0007,
+	0x0010, 0x684b, 0x0000, 0x6837, 0x0103, 0x6e46, 0xa01e, 0xd6c4,
+	0x01f0, 0xa686, 0x0100, 0x1140, 0x2001, 0xb699, 0x2004, 0xa005,
+	0x1118, 0xc6c4, 0x0804, 0x8e6e, 0x7328, 0x732c, 0x6b56, 0x83ff,
+	0x0170, 0xa38a, 0x0009, 0x0210, 0x2019, 0x0008, 0x0036, 0x2308,
+	0x2019, 0xb698, 0xad90, 0x0019, 0x080c, 0x953f, 0x003e, 0xd6cc,
+	0x0904, 0x8f28, 0x7124, 0x695a, 0x81ff, 0x0904, 0x8f28, 0xa192,
+	0x0021, 0x1250, 0x2071, 0xb698, 0x831c, 0x2300, 0xae18, 0xad90,
+	0x001d, 0x080c, 0x953f, 0x04a0, 0x6838, 0xd0fc, 0x0120, 0x2009,
+	0x0020, 0x695a, 0x0c78, 0x00f6, 0x2d78, 0x080c, 0x94e4, 0x00fe,
+	0x080c, 0x952f, 0x0438, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x00fe,
+	0x0188, 0x684c, 0xd0ac, 0x0170, 0x6020, 0xd0dc, 0x1158, 0x6850,
+	0xd0bc, 0x1140, 0x684c, 0xd0f4, 0x1128, 0x080c, 0x9b43, 0x00de,
+	0x00ee, 0x00e0, 0x684b, 0x0000, 0x6837, 0x0103, 0x6e46, 0x684c,
+	0xd0ac, 0x0130, 0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x90c1,
+	0x080c, 0x5271, 0x6218, 0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x080c,
+	0x9b11, 0x00de, 0x00ee, 0x1110, 0x080c, 0x82eb, 0x0005, 0x00f6,
+	0x6003, 0x0003, 0x2079, 0xb68c, 0x7c04, 0x7b00, 0x7e0c, 0x7d08,
+	0x6010, 0x2078, 0x784c, 0xd0ac, 0x0138, 0x6003, 0x0002, 0x00fe,
+	0x0005, 0x2130, 0x2228, 0x0058, 0x2400, 0x797c, 0xa10a, 0x2300,
+	0x7a80, 0xa213, 0x2600, 0xa102, 0x2500, 0xa203, 0x0e90, 0x7c12,
+	0x7b16, 0x7e0a, 0x7d0e, 0x00fe, 0x603f, 0x0000, 0x2c10, 0x080c,
+	0x1ec4, 0x080c, 0x6a59, 0x080c, 0x6f5b, 0x0005, 0x2001, 0xb3b7,
+	0x2004, 0x603e, 0x6003, 0x0004, 0x6110, 0x20e1, 0x0005, 0x3d18,
+	0x3e20, 0x2c10, 0x080c, 0x1828, 0x0005, 0xa182, 0x0040, 0x0002,
+	0x8f8b, 0x8f8b, 0x8f8b, 0x8f8b, 0x8f8b, 0x8f8d, 0x901e, 0x8f8b,
+	0x8f8b, 0x9034, 0x9098, 0x8f8b, 0x8f8b, 0x8f8b, 0x8f8b, 0x90a7,
+	0x8f8b, 0x8f8b, 0x8f8b, 0x080c, 0x14fa, 0x0076, 0x00f6, 0x00e6,
+	0x00d6, 0x2071, 0xb68c, 0x6110, 0x2178, 0x7614, 0xa6b4, 0x0fff,
+	0x7e46, 0x7f4c, 0xc7e5, 0x7f4e, 0x6218, 0x2268, 0x6a3c, 0x8211,
+	0x6a3e, 0x86ff, 0x0904, 0x9019, 0xa694, 0xff00, 0xa284, 0x0c00,
+	0x0120, 0x7018, 0x7862, 0x701c, 0x785e, 0xa284, 0x0300, 0x0904,
+	0x9019, 0x080c, 0x15dd, 0x090c, 0x14fa, 0x2d00, 0x784a, 0x7f4c,
+	0xc7cd, 0x7f4e, 0x6837, 0x0103, 0x7838, 0x683a, 0x783c, 0x683e,
+	0x7840, 0x6842, 0x6e46, 0xa68c, 0x0c00, 0x0120, 0x7318, 0x6b62,
+	0x731c, 0x6b5e, 0xa68c, 0x00ff, 0xa186, 0x0002, 0x0180, 0xa186,
+	0x0028, 0x1118, 0x684b, 0x001c, 0x0060, 0xd6dc, 0x0118, 0x684b,
+	0x0015, 0x0038, 0xd6d4, 0x0118, 0x684b, 0x0007, 0x0010, 0x684b,
+	0x0000, 0x6f4e, 0x7850, 0x6852, 0x7854, 0x6856, 0xa01e, 0xd6c4,
+	0x0198, 0x7328, 0x732c, 0x6b56, 0x83ff, 0x0170, 0xa38a, 0x0009,
+	0x0210, 0x2019, 0x0008, 0x0036, 0x2308, 0x2019, 0xb698, 0xad90,
+	0x0019, 0x080c, 0x953f, 0x003e, 0xd6cc, 0x01d8, 0x7124, 0x695a,
+	0x81ff, 0x01b8, 0xa192, 0x0021, 0x1250, 0x2071, 0xb698, 0x831c,
+	0x2300, 0xae18, 0xad90, 0x001d, 0x080c, 0x953f, 0x0050, 0x7838,
+	0xd0fc, 0x0120, 0x2009, 0x0020, 0x695a, 0x0c78, 0x2d78, 0x080c,
+	0x94e4, 0x00de, 0x00ee, 0x00fe, 0x007e, 0x0005, 0x00f6, 0x6003,
+	0x0003, 0x2079, 0xb68c, 0x7c04, 0x7b00, 0x7e0c, 0x7d08, 0x6010,
+	0x2078, 0x7c12, 0x7b16, 0x7e0a, 0x7d0e, 0x00fe, 0x2c10, 0x080c,
+	0x1ec4, 0x080c, 0x7a72, 0x0005, 0x00d6, 0x00f6, 0x2c78, 0x080c,
+	0x5177, 0x00fe, 0x0120, 0x2001, 0xb3b7, 0x2004, 0x603e, 0x6003,
+	0x0002, 0x080c, 0x6e53, 0x080c, 0x6f5b, 0x6110, 0x2168, 0x694c,
+	0xd1e4, 0x0904, 0x9096, 0xd1cc, 0x0540, 0x6948, 0x6838, 0xd0fc,
+	0x01e8, 0x0016, 0x684c, 0x0006, 0x6850, 0x0006, 0xad90, 0x000d,
+	0xa198, 0x000d, 0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012,
+	0x8318, 0x8210, 0x1f04, 0x905e, 0x015e, 0x000e, 0x6852, 0x000e,
+	0x684e, 0x001e, 0x2168, 0x080c, 0x1604, 0x0418, 0x0016, 0x080c,
+	0x1604, 0x00de, 0x080c, 0x952f, 0x00e0, 0x6837, 0x0103, 0x6944,
+	0xa184, 0x00ff, 0xa0b6, 0x0002, 0x0180, 0xa086, 0x0028, 0x1118,
+	0x684b, 0x001c, 0x0060, 0xd1dc, 0x0118, 0x684b, 0x0015, 0x0038,
+	0xd1d4, 0x0118, 0x684b, 0x0007, 0x0010, 0x684b, 0x0000, 0x080c,
+	0x5271, 0x080c, 0x9b11, 0x1110, 0x080c, 0x82eb, 0x00de, 0x0005,
+	0x2019, 0x0001, 0x080c, 0x7cc4, 0x6003, 0x0002, 0x2001, 0xb3b7,
+	0x2004, 0x603e, 0x080c, 0x6e53, 0x080c, 0x6f5b, 0x0005, 0x080c,
+	0x6e53, 0x080c, 0x2b73, 0x00d6, 0x6110, 0x2168, 0x080c, 0x986a,
+	0x0150, 0x6837, 0x0103, 0x684b, 0x0029, 0x6847, 0x0000, 0x080c,
+	0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c, 0x82eb, 0x080c, 0x6f5b,
+	0x0005, 0x684b, 0x0015, 0xd1fc, 0x0138, 0x684b, 0x0007, 0x8002,
+	0x8000, 0x810a, 0xa189, 0x0000, 0x6962, 0x685e, 0x0005, 0xa182,
+	0x0040, 0x0002, 0x90e5, 0x90e5, 0x90e5, 0x90e5, 0x90e5, 0x90e7,
+	0x90e5, 0x91a0, 0x91ac, 0x90e5, 0x90e5, 0x90e5, 0x90e5, 0x90e5,
+	0x90e5, 0x90e5, 0x90e5, 0x90e5, 0x90e5, 0x080c, 0x14fa, 0x0076,
+	0x00f6, 0x00e6, 0x00d6, 0x2071, 0xb68c, 0x6110, 0x2178, 0x7614,
+	0xa6b4, 0x0fff, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x00fe, 0x0150,
+	0xa684, 0x00ff, 0x1138, 0x6020, 0xd0f4, 0x0120, 0x080c, 0x9b43,
+	0x0804, 0x919b, 0x7e46, 0x7f4c, 0xc7e5, 0x7f4e, 0x6218, 0x2268,
+	0x6a3c, 0x8211, 0x6a3e, 0x86ff, 0x0904, 0x9191, 0xa694, 0xff00,
+	0xa284, 0x0c00, 0x0120, 0x7018, 0x7862, 0x701c, 0x785e, 0xa284,
+	0x0300, 0x0904, 0x918f, 0xa686, 0x0100, 0x1140, 0x2001, 0xb699,
+	0x2004, 0xa005, 0x1118, 0xc6c4, 0x7e46, 0x0c28, 0x080c, 0x15dd,
+	0x090c, 0x14fa, 0x2d00, 0x784a, 0x7f4c, 0xa7bd, 0x0200, 0x7f4e,
+	0x6837, 0x0103, 0x7838, 0x683a, 0x783c, 0x683e, 0x7840, 0x6842,
+	0x6e46, 0xa68c, 0x0c00, 0x0120, 0x7318, 0x6b62, 0x731c, 0x6b5e,
+	0xa68c, 0x00ff, 0xa186, 0x0002, 0x0180, 0xa186, 0x0028, 0x1118,
+	0x684b, 0x001c, 0x0060, 0xd6dc, 0x0118, 0x684b, 0x0015, 0x0038,
+	0xd6d4, 0x0118, 0x684b, 0x0007, 0x0010, 0x684b, 0x0000, 0x6f4e,
+	0x7850, 0x6852, 0x7854, 0x6856, 0xa01e, 0xd6c4, 0x0198, 0x7328,
+	0x732c, 0x6b56, 0x83ff, 0x0170, 0xa38a, 0x0009, 0x0210, 0x2019,
+	0x0008, 0x0036, 0x2308, 0x2019, 0xb698, 0xad90, 0x0019, 0x080c,
+	0x953f, 0x003e, 0xd6cc, 0x01d8, 0x7124, 0x695a, 0x81ff, 0x01b8,
+	0xa192, 0x0021, 0x1250, 0x2071, 0xb698, 0x831c, 0x2300, 0xae18,
+	0xad90, 0x001d, 0x080c, 0x953f, 0x0050, 0x7838, 0xd0fc, 0x0120,
+	0x2009, 0x0020, 0x695a, 0x0c78, 0x2d78, 0x080c, 0x94e4, 0xd6dc,
+	0x1110, 0xa006, 0x0030, 0x2001, 0x0001, 0x2071, 0xb68c, 0x7218,
+	0x731c, 0x080c, 0x1873, 0x00de, 0x00ee, 0x00fe, 0x007e, 0x0005,
+	0x2001, 0xb3b7, 0x2004, 0x603e, 0x20e1, 0x0005, 0x3d18, 0x3e20,
+	0x2c10, 0x080c, 0x1828, 0x0005, 0x2001, 0xb3b7, 0x2004, 0x603e,
+	0x00d6, 0x6003, 0x0002, 0x6110, 0x2168, 0x694c, 0xd1e4, 0x0904,
+	0x92b3, 0x603f, 0x0000, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x00fe,
+	0x0560, 0x6814, 0x6910, 0xa115, 0x0540, 0x6a60, 0xa206, 0x1118,
+	0x685c, 0xa106, 0x0510, 0x684c, 0xc0e4, 0x684e, 0x6847, 0x0000,
+	0x6863, 0x0000, 0x685f, 0x0000, 0x6020, 0xd0f4, 0x1158, 0x697c,
+	0x6810, 0xa102, 0x603a, 0x6980, 0x6814, 0xa103, 0x6036, 0x6020,
+	0xc0f5, 0x6022, 0x00d6, 0x6018, 0x2068, 0x683c, 0x8000, 0x683e,
+	0x00de, 0x080c, 0x9b43, 0x0804, 0x92b3, 0x694c, 0xd1cc, 0x0904,
+	0x9283, 0x6948, 0x6838, 0xd0fc, 0x0904, 0x9248, 0x0016, 0x684c,
+	0x0006, 0x6850, 0x0006, 0x00f6, 0x2178, 0x7944, 0xa184, 0x00ff,
+	0xa0b6, 0x0002, 0x01e0, 0xa086, 0x0028, 0x1128, 0x684b, 0x001c,
+	0x784b, 0x001c, 0x00e8, 0xd1dc, 0x0158, 0x684b, 0x0015, 0x784b,
+	0x0015, 0x080c, 0x9ccd, 0x0118, 0x7944, 0xc1dc, 0x7946, 0x0080,
+	0xd1d4, 0x0128, 0x684b, 0x0007, 0x784b, 0x0007, 0x0048, 0x684c,
+	0xd0ac, 0x0130, 0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x90c1,
+	0x6848, 0x784a, 0x6860, 0x7862, 0x685c, 0x785e, 0xad90, 0x000d,
+	0xaf98, 0x000d, 0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012,
+	0x8318, 0x8210, 0x1f04, 0x9236, 0x015e, 0x00fe, 0x000e, 0x6852,
+	0x000e, 0x684e, 0x001e, 0x2168, 0x080c, 0x1604, 0x0804, 0x92ae,
+	0x0016, 0x00f6, 0x2178, 0x7944, 0xa184, 0x00ff, 0xa0b6, 0x0002,
+	0x01e0, 0xa086, 0x0028, 0x1128, 0x684b, 0x001c, 0x784b, 0x001c,
+	0x00e8, 0xd1dc, 0x0158, 0x684b, 0x0015, 0x784b, 0x0015, 0x080c,
+	0x9ccd, 0x0118, 0x7944, 0xc1dc, 0x7946, 0x0080, 0xd1d4, 0x0128,
+	0x684b, 0x0007, 0x784b, 0x0007, 0x0048, 0x684c, 0xd0ac, 0x0130,
+	0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x90c1, 0x6860, 0x7862,
+	0x685c, 0x785e, 0x684c, 0x784e, 0x00fe, 0x080c, 0x1604, 0x00de,
+	0x080c, 0x952f, 0x0458, 0x6837, 0x0103, 0x6944, 0xa184, 0x00ff,
+	0xa0b6, 0x0002, 0x01b0, 0xa086, 0x0028, 0x1118, 0x684b, 0x001c,
+	0x00d8, 0xd1dc, 0x0148, 0x684b, 0x0015, 0x080c, 0x9ccd, 0x0118,
+	0x6944, 0xc1dc, 0x6946, 0x0080, 0xd1d4, 0x0118, 0x684b, 0x0007,
+	0x0058, 0x684b, 0x0000, 0x684c, 0xd0ac, 0x0130, 0x6810, 0x6914,
+	0xa115, 0x0110, 0x080c, 0x90c1, 0x080c, 0x5271, 0x080c, 0x9b11,
+	0x1110, 0x080c, 0x82eb, 0x00de, 0x0005, 0x080c, 0x6dc1, 0x0010,
+	0x080c, 0x6e53, 0x080c, 0x986a, 0x01c0, 0x00d6, 0x6110, 0x2168,
+	0x6837, 0x0103, 0x2009, 0xb10c, 0x210c, 0xd18c, 0x11c0, 0xd184,
+	0x1198, 0x6108, 0x694a, 0xa18e, 0x0029, 0x1110, 0x080c, 0xaf46,
+	0x6847, 0x0000, 0x080c, 0x5271, 0x00de, 0x080c, 0x82eb, 0x080c,
+	0x6e9e, 0x080c, 0x6f5b, 0x0005, 0x684b, 0x0004, 0x0c88, 0x684b,
+	0x0004, 0x0c70, 0xa182, 0x0040, 0x0002, 0x92f8, 0x92f8, 0x92f8,
+	0x92f8, 0x92f8, 0x92fa, 0x92f8, 0x92fd, 0x92f8, 0x92f8, 0x92f8,
+	0x92f8, 0x92f8, 0x92f8, 0x92f8, 0x92f8, 0x92f8, 0x92f8, 0x92f8,
+	0x080c, 0x14fa, 0x080c, 0x82eb, 0x0005, 0x0006, 0x0026, 0xa016,
+	0x080c, 0x1828, 0x002e, 0x000e, 0x0005, 0xa182, 0x0085, 0x0002,
+	0x9311, 0x930f, 0x930f, 0x931d, 0x930f, 0x930f, 0x930f, 0x080c,
+	0x14fa, 0x6003, 0x0001, 0x6106, 0x080c, 0x69f6, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x6e9e, 0x012e, 0x0005, 0x0026, 0x0056, 0x00d6,
+	0x00e6, 0x2071, 0xb680, 0x7224, 0x6212, 0x7220, 0x080c, 0x985a,
+	0x01a0, 0x2268, 0x6800, 0xa086, 0x0000, 0x0178, 0x6018, 0x6d18,
+	0xa52e, 0x1158, 0x00c6, 0x2d60, 0x080c, 0x954f, 0x00ce, 0x0128,
+	0x6803, 0x0002, 0x6007, 0x0086, 0x0010, 0x6007, 0x0087, 0x6003,
+	0x0001, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x00f6, 0x2278, 0x080c,
+	0x5177, 0x00fe, 0x0150, 0x6820, 0xd0ec, 0x0138, 0x00c6, 0x2260,
+	0x603f, 0x0000, 0x080c, 0x9b43, 0x00ce, 0x00ee, 0x00de, 0x005e,
+	0x002e, 0x0005, 0xa186, 0x0013, 0x1160, 0x6004, 0xa08a, 0x0085,
+	0x0a0c, 0x14fa, 0xa08a, 0x008c, 0x1a0c, 0x14fa, 0xa082, 0x0085,
+	0x0072, 0xa186, 0x0027, 0x0120, 0xa186, 0x0014, 0x190c, 0x14fa,
+	0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0x937e,
+	0x9380, 0x9380, 0x937e, 0x937e, 0x937e, 0x937e, 0x080c, 0x14fa,
+	0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0xa186,
+	0x0013, 0x1128, 0x6004, 0xa082, 0x0085, 0x2008, 0x04a8, 0xa186,
+	0x0027, 0x11e8, 0x080c, 0x6dc1, 0x080c, 0x2b73, 0x00d6, 0x6010,
+	0x2068, 0x080c, 0x986a, 0x0150, 0x6837, 0x0103, 0x6847, 0x0000,
+	0x684b, 0x0029, 0x080c, 0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c,
+	0x82eb, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x8331, 0x0ce0, 0xa186,
+	0x0014, 0x1dd0, 0x080c, 0x6dc1, 0x00d6, 0x6010, 0x2068, 0x080c,
+	0x986a, 0x0d60, 0x6837, 0x0103, 0x6847, 0x0000, 0x684b, 0x0006,
+	0x6850, 0xc0ec, 0x6852, 0x08f0, 0x0002, 0x93ce, 0x93cc, 0x93cc,
+	0x93cc, 0x93cc, 0x93cc, 0x93e6, 0x080c, 0x14fa, 0x080c, 0x6dc1,
+	0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186,
+	0x0035, 0x1118, 0x2001, 0xb3b5, 0x0010, 0x2001, 0xb3b6, 0x2004,
+	0x6016, 0x6003, 0x000c, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x6dc1,
+	0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186,
+	0x0035, 0x1118, 0x2001, 0xb3b5, 0x0010, 0x2001, 0xb3b6, 0x2004,
+	0x6016, 0x6003, 0x000e, 0x080c, 0x6e9e, 0x0005, 0xa182, 0x008c,
+	0x1220, 0xa182, 0x0085, 0x0208, 0x001a, 0x080c, 0x8331, 0x0005,
+	0x940f, 0x940f, 0x940f, 0x940f, 0x9411, 0x9464, 0x940f, 0x080c,
+	0x14fa, 0x00d6, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x00fe, 0x0168,
+	0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186,
+	0x0035, 0x1118, 0x00de, 0x0804, 0x9477, 0x080c, 0x9a1f, 0x080c,
+	0x986a, 0x01c8, 0x6010, 0x2068, 0x6837, 0x0103, 0x6850, 0xd0b4,
+	0x0128, 0x684b, 0x0006, 0xc0ec, 0x6852, 0x0048, 0xd0bc, 0x0118,
+	0x684b, 0x0002, 0x0020, 0x684b, 0x0005, 0x080c, 0x9ae0, 0x6847,
+	0x0000, 0x080c, 0x5271, 0x2c68, 0x080c, 0x8295, 0x01c0, 0x6003,
+	0x0001, 0x6007, 0x001e, 0x600b, 0xffff, 0x2009, 0xb68e, 0x210c,
+	0x6136, 0x2009, 0xb68f, 0x210c, 0x613a, 0x6918, 0x611a, 0x080c,
+	0x9c35, 0x6950, 0x6152, 0x601f, 0x0001, 0x080c, 0x69f6, 0x2d60,
+	0x080c, 0x82eb, 0x00de, 0x0005, 0x00f6, 0x2c78, 0x080c, 0x5177,
+	0x00fe, 0x0598, 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0035,
+	0x0130, 0xa186, 0x001e, 0x0118, 0xa186, 0x0039, 0x1530, 0x00d6,
+	0x2c68, 0x080c, 0x9d16, 0x1904, 0x94bc, 0x080c, 0x8295, 0x01d8,
+	0x6106, 0x6003, 0x0001, 0x601f, 0x0001, 0x6918, 0x611a, 0x6928,
+	0x612a, 0x692c, 0x612e, 0x6930, 0xa18c, 0x00ff, 0x6132, 0x6934,
+	0x6136, 0x6938, 0x613a, 0x6950, 0x6152, 0x080c, 0x9c35, 0x080c,
+	0x69f6, 0x080c, 0x6e9e, 0x2d60, 0x00f8, 0x00d6, 0x6010, 0x2068,
+	0x080c, 0x986a, 0x01c8, 0x6837, 0x0103, 0x6850, 0xd0b4, 0x0128,
+	0xc0ec, 0x6852, 0x684b, 0x0006, 0x0048, 0xd0bc, 0x0118, 0x684b,
+	0x0002, 0x0020, 0x684b, 0x0005, 0x080c, 0x9ae0, 0x6847, 0x0000,
+	0x080c, 0x5271, 0x080c, 0x9a1f, 0x00de, 0x080c, 0x82eb, 0x0005,
+	0x0016, 0x00d6, 0x6010, 0x2068, 0x080c, 0x986a, 0x0140, 0x6837,
+	0x0103, 0x684b, 0x0028, 0x6847, 0x0000, 0x080c, 0x5271, 0x00de,
+	0x001e, 0xa186, 0x0013, 0x0148, 0xa186, 0x0014, 0x0130, 0xa186,
+	0x0027, 0x0118, 0x080c, 0x8331, 0x0030, 0x080c, 0x6dc1, 0x080c,
+	0x9a2b, 0x080c, 0x6e9e, 0x0005, 0x0056, 0x0066, 0x00d6, 0x00f6,
+	0x2029, 0x0001, 0xa182, 0x0101, 0x1208, 0x0010, 0x2009, 0x0100,
+	0x2130, 0x2069, 0xb698, 0x831c, 0x2300, 0xad18, 0x2009, 0x0020,
+	0xaf90, 0x001d, 0x080c, 0x953f, 0xa6b2, 0x0020, 0x7804, 0xa06d,
+	0x0110, 0x080c, 0x1604, 0x080c, 0x15dd, 0x0500, 0x8528, 0x6837,
+	0x0110, 0x683b, 0x0000, 0x2d20, 0x7c06, 0xa68a, 0x003d, 0x1228,
+	0x2608, 0xad90, 0x000f, 0x0459, 0x0088, 0xa6b2, 0x003c, 0x2009,
+	0x003c, 0x2d78, 0xad90, 0x000f, 0x0411, 0x0c28, 0x00fe, 0x852f,
+	0xa5ad, 0x0003, 0x7d36, 0xa5ac, 0x0000, 0x0028, 0x00fe, 0x852f,
+	0xa5ad, 0x0003, 0x7d36, 0x00de, 0x006e, 0x005e, 0x0005, 0x00f6,
+	0x8dff, 0x0158, 0x6804, 0xa07d, 0x0130, 0x6807, 0x0000, 0x080c,
+	0x5271, 0x2f68, 0x0cb8, 0x080c, 0x5271, 0x00fe, 0x0005, 0x0156,
+	0xa184, 0x0001, 0x0108, 0x8108, 0x810c, 0x21a8, 0x2304, 0x8007,
+	0x2012, 0x8318, 0x8210, 0x1f04, 0x9546, 0x015e, 0x0005, 0x0066,
+	0x0126, 0x2091, 0x8000, 0x2031, 0x0001, 0x601c, 0xa084, 0x000f,
+	0x0083, 0x012e, 0x006e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0066,
+	0x2031, 0x0000, 0x601c, 0xa084, 0x000f, 0x001b, 0x006e, 0x012e,
+	0x0005, 0x9586, 0x9586, 0x9581, 0x95a8, 0x9574, 0x9581, 0x95a8,
+	0x9581, 0x9581, 0x9574, 0x9581, 0x080c, 0x14fa, 0x0036, 0x2019,
+	0x0010, 0x080c, 0xa8af, 0x601f, 0x0006, 0x6003, 0x0007, 0x003e,
+	0x0005, 0xa006, 0x0005, 0xa085, 0x0001, 0x0005, 0x00d6, 0x86ff,
+	0x11d8, 0x6010, 0x2068, 0x080c, 0x986a, 0x01c0, 0x6834, 0xa086,
+	0x0139, 0x1128, 0x684b, 0x0005, 0x6853, 0x0000, 0x0028, 0xa00e,
+	0x2001, 0x0005, 0x080c, 0x5344, 0x080c, 0x9ae0, 0x080c, 0x5271,
+	0x080c, 0x82eb, 0xa085, 0x0001, 0x00de, 0x0005, 0xa006, 0x0ce0,
+	0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x95bf,
+	0x95e0, 0x95c1, 0x95ff, 0x95dd, 0x95bf, 0x9581, 0x9586, 0x9586,
+	0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x9581, 0x080c,
+	0x14fa, 0x86ff, 0x11b8, 0x601c, 0xa086, 0x0006, 0x0198, 0x00d6,
+	0x6010, 0x2068, 0x080c, 0x986a, 0x0110, 0x080c, 0x9ae0, 0x00de,
+	0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6,
+	0x080c, 0x6e9e, 0xa085, 0x0001, 0x0005, 0x080c, 0x190f, 0x0c08,
+	0x00e6, 0x2071, 0xb3d9, 0x7024, 0xac06, 0x1110, 0x080c, 0x7c41,
+	0x601c, 0xa084, 0x000f, 0xa086, 0x0006, 0x1150, 0x0086, 0x0096,
+	0x2049, 0x0001, 0x2c40, 0x080c, 0x7e0d, 0x009e, 0x008e, 0x0010,
+	0x080c, 0x7b3e, 0x00ee, 0x1928, 0x080c, 0x9581, 0x0005, 0x0036,
+	0x00e6, 0x2071, 0xb3d9, 0x703c, 0xac06, 0x1140, 0x2019, 0x0000,
+	0x080c, 0x7cc4, 0x00ee, 0x003e, 0x0804, 0x95c1, 0x080c, 0x7f2b,
+	0x00ee, 0x003e, 0x1904, 0x95c1, 0x080c, 0x9581, 0x0005, 0x00c6,
+	0x601c, 0xa084, 0x000f, 0x0013, 0x00ce, 0x0005, 0x9630, 0x969a,
+	0x97c8, 0x963b, 0x9a2b, 0x9630, 0xa8a1, 0x82eb, 0x969a, 0x9629,
+	0x9833, 0x080c, 0x14fa, 0x080c, 0x9a66, 0x1110, 0x080c, 0x8890,
+	0x0005, 0x080c, 0x6dc1, 0x080c, 0x6e9e, 0x080c, 0x82eb, 0x0005,
+	0x6017, 0x0001, 0x0005, 0x6010, 0xa080, 0x0019, 0x2c02, 0x6000,
+	0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x9656, 0x9658,
+	0x9678, 0x968a, 0x9697, 0x9656, 0x9630, 0x9630, 0x9630, 0x968a,
+	0x968a, 0x9656, 0x9656, 0x9656, 0x9656, 0x9694, 0x080c, 0x14fa,
+	0x00e6, 0x6010, 0x2070, 0x7050, 0xc0b5, 0x7052, 0x2071, 0xb3d9,
+	0x7024, 0xac06, 0x0190, 0x080c, 0x7b3e, 0x6007, 0x0085, 0x6003,
+	0x000b, 0x601f, 0x0002, 0x2001, 0xb3b6, 0x2004, 0x6016, 0x080c,
+	0x69f6, 0x080c, 0x6e9e, 0x00ee, 0x0005, 0x6017, 0x0001, 0x0cd8,
+	0x00d6, 0x6010, 0x2068, 0x6850, 0xc0b5, 0x6852, 0x00de, 0x6007,
+	0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x080c, 0x69f6, 0x080c,
+	0x6e9e, 0x0005, 0x00d6, 0x6017, 0x0001, 0x6010, 0x2068, 0x6850,
+	0xc0b5, 0x6852, 0x00de, 0x0005, 0x080c, 0x82eb, 0x0005, 0x080c,
+	0x190f, 0x08f0, 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b,
+	0x0005, 0x96b1, 0x9638, 0x96b3, 0x96b1, 0x96b3, 0x96b3, 0x9631,
+	0x96b1, 0x962b, 0x962b, 0x96b1, 0x96b1, 0x96b1, 0x96b1, 0x96b1,
+	0x96b1, 0x080c, 0x14fa, 0x00d6, 0x6018, 0x2068, 0x6804, 0xa084,
+	0x00ff, 0x00de, 0xa08a, 0x000c, 0x1a0c, 0x14fa, 0x000b, 0x0005,
+	0x96cc, 0x976e, 0x96ce, 0x9708, 0x96ce, 0x9708, 0x96ce, 0x96d8,
+	0x96cc, 0x9708, 0x96cc, 0x96f4, 0x080c, 0x14fa, 0x6004, 0xa08e,
+	0x0016, 0x0588, 0xa08e, 0x0004, 0x0570, 0xa08e, 0x0002, 0x0558,
+	0x6004, 0x080c, 0x9a66, 0x0904, 0x9787, 0xa08e, 0x0021, 0x0904,
+	0x978b, 0xa08e, 0x0022, 0x0904, 0x9787, 0xa08e, 0x003d, 0x0904,
+	0x978b, 0xa08e, 0x0039, 0x0904, 0x978f, 0xa08e, 0x0035, 0x0904,
+	0x978f, 0xa08e, 0x001e, 0x0188, 0xa08e, 0x0001, 0x1150, 0x00d6,
+	0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x00de, 0xa086, 0x0006,
+	0x0110, 0x080c, 0x2b73, 0x080c, 0x8890, 0x080c, 0x9a2b, 0x0005,
+	0x00c6, 0x00d6, 0x6104, 0xa186, 0x0016, 0x0904, 0x975f, 0xa186,
+	0x0002, 0x1518, 0x6018, 0x2068, 0x2001, 0xb134, 0x2004, 0xd0ac,
+	0x1904, 0x97b1, 0x68a0, 0xd0bc, 0x1904, 0x97b1, 0x6840, 0xa084,
+	0x00ff, 0xa005, 0x0190, 0x8001, 0x6842, 0x6013, 0x0000, 0x601f,
+	0x0007, 0x6017, 0x0398, 0x603f, 0x0000, 0x080c, 0x8295, 0x0128,
+	0x2d00, 0x601a, 0x601f, 0x0001, 0x0450, 0x00de, 0x00ce, 0x6004,
+	0xa08e, 0x0002, 0x11a8, 0x6018, 0xa080, 0x0028, 0x2004, 0xa086,
+	0x007e, 0x1170, 0x2009, 0xb134, 0x2104, 0xc085, 0x200a, 0x00e6,
+	0x2071, 0xb100, 0x080c, 0x4a3b, 0x00ee, 0x080c, 0x8890, 0x0020,
+	0x080c, 0x8890, 0x080c, 0x2b73, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x080c, 0x2b99, 0x012e, 0x00ee, 0x080c, 0x9a2b, 0x0005, 0x2001,
+	0x0002, 0x080c, 0x4d75, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c,
+	0x6a3c, 0x080c, 0x6e9e, 0x00de, 0x00ce, 0x0c80, 0x00c6, 0x00d6,
+	0x6104, 0xa186, 0x0016, 0x0d58, 0x6018, 0x2068, 0x6840, 0xa084,
+	0x00ff, 0xa005, 0x0904, 0x9735, 0x8001, 0x6842, 0x6003, 0x0001,
+	0x080c, 0x6a3c, 0x080c, 0x6e9e, 0x00de, 0x00ce, 0x08b8, 0x080c,
+	0x8890, 0x0804, 0x9705, 0x080c, 0x88be, 0x0804, 0x9705, 0x00d6,
+	0x2c68, 0x6104, 0x080c, 0x9d16, 0x00de, 0x0118, 0x080c, 0x82eb,
+	0x00b8, 0x6004, 0x8007, 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032,
+	0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, 0x6038, 0x600a,
+	0x2001, 0xb3b6, 0x2004, 0x6016, 0x080c, 0x69f6, 0x080c, 0x6e9e,
+	0x0005, 0x00de, 0x00ce, 0x080c, 0x8890, 0x080c, 0x2b73, 0x00e6,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x2b99, 0x6013, 0x0000, 0x601f,
+	0x0007, 0x6017, 0x0398, 0x603f, 0x0000, 0x012e, 0x00ee, 0x0005,
+	0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa, 0x000b, 0x0005, 0x97df,
+	0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df, 0x97df,
+	0x9630, 0x97df, 0x9638, 0x97e1, 0x9638, 0x97ee, 0x97df, 0x080c,
+	0x14fa, 0x6004, 0xa086, 0x008b, 0x0148, 0x6007, 0x008b, 0x6003,
+	0x000d, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x9a1f,
+	0x080c, 0x986a, 0x0580, 0x080c, 0x2b73, 0x00d6, 0x080c, 0x986a,
+	0x0168, 0x6010, 0x2068, 0x6837, 0x0103, 0x684b, 0x0006, 0x6847,
+	0x0000, 0x6850, 0xc0ed, 0x6852, 0x080c, 0x5271, 0x2c68, 0x080c,
+	0x8295, 0x0150, 0x6818, 0x601a, 0x080c, 0x9c35, 0x00c6, 0x2d60,
+	0x080c, 0x9a2b, 0x00ce, 0x0008, 0x2d60, 0x00de, 0x6013, 0x0000,
+	0x601f, 0x0001, 0x6007, 0x0001, 0x6003, 0x0001, 0x080c, 0x6a3c,
+	0x080c, 0x6e9e, 0x0078, 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186,
+	0x0039, 0x0118, 0xa186, 0x0035, 0x1118, 0x080c, 0x2b73, 0x08b0,
+	0x080c, 0x9a2b, 0x0005, 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x14fa,
+	0x000b, 0x0005, 0x984a, 0x984a, 0x984a, 0x984c, 0x984d, 0x984a,
+	0x984a, 0x984a, 0x984a, 0x984a, 0x984a, 0x984a, 0x984a, 0x984a,
+	0x984a, 0x984a, 0x080c, 0x14fa, 0x0005, 0x080c, 0x7f2b, 0x190c,
+	0x14fa, 0x6110, 0x2168, 0x684b, 0x0006, 0x080c, 0x5271, 0x080c,
+	0x82eb, 0x0005, 0xa284, 0x0007, 0x1158, 0xa282, 0xb800, 0x0240,
+	0x2001, 0xb116, 0x2004, 0xa202, 0x1218, 0xa085, 0x0001, 0x0005,
+	0xa006, 0x0ce8, 0x0026, 0x6210, 0xa294, 0xf000, 0x002e, 0x0005,
+	0x00e6, 0x00c6, 0x0036, 0x0006, 0x0126, 0x2091, 0x8000, 0x2061,
+	0xb800, 0x2071, 0xb100, 0x7344, 0x7064, 0xa302, 0x12a8, 0x601c,
+	0xa206, 0x1160, 0x080c, 0x9bc0, 0x0148, 0x080c, 0x9a66, 0x1110,
+	0x080c, 0x8890, 0x00c6, 0x080c, 0x82eb, 0x00ce, 0xace0, 0x0018,
+	0x7058, 0xac02, 0x1208, 0x0c38, 0x012e, 0x000e, 0x003e, 0x00ce,
+	0x00ee, 0x0005, 0x00e6, 0x00c6, 0x0016, 0xa188, 0xb235, 0x210c,
+	0x81ff, 0x0170, 0x2061, 0xb800, 0x2071, 0xb100, 0x0016, 0x080c,
+	0x8295, 0x001e, 0x0138, 0x611a, 0x080c, 0x2b73, 0x080c, 0x82eb,
+	0xa006, 0x0010, 0xa085, 0x0001, 0x001e, 0x00ce, 0x00ee, 0x0005,
+	0x00c6, 0x0056, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x8295,
+	0x005e, 0x0180, 0x6612, 0x651a, 0x080c, 0x9c35, 0x601f, 0x0003,
+	0x2009, 0x004b, 0x080c, 0x831a, 0xa085, 0x0001, 0x012e, 0x005e,
+	0x00ce, 0x0005, 0xa006, 0x0cd0, 0x00c6, 0x0056, 0x0126, 0x2091,
+	0x8000, 0x62a0, 0x00c6, 0x080c, 0x9ae4, 0x005e, 0x0550, 0x6013,
+	0x0000, 0x651a, 0x080c, 0x9c35, 0x601f, 0x0003, 0x0016, 0x00c6,
+	0x2560, 0x080c, 0x501c, 0x00ce, 0x080c, 0x6b35, 0x0076, 0x2039,
+	0x0000, 0x080c, 0x6a6b, 0x2c08, 0x080c, 0xaa51, 0x007e, 0x001e,
+	0xd184, 0x0128, 0x080c, 0x82eb, 0xa085, 0x0001, 0x0030, 0x2009,
+	0x004c, 0x080c, 0x831a, 0xa085, 0x0001, 0x012e, 0x005e, 0x00ce,
+	0x0005, 0xa006, 0x0cd0, 0x00f6, 0x00c6, 0x0046, 0x00c6, 0x080c,
+	0x8295, 0x2c78, 0x00ce, 0x0180, 0x7e12, 0x2c00, 0x781a, 0x781f,
+	0x0003, 0x2021, 0x0005, 0x080c, 0x9960, 0x2f60, 0x2009, 0x004d,
+	0x080c, 0x831a, 0xa085, 0x0001, 0x004e, 0x00ce, 0x00fe, 0x0005,
+	0x00f6, 0x00c6, 0x0046, 0x00c6, 0x080c, 0x8295, 0x2c78, 0x00ce,
+	0x0178, 0x7e12, 0x2c00, 0x781a, 0x781f, 0x0003, 0x2021, 0x0005,
+	0x0439, 0x2f60, 0x2009, 0x004e, 0x080c, 0x831a, 0xa085, 0x0001,
+	0x004e, 0x00ce, 0x00fe, 0x0005, 0x00f6, 0x00c6, 0x0046, 0x00c6,
+	0x080c, 0x8295, 0x2c78, 0x00ce, 0x0178, 0x7e12, 0x2c00, 0x781a,
+	0x781f, 0x0003, 0x2021, 0x0004, 0x0059, 0x2f60, 0x2009, 0x0052,
+	0x080c, 0x831a, 0xa085, 0x0001, 0x004e, 0x00ce, 0x00fe, 0x0005,
+	0x0096, 0x0076, 0x0126, 0x2091, 0x8000, 0x080c, 0x4fbe, 0x0118,
+	0x2001, 0x9965, 0x0028, 0x080c, 0x4f90, 0x0158, 0x2001, 0x996b,
+	0x0006, 0xa00e, 0x2400, 0x080c, 0x5344, 0x080c, 0x5271, 0x000e,
+	0x0807, 0x2418, 0x080c, 0x6d63, 0x62a0, 0x0086, 0x2041, 0x0001,
+	0x2039, 0x0001, 0x2608, 0x080c, 0x6b4e, 0x008e, 0x080c, 0x6a6b,
+	0x2f08, 0x2648, 0x080c, 0xaa51, 0x613c, 0x81ff, 0x090c, 0x6bf7,
+	0x012e, 0x007e, 0x009e, 0x0005, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x00c6, 0x080c, 0x8295, 0x001e, 0x0188, 0x660a, 0x611a, 0x080c,
+	0x9c35, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x001f, 0x080c,
+	0x831a, 0xa085, 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x8295, 0x001e,
+	0x0188, 0x660a, 0x611a, 0x080c, 0x9c35, 0x601f, 0x0008, 0x2d00,
+	0x6012, 0x2009, 0x0021, 0x080c, 0x831a, 0xa085, 0x0001, 0x012e,
+	0x00ce, 0x0005, 0xa006, 0x0cd8, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x00c6, 0x080c, 0x8295, 0x001e, 0x0188, 0x660a, 0x611a, 0x080c,
+	0x9c35, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x003d, 0x080c,
+	0x831a, 0xa085, 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x9ae4, 0x001e,
+	0x0180, 0x611a, 0x080c, 0x9c35, 0x601f, 0x0001, 0x2d00, 0x6012,
+	0x2009, 0x0000, 0x080c, 0x831a, 0xa085, 0x0001, 0x012e, 0x00ce,
+	0x0005, 0xa006, 0x0cd8, 0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6,
+	0x080c, 0x8295, 0x001e, 0x0188, 0x660a, 0x611a, 0x080c, 0x9c35,
+	0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x0044, 0x080c, 0x831a,
+	0xa085, 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8, 0x0026,
+	0x00d6, 0x6218, 0x2268, 0x6a3c, 0x82ff, 0x0110, 0x8211, 0x6a3e,
+	0x00de, 0x002e, 0x0005, 0x0006, 0x6000, 0xa086, 0x0000, 0x0190,
+	0x6013, 0x0000, 0x601f, 0x0007, 0x2001, 0xb3b5, 0x2004, 0x0006,
+	0xa082, 0x0051, 0x000e, 0x0208, 0x8004, 0x6016, 0x080c, 0xaf00,
+	0x603f, 0x0000, 0x000e, 0x0005, 0x0066, 0x00c6, 0x00d6, 0x2031,
+	0xb153, 0x2634, 0xd6e4, 0x0128, 0x6618, 0x2660, 0x6e48, 0x080c,
+	0x4f49, 0x00de, 0x00ce, 0x006e, 0x0005, 0x0006, 0x0016, 0x6004,
+	0xa08e, 0x0002, 0x0140, 0xa08e, 0x0003, 0x0128, 0xa08e, 0x0004,
+	0x0110, 0xa085, 0x0001, 0x001e, 0x000e, 0x0005, 0x0006, 0x00d6,
+	0x6010, 0xa06d, 0x0148, 0x6834, 0xa086, 0x0139, 0x0138, 0x6838,
+	0xd0fc, 0x0110, 0xa006, 0x0010, 0xa085, 0x0001, 0x00de, 0x000e,
+	0x0005, 0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x8295,
+	0x001e, 0x0190, 0x611a, 0x080c, 0x9c35, 0x601f, 0x0001, 0x2d00,
+	0x6012, 0x080c, 0x2b73, 0x2009, 0x0028, 0x080c, 0x831a, 0xa085,
+	0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8, 0xa186, 0x0015,
+	0x1178, 0x2011, 0xb120, 0x2204, 0xa086, 0x0074, 0x1148, 0x080c,
+	0x8bed, 0x6003, 0x0001, 0x6007, 0x0029, 0x080c, 0x6a3c, 0x0020,
+	0x080c, 0x8890, 0x080c, 0x82eb, 0x0005, 0xa186, 0x0016, 0x1128,
+	0x2001, 0x0004, 0x080c, 0x4d75, 0x00e8, 0xa186, 0x0015, 0x11e8,
+	0x2011, 0xb120, 0x2204, 0xa086, 0x0014, 0x11b8, 0x00d6, 0x6018,
+	0x2068, 0x080c, 0x4ebf, 0x00de, 0x080c, 0x8ca6, 0x1170, 0x00d6,
+	0x6018, 0x2068, 0x6890, 0x00de, 0xa005, 0x0138, 0x2001, 0x0006,
+	0x080c, 0x4d75, 0x080c, 0x8469, 0x0020, 0x080c, 0x8890, 0x080c,
+	0x82eb, 0x0005, 0x6848, 0xa086, 0x0005, 0x1108, 0x0009, 0x0005,
+	0x6850, 0xc0ad, 0x6852, 0x0005, 0x00e6, 0x0126, 0x2071, 0xb100,
+	0x2091, 0x8000, 0x7544, 0xa582, 0x0001, 0x0608, 0x7048, 0x2060,
+	0x6000, 0xa086, 0x0000, 0x0148, 0xace0, 0x0018, 0x7058, 0xac02,
+	0x1208, 0x0cb0, 0x2061, 0xb800, 0x0c98, 0x6003, 0x0008, 0x8529,
+	0x7546, 0xaca8, 0x0018, 0x7058, 0xa502, 0x1230, 0x754a, 0xa085,
+	0x0001, 0x012e, 0x00ee, 0x0005, 0x704b, 0xb800, 0x0cc0, 0xa006,
+	0x0cc0, 0x00e6, 0x2071, 0xb68c, 0x7014, 0xd0e4, 0x0150, 0x6013,
+	0x0000, 0x6003, 0x0001, 0x6007, 0x0050, 0x080c, 0x69f6, 0x080c,
+	0x6e9e, 0x00ee, 0x0005, 0x00c6, 0x00f6, 0x2c78, 0x080c, 0x5177,
+	0x00fe, 0x0120, 0x601c, 0xa084, 0x000f, 0x0013, 0x00ce, 0x0005,
+	0x9630, 0x9b3b, 0x9b3e, 0x9b41, 0xaced, 0xad08, 0xad0b, 0x9630,
+	0x9630, 0x080c, 0x14fa, 0xe000, 0xe000, 0x0005, 0xe000, 0xe000,
+	0x0005, 0x0009, 0x0005, 0x00f6, 0x2c78, 0x080c, 0x5177, 0x0538,
+	0x080c, 0x8295, 0x1128, 0x2001, 0xb3b7, 0x2004, 0x783e, 0x00f8,
+	0x7818, 0x601a, 0x080c, 0x9c35, 0x781c, 0xa086, 0x0003, 0x0128,
+	0x7808, 0x6036, 0x2f00, 0x603a, 0x0020, 0x7808, 0x603a, 0x2f00,
+	0x6036, 0x602a, 0x601f, 0x0001, 0x6007, 0x0035, 0x6003, 0x0001,
+	0x7950, 0x6152, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x2f60, 0x00fe,
+	0x0005, 0x0016, 0x00f6, 0x682c, 0x6032, 0xa08e, 0x0001, 0x0138,
+	0xa086, 0x0005, 0x0140, 0xa006, 0x602a, 0x602e, 0x00a0, 0x6820,
+	0xc0f4, 0xc0d5, 0x6822, 0x6810, 0x2078, 0x787c, 0x6938, 0xa102,
+	0x7880, 0x6934, 0xa103, 0x1e78, 0x6834, 0x602a, 0x6838, 0xa084,
+	0xfffc, 0x683a, 0x602e, 0x2d00, 0x6036, 0x6808, 0x603a, 0x6918,
+	0x611a, 0x6950, 0x6152, 0x601f, 0x0001, 0x6007, 0x0039, 0x6003,
+	0x0001, 0x080c, 0x69f6, 0x6803, 0x0002, 0x00fe, 0x001e, 0x0005,
+	0x00f6, 0x2c78, 0x080c, 0x5177, 0x1118, 0xa085, 0x0001, 0x0070,
+	0x6020, 0xd0f4, 0x1150, 0xc0f5, 0x6022, 0x6010, 0x2078, 0x7828,
+	0x603a, 0x782c, 0x6036, 0x080c, 0x190f, 0xa006, 0x00fe, 0x0005,
+	0x0006, 0x0016, 0x6004, 0xa08e, 0x0034, 0x01b8, 0xa08e, 0x0035,
+	0x01a0, 0xa08e, 0x0036, 0x0188, 0xa08e, 0x0037, 0x0170, 0xa08e,
+	0x0038, 0x0158, 0xa08e, 0x0039, 0x0140, 0xa08e, 0x003a, 0x0128,
+	0xa08e, 0x003b, 0x0110, 0xa085, 0x0001, 0x001e, 0x000e, 0x0005,
+	0x0006, 0x0016, 0x0026, 0x0036, 0x00e6, 0x2001, 0xb3b1, 0x200c,
+	0x8000, 0x2014, 0x2001, 0x0032, 0x080c, 0x68b3, 0x2001, 0xb3b5,
+	0x82ff, 0x1110, 0x2011, 0x0002, 0x2202, 0x2001, 0xb3b3, 0x200c,
+	0x8000, 0x2014, 0x2071, 0xb38e, 0x711a, 0x721e, 0x2001, 0x0064,
+	0x080c, 0x68b3, 0x2001, 0xb3b6, 0x82ff, 0x1110, 0x2011, 0x0002,
+	0x2202, 0x2009, 0xb3b7, 0xa280, 0x000a, 0x200a, 0x080c, 0x5193,
+	0x00ee, 0x003e, 0x002e, 0x001e, 0x000e, 0x0005, 0x0006, 0x00e6,
+	0x2001, 0xb3b5, 0x2003, 0x0028, 0x2001, 0xb3b6, 0x2003, 0x0014,
+	0x2071, 0xb38e, 0x701b, 0x0000, 0x701f, 0x07d0, 0x2001, 0xb3b7,
+	0x2003, 0x001e, 0x00ee, 0x000e, 0x0005, 0x00d6, 0x6054, 0xa06d,
+	0x0110, 0x080c, 0x15f4, 0x00de, 0x0005, 0x0005, 0x00c6, 0x0126,
+	0x2091, 0x8000, 0x00c6, 0x080c, 0x8295, 0x001e, 0x0178, 0x611a,
+	0x0ca1, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x0033, 0x080c,
+	0x831a, 0xa085, 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8,
+	0x00d6, 0x00e6, 0x00f6, 0x2071, 0xb100, 0xa186, 0x0015, 0x1500,
+	0x7080, 0xa086, 0x0018, 0x11e0, 0x6010, 0x2068, 0x6a3c, 0xd2e4,
+	0x1160, 0x2c78, 0x080c, 0x705a, 0x01d8, 0x706c, 0x6a50, 0xa206,
+	0x1160, 0x7070, 0x6a54, 0xa206, 0x1140, 0x6218, 0xa290, 0x0028,
+	0x2214, 0x2009, 0x0000, 0x080c, 0x2bb8, 0x080c, 0x8469, 0x0020,
+	0x080c, 0x8890, 0x080c, 0x82eb, 0x00fe, 0x00ee, 0x00de, 0x0005,
+	0x7050, 0x6a54, 0xa206, 0x0d48, 0x0c80, 0x00c6, 0x0126, 0x2091,
+	0x8000, 0x00c6, 0x080c, 0x8295, 0x001e, 0x0180, 0x611a, 0x080c,
+	0x9c35, 0x601f, 0x0001, 0x2d00, 0x6012, 0x2009, 0x0043, 0x080c,
+	0x831a, 0xa085, 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8,
+	0x00d6, 0x00e6, 0x00f6, 0x2071, 0xb100, 0xa186, 0x0015, 0x11c0,
+	0x7080, 0xa086, 0x0004, 0x11a0, 0x6010, 0xa0e8, 0x000f, 0x2c78,
+	0x080c, 0x705a, 0x01a8, 0x706c, 0x6a08, 0xa206, 0x1130, 0x7070,
+	0x6a0c, 0xa206, 0x1110, 0x080c, 0x2b73, 0x080c, 0x8469, 0x0020,
+	0x080c, 0x8890, 0x080c, 0x82eb, 0x00fe, 0x00ee, 0x00de, 0x0005,
+	0x7050, 0x6a0c, 0xa206, 0x0d78, 0x0c80, 0x0016, 0x0026, 0x684c,
+	0xd0ac, 0x0178, 0x6914, 0x6a10, 0x2100, 0xa205, 0x0150, 0x6860,
+	0xa106, 0x1118, 0x685c, 0xa206, 0x0120, 0x6962, 0x6a5e, 0xa085,
+	0x0001, 0x002e, 0x001e, 0x0005, 0x00d6, 0x0036, 0x6310, 0x2368,
+	0x684a, 0x6952, 0xa29e, 0x4000, 0x11a0, 0x00c6, 0x6318, 0x2360,
+	0x2009, 0x0000, 0x6838, 0xd0f4, 0x1140, 0x080c, 0x50bc, 0x1108,
+	0xc185, 0x6000, 0xd0bc, 0x0108, 0xc18d, 0x6a66, 0x696a, 0x00ce,
+	0x0080, 0x6a66, 0x3918, 0xa398, 0x0006, 0x231c, 0x686b, 0x0004,
+	0x6b72, 0x00c6, 0x6318, 0x2360, 0x6004, 0xa084, 0x00ff, 0x686e,
+	0x00ce, 0x080c, 0x5271, 0x003e, 0x00de, 0x0005, 0x00c6, 0x0026,
+	0x0016, 0xa186, 0x0035, 0x0110, 0x6a34, 0x0008, 0x6a28, 0x080c,
+	0x985a, 0x01f0, 0x2260, 0x611c, 0xa186, 0x0003, 0x0118, 0xa186,
+	0x0006, 0x1190, 0x6834, 0xa206, 0x0140, 0x6838, 0xa206, 0x1160,
+	0x6108, 0x6834, 0xa106, 0x1140, 0x0020, 0x6008, 0x6938, 0xa106,
+	0x1118, 0x6018, 0x6918, 0xa106, 0x001e, 0x002e, 0x00ce, 0x0005,
+	0xa085, 0x0001, 0x0cc8, 0x0066, 0x6000, 0xa0b2, 0x0010, 0x1a0c,
+	0x14fa, 0x0013, 0x006e, 0x0005, 0x9d5c, 0xa224, 0xa353, 0x9d5c,
+	0x9d5c, 0x9d5c, 0x9d5c, 0x9d5c, 0x9d94, 0xa3cf, 0x9d5c, 0x9d5c,
+	0x9d5c, 0x9d5c, 0x9d5c, 0x9d5c, 0x080c, 0x14fa, 0x0066, 0x6000,
+	0xa0b2, 0x0010, 0x1a0c, 0x14fa, 0x0013, 0x006e, 0x0005, 0x9d77,
+	0xa846, 0x9d77, 0x9d77, 0x9d77, 0x9d77, 0x9d77, 0x9d77, 0xa80a,
+	0xa88e, 0x9d77, 0xae32, 0xae62, 0xae32, 0xae62, 0x9d77, 0x080c,
+	0x14fa, 0x0066, 0x6000, 0xa0b2, 0x0010, 0x1a0c, 0x14fa, 0x0013,
+	0x006e, 0x0005, 0x9d92, 0xa511, 0xa5de, 0xa60b, 0xa68f, 0x9d92,
+	0xa77c, 0xa727, 0xa3db, 0xa7e0, 0xa7f5, 0x9d92, 0x9d92, 0x9d92,
+	0x9d92, 0x9d92, 0x080c, 0x14fa, 0xa1b2, 0x0080, 0x1a0c, 0x14fa,
+	0x2100, 0xa1b2, 0x0040, 0x1a04, 0xa198, 0x0002, 0x9dde, 0x9fa9,
+	0x9dde, 0x9dde, 0x9dde, 0x9fb0, 0x9dde, 0x9dde, 0x9dde, 0x9dde,
+	0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde,
+	0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9de0, 0x9e3e, 0x9e4d,
+	0x9e9b, 0x9eb9, 0x9f37, 0x9f96, 0x9dde, 0x9dde, 0x9fb3, 0x9dde,
+	0x9dde, 0x9fc6, 0x9fd1, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde,
+	0xa04d, 0x9dde, 0x9dde, 0xa05c, 0x9dde, 0x9dde, 0xa023, 0x9dde,
+	0x9dde, 0x9dde, 0xa074, 0x9dde, 0x9dde, 0x9dde, 0xa0ee, 0x9dde,
+	0x9dde, 0x9dde, 0x9dde, 0x9dde, 0x9dde, 0xa15f, 0x080c, 0x14fa,
+	0x080c, 0x517b, 0x1150, 0x2001, 0xb134, 0x2004, 0xd0cc, 0x1128,
+	0xa084, 0x0009, 0xa086, 0x0008, 0x1140, 0x6007, 0x0009, 0x602b,
+	0x0009, 0x6013, 0x0000, 0x0804, 0x9fa4, 0x080c, 0x516b, 0x00e6,
+	0x00c6, 0x0036, 0x0026, 0x0016, 0x6218, 0x2270, 0x72a0, 0x0026,
+	0x2019, 0x0029, 0x080c, 0x6b35, 0x0076, 0x2039, 0x0000, 0x080c,
+	0x6a6b, 0x2c08, 0x080c, 0xaa51, 0x007e, 0x001e, 0x2e60, 0x080c,
+	0x501c, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee, 0x6618, 0x00c6,
+	0x2660, 0x080c, 0x4e30, 0x00ce, 0xa6b0, 0x0001, 0x2634, 0xa684,
+	0x00ff, 0xa082, 0x0006, 0x0278, 0x080c, 0xa995, 0x1904, 0x9e95,
+	0x080c, 0xa935, 0x1120, 0x6007, 0x0008, 0x0804, 0x9fa4, 0x6007,
+	0x0009, 0x0804, 0x9fa4, 0x080c, 0xab41, 0x0128, 0x080c, 0xa995,
+	0x0d78, 0x0804, 0x9e95, 0x6013, 0x1900, 0x0c88, 0x080c, 0x2c87,
+	0x1904, 0xa195, 0x6106, 0x080c, 0xa8ef, 0x6007, 0x0006, 0x0804,
+	0x9fa4, 0x6007, 0x0007, 0x0804, 0x9fa4, 0x080c, 0xae96, 0x1904,
+	0xa195, 0x080c, 0x2c87, 0x1904, 0xa195, 0x00d6, 0x6618, 0x2668,
+	0x6e04, 0xa684, 0x00ff, 0xa082, 0x0006, 0x1220, 0x2001, 0x0001,
+	0x080c, 0x4d63, 0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0188,
+	0xa686, 0x0004, 0x0170, 0x6e04, 0xa6b4, 0x00ff, 0xa686, 0x0006,
+	0x0140, 0xa686, 0x0004, 0x0128, 0xa686, 0x0005, 0x0110, 0x00de,
+	0x00e0, 0x080c, 0xa9f3, 0x11a0, 0xa686, 0x0006, 0x1150, 0x0026,
+	0x6218, 0xa290, 0x0028, 0x2214, 0x2009, 0x0000, 0x080c, 0x2bb8,
+	0x002e, 0x080c, 0x4ebf, 0x6007, 0x000a, 0x00de, 0x0804, 0x9fa4,
+	0x6007, 0x000b, 0x00de, 0x0804, 0x9fa4, 0x080c, 0x2b73, 0x6007,
+	0x0001, 0x0804, 0x9fa4, 0x080c, 0xae96, 0x1904, 0xa195, 0x080c,
+	0x2c87, 0x1904, 0xa195, 0x6618, 0x00d6, 0x2668, 0x6e04, 0x00de,
+	0xa686, 0x0707, 0x0d50, 0x0026, 0x6218, 0xa290, 0x0028, 0x2214,
+	0x2009, 0x0000, 0x080c, 0x2bb8, 0x002e, 0x6007, 0x000c, 0x0804,
+	0x9fa4, 0x080c, 0x517b, 0x1140, 0x2001, 0xb134, 0x2004, 0xa084,
+	0x0009, 0xa086, 0x0008, 0x1110, 0x0804, 0x9ded, 0x080c, 0x516b,
+	0x6618, 0xa6b0, 0x0001, 0x2634, 0xa684, 0x00ff, 0xa082, 0x0006,
+	0x06e8, 0x1138, 0x0026, 0x2001, 0x0006, 0x080c, 0x4da2, 0x002e,
+	0x0050, 0xa6b4, 0xff00, 0x8637, 0xa686, 0x0004, 0x0120, 0xa686,
+	0x0006, 0x1904, 0x9e95, 0x080c, 0xaa00, 0x1120, 0x6007, 0x000e,
+	0x0804, 0x9fa4, 0x0046, 0x6418, 0xa4a0, 0x0028, 0x2424, 0xa4a4,
+	0x00ff, 0x8427, 0x0046, 0x080c, 0x2b73, 0x004e, 0x0016, 0xa006,
+	0x2009, 0xb153, 0x210c, 0xd1a4, 0x0158, 0x2009, 0x0029, 0x080c,
+	0xacae, 0x6018, 0x00d6, 0x2068, 0x6800, 0xc0e5, 0x6802, 0x00de,
+	0x001e, 0x004e, 0x6007, 0x0001, 0x0804, 0x9fa4, 0x2001, 0x0001,
+	0x080c, 0x4d63, 0x0156, 0x0016, 0x0026, 0x0036, 0x20a9, 0x0004,
+	0x2019, 0xb105, 0x2011, 0xb690, 0x080c, 0x8d2b, 0x003e, 0x002e,
+	0x001e, 0x015e, 0xa005, 0x0168, 0xa6b4, 0xff00, 0x8637, 0xa682,
+	0x0004, 0x0a04, 0x9e95, 0xa682, 0x0007, 0x0a04, 0x9ee3, 0x0804,
+	0x9e95, 0x6013, 0x1900, 0x6007, 0x0009, 0x0804, 0x9fa4, 0x080c,
+	0x517b, 0x1140, 0x2001, 0xb134, 0x2004, 0xa084, 0x0009, 0xa086,
+	0x0008, 0x1110, 0x0804, 0x9ded, 0x080c, 0x516b, 0x6618, 0xa6b0,
+	0x0001, 0x2634, 0xa684, 0x00ff, 0xa082, 0x0006, 0x06b8, 0xa6b4,
+	0xff00, 0x8637, 0xa686, 0x0004, 0x0120, 0xa686, 0x0006, 0x1904,
+	0x9e95, 0x080c, 0xaa28, 0x1138, 0x080c, 0xa935, 0x1120, 0x6007,
+	0x0010, 0x0804, 0x9fa4, 0x0046, 0x6418, 0xa4a0, 0x0028, 0x2424,
+	0xa4a4, 0x00ff, 0x8427, 0x0046, 0x080c, 0x2b73, 0x004e, 0x0016,
+	0xa006, 0x2009, 0xb153, 0x210c, 0xd1a4, 0x0158, 0x2009, 0x0029,
+	0x080c, 0xacae, 0x6018, 0x00d6, 0x2068, 0x6800, 0xc0e5, 0x6802,
+	0x00de, 0x001e, 0x004e, 0x6007, 0x0001, 0x00f0, 0x080c, 0xab41,
+	0x0140, 0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0950, 0x0804,
+	0x9e95, 0x6013, 0x1900, 0x6007, 0x0009, 0x0070, 0x080c, 0x2c87,
+	0x1904, 0xa195, 0x080c, 0xae96, 0x1904, 0xa195, 0x080c, 0xa1bd,
+	0x1904, 0x9e95, 0x6007, 0x0012, 0x6003, 0x0001, 0x080c, 0x6a3c,
+	0x0005, 0x6007, 0x0001, 0x6003, 0x0001, 0x080c, 0x6a3c, 0x0cc0,
+	0x6007, 0x0005, 0x0cc0, 0x080c, 0xae96, 0x1904, 0xa195, 0x080c,
+	0x2c87, 0x1904, 0xa195, 0x080c, 0xa1bd, 0x1904, 0x9e95, 0x6007,
+	0x0020, 0x6003, 0x0001, 0x080c, 0x6a3c, 0x0005, 0x080c, 0x2c87,
+	0x1904, 0xa195, 0x6007, 0x0023, 0x6003, 0x0001, 0x080c, 0x6a3c,
+	0x0005, 0x080c, 0xae96, 0x1904, 0xa195, 0x080c, 0x2c87, 0x1904,
+	0xa195, 0x080c, 0xa1bd, 0x1904, 0x9e95, 0x0016, 0x0026, 0x2011,
+	0xb691, 0x2214, 0xa286, 0xffff, 0x0190, 0x2c08, 0x080c, 0x985a,
+	0x01e0, 0x2260, 0x2011, 0xb690, 0x2214, 0x6008, 0xa206, 0x11a8,
+	0x6018, 0xa190, 0x0006, 0x2214, 0xa206, 0x01e8, 0x0070, 0x2011,
+	0xb690, 0x2214, 0x2c08, 0xa006, 0x080c, 0xac80, 0x11a0, 0x2011,
+	0xb691, 0x2214, 0xa286, 0xffff, 0x01a0, 0x2160, 0x6007, 0x0026,
+	0x6013, 0x1700, 0x2011, 0xb689, 0x2214, 0xa296, 0xffff, 0x1160,
+	0x6007, 0x0025, 0x0048, 0x601c, 0xa086, 0x0007, 0x1d70, 0x080c,
+	0x82eb, 0x2160, 0x6007, 0x0025, 0x6003, 0x0001, 0x080c, 0x6a3c,
+	0x002e, 0x001e, 0x0005, 0x2001, 0x0001, 0x080c, 0x4d63, 0x0156,
+	0x0016, 0x0026, 0x0036, 0x20a9, 0x0004, 0x2019, 0xb105, 0x2011,
+	0xb696, 0x080c, 0x8d2b, 0x003e, 0x002e, 0x001e, 0x015e, 0x0120,
+	0x6007, 0x0031, 0x0804, 0x9fa4, 0x080c, 0x8a69, 0x080c, 0x58d5,
+	0x1158, 0x0006, 0x0026, 0x0036, 0x080c, 0x58f1, 0x0110, 0x080c,
+	0x58ac, 0x003e, 0x002e, 0x000e, 0x0005, 0x080c, 0x2c87, 0x1904,
+	0xa195, 0x6106, 0x080c, 0xa1d9, 0x6007, 0x002b, 0x0804, 0x9fa4,
+	0x6007, 0x002c, 0x0804, 0x9fa4, 0x080c, 0xae96, 0x1904, 0xa195,
+	0x080c, 0x2c87, 0x1904, 0xa195, 0x080c, 0xa1bd, 0x1904, 0x9e95,
+	0x6106, 0x080c, 0xa1dd, 0x1120, 0x6007, 0x002e, 0x0804, 0x9fa4,
+	0x6007, 0x002f, 0x0804, 0x9fa4, 0x080c, 0x2c87, 0x1904, 0xa195,
+	0x00e6, 0x00d6, 0x00c6, 0x6018, 0xa080, 0x0001, 0x200c, 0xa184,
+	0x00ff, 0xa086, 0x0006, 0x0158, 0xa184, 0xff00, 0x8007, 0xa086,
+	0x0006, 0x0128, 0x00ce, 0x00de, 0x00ee, 0x0804, 0x9fa9, 0x2001,
+	0xb172, 0x2004, 0xd0e4, 0x0904, 0xa0eb, 0x2071, 0xb68c, 0x7010,
+	0x6036, 0x7014, 0x603a, 0x7108, 0x720c, 0x2001, 0xb153, 0x2004,
+	0xd0a4, 0x0140, 0x6018, 0x2068, 0x6810, 0xa106, 0x1118, 0x6814,
+	0xa206, 0x01f8, 0x2001, 0xb153, 0x2004, 0xd0ac, 0x1590, 0x2069,
+	0xb100, 0x6870, 0xa206, 0x1568, 0x686c, 0xa106, 0x1550, 0x7210,
+	0x080c, 0x985a, 0x0558, 0x080c, 0xad1a, 0x0540, 0x622a, 0x6007,
+	0x0036, 0x6003, 0x0001, 0x080c, 0x69f6, 0x00ce, 0x00de, 0x00ee,
+	0x0005, 0x7214, 0xa286, 0xffff, 0x0150, 0x080c, 0x985a, 0x01b0,
+	0xa280, 0x0002, 0x2004, 0x7110, 0xa106, 0x1180, 0x0c08, 0x7210,
+	0x2c08, 0xa085, 0x0001, 0x080c, 0xac80, 0x2c10, 0x2160, 0x0130,
+	0x08b8, 0x6007, 0x0037, 0x6013, 0x1500, 0x08d8, 0x6007, 0x0037,
+	0x6013, 0x1700, 0x08b0, 0x6007, 0x0012, 0x0898, 0x080c, 0x2c87,
+	0x1904, 0xa195, 0x6018, 0xa080, 0x0001, 0x2004, 0xa084, 0xff00,
+	0x8007, 0xa086, 0x0006, 0x1904, 0x9fa9, 0x00e6, 0x00d6, 0x00c6,
+	0x2001, 0xb172, 0x2004, 0xd0e4, 0x0904, 0xa157, 0x2069, 0xb100,
+	0x2071, 0xb68c, 0x7008, 0x6036, 0x720c, 0x623a, 0xa286, 0xffff,
+	0x1150, 0x7208, 0x00c6, 0x2c08, 0xa085, 0x0001, 0x080c, 0xac80,
+	0x2c10, 0x00ce, 0x0588, 0x080c, 0x985a, 0x0570, 0x00c6, 0x0026,
+	0x2260, 0x080c, 0x954f, 0x002e, 0x00ce, 0x7118, 0xa18c, 0xff00,
+	0x810f, 0xa186, 0x0001, 0x0158, 0xa186, 0x0005, 0x0118, 0xa186,
+	0x0007, 0x1178, 0xa280, 0x0004, 0x2004, 0xa005, 0x0150, 0x0056,
+	0x7510, 0x7614, 0x080c, 0xad31, 0x005e, 0x00ce, 0x00de, 0x00ee,
+	0x0005, 0x6007, 0x003b, 0x602b, 0x0009, 0x6013, 0x2a00, 0x6003,
+	0x0001, 0x080c, 0x69f6, 0x0c88, 0x6007, 0x003b, 0x602b, 0x0009,
+	0x6013, 0x1700, 0x6003, 0x0001, 0x080c, 0x69f6, 0x0c30, 0x6007,
+	0x003b, 0x602b, 0x000b, 0x6013, 0x0000, 0x0804, 0xa0c1, 0x00e6,
+	0x0026, 0x080c, 0x517b, 0x0558, 0x080c, 0x516b, 0x080c, 0xaf11,
+	0x1520, 0x2071, 0xb100, 0x70d0, 0xc085, 0x70d2, 0x00f6, 0x2079,
+	0x0100, 0x729c, 0xa284, 0x00ff, 0x706e, 0x78e6, 0xa284, 0xff00,
+	0x7270, 0xa205, 0x7072, 0x78ea, 0x00fe, 0x70db, 0x0000, 0x2001,
+	0xb153, 0x2004, 0xd0a4, 0x0120, 0x2011, 0xb3f2, 0x2013, 0x07d0,
+	0xd0ac, 0x1128, 0x080c, 0x2991, 0x0010, 0x080c, 0xaf3d, 0x002e,
+	0x00ee, 0x080c, 0x82eb, 0x0804, 0x9fa8, 0x080c, 0x82eb, 0x0005,
+	0x2600, 0x0002, 0xa1a3, 0xa1a3, 0xa1a3, 0xa1a3, 0xa1a3, 0xa1a5,
+	0xa1a3, 0xa1a3, 0xa1a3, 0x080c, 0x14fa, 0x080c, 0xae96, 0x1d68,
+	0x080c, 0x2c87, 0x1d50, 0x0089, 0x1138, 0x6007, 0x0045, 0x6003,
+	0x0001, 0x080c, 0x6a3c, 0x0005, 0x080c, 0x2b73, 0x6007, 0x0001,
+	0x6003, 0x0001, 0x080c, 0x6a3c, 0x0005, 0x00d6, 0x0066, 0x6618,
+	0x2668, 0x6e04, 0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0170,
+	0xa686, 0x0004, 0x0158, 0x6e04, 0xa6b4, 0x00ff, 0xa686, 0x0006,
+	0x0128, 0xa686, 0x0004, 0x0110, 0xa085, 0x0001, 0x006e, 0x00de,
+	0x0005, 0x00d6, 0x0449, 0x00de, 0x0005, 0x00d6, 0x0491, 0x11f0,
+	0x680c, 0xa08c, 0xff00, 0x6820, 0xa084, 0x00ff, 0xa115, 0x6212,
+	0x6824, 0x602a, 0xd1e4, 0x0118, 0x2009, 0x0001, 0x0060, 0xd1ec,
+	0x0168, 0x6920, 0xa18c, 0x00ff, 0x6824, 0x080c, 0x26f6, 0x1130,
+	0x2110, 0x2009, 0x0000, 0x080c, 0x2bb8, 0x0018, 0xa085, 0x0001,
+	0x0008, 0xa006, 0x00de, 0x0005, 0x2069, 0xb68d, 0x6800, 0xa082,
+	0x0010, 0x1228, 0x6013, 0x0000, 0xa085, 0x0001, 0x0008, 0xa006,
+	0x0005, 0x6013, 0x0000, 0x2069, 0xb68c, 0x6808, 0xa084, 0xff00,
+	0xa086, 0x0800, 0x1140, 0x6800, 0xa084, 0x00ff, 0xa08e, 0x0014,
+	0x0110, 0xa08e, 0x0010, 0x0005, 0x6004, 0xa0b2, 0x0080, 0x1a0c,
+	0x14fa, 0xa1b6, 0x0013, 0x1130, 0x2008, 0xa1b2, 0x0040, 0x1a04,
+	0xa324, 0x0092, 0xa1b6, 0x0027, 0x0120, 0xa1b6, 0x0014, 0x190c,
+	0x14fa, 0x2001, 0x0007, 0x080c, 0x4da2, 0x080c, 0x6dc1, 0x080c,
+	0x9a2b, 0x080c, 0x6e9e, 0x0005, 0xa284, 0xa286, 0xa284, 0xa284,
+	0xa284, 0xa286, 0xa298, 0xa31d, 0xa2e8, 0xa31d, 0xa2f9, 0xa31d,
+	0xa298, 0xa31d, 0xa315, 0xa31d, 0xa315, 0xa31d, 0xa31d, 0xa284,
+	0xa284, 0xa284, 0xa284, 0xa284, 0xa284, 0xa284, 0xa284, 0xa284,
+	0xa284, 0xa284, 0xa286, 0xa284, 0xa31d, 0xa284, 0xa284, 0xa31d,
+	0xa284, 0xa31a, 0xa31d, 0xa284, 0xa284, 0xa284, 0xa284, 0xa31d,
+	0xa31d, 0xa284, 0xa31d, 0xa31d, 0xa284, 0xa292, 0xa284, 0xa284,
+	0xa284, 0xa284, 0xa319, 0xa31d, 0xa284, 0xa284, 0xa31d, 0xa31d,
+	0xa284, 0xa284, 0xa284, 0xa284, 0x080c, 0x14fa, 0x080c, 0x6dc1,
+	0x2001, 0xb3b5, 0x2004, 0x6016, 0x6003, 0x0002, 0x080c, 0x6e9e,
+	0x0804, 0xa323, 0x2001, 0x0000, 0x080c, 0x4d63, 0x0804, 0xa31d,
+	0x00f6, 0x2079, 0xb152, 0x7804, 0x00fe, 0xd0ac, 0x1904, 0xa31d,
+	0x2001, 0x0000, 0x080c, 0x4d63, 0x6018, 0xa080, 0x0004, 0x2004,
+	0xa086, 0x00ff, 0x1140, 0x00f6, 0x2079, 0xb100, 0x7894, 0x8000,
+	0x7896, 0x00fe, 0x00e0, 0x00c6, 0x6018, 0x2060, 0x6000, 0xd0f4,
+	0x1140, 0x6010, 0xa005, 0x0128, 0x00ce, 0x080c, 0x3dcd, 0x0804,
+	0xa31d, 0x00ce, 0x2001, 0xb100, 0x2004, 0xa086, 0x0002, 0x1138,
+	0x00f6, 0x2079, 0xb100, 0x7894, 0x8000, 0x7896, 0x00fe, 0x2001,
+	0x0002, 0x080c, 0x4d75, 0x080c, 0x6dc1, 0x601f, 0x0001, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x080c, 0x6a3c, 0x080c, 0x6e9e, 0x00c6,
+	0x6118, 0x2160, 0x2009, 0x0001, 0x080c, 0x674e, 0x00ce, 0x04d8,
+	0x6618, 0x00d6, 0x2668, 0x6e04, 0x00de, 0xa6b4, 0xff00, 0x8637,
+	0xa686, 0x0006, 0x0550, 0xa686, 0x0004, 0x0538, 0x2001, 0x0004,
+	0x0410, 0x2001, 0xb100, 0x2004, 0xa086, 0x0003, 0x1110, 0x080c,
+	0x3dcd, 0x2001, 0x0006, 0x04a1, 0x6618, 0x00d6, 0x2668, 0x6e04,
+	0x00de, 0xa6b4, 0xff00, 0x8637, 0xa686, 0x0006, 0x0170, 0x2001,
+	0x0006, 0x0048, 0x2001, 0x0004, 0x0030, 0x2001, 0x0006, 0x0401,
+	0x0020, 0x0018, 0x0010, 0x080c, 0x4da2, 0x080c, 0x6dc1, 0x080c,
+	0x82eb, 0x080c, 0x6e9e, 0x0005, 0x2600, 0x0002, 0xa32f, 0xa32f,
+	0xa32f, 0xa32f, 0xa32f, 0xa331, 0xa32f, 0xa32f, 0xa32f, 0x080c,
+	0x14fa, 0x080c, 0x6dc1, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005,
+	0x0016, 0x00d6, 0x6118, 0x2168, 0x6900, 0xd184, 0x0188, 0x6104,
+	0xa18e, 0x000a, 0x1128, 0x699c, 0xd1a4, 0x1110, 0x2001, 0x0007,
+	0x080c, 0x4d75, 0x2001, 0x0000, 0x080c, 0x4d63, 0x080c, 0x2b99,
+	0x00de, 0x001e, 0x0005, 0x00d6, 0x6618, 0x2668, 0x6804, 0xa084,
+	0xff00, 0x8007, 0x00de, 0xa0b2, 0x000c, 0x1a0c, 0x14fa, 0xa1b6,
+	0x0015, 0x1110, 0x003b, 0x0028, 0xa1b6, 0x0016, 0x190c, 0x14fa,
+	0x006b, 0x0005, 0x8956, 0x8956, 0x8956, 0x8956, 0x8956, 0x8956,
+	0xa3bb, 0xa382, 0x8956, 0x8956, 0x8956, 0x8956, 0x8956, 0x8956,
+	0x8956, 0x8956, 0x8956, 0x8956, 0xa3bb, 0xa3c2, 0x8956, 0x8956,
+	0x8956, 0x8956, 0x00f6, 0x2079, 0xb152, 0x7804, 0xd0ac, 0x11e0,
+	0x6018, 0xa07d, 0x01c8, 0x7800, 0xd0f4, 0x1118, 0x7810, 0xa005,
+	0x1198, 0x2001, 0x0000, 0x080c, 0x4d63, 0x2001, 0x0002, 0x080c,
+	0x4d75, 0x601f, 0x0001, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c,
+	0x6a3c, 0x080c, 0x6e9e, 0x00a8, 0x2011, 0xb683, 0x2204, 0x8211,
+	0x220c, 0x080c, 0x26f6, 0x1168, 0x00c6, 0x080c, 0x4e21, 0x0120,
+	0x00ce, 0x080c, 0x82eb, 0x0028, 0x080c, 0x4a80, 0x00ce, 0x080c,
+	0x82eb, 0x00fe, 0x0005, 0x6604, 0xa6b6, 0x001e, 0x1110, 0x080c,
+	0x82eb, 0x0005, 0x080c, 0x8bea, 0x1138, 0x6003, 0x0001, 0x6007,
+	0x0001, 0x080c, 0x6a3c, 0x0010, 0x080c, 0x82eb, 0x0005, 0x6004,
+	0xa08a, 0x0080, 0x1a0c, 0x14fa, 0x080c, 0x6dc1, 0x080c, 0x9a2b,
+	0x080c, 0x6e9e, 0x0005, 0xa182, 0x0040, 0x0002, 0xa3f1, 0xa3f1,
+	0xa3f1, 0xa3f1, 0xa3f3, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1,
+	0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1, 0xa3f1,
+	0xa3f1, 0x080c, 0x14fa, 0x00d6, 0x00e6, 0x00f6, 0x0156, 0x0046,
+	0x0026, 0x6218, 0xa280, 0x002b, 0x2004, 0xa005, 0x0120, 0x2021,
+	0x0000, 0x080c, 0xaee2, 0x6106, 0x2071, 0xb680, 0x7444, 0xa4a4,
+	0xff00, 0x0904, 0xa457, 0xa486, 0x2000, 0x1130, 0x2009, 0x0001,
+	0x2011, 0x0200, 0x080c, 0x688d, 0x080c, 0x15dd, 0x090c, 0x14fa,
+	0x6003, 0x0007, 0x2d00, 0x6837, 0x010d, 0x6803, 0x0000, 0x683b,
+	0x0000, 0x6c5a, 0x2c00, 0x685e, 0x6008, 0x68b2, 0x6018, 0x2078,
+	0x78a0, 0x8007, 0x7130, 0x694a, 0x0016, 0xa084, 0xff00, 0x6846,
+	0x684f, 0x0000, 0x6853, 0x0000, 0x6857, 0x0036, 0x080c, 0x5271,
+	0x001e, 0xa486, 0x2000, 0x1130, 0x2019, 0x0017, 0x080c, 0xac2b,
+	0x0804, 0xa4b4, 0xa486, 0x0400, 0x1130, 0x2019, 0x0002, 0x080c,
+	0xabdd, 0x0804, 0xa4b4, 0xa486, 0x0200, 0x1110, 0x080c, 0xabc2,
+	0xa486, 0x1000, 0x1110, 0x080c, 0xac10, 0x0804, 0xa4b4, 0x2069,
+	0xb464, 0x6a00, 0xd284, 0x0904, 0xa50d, 0xa284, 0x0300, 0x1904,
+	0xa506, 0x6804, 0xa005, 0x0904, 0xa4ee, 0x2d78, 0x6003, 0x0007,
+	0x080c, 0x15c4, 0x0904, 0xa4bb, 0x7800, 0xd08c, 0x1118, 0x7804,
+	0x8001, 0x7806, 0x6013, 0x0000, 0x6803, 0x0000, 0x6837, 0x0116,
+	0x683b, 0x0000, 0x6008, 0x68b2, 0x2c00, 0x684a, 0x6018, 0x2078,
+	0x78a0, 0x8007, 0x7130, 0x6986, 0x6846, 0x7928, 0x698a, 0x792c,
+	0x698e, 0x7930, 0x6992, 0x7934, 0x6996, 0x6853, 0x003d, 0x7244,
+	0xa294, 0x0003, 0xa286, 0x0002, 0x1118, 0x684f, 0x0040, 0x0040,
+	0xa286, 0x0001, 0x1118, 0x684f, 0x0080, 0x0010, 0x684f, 0x0000,
+	0x20a9, 0x000a, 0x2001, 0xb690, 0xad90, 0x0015, 0x200c, 0x810f,
+	0x2112, 0x8000, 0x8210, 0x1f04, 0xa4a6, 0x200c, 0x6982, 0x8000,
+	0x200c, 0x697e, 0x080c, 0x5271, 0x002e, 0x004e, 0x015e, 0x00fe,
+	0x00ee, 0x00de, 0x0005, 0x6013, 0x0100, 0x6003, 0x0001, 0x6007,
+	0x0041, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0c70, 0x2069, 0xb692,
+	0x2d04, 0xa084, 0xff00, 0xa086, 0x1200, 0x11a8, 0x2069, 0xb680,
+	0x686c, 0xa084, 0x00ff, 0x0016, 0x6110, 0xa18c, 0x0700, 0xa10d,
+	0x6112, 0x001e, 0x6003, 0x0001, 0x6007, 0x0043, 0x080c, 0x69f6,
+	0x080c, 0x6e9e, 0x0888, 0x6013, 0x0200, 0x6003, 0x0001, 0x6007,
+	0x0041, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0830, 0x2001, 0xb10d,
+	0x2004, 0xd0ec, 0x0120, 0x2011, 0x8049, 0x080c, 0x3d5b, 0x6013,
+	0x0300, 0x0010, 0x6013, 0x0100, 0x6003, 0x0001, 0x6007, 0x0041,
+	0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0804, 0xa4b4, 0x6013, 0x0500,
+	0x0c98, 0x6013, 0x0600, 0x0804, 0xa4c6, 0x6013, 0x0200, 0x0804,
+	0xa4c6, 0xa186, 0x0013, 0x1170, 0x6004, 0xa08a, 0x0040, 0x0a0c,
+	0x14fa, 0xa08a, 0x0053, 0x1a0c, 0x14fa, 0xa082, 0x0040, 0x2008,
+	0x0804, 0xa59b, 0xa186, 0x0051, 0x0138, 0xa186, 0x0047, 0x11d8,
+	0x6004, 0xa086, 0x0041, 0x0518, 0x2001, 0x0109, 0x2004, 0xd084,
+	0x01f0, 0x0126, 0x2091, 0x2800, 0x0006, 0x0016, 0x0026, 0x080c,
+	0x68e7, 0x002e, 0x001e, 0x000e, 0x012e, 0x6000, 0xa086, 0x0002,
+	0x1170, 0x0804, 0xa5de, 0xa186, 0x0027, 0x0120, 0xa186, 0x0014,
+	0x190c, 0x14fa, 0x6004, 0xa082, 0x0040, 0x2008, 0x001a, 0x080c,
+	0x8331, 0x0005, 0xa565, 0xa567, 0xa567, 0xa58b, 0xa565, 0xa565,
+	0xa565, 0xa565, 0xa565, 0xa565, 0xa565, 0xa565, 0xa565, 0xa565,
+	0xa565, 0xa565, 0xa565, 0xa565, 0xa565, 0x080c, 0x14fa, 0x080c,
+	0x6dc1, 0x080c, 0x6e9e, 0x0036, 0x00d6, 0x6010, 0xa06d, 0x01c0,
+	0xad84, 0xf000, 0x01a8, 0x6003, 0x0002, 0x6018, 0x2004, 0xd0bc,
+	0x1178, 0x2019, 0x0004, 0x080c, 0xac5f, 0x6013, 0x0000, 0x6014,
+	0xa005, 0x1120, 0x2001, 0xb3b6, 0x2004, 0x6016, 0x6003, 0x0007,
+	0x00de, 0x003e, 0x0005, 0x00d6, 0x080c, 0x6dc1, 0x080c, 0x6e9e,
+	0x080c, 0x986a, 0x0120, 0x6010, 0x2068, 0x080c, 0x15f4, 0x080c,
+	0x9a2b, 0x00de, 0x0005, 0x0002, 0xa5af, 0xa5cc, 0xa5b8, 0xa5d8,
+	0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af,
+	0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0xa5af, 0x080c,
+	0x14fa, 0x6010, 0xa088, 0x0013, 0x2104, 0xa085, 0x0400, 0x200a,
+	0x080c, 0x6dc1, 0x6010, 0xa080, 0x0013, 0x2004, 0xd0b4, 0x0138,
+	0x6003, 0x0007, 0x2009, 0x0043, 0x080c, 0x831a, 0x0010, 0x6003,
+	0x0002, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x6dc1, 0x080c, 0xae9d,
+	0x1120, 0x080c, 0x6866, 0x080c, 0x82eb, 0x080c, 0x6e9e, 0x0005,
+	0x080c, 0x6dc1, 0x2009, 0x0041, 0x0804, 0xa727, 0xa182, 0x0040,
+	0x0002, 0xa5f4, 0xa5f6, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4,
+	0xa5f7, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4, 0xa5f4,
+	0xa5f4, 0xa5f4, 0xa602, 0xa5f4, 0x080c, 0x14fa, 0x0005, 0x6003,
+	0x0004, 0x6110, 0x20e1, 0x0005, 0x3d18, 0x3e20, 0x2c10, 0x080c,
+	0x1828, 0x0005, 0x00d6, 0x080c, 0x6866, 0x00de, 0x080c, 0xaf00,
+	0x080c, 0x82eb, 0x0005, 0xa182, 0x0040, 0x0002, 0xa621, 0xa621,
+	0xa621, 0xa621, 0xa621, 0xa621, 0xa621, 0xa623, 0xa621, 0xa626,
+	0xa65f, 0xa621, 0xa621, 0xa621, 0xa621, 0xa65f, 0xa621, 0xa621,
+	0xa621, 0x080c, 0x14fa, 0x080c, 0x8331, 0x0005, 0x2001, 0xb172,
+	0x2004, 0xd0e4, 0x0158, 0x2001, 0x0100, 0x2004, 0xa082, 0x0005,
+	0x0228, 0x2001, 0x011f, 0x2004, 0x6036, 0x0010, 0x6037, 0x0000,
+	0x080c, 0x6e53, 0x080c, 0x6f5b, 0x6010, 0x00d6, 0x2068, 0x684c,
+	0xd0fc, 0x0150, 0xa08c, 0x0003, 0xa18e, 0x0002, 0x0168, 0x2009,
+	0x0041, 0x00de, 0x0804, 0xa727, 0x6003, 0x0007, 0x6017, 0x0000,
+	0x080c, 0x6866, 0x00de, 0x0005, 0x080c, 0xae9d, 0x0110, 0x00de,
+	0x0005, 0x080c, 0x6866, 0x080c, 0x82eb, 0x00de, 0x0ca0, 0x0036,
+	0x080c, 0x6e53, 0x080c, 0x6f5b, 0x6010, 0x00d6, 0x2068, 0x6018,
+	0x2004, 0xd0bc, 0x0188, 0x684c, 0xa084, 0x0003, 0xa086, 0x0002,
+	0x0140, 0x687c, 0x632c, 0xa31a, 0x632e, 0x6880, 0x6328, 0xa31b,
+	0x632a, 0x6003, 0x0002, 0x0080, 0x2019, 0x0004, 0x080c, 0xac5f,
+	0x6014, 0xa005, 0x1128, 0x2001, 0xb3b6, 0x2004, 0x8003, 0x6016,
+	0x6013, 0x0000, 0x6003, 0x0007, 0x00de, 0x003e, 0x0005, 0xa186,
+	0x0013, 0x1150, 0x6004, 0xa086, 0x0042, 0x190c, 0x14fa, 0x080c,
+	0x6dc1, 0x080c, 0x6e9e, 0x0005, 0xa186, 0x0027, 0x0118, 0xa186,
+	0x0014, 0x1180, 0x6004, 0xa086, 0x0042, 0x190c, 0x14fa, 0x2001,
+	0x0007, 0x080c, 0x4da2, 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c,
+	0x6e9e, 0x0005, 0xa182, 0x0040, 0x0002, 0xa6c8, 0xa6c8, 0xa6c8,
+	0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8, 0xa6ca, 0xa6d6, 0xa6c8, 0xa6c8,
+	0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8, 0xa6c8,
+	0x080c, 0x14fa, 0x0036, 0x0046, 0x20e1, 0x0005, 0x3d18, 0x3e20,
+	0x2c10, 0x080c, 0x1828, 0x004e, 0x003e, 0x0005, 0x6010, 0x00d6,
+	0x2068, 0x6810, 0x6a14, 0x0006, 0x0046, 0x0056, 0x6c7c, 0xa422,
+	0x6d80, 0x2200, 0xa52b, 0x602c, 0xa420, 0x642e, 0x6028, 0xa529,
+	0x652a, 0x005e, 0x004e, 0x000e, 0xa20d, 0x1178, 0x684c, 0xd0fc,
+	0x0120, 0x2009, 0x0041, 0x00de, 0x0490, 0x6003, 0x0007, 0x6017,
+	0x0000, 0x080c, 0x6866, 0x00de, 0x0005, 0x0006, 0x00f6, 0x2c78,
+	0x080c, 0x5177, 0x00fe, 0x000e, 0x0120, 0x6003, 0x0002, 0x00de,
+	0x0005, 0x2009, 0xb10d, 0x210c, 0xd19c, 0x0118, 0x6003, 0x0007,
+	0x0010, 0x6003, 0x0006, 0x0021, 0x080c, 0x6868, 0x00de, 0x0005,
+	0xd2fc, 0x0140, 0x8002, 0x8000, 0x8212, 0xa291, 0x0000, 0x2009,
+	0x0009, 0x0010, 0x2009, 0x0015, 0x6a6a, 0x6866, 0x0005, 0xa182,
+	0x0040, 0x0208, 0x0062, 0xa186, 0x0013, 0x0120, 0xa186, 0x0014,
+	0x190c, 0x14fa, 0x6020, 0xd0dc, 0x090c, 0x14fa, 0x0005, 0xa74a,
+	0xa751, 0xa75d, 0xa769, 0xa74a, 0xa74a, 0xa74a, 0xa778, 0xa74a,
+	0xa74c, 0xa74c, 0xa74a, 0xa74a, 0xa74a, 0xa74a, 0xa74c, 0xa74a,
+	0xa74c, 0xa74a, 0x080c, 0x14fa, 0x6020, 0xd0dc, 0x090c, 0x14fa,
+	0x0005, 0x6003, 0x0001, 0x6106, 0x080c, 0x69f6, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x6e9e, 0x012e, 0x0005, 0x6003, 0x0001, 0x6106,
+	0x080c, 0x69f6, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e, 0x012e,
+	0x0005, 0x6003, 0x0003, 0x6106, 0x2c10, 0x080c, 0x1ec4, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6a59, 0x080c, 0x6f5b, 0x012e, 0x0005,
+	0xa016, 0x080c, 0x1828, 0x0005, 0x0126, 0x2091, 0x8000, 0x0036,
+	0x00d6, 0xa182, 0x0040, 0x0023, 0x00de, 0x003e, 0x012e, 0x0005,
+	0xa798, 0xa79a, 0xa7ac, 0xa7c7, 0xa798, 0xa798, 0xa798, 0xa7dc,
+	0xa798, 0xa798, 0xa798, 0xa798, 0xa798, 0xa798, 0xa798, 0xa798,
+	0x080c, 0x14fa, 0x6010, 0x2068, 0x684c, 0xd0fc, 0x01f8, 0xa09c,
+	0x0003, 0xa39e, 0x0003, 0x01d0, 0x6003, 0x0001, 0x6106, 0x080c,
+	0x69f6, 0x080c, 0x6e9e, 0x0498, 0x6010, 0x2068, 0x684c, 0xd0fc,
+	0x0168, 0xa09c, 0x0003, 0xa39e, 0x0003, 0x0140, 0x6003, 0x0001,
+	0x6106, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x0408, 0x6013, 0x0000,
+	0x6017, 0x0000, 0x2019, 0x0004, 0x080c, 0xac5f, 0x00c0, 0x6010,
+	0x2068, 0x684c, 0xd0fc, 0x0d90, 0xa09c, 0x0003, 0xa39e, 0x0003,
+	0x0d68, 0x6003, 0x0003, 0x6106, 0x2c10, 0x080c, 0x1ec4, 0x080c,
+	0x6a59, 0x080c, 0x6f5b, 0x0018, 0xa016, 0x080c, 0x1828, 0x0005,
+	0x080c, 0x6dc1, 0x6110, 0x81ff, 0x0158, 0x00d6, 0x2168, 0x080c,
+	0xaf46, 0x0036, 0x2019, 0x0029, 0x080c, 0xac5f, 0x003e, 0x00de,
+	0x080c, 0x9a2b, 0x080c, 0x6e9e, 0x0005, 0x080c, 0x6e53, 0x6110,
+	0x81ff, 0x0158, 0x00d6, 0x2168, 0x080c, 0xaf46, 0x0036, 0x2019,
+	0x0029, 0x080c, 0xac5f, 0x003e, 0x00de, 0x080c, 0x9a2b, 0x080c,
+	0x6f5b, 0x0005, 0xa182, 0x0085, 0x0002, 0xa816, 0xa814, 0xa814,
+	0xa822, 0xa814, 0xa814, 0xa814, 0x080c, 0x14fa, 0x6003, 0x000b,
+	0x6106, 0x080c, 0x69f6, 0x0126, 0x2091, 0x8000, 0x080c, 0x6e9e,
+	0x012e, 0x0005, 0x0026, 0x00e6, 0x080c, 0xae96, 0x0118, 0x080c,
+	0x82eb, 0x00c8, 0x2071, 0xb680, 0x7224, 0x6212, 0x7220, 0x080c,
+	0xab0d, 0x0118, 0x6007, 0x0086, 0x0040, 0x6007, 0x0087, 0x7224,
+	0xa296, 0xffff, 0x1110, 0x6007, 0x0086, 0x6003, 0x0001, 0x080c,
+	0x69f6, 0x080c, 0x6e9e, 0x00ee, 0x002e, 0x0005, 0xa186, 0x0013,
+	0x1160, 0x6004, 0xa08a, 0x0085, 0x0a0c, 0x14fa, 0xa08a, 0x008c,
+	0x1a0c, 0x14fa, 0xa082, 0x0085, 0x00a2, 0xa186, 0x0027, 0x0130,
+	0xa186, 0x0014, 0x0118, 0x080c, 0x8331, 0x0050, 0x2001, 0x0007,
+	0x080c, 0x4da2, 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e,
+	0x0005, 0xa870, 0xa872, 0xa872, 0xa870, 0xa870, 0xa870, 0xa870,
+	0x080c, 0x14fa, 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e,
+	0x0005, 0xa182, 0x0085, 0x0a0c, 0x14fa, 0xa182, 0x008c, 0x1a0c,
+	0x14fa, 0xa182, 0x0085, 0x0002, 0xa88b, 0xa88b, 0xa88b, 0xa88d,
+	0xa88b, 0xa88b, 0xa88b, 0x080c, 0x14fa, 0x0005, 0xa186, 0x0013,
+	0x0148, 0xa186, 0x0014, 0x0130, 0xa186, 0x0027, 0x0118, 0x080c,
+	0x8331, 0x0030, 0x080c, 0x6dc1, 0x080c, 0x9a2b, 0x080c, 0x6e9e,
+	0x0005, 0x0036, 0x080c, 0xaf00, 0x603f, 0x0000, 0x2019, 0x000b,
+	0x0031, 0x601f, 0x0006, 0x6003, 0x0007, 0x003e, 0x0005, 0x0126,
+	0x0036, 0x2091, 0x8000, 0x0086, 0x2c40, 0x0096, 0x2049, 0x0000,
+	0x080c, 0x7e0d, 0x009e, 0x008e, 0x1578, 0x0076, 0x2c38, 0x080c,
+	0x7ea7, 0x007e, 0x1548, 0x6000, 0xa086, 0x0000, 0x0528, 0x601c,
+	0xa086, 0x0007, 0x0508, 0x00d6, 0x6000, 0xa086, 0x0004, 0x1150,
+	0x080c, 0xaf00, 0x601f, 0x0007, 0x2001, 0xb3b5, 0x2004, 0x6016,
+	0x080c, 0x190f, 0x6010, 0x2068, 0x080c, 0x986a, 0x0110, 0x080c,
+	0xac5f, 0x00de, 0x6013, 0x0000, 0x080c, 0xaf00, 0x601f, 0x0007,
+	0x2001, 0xb3b5, 0x2004, 0x6016, 0x003e, 0x012e, 0x0005, 0x00f6,
+	0x00c6, 0x0036, 0x0156, 0x2079, 0xb680, 0x7938, 0x783c, 0x080c,
+	0x26f6, 0x15b0, 0x0016, 0x00c6, 0x080c, 0x4e21, 0x1578, 0x001e,
+	0x002e, 0x0026, 0x0016, 0x2019, 0x0029, 0x080c, 0x7f67, 0x080c,
+	0x6b35, 0x0076, 0x2039, 0x0000, 0x080c, 0x6a6b, 0x007e, 0x001e,
+	0x0076, 0x2039, 0x0000, 0x080c, 0xaa51, 0x007e, 0x080c, 0x501c,
+	0x0026, 0x6204, 0xa294, 0xff00, 0x8217, 0xa286, 0x0006, 0x0118,
+	0xa286, 0x0004, 0x1118, 0x62a0, 0x080c, 0x2c2c, 0x002e, 0x001e,
+	0x080c, 0x4a80, 0x6612, 0x6516, 0xa006, 0x0010, 0x00ce, 0x001e,
+	0x015e, 0x003e, 0x00ce, 0x00fe, 0x0005, 0x00c6, 0x00d6, 0x00e6,
+	0x0016, 0x2009, 0xb120, 0x2104, 0xa086, 0x0074, 0x1904, 0xa98a,
+	0x2069, 0xb68e, 0x690c, 0xa182, 0x0100, 0x06c0, 0x6908, 0xa184,
+	0x8000, 0x05e8, 0x2001, 0xb39e, 0x2004, 0xa005, 0x1160, 0x6018,
+	0x2070, 0x7010, 0xa084, 0x00ff, 0x0118, 0x7000, 0xd0f4, 0x0118,
+	0xa184, 0x0800, 0x0560, 0x6910, 0xa18a, 0x0001, 0x0610, 0x6914,
+	0x2069, 0xb6ae, 0x6904, 0x81ff, 0x1198, 0x690c, 0xa182, 0x0100,
+	0x02a8, 0x6908, 0x81ff, 0x1178, 0x6910, 0xa18a, 0x0001, 0x0288,
+	0x6918, 0xa18a, 0x0001, 0x0298, 0x00d0, 0x6013, 0x0100, 0x00a0,
+	0x6013, 0x0300, 0x0088, 0x6013, 0x0500, 0x0070, 0x6013, 0x0700,
+	0x0058, 0x6013, 0x0900, 0x0040, 0x6013, 0x0b00, 0x0028, 0x6013,
+	0x0f00, 0x0010, 0x6013, 0x2d00, 0xa085, 0x0001, 0x0008, 0xa006,
+	0x001e, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x00c6, 0x00d6, 0x0026,
+	0x0036, 0x0156, 0x6218, 0x2268, 0x6b04, 0xa394, 0x00ff, 0xa286,
+	0x0006, 0x0190, 0xa286, 0x0004, 0x0178, 0xa394, 0xff00, 0x8217,
+	0xa286, 0x0006, 0x0148, 0xa286, 0x0004, 0x0130, 0x00c6, 0x2d60,
+	0x080c, 0x4e30, 0x00ce, 0x04c0, 0x2011, 0xb696, 0xad98, 0x000a,
+	0x20a9, 0x0004, 0x080c, 0x8d2b, 0x1580, 0x2011, 0xb69a, 0xad98,
+	0x0006, 0x20a9, 0x0004, 0x080c, 0x8d2b, 0x1538, 0x0046, 0x0016,
+	0x6aa0, 0xa294, 0x00ff, 0x8227, 0xa006, 0x2009, 0xb153, 0x210c,
+	0xd1a4, 0x0138, 0x2009, 0x0029, 0x080c, 0xacae, 0x6800, 0xc0e5,
+	0x6802, 0x2019, 0x0029, 0x080c, 0x6b35, 0x0076, 0x2039, 0x0000,
+	0x080c, 0x6a6b, 0x2c08, 0x080c, 0xaa51, 0x007e, 0x2001, 0x0007,
+	0x080c, 0x4da2, 0x001e, 0x004e, 0xa006, 0x015e, 0x003e, 0x002e,
+	0x00de, 0x00ce, 0x0005, 0x00d6, 0x2069, 0xb68e, 0x6800, 0xa086,
+	0x0800, 0x0118, 0x6013, 0x0000, 0x0008, 0xa006, 0x00de, 0x0005,
+	0x00c6, 0x00f6, 0x0016, 0x0026, 0x0036, 0x0156, 0x2079, 0xb68c,
+	0x7930, 0x7834, 0x080c, 0x26f6, 0x11a0, 0x080c, 0x4e21, 0x1188,
+	0x2011, 0xb690, 0xac98, 0x000a, 0x20a9, 0x0004, 0x080c, 0x8d2b,
+	0x1140, 0x2011, 0xb694, 0xac98, 0x0006, 0x20a9, 0x0004, 0x080c,
+	0x8d2b, 0x015e, 0x003e, 0x002e, 0x001e, 0x00fe, 0x00ce, 0x0005,
+	0x00c6, 0x0006, 0x0016, 0x0026, 0x0036, 0x0156, 0x2011, 0xb683,
+	0x2204, 0x8211, 0x220c, 0x080c, 0x26f6, 0x11a0, 0x080c, 0x4e21,
+	0x1188, 0x2011, 0xb696, 0xac98, 0x000a, 0x20a9, 0x0004, 0x080c,
+	0x8d2b, 0x1140, 0x2011, 0xb69a, 0xac98, 0x0006, 0x20a9, 0x0004,
+	0x080c, 0x8d2b, 0x015e, 0x003e, 0x002e, 0x001e, 0x000e, 0x00ce,
+	0x0005, 0x00e6, 0x00c6, 0x0086, 0x0076, 0x0066, 0x0056, 0x0046,
+	0x0026, 0x0126, 0x2091, 0x8000, 0x2740, 0x2029, 0xb3e2, 0x252c,
+	0x2021, 0xb3e8, 0x2424, 0x2061, 0xb800, 0x2071, 0xb100, 0x7644,
+	0x7064, 0x81ff, 0x0128, 0x8001, 0xa602, 0x1a04, 0xaacd, 0x0018,
+	0xa606, 0x0904, 0xaacd, 0x2100, 0xac06, 0x0904, 0xaac4, 0x080c,
+	0xacd6, 0x0904, 0xaac4, 0x671c, 0xa786, 0x0001, 0x0904, 0xaae4,
+	0xa786, 0x0004, 0x0904, 0xaae4, 0xa786, 0x0007, 0x05e8, 0x2500,
+	0xac06, 0x05d0, 0x2400, 0xac06, 0x05b8, 0x080c, 0xace6, 0x15a0,
+	0x88ff, 0x0118, 0x6050, 0xa906, 0x1578, 0x00d6, 0x6000, 0xa086,
+	0x0004, 0x1120, 0x0016, 0x080c, 0x190f, 0x001e, 0xa786, 0x0008,
+	0x1148, 0x080c, 0x9a66, 0x1130, 0x080c, 0x8890, 0x00de, 0x080c,
+	0x9a2b, 0x00d0, 0x6010, 0x2068, 0x080c, 0x986a, 0x0190, 0xa786,
+	0x0003, 0x1528, 0x6837, 0x0103, 0x6b4a, 0x6847, 0x0000, 0x080c,
+	0xaf46, 0x0016, 0x080c, 0x9ada, 0x080c, 0x5271, 0x001e, 0x080c,
+	0x9a1f, 0x00de, 0x080c, 0x9a2b, 0xace0, 0x0018, 0x2001, 0xb116,
+	0x2004, 0xac02, 0x1210, 0x0804, 0xaa65, 0x012e, 0x002e, 0x004e,
+	0x005e, 0x006e, 0x007e, 0x008e, 0x00ce, 0x00ee, 0x0005, 0xa786,
+	0x0006, 0x19c0, 0xa386, 0x0005, 0x0128, 0x080c, 0xaf46, 0x080c,
+	0xac5f, 0x08f8, 0x00de, 0x0c00, 0x080c, 0xace6, 0x19e8, 0x81ff,
+	0x09d8, 0xa180, 0x0001, 0x2004, 0xa086, 0x0018, 0x0130, 0xa180,
+	0x0001, 0x2004, 0xa086, 0x002d, 0x1978, 0x6000, 0xa086, 0x0002,
+	0x1958, 0x080c, 0x9a55, 0x0130, 0x080c, 0x9a66, 0x1928, 0x080c,
+	0x8890, 0x0038, 0x080c, 0x2b99, 0x080c, 0x9a66, 0x1110, 0x080c,
+	0x8890, 0x080c, 0x9a2b, 0x0804, 0xaac4, 0x00c6, 0x00e6, 0x0016,
+	0x2c08, 0x2170, 0xa006, 0x080c, 0xac80, 0x001e, 0x0120, 0x601c,
+	0xa084, 0x000f, 0x001b, 0x00ee, 0x00ce, 0x0005, 0xab26, 0xab26,
+	0xab26, 0xab26, 0xab26, 0xab26, 0xab28, 0xab26, 0xa006, 0x0005,
+	0x0046, 0x0016, 0x7018, 0xa080, 0x0028, 0x2024, 0xa4a4, 0x00ff,
+	0x8427, 0x2c00, 0x2009, 0x0020, 0x080c, 0xacae, 0x001e, 0x004e,
+	0x0036, 0x2019, 0x0002, 0x080c, 0xa8af, 0x003e, 0xa085, 0x0001,
+	0x0005, 0x2001, 0x0001, 0x080c, 0x4d63, 0x0156, 0x0016, 0x0026,
+	0x0036, 0x20a9, 0x0004, 0x2019, 0xb105, 0x2011, 0xb696, 0x080c,
+	0x8d2b, 0x003e, 0x002e, 0x001e, 0x015e, 0xa005, 0x0005, 0x00f6,
+	0x00e6, 0x00c6, 0x0086, 0x0076, 0x0066, 0x0026, 0x0126, 0x2091,
+	0x8000, 0x2740, 0x2061, 0xb800, 0x2079, 0x0001, 0x8fff, 0x0904,
+	0xabb5, 0x2071, 0xb100, 0x7644, 0x7064, 0x8001, 0xa602, 0x1a04,
+	0xabb5, 0x88ff, 0x0128, 0x2800, 0xac06, 0x15b0, 0x2079, 0x0000,
+	0x080c, 0xacd6, 0x0588, 0x2400, 0xac06, 0x0570, 0x671c, 0xa786,
+	0x0006, 0x1550, 0xa786, 0x0007, 0x0538, 0x88ff, 0x1140, 0x6018,
+	0xa206, 0x1510, 0x85ff, 0x0118, 0x6050, 0xa106, 0x11e8, 0x00d6,
+	0x6000, 0xa086, 0x0004, 0x1150, 0x080c, 0xaf00, 0x601f, 0x0007,
+	0x2001, 0xb3b5, 0x2004, 0x6016, 0x080c, 0x190f, 0x6010, 0x2068,
+	0x080c, 0x986a, 0x0120, 0x0046, 0x080c, 0xac5f, 0x004e, 0x00de,
+	0x080c, 0x9a2b, 0x88ff, 0x1198, 0xace0, 0x0018, 0x2001, 0xb116,
+	0x2004, 0xac02, 0x1210, 0x0804, 0xab66, 0xa006, 0x012e, 0x002e,
+	0x006e, 0x007e, 0x008e, 0x00ce, 0x00ee, 0x00fe, 0x0005, 0xa8c5,
+	0x0001, 0x0ca0, 0x0076, 0x0056, 0x0086, 0x2041, 0x0000, 0x2029,
+	0x0001, 0x2c20, 0x2019, 0x0002, 0x6218, 0x0096, 0x2049, 0x0000,
+	0x080c, 0x7e0d, 0x009e, 0x008e, 0x2039, 0x0000, 0x080c, 0x7ea7,
+	0x080c, 0xab57, 0x005e, 0x007e, 0x0005, 0x0026, 0x0046, 0x0056,
+	0x0076, 0x00c6, 0x0156, 0x2c20, 0x2128, 0x20a9, 0x007f, 0x2009,
+	0x0000, 0x0016, 0x0036, 0x080c, 0x4e21, 0x11b0, 0x2c10, 0x0056,
+	0x0086, 0x2041, 0x0000, 0x2508, 0x2029, 0x0001, 0x0096, 0x2049,
+	0x0000, 0x080c, 0x7e0d, 0x009e, 0x008e, 0x2039, 0x0000, 0x080c,
+	0x7ea7, 0x080c, 0xab57, 0x005e, 0x003e, 0x001e, 0x8108, 0x1f04,
+	0xabe9, 0x015e, 0x00ce, 0x007e, 0x005e, 0x004e, 0x002e, 0x0005,
+	0x0076, 0x0056, 0x6218, 0x0086, 0x2041, 0x0000, 0x2029, 0x0001,
+	0x2019, 0x0048, 0x0096, 0x2049, 0x0000, 0x080c, 0x7e0d, 0x009e,
+	0x008e, 0x2039, 0x0000, 0x080c, 0x7ea7, 0x2c20, 0x080c, 0xab57,
+	0x005e, 0x007e, 0x0005, 0x0026, 0x0046, 0x0056, 0x0076, 0x00c6,
+	0x0156, 0x2c20, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x0036,
+	0x080c, 0x4e21, 0x11c0, 0x2c10, 0x0086, 0x2041, 0x0000, 0x2828,
+	0x0046, 0x2021, 0x0001, 0x080c, 0xaee2, 0x004e, 0x0096, 0x2049,
+	0x0000, 0x080c, 0x7e0d, 0x009e, 0x008e, 0x2039, 0x0000, 0x080c,
+	0x7ea7, 0x080c, 0xab57, 0x003e, 0x001e, 0x8108, 0x1f04, 0xac36,
+	0x015e, 0x00ce, 0x007e, 0x005e, 0x004e, 0x002e, 0x0005, 0x0016,
+	0x00f6, 0x3800, 0xd08c, 0x0130, 0xad82, 0x1000, 0x02b0, 0xad82,
+	0xb100, 0x0230, 0xad82, 0xe800, 0x0280, 0xad82, 0xffff, 0x1268,
+	0x6800, 0xa07d, 0x0138, 0x6803, 0x0000, 0x6b52, 0x080c, 0x5271,
+	0x2f68, 0x0cb0, 0x6b52, 0x080c, 0x5271, 0x00fe, 0x001e, 0x0005,
+	0x00e6, 0x0046, 0x0036, 0x2061, 0xb800, 0xa005, 0x1138, 0x2071,
+	0xb100, 0x7444, 0x7064, 0x8001, 0xa402, 0x12d8, 0x2100, 0xac06,
+	0x0168, 0x6000, 0xa086, 0x0000, 0x0148, 0x6008, 0xa206, 0x1130,
+	0x6018, 0xa1a0, 0x0006, 0x2424, 0xa406, 0x0140, 0xace0, 0x0018,
+	0x2001, 0xb116, 0x2004, 0xac02, 0x1220, 0x0c40, 0xa085, 0x0001,
+	0x0008, 0xa006, 0x003e, 0x004e, 0x00ee, 0x0005, 0x00d6, 0x0006,
+	0x080c, 0x15dd, 0x000e, 0x090c, 0x14fa, 0x6837, 0x010d, 0x685e,
+	0x0026, 0x2010, 0x080c, 0x985a, 0x2001, 0x0000, 0x0120, 0x2200,
+	0xa080, 0x0014, 0x2004, 0x002e, 0x684a, 0x6956, 0x6c46, 0x684f,
+	0x0000, 0x2001, 0xb3bd, 0x2004, 0x6852, 0xa006, 0x68b2, 0x6802,
+	0x683a, 0x685a, 0x080c, 0x5271, 0x00de, 0x0005, 0x6700, 0xa786,
+	0x0000, 0x0158, 0xa786, 0x0001, 0x0140, 0xa786, 0x000a, 0x0128,
+	0xa786, 0x0009, 0x0110, 0xa085, 0x0001, 0x0005, 0x00e6, 0x6018,
+	0x2070, 0x70a0, 0xa206, 0x00ee, 0x0005, 0x0016, 0x6004, 0xa08e,
+	0x001e, 0x11a0, 0x8007, 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032,
+	0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0005, 0x2001, 0xb3b6,
+	0x2004, 0x6016, 0x080c, 0x69f6, 0x080c, 0x6e9e, 0x001e, 0x0005,
+	0xe000, 0xe000, 0x0005, 0x6020, 0xd0e4, 0x0158, 0xd0cc, 0x0118,
+	0x080c, 0x9b43, 0x0030, 0x080c, 0xaf00, 0x080c, 0x6866, 0x080c,
+	0x82eb, 0x0005, 0xa280, 0x0007, 0x2004, 0xa084, 0x000f, 0x0002,
+	0xad29, 0xad29, 0xad29, 0xad2e, 0xad29, 0xad2b, 0xad2b, 0xad29,
+	0xad2b, 0xa006, 0x0005, 0x00c6, 0x2260, 0x00ce, 0xa085, 0x0001,
+	0x0005, 0xa280, 0x0007, 0x2004, 0xa084, 0x000f, 0x0002, 0xad40,
+	0xad40, 0xad40, 0xad40, 0xad40, 0xad40, 0xad4b, 0xad40, 0xad40,
+	0x6007, 0x003b, 0x602b, 0x0009, 0x6013, 0x2a00, 0x6003, 0x0001,
+	0x080c, 0x69f6, 0x0005, 0x00c6, 0x2260, 0x080c, 0xaf00, 0x603f,
+	0x0000, 0x6020, 0xc0f4, 0xc0cc, 0x6022, 0x6037, 0x0000, 0x00ce,
+	0x00d6, 0x2268, 0xa186, 0x0007, 0x1904, 0xada6, 0x6810, 0xa005,
+	0x0138, 0xa080, 0x0013, 0x2004, 0xd0fc, 0x1110, 0x00de, 0x08c0,
+	0x6007, 0x003a, 0x6003, 0x0001, 0x080c, 0x69f6, 0x080c, 0x6e9e,
+	0x00c6, 0x2d60, 0x6100, 0xa186, 0x0002, 0x1904, 0xae2f, 0x6010,
+	0xa005, 0x1138, 0x6000, 0xa086, 0x0007, 0x190c, 0x14fa, 0x0804,
+	0xae2f, 0xa08c, 0xf000, 0x1130, 0x0028, 0x2068, 0x6800, 0xa005,
+	0x1de0, 0x2d00, 0xa080, 0x0013, 0x2004, 0xa084, 0x0003, 0xa086,
+	0x0002, 0x1180, 0x6010, 0x2068, 0x684c, 0xc0dc, 0xc0f4, 0x684e,
+	0x6850, 0xc0f4, 0xc0fc, 0x6852, 0x2009, 0x0043, 0x080c, 0xa727,
+	0x0804, 0xae2f, 0x2009, 0x0041, 0x0804, 0xae29, 0xa186, 0x0005,
+	0x15f0, 0x6810, 0xa080, 0x0013, 0x2004, 0xd0bc, 0x1118, 0x00de,
+	0x0804, 0xad40, 0xd0b4, 0x0128, 0xd0fc, 0x090c, 0x14fa, 0x0804,
+	0xad5e, 0x6007, 0x003a, 0x6003, 0x0001, 0x080c, 0x69f6, 0x080c,
+	0x6e9e, 0x00c6, 0x2d60, 0x6100, 0xa186, 0x0002, 0x0120, 0xa186,
+	0x0004, 0x1904, 0xae2f, 0x2071, 0xb419, 0x7000, 0xa086, 0x0003,
+	0x1128, 0x7004, 0xac06, 0x1110, 0x7003, 0x0000, 0x6810, 0xa080,
+	0x0013, 0x200c, 0xc1f4, 0xc1dc, 0x2102, 0x8000, 0x200c, 0xc1f4,
+	0xc1fc, 0xc1bc, 0x2102, 0x2009, 0x0042, 0x0804, 0xae29, 0x0036,
+	0x00d6, 0x00d6, 0x080c, 0x15dd, 0x003e, 0x090c, 0x14fa, 0x6837,
+	0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b, 0x0000, 0x6b5e,
+	0x6857, 0x0045, 0x2c00, 0x6862, 0x6034, 0x6872, 0x2360, 0x6020,
+	0xc0dd, 0x6022, 0x6018, 0xa080, 0x0028, 0x2004, 0xa084, 0x00ff,
+	0x8007, 0x6350, 0x6b4a, 0x6846, 0x684f, 0x0000, 0x6853, 0x0000,
+	0x6d6a, 0x6e66, 0x686f, 0x0001, 0x080c, 0x5271, 0x2019, 0x0045,
+	0x6008, 0x2068, 0x080c, 0xa8af, 0x2d00, 0x600a, 0x601f, 0x0006,
+	0x6003, 0x0007, 0x6017, 0x0000, 0x603f, 0x0000, 0x00de, 0x003e,
+	0x0038, 0x603f, 0x0000, 0x6003, 0x0007, 0x080c, 0xa727, 0x00ce,
+	0x00de, 0x0005, 0xa186, 0x0013, 0x1128, 0x6004, 0xa082, 0x0085,
+	0x2008, 0x00c2, 0xa186, 0x0027, 0x1178, 0x080c, 0x6dc1, 0x0036,
+	0x00d6, 0x6010, 0x2068, 0x2019, 0x0004, 0x080c, 0xac5f, 0x00de,
+	0x003e, 0x080c, 0x6e9e, 0x0005, 0xa186, 0x0014, 0x0d70, 0x080c,
+	0x8331, 0x0005, 0xae5b, 0xae59, 0xae59, 0xae59, 0xae59, 0xae59,
+	0xae5b, 0x080c, 0x14fa, 0x080c, 0x6dc1, 0x6003, 0x000c, 0x080c,
+	0x6e9e, 0x0005, 0xa182, 0x008c, 0x1220, 0xa182, 0x0085, 0x0208,
+	0x001a, 0x080c, 0x8331, 0x0005, 0xae73, 0xae73, 0xae73, 0xae73,
+	0xae75, 0xae93, 0xae73, 0x080c, 0x14fa, 0x00d6, 0x2c68, 0x080c,
+	0x8295, 0x01a0, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, 0xb68e,
+	0x210c, 0x6136, 0x2009, 0xb68f, 0x210c, 0x613a, 0x600b, 0xffff,
+	0x6918, 0x611a, 0x601f, 0x0004, 0x080c, 0x69f6, 0x2d60, 0x080c,
+	0x82eb, 0x00de, 0x0005, 0x080c, 0x82eb, 0x0005, 0x00e6, 0x6018,
+	0x2070, 0x7000, 0xd0ec, 0x00ee, 0x0005, 0x6010, 0xa08c, 0xf000,
+	0x0904, 0xaee1, 0xa080, 0x0013, 0x200c, 0xd1ec, 0x05d0, 0x2001,
+	0xb172, 0x2004, 0xd0ec, 0x05a8, 0x6003, 0x0002, 0x6020, 0xc0e5,
+	0x6022, 0xd1ac, 0x0180, 0x00f6, 0x2c78, 0x080c, 0x5173, 0x00fe,
+	0x0150, 0x2001, 0xb3b7, 0x2004, 0x603e, 0x2009, 0xb172, 0x210c,
+	0xd1f4, 0x11e8, 0x0080, 0x2009, 0xb172, 0x210c, 0xd1f4, 0x0128,
+	0x6020, 0xc0e4, 0x6022, 0xa006, 0x00a0, 0x2001, 0xb3b7, 0x200c,
+	0x8103, 0xa100, 0x603e, 0x6018, 0xa088, 0x002b, 0x2104, 0xa005,
+	0x0118, 0xa088, 0x0003, 0x0cd0, 0x2c0a, 0x600f, 0x0000, 0xa085,
+	0x0001, 0x0005, 0x0016, 0x00c6, 0x00e6, 0x6150, 0xa2f0, 0x002b,
+	0x2e04, 0x2060, 0x8cff, 0x0180, 0x84ff, 0x1118, 0x6050, 0xa106,
+	0x1138, 0x600c, 0x2072, 0x080c, 0x6866, 0x080c, 0x82eb, 0x0010,
+	0xacf0, 0x0003, 0x2e64, 0x0c70, 0x00ee, 0x00ce, 0x001e, 0x0005,
+	0x00d6, 0x6018, 0xa0e8, 0x002b, 0x2d04, 0xa005, 0x0140, 0xac06,
+	0x0120, 0x2d04, 0xa0e8, 0x0003, 0x0cb8, 0x600c, 0x206a, 0x00de,
+	0x0005, 0x0026, 0x0036, 0x0156, 0x2011, 0xb127, 0x2204, 0xa084,
+	0x00ff, 0x2019, 0xb68e, 0x2334, 0xa636, 0x11d8, 0x8318, 0x2334,
+	0x2204, 0xa084, 0xff00, 0xa636, 0x11a0, 0x2011, 0xb690, 0x6018,
+	0xa098, 0x000a, 0x20a9, 0x0004, 0x080c, 0x8d2b, 0x1150, 0x2011,
+	0xb694, 0x6018, 0xa098, 0x0006, 0x20a9, 0x0004, 0x080c, 0x8d2b,
+	0x1100, 0x015e, 0x003e, 0x002e, 0x0005, 0x00e6, 0x2071, 0xb100,
+	0x080c, 0x4a3b, 0x080c, 0x2991, 0x00ee, 0x0005, 0x00e6, 0x6018,
+	0x2070, 0x7000, 0xd0fc, 0x0108, 0x0011, 0x00ee, 0x0005, 0x6850,
+	0xc0e5, 0x6852, 0x0005, 0x00e6, 0x00c6, 0x0076, 0x0066, 0x0056,
+	0x0046, 0x0026, 0x0016, 0x0126, 0x2091, 0x8000, 0x2029, 0xb3e2,
+	0x252c, 0x2021, 0xb3e8, 0x2424, 0x2061, 0xb800, 0x2071, 0xb100,
+	0x7644, 0x7064, 0xa606, 0x0578, 0x671c, 0xa786, 0x0001, 0x0118,
+	0xa786, 0x0008, 0x1500, 0x2500, 0xac06, 0x01e8, 0x2400, 0xac06,
+	0x01d0, 0x080c, 0xacd6, 0x01b8, 0x080c, 0xace6, 0x11a0, 0x6000,
+	0xa086, 0x0004, 0x1120, 0x0016, 0x080c, 0x190f, 0x001e, 0x080c,
+	0x9a55, 0x1110, 0x080c, 0x2b99, 0x080c, 0x9a66, 0x1110, 0x080c,
+	0x8890, 0x080c, 0x9a2b, 0xace0, 0x0018, 0x2001, 0xb116, 0x2004,
+	0xac02, 0x1208, 0x0858, 0x012e, 0x001e, 0x002e, 0x004e, 0x005e,
+	0x006e, 0x007e, 0x00ce, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6,
+	0x2091, 0x8000, 0x2071, 0xb140, 0xd5a4, 0x0118, 0x7034, 0x8000,
+	0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0118,
+	0x2071, 0xb14a, 0x0451, 0x00ee, 0x000e, 0x012e, 0x0005, 0x0126,
+	0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, 0xb140, 0xd5a4, 0x0118,
+	0x7034, 0x8000, 0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032,
+	0xd5ac, 0x0118, 0x2071, 0xb14a, 0x0081, 0x00ee, 0x000e, 0x012e,
+	0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, 0xb142,
+	0x0021, 0x00ee, 0x000e, 0x012e, 0x0005, 0x2e04, 0x8000, 0x2072,
+	0x1220, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x0005, 0x00e6, 0x2071,
+	0xb140, 0x0c99, 0x00ee, 0x0005, 0x00e6, 0x2071, 0xb144, 0x0c69,
+	0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071,
+	0xb140, 0x7044, 0x8000, 0x7046, 0x00ee, 0x000e, 0x012e, 0x0005,
+	0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
+	0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
+	0x5790
+};
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2200tp_length01 = 0xa019;
+#else
+unsigned short risc_code_length01 = 0xa019;
+#endif
+
diff -urN linux-2.4.16/drivers/scsi/ql2300_fw.h lia64-2.4/drivers/scsi/ql2300_fw.h
--- linux-2.4.16/drivers/scsi/ql2300_fw.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/ql2300_fw.h	Mon Jul 23 14:12:14 2001
@@ -0,0 +1,5486 @@
+/************************************************************************
+ *									*
+ *               --- ISP2300 Initiator/Target Firmware ---              *
+ *             with Fabric (Public Loop), Point-point, and              *
+ *             expanded LUN addressing for FCTAPE                       *
+ *									*
+ ************************************************************************
+  Copyright (C) 2000 and 2001 Qlogic Corporation 
+  (www.qlogic.com)
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+ ************************************************************************/
+/*
+ *	Firmware Version 3.00.24 (14:18 Jun 05, 2001)
+ */
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2300tp_version = 3*1024+0;
+#else
+unsigned short risc_code_version = 3*1024+0;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned char fw2300tp_version_str[] = {3, 0,24};
+#else
+unsigned char firmware_version[] = {3, 0,24};
+#endif
+
+#ifdef UNIQUE_FW_NAME
+#define fw2300tp_VERSION_STRING "3.00.24"
+#else
+#define FW_VERSION_STRING "3.00.24"
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2300tp_addr01 = 0x0800 ;
+#else
+unsigned short risc_code_addr01 = 0x0800 ;
+#endif
+
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2300tp_code01[] = { 
+#else
+unsigned short risc_code01[] = { 
+#endif
+	0x0470, 0x0000, 0x0000, 0xa9b8, 0x0000, 0x0003, 0x0000, 0x0018,
+	0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030,
+	0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
+	0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972,
+	0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
+	0x332e, 0x3030, 0x2e32, 0x3420, 0x2020, 0x2020, 0x2400, 0x20a9,
+	0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f,
+	0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001,
+	0x0000, 0x400f, 0x2091, 0x2600, 0x20a9, 0x000f, 0x2001, 0x0000,
+	0x400f, 0x2091, 0x2800, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f,
+	0x2091, 0x2a00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091,
+	0x2c00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2e00,
+	0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2000, 0x2001,
+	0x0000, 0x20c1, 0x0004, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9,
+	0x14ff, 0x2059, 0x0000, 0x2b78, 0x7883, 0x0004, 0x2089, 0x2102,
+	0x2051, 0x1100, 0x2a70, 0x20e1, 0x0001, 0x20e9, 0x0001, 0x2029,
+	0x45c0, 0x2031, 0xffff, 0x2039, 0x45a9, 0x2021, 0x0200, 0x20e9,
+	0x0001, 0x20a1, 0x1000, 0x900e, 0x20a9, 0x05c0, 0x4104, 0x755e,
+	0x7662, 0x775a, 0x7466, 0x746a, 0x20a1, 0x15c0, 0x7160, 0x810d,
+	0x810d, 0x810d, 0x810d, 0x918c, 0x000f, 0x2001, 0x0001, 0x9112,
+	0x900e, 0x21a8, 0x4104, 0x8211, 0x1de0, 0x7160, 0x3400, 0x8001,
+	0x9102, 0x0120, 0x0218, 0x20a8, 0x900e, 0x4104, 0x2009, 0x1100,
+	0x810d, 0x810d, 0x810d, 0x810d, 0x810d, 0x918c, 0x001f, 0x2001,
+	0x0001, 0x9112, 0x20e9, 0x0001, 0x20a1, 0x0800, 0x900e, 0x20a9,
+	0x0800, 0x4104, 0x8211, 0x1dd8, 0x2009, 0x1100, 0x3400, 0x9102,
+	0x0120, 0x0218, 0x20a8, 0x900e, 0x4104, 0x080c, 0x0e42, 0x080c,
+	0x0f8f, 0x080c, 0x13a2, 0x080c, 0x0c8a, 0x080c, 0x4721, 0x080c,
+	0x7ebf, 0x080c, 0x0dae, 0x080c, 0x27c1, 0x080c, 0x5a05, 0x080c,
+	0x4e0f, 0x080c, 0x64ba, 0x080c, 0x1956, 0x080c, 0x6721, 0x080c,
+	0x5fe8, 0x080c, 0x1768, 0x080c, 0x18cb, 0x080c, 0x194b, 0x2091,
+	0x3009, 0x7883, 0x0000, 0x1004, 0x0905, 0x7880, 0x9086, 0x0002,
+	0x1160, 0x7883, 0x4000, 0x7837, 0x4000, 0x7833, 0x0010, 0x0e04,
+	0x08ff, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000,
+	0x2a70, 0x7000, 0x908e, 0x0003, 0x1168, 0x080c, 0x3816, 0x080c,
+	0x27e5, 0x080c, 0x5a60, 0x080c, 0x52b6, 0x080c, 0x64e0, 0x080c,
+	0x20a5, 0x0c70, 0x000b, 0x0c88, 0x0926, 0x0927, 0x0a62, 0x0924,
+	0x0b34, 0x0c87, 0x0c88, 0x0c89, 0x080c, 0x0cf1, 0x0005, 0x0126,
+	0x00f6, 0x2091, 0x8000, 0x7000, 0x9086, 0x0001, 0x1904, 0x0a30,
+	0x7034, 0xd0b4, 0x1130, 0x0026, 0x2011, 0x0080, 0x080c, 0x0d63,
+	0x002e, 0x080c, 0x5745, 0x0150, 0x080c, 0x576b, 0x1570, 0x2079,
+	0x0100, 0x7828, 0x9085, 0x1800, 0x782a, 0x0438, 0x080c, 0x5682,
+	0x7000, 0x9086, 0x0001, 0x1904, 0x0a30, 0x7088, 0x9086, 0x0028,
+	0x1904, 0x0a30, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100,
+	0x7827, 0xffff, 0x7a28, 0x9295, 0x1e2f, 0x7a2a, 0x2011, 0x5654,
+	0x080c, 0x655b, 0x2011, 0x4586, 0x080c, 0x655b, 0x2011, 0x8030,
+	0x2019, 0x0000, 0x7087, 0x0000, 0x00d8, 0x080c, 0x3e5a, 0x2079,
+	0x0100, 0x7844, 0x9005, 0x1904, 0x0a30, 0x2011, 0x4586, 0x080c,
+	0x655b, 0x2001, 0x0265, 0x2001, 0x0205, 0x2003, 0x0000, 0x780f,
+	0x006b, 0x7840, 0x9084, 0xfffb, 0x7842, 0x2011, 0x8010, 0x73c8,
+	0x080c, 0x1f80, 0x080c, 0x37dc, 0x7238, 0xc284, 0x723a, 0x2001,
+	0x110c, 0x200c, 0xc1ac, 0xc1cc, 0x2102, 0x080c, 0x788f, 0x2011,
+	0x0004, 0x080c, 0x95d8, 0x080c, 0x4d24, 0x080c, 0x5745, 0x01e8,
+	0x080c, 0x46dd, 0x0140, 0x7087, 0x0001, 0x70c3, 0x0000, 0x080c,
+	0x4016, 0x0804, 0x0a30, 0x2001, 0x1153, 0x2004, 0xd094, 0x0168,
+	0x2011, 0x110c, 0x2204, 0xc0cd, 0x2012, 0x080c, 0x1fc4, 0x1228,
+	0x2011, 0x110c, 0x2204, 0xc0bc, 0x0020, 0x2011, 0x110c, 0x2204,
+	0xc0bd, 0x2012, 0x080c, 0x4de0, 0x0120, 0x7a0c, 0xc2b4, 0x7a0e,
+	0x0050, 0x080c, 0x99a3, 0x70cc, 0xd09c, 0x1128, 0x709c, 0x9005,
+	0x0110, 0x080c, 0x46bb, 0x70d7, 0x0000, 0x70d3, 0x0000, 0x72cc,
+	0x080c, 0x5745, 0x1178, 0x2011, 0x0000, 0x0016, 0x080c, 0x1d69,
+	0x2019, 0x1280, 0x211a, 0x001e, 0x704f, 0xffff, 0x7053, 0x00ef,
+	0x7073, 0x0000, 0x2079, 0x1152, 0x7804, 0xd0ac, 0x0108, 0xc295,
+	0x72ce, 0x080c, 0x5745, 0x0118, 0x9296, 0x0004, 0x0508, 0x2011,
+	0x0001, 0x080c, 0x95d8, 0x7097, 0x0000, 0x709b, 0xffff, 0x7003,
+	0x0002, 0x00fe, 0x080c, 0x23cd, 0x2011, 0x0005, 0x080c, 0x79c2,
+	0x080c, 0x6d42, 0x080c, 0x5745, 0x0148, 0x00c6, 0x2061, 0x0100,
+	0x0016, 0x080c, 0x1d69, 0x61e2, 0x001e, 0x00ce, 0x012e, 0x00d0,
+	0x7097, 0x0000, 0x709b, 0xffff, 0x7003, 0x0002, 0x2011, 0x0005,
+	0x080c, 0x79c2, 0x080c, 0x6d42, 0x080c, 0x5745, 0x0148, 0x00c6,
+	0x2061, 0x0100, 0x0016, 0x080c, 0x1d69, 0x61e2, 0x001e, 0x00ce,
+	0x00fe, 0x012e, 0x0005, 0x00c6, 0x080c, 0x5745, 0x1118, 0x20a9,
+	0x0100, 0x0010, 0x20a9, 0x0082, 0x080c, 0x5745, 0x1118, 0x2009,
+	0x0000, 0x0010, 0x2009, 0x007e, 0x0016, 0x0026, 0x0036, 0x2110,
+	0x0026, 0x2019, 0x0029, 0x080c, 0x7ba2, 0x002e, 0x080c, 0xad6c,
+	0x003e, 0x002e, 0x001e, 0x080c, 0x26a3, 0x8108, 0x1f04, 0x0a44,
+	0x00ce, 0x706f, 0x0000, 0x7070, 0x9084, 0x00ff, 0x7072, 0x709f,
+	0x0000, 0x0005, 0x0126, 0x2091, 0x8000, 0x7000, 0x9086, 0x0002,
+	0x1904, 0x0b32, 0x7098, 0x9086, 0xffff, 0x0130, 0x080c, 0x23cd,
+	0x080c, 0x6d42, 0x0804, 0x0b32, 0x70cc, 0xd0ac, 0x1110, 0xd09c,
+	0x0520, 0xd084, 0x0510, 0x0006, 0x2001, 0x0103, 0x2003, 0x002b,
+	0x000e, 0xd08c, 0x01d0, 0x70d0, 0x9086, 0xffff, 0x0190, 0x080c,
+	0x252c, 0x080c, 0x6d42, 0x70cc, 0xd094, 0x1904, 0x0b32, 0x2011,
+	0x0001, 0x2019, 0x0000, 0x080c, 0x2562, 0x080c, 0x6d42, 0x0804,
+	0x0b32, 0x70d4, 0x9005, 0x1904, 0x0b32, 0x7094, 0x9005, 0x1904,
+	0x0b32, 0x70cc, 0xd0a4, 0x0118, 0xd0b4, 0x0904, 0x0b32, 0x080c,
+	0x4de0, 0x1904, 0x0b32, 0x2001, 0x1153, 0x2004, 0xd0ac, 0x01c8,
+	0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x080c,
+	0x4b58, 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, 0x8108, 0x1f04,
+	0x0ab6, 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, 0x015e, 0x0804,
+	0x0b32, 0x0006, 0x2001, 0x0103, 0x2003, 0x006b, 0x000e, 0x9006,
+	0x2009, 0x0700, 0x20a9, 0x0002, 0x20a1, 0x12ca, 0x20e9, 0x0001,
+	0x4001, 0x706c, 0x8007, 0x7170, 0x810f, 0x20a9, 0x0002, 0x4001,
+	0x2009, 0x0000, 0x080c, 0x0cd7, 0x2001, 0x0000, 0x810f, 0x20a9,
+	0x0002, 0x4001, 0x9006, 0x2009, 0x0200, 0x20a9, 0x0002, 0x20a1,
+	0x12da, 0x4001, 0x7030, 0xc08c, 0x7032, 0x7003, 0x0003, 0x709b,
+	0xffff, 0x7034, 0xd0b4, 0x1130, 0x0026, 0x2011, 0x0040, 0x080c,
+	0x0d63, 0x002e, 0x9006, 0x080c, 0x1c36, 0x0036, 0x0046, 0x2019,
+	0xffff, 0x2021, 0x0006, 0x080c, 0x384a, 0x004e, 0x003e, 0x00f6,
+	0x2079, 0x0100, 0x080c, 0x576b, 0x0150, 0x080c, 0x5745, 0x7828,
+	0x0118, 0x9084, 0xe1ff, 0x0010, 0x9084, 0xffdf, 0x782a, 0x00fe,
+	0x2001, 0x12dd, 0x2004, 0x9086, 0x0005, 0x1120, 0x2011, 0x0000,
+	0x080c, 0x79c2, 0x2011, 0x0000, 0x080c, 0x79cc, 0x080c, 0x6d42,
+	0x080c, 0x6e10, 0x012e, 0x0005, 0x0016, 0x0046, 0x00f6, 0x0126,
+	0x2091, 0x8000, 0x2079, 0x0100, 0x2009, 0x00f7, 0x080c, 0x46a4,
+	0x7940, 0x918c, 0x0010, 0x7942, 0x7924, 0xd1b4, 0x0110, 0x7827,
+	0x0040, 0xd19c, 0x0110, 0x7827, 0x0008, 0x0006, 0x0036, 0x0156,
+	0x7954, 0xd1ac, 0x1904, 0x0b9b, 0x080c, 0x5757, 0x0158, 0x080c,
+	0x576b, 0x1128, 0x2001, 0x128f, 0x2003, 0x0000, 0x0070, 0x080c,
+	0x574d, 0x0dc0, 0x2001, 0x128f, 0x2003, 0xaaaa, 0x2001, 0x1290,
+	0x2003, 0x0001, 0x080c, 0x5682, 0x0058, 0x080c, 0x5745, 0x0140,
+	0x2009, 0x00f8, 0x080c, 0x46a4, 0x7843, 0x0090, 0x7843, 0x0010,
+	0x20a9, 0x09c4, 0x7820, 0xd09c, 0x1138, 0x080c, 0x5745, 0x0138,
+	0x7824, 0xd0ac, 0x1904, 0x0c6f, 0x1f04, 0x0b7a, 0x0070, 0x7824,
+	0x080c, 0x5761, 0x0118, 0xd0ac, 0x1904, 0x0c6f, 0x9084, 0x1800,
+	0x0d98, 0x7003, 0x0001, 0x0804, 0x0c6f, 0x2001, 0x0001, 0x080c,
+	0x1c36, 0x0804, 0x0c78, 0x080c, 0x203d, 0x1148, 0x2001, 0x0001,
+	0x080c, 0x1faf, 0x2001, 0x0001, 0x080c, 0x1f92, 0x00d8, 0x080c,
+	0x2045, 0x1138, 0x9006, 0x080c, 0x1faf, 0x9006, 0x080c, 0x1f92,
+	0x0088, 0x080c, 0x204d, 0x1d50, 0x2001, 0x12b8, 0x2004, 0xd0fc,
+	0x0128, 0x7828, 0x9085, 0x0020, 0x782a, 0x0020, 0x080c, 0x1d96,
+	0x0804, 0x0c6a, 0x7850, 0x9085, 0x0040, 0x7852, 0x7938, 0x7850,
+	0x9084, 0xfbcf, 0x7852, 0x080c, 0x2055, 0x9085, 0x2000, 0x7852,
+	0x793a, 0x20a9, 0x0046, 0x1d04, 0x0bd3, 0x2091, 0x6000, 0x1f04,
+	0x0bd3, 0x7850, 0x9085, 0x0400, 0x9084, 0xdfbf, 0x7852, 0x793a,
+	0x080c, 0x5757, 0x0158, 0x080c, 0x576b, 0x1128, 0x2001, 0x128f,
+	0x2003, 0x0000, 0x0070, 0x080c, 0x574d, 0x0dc0, 0x2001, 0x128f,
+	0x2003, 0xaaaa, 0x2001, 0x1290, 0x2003, 0x0001, 0x080c, 0x5682,
+	0x0020, 0x2009, 0x00f8, 0x080c, 0x46a4, 0x20a9, 0x0028, 0xa001,
+	0x1f04, 0x0bff, 0x7850, 0x9085, 0x1400, 0x7852, 0x080c, 0x5745,
+	0x0120, 0x7843, 0x0090, 0x7843, 0x0010, 0x2021, 0xe678, 0x2019,
+	0xea60, 0x7820, 0xd09c, 0x1528, 0x080c, 0x5745, 0x05c0, 0x7824,
+	0xd0ac, 0x1904, 0x0c6f, 0x080c, 0x576b, 0x11d8, 0x0046, 0x2021,
+	0x0320, 0x8421, 0x1df0, 0x004e, 0x7827, 0x1800, 0x080c, 0x2055,
+	0x7824, 0x9084, 0x1800, 0x1110, 0x8421, 0x1158, 0x2001, 0x128f,
+	0x2003, 0xaaaa, 0x2001, 0x1290, 0x2003, 0x0001, 0x7003, 0x0001,
+	0x04b0, 0x8319, 0x19b0, 0x2009, 0x12bb, 0x2104, 0x8001, 0x200a,
+	0x1168, 0x7827, 0x0048, 0x20a9, 0x0002, 0x080c, 0x2036, 0x7924,
+	0x080c, 0x2055, 0xd19c, 0x0110, 0x080c, 0x1f80, 0x00d8, 0x080c,
+	0x5757, 0x1140, 0x94a2, 0x03e8, 0x1128, 0x080c, 0x571c, 0x7003,
+	0x0001, 0x00a8, 0x7827, 0x1800, 0x080c, 0x2055, 0x7824, 0x080c,
+	0x5761, 0x0110, 0xd0ac, 0x1158, 0x9084, 0x1800, 0x0990, 0x7003,
+	0x0001, 0x0028, 0x2001, 0x0001, 0x080c, 0x1c36, 0x0028, 0x7827,
+	0x0048, 0x7828, 0xc09d, 0x782a, 0x7850, 0x9085, 0x0400, 0x7852,
+	0x9006, 0x78f2, 0x015e, 0x003e, 0x000e, 0x7034, 0xd0b4, 0x1110,
+	0x080c, 0x0d29, 0x012e, 0x00fe, 0x004e, 0x001e, 0x0005, 0x0005,
+	0x0005, 0x0005, 0x2a70, 0x2001, 0x128f, 0x2003, 0x0000, 0x7087,
+	0x0000, 0x2009, 0x0100, 0x2104, 0x9082, 0x0002, 0x0218, 0x704f,
+	0xffff, 0x0010, 0x704f, 0x0000, 0x7057, 0xffff, 0x706f, 0x0000,
+	0x7073, 0x0000, 0x080c, 0x99a3, 0x2061, 0x127f, 0x6003, 0x0909,
+	0x6007, 0x0000, 0x600b, 0x8800, 0x600f, 0x0200, 0x6013, 0x00ff,
+	0x6017, 0x0003, 0x601b, 0x0000, 0x601f, 0x07d0, 0x2061, 0x1287,
+	0x6003, 0x8000, 0x6007, 0x0000, 0x600b, 0x0000, 0x600f, 0x0200,
+	0x6013, 0x00ff, 0x6017, 0x0000, 0x601b, 0x0001, 0x601f, 0x0000,
+	0x2061, 0x12a9, 0x6003, 0x514c, 0x6007, 0x4f47, 0x600b, 0x4943,
+	0x600f, 0x2020, 0x2001, 0x1127, 0x2003, 0x0000, 0x0005, 0x2011,
+	0x0000, 0x080c, 0x4b58, 0x1178, 0x6004, 0x90c4, 0x00ff, 0x98c6,
+	0x0006, 0x0128, 0x90c4, 0xff00, 0x98c6, 0x0600, 0x1120, 0x9186,
+	0x0080, 0x0108, 0x8210, 0x8108, 0x9186, 0x0100, 0x1d50, 0x2208,
+	0x0005, 0x2091, 0x8000, 0x0e04, 0x0cf3, 0x0006, 0x0016, 0x2079,
+	0x0000, 0x001e, 0x798e, 0x000e, 0x788a, 0x000e, 0x7886, 0x3900,
+	0x789a, 0x7883, 0x8002, 0x7837, 0x8002, 0x7833, 0x0012, 0x2091,
+	0x5000, 0x0156, 0x00d6, 0x2079, 0x0300, 0x7803, 0x0000, 0x2069,
+	0x1331, 0x901e, 0x20a9, 0x0020, 0x7b26, 0x7a28, 0x226a, 0x8d68,
+	0x8318, 0x1f04, 0x0d14, 0x00de, 0x015e, 0x2079, 0x1100, 0x7803,
+	0x0005, 0x2091, 0x4080, 0x7834, 0xd0b4, 0x1108, 0x0451, 0x0cd8,
+	0x0005, 0x00f6, 0x0006, 0x2079, 0x1123, 0x2f04, 0x8000, 0x207a,
+	0x9082, 0x000f, 0x0258, 0x9006, 0x207a, 0x2079, 0x1125, 0x2f04,
+	0x9084, 0x0001, 0x9086, 0x0001, 0x207a, 0x0080, 0x2079, 0x1125,
+	0x2f7c, 0x8fff, 0x1130, 0x0026, 0x2011, 0x0080, 0x00e1, 0x002e,
+	0x0028, 0x0026, 0x2011, 0x0000, 0x00b1, 0x002e, 0x000e, 0x00fe,
+	0x0005, 0x0026, 0x2011, 0x0080, 0x0071, 0x002e, 0x2009, 0x0fff,
+	0x00b9, 0x0026, 0x2011, 0x0040, 0x0031, 0x002e, 0x2009, 0x0fff,
+	0x0079, 0x0c78, 0x0005, 0x0016, 0x3b08, 0x3a00, 0x9104, 0x918d,
+	0x00c0, 0x21d8, 0x9084, 0xff3f, 0x9205, 0x20d0, 0x001e, 0x0005,
+	0x0156, 0x0126, 0x918c, 0x0fff, 0x21a8, 0x1d04, 0x0d75, 0x2091,
+	0x6000, 0x1f04, 0x0d75, 0x012e, 0x015e, 0x0005, 0x890b, 0x810b,
+	0x810b, 0x810b, 0x810b, 0x810b, 0x9994, 0xfc00, 0x8217, 0x8214,
+	0x8214, 0x0005, 0x0006, 0x814c, 0x894c, 0x894c, 0x894c, 0x894c,
+	0x894c, 0x9284, 0x003f, 0x8007, 0x8003, 0x8003, 0x994d, 0x000e,
+	0x0005, 0x0016, 0x0026, 0x0096, 0x3348, 0x0c01, 0x2100, 0x9300,
+	0x2098, 0x22e0, 0x009e, 0x002e, 0x001e, 0x3518, 0x20a9, 0x0001,
+	0x4002, 0x8007, 0x4004, 0x8319, 0x1dd8, 0x0005, 0x2071, 0x1100,
+	0x715c, 0x712e, 0x2021, 0x0001, 0x9190, 0x0040, 0x9298, 0x0040,
+	0x0240, 0x7060, 0x9302, 0x1228, 0x220a, 0x2208, 0x2310, 0x8420,
+	0x0ca8, 0x200b, 0x0000, 0x74ae, 0x74b2, 0x0005, 0x00e6, 0x0126,
+	0x2091, 0x8000, 0x2071, 0x1100, 0x70b0, 0x90ea, 0x0010, 0x0268,
+	0x8001, 0x70b2, 0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000,
+	0x6807, 0x0000, 0x012e, 0x00ee, 0x0005, 0x906e, 0x0cd8, 0x00e6,
+	0x2071, 0x1100, 0x0126, 0x2091, 0x8000, 0x70b0, 0x8001, 0x0260,
+	0x70b2, 0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807,
+	0x0000, 0x012e, 0x00ee, 0x0005, 0x906e, 0x0cd8, 0x00e6, 0x0126,
+	0x2091, 0x8000, 0x2071, 0x1100, 0x702c, 0x206a, 0x2d00, 0x702e,
+	0x70b0, 0x8000, 0x70b2, 0x012e, 0x00ee, 0x0005, 0x8dff, 0x0138,
+	0x6804, 0x6807, 0x0000, 0x0006, 0x0c49, 0x00de, 0x0cb8, 0x0005,
+	0x00e6, 0x2071, 0x1100, 0x70b0, 0x908a, 0x0010, 0x900d, 0x00ee,
+	0x0005, 0x00d6, 0x0821, 0x0148, 0x0016, 0x0026, 0x2d08, 0x2011,
+	0x0001, 0x080c, 0x0d8a, 0x002e, 0x001e, 0x00de, 0x0005, 0x00d6,
+	0x080c, 0x0dc6, 0x0148, 0x0016, 0x0026, 0x2d08, 0x2011, 0x0001,
+	0x080c, 0x0d8a, 0x002e, 0x001e, 0x00de, 0x0005, 0x00d6, 0x0016,
+	0x0026, 0x080c, 0x0d7e, 0x2168, 0x002e, 0x001e, 0x080c, 0x0df6,
+	0x00de, 0x0005, 0x00e6, 0x2071, 0x130a, 0x7007, 0x0000, 0x701f,
+	0x0000, 0x7023, 0x0000, 0x7003, 0x0000, 0x2071, 0x0000, 0x7010,
+	0x9085, 0x8004, 0x7012, 0x00ee, 0x0005, 0x00e6, 0x2270, 0x700b,
+	0x0000, 0x2071, 0x130a, 0x701c, 0x9088, 0x1314, 0x220a, 0x8000,
+	0x9084, 0x0007, 0x701e, 0x7004, 0x9005, 0x1128, 0x00f6, 0x2079,
+	0x0080, 0x0081, 0x00fe, 0x00ee, 0x0005, 0x00e6, 0x2071, 0x130a,
+	0x7004, 0x9005, 0x1128, 0x00f6, 0x2079, 0x0080, 0x0019, 0x00fe,
+	0x00ee, 0x0005, 0x7000, 0x0002, 0x0e7e, 0x0cf1, 0x701c, 0x7120,
+	0x9106, 0x1118, 0x7007, 0x0000, 0x0005, 0x00d6, 0x9180, 0x1314,
+	0x2004, 0x700a, 0x2068, 0x8108, 0x918c, 0x0007, 0x7122, 0x782b,
+	0x0026, 0x6828, 0x7802, 0x682c, 0x7806, 0x6830, 0x780a, 0x6834,
+	0x780e, 0x6814, 0x700e, 0x680c, 0x7016, 0x6810, 0x701a, 0x6804,
+	0x00de, 0xd084, 0x0120, 0x7007, 0x0001, 0x0029, 0x0005, 0x7007,
+	0x0002, 0x00b1, 0x0005, 0x0016, 0x0026, 0x710c, 0x2011, 0x0040,
+	0x9182, 0x0040, 0x1210, 0x2110, 0x9006, 0x700e, 0x7212, 0x8203,
+	0x7812, 0x782b, 0x0020, 0x782b, 0x0041, 0x002e, 0x001e, 0x0005,
+	0x0016, 0x0026, 0x0136, 0x0146, 0x0156, 0x7014, 0x20e0, 0x7018,
+	0x2098, 0x20e9, 0x0000, 0x20a1, 0x0088, 0x782b, 0x0026, 0x710c,
+	0x2011, 0x0040, 0x9182, 0x0040, 0x1210, 0x2110, 0x9006, 0x700e,
+	0x22a8, 0x4006, 0x8203, 0x7812, 0x782b, 0x0020, 0x3300, 0x701a,
+	0x782b, 0x0001, 0x015e, 0x014e, 0x013e, 0x002e, 0x001e, 0x0005,
+	0x0016, 0x00e6, 0x2071, 0x130a, 0x00f6, 0x2079, 0x0080, 0x792c,
+	0x782b, 0x0002, 0xd1fc, 0x0120, 0x918c, 0x0700, 0x7004, 0x0023,
+	0x00fe, 0x00ee, 0x001e, 0x0005, 0x0e7a, 0x0f01, 0x0f33, 0x0f00,
+	0x0cf8, 0x918c, 0x0700, 0x1548, 0x0136, 0x0146, 0x0156, 0x7014,
+	0x20e8, 0x7018, 0x20a0, 0x20e1, 0x0000, 0x2099, 0x0088, 0x782b,
+	0x0040, 0x7010, 0x20a8, 0x4005, 0x3400, 0x701a, 0x015e, 0x014e,
+	0x013e, 0x700c, 0x9005, 0x0560, 0x7800, 0x7802, 0x7804, 0x7806,
+	0x080c, 0x0eab, 0x0005, 0x7008, 0x9080, 0x0002, 0x2003, 0x0100,
+	0x7007, 0x0000, 0x080c, 0x0e7a, 0x0005, 0x7008, 0x9080, 0x0002,
+	0x2003, 0x0200, 0x0ca8, 0x918c, 0x0700, 0x1150, 0x700c, 0x9005,
+	0x0178, 0x7800, 0x7802, 0x7804, 0x7806, 0x080c, 0x0ec0, 0x0005,
+	0x7008, 0x9080, 0x0002, 0x2003, 0x0200, 0x7007, 0x0000, 0x0080,
+	0x00d6, 0x7008, 0x2068, 0x7800, 0x682a, 0x7804, 0x682e, 0x7808,
+	0x6832, 0x780c, 0x6836, 0x680b, 0x0100, 0x00de, 0x7007, 0x0000,
+	0x00c6, 0x00d6, 0x7008, 0x2060, 0x0081, 0x0150, 0x6038, 0x080f,
+	0x603b, 0x0000, 0x603f, 0x0000, 0x2c00, 0x2068, 0x080c, 0x0df6,
+	0x00de, 0x00ce, 0x080c, 0x0e7a, 0x0005, 0x00e6, 0x2071, 0x1100,
+	0x8cff, 0x0140, 0x705c, 0x9c02, 0x0238, 0x9c82, 0xffff, 0x1220,
+	0x9085, 0x0001, 0x00ee, 0x0005, 0x9006, 0x0ce0, 0x603c, 0x906d,
+	0x090c, 0x0cf1, 0x6008, 0x908e, 0x0100, 0x0130, 0x687b, 0x0030,
+	0x6883, 0x0000, 0x6897, 0x4002, 0x080c, 0x50a5, 0x0005, 0x0126,
+	0x2091, 0x2200, 0x2079, 0x0300, 0x2071, 0x131c, 0x7003, 0x0000,
+	0x78bf, 0x00f6, 0x00c1, 0x7803, 0x0003, 0x780f, 0x0000, 0x20a9,
+	0x01c4, 0x2061, 0xae21, 0x2c0d, 0x7912, 0xe104, 0x9ce0, 0x0002,
+	0x7916, 0x1f04, 0x0fa3, 0x7807, 0x0001, 0x7803, 0x0000, 0x7803,
+	0x0001, 0x012e, 0x0005, 0x00c6, 0x7803, 0x0000, 0x7827, 0x0030,
+	0x782b, 0x0400, 0x7827, 0x0031, 0x782b, 0x1331, 0x781f, 0xff00,
+	0x781b, 0xff00, 0x2061, 0x1331, 0x602f, 0x15c0, 0x6033, 0x3000,
+	0x603b, 0x168e, 0x00ce, 0x0005, 0x0126, 0x2091, 0x2200, 0x7808,
+	0xd09c, 0x0138, 0x7820, 0x908c, 0xf000, 0x1508, 0x0043, 0x012e,
+	0x0005, 0x9084, 0x0070, 0x190c, 0x0cf1, 0x012e, 0x0005, 0x0ff5,
+	0x0ff7, 0x0ffe, 0x1002, 0x1006, 0x100b, 0x100e, 0x1012, 0x101f,
+	0x1024, 0x0ff5, 0x108d, 0x1091, 0x10d3, 0x0ff5, 0x0ff5, 0x0ff5,
+	0x0ff5, 0x0ff5, 0x0ff5, 0x0ff5, 0x0ff5, 0x080c, 0x0cf1, 0x2009,
+	0x0048, 0x2060, 0x080c, 0x7f4e, 0x012e, 0x0005, 0x7004, 0xc085,
+	0x7006, 0x0005, 0x7004, 0xc085, 0x7006, 0x0005, 0x080c, 0x10da,
+	0x080c, 0x1161, 0x0005, 0x080c, 0x0cf1, 0x0005, 0x7004, 0xc095,
+	0x7006, 0x0005, 0x080c, 0x10da, 0x2060, 0x6014, 0x9080, 0x000e,
+	0x2003, 0xffff, 0x2009, 0x0048, 0x080c, 0x7f4e, 0x0005, 0x080c,
+	0x10da, 0x080c, 0x0cf1, 0x0005, 0x080c, 0x10da, 0x2001, 0x0016,
+	0x080c, 0x113b, 0x7827, 0x0018, 0x79ac, 0xd1dc, 0x01c8, 0x7827,
+	0x0015, 0x7828, 0x782b, 0x0000, 0x9065, 0x0138, 0x2001, 0x020d,
+	0x2003, 0x0050, 0x2003, 0x0020, 0x0088, 0x7004, 0x9005, 0x090c,
+	0x0cf1, 0x78ab, 0x0004, 0x7803, 0x0001, 0x080c, 0x1091, 0x0005,
+	0x7828, 0x782b, 0x0000, 0x9065, 0x090c, 0x0cf1, 0x6014, 0x2068,
+	0x78ab, 0x0004, 0x918c, 0x0700, 0x01d8, 0x080c, 0x1337, 0x080c,
+	0x95d2, 0x0158, 0x69ac, 0x6936, 0x69b0, 0x693a, 0x683f, 0xffff,
+	0x6843, 0xffff, 0x6880, 0xc0bd, 0x6882, 0x7827, 0x0015, 0x782b,
+	0x0000, 0x781f, 0x0300, 0x7803, 0x0001, 0x080c, 0x92a4, 0x0005,
+	0x6010, 0x2004, 0xd0bc, 0x190c, 0x993c, 0x2001, 0x0201, 0x2004,
+	0x9005, 0x0dd8, 0x7dbc, 0x080c, 0xadd8, 0xd5a4, 0x1118, 0x080c,
+	0x10df, 0x0005, 0x080c, 0x1337, 0x7827, 0x0015, 0x782b, 0x0000,
+	0x781f, 0x0300, 0x7803, 0x0001, 0x0005, 0x7004, 0xc09d, 0x7006,
+	0x0005, 0x7104, 0x9184, 0x0004, 0x190c, 0x0cf1, 0xd184, 0x1181,
+	0xd19c, 0x0150, 0xc19c, 0x7106, 0x2001, 0x020d, 0x2003, 0x0050,
+	0x2003, 0x0020, 0x04e1, 0x0005, 0x81ff, 0x190c, 0x0cf1, 0x0005,
+	0xc184, 0x7106, 0x0016, 0x00e6, 0x2071, 0x0200, 0x080c, 0x1155,
+	0x6014, 0x9005, 0x01c0, 0x9080, 0x0019, 0x2004, 0x9084, 0x00ff,
+	0x9086, 0x0029, 0x1180, 0x00f6, 0x2c78, 0x080c, 0x119d, 0x00fe,
+	0x2001, 0x020d, 0x2003, 0x0020, 0x080c, 0x0fb3, 0x7803, 0x0001,
+	0x00ee, 0x001e, 0x0005, 0x2001, 0x020d, 0x2003, 0x0050, 0x2003,
+	0x0020, 0x0069, 0x0ca8, 0x0031, 0x2060, 0x2009, 0x0053, 0x080c,
+	0x7f4e, 0x0005, 0x7808, 0xd09c, 0x0de8, 0x7820, 0x0005, 0x00d6,
+	0x2069, 0x0200, 0x7908, 0x918c, 0x0007, 0x9186, 0x0003, 0x0120,
+	0x2001, 0x0016, 0x080c, 0x113b, 0x6804, 0x9005, 0x0de8, 0x2001,
+	0x015d, 0x2003, 0x0000, 0x79bc, 0x0016, 0x001e, 0xd1a4, 0x1518,
+	0x79b8, 0x0016, 0x001e, 0x918c, 0x0fff, 0x0178, 0x9182, 0x0841,
+	0x1260, 0x9188, 0x0007, 0x918c, 0x0ff8, 0x810c, 0x810c, 0x810c,
+	0x0421, 0x6827, 0x0001, 0x8109, 0x1dd8, 0x00f9, 0x6827, 0x0002,
+	0x00e1, 0x682c, 0xd0e4, 0x1148, 0x6804, 0x9005, 0x0de8, 0x79b8,
+	0xd1ec, 0x1118, 0x08c0, 0x080c, 0x1337, 0x7827, 0x0015, 0x782b,
+	0x0000, 0x2001, 0x020d, 0x2003, 0x0020, 0x2001, 0x0307, 0x2003,
+	0x0300, 0x7803, 0x0001, 0x00de, 0x0005, 0x6824, 0x9084, 0x0003,
+	0x1de0, 0x0005, 0x2001, 0x0030, 0x2c08, 0x621c, 0x0021, 0x7830,
+	0x9086, 0x0041, 0x0005, 0x00f6, 0x2079, 0x0300, 0x0006, 0x7808,
+	0xd09c, 0x0140, 0x0016, 0x0026, 0x00c6, 0x080c, 0x0fcc, 0x00ce,
+	0x002e, 0x001e, 0x000e, 0x7832, 0x7936, 0x7a3a, 0x781b, 0x8080,
+	0x7818, 0xd0bc, 0x1de8, 0x00fe, 0x0005, 0x7037, 0x0001, 0x7150,
+	0x7037, 0x0002, 0x7050, 0x2060, 0xd1bc, 0x1110, 0x7054, 0x2060,
+	0x0005, 0x00e6, 0x0016, 0x2071, 0x0200, 0x0c79, 0x7358, 0x745c,
+	0x6014, 0x905d, 0x0530, 0x2b68, 0x6010, 0x2004, 0xd0bc, 0x190c,
+	0x9917, 0x6b42, 0x6c3e, 0x2001, 0x1174, 0x2004, 0xd0b4, 0x1120,
+	0x683b, 0xffff, 0x6837, 0xffff, 0x080c, 0x16ae, 0x1190, 0x080c,
+	0x1255, 0x2a00, 0x6816, 0x0130, 0x2c00, 0x680e, 0x2805, 0x680a,
+	0x2800, 0x6812, 0x7037, 0x0020, 0x781f, 0x0300, 0x001e, 0x00ee,
+	0x0005, 0x7037, 0x0050, 0x7037, 0x0020, 0x001e, 0x00ee, 0x080c,
+	0x10df, 0x0005, 0x080c, 0x0cf1, 0x0005, 0x2ff0, 0x0126, 0x2091,
+	0x2200, 0x3e60, 0x6014, 0x2068, 0x2d60, 0x903e, 0x2730, 0x6964,
+	0x691a, 0x9184, 0x000f, 0x9088, 0x168e, 0x2145, 0x0002, 0x11bf,
+	0x1226, 0x11bf, 0x11bf, 0x11bf, 0x11ff, 0x11bf, 0x11c3, 0x11bf,
+	0x1214, 0x11bf, 0x11bf, 0x11bf, 0x11bf, 0x11e9, 0x11d5, 0x9085,
+	0x0001, 0x0804, 0x124d, 0x687c, 0xd0bc, 0x0dc8, 0x6890, 0x6842,
+	0x688c, 0x683e, 0x6888, 0x00d6, 0x2805, 0x9c68, 0x6b08, 0x6a0c,
+	0x6d00, 0x6c04, 0x00de, 0x0804, 0x1235, 0x687c, 0xd0bc, 0x0d38,
+	0x6890, 0x6842, 0x688c, 0x683e, 0x6888, 0x00d6, 0x2805, 0x9c68,
+	0x6b10, 0x6a14, 0x6d00, 0x6c04, 0x6f08, 0x6e0c, 0x00de, 0x0804,
+	0x1235, 0x687c, 0xd0bc, 0x0998, 0x6890, 0x6842, 0x688c, 0x683e,
+	0x6804, 0x2060, 0x9080, 0x0019, 0x200c, 0x691a, 0x91cc, 0x000f,
+	0x9980, 0x168e, 0x2045, 0x6888, 0xd19c, 0x11e8, 0x0470, 0x687c,
+	0xd0ac, 0x0904, 0x11bf, 0x6804, 0x2060, 0x9080, 0x0019, 0x200c,
+	0x691a, 0x91cc, 0x000f, 0x9980, 0x168e, 0x2045, 0x9006, 0x6842,
+	0x683e, 0xd19c, 0x1140, 0x00c8, 0x687c, 0xd0ac, 0x0904, 0x11bf,
+	0x9006, 0x6842, 0x683e, 0x00d6, 0x2805, 0x9c68, 0x6b10, 0x6a14,
+	0x6d00, 0x6c04, 0x6f08, 0x6e0c, 0x00de, 0x0078, 0x687c, 0xd0ac,
+	0x0904, 0x11bf, 0x9006, 0x6842, 0x683e, 0x00d6, 0x2805, 0x9c68,
+	0x6b08, 0x6a0c, 0x6d00, 0x6c04, 0x00de, 0x6b2e, 0x6a32, 0x6d1e,
+	0x6c22, 0x6f26, 0x6e2a, 0x6988, 0x8840, 0x281d, 0x68ac, 0x6ab0,
+	0x6836, 0x6a3a, 0x8109, 0x6916, 0x1150, 0x3e60, 0x601c, 0xc085,
+	0x601e, 0x687c, 0xc0dd, 0x687e, 0x9006, 0x012e, 0x0005, 0x2c00,
+	0x680e, 0x6b0a, 0x2800, 0x6812, 0x0c80, 0x903e, 0x2730, 0x6880,
+	0xd0fc, 0x11a8, 0x00d6, 0x2805, 0x9c68, 0x2900, 0x0002, 0x1297,
+	0x127d, 0x127d, 0x1297, 0x1297, 0x1291, 0x1297, 0x127d, 0x1297,
+	0x1282, 0x1282, 0x1297, 0x1297, 0x1297, 0x1289, 0x1282, 0xc0fc,
+	0x6882, 0x6b2c, 0x6a30, 0x6d1c, 0x6c20, 0x00d6, 0xd99c, 0x0510,
+	0x2805, 0x9c68, 0x6f08, 0x6e0c, 0x00e8, 0x6b08, 0x6a0c, 0x6d00,
+	0x6c04, 0x00c0, 0x6b10, 0x6a14, 0x6d00, 0x6c04, 0x6f08, 0x6e0c,
+	0x0088, 0x00de, 0x00d6, 0x6864, 0x9084, 0x00ff, 0x9086, 0x001e,
+	0x1130, 0x00de, 0x080c, 0x164e, 0x1900, 0x900e, 0x0060, 0x00de,
+	0x080c, 0x0cf1, 0x00de, 0x6b2e, 0x6a32, 0x6d1e, 0x6c22, 0x6f26,
+	0x6e2a, 0x080c, 0x164e, 0x0005, 0x2001, 0x020b, 0x2004, 0xd0e4,
+	0x0110, 0xd0d4, 0x1140, 0x6014, 0x9080, 0x0021, 0x6118, 0x2102,
+	0x601b, 0x0002, 0x0005, 0x0126, 0x00c6, 0x2091, 0x2200, 0x00ce,
+	0x2001, 0x0037, 0x2c08, 0x080c, 0x113b, 0x6000, 0x9086, 0x0004,
+	0x1120, 0x2009, 0x0048, 0x080c, 0x7f4e, 0x012e, 0x0005, 0x0126,
+	0x00c6, 0x2091, 0x2200, 0x00ce, 0x7908, 0x918c, 0x0007, 0x9186,
+	0x0000, 0x0904, 0x132c, 0x9186, 0x0003, 0x0904, 0x132c, 0x6020,
+	0x6023, 0x0000, 0x0006, 0x2031, 0x0190, 0x00c6, 0x7808, 0xd09c,
+	0x190c, 0x0fcc, 0x00ce, 0x2001, 0x0038, 0x2c08, 0x621c, 0x080c,
+	0x113b, 0x7930, 0x9186, 0x0040, 0x05d8, 0x9186, 0x0042, 0x190c,
+	0x0cf1, 0x2001, 0x001e, 0x8001, 0x1df0, 0x8631, 0x1d30, 0x080c,
+	0x136e, 0x0026, 0x0056, 0x2001, 0x00d2, 0x8001, 0x1df0, 0x2031,
+	0x2000, 0x8631, 0x05a1, 0x2001, 0x020b, 0x2004, 0xd0e4, 0x0dc8,
+	0x78ab, 0x0004, 0x080c, 0x0fb3, 0x781f, 0x8080, 0x78ab, 0x0009,
+	0x601c, 0xc084, 0x601e, 0x080c, 0x5745, 0x1130, 0x0066, 0x2031,
+	0x0001, 0x080c, 0x57d6, 0x006e, 0x7803, 0x0000, 0x7803, 0x0001,
+	0x005e, 0x002e, 0x2001, 0x0160, 0x2502, 0x2001, 0x0138, 0x2202,
+	0x000e, 0x6022, 0x012e, 0x0005, 0x601c, 0xc084, 0x601e, 0x7827,
+	0x0015, 0x7828, 0x9c06, 0x1db0, 0x782b, 0x0000, 0x0c98, 0x080c,
+	0x5745, 0x11b0, 0x2001, 0x0138, 0x2003, 0x0000, 0x2001, 0x0160,
+	0x2003, 0x0000, 0x2011, 0x012c, 0xa001, 0xa001, 0x8211, 0x1de0,
+	0x0081, 0x0066, 0x2031, 0x0000, 0x080c, 0x57d6, 0x006e, 0x0005,
+	0x00e9, 0x0039, 0x2001, 0x0160, 0x2502, 0x2001, 0x0138, 0x2202,
+	0x0005, 0x00e6, 0x2071, 0x0200, 0x080c, 0x205b, 0x7003, 0x002c,
+	0x2001, 0x015d, 0x2003, 0x0000, 0x7000, 0x9084, 0x002c, 0x1de0,
+	0x7098, 0x709a, 0x709c, 0x709e, 0x00ee, 0x0005, 0x2001, 0x0138,
+	0x2014, 0x2003, 0x0000, 0x2001, 0x0160, 0x202c, 0x2003, 0x0000,
+	0x2021, 0x0260, 0x2001, 0x0141, 0x201c, 0xd3dc, 0x1168, 0x2001,
+	0x0109, 0x201c, 0x939c, 0x0048, 0x1160, 0x2001, 0x0111, 0x201c,
+	0x83ff, 0x1110, 0x8421, 0x1d70, 0x2001, 0x015d, 0x2003, 0x0000,
+	0x0005, 0x0046, 0x2021, 0x0019, 0x2003, 0x0048, 0xa001, 0xa001,
+	0x201c, 0x939c, 0x0048, 0x0120, 0x8421, 0x1db0, 0x004e, 0x0c60,
+	0x004e, 0x0c40, 0x00e6, 0x2071, 0x131f, 0x7003, 0x0000, 0x00ee,
+	0x0005, 0x00d6, 0x9280, 0x0005, 0x206c, 0x697c, 0xd1dc, 0x1904,
+	0x141f, 0x6964, 0x9184, 0x0007, 0x0002, 0x13bd, 0x140a, 0x13bd,
+	0x13bd, 0x13bd, 0x13f1, 0x13d0, 0x13bf, 0x080c, 0x0cf1, 0x687c,
+	0xd0b4, 0x0904, 0x1507, 0x6890, 0x6842, 0x683a, 0x688c, 0x683e,
+	0x6836, 0x68ac, 0x6846, 0x68b0, 0x684a, 0x6988, 0x0804, 0x1412,
+	0x6864, 0x9084, 0x00ff, 0x9086, 0x001e, 0x1d38, 0x687c, 0xd0b4,
+	0x0904, 0x1507, 0x6890, 0x6842, 0x683a, 0x688c, 0x683e, 0x6836,
+	0x68ac, 0x6846, 0x68b0, 0x684a, 0x6804, 0x685a, 0x9080, 0x0019,
+	0x2004, 0x9084, 0x000f, 0x9080, 0x168e, 0x2005, 0x6812, 0x6988,
+	0x0450, 0x918c, 0x00ff, 0x9186, 0x0015, 0x1548, 0x687c, 0xd0b4,
+	0x0904, 0x1507, 0x6804, 0x685a, 0x9080, 0x0019, 0x2004, 0x9084,
+	0x000f, 0x9080, 0x168e, 0x2005, 0x6812, 0x6988, 0x9006, 0x6842,
+	0x683e, 0x0088, 0x687c, 0xd0b4, 0x0904, 0x1507, 0x6988, 0x9006,
+	0x6842, 0x683e, 0x2d00, 0x685a, 0x6864, 0x9084, 0x000f, 0x9080,
+	0x168e, 0x2005, 0x6812, 0x6916, 0x687c, 0xc0dd, 0x687e, 0x00de,
+	0x0005, 0x00f6, 0x2079, 0x0090, 0x782c, 0xd0fc, 0x190c, 0x1543,
+	0x00e6, 0x00d6, 0x2071, 0x131f, 0x7000, 0x9005, 0x1904, 0x1478,
+	0x00c6, 0x7206, 0x9280, 0x0005, 0x205c, 0x7004, 0x2068, 0x782b,
+	0x0004, 0x6810, 0x00d6, 0x2068, 0x686c, 0x7836, 0x6890, 0x00f6,
+	0x2079, 0x0200, 0x7803, 0x0040, 0x781a, 0x2079, 0x0100, 0x8004,
+	0x78d6, 0x00fe, 0x00de, 0x2b68, 0x6814, 0x2050, 0x6858, 0x2060,
+	0x6810, 0x2040, 0x6064, 0x90cc, 0x000f, 0x6944, 0x791a, 0x7116,
+	0x6848, 0x781e, 0x701a, 0x9006, 0x700e, 0x7012, 0x7004, 0x6940,
+	0x6838, 0x9106, 0x11c8, 0x693c, 0x6834, 0x9106, 0x11a8, 0x8aff,
+	0x01f0, 0x0126, 0x2091, 0x8000, 0x2079, 0x0090, 0x2009, 0x0001,
+	0x00d1, 0x0118, 0x2009, 0x0001, 0x00b1, 0x012e, 0x00ce, 0x9006,
+	0x00de, 0x00ee, 0x00fe, 0x0005, 0x0036, 0x0046, 0x6b38, 0x6c34,
+	0x080c, 0x16ae, 0x004e, 0x003e, 0x0d10, 0x00ce, 0x0c88, 0x00ce,
+	0x9085, 0x0001, 0x0c68, 0x0076, 0x0066, 0x0056, 0x0046, 0x0036,
+	0x0026, 0x8aff, 0x0904, 0x1500, 0x700c, 0x7214, 0x923a, 0x7010,
+	0x7218, 0x9203, 0x0a04, 0x14ff, 0x9705, 0x0904, 0x14ff, 0x903e,
+	0x2730, 0x6880, 0xd0fc, 0x11a8, 0x00d6, 0x2805, 0x9c68, 0x2900,
+	0x0002, 0x14e2, 0x14c7, 0x14c7, 0x14e2, 0x14e2, 0x14db, 0x14e2,
+	0x14c7, 0x14e2, 0x14cc, 0x14cc, 0x14e2, 0x14e2, 0x14e2, 0x14d3,
+	0x14cc, 0xc0fc, 0x6882, 0x6b2c, 0x6a30, 0x6d1c, 0x6c20, 0xd99c,
+	0x0528, 0x00d6, 0x2805, 0x9c68, 0x6f08, 0x6e0c, 0x00f0, 0x6b08,
+	0x6a0c, 0x6d00, 0x6c04, 0x00c8, 0x6b10, 0x6a14, 0x6d00, 0x6c04,
+	0x6f08, 0x6e0c, 0x0090, 0x00de, 0x00d6, 0x6864, 0x9084, 0x00ff,
+	0x9086, 0x001e, 0x1138, 0x00de, 0x080c, 0x164e, 0x1904, 0x1491,
+	0x900e, 0x00f0, 0x00de, 0x080c, 0x0cf1, 0x00de, 0x7b12, 0x7a16,
+	0x7d02, 0x7c06, 0x7f0a, 0x7e0e, 0x792a, 0x7000, 0x8000, 0x7002,
+	0x683c, 0x9300, 0x683e, 0x6840, 0x9201, 0x6842, 0x700c, 0x9300,
+	0x700e, 0x7010, 0x9201, 0x7012, 0x080c, 0x164e, 0x0008, 0x9006,
+	0x002e, 0x003e, 0x004e, 0x005e, 0x006e, 0x007e, 0x0005, 0x080c,
+	0x0cf1, 0x0026, 0x2001, 0x0105, 0x2003, 0x0010, 0x782b, 0x0004,
+	0x7003, 0x0000, 0x7004, 0x2060, 0x00d6, 0x6014, 0x2068, 0x080c,
+	0x95d2, 0x0118, 0x6880, 0xc0bd, 0x6882, 0x6020, 0x9086, 0x0006,
+	0x1180, 0x2061, 0x0100, 0x62c8, 0x2001, 0x00fa, 0x8001, 0x1df0,
+	0x60c8, 0x9206, 0x1dc0, 0x60c4, 0x689a, 0x60c8, 0x6896, 0x7004,
+	0x2060, 0x00de, 0x080c, 0x92a4, 0x2001, 0x0200, 0x2003, 0x0040,
+	0x080c, 0x7b66, 0x2011, 0x0000, 0x080c, 0x79cc, 0x080c, 0x6e10,
+	0x002e, 0x0804, 0x15fd, 0x0126, 0x2091, 0x2400, 0x0006, 0x0016,
+	0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x2079, 0x0090, 0x2071, 0x131f,
+	0x2b68, 0x6858, 0x2060, 0x792c, 0x782b, 0x0002, 0x9184, 0x0700,
+	0x1904, 0x1509, 0x7000, 0x0002, 0x15fd, 0x1560, 0x15d0, 0x15fb,
+	0x8001, 0x7002, 0xd19c, 0x1170, 0x8aff, 0x05d0, 0x2009, 0x0001,
+	0x080c, 0x148b, 0x0904, 0x15fd, 0x2009, 0x0001, 0x080c, 0x148b,
+	0x0804, 0x15fd, 0x782b, 0x0004, 0xd194, 0x0148, 0x6880, 0xc0fc,
+	0x6882, 0x8aff, 0x11d8, 0x687c, 0xc0f5, 0x687e, 0x00b8, 0x0026,
+	0x0036, 0x6b3c, 0x6a40, 0x7810, 0x682e, 0x931a, 0x7814, 0x6832,
+	0x9213, 0x7800, 0x681e, 0x7804, 0x6822, 0x6b3e, 0x6a42, 0x003e,
+	0x002e, 0x080c, 0x1666, 0x6880, 0xc0fd, 0x6882, 0x2a00, 0x6816,
+	0x2c00, 0x685a, 0x2800, 0x6812, 0x7003, 0x0000, 0x0804, 0x15fd,
+	0x00f6, 0x0026, 0x781c, 0x0006, 0x7818, 0x0006, 0x2079, 0x0100,
+	0x7a14, 0x9284, 0x1984, 0x9085, 0x0012, 0x7816, 0x0036, 0x2019,
+	0x1000, 0x8319, 0x090c, 0x0cf1, 0x7820, 0xd0bc, 0x1dd0, 0x003e,
+	0x79c8, 0x000e, 0x9102, 0x001e, 0x0006, 0x0016, 0x79c4, 0x000e,
+	0x9103, 0x78c6, 0x000e, 0x78ca, 0x9284, 0x1984, 0x9085, 0x0012,
+	0x7816, 0x002e, 0x00fe, 0x782b, 0x0008, 0x7003, 0x0000, 0x0468,
+	0x8001, 0x7002, 0xd194, 0x0168, 0x782c, 0xd0fc, 0x1904, 0x1553,
+	0xd19c, 0x11f8, 0x8aff, 0x0508, 0x2009, 0x0001, 0x080c, 0x148b,
+	0x00e0, 0x0026, 0x0036, 0x6b3c, 0x6a40, 0x080c, 0x1666, 0x00d6,
+	0x2805, 0x9c68, 0x6064, 0xd09c, 0x1128, 0x6808, 0x931a, 0x680c,
+	0x9213, 0x0020, 0x6810, 0x931a, 0x6814, 0x9213, 0x00de, 0x0804,
+	0x1583, 0x0804, 0x157f, 0x080c, 0x0cf1, 0x00ce, 0x00de, 0x00ee,
+	0x00fe, 0x001e, 0x000e, 0x012e, 0x0005, 0x00f6, 0x00e6, 0x2071,
+	0x131f, 0x7000, 0x9086, 0x0000, 0x05f0, 0x2079, 0x0090, 0x2009,
+	0x0207, 0x210c, 0xd194, 0x01a8, 0x2009, 0x020c, 0x210c, 0x9184,
+	0x0003, 0x0178, 0x080c, 0xae13, 0x2001, 0x0133, 0x2004, 0x9005,
+	0x090c, 0x0cf1, 0x2001, 0x0200, 0x2003, 0x0040, 0x2001, 0x020c,
+	0x2102, 0x2009, 0x0206, 0x2104, 0x2009, 0x0203, 0x210c, 0x9106,
+	0x1120, 0x2001, 0x0200, 0x2003, 0x0040, 0x782c, 0xd0fc, 0x09b8,
+	0x080c, 0x1543, 0x7000, 0x9086, 0x0000, 0x1988, 0x782b, 0x0004,
+	0x782c, 0xd0ac, 0x1de8, 0x2001, 0x0200, 0x2003, 0x0040, 0x782b,
+	0x0002, 0x7003, 0x0000, 0x00ee, 0x00fe, 0x0005, 0x8840, 0x2805,
+	0x9005, 0x0110, 0x8a51, 0x0005, 0x6004, 0x9005, 0x0168, 0x685a,
+	0x2060, 0x6064, 0x9084, 0x000f, 0x9080, 0x168e, 0x2045, 0x88ff,
+	0x090c, 0x0cf1, 0x8a51, 0x0005, 0x2050, 0x0005, 0x8a50, 0x8841,
+	0x2805, 0x9005, 0x1190, 0x2c00, 0x9d06, 0x0120, 0x6000, 0x9005,
+	0x1108, 0x2d00, 0x2060, 0x685a, 0x6064, 0x9084, 0x000f, 0x9080,
+	0x169e, 0x2045, 0x88ff, 0x090c, 0x0cf1, 0x0005, 0x0000, 0x001d,
+	0x0021, 0x0025, 0x0029, 0x002d, 0x0031, 0x0035, 0x0000, 0x001b,
+	0x0021, 0x0027, 0x002d, 0x0033, 0x0000, 0x0000, 0x0000, 0x1683,
+	0x167f, 0x0000, 0x0000, 0x168d, 0x0000, 0x1683, 0x0000, 0x168a,
+	0x1687, 0x0000, 0x0000, 0x0000, 0x168d, 0x168a, 0x0000, 0x1685,
+	0x1685, 0x0000, 0x0000, 0x168d, 0x0000, 0x1685, 0x0000, 0x168b,
+	0x168b, 0x0000, 0x0000, 0x0000, 0x168d, 0x168b, 0x00a6, 0x0096,
+	0x0086, 0x6b42, 0x6c3e, 0x6888, 0x9055, 0x0904, 0x173f, 0x2d60,
+	0x6064, 0x90cc, 0x000f, 0x99c0, 0x168e, 0x9986, 0x0007, 0x0130,
+	0x9986, 0x000e, 0x0118, 0x9986, 0x000f, 0x1120, 0x608c, 0x9422,
+	0x6090, 0x931a, 0x2805, 0x9045, 0x1140, 0x0310, 0x0804, 0x173f,
+	0x6004, 0x9065, 0x0904, 0x173f, 0x0c18, 0x2805, 0x9005, 0x01a8,
+	0x9c68, 0xd99c, 0x1128, 0x6808, 0x9422, 0x680c, 0x931b, 0x0020,
+	0x6810, 0x9422, 0x6814, 0x931b, 0x0620, 0x2300, 0x9405, 0x0150,
+	0x8a51, 0x0904, 0x173f, 0x8840, 0x0c40, 0x6004, 0x9065, 0x0904,
+	0x173f, 0x0830, 0x8a51, 0x0904, 0x173f, 0x8840, 0x2805, 0x9005,
+	0x1158, 0x6004, 0x9065, 0x0904, 0x173f, 0x6064, 0x90cc, 0x000f,
+	0x99c0, 0x168e, 0x2805, 0x2040, 0x2b68, 0x6880, 0xc0fc, 0x6882,
+	0x0458, 0x8422, 0x8420, 0x831a, 0x9399, 0x0000, 0x00d6, 0x2b68,
+	0x6c2e, 0x6b32, 0x00de, 0xd99c, 0x1168, 0x6908, 0x2400, 0x9122,
+	0x690c, 0x2300, 0x911b, 0x0a0c, 0x0cf1, 0x6800, 0x9420, 0x6804,
+	0x9319, 0x0060, 0x6910, 0x2400, 0x9122, 0x6914, 0x2300, 0x911b,
+	0x0a0c, 0x0cf1, 0x6800, 0x9420, 0x6804, 0x9319, 0x2b68, 0x6c1e,
+	0x6b22, 0x6880, 0xc0fd, 0x6882, 0x2c00, 0x685a, 0x2800, 0x6812,
+	0x2a00, 0x6816, 0x000e, 0x000e, 0x000e, 0x9006, 0x0028, 0x008e,
+	0x009e, 0x00ae, 0x9085, 0x0001, 0x0005, 0x2001, 0x0005, 0x2004,
+	0x9084, 0x0007, 0x0002, 0x1753, 0x1543, 0x1754, 0x1755, 0x1758,
+	0x175b, 0x1760, 0x1763, 0x0005, 0x0005, 0x080c, 0x1543, 0x0005,
+	0x080c, 0x0ee8, 0x0005, 0x080c, 0x1543, 0x080c, 0x0ee8, 0x0005,
+	0x080c, 0x0ee8, 0x0005, 0x080c, 0x1543, 0x080c, 0x0ee8, 0x0005,
+	0x0126, 0x2091, 0x2600, 0x2079, 0x0200, 0x2071, 0x0260, 0x2069,
+	0x1100, 0x7817, 0x0000, 0x789b, 0x0814, 0x78a3, 0x0406, 0x789f,
+	0x0410, 0x2009, 0x013b, 0x200b, 0x0400, 0x781b, 0x0002, 0x783b,
+	0x001f, 0x7837, 0x0020, 0x7803, 0x1600, 0x012e, 0x0005, 0x2091,
+	0x2600, 0x781c, 0xd0a4, 0x190c, 0x18c8, 0x9084, 0x0006, 0x0002,
+	0x17a3, 0x1798, 0x5fe9, 0x179a, 0x179c, 0x179e, 0x17a0, 0x17a2,
+	0x080c, 0x0cf1, 0x080c, 0x0cf1, 0x0039, 0x0028, 0x0029, 0x0018,
+	0x0019, 0x0008, 0x0009, 0x0005, 0x0006, 0x0016, 0x0026, 0x080c,
+	0xae13, 0x7930, 0x9184, 0x0003, 0x0178, 0x2001, 0x12eb, 0x2004,
+	0x9005, 0x0130, 0x2001, 0x0133, 0x2004, 0x9005, 0x090c, 0x0cf1,
+	0x7803, 0x0040, 0x0804, 0x17fc, 0x9184, 0x0014, 0x01f0, 0x6a00,
+	0x9286, 0x0003, 0x1108, 0x00a0, 0x080c, 0x5745, 0x1178, 0x2001,
+	0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x9085,
+	0x0001, 0x080c, 0x5789, 0x080c, 0x5682, 0x0010, 0x080c, 0x45d6,
+	0x7803, 0x0010, 0x78a0, 0x78a2, 0x00f8, 0x9184, 0x1400, 0x0168,
+	0x00e6, 0x0036, 0x0046, 0x0056, 0x2071, 0x131c, 0x080c, 0x1337,
+	0x005e, 0x004e, 0x003e, 0x00ee, 0x0078, 0x9184, 0x0140, 0x0118,
+	0x7803, 0x0020, 0x0048, 0x9184, 0x8000, 0x0130, 0x080c, 0x205b,
+	0x7803, 0x0004, 0x7898, 0x789a, 0x002e, 0x001e, 0x000e, 0x0005,
+	0x0016, 0x0026, 0x0036, 0x0046, 0x00e6, 0x00f6, 0x2071, 0x1100,
+	0x7128, 0x2001, 0x1282, 0x2102, 0x2001, 0x128a, 0x2102, 0x2001,
+	0x013b, 0x2102, 0x2079, 0x0200, 0x9198, 0x0007, 0x831c, 0x831c,
+	0x831c, 0x2320, 0x9182, 0x0224, 0x1228, 0x2011, 0x0004, 0x8423,
+	0x8423, 0x0088, 0x9182, 0x02d4, 0x1228, 0x2011, 0x0003, 0x8403,
+	0x9420, 0x0048, 0x9182, 0x0444, 0x1220, 0x2011, 0x0002, 0x8423,
+	0x0010, 0x2011, 0x0001, 0x9482, 0x0110, 0x8002, 0x8020, 0x8301,
+	0x9402, 0x0110, 0x0208, 0x8321, 0x8217, 0x8203, 0x9405, 0x2001,
+	0x0201, 0x789e, 0x9198, 0x0007, 0x831c, 0x831c, 0x831c, 0x9398,
+	0x0003, 0x2320, 0x9182, 0x0204, 0x1228, 0x2011, 0x0004, 0x8423,
+	0x8423, 0x0088, 0x9182, 0x02b4, 0x1228, 0x2011, 0x0003, 0x8403,
+	0x9420, 0x0048, 0x9182, 0x041c, 0x1220, 0x2011, 0x0002, 0x8423,
+	0x0010, 0x2011, 0x0001, 0x9482, 0x010c, 0x8002, 0x8020, 0x8301,
+	0x9402, 0x0110, 0x0208, 0x8321, 0x8217, 0x8203, 0x9405, 0x2001,
+	0x0200, 0x78a2, 0x9198, 0x0007, 0x831c, 0x831c, 0x831c, 0x9398,
+	0x0005, 0x2320, 0x9182, 0x0204, 0x1230, 0x2011, 0x0008, 0x8423,
+	0x8423, 0x8423, 0x0488, 0x9182, 0x024c, 0x1240, 0x2011, 0x0007,
+	0x8403, 0x8003, 0x9400, 0x9400, 0x9420, 0x0430, 0x9182, 0x02bc,
+	0x1238, 0x2011, 0x0006, 0x8403, 0x8003, 0x9400, 0x9420, 0x00e0,
+	0x9182, 0x034c, 0x1230, 0x2011, 0x0005, 0x8403, 0x8003, 0x9420,
+	0x0098, 0x9182, 0x042c, 0x1228, 0x2011, 0x0004, 0x8423, 0x8423,
+	0x0058, 0x9182, 0x059c, 0x1228, 0x2011, 0x0003, 0x8403, 0x9420,
+	0x0018, 0x2011, 0x0002, 0x8423, 0x9482, 0x0228, 0x8002, 0x8020,
+	0x8301, 0x9402, 0x0110, 0x0208, 0x8321, 0x8217, 0x8203, 0x9405,
+	0x789a, 0x00fe, 0x00ee, 0x004e, 0x003e, 0x002e, 0x001e, 0x0005,
+	0x7938, 0x080c, 0x0cf1, 0x0126, 0x2091, 0x2800, 0x2061, 0x0100,
+	0x2071, 0x1100, 0x080c, 0x1f80, 0x6054, 0x8004, 0x8004, 0x8004,
+	0x8004, 0x9084, 0x000c, 0x6150, 0x918c, 0xfff3, 0x9105, 0x6052,
+	0x6050, 0x9084, 0xfbff, 0x9085, 0x2000, 0x6052, 0x2009, 0x12bd,
+	0x2011, 0x12be, 0x6358, 0x939c, 0x38f0, 0x2320, 0x080c, 0x1fc4,
+	0x1238, 0x939d, 0x4003, 0x94a5, 0x8603, 0x230a, 0x2412, 0x0030,
+	0x939d, 0x0203, 0x94a5, 0x8603, 0x230a, 0x2412, 0x9006, 0x080c,
+	0x1faf, 0x9006, 0x080c, 0x1f92, 0x20a9, 0x0012, 0x1d04, 0x1906,
+	0x2091, 0x6000, 0x1f04, 0x1906, 0x602f, 0x0100, 0x602f, 0x0000,
+	0x6050, 0x9085, 0x0400, 0x9084, 0xdfff, 0x6052, 0x6024, 0x6026,
+	0x080c, 0x1c83, 0x2009, 0x00ef, 0x6132, 0x6136, 0x080c, 0x1c93,
+	0x60e7, 0x0000, 0x61ea, 0x60e3, 0x0008, 0x604b, 0xf7f7, 0x6043,
+	0x0000, 0x602f, 0x0080, 0x602f, 0x0000, 0x6007, 0x049f, 0x60bb,
+	0x0000, 0x20a9, 0x0018, 0x60bf, 0x0000, 0x1f04, 0x1933, 0x60bb,
+	0x0000, 0x60bf, 0x0108, 0x60bf, 0x0012, 0x60bf, 0x0320, 0x60bf,
+	0x0018, 0x601b, 0x001e, 0x601f, 0x001e, 0x600f, 0x006b, 0x602b,
+	0x402f, 0x012e, 0x0005, 0x00f6, 0x2079, 0x0140, 0x78c3, 0x0080,
+	0x78c3, 0x0083, 0x78c3, 0x0000, 0x00fe, 0x0005, 0x2001, 0x1131,
+	0x2003, 0x0000, 0x2001, 0x1130, 0x2003, 0x0001, 0x0005, 0x0126,
+	0x2091, 0x2800, 0x0006, 0x0016, 0x0026, 0x6124, 0x9184, 0x5e2c,
+	0x1118, 0x9184, 0x0007, 0x002a, 0x9195, 0x0004, 0x9284, 0x0007,
+	0x0002, 0x1993, 0x1979, 0x197c, 0x197f, 0x1984, 0x1986, 0x198a,
+	0x198e, 0x080c, 0x677e, 0x00b8, 0x080c, 0x684f, 0x00a0, 0x080c,
+	0x684f, 0x080c, 0x677e, 0x0078, 0x0099, 0x0068, 0x080c, 0x677e,
+	0x0079, 0x0048, 0x080c, 0x684f, 0x0059, 0x0028, 0x080c, 0x684f,
+	0x080c, 0x677e, 0x0029, 0x002e, 0x001e, 0x000e, 0x012e, 0x0005,
+	0x6124, 0xd19c, 0x1904, 0x1bbd, 0xd1f4, 0x0110, 0x080c, 0x0cf1,
+	0x080c, 0x5745, 0x0578, 0x7000, 0x9086, 0x0003, 0x0198, 0x6024,
+	0x9084, 0x1800, 0x0178, 0x080c, 0x576b, 0x0118, 0x080c, 0x5757,
+	0x1148, 0x6027, 0x0020, 0x6043, 0x0000, 0x2001, 0x128f, 0x2003,
+	0xaaaa, 0x0458, 0x080c, 0x576b, 0x15d0, 0x6024, 0x9084, 0x1800,
+	0x1108, 0x04a8, 0x2001, 0x128f, 0x2003, 0xaaaa, 0x2001, 0x1290,
+	0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x080c, 0x5682,
+	0x0804, 0x1bbd, 0xd1ac, 0x1518, 0x6024, 0xd0dc, 0x1170, 0xd0e4,
+	0x1188, 0xd0d4, 0x11a0, 0xd0cc, 0x0130, 0x7088, 0x9086, 0x0028,
+	0x1110, 0x080c, 0x58e5, 0x0804, 0x1bbd, 0x2001, 0x1290, 0x2003,
+	0x0000, 0x0048, 0x2001, 0x1290, 0x2003, 0x0002, 0x0020, 0x080c,
+	0x5857, 0x0804, 0x1bbd, 0x080c, 0x597e, 0x0804, 0x1bbd, 0xd1ac,
+	0x0904, 0x1af0, 0x080c, 0x5745, 0x11d8, 0x6027, 0x0020, 0x0006,
+	0x0026, 0x0036, 0x080c, 0x5761, 0x1170, 0x2001, 0x1290, 0x2003,
+	0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x080c, 0x5682, 0x003e,
+	0x002e, 0x000e, 0x0005, 0x003e, 0x002e, 0x000e, 0x080c, 0x571c,
+	0x0016, 0x0046, 0x00c6, 0x644c, 0x9486, 0xf0f0, 0x1138, 0x2061,
+	0x0100, 0x644a, 0x6043, 0x0090, 0x6043, 0x0010, 0x74ca, 0x948c,
+	0xff00, 0x7034, 0xd084, 0x0178, 0x9186, 0xf800, 0x1160, 0x7038,
+	0xd084, 0x1148, 0xc085, 0x703a, 0x0036, 0x2418, 0x2011, 0x8016,
+	0x080c, 0x37dc, 0x003e, 0x9196, 0xff00, 0x05b8, 0x7050, 0x9084,
+	0x00ff, 0x810f, 0x9116, 0x0588, 0x7130, 0xd184, 0x1570, 0x2011,
+	0x1153, 0x2214, 0xd2ec, 0x0138, 0xc18d, 0x7132, 0x2011, 0x1153,
+	0x2214, 0xd2ac, 0x1510, 0x6240, 0x9294, 0x0010, 0x0130, 0x6248,
+	0x9294, 0xff00, 0x9296, 0xff00, 0x01c0, 0x7030, 0xd08c, 0x0904,
+	0x1ac6, 0x7034, 0xd08c, 0x1140, 0x2001, 0x110c, 0x200c, 0xd1ac,
+	0x1904, 0x1ac6, 0xc1ad, 0x2102, 0x0036, 0x73c8, 0x2011, 0x8013,
+	0x080c, 0x37dc, 0x003e, 0x0804, 0x1ac6, 0x7034, 0xd08c, 0x1140,
+	0x2001, 0x110c, 0x200c, 0xd1ac, 0x1904, 0x1ac6, 0xc1ad, 0x2102,
+	0x0036, 0x73c8, 0x2011, 0x8013, 0x080c, 0x37dc, 0x003e, 0x7130,
+	0xc185, 0x7132, 0x2011, 0x1153, 0x220c, 0xd1a4, 0x01f0, 0x0016,
+	0x2009, 0x0001, 0x2011, 0x0100, 0x080c, 0x66d5, 0x2019, 0x000e,
+	0x00c6, 0x2061, 0x0000, 0x080c, 0xaa50, 0x00ce, 0x9484, 0x00ff,
+	0x9080, 0x26c1, 0x200d, 0x918c, 0xff00, 0x810f, 0x8127, 0x9006,
+	0x2009, 0x000e, 0x080c, 0xaaca, 0x001e, 0xd1ac, 0x1148, 0x0016,
+	0x2009, 0x0000, 0x2019, 0x0004, 0x080c, 0x2582, 0x001e, 0x0070,
+	0x0156, 0x20a9, 0x007f, 0x2009, 0x0000, 0x080c, 0x4b58, 0x1110,
+	0x080c, 0x472d, 0x8108, 0x1f04, 0x1abd, 0x015e, 0x00ce, 0x004e,
+	0x2011, 0x0003, 0x080c, 0x79c2, 0x2011, 0x0002, 0x080c, 0x79cc,
+	0x080c, 0x78b3, 0x080c, 0x65cf, 0x0036, 0x2019, 0x0000, 0x080c,
+	0x7936, 0x003e, 0x60e3, 0x0000, 0x001e, 0x2001, 0x1100, 0x2014,
+	0x9296, 0x0004, 0x1128, 0xd19c, 0x1118, 0x6228, 0xc29d, 0x622a,
+	0x2003, 0x0001, 0x2001, 0x1122, 0x2003, 0x0000, 0x6027, 0x0020,
+	0xd194, 0x0904, 0x1bbd, 0x0016, 0x6220, 0xd2b4, 0x0904, 0x1b6e,
+	0x080c, 0x65cf, 0x080c, 0x7721, 0x6027, 0x0004, 0x00f6, 0x2019,
+	0x12e5, 0x2304, 0x907d, 0x05f0, 0x7804, 0x9086, 0x0032, 0x15d0,
+	0x00d6, 0x00c6, 0x00e6, 0x2069, 0x0140, 0x7810, 0x685e, 0x7808,
+	0x685a, 0x6043, 0x0002, 0x2001, 0x0003, 0x8001, 0x1df0, 0x6043,
+	0x0000, 0x2001, 0x003c, 0x8001, 0x1df0, 0x6803, 0x1000, 0x6803,
+	0x0000, 0x2001, 0x001e, 0x8001, 0x0240, 0x20a9, 0x0009, 0x080c,
+	0x2036, 0x6904, 0xd1dc, 0x1128, 0x0cb0, 0x6803, 0x1000, 0x6803,
+	0x0000, 0x080c, 0x6c56, 0x080c, 0x6d42, 0x7814, 0x2070, 0x7067,
+	0x0103, 0x2f60, 0x080c, 0x7f1e, 0x00ee, 0x00ce, 0x00de, 0x00fe,
+	0x001e, 0x0005, 0x00fe, 0x00d6, 0x2069, 0x0140, 0x6804, 0x9084,
+	0x4000, 0x0120, 0x6803, 0x1000, 0x6803, 0x0000, 0x00de, 0x00c6,
+	0x2061, 0x12dc, 0x6028, 0x909a, 0x00c8, 0x1238, 0x8000, 0x602a,
+	0x00ce, 0x080c, 0x76fd, 0x0804, 0x1bbc, 0x2061, 0x0100, 0x62c0,
+	0x080c, 0x7e9f, 0x2019, 0x12e5, 0x2304, 0x9065, 0x0120, 0x2009,
+	0x0027, 0x080c, 0x7f4e, 0x00ce, 0x0804, 0x1bbc, 0xd2bc, 0x0904,
+	0x1bbc, 0x080c, 0x65dc, 0x6014, 0x9084, 0x1984, 0x9085, 0x0010,
+	0x6016, 0x6027, 0x0004, 0x00d6, 0x2069, 0x0140, 0x6804, 0x9084,
+	0x4000, 0x0120, 0x6803, 0x1000, 0x6803, 0x0000, 0x00de, 0x00c6,
+	0x2061, 0x12dc, 0x6044, 0x909a, 0x00c8, 0x12f0, 0x8000, 0x6046,
+	0x603c, 0x00ce, 0x9005, 0x0540, 0x2009, 0x07d0, 0x080c, 0x65d4,
+	0x9080, 0x0008, 0x2004, 0x9086, 0x0006, 0x1138, 0x6114, 0x918c,
+	0x1984, 0x918d, 0x0012, 0x6116, 0x00b8, 0x6114, 0x918c, 0x1984,
+	0x918d, 0x0016, 0x6116, 0x0080, 0x0036, 0x2019, 0x0001, 0x080c,
+	0x7936, 0x003e, 0x2019, 0x12eb, 0x2304, 0x9065, 0x0120, 0x2009,
+	0x004f, 0x080c, 0x7f4e, 0x00ce, 0x001e, 0xd19c, 0x0904, 0x1c32,
+	0x0016, 0x0156, 0x6027, 0x0008, 0x6050, 0x9085, 0x0040, 0x6052,
+	0x6050, 0x9084, 0xfbcf, 0x6052, 0x080c, 0x2055, 0x9085, 0x2000,
+	0x6052, 0x20a9, 0x0012, 0x1d04, 0x1bd3, 0x2091, 0x6000, 0x1f04,
+	0x1bd3, 0x6050, 0x9085, 0x0400, 0x9084, 0xdfbf, 0x6052, 0x20a9,
+	0x0028, 0xa001, 0x1f04, 0x1be1, 0x6150, 0x9185, 0x1400, 0x6052,
+	0x20a9, 0x0366, 0x1d04, 0x1bea, 0x2091, 0x6000, 0x6020, 0xd09c,
+	0x1130, 0x015e, 0x6152, 0x001e, 0x6027, 0x0008, 0x04d8, 0x080c,
+	0x201f, 0x1f04, 0x1bea, 0x015e, 0x6152, 0x001e, 0x6027, 0x0008,
+	0x0016, 0x6028, 0xc09c, 0x602a, 0x2011, 0x0003, 0x080c, 0x79c2,
+	0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf,
+	0x0036, 0x2019, 0x0000, 0x080c, 0x7936, 0x003e, 0x60e3, 0x0000,
+	0x080c, 0xadf2, 0x080c, 0xae0d, 0x2001, 0x1172, 0x2004, 0xd0fc,
+	0x1120, 0x9085, 0x0001, 0x080c, 0x5789, 0x2001, 0x0140, 0x2003,
+	0x0000, 0x2001, 0x1100, 0x2003, 0x0004, 0x6027, 0x0008, 0x080c,
+	0x0b34, 0x001e, 0x918c, 0xffd0, 0x6126, 0x0005, 0x0006, 0x0016,
+	0x0026, 0x0036, 0x00e6, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2071,
+	0x1100, 0x71c0, 0x70c2, 0x9116, 0x01e0, 0x81ff, 0x0128, 0x2011,
+	0x8011, 0x080c, 0x37dc, 0x00a8, 0x2011, 0x8012, 0x080c, 0x37dc,
+	0x2001, 0x1172, 0x2004, 0xd0fc, 0x1160, 0x00c6, 0x080c, 0x1cde,
+	0x2061, 0x0100, 0x2019, 0x0028, 0x2009, 0x0000, 0x080c, 0x2582,
+	0x00ce, 0x012e, 0x00fe, 0x00ee, 0x003e, 0x002e, 0x001e, 0x000e,
+	0x0005, 0x2028, 0x918c, 0x00ff, 0x2130, 0x9094, 0xff00, 0x1110,
+	0x81ff, 0x0118, 0x080c, 0x6215, 0x0038, 0x9080, 0x26c1, 0x200d,
+	0x918c, 0xff00, 0x810f, 0x9006, 0x0005, 0x9080, 0x26c1, 0x200d,
+	0x918c, 0x00ff, 0x0005, 0x00d6, 0x2069, 0x0140, 0x2001, 0x1114,
+	0x2003, 0x00ef, 0x20a9, 0x0010, 0x9006, 0x6852, 0x6856, 0x1f04,
+	0x1c8e, 0x00de, 0x0005, 0x0006, 0x00d6, 0x0026, 0x2069, 0x0140,
+	0x2001, 0x1114, 0x2102, 0x8114, 0x8214, 0x8214, 0x8214, 0x20a9,
+	0x0010, 0x6853, 0x0000, 0x9006, 0x82ff, 0x1128, 0x9184, 0x000f,
+	0x9080, 0xb1a7, 0x2005, 0x6856, 0x8211, 0x1f04, 0x1ca3, 0x002e,
+	0x00de, 0x000e, 0x0005, 0x00c6, 0x2061, 0x1100, 0x6030, 0x0110,
+	0xc09d, 0x0008, 0xc09c, 0x6032, 0x00ce, 0x0005, 0x0156, 0x00d6,
+	0x0026, 0x0016, 0x0006, 0x2069, 0x0140, 0x6980, 0x9116, 0x0180,
+	0x9112, 0x1230, 0x8212, 0x8210, 0x22a8, 0x2001, 0x0402, 0x0018,
+	0x22a8, 0x2001, 0x0404, 0x680e, 0x1f04, 0x1cd3, 0x680f, 0x0000,
+	0x000e, 0x001e, 0x002e, 0x00de, 0x015e, 0x0005, 0x2001, 0x1153,
+	0x2004, 0xd0c4, 0x0150, 0xd0a4, 0x0140, 0x9006, 0x0046, 0x2020,
+	0x2009, 0x002e, 0x080c, 0xaaca, 0x004e, 0x0005, 0x00f6, 0x0016,
+	0x0026, 0x2079, 0x0140, 0x78c4, 0xd0dc, 0x0904, 0x1d51, 0x2009,
+	0x0100, 0x210c, 0x918a, 0x0007, 0x0610, 0x9084, 0x0700, 0x908e,
+	0x0600, 0x1128, 0x2011, 0x4000, 0x2009, 0x0000, 0x0400, 0x908e,
+	0x0500, 0x1128, 0x2011, 0x8000, 0x2009, 0x0000, 0x00c0, 0x908e,
+	0x0400, 0x1128, 0x2011, 0x0000, 0x2009, 0x0001, 0x0080, 0x908e,
+	0x0300, 0x15b8, 0x2011, 0x0000, 0x2009, 0x0002, 0x0040, 0x9084,
+	0x0700, 0x908e, 0x0300, 0x1568, 0x2011, 0x0030, 0x0038, 0x2300,
+	0x9080, 0x0020, 0x2018, 0x2300, 0x080c, 0x66ff, 0x2200, 0x8007,
+	0x9085, 0x004c, 0x78c2, 0x2009, 0x0227, 0x210c, 0x810f, 0x918c,
+	0x00ff, 0x810c, 0x2200, 0x9100, 0x2009, 0x0226, 0x210c, 0x810f,
+	0x918c, 0x00ff, 0x810c, 0x9100, 0x2009, 0x0138, 0x200a, 0x080c,
+	0x5745, 0x1118, 0x2009, 0x1280, 0x200a, 0x002e, 0x001e, 0x00fe,
+	0x0005, 0x78c3, 0x0000, 0x0cc8, 0x0126, 0x2091, 0x2800, 0x0006,
+	0x0016, 0x0026, 0x2001, 0x0170, 0x200c, 0x8000, 0x2014, 0x9184,
+	0x0003, 0x0110, 0x0804, 0x0cf1, 0x002e, 0x001e, 0x000e, 0x012e,
+	0x0005, 0x2001, 0x0171, 0x2004, 0xd0dc, 0x0168, 0x2001, 0x0170,
+	0x200c, 0x918c, 0x00ff, 0x918e, 0x004c, 0x1128, 0x200c, 0x918c,
+	0xff00, 0x810f, 0x0010, 0x2009, 0x0000, 0x2001, 0x0227, 0x2004,
+	0x8007, 0x9084, 0x00ff, 0x8004, 0x9108, 0x2001, 0x0226, 0x2004,
+	0x8007, 0x9084, 0x00ff, 0x8004, 0x9108, 0x0005, 0x0018, 0x000c,
+	0x0018, 0x0020, 0x1000, 0x0800, 0x1000, 0x1800, 0x0156, 0x0006,
+	0x0016, 0x0026, 0x00e6, 0x2001, 0x12b0, 0x2004, 0x908a, 0x0007,
+	0x1210, 0x004b, 0x0010, 0x080c, 0x0cf1, 0x00ee, 0x002e, 0x001e,
+	0x000e, 0x015e, 0x0005, 0x1db2, 0x1dd1, 0x1df6, 0x1df9, 0x1e23,
+	0x1e26, 0x1e29, 0x2001, 0x0001, 0x080c, 0x1c36, 0x080c, 0x201a,
+	0x2001, 0x12b2, 0x2003, 0x0000, 0x7828, 0x9084, 0xe1d7, 0x782a,
+	0x2001, 0x0000, 0x20a9, 0x0009, 0x080c, 0x1fd8, 0x2001, 0x12b0,
+	0x2003, 0x0006, 0x2009, 0x001e, 0x2011, 0x1e2a, 0x080c, 0x65e1,
+	0x0005, 0x2009, 0x12b5, 0x200b, 0x0000, 0x2001, 0x12ba, 0x2003,
+	0x0036, 0x2001, 0x12b9, 0x2003, 0x002a, 0x2001, 0x12b2, 0x2003,
+	0x0001, 0x2001, 0x0000, 0x080c, 0x1f92, 0x2001, 0xffff, 0x20a9,
+	0x0009, 0x080c, 0x1fd8, 0x2001, 0x12b0, 0x2003, 0x0006, 0x2009,
+	0x001e, 0x2011, 0x1e2a, 0x080c, 0x65e1, 0x0005, 0x080c, 0x0cf1,
+	0x0005, 0x2001, 0x12ba, 0x2003, 0x0036, 0x2001, 0x12b2, 0x2003,
+	0x0003, 0x7a38, 0x9294, 0x0005, 0x9296, 0x0004, 0x0118, 0x2001,
+	0x0000, 0x0010, 0x2001, 0x0001, 0x080c, 0x1f92, 0x2001, 0x12b6,
+	0x2003, 0x0000, 0x2001, 0xffff, 0x20a9, 0x0009, 0x080c, 0x1fd8,
+	0x2001, 0x12b0, 0x2003, 0x0006, 0x2009, 0x001e, 0x2011, 0x1e2a,
+	0x080c, 0x65e1, 0x0005, 0x080c, 0x0cf1, 0x0005, 0x080c, 0x0cf1,
+	0x0005, 0x0005, 0x0006, 0x0016, 0x0026, 0x00e6, 0x00f6, 0x0156,
+	0x0126, 0x2091, 0x8000, 0x2079, 0x0100, 0x2001, 0x12b2, 0x2004,
+	0x908a, 0x0007, 0x1210, 0x005b, 0x0010, 0x080c, 0x0cf1, 0x012e,
+	0x015e, 0x00fe, 0x00ee, 0x002e, 0x001e, 0x000e, 0x0005, 0x1e4e,
+	0x1e6e, 0x1eaf, 0x1edf, 0x1f03, 0x1f13, 0x1f16, 0x080c, 0x1fcc,
+	0x11b0, 0x7850, 0x9084, 0xefff, 0x7852, 0x2009, 0x12b8, 0x2104,
+	0x7a38, 0x9294, 0x0005, 0x9296, 0x0004, 0x0110, 0xc08d, 0x0008,
+	0xc085, 0x200a, 0x2001, 0x12b0, 0x2003, 0x0001, 0x0030, 0x080c,
+	0x1f3e, 0x2001, 0xffff, 0x080c, 0x1dc2, 0x0005, 0x080c, 0x1f19,
+	0x05e8, 0x2009, 0x12b9, 0x2104, 0x8001, 0x200a, 0x080c, 0x1fcc,
+	0x1178, 0x7850, 0x9084, 0xefff, 0x7852, 0x7a38, 0x9294, 0x0005,
+	0x9296, 0x0005, 0x0520, 0x2009, 0x12b8, 0x2104, 0xc085, 0x200a,
+	0x2009, 0x12b5, 0x2104, 0x8000, 0x200a, 0x9086, 0x0005, 0x0118,
+	0x080c, 0x1f22, 0x00c8, 0x200b, 0x0000, 0x7a38, 0x9294, 0x0006,
+	0x9296, 0x0004, 0x0118, 0x2001, 0x0000, 0x0010, 0x2001, 0x0001,
+	0x080c, 0x1faf, 0x2001, 0x12b2, 0x2003, 0x0002, 0x0028, 0x2001,
+	0x12b0, 0x2003, 0x0003, 0x0010, 0x080c, 0x1de5, 0x0005, 0x080c,
+	0x1f19, 0x0560, 0x2009, 0x12b9, 0x2104, 0x8001, 0x200a, 0x080c,
+	0x1fcc, 0x1168, 0x7850, 0x9084, 0xefff, 0x7852, 0x2001, 0x12b0,
+	0x2003, 0x0003, 0x2001, 0x12b1, 0x2003, 0x0000, 0x00b8, 0x2009,
+	0x12b9, 0x2104, 0x9005, 0x1118, 0x080c, 0x1f63, 0x0010, 0x080c,
+	0x1f30, 0x080c, 0x1f22, 0x2009, 0x12b5, 0x200b, 0x0000, 0x2001,
+	0x12b2, 0x2003, 0x0001, 0x080c, 0x1de5, 0x0000, 0x0005, 0x04c9,
+	0x0508, 0x080c, 0x1fcc, 0x11b8, 0x7850, 0x9084, 0xefff, 0x7852,
+	0x2009, 0x12b6, 0x2104, 0x8000, 0x200a, 0x9086, 0x0007, 0x0108,
+	0x0078, 0x2001, 0x12bb, 0x2003, 0x000a, 0x2009, 0x12b8, 0x2104,
+	0xc0fd, 0x200a, 0x0038, 0x0431, 0x2001, 0x12b2, 0x2003, 0x0004,
+	0x080c, 0x1e12, 0x0005, 0x00a9, 0x0168, 0x080c, 0x1fcc, 0x1138,
+	0x7850, 0x9084, 0xefff, 0x7852, 0x080c, 0x1dfd, 0x0018, 0x0091,
+	0x080c, 0x1e12, 0x0005, 0x080c, 0x0cf1, 0x0005, 0x080c, 0x0cf1,
+	0x0005, 0x2009, 0x12ba, 0x2104, 0x8001, 0x200a, 0x1110, 0x080c,
+	0x1f80, 0x0005, 0x7a38, 0x9294, 0x0005, 0x9296, 0x0005, 0x0118,
+	0x2001, 0x0000, 0x0010, 0x2001, 0x0001, 0x080c, 0x1faf, 0x0005,
+	0x7a38, 0x9294, 0x0006, 0x9296, 0x0006, 0x0118, 0x2001, 0x0000,
+	0x0010, 0x2001, 0x0001, 0x080c, 0x1f92, 0x0005, 0x2009, 0x12b5,
+	0x2104, 0x8000, 0x200a, 0x9086, 0x0005, 0x0108, 0x0070, 0x200b,
+	0x0000, 0x7a38, 0x9294, 0x0006, 0x9296, 0x0006, 0x0118, 0x2001,
+	0x0000, 0x0010, 0x2001, 0x0001, 0x04e9, 0x7a38, 0x9294, 0x0005,
+	0x9296, 0x0005, 0x0118, 0x2001, 0x0000, 0x0010, 0x2001, 0x0001,
+	0x080c, 0x1faf, 0x0005, 0x0086, 0x2001, 0x12b8, 0x2004, 0x9084,
+	0x7fff, 0x090c, 0x0cf1, 0x2009, 0x12b7, 0x2144, 0x8846, 0x280a,
+	0x9844, 0x0dd8, 0xd08c, 0x1120, 0xd084, 0x1128, 0x080c, 0x0cf1,
+	0x2001, 0x0000, 0x0010, 0x2001, 0x0001, 0x00a1, 0x008e, 0x0005,
+	0x0006, 0x0156, 0x2001, 0x12b0, 0x20a9, 0x0009, 0x2003, 0x0000,
+	0x8000, 0x1f04, 0x1f86, 0x2001, 0x12b7, 0x2003, 0x8000, 0x015e,
+	0x000e, 0x0005, 0x00f6, 0x2079, 0x0100, 0x9085, 0x0000, 0x0158,
+	0x7838, 0x9084, 0xfff9, 0x9085, 0x0004, 0x783a, 0x2009, 0x12bd,
+	0x210c, 0x795a, 0x0050, 0x7838, 0x9084, 0xfffb, 0x9085, 0x0006,
+	0x783a, 0x2009, 0x12be, 0x210c, 0x795a, 0x00fe, 0x0005, 0x00f6,
+	0x2079, 0x0100, 0x9085, 0x0000, 0x0138, 0x7838, 0x9084, 0xfffa,
+	0x9085, 0x0004, 0x783a, 0x0030, 0x7838, 0x9084, 0xfffb, 0x9085,
+	0x0005, 0x783a, 0x00fe, 0x0005, 0x0006, 0x2001, 0x0100, 0x2004,
+	0x9082, 0x0007, 0x000e, 0x0005, 0x0156, 0x20a9, 0x0064, 0x7820,
+	0x080c, 0x2055, 0xd09c, 0x1110, 0x1f04, 0x1fcf, 0x015e, 0x0005,
+	0x0126, 0x0016, 0x0006, 0x2091, 0x8000, 0x7850, 0x9085, 0x0040,
+	0x7852, 0x7850, 0x9084, 0xfbcf, 0x7852, 0x080c, 0x2055, 0x9085,
+	0x2000, 0x7852, 0x000e, 0x2008, 0x9186, 0x0000, 0x1118, 0x783b,
+	0x0007, 0x0090, 0x9186, 0x0001, 0x1118, 0x783b, 0x0006, 0x0060,
+	0x9186, 0x0002, 0x1118, 0x783b, 0x0005, 0x0030, 0x9186, 0x0003,
+	0x1118, 0x783b, 0x0004, 0x0000, 0x0006, 0x1d04, 0x2005, 0x2091,
+	0x6000, 0x1f04, 0x2005, 0x7850, 0x9085, 0x0400, 0x9084, 0xdfbf,
+	0x7852, 0x080c, 0x2055, 0x9085, 0x1000, 0x7852, 0x000e, 0x001e,
+	0x012e, 0x0005, 0x7850, 0x9084, 0xffcf, 0x7852, 0x0005, 0x0006,
+	0x0156, 0x00f6, 0x2079, 0x0100, 0x20a9, 0x000a, 0x7854, 0xd0ac,
+	0x1100, 0x7854, 0xd08c, 0x1110, 0x1f04, 0x2029, 0x00fe, 0x015e,
+	0x000e, 0x0005, 0x7820, 0x0409, 0xd09c, 0x0005, 0x1d04, 0x2036,
+	0x2091, 0x6000, 0x1f04, 0x2036, 0x0005, 0x0006, 0x2001, 0x12bc,
+	0x2004, 0x9086, 0x0000, 0x000e, 0x0005, 0x0006, 0x2001, 0x12bc,
+	0x2004, 0x9086, 0x0001, 0x000e, 0x0005, 0x0006, 0x2001, 0x12bc,
+	0x2004, 0x9086, 0x0002, 0x000e, 0x0005, 0xa001, 0xa001, 0xa001,
+	0xa001, 0xa001, 0x0005, 0x2009, 0x0171, 0x2104, 0xd0dc, 0x0140,
+	0x2009, 0x0170, 0x2104, 0x200b, 0x0080, 0xa001, 0xa001, 0x200a,
+	0x0005, 0x0036, 0x0046, 0x2001, 0x0141, 0x200c, 0x918c, 0xff00,
+	0x9186, 0x2000, 0x0118, 0x9186, 0x0100, 0x1560, 0x2009, 0x017f,
+	0x200b, 0x00a2, 0x2009, 0x0169, 0x2019, 0x0160, 0x2324, 0x2011,
+	0x0003, 0x2104, 0x9084, 0x0007, 0x9086, 0x0003, 0x11b8, 0x2304,
+	0x9402, 0x02a0, 0x1d98, 0x8211, 0x1da0, 0x84ff, 0x0170, 0x2001,
+	0x0141, 0x200c, 0x918c, 0xff00, 0x9186, 0x0100, 0x0130, 0x2009,
+	0x110c, 0x2104, 0xc0dd, 0x200a, 0x0008, 0x0419, 0x2001, 0x017f,
+	0x2003, 0x0000, 0x004e, 0x003e, 0x0005, 0x2001, 0x110c, 0x2004,
+	0xd0dc, 0x01b0, 0x2001, 0x0160, 0x2004, 0x9005, 0x0140, 0x2001,
+	0x0141, 0x2004, 0x9084, 0xff00, 0x9086, 0x0100, 0x1148, 0x0126,
+	0x2091, 0x8000, 0x0016, 0x0026, 0x0021, 0x002e, 0x001e, 0x012e,
+	0x0005, 0x00c6, 0x2061, 0x0100, 0x6014, 0x0006, 0x2001, 0x0161,
+	0x2003, 0x0000, 0x6017, 0x0018, 0xa001, 0xa001, 0x602f, 0x0008,
+	0x6104, 0x918e, 0x0010, 0x6106, 0x918e, 0x0010, 0x6106, 0x6017,
+	0x0040, 0x2001, 0x0140, 0x2003, 0x1000, 0x2003, 0x0000, 0x001e,
+	0x9184, 0x0003, 0x01c0, 0x0036, 0x2019, 0x0141, 0x2304, 0x9084,
+	0xff00, 0x9086, 0x0800, 0x1dd0, 0x919c, 0xffe4, 0x9184, 0x0001,
+	0x0118, 0x9385, 0x0009, 0x6016, 0x9184, 0x0002, 0x0118, 0x9385,
+	0x0012, 0x6016, 0x003e, 0x2001, 0x110c, 0x200c, 0xc1dc, 0x2102,
+	0x00ce, 0x0005, 0x23cc, 0x23cc, 0x2192, 0x219e, 0x21aa, 0x21b6,
+	0x21c2, 0x21d0, 0x21de, 0x21ea, 0x21f6, 0x2204, 0x2212, 0x2220,
+	0x222e, 0x223e, 0x2250, 0x2250, 0x225c, 0x225c, 0x226a, 0x226a,
+	0x2288, 0x2288, 0x22a8, 0x22a8, 0x2278, 0x2278, 0x2298, 0x2298,
+	0x22b6, 0x22b6, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x22c8, 0x22c8, 0x22d4, 0x22d4, 0x22e2, 0x22e2,
+	0x22f0, 0x22f0, 0x2300, 0x2300, 0x230e, 0x230e, 0x231e, 0x231e,
+	0x232e, 0x232e, 0x2340, 0x2340, 0x234e, 0x234e, 0x235e, 0x235e,
+	0x2380, 0x2380, 0x23a2, 0x23a2, 0x236e, 0x236e, 0x2391, 0x2391,
+	0x23b1, 0x23b1, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e, 0x224e,
+	0x224e, 0x224e, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x195f, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1745, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1745,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x195f, 0x080c, 0x1745, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x195f, 0x080c, 0x1745, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1787,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f,
+	0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6,
+	0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f, 0x080c, 0x1787,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f,
+	0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f,
+	0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4, 0xa001, 0x0cf0,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x0fcc, 0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6,
+	0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f, 0x080c, 0x0fcc,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1745, 0x080c, 0x0fcc, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x195f, 0x080c, 0x0fcc, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x195f, 0x080c, 0x1745, 0x080c, 0x0fcc, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1745, 0x080c, 0x0fcc, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x0fcc, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x195f,
+	0x080c, 0x1745, 0x080c, 0x0fcc, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1d54, 0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6,
+	0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54, 0x080c, 0x195f,
+	0x0804, 0x23c4, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1d54, 0x080c, 0x1745, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1d54, 0x080c, 0x195f, 0x080c, 0x1745, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1d54, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x195f, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x195f, 0x080c, 0x1745, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1d54, 0x080c, 0x0fcc, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x195f, 0x080c, 0x0fcc, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x1745, 0x080c, 0x0fcc, 0x0804, 0x23c4, 0x0106, 0x0006,
+	0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, 0x1d54,
+	0x080c, 0x195f, 0x080c, 0x0fcc, 0x080c, 0x1787, 0x0804, 0x23c4,
+	0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156,
+	0x080c, 0x1d54, 0x080c, 0x195f, 0x080c, 0x1745, 0x080c, 0x0fcc,
+	0x0498, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146,
+	0x0156, 0x080c, 0x1d54, 0x080c, 0x1745, 0x080c, 0x0fcc, 0x080c,
+	0x1787, 0x0410, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136,
+	0x0146, 0x0156, 0x080c, 0x1d54, 0x080c, 0x0fcc, 0x080c, 0x1787,
+	0x0098, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146,
+	0x0156, 0x080c, 0x1d54, 0x080c, 0x195f, 0x080c, 0x1745, 0x080c,
+	0x0fcc, 0x080c, 0x1787, 0x0000, 0x015e, 0x014e, 0x013e, 0x01de,
+	0x01ce, 0x012e, 0x000e, 0x010e, 0x000d, 0x00c6, 0x0026, 0x0046,
+	0x2021, 0x0000, 0x080c, 0x4de0, 0x1904, 0x24aa, 0x72cc, 0x2001,
+	0x128f, 0x2004, 0x9005, 0x1110, 0xd29c, 0x0148, 0xd284, 0x1138,
+	0xd2bc, 0x1904, 0x24aa, 0x080c, 0x24ae, 0x0804, 0x24aa, 0xd2cc,
+	0x1904, 0x24aa, 0x080c, 0x5745, 0x1120, 0x709b, 0xffff, 0x0804,
+	0x24aa, 0xd294, 0x0120, 0x709b, 0xffff, 0x0804, 0x24aa, 0x2001,
+	0x1114, 0x203c, 0x7284, 0xd284, 0x0904, 0x244c, 0xd28c, 0x1904,
+	0x244c, 0x0036, 0x7398, 0x938e, 0xffff, 0x1110, 0x2019, 0x0001,
+	0x8314, 0x92e0, 0x1580, 0x2c04, 0x938c, 0x0001, 0x0120, 0x9084,
+	0xff00, 0x8007, 0x0010, 0x9084, 0x00ff, 0x970e, 0x0560, 0x908e,
+	0x0000, 0x0548, 0x908e, 0x00ff, 0x1150, 0x7230, 0xd284, 0x1538,
+	0x7284, 0xc28d, 0x7286, 0x709b, 0xffff, 0x003e, 0x0428, 0x2009,
+	0x0000, 0x080c, 0x1c69, 0x080c, 0x4b03, 0x11b8, 0x6004, 0x9084,
+	0x00ff, 0x9086, 0x0006, 0x1150, 0x7030, 0xd08c, 0x0118, 0x6000,
+	0xd0bc, 0x0120, 0x080c, 0x24c1, 0x0140, 0x0028, 0x080c, 0x25ec,
+	0x080c, 0x24ef, 0x0110, 0x8318, 0x0818, 0x739a, 0x0010, 0x709b,
+	0xffff, 0x003e, 0x0804, 0x24aa, 0x9780, 0x26c1, 0x203d, 0x97bc,
+	0xff00, 0x873f, 0x2041, 0x007e, 0x7098, 0x9096, 0xffff, 0x1120,
+	0x2009, 0x0000, 0x28a8, 0x0050, 0x9812, 0x0220, 0x2008, 0x9802,
+	0x20a8, 0x0020, 0x709b, 0xffff, 0x0804, 0x24aa, 0x2700, 0x0156,
+	0x0016, 0x9106, 0x05a0, 0xc484, 0x080c, 0x4b58, 0x0120, 0x080c,
+	0x4b03, 0x15a8, 0x0008, 0xc485, 0x6004, 0x9084, 0x00ff, 0x9086,
+	0x0006, 0x1130, 0x7030, 0xd08c, 0x01e8, 0x6000, 0xd0bc, 0x11d0,
+	0x7284, 0xd28c, 0x0188, 0x6004, 0x9084, 0x00ff, 0x9082, 0x0006,
+	0x02b0, 0xd484, 0x1118, 0x080c, 0x4b20, 0x0028, 0x080c, 0x2676,
+	0x0170, 0x080c, 0x26a3, 0x0058, 0x080c, 0x25ec, 0x080c, 0x24ef,
+	0x0170, 0x0028, 0x080c, 0x2676, 0x0110, 0x0419, 0x0140, 0x001e,
+	0x8108, 0x015e, 0x1f04, 0x2466, 0x709b, 0xffff, 0x0018, 0x001e,
+	0x015e, 0x719a, 0x004e, 0x002e, 0x00ce, 0x0005, 0x00c6, 0x0016,
+	0x709b, 0x0001, 0x2009, 0x007e, 0x080c, 0x4b03, 0x1138, 0x080c,
+	0x25ec, 0x04a9, 0x0118, 0x70cc, 0xc0bd, 0x70ce, 0x001e, 0x00ce,
+	0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x2c68, 0x2001, 0x1157,
+	0x2004, 0x9084, 0x00ff, 0x6842, 0x080c, 0x984d, 0x01d8, 0x2d00,
+	0x6012, 0x080c, 0x99cc, 0x6023, 0x0001, 0x2001, 0x0000, 0x080c,
+	0x4aa1, 0x2001, 0x0000, 0x080c, 0x4ab3, 0x0126, 0x2091, 0x8000,
+	0x7094, 0x8000, 0x7096, 0x012e, 0x2009, 0x0004, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005, 0x0016,
+	0x0076, 0x00d6, 0x00c6, 0x2c68, 0x2001, 0x1157, 0x2004, 0x9084,
+	0x00ff, 0x6842, 0x080c, 0x984d, 0x0550, 0x2d00, 0x6012, 0x6800,
+	0xc0c4, 0x6802, 0x68a0, 0x9086, 0x007e, 0x0140, 0x6804, 0x9084,
+	0x00ff, 0x9086, 0x0006, 0x1110, 0x080c, 0x25ad, 0x080c, 0x99cc,
+	0x6023, 0x0001, 0x2001, 0x0000, 0x080c, 0x4aa1, 0x2001, 0x0002,
+	0x080c, 0x4ab3, 0x0126, 0x2091, 0x8000, 0x7094, 0x8000, 0x7096,
+	0x012e, 0x2009, 0x0002, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x00ce,
+	0x00de, 0x007e, 0x001e, 0x0005, 0x00c6, 0x0026, 0x2009, 0x0080,
+	0x080c, 0x4b03, 0x1120, 0x0031, 0x0110, 0x70d3, 0xffff, 0x002e,
+	0x00ce, 0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x2c68, 0x080c,
+	0x7ec8, 0x01d8, 0x2d00, 0x6012, 0x080c, 0x99cc, 0x6023, 0x0001,
+	0x2001, 0x0000, 0x080c, 0x4aa1, 0x2001, 0x0002, 0x080c, 0x4ab3,
+	0x0126, 0x2091, 0x8000, 0x70d4, 0x8000, 0x70d6, 0x012e, 0x2009,
+	0x0002, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x00ce, 0x00de, 0x007e,
+	0x001e, 0x0005, 0x00c6, 0x00d6, 0x0126, 0x2091, 0x8000, 0x2009,
+	0x007f, 0x080c, 0x4b03, 0x1190, 0x2c68, 0x080c, 0x7ec8, 0x0170,
+	0x2d00, 0x6012, 0x6316, 0x6023, 0x0001, 0x620a, 0x080c, 0x99cc,
+	0x2009, 0x0022, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x012e, 0x00de,
+	0x00ce, 0x0005, 0x00e6, 0x00c6, 0x0066, 0x0036, 0x0026, 0x080c,
+	0x69d6, 0x080c, 0x697f, 0x080c, 0x89dd, 0x2130, 0x81ff, 0x0128,
+	0x20a9, 0x007e, 0x2009, 0x0000, 0x0020, 0x20a9, 0x007f, 0x2009,
+	0x0000, 0x0016, 0x080c, 0x4b58, 0x1110, 0x080c, 0x472d, 0x001e,
+	0x8108, 0x1f04, 0x2599, 0x86ff, 0x1110, 0x080c, 0x0a33, 0x002e,
+	0x003e, 0x006e, 0x00ce, 0x00ee, 0x0005, 0x00e6, 0x00c6, 0x0036,
+	0x0026, 0x0016, 0x6210, 0x2270, 0x72a0, 0x0026, 0x2019, 0x0029,
+	0x080c, 0x69ca, 0x0076, 0x2039, 0x0000, 0x080c, 0x68fe, 0x2c08,
+	0x080c, 0xa85f, 0x007e, 0x001e, 0x2e60, 0x6210, 0x6314, 0x080c,
+	0x472d, 0x6212, 0x6316, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee,
+	0x0005, 0x00e6, 0x0006, 0x6010, 0x9080, 0x0028, 0x2004, 0x9086,
+	0x0080, 0x0150, 0x2071, 0x1100, 0x7094, 0x9005, 0x0110, 0x8001,
+	0x7096, 0x000e, 0x00ee, 0x0005, 0x2071, 0x1100, 0x70d4, 0x9005,
+	0x0dc0, 0x8001, 0x70d6, 0x0ca8, 0x6000, 0xc08c, 0x6002, 0x0005,
+	0x00f6, 0x00e6, 0x00c6, 0x0036, 0x0026, 0x0016, 0x0156, 0x2178,
+	0x81ff, 0x1118, 0x20a9, 0x0001, 0x0098, 0x2001, 0x1153, 0x2004,
+	0xd0c4, 0x0150, 0xd0a4, 0x0140, 0x9006, 0x0046, 0x2020, 0x2009,
+	0x002d, 0x080c, 0xaaca, 0x004e, 0x20a9, 0x00ff, 0x2011, 0x0000,
+	0x0026, 0x928e, 0x007e, 0x0904, 0x2655, 0x928e, 0x007f, 0x05e8,
+	0x928e, 0x0080, 0x05d0, 0x9288, 0x1000, 0x210c, 0x81ff, 0x05a8,
+	0x8fff, 0x1148, 0x2001, 0x12ae, 0x0006, 0x2003, 0x0001, 0x04c9,
+	0x000e, 0x2003, 0x0000, 0x00c6, 0x2160, 0x2001, 0x0001, 0x080c,
+	0x4dea, 0x00ce, 0x2019, 0x0029, 0x080c, 0x69ca, 0x0076, 0x2039,
+	0x0000, 0x080c, 0x68fe, 0x00c6, 0x0026, 0x2160, 0x6204, 0x9294,
+	0x00ff, 0x9286, 0x0006, 0x1118, 0x6007, 0x0404, 0x0028, 0x2001,
+	0x0004, 0x8007, 0x9215, 0x6206, 0x002e, 0x00ce, 0x0016, 0x2c08,
+	0x080c, 0xa85f, 0x001e, 0x007e, 0x2160, 0x002e, 0x8210, 0x1f04,
+	0x2610, 0x015e, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee, 0x00fe,
+	0x0005, 0x0046, 0x0026, 0x0016, 0x2001, 0x1153, 0x2004, 0xd0c4,
+	0x0148, 0xd0a4, 0x0138, 0x9006, 0x2220, 0x8427, 0x2009, 0x0029,
+	0x080c, 0xaaca, 0x001e, 0x002e, 0x004e, 0x0005, 0x0016, 0x0026,
+	0x0036, 0x00c6, 0x7284, 0x82ff, 0x01f8, 0x2011, 0x1153, 0x2214,
+	0xd2ac, 0x11d0, 0x2100, 0x080c, 0x1c7d, 0x81ff, 0x01b8, 0x2019,
+	0x0001, 0x8314, 0x92e0, 0x1580, 0x2c04, 0xd384, 0x0120, 0x9084,
+	0xff00, 0x8007, 0x0010, 0x9084, 0x00ff, 0x9116, 0x0138, 0x9096,
+	0x00ff, 0x0110, 0x8318, 0x0c68, 0x9085, 0x0001, 0x00ce, 0x003e,
+	0x002e, 0x001e, 0x0005, 0x0016, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x9180, 0x1000, 0x2004, 0x9065, 0x0158, 0x0016, 0x00c6, 0x2061,
+	0x135e, 0x001e, 0x6112, 0x080c, 0x25ad, 0x001e, 0x080c, 0x4b20,
+	0x012e, 0x00ce, 0x001e, 0x0005, 0x2001, 0x1133, 0x2004, 0xd0cc,
+	0x0005, 0x7eef, 0x7de8, 0x7ce4, 0x80e2, 0x7be1, 0x80e0, 0x80dc,
+	0x80da, 0x7ad9, 0x80d6, 0x80d5, 0x80d4, 0x80d3, 0x80d2, 0x80d1,
+	0x79ce, 0x78cd, 0x80cc, 0x80cb, 0x80ca, 0x80c9, 0x80c7, 0x80c6,
+	0x77c5, 0x76c3, 0x80bc, 0x80ba, 0x75b9, 0x80b6, 0x74b5, 0x73b4,
+	0x72b3, 0x80b2, 0x80b1, 0x80ae, 0x71ad, 0x80ac, 0x70ab, 0x6faa,
+	0x6ea9, 0x80a7, 0x6da6, 0x6ca5, 0x6ba3, 0x6a9f, 0x699e, 0x689d,
+	0x809b, 0x8098, 0x6797, 0x6690, 0x658f, 0x6488, 0x6384, 0x6282,
+	0x8081, 0x8080, 0x617c, 0x607a, 0x8079, 0x5f76, 0x8075, 0x8074,
+	0x8073, 0x8072, 0x8071, 0x806e, 0x5e6d, 0x806c, 0x5d6b, 0x5c6a,
+	0x5b69, 0x8067, 0x5a66, 0x5965, 0x5863, 0x575c, 0x565a, 0x5559,
+	0x8056, 0x8055, 0x5454, 0x5353, 0x5252, 0x5151, 0x504e, 0x4f4d,
+	0x804c, 0x804b, 0x4e4a, 0x4d49, 0x8047, 0x4c46, 0x8045, 0x8043,
+	0x803c, 0x803a, 0x8039, 0x8036, 0x4b35, 0x8034, 0x4a33, 0x4932,
+	0x4831, 0x802e, 0x472d, 0x462c, 0x452b, 0x442a, 0x4329, 0x4227,
+	0x8026, 0x8025, 0x4123, 0x401f, 0x3f1e, 0x3e1d, 0x3d1b, 0x3c18,
+	0x8017, 0x8010, 0x3b0f, 0x3a08, 0x8004, 0x3902, 0x8001, 0x8000,
+	0x8000, 0x3800, 0x3700, 0x3600, 0x8000, 0x3500, 0x8000, 0x8000,
+	0x8000, 0x3400, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x3300, 0x3200, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x3100, 0x3000, 0x8000, 0x8000, 0x2f00, 0x8000, 0x2e00, 0x2d00,
+	0x2c00, 0x8000, 0x8000, 0x8000, 0x2b00, 0x8000, 0x2a00, 0x2900,
+	0x2800, 0x8000, 0x2700, 0x2600, 0x2500, 0x2400, 0x2300, 0x2200,
+	0x8000, 0x8000, 0x2100, 0x2000, 0x1f00, 0x1e00, 0x1d00, 0x1c00,
+	0x8000, 0x8000, 0x1b00, 0x1a00, 0x8000, 0x1900, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x1800, 0x8000, 0x1700, 0x1600,
+	0x1500, 0x8000, 0x1400, 0x1300, 0x1200, 0x1100, 0x1000, 0x0f00,
+	0x8000, 0x8000, 0x0e00, 0x0d00, 0x0c00, 0x0b00, 0x0a00, 0x0900,
+	0x8000, 0x8000, 0x0800, 0x0700, 0x8000, 0x0600, 0x8000, 0x8000,
+	0x8000, 0x0500, 0x0400, 0x0300, 0x8000, 0x0200, 0x8000, 0x8000,
+	0x8000, 0x0100, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x0000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+	0x8000, 0x2071, 0x1193, 0x7003, 0x0002, 0x9006, 0x7012, 0x7016,
+	0x703a, 0x703e, 0x7033, 0x11a3, 0x7037, 0x11a3, 0x7007, 0x0001,
+	0x2061, 0x11e3, 0x6003, 0x0002, 0x0005, 0x1004, 0x27e4, 0x0e04,
+	0x27e4, 0x2071, 0x1193, 0x2b78, 0x2a60, 0x7880, 0x908e, 0x0069,
+	0x1904, 0x28cc, 0x0804, 0x2860, 0x0005, 0x2071, 0x1193, 0x7004,
+	0x0002, 0x27ed, 0x27ee, 0x27f5, 0x2806, 0x0005, 0x1004, 0x27f4,
+	0x0e04, 0x27f4, 0x2b78, 0x00e8, 0x0005, 0x2b78, 0x2061, 0x11e3,
+	0x6008, 0x908e, 0x0100, 0x0128, 0x9086, 0x0200, 0x0904, 0x28c6,
+	0x0005, 0x7014, 0x2068, 0x2a60, 0x7018, 0x0807, 0x7010, 0x2068,
+	0x6864, 0x9086, 0x0103, 0x0108, 0x0005, 0x2a60, 0x2b78, 0x7018,
+	0x0807, 0x2a60, 0x7880, 0x908a, 0x0040, 0x1210, 0x61c0, 0x0042,
+	0x2100, 0x908a, 0x003f, 0x1a04, 0x28c3, 0x61c0, 0x0804, 0x2860,
+	0x28a2, 0x28d2, 0x28dc, 0x28e0, 0x28ea, 0x28f0, 0x28f4, 0x2904,
+	0x2907, 0x2911, 0x2916, 0x291b, 0x2926, 0x2931, 0x2940, 0x294f,
+	0x295d, 0x2974, 0x298f, 0x2a10, 0x2a15, 0x2a3e, 0x2a8b, 0x2a9c,
+	0x2aba, 0x28c3, 0x28c3, 0x28c3, 0x2af1, 0x2b10, 0x2b19, 0x2b4c,
+	0x2b52, 0x28c3, 0x2b7b, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3,
+	0x2b86, 0x2b90, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3,
+	0x28c3, 0x28c3, 0x2b98, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3,
+	0x2bb5, 0x2bdb, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3,
+	0x0002, 0x2c05, 0x2c59, 0x2cb4, 0x2cc7, 0x28c3, 0x2ce1, 0x3102,
+	0x3b4e, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x28c3,
+	0x28c3, 0x2911, 0x2916, 0x3104, 0x28c3, 0x3116, 0x3bde, 0x3c39,
+	0x3c9f, 0x28c3, 0x3d00, 0x3d2a, 0x3d4f, 0x3e32, 0x3d81, 0x3ddc,
+	0x28c3, 0x311a, 0x32a9, 0x32bf, 0x32dd, 0x3342, 0x33a8, 0x33b3,
+	0x33ea, 0x33f9, 0x3408, 0x340b, 0x3433, 0x3486, 0x3502, 0x350f,
+	0x3612, 0x3732, 0x375b, 0x3856, 0x3878, 0x3884, 0x38bd, 0x398a,
+	0x28c3, 0x28c3, 0x28c3, 0x28c3, 0x39f2, 0x3a0d, 0x3a85, 0x3b3f,
+	0x713c, 0x0000, 0x2021, 0x4000, 0x080c, 0x37b8, 0x0126, 0x2091,
+	0x8000, 0x0e04, 0x28ac, 0x0010, 0x012e, 0x0cc0, 0x7c36, 0x9486,
+	0x4000, 0x0118, 0x7833, 0x0011, 0x0010, 0x7833, 0x0010, 0x7c82,
+	0x7986, 0x7a8a, 0x7b8e, 0x2091, 0x4080, 0x7007, 0x0001, 0x2091,
+	0x5000, 0x012e, 0x0005, 0x2021, 0x4001, 0x08f0, 0x2021, 0x4002,
+	0x08d8, 0x2021, 0x4003, 0x08c0, 0x2021, 0x4005, 0x08a8, 0x2021,
+	0x4006, 0x0890, 0x2039, 0x0001, 0x902e, 0x2520, 0x7b88, 0x7a8c,
+	0x7884, 0x7990, 0x0804, 0x37c5, 0x7883, 0x0004, 0x7884, 0x0807,
+	0x2039, 0x0001, 0x902e, 0x2520, 0x7b88, 0x7a8c, 0x7884, 0x7990,
+	0x0804, 0x37c8, 0x7984, 0x7888, 0x2114, 0x200a, 0x0804, 0x28a2,
+	0x7984, 0x2114, 0x0804, 0x28a2, 0x20e1, 0x0000, 0x2099, 0x0021,
+	0x20e9, 0x0000, 0x20a1, 0x0021, 0x20a9, 0x001f, 0x4003, 0x7984,
+	0x7a88, 0x7b8c, 0x0804, 0x28a2, 0x7884, 0x2060, 0x04d8, 0x2009,
+	0x0003, 0x2011, 0x0000, 0x2019, 0x0018, 0x789b, 0x0017, 0x0804,
+	0x28a2, 0x2039, 0x0001, 0x7d98, 0x7c9c, 0x0800, 0x2039, 0x0001,
+	0x7d98, 0x7c9c, 0x0848, 0x79a0, 0x9182, 0x0040, 0x0210, 0x0804,
+	0x28cf, 0x2138, 0x7d98, 0x7c9c, 0x0804, 0x28d6, 0x79a0, 0x9182,
+	0x0040, 0x0210, 0x0804, 0x28cf, 0x2138, 0x7d98, 0x7c9c, 0x0804,
+	0x28e4, 0x79a0, 0x9182, 0x0040, 0x0210, 0x0804, 0x28cf, 0x21e8,
+	0x7984, 0x7888, 0x20a9, 0x0001, 0x21a0, 0x4004, 0x0804, 0x28a2,
+	0x2061, 0x0800, 0xe10c, 0x9006, 0x2c15, 0x9200, 0x8c60, 0x8109,
+	0x1dd8, 0x2010, 0x9005, 0x0904, 0x28a2, 0x0804, 0x28c9, 0x79a0,
+	0x9182, 0x0040, 0x0210, 0x0804, 0x28cf, 0x21e0, 0x20a9, 0x0001,
+	0x7984, 0x2198, 0x4012, 0x0804, 0x28a2, 0x2069, 0x1152, 0x7884,
+	0x7990, 0x911a, 0x1a04, 0x28cf, 0x8019, 0x0904, 0x28cf, 0x684a,
+	0x6942, 0x788c, 0x6852, 0x7888, 0x6856, 0x9006, 0x685a, 0x685e,
+	0x080c, 0x5a12, 0x0804, 0x28a2, 0x2069, 0x1152, 0x7884, 0x7994,
+	0x911a, 0x1a04, 0x28cf, 0x8019, 0x0904, 0x28cf, 0x684e, 0x6946,
+	0x788c, 0x6862, 0x7888, 0x6866, 0x9006, 0x686a, 0x686e, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x4e87, 0x012e, 0x0804, 0x28a2, 0x902e,
+	0x2520, 0x81ff, 0x1904, 0x28cc, 0x7984, 0x7b88, 0x7a8c, 0x20a9,
+	0x0005, 0x20e9, 0x0001, 0x20a1, 0x119a, 0x4101, 0x080c, 0x3784,
+	0x0904, 0x28cc, 0x2009, 0x0020, 0x2039, 0x0001, 0x080c, 0x37c5,
+	0x701b, 0x29ab, 0x0005, 0x6864, 0x2008, 0x9084, 0x00ff, 0x9096,
+	0x0011, 0x0120, 0x9096, 0x0019, 0x1904, 0x28cc, 0x810f, 0x918c,
+	0x00ff, 0x0904, 0x28cc, 0x710e, 0x700c, 0x8001, 0x0538, 0x700e,
+	0x080c, 0x3784, 0x0904, 0x28cc, 0x2009, 0x0020, 0x2061, 0x11e3,
+	0x6228, 0x632c, 0x6430, 0x6534, 0x9290, 0x0040, 0x9399, 0x0000,
+	0x94a1, 0x0000, 0x95a9, 0x0000, 0x2039, 0x0001, 0x080c, 0x37c5,
+	0x701b, 0x29db, 0x0005, 0x6864, 0x9084, 0x00ff, 0x9096, 0x0002,
+	0x0120, 0x9096, 0x000a, 0x1904, 0x28cc, 0x08b0, 0x7010, 0x2068,
+	0x6868, 0xc0fd, 0x686a, 0x080c, 0x4a18, 0x1128, 0x7007, 0x0003,
+	0x701b, 0x29f5, 0x0005, 0x080c, 0x52a0, 0x0126, 0x2091, 0x8000,
+	0x20a9, 0x0005, 0x20e1, 0x0001, 0x2099, 0x119a, 0x400a, 0x2100,
+	0x9210, 0x9399, 0x0000, 0x94a1, 0x0000, 0x95a9, 0x0000, 0x9d80,
+	0x0019, 0x2009, 0x0020, 0x012e, 0x2039, 0x0001, 0x0804, 0x37c8,
+	0x61a8, 0x7884, 0x60aa, 0x0804, 0x28a2, 0x2091, 0x8000, 0x7837,
+	0x4000, 0x7833, 0x0010, 0x7883, 0x4000, 0x7887, 0x4953, 0x788b,
+	0x5020, 0x788f, 0x2020, 0x2009, 0x017f, 0x2104, 0x7892, 0x3f00,
+	0x7896, 0x2061, 0x0100, 0x6200, 0x2061, 0x0200, 0x603c, 0x8007,
+	0x9205, 0x789a, 0x2009, 0x04fd, 0x2104, 0x789e, 0x2091, 0x5000,
+	0x2091, 0x4080, 0x2071, 0x0080, 0x0804, 0x0427, 0x81ff, 0x1904,
+	0x28cc, 0x7984, 0x810f, 0x918c, 0x00ff, 0x080c, 0x4b58, 0x1904,
+	0x28cf, 0x7e98, 0x9684, 0x3fff, 0x9082, 0x4000, 0x0210, 0x0804,
+	0x28cf, 0x7c88, 0x7d8c, 0x080c, 0x4ca3, 0x080c, 0x4c75, 0x0000,
+	0x1518, 0x2061, 0x15c0, 0x0126, 0x2091, 0x8000, 0x6000, 0x9086,
+	0x0000, 0x0148, 0x6014, 0x906d, 0x0130, 0x686c, 0x9406, 0x1118,
+	0x6870, 0x9506, 0x0150, 0x012e, 0x9ce0, 0x0018, 0x2001, 0x1116,
+	0x2004, 0x9c02, 0x1a04, 0x28cc, 0x0c30, 0x080c, 0x92a4, 0x012e,
+	0x0904, 0x28cc, 0x0804, 0x28a2, 0x900e, 0x2001, 0x0005, 0x080c,
+	0x52a0, 0x0126, 0x2091, 0x8000, 0x080c, 0x9849, 0x080c, 0x50a5,
+	0x012e, 0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x3799,
+	0x0904, 0x28cf, 0x080c, 0x4c17, 0x0904, 0x28cc, 0x080c, 0x4ca9,
+	0x0904, 0x28cc, 0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc, 0x080c,
+	0x37a9, 0x0904, 0x28cf, 0x080c, 0x4cf1, 0x0904, 0x28cc, 0x2019,
+	0x0005, 0x080c, 0x4cc4, 0x0904, 0x28cc, 0x7888, 0x908a, 0x1000,
+	0x1a04, 0x28cf, 0x8003, 0x800b, 0x810b, 0x9108, 0x080c, 0x6567,
+	0x0804, 0x28a2, 0x0126, 0x2091, 0x8000, 0x81ff, 0x0118, 0x2009,
+	0x0001, 0x0448, 0x2029, 0x00ff, 0x644c, 0x2400, 0x9506, 0x01f0,
+	0x2508, 0x080c, 0x4b58, 0x11d0, 0x080c, 0x4cf1, 0x1128, 0x2009,
+	0x0002, 0x62b0, 0x2518, 0x00b8, 0x2019, 0x0004, 0x080c, 0x4cc4,
+	0x1118, 0x2009, 0x0006, 0x0078, 0x7884, 0x908a, 0x1000, 0x1270,
+	0x8003, 0x800b, 0x810b, 0x9108, 0x080c, 0x6567, 0x8529, 0x1ae8,
+	0x012e, 0x0804, 0x28a2, 0x012e, 0x0804, 0x28cc, 0x012e, 0x0804,
+	0x28cf, 0x080c, 0x3799, 0x0904, 0x28cf, 0x080c, 0x4c17, 0x0904,
+	0x28cc, 0x62a0, 0x2019, 0x0005, 0x00c6, 0x2061, 0x0000, 0x080c,
+	0x69ca, 0x0076, 0x2039, 0x0000, 0x080c, 0x68fe, 0x2009, 0x0000,
+	0x080c, 0xa85f, 0x007e, 0x00ce, 0x080c, 0x4ca3, 0x0804, 0x28a2,
+	0x080c, 0x3799, 0x0904, 0x28cf, 0x080c, 0x4ca3, 0x2208, 0x0804,
+	0x28a2, 0x0156, 0x00d6, 0x00e6, 0x2069, 0x1228, 0x6810, 0x6914,
+	0x910a, 0x1210, 0x2009, 0x0000, 0x6816, 0x2011, 0x0000, 0x2019,
+	0x0000, 0x20a9, 0x007e, 0x2069, 0x1000, 0x2d04, 0x9075, 0x0118,
+	0x704c, 0x0059, 0x9210, 0x8d68, 0x1f04, 0x2b2d, 0x2300, 0x9218,
+	0x00ee, 0x00de, 0x015e, 0x0804, 0x28a2, 0x00f6, 0x0016, 0x907d,
+	0x0140, 0x2001, 0x0000, 0x8000, 0x2f0c, 0x81ff, 0x0110, 0x2178,
+	0x0cd0, 0x001e, 0x00fe, 0x0005, 0x2069, 0x1228, 0x6910, 0x62ac,
+	0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc, 0x614c, 0x9190, 0x26c1,
+	0x2215, 0x9294, 0x00ff, 0x636c, 0x83ff, 0x0108, 0x6270, 0x67cc,
+	0xd79c, 0x0118, 0x2031, 0x0001, 0x0090, 0xd7ac, 0x0118, 0x2031,
+	0x0003, 0x0068, 0xd7a4, 0x0118, 0x2031, 0x0002, 0x0040, 0x080c,
+	0x5745, 0x1118, 0x2031, 0x0004, 0x0010, 0x2031, 0x0000, 0x7e9a,
+	0x7f9e, 0x0804, 0x28a2, 0x613c, 0x6240, 0x2019, 0x12a6, 0x231c,
+	0x2001, 0x12a7, 0x2004, 0x789a, 0x0804, 0x28a2, 0x0126, 0x2091,
+	0x8000, 0x6134, 0x9006, 0x2010, 0x2018, 0x012e, 0x0804, 0x28a2,
+	0x080c, 0x37a9, 0x0904, 0x28cf, 0x6244, 0x6338, 0x0804, 0x28a2,
+	0x613c, 0x6240, 0x7884, 0x603e, 0x7b88, 0x6342, 0x2069, 0x1152,
+	0x831f, 0x9305, 0x6816, 0x788c, 0x2069, 0x12a6, 0x2d1c, 0x206a,
+	0x7e98, 0x9682, 0x0014, 0x1210, 0x2031, 0x07d0, 0x2069, 0x12a7,
+	0x2d04, 0x266a, 0x789a, 0x0804, 0x28a2, 0x0126, 0x2091, 0x8000,
+	0x7884, 0x6036, 0xd0c4, 0x01a8, 0x00d6, 0x78a8, 0x2009, 0x12bd,
+	0x200a, 0x78ac, 0x2011, 0x12be, 0x2012, 0x2069, 0x0100, 0x6838,
+	0x9086, 0x0007, 0x1118, 0x2214, 0x6a5a, 0x0010, 0x210c, 0x695a,
+	0x00de, 0x7884, 0xd0b4, 0x0120, 0x3b00, 0x9084, 0xff3f, 0x20d8,
+	0x012e, 0x0804, 0x28a2, 0x7898, 0x9005, 0x01a8, 0x7888, 0x9025,
+	0x0904, 0x28cf, 0x788c, 0x902d, 0x0904, 0x28cf, 0x900e, 0x080c,
+	0x4b58, 0x1120, 0x6244, 0x6338, 0x6446, 0x653a, 0x9186, 0x00ff,
+	0x0190, 0x8108, 0x0ca0, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x7888,
+	0x900d, 0x0904, 0x28cf, 0x788c, 0x9005, 0x0904, 0x28cf, 0x6244,
+	0x6146, 0x6338, 0x603a, 0x0804, 0x28a2, 0x2001, 0x1100, 0x2004,
+	0x9086, 0x0003, 0x1904, 0x28cc, 0x00c6, 0x2061, 0x0100, 0x7984,
+	0x810f, 0x918c, 0x00ff, 0x9196, 0x00ff, 0x1130, 0x2001, 0x1114,
+	0x2004, 0x9085, 0xff00, 0x0078, 0x9182, 0x007f, 0x16a0, 0x9188,
+	0x26c1, 0x210d, 0x918c, 0x00ff, 0x2001, 0x1114, 0x2004, 0x9116,
+	0x0550, 0x810f, 0x9105, 0x0126, 0x2091, 0x8000, 0x0006, 0x080c,
+	0x7ec8, 0x000e, 0x01e0, 0x6012, 0x600b, 0xbc09, 0x6023, 0x0001,
+	0x080c, 0x3784, 0x01d8, 0x6867, 0x0000, 0x7007, 0x0003, 0x6833,
+	0x0000, 0x6868, 0xc0fd, 0x686a, 0x701b, 0x2cad, 0x2d00, 0x6016,
+	0x2009, 0x0032, 0x080c, 0x7f4e, 0x012e, 0x00ce, 0x0005, 0x012e,
+	0x00ce, 0x0804, 0x28cc, 0x00ce, 0x0804, 0x28cf, 0x080c, 0x7f1e,
+	0x0cb0, 0x2001, 0x1100, 0x2004, 0x9086, 0x0003, 0x1904, 0x28cc,
+	0x00c6, 0x2061, 0x0100, 0x7984, 0x810f, 0x918c, 0x00ff, 0x9196,
+	0x00ff, 0x1130, 0x2001, 0x1114, 0x2004, 0x9085, 0xff00, 0x0078,
+	0x9182, 0x007f, 0x16a0, 0x9188, 0x26c1, 0x210d, 0x918c, 0x00ff,
+	0x2001, 0x1114, 0x2004, 0x9116, 0x0550, 0x810f, 0x9105, 0x0126,
+	0x2091, 0x8000, 0x0006, 0x080c, 0x7ec8, 0x000e, 0x01e0, 0x6012,
+	0x600b, 0xbc05, 0x6023, 0x0001, 0x080c, 0x3784, 0x01d8, 0x6867,
+	0x0000, 0x7007, 0x0003, 0x6833, 0x0000, 0x6868, 0xc0fd, 0x686a,
+	0x701b, 0x2cad, 0x2d00, 0x6016, 0x2009, 0x0032, 0x080c, 0x7f4e,
+	0x012e, 0x00ce, 0x0005, 0x012e, 0x00ce, 0x0804, 0x28cc, 0x00ce,
+	0x0804, 0x28cf, 0x080c, 0x7f1e, 0x0cb0, 0x6830, 0x9086, 0x0100,
+	0x0904, 0x28cc, 0x0804, 0x28a2, 0x2061, 0x1329, 0x0126, 0x2091,
+	0x8000, 0x6000, 0xd084, 0x0140, 0x6104, 0x6208, 0x2019, 0x1111,
+	0x231c, 0x012e, 0x0804, 0x28a2, 0x012e, 0x0804, 0x28cf, 0x81ff,
+	0x1904, 0x28cc, 0x080c, 0x5745, 0x0904, 0x28cc, 0x0126, 0x2091,
+	0x8000, 0x6244, 0x6064, 0x9202, 0x0248, 0x9085, 0x0001, 0x080c,
+	0x1cb3, 0x080c, 0x4016, 0x012e, 0x0804, 0x28a2, 0x012e, 0x0804,
+	0x28cf, 0x0126, 0x2091, 0x8000, 0x81ff, 0x0148, 0x080c, 0x204d,
+	0x1130, 0x9006, 0x080c, 0x1faf, 0x9006, 0x080c, 0x1f92, 0x7884,
+	0x9084, 0x0007, 0x0002, 0x2cfe, 0x2d07, 0x2d10, 0x2cfb, 0x2cfb,
+	0x2cfb, 0x2cfb, 0x2cfb, 0x012e, 0x0804, 0x28cf, 0x2009, 0x0114,
+	0x2104, 0x9085, 0x0800, 0x200a, 0x080c, 0x2e61, 0x0080, 0x2009,
+	0x0114, 0x2104, 0x9085, 0x4000, 0x200a, 0x080c, 0x2e61, 0x0038,
+	0x81ff, 0x0128, 0x012e, 0x2021, 0x400b, 0x0804, 0x28a4, 0x0086,
+	0x0096, 0x00a6, 0x00b6, 0x00c6, 0x00d6, 0x00e6, 0x00f6, 0x2009,
+	0x0101, 0x210c, 0x0016, 0x2001, 0x0032, 0x2034, 0x2001, 0x0033,
+	0x202c, 0x9006, 0x2048, 0x2050, 0x2058, 0x080c, 0x3098, 0x080c,
+	0x2ffe, 0x903e, 0x2720, 0x00f6, 0x00e6, 0x00c6, 0x2d60, 0x2071,
+	0x131f, 0x2079, 0x0090, 0x00d6, 0x2069, 0x0000, 0x6884, 0xd0b4,
+	0x0140, 0x2001, 0x0035, 0x2004, 0x780e, 0x2001, 0x0034, 0x2004,
+	0x780a, 0x00de, 0x2011, 0x0001, 0x080c, 0x2faa, 0x080c, 0x2faa,
+	0x00ce, 0x00ee, 0x00fe, 0x080c, 0x2f03, 0x080c, 0x2fd2, 0x080c,
+	0x2f4f, 0x080c, 0x2ec8, 0x080c, 0x2ef9, 0x00f6, 0x2079, 0x0100,
+	0x7824, 0xd0ac, 0x0130, 0x8b58, 0x080c, 0x2e43, 0x00fe, 0x0804,
+	0x2df2, 0x00fe, 0x080c, 0x2e39, 0x1150, 0x8948, 0x2001, 0x0032,
+	0x2602, 0x2001, 0x0033, 0x2502, 0x080c, 0x2e43, 0x0078, 0x87ff,
+	0x0138, 0x2001, 0x0201, 0x2004, 0x9005, 0x19b8, 0x8739, 0x0030,
+	0x2001, 0x131c, 0x2004, 0x9086, 0x0000, 0x1978, 0x2001, 0x034f,
+	0x2003, 0x00f6, 0x8631, 0x1208, 0x8529, 0x2500, 0x9605, 0x0904,
+	0x2df2, 0x7884, 0xd0bc, 0x0128, 0x2900, 0x9a05, 0x9b05, 0x1904,
+	0x2df2, 0x6013, 0x0019, 0x2001, 0x032a, 0x2003, 0x0004, 0x7884,
+	0xd0ac, 0x1148, 0x2001, 0x131c, 0x2003, 0x0003, 0x2001, 0x032a,
+	0x2003, 0x0009, 0x0040, 0x6017, 0x0001, 0x2001, 0x002d, 0x2004,
+	0x9005, 0x0108, 0x6016, 0x2c00, 0x605a, 0x2001, 0x0200, 0x2003,
+	0x0040, 0x2d00, 0x685a, 0x6813, 0x0019, 0x7884, 0xd0a4, 0x1180,
+	0x6817, 0x0000, 0x00c6, 0x20a9, 0x0004, 0x2061, 0x0090, 0x602b,
+	0x0008, 0x2001, 0x0203, 0x2004, 0x1f04, 0x2dc7, 0x00ce, 0x0040,
+	0x6817, 0x0001, 0x2001, 0x002c, 0x2004, 0x9005, 0x0108, 0x6816,
+	0x00f6, 0x00c6, 0x2079, 0x0100, 0x2061, 0x0090, 0x7827, 0x0002,
+	0x2001, 0x002a, 0x2004, 0x9084, 0xfff8, 0x601a, 0x0006, 0x2001,
+	0x002b, 0x2004, 0x601e, 0x78c6, 0x000e, 0x78ca, 0x00ce, 0x00fe,
+	0x0804, 0x2d33, 0x2001, 0x032a, 0x2003, 0x0004, 0x2061, 0x0100,
+	0x6027, 0x0002, 0x001e, 0x6106, 0x2011, 0x020d, 0x2013, 0x0020,
+	0x2001, 0x0004, 0x200c, 0x918c, 0xfffd, 0x2102, 0x080c, 0x0f8f,
+	0x7884, 0x9084, 0x0003, 0x9086, 0x0002, 0x01a0, 0x2001, 0x0200,
+	0x2003, 0x0028, 0x2001, 0x0227, 0x200c, 0x2102, 0x6050, 0x9084,
+	0xb7ef, 0x6052, 0x602f, 0x0000, 0x604b, 0xf7f7, 0x6043, 0x0090,
+	0x6043, 0x0010, 0x2908, 0x2a10, 0x2b18, 0x2b00, 0x9a05, 0x9905,
+	0x00fe, 0x00ee, 0x00de, 0x00ce, 0x00be, 0x00ae, 0x009e, 0x008e,
+	0x1118, 0x012e, 0x0804, 0x28a2, 0x012e, 0x2021, 0x400c, 0x0804,
+	0x28a4, 0x9085, 0x0001, 0x1d04, 0x2e42, 0x2091, 0x6000, 0x8420,
+	0x9486, 0x0064, 0x0005, 0x2001, 0x0105, 0x2003, 0x0010, 0x2001,
+	0x032a, 0x2003, 0x0004, 0x2001, 0x009a, 0x2003, 0x0004, 0x2001,
+	0x131c, 0x2003, 0x0000, 0x2001, 0x131f, 0x2003, 0x0000, 0x2001,
+	0x0200, 0x2003, 0x0048, 0x2001, 0x0227, 0x2024, 0x2402, 0x9026,
+	0x0005, 0x00f6, 0x2079, 0x0100, 0x2001, 0x1114, 0x200c, 0x7932,
+	0x7936, 0x080c, 0x1c93, 0x7850, 0x9084, 0xfbff, 0x9085, 0x0030,
+	0x7852, 0x2019, 0x01f4, 0x8319, 0x1df0, 0x9084, 0xffcf, 0x9085,
+	0x2000, 0x7852, 0x20a9, 0x0046, 0x1d04, 0x2e7c, 0x2091, 0x6000,
+	0x1f04, 0x2e7c, 0x7850, 0x9085, 0x0400, 0x9084, 0xdfff, 0x7852,
+	0x2001, 0x0021, 0x2004, 0x9084, 0x0003, 0x9086, 0x0001, 0x1120,
+	0x7850, 0x9084, 0xdfff, 0x7852, 0x784b, 0xf7f7, 0x7843, 0x0090,
+	0x7843, 0x0010, 0x20a9, 0x0028, 0xa001, 0x1f04, 0x2e9c, 0x7850,
+	0x9085, 0x1400, 0x7852, 0x2019, 0x61a8, 0x7854, 0xa001, 0xa001,
+	0xd08c, 0x1110, 0x8319, 0x1dc8, 0x7827, 0x0048, 0x7850, 0x9085,
+	0x0400, 0x7852, 0x7843, 0x0040, 0x2019, 0x01f4, 0xa001, 0xa001,
+	0x8319, 0x1de0, 0x2001, 0x0140, 0x2003, 0x0100, 0x7827, 0x0020,
+	0x7843, 0x0000, 0x2003, 0x0000, 0x7827, 0x0048, 0x00fe, 0x0005,
+	0x7884, 0xd0ac, 0x11c8, 0x00f6, 0x00e6, 0x2071, 0x131c, 0x2079,
+	0x0320, 0x2001, 0x0201, 0x2004, 0x9005, 0x0160, 0x7000, 0x9086,
+	0x0000, 0x1140, 0x0051, 0xd0bc, 0x0108, 0x8738, 0x7003, 0x0003,
+	0x782b, 0x0019, 0x00ee, 0x00fe, 0x0005, 0x78bc, 0x908c, 0x0070,
+	0x0178, 0x2009, 0x0032, 0x260a, 0x2009, 0x0033, 0x250a, 0xd0b4,
+	0x0108, 0x8a50, 0xd0ac, 0x0108, 0x8948, 0xd0a4, 0x0108, 0x8b58,
+	0x0005, 0x00f6, 0x2079, 0x0200, 0x781c, 0xd084, 0x0110, 0x7837,
+	0x0050, 0x00fe, 0x0005, 0x00e6, 0x2071, 0x0100, 0x70e3, 0x0005,
+	0x702c, 0x9085, 0x0002, 0x702e, 0x2009, 0x1114, 0x210c, 0x716e,
+	0x7063, 0x0100, 0x7166, 0x719e, 0x706b, 0x0000, 0x7073, 0x0809,
+	0x7077, 0x0008, 0x7078, 0x9080, 0x0100, 0x707a, 0x7080, 0x8000,
+	0x7082, 0x7087, 0xaaaa, 0x9006, 0x708a, 0x708e, 0x707e, 0x70d6,
+	0x70ab, 0x0036, 0x70af, 0x95d5, 0x7014, 0x9084, 0x1984, 0x9085,
+	0x0012, 0x7016, 0x080c, 0x2fd2, 0x00f6, 0x2071, 0x131c, 0x2079,
+	0x0320, 0x00d6, 0x2069, 0x0000, 0x6884, 0xd0b4, 0x0120, 0x689c,
+	0x780e, 0x6898, 0x780a, 0x00de, 0x2011, 0x0011, 0x080c, 0x2faa,
+	0x2011, 0x0001, 0x080c, 0x2faa, 0x00fe, 0x00ee, 0x0005, 0x00f6,
+	0x00e6, 0x2071, 0x131c, 0x2079, 0x0320, 0x792c, 0xd1fc, 0x0904,
+	0x2fa7, 0x782b, 0x0002, 0x9026, 0xd19c, 0x1904, 0x2fa3, 0x7000,
+	0x0002, 0x2fa7, 0x2f65, 0x2f89, 0x2fa3, 0xd1bc, 0x1150, 0xd1dc,
+	0x1150, 0x8001, 0x7002, 0x2011, 0x0001, 0x04e1, 0x05c0, 0x04d1,
+	0x04b0, 0x78bf, 0x0000, 0x7810, 0x7914, 0x782b, 0x0004, 0x7812,
+	0x7916, 0x2001, 0x0201, 0x200c, 0x81ff, 0x0de8, 0x080c, 0x2ee5,
+	0x2009, 0x0001, 0x78b8, 0xd0ec, 0x0110, 0x2009, 0x0011, 0x792a,
+	0x00f0, 0x8001, 0x7002, 0x9184, 0x0880, 0x1138, 0x782c, 0xd0fc,
+	0x1940, 0x2011, 0x0001, 0x00b1, 0x0090, 0x6010, 0x9092, 0x0004,
+	0x9086, 0x0015, 0x1120, 0x6000, 0x605a, 0x2011, 0x0031, 0x6212,
+	0xd1dc, 0x1988, 0x0870, 0x782b, 0x0004, 0x7003, 0x0000, 0x00ee,
+	0x00fe, 0x0005, 0x6014, 0x9005, 0x0520, 0x8001, 0x6016, 0x6058,
+	0x6110, 0x9140, 0x2804, 0x7802, 0x8840, 0x2804, 0x7806, 0x8840,
+	0x2804, 0x7812, 0x8840, 0x2804, 0x7816, 0x8840, 0x7a2a, 0x7000,
+	0x8000, 0x7002, 0x6058, 0x9802, 0x908a, 0x0029, 0x1138, 0x6058,
+	0x9080, 0x0001, 0x2004, 0x605a, 0x2001, 0x0019, 0x6012, 0x9085,
+	0x0001, 0x0005, 0x00f6, 0x00e6, 0x00c6, 0x2071, 0x131f, 0x2079,
+	0x0090, 0x792c, 0xd1fc, 0x01f0, 0x782b, 0x0002, 0x2d60, 0x9026,
+	0x7000, 0x0002, 0x2ffa, 0x2fe5, 0x2ff1, 0x8001, 0x7002, 0xd19c,
+	0x1188, 0x2011, 0x0001, 0x080c, 0x2faa, 0x0160, 0x080c, 0x2faa,
+	0x0048, 0x8001, 0x7002, 0x782c, 0xd0fc, 0x1d30, 0x2011, 0x0001,
+	0x080c, 0x2faa, 0x00ce, 0x00ee, 0x00fe, 0x0005, 0x00f6, 0x00e6,
+	0x00c6, 0x2061, 0x0200, 0x601b, 0x0004, 0x2061, 0x0100, 0x60cf,
+	0x0400, 0x6104, 0xc1ac, 0x6106, 0x2001, 0x002c, 0x2004, 0x9005,
+	0x01f8, 0x2038, 0x2001, 0x002e, 0x2024, 0x2001, 0x002f, 0x201c,
+	0x080c, 0x3784, 0x6813, 0x0019, 0x6f16, 0x2d00, 0x685a, 0x978a,
+	0x0007, 0x0220, 0x2138, 0x2009, 0x0007, 0x0010, 0x2708, 0x903e,
+	0x6858, 0x9080, 0x0019, 0x04b1, 0x1d90, 0x2d00, 0x685a, 0x0088,
+	0x080c, 0x3784, 0x6813, 0x0019, 0x2070, 0x6817, 0x0001, 0x2d00,
+	0x685a, 0x2001, 0x002e, 0x2004, 0x2072, 0x2001, 0x002f, 0x2004,
+	0x7006, 0x2061, 0x0090, 0x2079, 0x0100, 0x6037, 0x0400, 0x2001,
+	0x0200, 0x2003, 0x0040, 0x2001, 0x002a, 0x2004, 0x9084, 0xfff8,
+	0x700a, 0x601a, 0x0006, 0x2001, 0x002b, 0x2004, 0x700e, 0x601e,
+	0x78c6, 0x000e, 0x78ca, 0x9006, 0x600a, 0x600e, 0x00ce, 0x00ee,
+	0x00fe, 0x0005, 0x00e6, 0x2071, 0x0080, 0x20e9, 0x0001, 0x20a0,
+	0x20e1, 0x0000, 0x2099, 0x0088, 0x702b, 0x0026, 0x7402, 0x7306,
+	0x9006, 0x700a, 0x700e, 0x810b, 0x810b, 0x21a8, 0x810b, 0x7112,
+	0x702b, 0x0041, 0x702c, 0xd0fc, 0x0de8, 0x702b, 0x0002, 0x702b,
+	0x0040, 0x4005, 0x7400, 0x7304, 0x87ff, 0x0180, 0x00c6, 0x00d6,
+	0x2d60, 0x00c6, 0x080c, 0x3784, 0x00ce, 0x6058, 0x2070, 0x2d00,
+	0x7006, 0x605a, 0x00de, 0x00ce, 0x9085, 0x0001, 0x00ee, 0x0005,
+	0x00e6, 0x2001, 0x002d, 0x2004, 0x9005, 0x0508, 0x2038, 0x2001,
+	0x0030, 0x2024, 0x2001, 0x0031, 0x201c, 0x080c, 0x3784, 0x2d60,
+	0x6813, 0x0019, 0x6f16, 0x2d00, 0x685a, 0x978a, 0x0007, 0x0220,
+	0x2138, 0x2009, 0x0007, 0x0010, 0x2708, 0x903e, 0x6858, 0x9080,
+	0x0019, 0x080c, 0x3062, 0x1d88, 0x2d00, 0x685a, 0x00e0, 0x080c,
+	0x3784, 0x2d60, 0x6013, 0x0019, 0x2070, 0x6017, 0x0001, 0x2c00,
+	0x605a, 0x2001, 0x0030, 0x2004, 0x2072, 0x2001, 0x0031, 0x2004,
+	0x7006, 0x2001, 0x002a, 0x2004, 0x9084, 0xfff8, 0x700a, 0x2001,
+	0x002b, 0x2004, 0x700e, 0x2001, 0x032a, 0x2003, 0x0004, 0x7884,
+	0xd0ac, 0x1180, 0x2001, 0x0101, 0x200c, 0x918d, 0x0200, 0x2102,
+	0x6017, 0x0000, 0x2001, 0x131c, 0x2003, 0x0003, 0x2001, 0x032a,
+	0x2003, 0x0009, 0x2001, 0x0300, 0x2003, 0x0000, 0x2001, 0x020d,
+	0x2003, 0x0000, 0x2001, 0x0004, 0x200c, 0x918d, 0x0002, 0x2102,
+	0x00ee, 0x0005, 0x0804, 0x28a2, 0x0126, 0x2091, 0x8000, 0x20a9,
+	0x0012, 0x2001, 0x1140, 0x20e9, 0x0001, 0x20a0, 0x9006, 0x4004,
+	0x2009, 0x013c, 0x200a, 0x012e, 0x0804, 0x28a2, 0x7d98, 0x7c9c,
+	0x0804, 0x2991, 0x080c, 0x5745, 0x0110, 0x080c, 0x46e5, 0x2069,
+	0x1152, 0x2d00, 0x2009, 0x0030, 0x7a8c, 0x7b88, 0x7c9c, 0x7d98,
+	0x2039, 0x0001, 0x080c, 0x37c5, 0x701b, 0x312f, 0x0005, 0x2069,
+	0x1152, 0x6800, 0x9005, 0x0904, 0x28cf, 0x6804, 0xd0ac, 0x0118,
+	0xd0a4, 0x0904, 0x28cf, 0xd094, 0x00c6, 0x2061, 0x0100, 0x6104,
+	0x0138, 0x6200, 0x9292, 0x0005, 0x0218, 0x918c, 0xffdf, 0x0010,
+	0x918d, 0x0020, 0x6106, 0x00ce, 0xd08c, 0x00c6, 0x2061, 0x0100,
+	0x6104, 0x0118, 0x918d, 0x0010, 0x0010, 0x918c, 0xffef, 0x6106,
+	0x00ce, 0xd084, 0x0158, 0x6a28, 0x928a, 0x007f, 0x1a04, 0x28cf,
+	0x9288, 0x26c1, 0x210d, 0x918c, 0x00ff, 0x6156, 0xd0dc, 0x0130,
+	0x6828, 0x908a, 0x007f, 0x1a04, 0x28cf, 0x604e, 0x6888, 0x9084,
+	0x0030, 0x8004, 0x8004, 0x8004, 0x8004, 0x0006, 0x2009, 0x12c0,
+	0x9080, 0x1d8e, 0x2005, 0x200a, 0x000e, 0x2009, 0x12c1, 0x9080,
+	0x1d92, 0x2005, 0x200a, 0x6808, 0x908a, 0x0100, 0x0a04, 0x28cf,
+	0x908a, 0x0841, 0x1a04, 0x28cf, 0x9084, 0x0007, 0x1904, 0x28cf,
+	0x680c, 0x9005, 0x0904, 0x28cf, 0x6810, 0x9005, 0x0904, 0x28cf,
+	0x6848, 0x6940, 0x910a, 0x1a04, 0x28cf, 0x8001, 0x0904, 0x28cf,
+	0x684c, 0x6944, 0x910a, 0x1a04, 0x28cf, 0x8001, 0x0904, 0x28cf,
+	0x6980, 0xd1e4, 0x0140, 0x00c6, 0x2061, 0x0100, 0x6004, 0x9085,
+	0x0100, 0x6006, 0x00ce, 0x6814, 0x908c, 0x00ff, 0x613e, 0x8007,
+	0x9084, 0x00ff, 0x6042, 0x080c, 0x5a12, 0x080c, 0x4e38, 0x080c,
+	0x4e87, 0x6808, 0x602a, 0x080c, 0x1800, 0x2009, 0x0170, 0x200b,
+	0x0080, 0xa001, 0xa001, 0x200b, 0x0000, 0x0036, 0x6b08, 0x080c,
+	0x1cee, 0x003e, 0x6000, 0x9086, 0x0000, 0x1904, 0x3299, 0x6818,
+	0x691c, 0x6a20, 0x6b24, 0x8007, 0x810f, 0x8217, 0x831f, 0x6016,
+	0x611a, 0x621e, 0x6322, 0x6c04, 0xd4f4, 0x0148, 0x6830, 0x6934,
+	0x6a38, 0x6b3c, 0x8007, 0x810f, 0x8217, 0x831f, 0x0010, 0x9084,
+	0xf0ff, 0x6006, 0x610a, 0x620e, 0x6312, 0x8007, 0x810f, 0x8217,
+	0x831f, 0x20a9, 0x0004, 0x20a1, 0x12c2, 0x20e9, 0x0001, 0x4001,
+	0x080c, 0x6603, 0x00c6, 0x2009, 0x0000, 0x20a9, 0x0001, 0x6b70,
+	0xd384, 0x01d0, 0x0028, 0x83f5, 0x3e18, 0x12b0, 0x3508, 0x8109,
+	0x080c, 0x5f4d, 0x6878, 0x6016, 0x6874, 0x2008, 0x9084, 0xff00,
+	0x8007, 0x600a, 0x9184, 0x00ff, 0x6006, 0x8108, 0x1118, 0x6003,
+	0x0003, 0x0010, 0x6003, 0x0001, 0x1f04, 0x320b, 0x00ce, 0x00c6,
+	0x2061, 0x12bc, 0x6a88, 0x9284, 0xc000, 0x2010, 0x9286, 0x0000,
+	0x1118, 0x2063, 0x0000, 0x0058, 0x9286, 0x4000, 0x1118, 0x2063,
+	0x0001, 0x0028, 0x9286, 0x8000, 0x1da0, 0x2063, 0x0002, 0x00ce,
+	0x6888, 0xd0ec, 0x0130, 0x2011, 0x0114, 0x2204, 0x9085, 0x0100,
+	0x2012, 0x6a80, 0x9284, 0x0030, 0x9086, 0x0030, 0x1128, 0x9294,
+	0xffcf, 0x9295, 0x0020, 0x6a82, 0x2001, 0x128f, 0x6a80, 0x9294,
+	0x0030, 0x928e, 0x0000, 0x0170, 0x928e, 0x0010, 0x0118, 0x928e,
+	0x0020, 0x0140, 0x2003, 0xaaaa, 0x080c, 0x1d69, 0x2001, 0x1280,
+	0x2102, 0x0008, 0x2102, 0x00c6, 0x2061, 0x0100, 0x602f, 0x0040,
+	0x602f, 0x0000, 0x00ce, 0x080c, 0x5745, 0x0128, 0x080c, 0x39e4,
+	0x0110, 0x080c, 0x1cb3, 0x60c4, 0x9005, 0x01b0, 0x6003, 0x0001,
+	0x2009, 0x3283, 0x00c0, 0x080c, 0x5745, 0x1158, 0x2011, 0x5654,
+	0x080c, 0x655b, 0x2001, 0x1290, 0x2003, 0x0000, 0x080c, 0x5682,
+	0x0040, 0x080c, 0x45d6, 0x0028, 0x6003, 0x0004, 0x2009, 0x3299,
+	0x0010, 0x0804, 0x28a2, 0x2001, 0x0170, 0x2004, 0x9084, 0x00ff,
+	0x9086, 0x004c, 0x1118, 0x2091, 0x30bd, 0x0817, 0x2091, 0x303d,
+	0x0817, 0x6000, 0x9086, 0x0000, 0x0904, 0x28cc, 0x2069, 0x1152,
+	0x7890, 0x6842, 0x7894, 0x6846, 0x2d00, 0x2009, 0x0030, 0x7a8c,
+	0x7b88, 0x7c9c, 0x7d98, 0x2039, 0x0001, 0x0804, 0x37c8, 0x9006,
+	0x080c, 0x1cb3, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x5745, 0x1178,
+	0x2001, 0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001,
+	0x9085, 0x0001, 0x080c, 0x5789, 0x080c, 0x5682, 0x0020, 0x080c,
+	0x46e5, 0x080c, 0x45d6, 0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc,
+	0x080c, 0x5745, 0x1110, 0x0804, 0x28cc, 0x6184, 0x81ff, 0x01a8,
+	0x703f, 0x0000, 0x2001, 0x1580, 0x2009, 0x0040, 0x7a8c, 0x7b88,
+	0x7c9c, 0x7d98, 0x0126, 0x2091, 0x8000, 0x2039, 0x0001, 0x080c,
+	0x37c8, 0x701b, 0x28a0, 0x012e, 0x0005, 0x703f, 0x0001, 0x00d6,
+	0x2069, 0x1580, 0x20a9, 0x0040, 0x20e9, 0x0001, 0x20a1, 0x1580,
+	0x2019, 0xffff, 0x4304, 0x654c, 0x9588, 0x26c1, 0x210d, 0x918c,
+	0x00ff, 0x216a, 0x900e, 0x2011, 0x0002, 0x2100, 0x9506, 0x01a8,
+	0x080c, 0x4b58, 0x1190, 0x6014, 0x821c, 0x0238, 0x9398, 0x1580,
+	0x9085, 0xff00, 0x8007, 0x201a, 0x0038, 0x9398, 0x1580, 0x2324,
+	0x94a4, 0xff00, 0x9405, 0x201a, 0x8210, 0x8108, 0x9182, 0x0080,
+	0x1208, 0x0c18, 0x8201, 0x8007, 0x2d0c, 0x9105, 0x206a, 0x00de,
+	0x20a9, 0x0040, 0x20a1, 0x1580, 0x2099, 0x1580, 0x080c, 0x4678,
+	0x0804, 0x32ea, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x00c6, 0x080c,
+	0x3784, 0x00ce, 0x1120, 0x2009, 0x0002, 0x0804, 0x28cc, 0x2001,
+	0x1153, 0x2004, 0xd0b4, 0x0550, 0x7884, 0x9084, 0xff00, 0x908e,
+	0x7e00, 0x0520, 0x908e, 0x7f00, 0x0508, 0x908e, 0x8000, 0x01f0,
+	0x6000, 0xd08c, 0x11d8, 0x6004, 0x9084, 0x00ff, 0x9086, 0x0006,
+	0x11a8, 0x6867, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x080c, 0x9744,
+	0x1120, 0x2009, 0x0003, 0x0804, 0x28cc, 0x7007, 0x0003, 0x701b,
+	0x337a, 0x0005, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x20a9, 0x002b,
+	0x20e1, 0x0001, 0x2c98, 0x9de8, 0x0002, 0x20e9, 0x0001, 0x2da0,
+	0x4003, 0x20a9, 0x0004, 0x9d80, 0x0006, 0x20a0, 0x9c80, 0x0006,
+	0x2098, 0x080c, 0x4678, 0x20a9, 0x0004, 0x9d80, 0x000a, 0x20a0,
+	0x9c80, 0x000a, 0x2098, 0x080c, 0x4678, 0x2d00, 0x2009, 0x002b,
+	0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x2039, 0x0001, 0x0804, 0x37c8,
+	0x81ff, 0x1904, 0x28cc, 0x080c, 0x3799, 0x0904, 0x28cf, 0x080c,
+	0x4cb2, 0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc, 0x7888, 0x908a,
+	0x1000, 0x1a04, 0x28cf, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x080c,
+	0x4cf1, 0x0904, 0x28cc, 0x2019, 0x0004, 0x080c, 0x4cc4, 0x7984,
+	0x810f, 0x7a88, 0x0011, 0x0804, 0x28a2, 0x9186, 0x00ff, 0x0110,
+	0x0071, 0x0060, 0x2029, 0x007e, 0x2061, 0x1100, 0x644c, 0x2400,
+	0x9506, 0x0110, 0x2508, 0x0019, 0x8529, 0x1ec8, 0x0005, 0x080c,
+	0x4b58, 0x1138, 0x2200, 0x8003, 0x800b, 0x810b, 0x9108, 0x080c,
+	0x6567, 0x0005, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x3799, 0x0904,
+	0x28cf, 0x080c, 0x4c17, 0x0904, 0x28cc, 0x080c, 0x4cbb, 0x0804,
+	0x28a2, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x3799, 0x0904, 0x28cf,
+	0x080c, 0x4c17, 0x0904, 0x28cc, 0x080c, 0x4ca9, 0x0804, 0x28a2,
+	0x6100, 0x0804, 0x28a2, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x6004,
+	0x9086, 0x0707, 0x0904, 0x28cf, 0x2001, 0x1100, 0x2004, 0x9086,
+	0x0003, 0x1904, 0x28cc, 0x00d6, 0x9ce8, 0x000a, 0x7984, 0xd184,
+	0x0110, 0x9ce8, 0x0006, 0x680c, 0x8007, 0x789e, 0x6808, 0x8007,
+	0x789a, 0x6b04, 0x831f, 0x6a00, 0x8217, 0x00de, 0x6100, 0x918c,
+	0x0200, 0x0804, 0x28a2, 0x7884, 0x909c, 0x00ff, 0x939a, 0x0003,
+	0x1a04, 0x28cc, 0x624c, 0x9294, 0x00ff, 0x9084, 0xff00, 0x8007,
+	0x9206, 0x1188, 0x2031, 0x1148, 0x2009, 0x013c, 0x2136, 0x2001,
+	0x1140, 0x2009, 0x000c, 0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x2039,
+	0x0001, 0x0804, 0x37c8, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x37a9,
+	0x0904, 0x28cf, 0x6004, 0x9084, 0x00ff, 0x9086, 0x0006, 0x1904,
+	0x28cc, 0x00c6, 0x080c, 0x3784, 0x00ce, 0x0904, 0x28cc, 0x6867,
+	0x0000, 0x6868, 0xc0fd, 0x686a, 0x080c, 0x96eb, 0x0904, 0x28cc,
+	0x7007, 0x0003, 0x701b, 0x3475, 0x0005, 0x6830, 0x9086, 0x0100,
+	0x0904, 0x28cc, 0x9d80, 0x001b, 0x2009, 0x000c, 0x7a8c, 0x7b88,
+	0x7c9c, 0x7d98, 0x2039, 0x0001, 0x0804, 0x37c8, 0x9006, 0x080c,
+	0x1cb3, 0x7884, 0x9084, 0x00ff, 0x9086, 0x00ff, 0x0118, 0x81ff,
+	0x1904, 0x28cc, 0x080c, 0x5745, 0x0110, 0x080c, 0x46e5, 0x7888,
+	0x908a, 0x1000, 0x1a04, 0x28cf, 0x7984, 0x918c, 0xff00, 0x810f,
+	0x9186, 0x00ff, 0x0138, 0x9182, 0x007f, 0x1a04, 0x28cf, 0x2100,
+	0x080c, 0x1c7d, 0x0026, 0x00c6, 0x0126, 0x2091, 0x8000, 0x2061,
+	0x12ef, 0x601b, 0x0000, 0x601f, 0x0000, 0x080c, 0x5745, 0x1178,
+	0x2001, 0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001,
+	0x9085, 0x0001, 0x080c, 0x5789, 0x080c, 0x5682, 0x0450, 0x2011,
+	0x0003, 0x080c, 0x79c2, 0x2011, 0x0002, 0x080c, 0x79cc, 0x080c,
+	0x78b3, 0x080c, 0x65cf, 0x0036, 0x2019, 0x0000, 0x080c, 0x7936,
+	0x003e, 0x2061, 0x0100, 0x2001, 0x1114, 0x2004, 0x9084, 0x00ff,
+	0x810f, 0x9105, 0x604a, 0x6043, 0x0090, 0x6043, 0x0010, 0x2009,
+	0x12b9, 0x200b, 0x0000, 0x2009, 0x002d, 0x2011, 0x4611, 0x080c,
+	0x65e1, 0x7984, 0x918c, 0xff00, 0x810f, 0x080c, 0x5745, 0x1110,
+	0x2009, 0x00ff, 0x7a88, 0x080c, 0x33cd, 0x012e, 0x00ce, 0x002e,
+	0x0804, 0x28a2, 0x7984, 0x918c, 0xff00, 0x810f, 0x00c6, 0x080c,
+	0x4b03, 0x2c08, 0x00ce, 0x1904, 0x28cf, 0x0804, 0x28a2, 0x81ff,
+	0x0120, 0x2009, 0x0001, 0x0804, 0x28cc, 0x60cc, 0xd0ac, 0x1130,
+	0xd09c, 0x1120, 0x2009, 0x0005, 0x0804, 0x28cc, 0x080c, 0x3784,
+	0x1120, 0x2009, 0x0002, 0x0804, 0x28cc, 0x7984, 0x7a8c, 0x7b88,
+	0x7c9c, 0x7d98, 0x2039, 0x0001, 0x080c, 0x37c5, 0x701b, 0x3531,
+	0x0005, 0x2009, 0x0080, 0x080c, 0x4b58, 0x1130, 0x6004, 0x9084,
+	0x00ff, 0x9086, 0x0006, 0x0120, 0x2021, 0x400a, 0x0804, 0x28a4,
+	0x00d6, 0x9de8, 0x0019, 0x6900, 0x6a08, 0x6b0c, 0x6c10, 0x6d14,
+	0x6e18, 0x6820, 0x90be, 0x0100, 0x0904, 0x35a8, 0x90be, 0x0112,
+	0x0904, 0x35a8, 0x90be, 0x0113, 0x0904, 0x35a8, 0x90be, 0x0114,
+	0x0904, 0x35a8, 0x90be, 0x0117, 0x0904, 0x35a8, 0x90be, 0x011a,
+	0x0904, 0x35a8, 0x90be, 0x011c, 0x0904, 0x35a8, 0x90be, 0x0121,
+	0x05b0, 0x90be, 0x0131, 0x0598, 0x90be, 0x0171, 0x05c8, 0x90be,
+	0x0173, 0x05b0, 0x90be, 0x01a1, 0x1120, 0x6830, 0x8007, 0x6832,
+	0x04a8, 0x90be, 0x0212, 0x0540, 0x90be, 0x0213, 0x0528, 0x90be,
+	0x0214, 0x01b0, 0x90be, 0x0217, 0x0168, 0x90be, 0x021a, 0x1120,
+	0x6838, 0x8007, 0x683a, 0x00e0, 0x90be, 0x0300, 0x01c8, 0x00de,
+	0x0804, 0x28cf, 0x9d80, 0x0010, 0x20a9, 0x0007, 0x080c, 0x35ee,
+	0x9d80, 0x000e, 0x20a9, 0x0001, 0x080c, 0x35ee, 0x0048, 0x9d80,
+	0x000c, 0x080c, 0x35fc, 0x0050, 0x9d80, 0x000e, 0x080c, 0x35fc,
+	0x9d80, 0x000c, 0x20a9, 0x0001, 0x080c, 0x35ee, 0x00c6, 0x080c,
+	0x3784, 0x0568, 0x6868, 0xc0fd, 0x686a, 0x6867, 0x0119, 0x6883,
+	0x0000, 0x687f, 0x0020, 0x688b, 0x0001, 0x810b, 0x69ae, 0x68b3,
+	0x0000, 0x6ab6, 0x6bba, 0x6cbe, 0x6dc2, 0x69c6, 0x68cb, 0x0000,
+	0x00ce, 0x00de, 0x6867, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x6823,
+	0x0000, 0x6804, 0x2068, 0x080c, 0x9707, 0x1120, 0x2009, 0x0003,
+	0x0804, 0x28cc, 0x7007, 0x0003, 0x701b, 0x35e5, 0x0005, 0x00ce,
+	0x00de, 0x2009, 0x0002, 0x0804, 0x28cc, 0x6820, 0x9086, 0x8001,
+	0x1904, 0x28a2, 0x2009, 0x0004, 0x0804, 0x28cc, 0x0016, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x290a, 0x8108, 0x280a, 0x8108,
+	0x1f04, 0x35f0, 0x001e, 0x0005, 0x0016, 0x00a6, 0x00b6, 0x2008,
+	0x2044, 0x8000, 0x204c, 0x8000, 0x2054, 0x8000, 0x205c, 0x2b0a,
+	0x8108, 0x2a0a, 0x8108, 0x290a, 0x8108, 0x280a, 0x00be, 0x00ae,
+	0x001e, 0x0005, 0x81ff, 0x0120, 0x2009, 0x0001, 0x0804, 0x28cc,
+	0x7984, 0x2140, 0x918c, 0xff00, 0x810f, 0x60cc, 0xd0ac, 0x1120,
+	0x9182, 0x0080, 0x0a04, 0x28cf, 0x9182, 0x00ff, 0x1a04, 0x28cf,
+	0x7a8c, 0x7b88, 0x606c, 0x9306, 0x1140, 0x6070, 0x924e, 0x0904,
+	0x28cf, 0x99cc, 0xff00, 0x0904, 0x28cf, 0x00c6, 0x080c, 0x36d2,
+	0x2c68, 0x00ce, 0x0538, 0x90c6, 0x4000, 0x1180, 0x00c6, 0x0006,
+	0x2d60, 0x2009, 0x0000, 0x080c, 0x4d21, 0x1108, 0xc185, 0x6000,
+	0xd0bc, 0x0108, 0xc18d, 0x000e, 0x00ce, 0x0088, 0x90c6, 0x4007,
+	0x1110, 0x2408, 0x0060, 0x90c6, 0x4008, 0x1118, 0x2708, 0x2610,
+	0x0030, 0x90c6, 0x4009, 0x1108, 0x0010, 0x2001, 0x4006, 0x2020,
+	0x0804, 0x28a4, 0x2d00, 0x7022, 0x0016, 0x00b6, 0x00c6, 0x00e6,
+	0x2c70, 0x080c, 0x7ec8, 0x05d8, 0x2d00, 0x6012, 0x080c, 0x99cc,
+	0x2e58, 0x00ee, 0x00e6, 0x00c6, 0x080c, 0x3784, 0x00ce, 0x2b70,
+	0x1150, 0x080c, 0x7f1e, 0x00ee, 0x00ce, 0x00be, 0x001e, 0x2009,
+	0x0002, 0x0804, 0x28cc, 0x6867, 0x0000, 0x686b, 0x0000, 0x2d00,
+	0x6016, 0x6833, 0x0000, 0x6868, 0xc0fd, 0xd88c, 0x0108, 0xc0f5,
+	0x686a, 0x0126, 0x2091, 0x8000, 0x080c, 0x25ad, 0x012e, 0x6023,
+	0x0001, 0x2001, 0x0000, 0x080c, 0x4aa1, 0x2001, 0x0002, 0x080c,
+	0x4ab3, 0x2009, 0x0002, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x00ee,
+	0x00ce, 0x00be, 0x001e, 0x1120, 0x2009, 0x0003, 0x0804, 0x28cc,
+	0x7007, 0x0003, 0x701b, 0x36b5, 0x0005, 0x6830, 0x9086, 0x0100,
+	0x7020, 0x2060, 0x1138, 0x2009, 0x0004, 0x6204, 0x9294, 0x00ff,
+	0x0804, 0x28cc, 0x2009, 0x0000, 0x6868, 0xd0f4, 0x1904, 0x28a2,
+	0x080c, 0x4d21, 0x1108, 0xc185, 0x6000, 0xd0bc, 0x0108, 0xc18d,
+	0x0804, 0x28a2, 0x00e6, 0x00d6, 0x2029, 0x0000, 0x2001, 0x1133,
+	0x2004, 0xd0ac, 0x0138, 0x2021, 0x0000, 0x20a9, 0x00ff, 0x2071,
+	0x1000, 0x0030, 0x2021, 0x0080, 0x20a9, 0x007f, 0x2071, 0x1080,
+	0x2e04, 0x9005, 0x1130, 0x2100, 0x9406, 0x1570, 0x2428, 0xc5fd,
+	0x0458, 0x2068, 0x6f10, 0x2700, 0x9306, 0x11b0, 0x6e14, 0x2600,
+	0x9206, 0x1190, 0x2400, 0x9106, 0x1160, 0x2d60, 0xd884, 0x0568,
+	0x6004, 0x9084, 0x00ff, 0x9086, 0x0006, 0x1538, 0x2001, 0x4000,
+	0x0428, 0x2001, 0x4007, 0x0410, 0x2400, 0x9106, 0x1168, 0x6e14,
+	0x87ff, 0x1138, 0x86ff, 0x09d0, 0x2001, 0x1133, 0x2004, 0xd0ac,
+	0x19a8, 0x2001, 0x4008, 0x0090, 0x8420, 0x8e70, 0x1f04, 0x36e8,
+	0x85ff, 0x1130, 0x2001, 0x4009, 0x0048, 0x2001, 0x0001, 0x0030,
+	0x080c, 0x4b03, 0x1dd0, 0x6312, 0x6216, 0x9006, 0x9005, 0x00de,
+	0x00ee, 0x0005, 0x81ff, 0x1904, 0x28cc, 0x080c, 0x3784, 0x0904,
+	0x28cc, 0x6867, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x7884, 0x9005,
+	0x0904, 0x28cf, 0x9096, 0x00ff, 0x0120, 0x9092, 0x0004, 0x1a04,
+	0x28cf, 0x2010, 0x2d18, 0x080c, 0x2562, 0x0904, 0x28cc, 0x7007,
+	0x0003, 0x701b, 0x3754, 0x0005, 0x6830, 0x9086, 0x0100, 0x0904,
+	0x28cc, 0x0804, 0x28a2, 0x7984, 0x918c, 0xff00, 0x810f, 0x60cc,
+	0xd0ac, 0x1120, 0x9182, 0x0080, 0x0a04, 0x28cf, 0x9182, 0x00ff,
+	0x1a04, 0x28cf, 0x0126, 0x2091, 0x8000, 0x080c, 0x9602, 0x1188,
+	0x9190, 0x1000, 0x2204, 0x9065, 0x0160, 0x080c, 0x472d, 0x2001,
+	0x1133, 0x2004, 0xd0ac, 0x0110, 0x6017, 0x0000, 0x012e, 0x0804,
+	0x28a2, 0x012e, 0x0804, 0x28cc, 0x080c, 0x0ddf, 0x0188, 0x9006,
+	0x6802, 0x7010, 0x9005, 0x1120, 0x2d00, 0x7012, 0x7016, 0x0030,
+	0x7014, 0x6802, 0x2060, 0x2d00, 0x6006, 0x7016, 0x9d80, 0x0019,
+	0x0005, 0x7984, 0x810f, 0x918c, 0x00ff, 0x080c, 0x4b58, 0x1130,
+	0x7e88, 0x9684, 0x3fff, 0x9082, 0x4000, 0x0208, 0x9066, 0x8cff,
+	0x0005, 0x7e84, 0x860f, 0x918c, 0x00ff, 0x080c, 0x4b58, 0x1128,
+	0x96b4, 0x00ff, 0x9682, 0x4000, 0x0208, 0x9066, 0x8cff, 0x0005,
+	0x0016, 0x7110, 0x81ff, 0x0128, 0x2168, 0x6904, 0x080c, 0x0df6,
+	0x0cc8, 0x7112, 0x7116, 0x001e, 0x0005, 0x2031, 0x0001, 0x0010,
+	0x2031, 0x0000, 0x2061, 0x11e3, 0x6606, 0x6116, 0x670e, 0x6012,
+	0x622a, 0x632e, 0x6432, 0x6536, 0x2c10, 0x080c, 0x0e55, 0x7007,
+	0x0002, 0x701b, 0x28a2, 0x0005, 0x00f6, 0x0126, 0x2091, 0x8000,
+	0x2079, 0x0000, 0x2001, 0x11a1, 0x2004, 0x9005, 0x1158, 0x0e04,
+	0x37f2, 0x7a36, 0x7833, 0x0012, 0x7a82, 0x7b86, 0x7c8a, 0x2091,
+	0x4080, 0x0408, 0x0016, 0x00c6, 0x00e6, 0x2071, 0x1193, 0x7138,
+	0x9182, 0x0010, 0x0218, 0x7030, 0x2060, 0x0078, 0x7030, 0x90e0,
+	0x0004, 0x9c82, 0x11e3, 0x0210, 0x2061, 0x11a3, 0x2c00, 0x7032,
+	0x81ff, 0x1108, 0x7036, 0x8108, 0x713a, 0x2262, 0x6306, 0x640a,
+	0x00ee, 0x00ce, 0x001e, 0x012e, 0x00fe, 0x0005, 0x00e6, 0x2071,
+	0x1193, 0x7038, 0x9005, 0x0560, 0x0126, 0x2091, 0x8000, 0x0e04,
+	0x3847, 0x00f6, 0x2079, 0x0000, 0x00c6, 0x7034, 0x2060, 0x2c04,
+	0x7836, 0x7833, 0x0012, 0x7882, 0x6004, 0x7886, 0x6008, 0x788a,
+	0x2091, 0x4080, 0x7038, 0x8001, 0x703a, 0x9005, 0x1130, 0x7033,
+	0x11a3, 0x7037, 0x11a3, 0x00ce, 0x0048, 0x9c80, 0x0004, 0x90fa,
+	0x11e3, 0x0210, 0x2001, 0x11a3, 0x7036, 0x00ce, 0x00fe, 0x012e,
+	0x00ee, 0x0005, 0x0026, 0x2001, 0x1153, 0x2004, 0xd0c4, 0x0120,
+	0x2011, 0x8014, 0x080c, 0x37dc, 0x002e, 0x0005, 0x81ff, 0x1904,
+	0x28cc, 0x0126, 0x2091, 0x8000, 0x6030, 0xc08d, 0xc085, 0xc0ac,
+	0x6032, 0x080c, 0x5745, 0x1178, 0x2001, 0x1290, 0x2003, 0x0001,
+	0x2001, 0x1100, 0x2003, 0x0001, 0x9085, 0x0001, 0x080c, 0x5789,
+	0x080c, 0x5682, 0x0010, 0x080c, 0x45d6, 0x012e, 0x0804, 0x28a2,
+	0x7884, 0x2008, 0x918c, 0xfffd, 0x1128, 0x61d8, 0x910d, 0x61da,
+	0x0804, 0x28a2, 0x0804, 0x28cf, 0x81ff, 0x1904, 0x28cc, 0x6000,
+	0x9086, 0x0003, 0x1904, 0x28cc, 0x2001, 0x1153, 0x2004, 0xd0ac,
+	0x1904, 0x28cc, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x6004, 0x9084,
+	0x00ff, 0x9086, 0x0006, 0x1120, 0x7888, 0x9005, 0x0904, 0x28a2,
+	0x00c6, 0x080c, 0x3784, 0x00ce, 0x0904, 0x28cc, 0x6867, 0x0000,
+	0x6833, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x080c, 0x97e0, 0x0904,
+	0x28cc, 0x7007, 0x0003, 0x701b, 0x38b6, 0x0005, 0x6830, 0x9086,
+	0x0100, 0x0904, 0x28cc, 0x0804, 0x28a2, 0x2001, 0x1100, 0x2004,
+	0x9086, 0x0003, 0x1904, 0x28cc, 0x7f84, 0x7a8c, 0x7b88, 0x7c9c,
+	0x7d98, 0x080c, 0x3784, 0x0904, 0x28cc, 0x2009, 0x0000, 0x2031,
+	0x0000, 0x7023, 0x0000, 0x702f, 0x0000, 0x9d80, 0x0005, 0x7026,
+	0x20a0, 0x20e1, 0x0001, 0x20e9, 0x0001, 0x080c, 0x4b58, 0x1904,
+	0x3937, 0x6004, 0x90c4, 0x00ff, 0x98c6, 0x0006, 0x0130, 0x90c4,
+	0xff00, 0x98c6, 0x0600, 0x1904, 0x3937, 0x2001, 0x1153, 0x2004,
+	0xd0ac, 0x1130, 0x080c, 0x4d21, 0x1118, 0xd79c, 0x0904, 0x3937,
+	0xd794, 0x1110, 0xd784, 0x0158, 0x9c80, 0x0006, 0x2098, 0x3400,
+	0x20a9, 0x0004, 0x4003, 0x080c, 0x35fc, 0xd794, 0x0148, 0x9c80,
+	0x000a, 0x2098, 0x3400, 0x20a9, 0x0004, 0x4003, 0x080c, 0x35fc,
+	0x21a2, 0x3400, 0x8000, 0x20a0, 0xd794, 0x01d8, 0x9c80, 0x0000,
+	0x2098, 0x20a9, 0x0002, 0x4003, 0x9c80, 0x0003, 0x2098, 0x20a9,
+	0x0001, 0x4005, 0x9c80, 0x0004, 0x2098, 0x3400, 0x20a9, 0x0002,
+	0x4003, 0x080c, 0x35ee, 0x9c80, 0x0026, 0x2098, 0x20a9, 0x0002,
+	0x4003, 0xd794, 0x0110, 0x96b0, 0x000b, 0x96b0, 0x0005, 0x8108,
+	0x2001, 0x1133, 0x2004, 0xd0ac, 0x0118, 0x9186, 0x0100, 0x0040,
+	0xd78c, 0x0120, 0x9186, 0x0100, 0x0170, 0x0018, 0x9186, 0x007e,
+	0x0150, 0xd794, 0x0118, 0x9686, 0x0020, 0x0010, 0x9686, 0x0028,
+	0x0150, 0x0804, 0x38d9, 0x86ff, 0x1120, 0x7120, 0x810b, 0x0804,
+	0x28a2, 0x702f, 0x0001, 0x711e, 0x7020, 0x9600, 0x7022, 0x772a,
+	0x2061, 0x11e3, 0x6007, 0x0000, 0x6616, 0x7024, 0x600f, 0x0001,
+	0x6012, 0x622a, 0x632e, 0x6432, 0x6536, 0x2c10, 0x080c, 0x0e55,
+	0x7007, 0x0002, 0x701b, 0x3975, 0x0005, 0x702c, 0x9005, 0x1170,
+	0x711c, 0x7024, 0x20a0, 0x7728, 0x2031, 0x0000, 0x2061, 0x11e3,
+	0x6228, 0x632c, 0x6430, 0x6534, 0x0804, 0x38d9, 0x7120, 0x810b,
+	0x0804, 0x28a2, 0x2029, 0x007e, 0x7984, 0x7a88, 0x7b8c, 0x7c98,
+	0x9184, 0xff00, 0x8007, 0x90e2, 0x0020, 0x0a04, 0x28cf, 0x9502,
+	0x0a04, 0x28cf, 0x9184, 0x00ff, 0x90e2, 0x0020, 0x0a04, 0x28cf,
+	0x9502, 0x0a04, 0x28cf, 0x9284, 0xff00, 0x8007, 0x90e2, 0x0020,
+	0x0a04, 0x28cf, 0x9502, 0x0a04, 0x28cf, 0x9284, 0x00ff, 0x90e2,
+	0x0020, 0x0a04, 0x28cf, 0x9502, 0x0a04, 0x28cf, 0x9384, 0xff00,
+	0x8007, 0x90e2, 0x0020, 0x0a04, 0x28cf, 0x9502, 0x0a04, 0x28cf,
+	0x9384, 0x00ff, 0x90e2, 0x0020, 0x0a04, 0x28cf, 0x9502, 0x0a04,
+	0x28cf, 0x9484, 0xff00, 0x8007, 0x90e2, 0x0020, 0x0a04, 0x28cf,
+	0x9502, 0x0a04, 0x28cf, 0x9484, 0x00ff, 0x90e2, 0x0020, 0x0a04,
+	0x28cf, 0x9502, 0x0a04, 0x28cf, 0x2061, 0x12a9, 0x6102, 0x6206,
+	0x630a, 0x640e, 0x0804, 0x28a2, 0x0006, 0x2001, 0x1153, 0x2004,
+	0xd0cc, 0x000e, 0x0005, 0x0006, 0x2001, 0x1172, 0x2004, 0xd0bc,
+	0x000e, 0x0005, 0x6164, 0x7a84, 0x6300, 0x82ff, 0x1118, 0x7986,
+	0x0804, 0x28a2, 0x83ff, 0x1904, 0x28cf, 0x2001, 0xfff0, 0x9200,
+	0x1a04, 0x28cf, 0x2019, 0xffff, 0x6068, 0x9302, 0x9200, 0x0a04,
+	0x28cf, 0x7986, 0x6266, 0x0804, 0x28a2, 0x2001, 0x1100, 0x2004,
+	0x9086, 0x0003, 0x1904, 0x28cc, 0x7c88, 0x7d84, 0x7e98, 0x7f8c,
+	0x080c, 0x3784, 0x0904, 0x28cc, 0x2009, 0x0000, 0x2019, 0x0000,
+	0x7023, 0x0000, 0x702f, 0x0000, 0x9d80, 0x0003, 0x7026, 0x20a0,
+	0x91e0, 0x1000, 0x2c64, 0x8cff, 0x01d8, 0x6004, 0x9084, 0x00ff,
+	0x9086, 0x0006, 0x0130, 0x6004, 0x9084, 0xff00, 0x9086, 0x0600,
+	0x1178, 0x00d6, 0x3468, 0x6014, 0x206a, 0x8d68, 0x6010, 0x8007,
+	0x9105, 0x8007, 0x206a, 0x8d68, 0x2da0, 0x00de, 0x9398, 0x0002,
+	0x8108, 0x9182, 0x00ff, 0x0120, 0x9386, 0x002a, 0x0148, 0x08c0,
+	0x83ff, 0x1120, 0x7120, 0x810c, 0x0804, 0x28a2, 0x702f, 0x0001,
+	0x711e, 0x7020, 0x9300, 0x7022, 0x2061, 0x11e3, 0x6007, 0x0000,
+	0x6316, 0x7024, 0x600f, 0x0001, 0x6012, 0x642a, 0x652e, 0x6632,
+	0x6736, 0x2c10, 0x080c, 0x0e55, 0x7007, 0x0002, 0x701b, 0x3a71,
+	0x0005, 0x702c, 0x9005, 0x1168, 0x711c, 0x7024, 0x20a0, 0x2019,
+	0x0000, 0x2061, 0x11e3, 0x6428, 0x652c, 0x6630, 0x6734, 0x0804,
+	0x3a28, 0x7120, 0x810c, 0x0804, 0x28a2, 0x81ff, 0x1904, 0x28cc,
+	0x60cc, 0xd0ac, 0x1118, 0xd09c, 0x0904, 0x28cc, 0x080c, 0x3784,
+	0x0904, 0x28cc, 0x7984, 0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x2039,
+	0x0001, 0x080c, 0x37c5, 0x701b, 0x3a9e, 0x0005, 0x00d6, 0x9de8,
+	0x0019, 0x6828, 0x90be, 0x7000, 0x0148, 0x90be, 0x7100, 0x0130,
+	0x90be, 0x7200, 0x0118, 0x00de, 0x0804, 0x28cf, 0x6820, 0x6924,
+	0x080c, 0x1c69, 0x1510, 0x080c, 0x4b03, 0x11f8, 0x7122, 0x6612,
+	0x6516, 0x6e18, 0x00c6, 0x080c, 0x3784, 0x01b8, 0x080c, 0x3784,
+	0x01a0, 0x00ce, 0x00de, 0x6867, 0x0000, 0x6868, 0xc0fd, 0x686a,
+	0x6823, 0x0000, 0x6804, 0x2068, 0x080c, 0x9728, 0x0904, 0x28cc,
+	0x7007, 0x0003, 0x701b, 0x3ad8, 0x0005, 0x00de, 0x0804, 0x28cc,
+	0x7120, 0x080c, 0x26a3, 0x6820, 0x9086, 0x8001, 0x0904, 0x28cc,
+	0x2d00, 0x701e, 0x6804, 0x9080, 0x0002, 0x0006, 0x20a9, 0x002a,
+	0x2098, 0x20a0, 0x080c, 0x4678, 0x000e, 0x9de8, 0x0019, 0x6a08,
+	0x6b0c, 0x6c10, 0x6d14, 0x2061, 0x11e3, 0x6007, 0x0000, 0x6e00,
+	0x6f28, 0x97c6, 0x7000, 0x1108, 0x0018, 0x97c6, 0x7100, 0x1150,
+	0x96c2, 0x0004, 0x0a04, 0x28cf, 0x2009, 0x0004, 0x2039, 0x0001,
+	0x0804, 0x37c8, 0x97c6, 0x7200, 0x1904, 0x28cf, 0x96c2, 0x0054,
+	0x0a04, 0x28cf, 0x600f, 0x0001, 0x6012, 0x6017, 0x002a, 0x622a,
+	0x632e, 0x6432, 0x6536, 0x2c10, 0x080c, 0x0e55, 0x7007, 0x0002,
+	0x701b, 0x3b23, 0x0005, 0x701c, 0x2068, 0x6804, 0x9080, 0x0001,
+	0x2004, 0x9080, 0x0002, 0x0006, 0x20a9, 0x002a, 0x2098, 0x20a0,
+	0x080c, 0x4678, 0x000e, 0x2009, 0x002a, 0x2061, 0x11e3, 0x6228,
+	0x632c, 0x6430, 0x6534, 0x2039, 0x0001, 0x0804, 0x37c8, 0x81ff,
+	0x1904, 0x28cc, 0x080c, 0x3799, 0x0904, 0x28cf, 0x080c, 0x4c17,
+	0x0904, 0x28cc, 0x080c, 0x4ccd, 0x0804, 0x28a2, 0x7884, 0xd084,
+	0x0904, 0x3342, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x00c6, 0x080c,
+	0x3784, 0x00ce, 0x1120, 0x2009, 0x0002, 0x0804, 0x28cc, 0x6004,
+	0x9084, 0x00ff, 0x9086, 0x0006, 0x0128, 0x908e, 0x0004, 0x0110,
+	0x908e, 0x0005, 0x1580, 0x2001, 0x1153, 0x2004, 0xd0b4, 0x0904,
+	0x337e, 0x7884, 0x9084, 0xff00, 0x908e, 0x7e00, 0x0904, 0x337e,
+	0x908e, 0x7f00, 0x0904, 0x337e, 0x908e, 0x8000, 0x0904, 0x337e,
+	0x6000, 0xd08c, 0x1904, 0x337e, 0x6867, 0x0000, 0x6868, 0xc0fd,
+	0x686a, 0x080c, 0x9744, 0x1120, 0x2009, 0x0003, 0x0804, 0x28cc,
+	0x7007, 0x0003, 0x701b, 0x3b95, 0x0005, 0x080c, 0x37a9, 0x0904,
+	0x28cf, 0x0804, 0x337e, 0x2009, 0x1130, 0x210c, 0x81ff, 0x0120,
+	0x2009, 0x0001, 0x0804, 0x28cc, 0x2001, 0x1100, 0x2004, 0x9086,
+	0x0003, 0x0120, 0x2009, 0x0007, 0x0804, 0x28cc, 0x2001, 0x1153,
+	0x2004, 0xd0ac, 0x0120, 0x2009, 0x0008, 0x0804, 0x28cc, 0x609c,
+	0xd0a4, 0x1118, 0xd0ac, 0x1904, 0x337e, 0x6867, 0x0000, 0x6833,
+	0x0000, 0x6868, 0xc0fd, 0x686a, 0x080c, 0x97e0, 0x1120, 0x2009,
+	0x0003, 0x0804, 0x28cc, 0x7007, 0x0003, 0x701b, 0x3bd0, 0x0005,
+	0x6830, 0x9086, 0x0100, 0x1120, 0x2009, 0x0004, 0x0804, 0x28cc,
+	0x080c, 0x37a9, 0x0904, 0x28cf, 0x0804, 0x3b6b, 0x81ff, 0x2009,
+	0x0001, 0x1904, 0x28cc, 0x6000, 0x9086, 0x0003, 0x2009, 0x0007,
+	0x1904, 0x28cc, 0x2001, 0x1153, 0x2004, 0xd0ac, 0x2009, 0x0008,
+	0x1904, 0x28cc, 0x080c, 0x37a9, 0x0904, 0x28cf, 0x6004, 0x9084,
+	0x00ff, 0x9086, 0x0006, 0x2009, 0x0009, 0x1904, 0x28cc, 0x00c6,
+	0x080c, 0x3784, 0x00ce, 0x2009, 0x0002, 0x0904, 0x28cc, 0x6867,
+	0x0000, 0x6833, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x7988, 0x9194,
+	0xff00, 0x918c, 0x00ff, 0x9006, 0x82ff, 0x1128, 0xc0ed, 0x6952,
+	0x798c, 0x6956, 0x0048, 0x928e, 0x0100, 0x1904, 0x28cf, 0xc0e5,
+	0x6853, 0x0000, 0x6857, 0x0000, 0x683e, 0x080c, 0x99cd, 0x2009,
+	0x0003, 0x0904, 0x28cc, 0x7007, 0x0003, 0x701b, 0x3c30, 0x0005,
+	0x6830, 0x9086, 0x0100, 0x2009, 0x0004, 0x0904, 0x28cc, 0x0804,
+	0x28a2, 0x81ff, 0x2009, 0x0001, 0x1904, 0x28cc, 0x6000, 0x9086,
+	0x0003, 0x2009, 0x0007, 0x1904, 0x28cc, 0x080c, 0x37a9, 0x0904,
+	0x28cf, 0x6004, 0x9084, 0x00ff, 0x9086, 0x0006, 0x2009, 0x0009,
+	0x1904, 0x28cc, 0x00c6, 0x080c, 0x3784, 0x00ce, 0x2009, 0x0002,
+	0x0904, 0x28cc, 0x9d80, 0x001b, 0x2009, 0x0008, 0x7a8c, 0x7b88,
+	0x7c9c, 0x7d98, 0x2039, 0x0001, 0x080c, 0x37c5, 0x701b, 0x3c69,
+	0x0005, 0x00d6, 0x9de8, 0x001b, 0x6800, 0x9086, 0x0500, 0x1140,
+	0x6804, 0x9005, 0x1128, 0x6808, 0x9084, 0xff00, 0x1108, 0x0018,
+	0x00de, 0x1904, 0x28cf, 0x00de, 0x6867, 0x0000, 0x6833, 0x0000,
+	0x6868, 0xc0fd, 0x686a, 0x00c6, 0x080c, 0x37a9, 0x1118, 0x00ce,
+	0x0804, 0x28cf, 0x080c, 0x9a1c, 0x2009, 0x0003, 0x00ce, 0x0904,
+	0x28cc, 0x7007, 0x0003, 0x701b, 0x3c96, 0x0005, 0x6830, 0x9086,
+	0x0100, 0x2009, 0x0004, 0x0904, 0x28cc, 0x0804, 0x28a2, 0x81ff,
+	0x0120, 0x2009, 0x0001, 0x0804, 0x28cc, 0x6000, 0x9086, 0x0003,
+	0x0120, 0x2009, 0x0007, 0x0804, 0x28cc, 0x7e84, 0x860f, 0x918c,
+	0x00ff, 0x96b4, 0x00ff, 0x080c, 0x4b58, 0x1904, 0x28cf, 0x9186,
+	0x007f, 0x0150, 0x6004, 0x9084, 0x00ff, 0x9086, 0x0006, 0x0120,
+	0x2009, 0x0009, 0x0804, 0x28cc, 0x00c6, 0x080c, 0x3784, 0x00ce,
+	0x1120, 0x2009, 0x0002, 0x0804, 0x28cc, 0x6867, 0x0000, 0x6868,
+	0xc0fd, 0x686a, 0x080c, 0x975f, 0x1120, 0x2009, 0x0003, 0x0804,
+	0x28cc, 0x7007, 0x0003, 0x701b, 0x3cde, 0x0005, 0x6808, 0x8007,
+	0x9086, 0x0100, 0x1120, 0x2009, 0x0004, 0x0804, 0x28cc, 0x68e0,
+	0x6866, 0x6810, 0x8007, 0x9084, 0x00ff, 0x800c, 0x6814, 0x8007,
+	0x9084, 0x00ff, 0x8004, 0x9080, 0x0002, 0x9108, 0x9d80, 0x0004,
+	0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x2039, 0x0001, 0x0804, 0x37c8,
+	0x080c, 0x3784, 0x1120, 0x2009, 0x0002, 0x0804, 0x28cc, 0x7984,
+	0x9194, 0xff00, 0x918c, 0x00ff, 0x8217, 0x82ff, 0x0110, 0x0804,
+	0x28cf, 0x2009, 0x001a, 0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x080c,
+	0x37c5, 0x701b, 0x3d1c, 0x0005, 0x9d80, 0x0019, 0x2098, 0x20a9,
+	0x001a, 0x20a1, 0x12c2, 0x20e1, 0x0001, 0x20e9, 0x0001, 0x4003,
+	0x0804, 0x28a2, 0x080c, 0x3784, 0x1120, 0x2009, 0x0002, 0x0804,
+	0x28cc, 0x7984, 0x9194, 0xff00, 0x918c, 0x00ff, 0x8217, 0x82ff,
+	0x0110, 0x0804, 0x28cf, 0x2099, 0x12c2, 0x20a0, 0x20a9, 0x001a,
+	0x20e1, 0x0001, 0x20e9, 0x0001, 0x4003, 0x2009, 0x001a, 0x7a8c,
+	0x7b88, 0x7c9c, 0x7d98, 0x2039, 0x0001, 0x0804, 0x37c8, 0x7884,
+	0x908a, 0x1000, 0x1a04, 0x28cf, 0x0126, 0x2091, 0x8000, 0x8003,
+	0x800b, 0x810b, 0x9108, 0x00c6, 0x2061, 0x12ef, 0x6142, 0x00ce,
+	0x012e, 0x0804, 0x28a2, 0x00c6, 0x080c, 0x5745, 0x1188, 0x2001,
+	0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x9085,
+	0x0001, 0x080c, 0x5789, 0x080c, 0x5682, 0x080c, 0x0cf1, 0x0038,
+	0x2061, 0x1100, 0x6030, 0xc09d, 0x6032, 0x080c, 0x45d6, 0x00ce,
+	0x0005, 0x00c6, 0x2001, 0x1100, 0x2004, 0x908e, 0x0000, 0x0904,
+	0x28cc, 0x7884, 0x9005, 0x0188, 0x7888, 0x2061, 0x12bc, 0x2c0c,
+	0x2062, 0x080c, 0x203d, 0x01a0, 0x080c, 0x2045, 0x0188, 0x080c,
+	0x204d, 0x0170, 0x2162, 0x0804, 0x28cf, 0x2061, 0x0100, 0x6038,
+	0x9086, 0x0007, 0x1118, 0x2009, 0x0001, 0x0010, 0x2009, 0x0000,
+	0x7884, 0x9086, 0x0002, 0x1568, 0x2061, 0x0100, 0x6028, 0xc09c,
+	0x602a, 0x0026, 0x2011, 0x0003, 0x080c, 0x79c2, 0x2011, 0x0002,
+	0x080c, 0x79cc, 0x002e, 0x080c, 0x78b3, 0x080c, 0x65cf, 0x0036,
+	0x2019, 0x0000, 0x080c, 0x7936, 0x003e, 0x60e3, 0x0000, 0x080c,
+	0xadf2, 0x080c, 0xae0d, 0x9085, 0x0001, 0x080c, 0x5789, 0x2001,
+	0x0140, 0x2003, 0x0000, 0x2001, 0x1100, 0x2003, 0x0004, 0x6027,
+	0x0008, 0x00ce, 0x0804, 0x28a2, 0x81ff, 0x0120, 0x2009, 0x0001,
+	0x0804, 0x28cc, 0x6000, 0x9086, 0x0003, 0x0120, 0x2009, 0x0007,
+	0x0804, 0x28cc, 0x7e84, 0x860f, 0x918c, 0x00ff, 0x96b4, 0x00ff,
+	0x080c, 0x4b58, 0x1904, 0x28cf, 0x9186, 0x007f, 0x0150, 0x6004,
+	0x9084, 0x00ff, 0x9086, 0x0006, 0x0120, 0x2009, 0x0009, 0x0804,
+	0x28cc, 0x00c6, 0x080c, 0x3784, 0x00ce, 0x1120, 0x2009, 0x0002,
+	0x0804, 0x28cc, 0x6867, 0x0000, 0x6868, 0xc0fd, 0x686a, 0x080c,
+	0x977b, 0x1120, 0x2009, 0x0003, 0x0804, 0x28cc, 0x7007, 0x0003,
+	0x701b, 0x3e1b, 0x0005, 0x6830, 0x9086, 0x0100, 0x1120, 0x2009,
+	0x0004, 0x0804, 0x28cc, 0x68e0, 0x6866, 0x6834, 0x8007, 0x800c,
+	0x9d80, 0x000c, 0x7a8c, 0x7b88, 0x7c9c, 0x7d98, 0x2039, 0x0001,
+	0x0804, 0x37c8, 0x0126, 0x2091, 0x8000, 0x00c6, 0x2061, 0x12ef,
+	0x7984, 0x6152, 0x614e, 0x6057, 0x0000, 0x604b, 0x0009, 0x7898,
+	0x606a, 0x789c, 0x6066, 0x7888, 0x6062, 0x788c, 0x605e, 0x2061,
+	0x1291, 0x2001, 0x1304, 0x6012, 0x600f, 0x0001, 0x6017, 0x0001,
+	0x601b, 0x0002, 0x6007, 0x0000, 0x603b, 0x0000, 0x00ce, 0x012e,
+	0x0804, 0x28a2, 0x0126, 0x0156, 0x0136, 0x0146, 0x01c6, 0x01d6,
+	0x00c6, 0x00d6, 0x00e6, 0x00f6, 0x2061, 0x0100, 0x2069, 0x0200,
+	0x2071, 0x1100, 0x6044, 0xd0a4, 0x11e8, 0xd084, 0x0118, 0x080c,
+	0x3ff0, 0x0068, 0xd08c, 0x0118, 0x080c, 0x3f00, 0x0040, 0xd094,
+	0x0118, 0x080c, 0x3ed3, 0x0018, 0xd09c, 0x0108, 0x0099, 0x00fe,
+	0x00ee, 0x00de, 0x00ce, 0x01de, 0x01ce, 0x014e, 0x013e, 0x015e,
+	0x012e, 0x0005, 0x0016, 0x6128, 0xd19c, 0x1110, 0xc19d, 0x612a,
+	0x001e, 0x0c68, 0x624c, 0x9286, 0xf0f0, 0x1150, 0x6048, 0x9086,
+	0xf0f0, 0x0130, 0x624a, 0x6043, 0x0090, 0x6043, 0x0010, 0x0490,
+	0x9294, 0xff00, 0x9296, 0xf700, 0x0178, 0x7134, 0xd1a4, 0x1160,
+	0x6240, 0x9295, 0x0100, 0x6242, 0x9294, 0x0010, 0x0128, 0x2009,
+	0x00f7, 0x080c, 0x46a4, 0x00f0, 0x6040, 0x9084, 0x0010, 0x9085,
+	0x0140, 0x6042, 0x6043, 0x0000, 0x7077, 0x0000, 0x7093, 0x0001,
+	0x70b7, 0x0000, 0x70cf, 0x0000, 0x2009, 0x1580, 0x200b, 0x0000,
+	0x7087, 0x0000, 0x707b, 0x000f, 0x2009, 0x000f, 0x2011, 0x457f,
+	0x080c, 0x65e1, 0x0005, 0x2001, 0x1174, 0x2004, 0xd08c, 0x0110,
+	0x704f, 0xffff, 0x7078, 0x9005, 0x1510, 0x2011, 0x457f, 0x080c,
+	0x655b, 0x6040, 0x9094, 0x0010, 0x9285, 0x0020, 0x6042, 0x20a9,
+	0x00c8, 0x6044, 0xd08c, 0x1168, 0x1f04, 0x3ee9, 0x6242, 0x708b,
+	0x0000, 0x6040, 0x9094, 0x0010, 0x9285, 0x0080, 0x6042, 0x6242,
+	0x0030, 0x6242, 0x708b, 0x0000, 0x707f, 0x0000, 0x0000, 0x0005,
+	0x707c, 0x908a, 0x0003, 0x1210, 0x0023, 0x0010, 0x080c, 0x0cf1,
+	0x0005, 0x3f0c, 0x3f54, 0x3fef, 0x00f6, 0x707f, 0x0001, 0x6803,
+	0x00fc, 0x20a9, 0x0004, 0x6800, 0x9084, 0x00fc, 0x0120, 0x1f04,
+	0x3f13, 0x080c, 0x0cf1, 0x68a0, 0x68a2, 0x689c, 0x689e, 0x6898,
+	0x689a, 0xa001, 0x6803, 0x1600, 0x6837, 0x0020, 0x080c, 0x4702,
+	0x2079, 0x1500, 0x7833, 0x1101, 0x7837, 0x0000, 0x20e1, 0x0001,
+	0x2099, 0x1105, 0x20e9, 0x0001, 0x20a1, 0x150e, 0x20a9, 0x0004,
+	0x4003, 0x080c, 0x7e9b, 0x20e1, 0x0001, 0x2099, 0x1500, 0x20e9,
+	0x0000, 0x20a1, 0x0240, 0x20a9, 0x0014, 0x4003, 0x60c3, 0x000c,
+	0x600f, 0x0000, 0x080c, 0x45b2, 0x00fe, 0x7083, 0x0000, 0x6043,
+	0x0008, 0x6043, 0x0000, 0x0005, 0x00f6, 0x7080, 0x7083, 0x0000,
+	0x9025, 0x0904, 0x3fcc, 0x6020, 0xd0b4, 0x1904, 0x3fca, 0x7190,
+	0x81ff, 0x0904, 0x3fb8, 0x9486, 0x000c, 0x1904, 0x3fc5, 0x9480,
+	0x0018, 0x8004, 0x20a8, 0x080c, 0x46fa, 0x2011, 0x0260, 0x2019,
+	0x1500, 0x220c, 0x2304, 0x9106, 0x11e8, 0x8210, 0x8318, 0x1f04,
+	0x3f71, 0x6043, 0x0004, 0x2061, 0x0140, 0x605b, 0xbc94, 0x605f,
+	0xf0f0, 0x2061, 0x0100, 0x6043, 0x0006, 0x707f, 0x0002, 0x708b,
+	0x0002, 0x2009, 0x07d0, 0x2011, 0x4586, 0x080c, 0x65e1, 0x080c,
+	0x4702, 0x04c0, 0x080c, 0x46fa, 0x2079, 0x0260, 0x7930, 0x918e,
+	0x1101, 0x1558, 0x7834, 0x9005, 0x1540, 0x7900, 0x918c, 0x00ff,
+	0x1118, 0x7804, 0x9005, 0x0190, 0x080c, 0x46fa, 0x2011, 0x026e,
+	0x2019, 0x1105, 0x20a9, 0x0004, 0x220c, 0x2304, 0x9102, 0x0230,
+	0x11a0, 0x8210, 0x8318, 0x1f04, 0x3fac, 0x0078, 0x7093, 0x0000,
+	0x080c, 0x46fa, 0x20e1, 0x0000, 0x2099, 0x0260, 0x20e9, 0x0001,
+	0x20a1, 0x1500, 0x20a9, 0x0014, 0x4003, 0x6043, 0x0008, 0x6043,
+	0x0000, 0x0010, 0x00fe, 0x0005, 0x6040, 0x9085, 0x0100, 0x6042,
+	0x6020, 0xd0b4, 0x1db8, 0x080c, 0x7e9b, 0x20e1, 0x0001, 0x2099,
+	0x1500, 0x20e9, 0x0000, 0x20a1, 0x0240, 0x20a9, 0x0014, 0x4003,
+	0x60c3, 0x000c, 0x2011, 0x12e6, 0x2013, 0x0000, 0x7083, 0x0000,
+	0x60a3, 0x0056, 0x60a7, 0x9575, 0x080c, 0x7718, 0x08d8, 0x0005,
+	0x7088, 0x908a, 0x001d, 0x1210, 0x0023, 0x0010, 0x080c, 0x0cf1,
+	0x0005, 0x4023, 0x4036, 0x4060, 0x4080, 0x40a6, 0x40d5, 0x40fb,
+	0x4133, 0x4159, 0x4187, 0x41c0, 0x41f8, 0x4216, 0x4241, 0x4263,
+	0x427a, 0x4282, 0x42b4, 0x42da, 0x4309, 0x432f, 0x4367, 0x43a6,
+	0x43db, 0x43f9, 0x4452, 0x4474, 0x449e, 0x449f, 0x00c6, 0x2061,
+	0x1100, 0x6003, 0x0007, 0x2061, 0x0100, 0x6004, 0x9084, 0xfff9,
+	0x6006, 0x00ce, 0x0005, 0x2061, 0x0140, 0x605b, 0xbc94, 0x605f,
+	0xf0f0, 0x2061, 0x0100, 0x6043, 0x0002, 0x708b, 0x0001, 0x2009,
+	0x07d0, 0x2011, 0x4586, 0x080c, 0x65e1, 0x0005, 0x00f6, 0x7080,
+	0x9086, 0x0014, 0x1518, 0x6043, 0x0000, 0x6020, 0xd0b4, 0x11f0,
+	0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30, 0x9296, 0x1102, 0x11a0,
+	0x7834, 0x9005, 0x1188, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0x9005,
+	0x1110, 0x70b7, 0x0001, 0x2011, 0x4586, 0x080c, 0x655b, 0x708b,
+	0x0010, 0x080c, 0x4282, 0x0010, 0x7083, 0x0000, 0x00fe, 0x0005,
+	0x00f6, 0x708b, 0x0003, 0x6043, 0x0004, 0x2011, 0x4586, 0x080c,
+	0x655b, 0x080c, 0x4686, 0x2079, 0x0240, 0x7833, 0x1102, 0x7837,
+	0x0000, 0x20a9, 0x0008, 0x9f88, 0x000e, 0x200b, 0x0000, 0x8108,
+	0x1f04, 0x4075, 0x60c3, 0x0014, 0x080c, 0x45b2, 0x00fe, 0x0005,
+	0x00f6, 0x7080, 0x9005, 0x0500, 0x2011, 0x4586, 0x080c, 0x655b,
+	0x9086, 0x0014, 0x11b8, 0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30,
+	0x9296, 0x1102, 0x1178, 0x7834, 0x9005, 0x1160, 0x7a38, 0xd2fc,
+	0x0128, 0x70b4, 0x9005, 0x1110, 0x70b7, 0x0001, 0x708b, 0x0004,
+	0x0029, 0x0010, 0x080c, 0x46d6, 0x00fe, 0x0005, 0x00f6, 0x708b,
+	0x0005, 0x080c, 0x4686, 0x2079, 0x0240, 0x7833, 0x1103, 0x7837,
+	0x0000, 0x080c, 0x46fa, 0x080c, 0x46dd, 0x1170, 0x7074, 0x9005,
+	0x1158, 0x714c, 0x9186, 0xffff, 0x0138, 0x2011, 0x0008, 0x080c,
+	0x4532, 0x0168, 0x080c, 0x46bb, 0x20a9, 0x0008, 0x20e1, 0x0000,
+	0x2099, 0x026e, 0x20e9, 0x0000, 0x20a1, 0x024e, 0x4003, 0x60c3,
+	0x0014, 0x080c, 0x45b2, 0x00fe, 0x0005, 0x00f6, 0x7080, 0x9005,
+	0x0500, 0x2011, 0x4586, 0x080c, 0x655b, 0x9086, 0x0014, 0x11b8,
+	0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30, 0x9296, 0x1103, 0x1178,
+	0x7834, 0x9005, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0x9005,
+	0x1110, 0x70b7, 0x0001, 0x708b, 0x0006, 0x0029, 0x0010, 0x080c,
+	0x46d6, 0x00fe, 0x0005, 0x00f6, 0x708b, 0x0007, 0x080c, 0x4686,
+	0x2079, 0x0240, 0x7833, 0x1104, 0x7837, 0x0000, 0x080c, 0x46fa,
+	0x080c, 0x46dd, 0x11b8, 0x7074, 0x9005, 0x11a0, 0x7154, 0x9186,
+	0xffff, 0x0180, 0x9180, 0x26c1, 0x200d, 0x918c, 0xff00, 0x810f,
+	0x2011, 0x0008, 0x080c, 0x4532, 0x0180, 0x080c, 0x39eb, 0x0110,
+	0x080c, 0x1cb3, 0x20a9, 0x0008, 0x20e1, 0x0000, 0x2099, 0x026e,
+	0x20e9, 0x0000, 0x20a1, 0x024e, 0x4003, 0x60c3, 0x0014, 0x080c,
+	0x45b2, 0x00fe, 0x0005, 0x00f6, 0x7080, 0x9005, 0x0500, 0x2011,
+	0x4586, 0x080c, 0x655b, 0x9086, 0x0014, 0x11b8, 0x080c, 0x46fa,
+	0x2079, 0x0260, 0x7a30, 0x9296, 0x1104, 0x1178, 0x7834, 0x9005,
+	0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110, 0x70b7,
+	0x0001, 0x708b, 0x0008, 0x0029, 0x0010, 0x080c, 0x46d6, 0x00fe,
+	0x0005, 0x00f6, 0x708b, 0x0009, 0x080c, 0x4686, 0x2079, 0x0240,
+	0x7833, 0x1105, 0x7837, 0x0100, 0x080c, 0x46dd, 0x1150, 0x7074,
+	0x9005, 0x1138, 0x080c, 0x44a0, 0x1188, 0x9085, 0x0001, 0x080c,
+	0x1cb3, 0x20a9, 0x0008, 0x080c, 0x46fa, 0x20e1, 0x0000, 0x2099,
+	0x026e, 0x20e9, 0x0000, 0x20a1, 0x024e, 0x4003, 0x60c3, 0x0014,
+	0x080c, 0x45b2, 0x0010, 0x080c, 0x4016, 0x00fe, 0x0005, 0x00f6,
+	0x7080, 0x9005, 0x0598, 0x2011, 0x4586, 0x080c, 0x655b, 0x9086,
+	0x0014, 0x1550, 0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30, 0x9296,
+	0x1105, 0x1510, 0x7834, 0x2011, 0x0100, 0x921e, 0x1160, 0x7a38,
+	0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110, 0x70b7, 0x0001, 0x708b,
+	0x000a, 0x00b1, 0x0098, 0x9005, 0x1178, 0x7a38, 0xd2fc, 0x0128,
+	0x70b4, 0x9005, 0x1110, 0x70b7, 0x0001, 0x7087, 0x0000, 0x708b,
+	0x000e, 0x080c, 0x4263, 0x0010, 0x080c, 0x46d6, 0x00fe, 0x0005,
+	0x00f6, 0x708b, 0x000b, 0x2011, 0x150e, 0x20e9, 0x0001, 0x22a0,
+	0x20a9, 0x0040, 0x2019, 0xffff, 0x4304, 0x080c, 0x4686, 0x2079,
+	0x0240, 0x7833, 0x1106, 0x7837, 0x0000, 0x080c, 0x46dd, 0x0118,
+	0x2013, 0x0000, 0x0020, 0x7050, 0x9085, 0x0100, 0x2012, 0x20a9,
+	0x0040, 0x2009, 0x024e, 0x2011, 0x150e, 0x220e, 0x8210, 0x8108,
+	0x9186, 0x0260, 0x1128, 0x6810, 0x8000, 0x6812, 0x2009, 0x0240,
+	0x1f04, 0x41e5, 0x60c3, 0x0084, 0x080c, 0x45b2, 0x00fe, 0x0005,
+	0x00f6, 0x7080, 0x9005, 0x01c0, 0x2011, 0x4586, 0x080c, 0x655b,
+	0x9086, 0x0084, 0x1178, 0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30,
+	0x9296, 0x1106, 0x1138, 0x7834, 0x9005, 0x1120, 0x708b, 0x000c,
+	0x0029, 0x0010, 0x080c, 0x46d6, 0x00fe, 0x0005, 0x00f6, 0x708b,
+	0x000d, 0x080c, 0x4686, 0x2079, 0x0240, 0x7833, 0x1107, 0x7837,
+	0x0000, 0x080c, 0x46fa, 0x20a9, 0x0040, 0x2011, 0x026e, 0x2009,
+	0x024e, 0x220e, 0x8210, 0x8108, 0x9186, 0x0260, 0x1150, 0x6810,
+	0x8000, 0x6812, 0x2009, 0x0240, 0x6814, 0x8000, 0x6816, 0x2011,
+	0x0260, 0x1f04, 0x4229, 0x60c3, 0x0084, 0x080c, 0x45b2, 0x00fe,
+	0x0005, 0x00f6, 0x7080, 0x9005, 0x01e0, 0x2011, 0x4586, 0x080c,
+	0x655b, 0x9086, 0x0084, 0x1198, 0x080c, 0x46fa, 0x2079, 0x0260,
+	0x7a30, 0x9296, 0x1107, 0x1158, 0x7834, 0x9005, 0x1140, 0x7087,
+	0x0001, 0x080c, 0x4658, 0x708b, 0x000e, 0x0029, 0x0010, 0x080c,
+	0x46d6, 0x00fe, 0x0005, 0x708b, 0x000f, 0x7083, 0x0000, 0x2061,
+	0x0140, 0x605b, 0xbc85, 0x605f, 0xb5b5, 0x2061, 0x0100, 0x6043,
+	0x0005, 0x6043, 0x0004, 0x2009, 0x07d0, 0x2011, 0x4586, 0x080c,
+	0x654f, 0x0005, 0x7080, 0x9005, 0x0120, 0x2011, 0x4586, 0x080c,
+	0x655b, 0x0005, 0x708b, 0x0011, 0x080c, 0x7e9b, 0x080c, 0x46fa,
+	0x20e1, 0x0000, 0x2099, 0x0260, 0x20e9, 0x0000, 0x20a1, 0x0240,
+	0x7480, 0x9480, 0x0018, 0x9080, 0x0007, 0x9084, 0x03f8, 0x8004,
+	0x20a8, 0x4003, 0x080c, 0x46dd, 0x1190, 0x716c, 0x81ff, 0x0178,
+	0x2009, 0x0000, 0x7070, 0x9084, 0x00ff, 0x0148, 0x080c, 0x1c69,
+	0x9186, 0x0080, 0x0120, 0x2011, 0x0008, 0x080c, 0x4532, 0x60c3,
+	0x0014, 0x080c, 0x45b2, 0x0005, 0x00f6, 0x7080, 0x9005, 0x0500,
+	0x2011, 0x4586, 0x080c, 0x655b, 0x9086, 0x0014, 0x11b8, 0x080c,
+	0x46fa, 0x2079, 0x0260, 0x7a30, 0x9296, 0x1103, 0x1178, 0x7834,
+	0x9005, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110,
+	0x70b7, 0x0001, 0x708b, 0x0012, 0x0029, 0x0010, 0x7083, 0x0000,
+	0x00fe, 0x0005, 0x00f6, 0x708b, 0x0013, 0x080c, 0x4694, 0x2079,
+	0x0240, 0x7833, 0x1103, 0x7837, 0x0000, 0x080c, 0x46fa, 0x080c,
+	0x46dd, 0x1170, 0x7074, 0x9005, 0x1158, 0x714c, 0x9186, 0xffff,
+	0x0138, 0x2011, 0x0008, 0x080c, 0x4532, 0x0168, 0x080c, 0x46bb,
+	0x20a9, 0x0008, 0x20e1, 0x0000, 0x2099, 0x026e, 0x20e9, 0x0000,
+	0x20a1, 0x024e, 0x4003, 0x60c3, 0x0014, 0x080c, 0x45b2, 0x00fe,
+	0x0005, 0x00f6, 0x7080, 0x9005, 0x0500, 0x2011, 0x4586, 0x080c,
+	0x655b, 0x9086, 0x0014, 0x11b8, 0x080c, 0x46fa, 0x2079, 0x0260,
+	0x7a30, 0x9296, 0x1104, 0x1178, 0x7834, 0x9005, 0x1160, 0x7a38,
+	0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110, 0x70b7, 0x0001, 0x708b,
+	0x0014, 0x0029, 0x0010, 0x7083, 0x0000, 0x00fe, 0x0005, 0x00f6,
+	0x708b, 0x0015, 0x080c, 0x4694, 0x2079, 0x0240, 0x7833, 0x1104,
+	0x7837, 0x0000, 0x080c, 0x46fa, 0x080c, 0x46dd, 0x11b8, 0x7074,
+	0x9005, 0x11a0, 0x7154, 0x9186, 0xffff, 0x0180, 0x9180, 0x26c1,
+	0x200d, 0x918c, 0xff00, 0x810f, 0x2011, 0x0008, 0x080c, 0x4532,
+	0x0180, 0x080c, 0x39eb, 0x0110, 0x080c, 0x1cb3, 0x20a9, 0x0008,
+	0x20e1, 0x0000, 0x2099, 0x026e, 0x20e9, 0x0000, 0x20a1, 0x024e,
+	0x4003, 0x60c3, 0x0014, 0x080c, 0x45b2, 0x00fe, 0x0005, 0x00f6,
+	0x7080, 0x9005, 0x05c8, 0x2011, 0x4586, 0x080c, 0x655b, 0x9086,
+	0x0014, 0x1580, 0x080c, 0x46fa, 0x2079, 0x0260, 0x7a30, 0x9296,
+	0x1105, 0x1540, 0x7834, 0x2011, 0x0100, 0x921e, 0x1148, 0x7a38,
+	0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110, 0x70b7, 0x0001, 0x0060,
+	0x9005, 0x11c0, 0x7a38, 0xd2fc, 0x0128, 0x70b4, 0x9005, 0x1110,
+	0x70b7, 0x0001, 0x7087, 0x0000, 0x7a38, 0xd2f4, 0x0138, 0x2001,
+	0x1174, 0x2004, 0xd0a4, 0x1110, 0x70cf, 0x0008, 0x708b, 0x0016,
+	0x0029, 0x0010, 0x7083, 0x0000, 0x00fe, 0x0005, 0x080c, 0x7e9b,
+	0x080c, 0x46fa, 0x20e1, 0x0000, 0x2099, 0x0260, 0x20e9, 0x0000,
+	0x20a1, 0x0240, 0x20a9, 0x000e, 0x4003, 0x2011, 0x026e, 0x708b,
+	0x0017, 0x080c, 0x46dd, 0x1150, 0x7074, 0x9005, 0x1138, 0x080c,
+	0x44a0, 0x1188, 0x9085, 0x0001, 0x080c, 0x1cb3, 0x20a9, 0x0008,
+	0x080c, 0x46fa, 0x20e1, 0x0000, 0x2099, 0x026e, 0x20e9, 0x0000,
+	0x20a1, 0x024e, 0x4003, 0x60c3, 0x0014, 0x080c, 0x45b2, 0x0010,
+	0x080c, 0x4016, 0x0005, 0x00f6, 0x7080, 0x9005, 0x01c0, 0x2011,
+	0x4586, 0x080c, 0x655b, 0x9086, 0x0084, 0x1178, 0x080c, 0x46fa,
+	0x2079, 0x0260, 0x7a30, 0x9296, 0x1106, 0x1138, 0x7834, 0x9005,
+	0x1120, 0x708b, 0x0018, 0x0029, 0x0010, 0x7083, 0x0000, 0x00fe,
+	0x0005, 0x00f6, 0x708b, 0x0019, 0x080c, 0x4694, 0x2079, 0x0240,
+	0x7833, 0x1106, 0x7837, 0x0000, 0x080c, 0x46fa, 0x2009, 0x026e,
+	0x2039, 0x150e, 0x20a9, 0x0040, 0x213e, 0x8738, 0x8108, 0x9186,
+	0x0280, 0x1128, 0x6814, 0x8000, 0x6816, 0x2009, 0x0260, 0x1f04,
+	0x440c, 0x2039, 0x150e, 0x080c, 0x46dd, 0x11e8, 0x2728, 0x2514,
+	0x8207, 0x9084, 0x00ff, 0x8000, 0x2018, 0x9294, 0x00ff, 0x8007,
+	0x9205, 0x202a, 0x7050, 0x2310, 0x8214, 0x92a0, 0x150e, 0x2414,
+	0x938c, 0x0001, 0x0118, 0x9294, 0xff00, 0x0018, 0x9294, 0x00ff,
+	0x8007, 0x9215, 0x2222, 0x20a9, 0x0040, 0x2009, 0x024e, 0x270e,
+	0x8738, 0x8108, 0x9186, 0x0260, 0x1128, 0x6810, 0x8000, 0x6812,
+	0x2009, 0x0240, 0x1f04, 0x443f, 0x60c3, 0x0084, 0x080c, 0x45b2,
+	0x00fe, 0x0005, 0x00f6, 0x7080, 0x9005, 0x01e0, 0x2011, 0x4586,
+	0x080c, 0x655b, 0x9086, 0x0084, 0x1198, 0x080c, 0x46fa, 0x2079,
+	0x0260, 0x7a30, 0x9296, 0x1107, 0x1158, 0x7834, 0x9005, 0x1140,
+	0x7087, 0x0001, 0x080c, 0x4658, 0x708b, 0x001a, 0x0029, 0x0010,
+	0x7083, 0x0000, 0x00fe, 0x0005, 0x708b, 0x001b, 0x080c, 0x7e9b,
+	0x080c, 0x46fa, 0x2011, 0x0260, 0x2009, 0x0240, 0x7480, 0x9480,
+	0x0018, 0x9080, 0x0007, 0x9084, 0x03f8, 0x8004, 0x20a8, 0x220e,
+	0x8210, 0x8108, 0x9186, 0x0260, 0x1150, 0x6810, 0x8000, 0x6812,
+	0x2009, 0x0240, 0x6814, 0x8000, 0x6816, 0x2011, 0x0260, 0x1f04,
+	0x4487, 0x60c3, 0x0084, 0x080c, 0x45b2, 0x0005, 0x0005, 0x0005,
+	0x0086, 0x0096, 0x2029, 0x1153, 0x252c, 0x20a9, 0x0008, 0x2041,
+	0x150e, 0x20e9, 0x0001, 0x28a0, 0x080c, 0x46fa, 0x20e1, 0x0000,
+	0x2099, 0x026e, 0x4003, 0x20a9, 0x0008, 0x2011, 0x0007, 0xd5d4,
+	0x0110, 0x2011, 0x0000, 0x2800, 0x9200, 0x200c, 0x91a6, 0xffff,
+	0x1148, 0xd5d4, 0x0110, 0x8210, 0x0008, 0x8211, 0x1f04, 0x44bb,
+	0x0804, 0x452a, 0x82ff, 0x1160, 0xd5d4, 0x0120, 0x91a6, 0x3fff,
+	0x0d90, 0x0020, 0x91a6, 0x3fff, 0x0904, 0x452a, 0x918d, 0xc000,
+	0x20a9, 0x0010, 0x2019, 0x0001, 0xd5d4, 0x0110, 0x2019, 0x0010,
+	0x2120, 0xd5d4, 0x0110, 0x8423, 0x0008, 0x8424, 0x1240, 0xd5d4,
+	0x0110, 0x8319, 0x0008, 0x8318, 0x1f04, 0x44e1, 0x04d8, 0x23a8,
+	0x2021, 0x0001, 0x8426, 0x8425, 0x1f04, 0x44f3, 0x2328, 0x8529,
+	0x92be, 0x0007, 0x0158, 0x0006, 0x2039, 0x0007, 0x2200, 0x973a,
+	0x000e, 0x27a8, 0x95a8, 0x0010, 0x1f04, 0x4502, 0x754e, 0x95c8,
+	0x26c1, 0x292d, 0x95ac, 0x00ff, 0x7572, 0x6532, 0x6536, 0x0016,
+	0x2508, 0x080c, 0x1c93, 0x001e, 0x60e7, 0x0000, 0x65ea, 0x2018,
+	0x2304, 0x9405, 0x201a, 0x7077, 0x0001, 0x20e9, 0x0000, 0x20a1,
+	0x024e, 0x20e1, 0x0001, 0x2898, 0x20a9, 0x0008, 0x4003, 0x9085,
+	0x0001, 0x0028, 0x9006, 0x0018, 0x9006, 0x080c, 0x0cf1, 0x009e,
+	0x008e, 0x0005, 0x0156, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x22a8,
+	0x20e1, 0x0000, 0x2099, 0x026e, 0x20e9, 0x0000, 0x2011, 0x024e,
+	0x22a0, 0x4003, 0x014e, 0x013e, 0x01de, 0x01ce, 0x015e, 0x2118,
+	0x2021, 0x0000, 0x2001, 0x0007, 0x939a, 0x0010, 0x0218, 0x8420,
+	0x8001, 0x0cd0, 0x2118, 0x84ff, 0x0120, 0x939a, 0x0010, 0x8421,
+	0x1de0, 0x2021, 0x0001, 0x83ff, 0x0118, 0x8423, 0x8319, 0x1de8,
+	0x9238, 0x2029, 0x026e, 0x9528, 0x2504, 0x942c, 0x11b8, 0x9405,
+	0x203a, 0x714e, 0x91a0, 0x26c1, 0x242d, 0x95ac, 0x00ff, 0x7572,
+	0x6532, 0x6536, 0x0016, 0x2508, 0x080c, 0x1c93, 0x001e, 0x60e7,
+	0x0000, 0x65ea, 0x7077, 0x0001, 0x9084, 0x0000, 0x0005, 0x00e6,
+	0x2071, 0x1100, 0x707b, 0x0000, 0x00ee, 0x0005, 0x00e6, 0x00f6,
+	0x2079, 0x0100, 0x2071, 0x0140, 0x080c, 0x4647, 0x080c, 0x7721,
+	0x7004, 0x9084, 0x4000, 0x0120, 0x7003, 0x1000, 0x7003, 0x0000,
+	0x0126, 0x2091, 0x8000, 0x2071, 0x1122, 0x2073, 0x0000, 0x7840,
+	0x0026, 0x0016, 0x2009, 0x00f7, 0x080c, 0x46a4, 0x001e, 0x9094,
+	0x0010, 0x9285, 0x0080, 0x7842, 0x7a42, 0x002e, 0x012e, 0x00fe,
+	0x00ee, 0x0005, 0x0126, 0x2091, 0x8000, 0x2011, 0x12e6, 0x2013,
+	0x0000, 0x7083, 0x0000, 0x012e, 0x60a3, 0x0056, 0x60a7, 0x9575,
+	0x080c, 0x7718, 0x6144, 0xd184, 0x0120, 0x7188, 0x918d, 0x2000,
+	0x0018, 0x717c, 0x918d, 0x1000, 0x2011, 0x12b9, 0x2112, 0x2009,
+	0x07d0, 0x2011, 0x4586, 0x080c, 0x65e1, 0x0005, 0x0016, 0x0026,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x2011, 0x0003, 0x080c, 0x79c2,
+	0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf,
+	0x0036, 0x2019, 0x0000, 0x080c, 0x7936, 0x003e, 0x2009, 0x00f7,
+	0x080c, 0x46a4, 0x2061, 0x12ef, 0x601b, 0x0000, 0x601f, 0x0000,
+	0x2061, 0x1100, 0x6003, 0x0001, 0x2061, 0x0100, 0x6043, 0x0090,
+	0x6043, 0x0010, 0x2009, 0x12b9, 0x200b, 0x0000, 0x2009, 0x002d,
+	0x2011, 0x4611, 0x080c, 0x654f, 0x012e, 0x00ce, 0x002e, 0x001e,
+	0x0005, 0x00e6, 0x0006, 0x0126, 0x2091, 0x8000, 0x0481, 0x2071,
+	0x0100, 0x080c, 0x7721, 0x2071, 0x0140, 0x7004, 0x9084, 0x4000,
+	0x0120, 0x7003, 0x1000, 0x7003, 0x0000, 0x080c, 0x574d, 0x01a8,
+	0x080c, 0x576b, 0x1190, 0x2001, 0x128f, 0x2003, 0xaaaa, 0x0016,
+	0x080c, 0x1d69, 0x2001, 0x1280, 0x2102, 0x001e, 0x2001, 0x1290,
+	0x2003, 0x0000, 0x080c, 0x5682, 0x0030, 0x2001, 0x0001, 0x080c,
+	0x1c36, 0x080c, 0x45d6, 0x012e, 0x000e, 0x00ee, 0x0005, 0x2001,
+	0x110d, 0x2004, 0xd0bc, 0x0158, 0x0026, 0x0036, 0x2011, 0x8017,
+	0x2001, 0x12b9, 0x201c, 0x080c, 0x37dc, 0x003e, 0x002e, 0x0005,
+	0x20a9, 0x0012, 0x20e9, 0x0001, 0x20a1, 0x1580, 0x080c, 0x46fa,
+	0x20e9, 0x0000, 0x2099, 0x026e, 0x0099, 0x20a9, 0x0020, 0x080c,
+	0x46f4, 0x2099, 0x0260, 0x20a1, 0x1592, 0x0051, 0x20a9, 0x000e,
+	0x080c, 0x46f7, 0x2099, 0x0260, 0x20a1, 0x15b2, 0x0009, 0x0005,
+	0x0016, 0x0026, 0x3410, 0x3308, 0x2104, 0x8007, 0x2012, 0x8108,
+	0x8210, 0x1f04, 0x467c, 0x002e, 0x001e, 0x0005, 0x080c, 0x7e9b,
+	0x20e1, 0x0001, 0x2099, 0x1500, 0x20e9, 0x0000, 0x20a1, 0x0240,
+	0x20a9, 0x000c, 0x4003, 0x0005, 0x080c, 0x7e9b, 0x080c, 0x46fa,
+	0x20e1, 0x0000, 0x2099, 0x0260, 0x20e9, 0x0000, 0x20a1, 0x0240,
+	0x20a9, 0x000c, 0x4003, 0x0005, 0x00c6, 0x0006, 0x2061, 0x0100,
+	0x810f, 0x2001, 0x1130, 0x2004, 0x9005, 0x1138, 0x2001, 0x1114,
+	0x2004, 0x9084, 0x00ff, 0x9105, 0x0010, 0x9185, 0x00f7, 0x604a,
+	0x000e, 0x00ce, 0x0005, 0x0016, 0x0046, 0x2001, 0x1153, 0x2004,
+	0xd0a4, 0x0158, 0x9006, 0x2020, 0x2009, 0x002a, 0x080c, 0xaaca,
+	0x2001, 0x110c, 0x200c, 0xc195, 0x2102, 0x2019, 0x002a, 0x2009,
+	0x0000, 0x080c, 0x2582, 0x004e, 0x001e, 0x0005, 0x080c, 0x45d6,
+	0x708b, 0x0000, 0x7083, 0x0000, 0x0005, 0x0006, 0x2001, 0x110c,
+	0x2004, 0xd09c, 0x0100, 0x000e, 0x0005, 0x0006, 0x0016, 0x0126,
+	0x2091, 0x8000, 0x2001, 0x0101, 0x200c, 0x918d, 0x0006, 0x2102,
+	0x012e, 0x001e, 0x000e, 0x0005, 0x2009, 0x0001, 0x0028, 0x2009,
+	0x0002, 0x0010, 0x2009, 0x0000, 0x6814, 0x9084, 0xffc0, 0x910d,
+	0x6916, 0x0005, 0x00f6, 0x0156, 0x0146, 0x01d6, 0x9006, 0x20a9,
+	0x0080, 0x20e9, 0x0001, 0x20a1, 0x1500, 0x4004, 0x2079, 0x1500,
+	0x7803, 0x2200, 0x7807, 0x00ef, 0x780f, 0x00ef, 0x7813, 0x0138,
+	0x7823, 0xffff, 0x7827, 0xffff, 0x01de, 0x014e, 0x015e, 0x00fe,
+	0x0005, 0x0156, 0x20a9, 0x00ff, 0x2009, 0x1000, 0x9006, 0x200a,
+	0x8108, 0x1f04, 0x4727, 0x015e, 0x0005, 0x00d6, 0x0036, 0x0156,
+	0x0136, 0x0146, 0x2069, 0x1152, 0x9006, 0x6002, 0x6007, 0x0707,
+	0x600a, 0x600e, 0x6012, 0x9198, 0x26c1, 0x231d, 0x939c, 0x00ff,
+	0x6316, 0x20a9, 0x0004, 0x9c98, 0x0006, 0x20e9, 0x0001, 0x23a0,
+	0x4004, 0x20a9, 0x0004, 0x9c98, 0x000a, 0x23a0, 0x4004, 0x603e,
+	0x6042, 0x604e, 0x6052, 0x6056, 0x605a, 0x605e, 0x6062, 0x6066,
+	0x606a, 0x606e, 0x6072, 0x6076, 0x607a, 0x608a, 0x608e, 0x6092,
+	0x6096, 0x609a, 0x609e, 0x60ae, 0x61a2, 0x00d6, 0x60a4, 0x906d,
+	0x0110, 0x080c, 0x0df6, 0x60a7, 0x0000, 0x00de, 0x9006, 0x604a,
+	0x6810, 0x603a, 0x680c, 0x6046, 0x6814, 0x9084, 0x00ff, 0x6042,
+	0x014e, 0x013e, 0x015e, 0x003e, 0x00de, 0x0005, 0x0126, 0x2091,
+	0x8000, 0x6974, 0x6e78, 0x9684, 0x3fff, 0x9082, 0x4000, 0x1a04,
+	0x47f0, 0x918c, 0xff00, 0x810f, 0x9182, 0x00ff, 0x1a04, 0x47f5,
+	0x2001, 0x110c, 0x2004, 0x9084, 0x0003, 0x1904, 0x47fc, 0x9188,
+	0x1000, 0x2104, 0x9065, 0x0508, 0x6004, 0x9084, 0x00ff, 0x908e,
+	0x0006, 0x1500, 0x60a4, 0x900d, 0x1904, 0x4811, 0x6050, 0x900d,
+	0x1148, 0x6802, 0x2d00, 0x6052, 0x604e, 0x080c, 0x68a3, 0x9006,
+	0x012e, 0x0005, 0x2d00, 0x200a, 0x6803, 0x0000, 0x6052, 0x0ca8,
+	0x2001, 0x0005, 0x2009, 0x0000, 0x04e0, 0x2001, 0x0028, 0x2009,
+	0x0000, 0x04b8, 0x9082, 0x0006, 0x1298, 0x2001, 0x1133, 0x2004,
+	0xd0ac, 0x1158, 0x60a0, 0xd0bc, 0x1140, 0x6100, 0xd1fc, 0x0990,
+	0x2001, 0x0029, 0x2009, 0x1000, 0x0420, 0x2001, 0x0028, 0x00a8,
+	0x2009, 0x110c, 0x210c, 0xd18c, 0x0118, 0x2001, 0x0004, 0x0068,
+	0xd184, 0x0118, 0x2001, 0x0004, 0x0040, 0x2001, 0x0029, 0x6100,
+	0xd1fc, 0x0118, 0x2009, 0x1000, 0x0060, 0x2009, 0x0000, 0x0048,
+	0x2001, 0x0029, 0x2009, 0x0000, 0x0020, 0x2001, 0x0029, 0x2009,
+	0x0000, 0x9005, 0x012e, 0x0005, 0x2001, 0x110c, 0x2004, 0xd084,
+	0x19b8, 0x9188, 0x1000, 0x2104, 0x9065, 0x0990, 0x6004, 0x9084,
+	0x00ff, 0x908e, 0x0006, 0x1960, 0x6000, 0xd0c4, 0x0948, 0x0804,
+	0x47a2, 0x080c, 0x4cdc, 0x0904, 0x47b8, 0x0804, 0x47a6, 0x00e6,
+	0x0126, 0x2091, 0x8000, 0x6874, 0x8007, 0x9084, 0x00ff, 0x2008,
+	0x9182, 0x00ff, 0x1a04, 0x486a, 0x9188, 0x1000, 0x2104, 0x9065,
+	0x01c0, 0x6004, 0x9084, 0x00ff, 0x908e, 0x0006, 0x11a8, 0x2c70,
+	0x080c, 0x7ec8, 0x05e8, 0x2e00, 0x6012, 0x2d00, 0x6016, 0x600b,
+	0xffff, 0x6023, 0x000a, 0x2009, 0x0003, 0x080c, 0x7f4e, 0x9006,
+	0x0460, 0x2001, 0x0028, 0x0440, 0x9082, 0x0006, 0x1298, 0x2001,
+	0x1133, 0x2004, 0xd0ac, 0x1158, 0x60a0, 0xd0bc, 0x1140, 0x6100,
+	0xd1fc, 0x09e8, 0x2001, 0x0029, 0x2009, 0x1000, 0x00a8, 0x2001,
+	0x0028, 0x0090, 0x2009, 0x110c, 0x210c, 0xd18c, 0x0118, 0x2001,
+	0x0004, 0x0050, 0xd184, 0x0118, 0x2001, 0x0004, 0x0028, 0x2001,
+	0x0029, 0x0010, 0x2001, 0x0029, 0x9005, 0x012e, 0x00ee, 0x0005,
+	0x2001, 0x002c, 0x0cc8, 0x00f6, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x2011, 0x0000, 0x2079, 0x1100, 0x6974, 0x918c, 0xff00, 0x810f,
+	0x9182, 0x00ff, 0x1a04, 0x4a12, 0x2001, 0x110c, 0x2004, 0x9084,
+	0x0003, 0x1904, 0x49ff, 0x080c, 0x4b58, 0x1180, 0x6004, 0x9084,
+	0x00ff, 0x9082, 0x0006, 0x1250, 0x2001, 0x1133, 0x2004, 0xd0ac,
+	0x1904, 0x49f9, 0x60a0, 0xd0bc, 0x1904, 0x49f9, 0x6894, 0x90c6,
+	0x006f, 0x0158, 0x90c6, 0x005e, 0x0904, 0x4940, 0x90c6, 0x0064,
+	0x0904, 0x4974, 0x2008, 0x0804, 0x4909, 0x6998, 0x2140, 0x918c,
+	0xff00, 0x810f, 0x78cc, 0xd0ac, 0x1120, 0x9182, 0x0080, 0x0a04,
+	0x4909, 0x9182, 0x00ff, 0x1a04, 0x4909, 0x6aa0, 0x6b9c, 0x786c,
+	0x9306, 0x1168, 0x7870, 0x924e, 0x1120, 0x2208, 0x2310, 0x0804,
+	0x4909, 0x99cc, 0xff00, 0x1118, 0x2208, 0x2310, 0x04d0, 0x080c,
+	0x36d2, 0x2c70, 0x05f0, 0x2009, 0x0000, 0x2011, 0x0000, 0x90c6,
+	0x4000, 0x1500, 0x0006, 0x2e60, 0x080c, 0x4d21, 0x1108, 0xc185,
+	0x7000, 0xd0bc, 0x0108, 0xc18d, 0x20a9, 0x0004, 0x9d80, 0x0031,
+	0x20a0, 0x9e80, 0x0006, 0x2098, 0x080c, 0x4678, 0x20a9, 0x0004,
+	0x9d80, 0x0035, 0x20a0, 0x9e80, 0x000a, 0x2098, 0x080c, 0x4678,
+	0x000e, 0x0088, 0x90c6, 0x4007, 0x1110, 0x2408, 0x0060, 0x90c6,
+	0x4008, 0x1118, 0x2708, 0x2610, 0x0030, 0x90c6, 0x4009, 0x1108,
+	0x0010, 0x2001, 0x4006, 0x6896, 0x699a, 0x6a9e, 0x2001, 0x0030,
+	0x0450, 0x080c, 0x7ec8, 0x1138, 0x2001, 0x4005, 0x2009, 0x0003,
+	0x2011, 0x0000, 0x0c80, 0x2e00, 0x6012, 0x080c, 0x99cc, 0x2d00,
+	0x6016, 0x6023, 0x0001, 0x6868, 0xd88c, 0x0108, 0xc0f5, 0x686a,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x25ad, 0x012e, 0x2001, 0x0000,
+	0x080c, 0x4aa1, 0x2001, 0x0002, 0x080c, 0x4ab3, 0x2009, 0x0002,
+	0x080c, 0x7f4e, 0x9006, 0x9005, 0x012e, 0x00ee, 0x00fe, 0x0005,
+	0x7800, 0x9086, 0x0003, 0x0118, 0x2009, 0x0007, 0x0448, 0x6e98,
+	0x860f, 0x918c, 0x00ff, 0x96b4, 0x00ff, 0x080c, 0x4b58, 0x0120,
+	0x2009, 0x000a, 0x0804, 0x4909, 0x9186, 0x007f, 0x0148, 0x6004,
+	0x9084, 0x00ff, 0x9086, 0x0006, 0x0118, 0x2009, 0x0009, 0x0080,
+	0x00d6, 0x080c, 0x0dc6, 0x1120, 0x00de, 0x2009, 0x0002, 0x0040,
+	0x2d00, 0x00de, 0x6806, 0x080c, 0x977b, 0x1960, 0x2009, 0x0003,
+	0x2001, 0x4005, 0x0804, 0x490b, 0x6e98, 0x860f, 0x918c, 0x00ff,
+	0x96b4, 0x00ff, 0x080c, 0x4b58, 0x0120, 0x2009, 0x000a, 0x0804,
+	0x4909, 0x00d6, 0x080c, 0x0dc6, 0x1128, 0x00de, 0x2009, 0x0002,
+	0x0804, 0x49dd, 0x2d00, 0x00de, 0x6806, 0x00d6, 0x6804, 0x2068,
+	0x20a9, 0x002b, 0x20e1, 0x0001, 0x2c98, 0x9de8, 0x0002, 0x20e9,
+	0x0001, 0x2da0, 0x4003, 0x20a9, 0x0004, 0x9d80, 0x0006, 0x20a0,
+	0x9c80, 0x0006, 0x2098, 0x080c, 0x4678, 0x20a9, 0x0004, 0x9d80,
+	0x000a, 0x20a0, 0x9c80, 0x000a, 0x2098, 0x080c, 0x4678, 0x2d10,
+	0x00de, 0x687b, 0x0000, 0x6883, 0x0000, 0x6897, 0x4000, 0xd684,
+	0x1170, 0x2001, 0x1153, 0x2004, 0xd0b4, 0x1118, 0x689b, 0x000b,
+	0x0400, 0x6000, 0xd08c, 0x0118, 0x689b, 0x000c, 0x00d0, 0x6004,
+	0x9084, 0x00ff, 0x9086, 0x0006, 0x0118, 0x689b, 0x0009, 0x0088,
+	0x7800, 0x9086, 0x0003, 0x0118, 0x689b, 0x0007, 0x0050, 0x080c,
+	0x9744, 0x1904, 0x493a, 0x2009, 0x0003, 0x2001, 0x4005, 0x0804,
+	0x490b, 0x687b, 0x0030, 0x6897, 0x4005, 0x2200, 0x2009, 0x002b,
+	0x6aa0, 0x6b9c, 0x6ca8, 0x6da4, 0x2031, 0x0000, 0x2039, 0x0001,
+	0x2041, 0x0f7e, 0x080c, 0x817f, 0x1904, 0x493a, 0x2009, 0x0002,
+	0x0c20, 0x2001, 0x0028, 0x2009, 0x0000, 0x0804, 0x493b, 0x2009,
+	0x110c, 0x210c, 0xd18c, 0x0118, 0x2001, 0x0004, 0x0038, 0xd184,
+	0x0118, 0x2001, 0x0004, 0x0010, 0x2001, 0x0029, 0x2009, 0x0000,
+	0x0804, 0x493b, 0x2001, 0x0029, 0x2009, 0x0000, 0x0804, 0x493b,
+	0x6974, 0x6e78, 0x9684, 0x3fff, 0x9082, 0x4000, 0x1658, 0x918c,
+	0xff00, 0x810f, 0x9182, 0x00ff, 0x1280, 0x9188, 0x1000, 0x2104,
+	0x9065, 0x0158, 0x6004, 0x9084, 0x00ff, 0x908e, 0x0006, 0x1150,
+	0x0491, 0x080c, 0x4c6e, 0x9006, 0x00c8, 0x2001, 0x0028, 0x2009,
+	0x0000, 0x00a0, 0x9082, 0x0006, 0x1240, 0x6100, 0xd1fc, 0x0d80,
+	0x2001, 0x0029, 0x2009, 0x1000, 0x0048, 0x2001, 0x0029, 0x2009,
+	0x0000, 0x0020, 0x2001, 0x0029, 0x2009, 0x0000, 0x9005, 0x0005,
+	0x0126, 0x2091, 0x8000, 0x6050, 0x900d, 0x0138, 0x2d00, 0x200a,
+	0x6803, 0x0000, 0x6052, 0x012e, 0x0005, 0x2d00, 0x6052, 0x604e,
+	0x6803, 0x0000, 0x0cc0, 0x0126, 0x2091, 0x8000, 0x604c, 0x9005,
+	0x0170, 0x00e6, 0x2071, 0x12dc, 0x7004, 0x9086, 0x0002, 0x0168,
+	0x00ee, 0x604c, 0x6802, 0x2d00, 0x604e, 0x012e, 0x0005, 0x2d00,
+	0x6052, 0x604e, 0x6803, 0x0000, 0x0cc0, 0x701c, 0x9c06, 0x1d80,
+	0x604c, 0x2070, 0x7000, 0x6802, 0x2d00, 0x7002, 0x00ee, 0x012e,
+	0x0005, 0x0126, 0x2091, 0x8000, 0x604c, 0x906d, 0x0130, 0x6800,
+	0x9005, 0x1108, 0x6052, 0x604e, 0x9d05, 0x012e, 0x0005, 0x604c,
+	0x906d, 0x0130, 0x6800, 0x9005, 0x1108, 0x6052, 0x604e, 0x9d05,
+	0x0005, 0x0126, 0x00c6, 0x0026, 0x2091, 0x8000, 0x6210, 0x2260,
+	0x6200, 0x9005, 0x0110, 0xc285, 0x0008, 0xc284, 0x6202, 0x002e,
+	0x00ce, 0x012e, 0x0005, 0x0126, 0x00c6, 0x2091, 0x8000, 0x6210,
+	0x2260, 0x6204, 0x0006, 0x9086, 0x0006, 0x1180, 0x609c, 0xd0ac,
+	0x0168, 0x2001, 0x1153, 0x2004, 0xd0a4, 0x0140, 0x9284, 0xff00,
+	0x8007, 0x9086, 0x0007, 0x1110, 0x2011, 0x0600, 0x000e, 0x9294,
+	0xff00, 0x9215, 0x6206, 0x0006, 0x9086, 0x0006, 0x1128, 0x6290,
+	0x82ff, 0x1110, 0x080c, 0x0cf1, 0x000e, 0x00ce, 0x012e, 0x0005,
+	0x0126, 0x00c6, 0x2091, 0x8000, 0x6210, 0x2260, 0x6204, 0x0006,
+	0x9086, 0x0006, 0x1178, 0x609c, 0xd0a4, 0x0160, 0x2001, 0x1153,
+	0x2004, 0xd0ac, 0x1138, 0x9284, 0x00ff, 0x9086, 0x0007, 0x1110,
+	0x2011, 0x0006, 0x000e, 0x9294, 0x00ff, 0x8007, 0x9215, 0x6206,
+	0x00ce, 0x012e, 0x0005, 0x0026, 0x9182, 0x00ff, 0x0218, 0x9085,
+	0x0001, 0x00a0, 0x9190, 0x1000, 0x2204, 0x9065, 0x1170, 0x0016,
+	0x00d6, 0x080c, 0x0dc6, 0x2d60, 0x00de, 0x001e, 0x0d80, 0x2c00,
+	0x2012, 0x60a7, 0x0000, 0x080c, 0x472d, 0x9006, 0x002e, 0x0005,
+	0x0126, 0x2091, 0x8000, 0x0026, 0x9182, 0x00ff, 0x0218, 0x9085,
+	0x0001, 0x0458, 0x00d6, 0x9190, 0x1000, 0x2204, 0x906d, 0x0518,
+	0x2013, 0x0000, 0x00d6, 0x00c6, 0x2d60, 0x60a4, 0x906d, 0x0110,
+	0x080c, 0x0df6, 0x00ce, 0x00de, 0x00d6, 0x00c6, 0x68ac, 0x2060,
+	0x8cff, 0x0168, 0x600c, 0x0006, 0x6014, 0x2068, 0x080c, 0x95d2,
+	0x0110, 0x080c, 0x0e06, 0x080c, 0x7f1e, 0x00ce, 0x0c88, 0x00ce,
+	0x00de, 0x080c, 0x0df6, 0x00de, 0x9006, 0x002e, 0x012e, 0x0005,
+	0x0016, 0x9182, 0x00ff, 0x0218, 0x9085, 0x0001, 0x0030, 0x9188,
+	0x1000, 0x2104, 0x9065, 0x0dc0, 0x9006, 0x001e, 0x0005, 0x00d6,
+	0x0156, 0x0136, 0x0146, 0x600b, 0x0000, 0x600f, 0x0000, 0x6000,
+	0xc08c, 0x6002, 0x080c, 0x5745, 0x1500, 0x60a0, 0x9086, 0x007e,
+	0x0130, 0x2001, 0x1133, 0x2004, 0xd0ac, 0x11b8, 0x0078, 0x7040,
+	0xd0e4, 0x0198, 0x00c6, 0x2061, 0x12a2, 0x7048, 0x2062, 0x704c,
+	0x6006, 0x7050, 0x600a, 0x7054, 0x600e, 0x00ce, 0x703c, 0x2069,
+	0x0140, 0x6886, 0x2069, 0x1100, 0x68a2, 0x7040, 0x605e, 0x7048,
+	0x6062, 0x6138, 0x910a, 0x0208, 0x603a, 0x704c, 0x6066, 0x20e1,
+	0x0000, 0x2099, 0x0276, 0x9c88, 0x000a, 0x20e9, 0x0001, 0x21a0,
+	0x20a9, 0x0004, 0x4003, 0x2099, 0x027a, 0x9c88, 0x0006, 0x21a0,
+	0x20a9, 0x0004, 0x4003, 0x2069, 0x0200, 0x6817, 0x0001, 0x7040,
+	0x606a, 0x7144, 0x616e, 0x7048, 0x6072, 0x7050, 0x6076, 0x2069,
+	0x0200, 0x6817, 0x0000, 0x60a0, 0x9086, 0x007e, 0x1110, 0x7144,
+	0x616e, 0x9182, 0x0211, 0x1218, 0x2009, 0x0008, 0x0400, 0x9182,
+	0x0259, 0x1218, 0x2009, 0x0007, 0x00d0, 0x9182, 0x02c1, 0x1218,
+	0x2009, 0x0006, 0x00a0, 0x9182, 0x0349, 0x1218, 0x2009, 0x0005,
+	0x0070, 0x9182, 0x0421, 0x1218, 0x2009, 0x0004, 0x0040, 0x9182,
+	0x0581, 0x1218, 0x2009, 0x0003, 0x0010, 0x2009, 0x0002, 0x6192,
+	0x014e, 0x013e, 0x015e, 0x00de, 0x0005, 0x0016, 0x0026, 0x00e6,
+	0x2071, 0x0260, 0x7034, 0x6896, 0x703c, 0x689a, 0x7054, 0x689e,
+	0x6a00, 0x2009, 0x1172, 0x210c, 0xd0bc, 0x0120, 0xd1ec, 0x0110,
+	0xc2ad, 0x0008, 0xc2ac, 0xd0c4, 0x0120, 0xd1e4, 0x0110, 0xc2bd,
+	0x0008, 0xc2bc, 0x6a02, 0x00ee, 0x002e, 0x001e, 0x0005, 0x00d6,
+	0x0126, 0x2091, 0x8000, 0x60a4, 0x906d, 0x01c0, 0x6900, 0x81ff,
+	0x1540, 0x6a04, 0x9282, 0x0010, 0x1648, 0x9d88, 0x0004, 0x20a9,
+	0x0010, 0x2104, 0x9086, 0xffff, 0x0128, 0x8108, 0x1f04, 0x4c29,
+	0x080c, 0x0cf1, 0x260a, 0x8210, 0x6a06, 0x0098, 0x080c, 0x0ddf,
+	0x01a8, 0x2d00, 0x60a6, 0x6803, 0x0000, 0x9d88, 0x0004, 0x20a9,
+	0x0010, 0x200b, 0xffff, 0x8108, 0x1f04, 0x4c41, 0x6807, 0x0001,
+	0x6e12, 0x9085, 0x0001, 0x012e, 0x00de, 0x0005, 0x9006, 0x0cd8,
+	0x0126, 0x2091, 0x8000, 0x00d6, 0x60a4, 0x900d, 0x01a0, 0x2168,
+	0x6800, 0x9005, 0x1160, 0x080c, 0x4cdc, 0x1168, 0x200b, 0xffff,
+	0x6804, 0x908a, 0x0002, 0x0218, 0x8001, 0x6806, 0x0020, 0x080c,
+	0x0df6, 0x60a7, 0x0000, 0x00de, 0x012e, 0x0005, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x68a3, 0x012e, 0x0005, 0x901e, 0x0010, 0x2019,
+	0x0001, 0x900e, 0x0126, 0x2091, 0x8000, 0x604c, 0x2068, 0x6000,
+	0xd0dc, 0x1170, 0x8dff, 0x01e8, 0x83ff, 0x0120, 0x6878, 0x9606,
+	0x0158, 0x0030, 0x686c, 0x9406, 0x1118, 0x6870, 0x9506, 0x0120,
+	0x2d08, 0x6800, 0x2068, 0x0c70, 0x6a00, 0x604c, 0x9d06, 0x1110,
+	0x624e, 0x0018, 0x9180, 0x0000, 0x2202, 0x82ff, 0x1110, 0x6152,
+	0x8dff, 0x012e, 0x0005, 0x9016, 0x0489, 0x1110, 0x2011, 0x0001,
+	0x0005, 0x080c, 0x4d21, 0x0118, 0x080c, 0x9685, 0x0010, 0x9085,
+	0x0001, 0x0005, 0x080c, 0x4d21, 0x0118, 0x080c, 0x9620, 0x0010,
+	0x9085, 0x0001, 0x0005, 0x080c, 0x4d21, 0x0118, 0x080c, 0x9668,
+	0x0010, 0x9085, 0x0001, 0x0005, 0x080c, 0x4d21, 0x0118, 0x080c,
+	0x963c, 0x0010, 0x9085, 0x0001, 0x0005, 0x080c, 0x4d21, 0x0118,
+	0x080c, 0x96a1, 0x0010, 0x9085, 0x0001, 0x0005, 0x60a4, 0x900d,
+	0x1118, 0x9085, 0x0001, 0x0005, 0x00e6, 0x2170, 0x7000, 0x9005,
+	0x1168, 0x20a9, 0x0010, 0x9e88, 0x0004, 0x2104, 0x9606, 0x0130,
+	0x8108, 0x1f04, 0x4ce5, 0x9085, 0x0001, 0x0008, 0x9006, 0x00ee,
+	0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4, 0x906d, 0x1128,
+	0x080c, 0x0ddf, 0x01a0, 0x2d00, 0x60a6, 0x6803, 0x0001, 0x6807,
+	0x0000, 0x9d88, 0x0004, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108,
+	0x1f04, 0x4d05, 0x9085, 0x0001, 0x012e, 0x00de, 0x0005, 0x9006,
+	0x0cd8, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4, 0x906d, 0x0130,
+	0x60a7, 0x0000, 0x080c, 0x0df6, 0x9085, 0x0001, 0x012e, 0x00de,
+	0x0005, 0x609c, 0xd0a4, 0x0005, 0x00f6, 0x080c, 0x5745, 0x01b0,
+	0x71b4, 0x81ff, 0x1198, 0x71cc, 0xd19c, 0x0180, 0x2001, 0x007e,
+	0x9080, 0x1000, 0x2004, 0x907d, 0x0148, 0x7804, 0x9084, 0x00ff,
+	0x9086, 0x0006, 0x1118, 0x7800, 0xc0ed, 0x7802, 0x2079, 0x1152,
+	0x7804, 0xd0a4, 0x01e8, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009,
+	0x0000, 0x0016, 0x080c, 0x4b58, 0x1168, 0x6004, 0x9084, 0xff00,
+	0x8007, 0x9096, 0x0004, 0x0118, 0x9086, 0x0006, 0x1118, 0x6000,
+	0xc0ed, 0x6002, 0x001e, 0x8108, 0x1f04, 0x4d49, 0x00ce, 0x015e,
+	0x080c, 0x4de0, 0x0120, 0x2001, 0x12a5, 0x200c, 0x0038, 0x2079,
+	0x1152, 0x7804, 0xd0a4, 0x0130, 0x2009, 0x07d0, 0x2011, 0x4d74,
+	0x080c, 0x65e1, 0x00fe, 0x0005, 0x2011, 0x4d74, 0x080c, 0x655b,
+	0x080c, 0x4de0, 0x01f0, 0x2001, 0x107e, 0x2004, 0x9080, 0x0000,
+	0x200c, 0xc1ec, 0x2102, 0x2001, 0x1153, 0x2004, 0xd0a4, 0x0130,
+	0x2009, 0x07d0, 0x2011, 0x4d74, 0x080c, 0x65e1, 0x00e6, 0x2071,
+	0x1100, 0x706f, 0x0000, 0x7073, 0x0000, 0x080c, 0x23cd, 0x00ee,
+	0x04b0, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016,
+	0x080c, 0x4b58, 0x1530, 0x6000, 0xd0ec, 0x0518, 0x0046, 0x62a0,
+	0x9294, 0x00ff, 0x8227, 0x9006, 0x2009, 0x0029, 0x080c, 0xaaca,
+	0x6000, 0xc0e5, 0xc0ec, 0x6002, 0x6004, 0x9084, 0x00ff, 0x9085,
+	0x0700, 0x6006, 0x2019, 0x0029, 0x080c, 0x69ca, 0x0076, 0x2039,
+	0x0000, 0x080c, 0x68fe, 0x2009, 0x0000, 0x080c, 0xa85f, 0x007e,
+	0x004e, 0x001e, 0x8108, 0x1f04, 0x4d9f, 0x00ce, 0x015e, 0x0005,
+	0x00c6, 0x6010, 0x2060, 0x6000, 0xc0ec, 0x6002, 0x00ce, 0x0005,
+	0x7810, 0x2004, 0xd0ac, 0x0005, 0x7810, 0x2004, 0xd0bc, 0x0005,
+	0x00f6, 0x2001, 0x107e, 0x2004, 0x907d, 0x0110, 0x7800, 0xd0ec,
+	0x00fe, 0x0005, 0x0126, 0x0026, 0x2091, 0x8000, 0x6200, 0x9005,
+	0x0110, 0xc2fd, 0x0008, 0xc2fc, 0x6202, 0x002e, 0x012e, 0x0005,
+	0x2011, 0x1133, 0x2204, 0xd0cc, 0x0138, 0x2001, 0x12a3, 0x200c,
+	0x2011, 0x4e05, 0x080c, 0x65e1, 0x0005, 0x2011, 0x4e05, 0x080c,
+	0x655b, 0x2011, 0x1133, 0x2204, 0xc0cc, 0x2012, 0x0005, 0x2071,
+	0x1228, 0x7003, 0x0001, 0x7007, 0x0000, 0x7013, 0x0000, 0x7017,
+	0x0000, 0x701b, 0x0000, 0x701f, 0x0000, 0x700b, 0x0000, 0x7047,
+	0x0000, 0x2071, 0x126e, 0x7003, 0x1228, 0x7007, 0x0000, 0x700b,
+	0x0000, 0x700f, 0x0001, 0x7013, 0x124e, 0x7017, 0x0020, 0x701b,
+	0x0040, 0x703b, 0x0000, 0x2001, 0x124a, 0x2003, 0x0000, 0x0005,
+	0x0016, 0x00e6, 0x2071, 0x124b, 0x900e, 0x710a, 0x2001, 0x1153,
+	0x2004, 0xd0fc, 0x1148, 0x2001, 0x1153, 0x2004, 0x900e, 0xd09c,
+	0x0108, 0x8108, 0x7102, 0x04c0, 0x2001, 0x1172, 0x200c, 0x9184,
+	0x000f, 0x0002, 0x4e43, 0x4e43, 0x4e43, 0x4e43, 0x4e43, 0x4e62,
+	0x4e43, 0x4e43, 0x4e70, 0x4e43, 0x4e43, 0x4e43, 0x4e43, 0x4e43,
+	0x4e43, 0x4e43, 0x7003, 0x0003, 0x2009, 0x1173, 0x210c, 0x9184,
+	0xff00, 0x8007, 0x9005, 0x1110, 0x2001, 0x0002, 0x7006, 0x00a0,
+	0x7003, 0x0004, 0x0136, 0x0146, 0x0156, 0x20e1, 0x0001, 0x2099,
+	0x1176, 0x20e9, 0x0001, 0x20a1, 0x1278, 0x20a9, 0x0004, 0x4003,
+	0x015e, 0x014e, 0x013e, 0x0000, 0x00ee, 0x001e, 0x0005, 0x00e6,
+	0x2071, 0x0050, 0x684c, 0x9005, 0x1150, 0x00e6, 0x2071, 0x1228,
+	0x7028, 0xc085, 0x702a, 0x00ee, 0x9085, 0x0001, 0x04e8, 0x6844,
+	0x9005, 0x01a8, 0x2009, 0x0000, 0x0156, 0x20a9, 0x0006, 0x8003,
+	0x81f5, 0x3e08, 0x1f04, 0x4e9f, 0x015e, 0x6a60, 0x9200, 0x7002,
+	0x6864, 0x9101, 0x7006, 0x7013, 0x0000, 0x7017, 0x0000, 0x6860,
+	0x7002, 0x6864, 0x7006, 0x6868, 0x700a, 0x686c, 0x700e, 0x6844,
+	0x9005, 0x1120, 0x7013, 0x0000, 0x7017, 0x0000, 0x684c, 0x701a,
+	0x701c, 0x9085, 0x0040, 0x701e, 0x7037, 0x0019, 0x702b, 0x0001,
+	0x00e6, 0x2071, 0x1228, 0x7028, 0xc084, 0x702a, 0x7007, 0x0001,
+	0x700b, 0x0000, 0x00ee, 0x9006, 0x00ee, 0x0005, 0x6868, 0xd0fc,
+	0x11d0, 0x00e6, 0x0026, 0x2001, 0x124b, 0x2004, 0x9005, 0x0904,
+	0x50aa, 0x687c, 0xd0bc, 0x1904, 0x50aa, 0x6978, 0x6874, 0x9105,
+	0x1904, 0x50aa, 0x2001, 0x124b, 0x2004, 0x0002, 0x50aa, 0x4f17,
+	0x4f4b, 0x4f4b, 0x53ec, 0x0005, 0x6868, 0xd0fc, 0x11f8, 0x00e6,
+	0x0026, 0x2009, 0x124b, 0x210c, 0x81ff, 0x0904, 0x50aa, 0x687c,
+	0xd0cc, 0x0904, 0x50aa, 0x6880, 0x9084, 0x00ff, 0x9086, 0x0001,
+	0x1904, 0x50aa, 0x9186, 0x0003, 0x05f0, 0x9186, 0x0004, 0x0904,
+	0x53ec, 0x684f, 0x8021, 0x6853, 0x0017, 0x0028, 0x0005, 0x684f,
+	0x8020, 0x6853, 0x0016, 0x2071, 0x1228, 0x701c, 0x9005, 0x1904,
+	0x5235, 0x0e04, 0x5278, 0x2071, 0x0000, 0x684c, 0x7082, 0x6850,
+	0x7032, 0x686c, 0x7086, 0x7036, 0x6870, 0x708a, 0x2091, 0x4080,
+	0x2071, 0x1100, 0x2011, 0x0001, 0x6804, 0x900d, 0x702c, 0x1148,
+	0x206a, 0x2d00, 0x702e, 0x70b0, 0x9200, 0x70b2, 0x002e, 0x00ee,
+	0x0005, 0x00d6, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff,
+	0x1dc8, 0x00de, 0x0c68, 0x684f, 0x0000, 0x00f6, 0x2079, 0x0050,
+	0x2071, 0x1228, 0x206b, 0x0000, 0x7010, 0x9005, 0x1904, 0x5039,
+	0x782c, 0x908c, 0x0780, 0x190c, 0x542a, 0x8004, 0x8004, 0x8004,
+	0x9084, 0x0003, 0x0002, 0x4f69, 0x5039, 0x4f8f, 0x4fd2, 0x080c,
+	0x0cf1, 0x2071, 0x1100, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822,
+	0x6804, 0x900d, 0x1170, 0x2071, 0x12ef, 0x703c, 0x9005, 0x1328,
+	0x2001, 0x124c, 0x2004, 0x8005, 0x703e, 0x00fe, 0x002e, 0x00ee,
+	0x0005, 0x9016, 0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00,
+	0x81ff, 0x1dc8, 0x702e, 0x70b0, 0x9200, 0x70b2, 0x0c20, 0x2071,
+	0x1100, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822, 0x6804, 0x900d,
+	0x1558, 0x7824, 0x00e6, 0x2071, 0x0040, 0x712c, 0xd19c, 0x1118,
+	0x7022, 0x00ee, 0x0060, 0x00ee, 0xc0d4, 0x8006, 0x8006, 0x806f,
+	0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0, 0x8000, 0x70b2, 0x782c,
+	0x9094, 0x0780, 0x190c, 0x542a, 0xd0a4, 0x1d18, 0x2071, 0x12ef,
+	0x703c, 0x9005, 0x1328, 0x2001, 0x124c, 0x2004, 0x8005, 0x703e,
+	0x00fe, 0x002e, 0x00ee, 0x0005, 0x9016, 0x702c, 0x2168, 0x6904,
+	0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e, 0x70b0, 0x9200,
+	0x70b2, 0x0838, 0x00d6, 0x00e6, 0x7824, 0xc0d4, 0x8006, 0x8006,
+	0x806f, 0x2071, 0x1100, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0,
+	0x8000, 0x70b2, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd0a4,
+	0x1d58, 0x00ee, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd09c,
+	0x11b8, 0x00de, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822, 0x6804,
+	0x900d, 0x1560, 0x2071, 0x12ef, 0x703c, 0x9005, 0x1328, 0x2001,
+	0x124c, 0x2004, 0x8005, 0x703e, 0x00fe, 0x002e, 0x00ee, 0x0005,
+	0x00de, 0x2d08, 0x7010, 0x8000, 0x7012, 0x7018, 0x906d, 0x711a,
+	0x0110, 0x6902, 0x0008, 0x711e, 0x2168, 0x6804, 0x900d, 0x1170,
+	0x2071, 0x12ef, 0x703c, 0x9005, 0x1328, 0x2001, 0x124c, 0x2004,
+	0x8005, 0x703e, 0x00fe, 0x002e, 0x00ee, 0x0005, 0x2071, 0x1100,
+	0x9016, 0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff,
+	0x1dc8, 0x702e, 0x70b0, 0x9200, 0x70b2, 0x00fe, 0x002e, 0x00ee,
+	0x0005, 0x2d08, 0x7010, 0x8000, 0x7012, 0x7018, 0x906d, 0x711a,
+	0x0110, 0x6902, 0x0008, 0x711e, 0x2168, 0x6804, 0x900d, 0x1904,
+	0x5092, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd09c, 0x11b0,
+	0x701c, 0x906d, 0x0198, 0x7010, 0x8001, 0x7012, 0x1108, 0x701a,
+	0x2d04, 0x701e, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822, 0x782c,
+	0x9094, 0x0780, 0x190c, 0x542a, 0xd09c, 0x0d50, 0x782c, 0x9094,
+	0x0780, 0x190c, 0x542a, 0xd0a4, 0x01b8, 0x00e6, 0x7824, 0xc0d4,
+	0x8006, 0x8006, 0x806f, 0x2071, 0x1100, 0x702c, 0x206a, 0x2d00,
+	0x702e, 0x70b0, 0x8000, 0x70b2, 0x782c, 0x9094, 0x0780, 0x190c,
+	0x542a, 0xd0a4, 0x1d58, 0x00ee, 0x2071, 0x12ef, 0x703c, 0x9005,
+	0x1328, 0x2001, 0x124c, 0x2004, 0x8005, 0x703e, 0x00fe, 0x002e,
+	0x00ee, 0x0005, 0x00e6, 0x2071, 0x1100, 0x9016, 0x702c, 0x2168,
+	0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e, 0x70b0,
+	0x9200, 0x70b2, 0x00ee, 0x0804, 0x5049, 0x6868, 0xd0fc, 0x1500,
+	0x00e6, 0x0026, 0x684f, 0x0000, 0x00f6, 0x2079, 0x0050, 0x2071,
+	0x1228, 0x206b, 0x0000, 0x7010, 0x9005, 0x1904, 0x51b5, 0x782c,
+	0x908c, 0x0780, 0x190c, 0x542a, 0x8004, 0x8004, 0x8004, 0x9084,
+	0x0003, 0x0002, 0x50c9, 0x51b5, 0x50e5, 0x514a, 0x080c, 0x0cf1,
+	0x0005, 0x2071, 0x1100, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822,
+	0x6804, 0x900d, 0x1120, 0x00fe, 0x002e, 0x00ee, 0x0005, 0x9016,
+	0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8,
+	0x702e, 0x70b0, 0x9200, 0x70b2, 0x0c70, 0x2071, 0x1100, 0x8d07,
+	0x8005, 0x8005, 0xc0d5, 0x7822, 0x6804, 0x900d, 0x1904, 0x513b,
+	0x7830, 0x8007, 0x9084, 0x001f, 0x9082, 0x0005, 0x1220, 0x00fe,
+	0x002e, 0x00ee, 0x0005, 0x7824, 0x00e6, 0x2071, 0x0040, 0x712c,
+	0xd19c, 0x1118, 0x7022, 0x00ee, 0x0060, 0x00ee, 0xc0d4, 0x8006,
+	0x8006, 0x806f, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0, 0x8000,
+	0x70b2, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd0a4, 0x1d18,
+	0x0e04, 0x5132, 0x7838, 0x7938, 0x910e, 0x1de0, 0x2069, 0x0000,
+	0x6836, 0x6833, 0x0013, 0x2001, 0x1239, 0x200c, 0xc184, 0x2102,
+	0x2091, 0x4080, 0x2009, 0x124a, 0x200b, 0x0000, 0x00fe, 0x002e,
+	0x00ee, 0x0005, 0x2001, 0x1239, 0x200c, 0xc185, 0x2102, 0x00fe,
+	0x002e, 0x00ee, 0x0005, 0x9016, 0x702c, 0x2168, 0x6904, 0x206a,
+	0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e, 0x70b0, 0x9200, 0x70b2,
+	0x0804, 0x50fb, 0x00d6, 0x00e6, 0x7824, 0xc0d4, 0x8006, 0x8006,
+	0x806f, 0x2071, 0x1100, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0,
+	0x8000, 0x70b2, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd0a4,
+	0x1d58, 0x00ee, 0x0e04, 0x518a, 0x7838, 0x7938, 0x910e, 0x1de0,
+	0x2069, 0x0000, 0x6836, 0x6833, 0x0013, 0x7044, 0xc084, 0x7046,
+	0x2091, 0x4080, 0x2009, 0x124a, 0x200b, 0x0000, 0x782c, 0x9094,
+	0x0780, 0x190c, 0x542a, 0xd09c, 0x1188, 0x00de, 0x8d07, 0x8005,
+	0x8005, 0xc0d5, 0x7822, 0x6804, 0x900d, 0x11e0, 0x00fe, 0x002e,
+	0x00ee, 0x0005, 0x7044, 0xc085, 0x7046, 0x0c40, 0x00de, 0x2d08,
+	0x7010, 0x8000, 0x7012, 0x7018, 0x906d, 0x711a, 0x0110, 0x6902,
+	0x0008, 0x711e, 0x2168, 0x6804, 0x900d, 0x1120, 0x00fe, 0x002e,
+	0x00ee, 0x0005, 0x2071, 0x1100, 0x9016, 0x702c, 0x2168, 0x6904,
+	0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e, 0x70b0, 0x9200,
+	0x70b2, 0x00fe, 0x002e, 0x00ee, 0x0005, 0x2d08, 0x7010, 0x8000,
+	0x7012, 0x7018, 0x906d, 0x711a, 0x0110, 0x6902, 0x0008, 0x711e,
+	0x2168, 0x6804, 0x900d, 0x1904, 0x5222, 0x782c, 0x9094, 0x0780,
+	0x190c, 0x542a, 0xd09c, 0x11c8, 0x701c, 0x906d, 0x01b0, 0x684c,
+	0x9005, 0x1198, 0x7010, 0x8001, 0x7012, 0x1108, 0x701a, 0x2d04,
+	0x701e, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7822, 0x782c, 0x9094,
+	0x0780, 0x190c, 0x542a, 0xd09c, 0x0d38, 0x782c, 0x9094, 0x0780,
+	0x190c, 0x542a, 0xd0a4, 0x0590, 0x00e6, 0x7824, 0xc0d4, 0x8006,
+	0x8006, 0x806f, 0x2071, 0x1100, 0x702c, 0x206a, 0x2d00, 0x702e,
+	0x70b0, 0x8000, 0x70b2, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a,
+	0xd0a4, 0x1d58, 0x00ee, 0x0e04, 0x521b, 0x7838, 0x7938, 0x910e,
+	0x1de0, 0x2069, 0x0000, 0x6836, 0x6833, 0x0013, 0x7044, 0xc084,
+	0x7046, 0x2091, 0x4080, 0x2009, 0x124a, 0x200b, 0x0000, 0x00fe,
+	0x002e, 0x00ee, 0x0005, 0x7044, 0xc085, 0x7046, 0x00fe, 0x002e,
+	0x00ee, 0x0005, 0x00e6, 0x2071, 0x1100, 0x9016, 0x702c, 0x2168,
+	0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e, 0x70b0,
+	0x9200, 0x70b2, 0x00ee, 0x0804, 0x51c5, 0x2071, 0x1228, 0x206b,
+	0x0000, 0x2d08, 0x7010, 0x8000, 0x7012, 0x7018, 0x906d, 0x711a,
+	0x0110, 0x6902, 0x0008, 0x711e, 0x2168, 0x6804, 0x900d, 0x1128,
+	0x1e04, 0x525e, 0x002e, 0x00ee, 0x0005, 0x2071, 0x1100, 0x9016,
+	0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8,
+	0x702e, 0x70b0, 0x9200, 0x70b2, 0x0e04, 0x524a, 0x2071, 0x1228,
+	0x701c, 0x2068, 0x684c, 0x900d, 0x0d28, 0x2071, 0x0000, 0x7182,
+	0x6850, 0x7032, 0x686c, 0x7086, 0x7036, 0x6870, 0x708a, 0x2091,
+	0x4080, 0x2071, 0x1228, 0x080c, 0x5416, 0x002e, 0x00ee, 0x0005,
+	0x2071, 0x1228, 0x206b, 0x0000, 0x2d08, 0x7010, 0x8000, 0x7012,
+	0x7018, 0x906d, 0x711a, 0x0110, 0x6902, 0x0008, 0x711e, 0x2168,
+	0x6804, 0x900d, 0x1118, 0x002e, 0x00ee, 0x0005, 0x2071, 0x1100,
+	0x9016, 0x702c, 0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff,
+	0x1dc8, 0x702e, 0x70b0, 0x9200, 0x70b2, 0x002e, 0x00ee, 0x0005,
+	0x0006, 0x687c, 0x0006, 0x6867, 0x0103, 0x20a9, 0x001c, 0x9d80,
+	0x001d, 0x20a0, 0x9006, 0x20e9, 0x0001, 0x4004, 0x000e, 0x9084,
+	0x00ff, 0x687e, 0x000e, 0x687a, 0x6982, 0x0005, 0x2071, 0x1228,
+	0x7004, 0x0002, 0x52c0, 0x52c1, 0x53ea, 0x53d8, 0x0cf1, 0x53eb,
+	0x0005, 0x2001, 0x124b, 0x2004, 0x0002, 0x52ca, 0x52ca, 0x531c,
+	0x531d, 0x5373, 0x0126, 0x2091, 0x8000, 0x1e0c, 0x542f, 0x701c,
+	0x906d, 0x01b0, 0x684c, 0x9005, 0x01a8, 0x0e04, 0x52e8, 0x694c,
+	0x2071, 0x0000, 0x7182, 0x6850, 0x7032, 0x686c, 0x7086, 0x7036,
+	0x6870, 0x708a, 0x2091, 0x4080, 0x2071, 0x1228, 0x080c, 0x5416,
+	0x012e, 0x0488, 0x2001, 0x005b, 0x2004, 0x9094, 0x0780, 0x190c,
+	0x542a, 0xd09c, 0x2071, 0x1228, 0x1528, 0x2071, 0x1228, 0x700f,
+	0x0001, 0x6964, 0x9184, 0x00ff, 0x9086, 0x0003, 0x1130, 0x810f,
+	0x918c, 0x00ff, 0x8101, 0x0108, 0x710e, 0x8d07, 0x8005, 0x8005,
+	0xc0d5, 0x00d6, 0x2069, 0x0050, 0x6822, 0x00de, 0x2071, 0x1228,
+	0x701c, 0x2068, 0x7010, 0x8001, 0x7012, 0x2d04, 0x701e, 0x9005,
+	0x1108, 0x701a, 0x012e, 0x0005, 0x0005, 0x2069, 0x12ef, 0x683c,
+	0x9005, 0x03d8, 0x11d0, 0x0126, 0x2091, 0x8000, 0x2069, 0x0050,
+	0x693c, 0x6838, 0x9106, 0x0160, 0x0e04, 0x533c, 0x2069, 0x0000,
+	0x6837, 0x8040, 0x6833, 0x0012, 0x6883, 0x8040, 0x2091, 0x4080,
+	0x2069, 0x12ef, 0x683f, 0xffff, 0x012e, 0x0126, 0x2091, 0x8000,
+	0x1e0c, 0x548e, 0x701c, 0x906d, 0x0560, 0x2001, 0x005b, 0x2004,
+	0x9094, 0x0780, 0x190c, 0x542a, 0xd09c, 0x1518, 0x2071, 0x1228,
+	0x700f, 0x0001, 0x6964, 0x9184, 0x00ff, 0x9086, 0x0003, 0x1130,
+	0x810f, 0x918c, 0x00ff, 0x8101, 0x0108, 0x710e, 0x8d07, 0x8005,
+	0x8005, 0xc0d5, 0x00d6, 0x2069, 0x0050, 0x6822, 0x00de, 0x701c,
+	0x2068, 0x7010, 0x8001, 0x7012, 0x2d04, 0x701e, 0x9005, 0x1108,
+	0x701a, 0x012e, 0x0005, 0x0126, 0x2091, 0x8000, 0x1e0c, 0x542f,
+	0x701c, 0x906d, 0x0548, 0x684c, 0x9086, 0x0004, 0x1538, 0x0136,
+	0x0146, 0x0156, 0x2099, 0x1176, 0x20e1, 0x0001, 0x20a1, 0x1278,
+	0x20e9, 0x0001, 0x20a9, 0x0004, 0x4003, 0x015e, 0x014e, 0x013e,
+	0x2071, 0x126e, 0x9d80, 0x001b, 0x700f, 0x0001, 0x7012, 0x7017,
+	0x0002, 0x7007, 0x0002, 0x700b, 0x0000, 0x2e10, 0x080c, 0x0e55,
+	0x2071, 0x1228, 0x7007, 0x0003, 0x012e, 0x0005, 0x2001, 0x005b,
+	0x2004, 0x9094, 0x0780, 0x190c, 0x542a, 0xd09c, 0x2071, 0x1228,
+	0x1d98, 0x2071, 0x1228, 0x700f, 0x0001, 0x6964, 0x9184, 0x00ff,
+	0x9086, 0x0003, 0x1130, 0x810f, 0x918c, 0x00ff, 0x8101, 0x0108,
+	0x710e, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x00d6, 0x2069, 0x0050,
+	0x6822, 0x00de, 0x2071, 0x1228, 0x701c, 0x2068, 0x7010, 0x8001,
+	0x7012, 0x2d04, 0x701e, 0x9005, 0x1978, 0x701a, 0x012e, 0x0005,
+	0x2001, 0x1270, 0x2004, 0x908e, 0x0100, 0x1120, 0x7007, 0x0001,
+	0x04a9, 0x0005, 0x908e, 0x0000, 0x0de0, 0x908e, 0x0200, 0x1dc8,
+	0x080c, 0x542a, 0x0005, 0x0005, 0x684f, 0x0004, 0x206b, 0x0000,
+	0x2d08, 0x2071, 0x1228, 0x7010, 0x8000, 0x7012, 0x7018, 0x906d,
+	0x711a, 0x0110, 0x6902, 0x0008, 0x711e, 0x2168, 0x6804, 0x900d,
+	0x1118, 0x002e, 0x00ee, 0x0005, 0x2071, 0x1100, 0x9016, 0x702c,
+	0x2168, 0x6904, 0x206a, 0x8210, 0x2d00, 0x81ff, 0x1dc8, 0x702e,
+	0x70b0, 0x9200, 0x70b2, 0x002e, 0x00ee, 0x0005, 0x0126, 0x2091,
+	0x8000, 0x701c, 0x906d, 0x0160, 0x7010, 0x8001, 0x7012, 0x2d04,
+	0x701e, 0x9005, 0x1108, 0x701a, 0x012e, 0x080c, 0x0df6, 0x0005,
+	0x012e, 0x0005, 0x2011, 0x8004, 0x080c, 0x37dc, 0x0cf8, 0x00f6,
+	0x2079, 0x0050, 0x7044, 0xd084, 0x0198, 0xc084, 0x7046, 0x7838,
+	0x7938, 0x910e, 0x1de0, 0x2069, 0x0000, 0x6836, 0x6833, 0x0013,
+	0x2091, 0x4080, 0x2009, 0x124a, 0x200b, 0x0000, 0x00fe, 0x0005,
+	0x782c, 0x9094, 0x0780, 0x19f1, 0xd0a4, 0x0dc0, 0x2001, 0x124b,
+	0x2004, 0x9086, 0x0004, 0x0140, 0x2009, 0x124a, 0x2104, 0x8000,
+	0x200a, 0x9082, 0x000f, 0x0e50, 0x00e6, 0x2071, 0x1100, 0x7824,
+	0x00e6, 0x2071, 0x0040, 0x712c, 0xd19c, 0x1118, 0x7022, 0x00ee,
+	0x0060, 0x00ee, 0xc0d4, 0x8006, 0x8006, 0x806f, 0x702c, 0x206a,
+	0x2d00, 0x702e, 0x70b0, 0x8000, 0x70b2, 0x782c, 0x9094, 0x0780,
+	0x190c, 0x542a, 0xd0a4, 0x1d18, 0x7838, 0x7938, 0x910e, 0x1de0,
+	0x2069, 0x0000, 0x6836, 0x6833, 0x0013, 0x2091, 0x4080, 0x2009,
+	0x124a, 0x200b, 0x0000, 0x00ee, 0x00fe, 0x0005, 0x00f6, 0x2079,
+	0x0050, 0x7044, 0xd084, 0x0178, 0xc084, 0x7046, 0x7838, 0x7938,
+	0x910e, 0x1de0, 0x2069, 0x0000, 0x6836, 0x6833, 0x0013, 0x2091,
+	0x4080, 0x00fe, 0x0005, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a,
+	0xd0a4, 0x0db8, 0x00e6, 0x2071, 0x1100, 0x7824, 0xc0d4, 0x8006,
+	0x8006, 0x806f, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70b0, 0x8000,
+	0x70b2, 0x782c, 0x9094, 0x0780, 0x190c, 0x542a, 0xd0a4, 0x1d68,
+	0x2069, 0x0050, 0x693c, 0x2069, 0x124b, 0x6808, 0x690a, 0x2069,
+	0x12ef, 0x9102, 0x1118, 0x683c, 0x9005, 0x1328, 0x2001, 0x124c,
+	0x200c, 0x810d, 0x693e, 0x00ee, 0x00fe, 0x0005, 0x7088, 0x908a,
+	0x0029, 0x1220, 0x9082, 0x001d, 0x0033, 0x0010, 0x080c, 0x0cf1,
+	0x6027, 0x1e00, 0x0005, 0x55a7, 0x5541, 0x5557, 0x557b, 0x559a,
+	0x55cc, 0x55de, 0x5557, 0x55b8, 0x54f0, 0x552a, 0x54ef, 0x0005,
+	0x00d6, 0x2069, 0x0200, 0x6804, 0x9005, 0x1180, 0x6808, 0x9005,
+	0x1578, 0x708b, 0x0028, 0x2069, 0x12af, 0x2d04, 0x7002, 0x080c,
+	0x5857, 0x6028, 0x9085, 0x0600, 0x602a, 0x0410, 0x708b, 0x0028,
+	0x2069, 0x12af, 0x2d04, 0x7002, 0x6028, 0x9085, 0x0600, 0x602a,
+	0x00e6, 0x0036, 0x0046, 0x0056, 0x2071, 0x131c, 0x080c, 0x1337,
+	0x005e, 0x004e, 0x003e, 0x00ee, 0x0126, 0x2091, 0x2200, 0x080c,
+	0x0fb3, 0x78ab, 0x0004, 0x7803, 0x0000, 0x7803, 0x0001, 0x012e,
+	0x00de, 0x0005, 0x00d6, 0x2069, 0x0200, 0x6804, 0x9005, 0x1178,
+	0x6808, 0x9005, 0x1160, 0x708b, 0x0028, 0x2069, 0x12af, 0x2d04,
+	0x7002, 0x080c, 0x58e5, 0x6028, 0x9085, 0x0600, 0x602a, 0x00de,
+	0x0005, 0x6803, 0x0090, 0x6124, 0xd1e4, 0x1180, 0x080c, 0x5649,
+	0xd1d4, 0x1150, 0xd1dc, 0x1128, 0xd1cc, 0x0140, 0x708b, 0x0020,
+	0x0028, 0x708b, 0x001d, 0x0010, 0x708b, 0x001f, 0x0005, 0x6803,
+	0x0088, 0x6124, 0xd1cc, 0x11c8, 0xd1dc, 0x11a0, 0xd1e4, 0x1178,
+	0x9184, 0x1e00, 0x11b8, 0x60e3, 0x0001, 0x600c, 0xc0b4, 0x600e,
+	0x080c, 0x5775, 0x6803, 0x0080, 0x708b, 0x0028, 0x0058, 0x708b,
+	0x001e, 0x0040, 0x708b, 0x001d, 0x0028, 0x708b, 0x0020, 0x0010,
+	0x708b, 0x001f, 0x0005, 0x60e3, 0x0001, 0x600c, 0xc0b4, 0x600e,
+	0x080c, 0x5775, 0x6803, 0x0080, 0x6124, 0xd1d4, 0x1180, 0xd1dc,
+	0x1158, 0xd1e4, 0x1130, 0x9184, 0x1e00, 0x1158, 0x708b, 0x0028,
+	0x0040, 0x708b, 0x001e, 0x0028, 0x708b, 0x001d, 0x0010, 0x708b,
+	0x001f, 0x0005, 0x6803, 0x00a0, 0x6124, 0xd1dc, 0x1128, 0xd1e4,
+	0x0128, 0x708b, 0x001e, 0x0010, 0x708b, 0x001d, 0x0005, 0x080c,
+	0x5675, 0x6124, 0xd1dc, 0x1158, 0x080c, 0x5649, 0xd1d4, 0x1128,
+	0xd1e4, 0x0128, 0x708b, 0x001e, 0x0010, 0x708b, 0x001f, 0x0005,
+	0x6803, 0x00a0, 0x6124, 0xd1d4, 0x1160, 0xd1cc, 0x1150, 0xd1dc,
+	0x1128, 0xd1e4, 0x0140, 0x708b, 0x001e, 0x0028, 0x708b, 0x001d,
+	0x0010, 0x708b, 0x0021, 0x0005, 0x080c, 0x5675, 0x6124, 0xd1d4,
+	0x1150, 0xd1dc, 0x1128, 0xd1e4, 0x0140, 0x708b, 0x001e, 0x0028,
+	0x708b, 0x001d, 0x0010, 0x708b, 0x001f, 0x0005, 0x6803, 0x0090,
+	0x6124, 0xd1d4, 0x1178, 0xd1cc, 0x1150, 0xd1dc, 0x1128, 0xd1e4,
+	0x0158, 0x708b, 0x001e, 0x0040, 0x708b, 0x001d, 0x0028, 0x708b,
+	0x0020, 0x0010, 0x708b, 0x001f, 0x0005, 0x0016, 0x00c6, 0x00d6,
+	0x00e6, 0x0126, 0x2061, 0x0100, 0x2069, 0x0140, 0x2071, 0x1100,
+	0x2091, 0x8000, 0x080c, 0x5745, 0x11e8, 0x2001, 0x110c, 0x200c,
+	0xd1b4, 0x01c0, 0xc1b4, 0x2102, 0x6027, 0x0200, 0x080c, 0x2055,
+	0x6024, 0xd0cc, 0x0158, 0x6803, 0x00a0, 0x2001, 0x1290, 0x2003,
+	0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x0428, 0x6028, 0xc0cd,
+	0x602a, 0x0408, 0x080c, 0x5761, 0x0150, 0x080c, 0x5757, 0x1138,
+	0x2001, 0x0001, 0x080c, 0x1c36, 0x080c, 0x571c, 0x00a0, 0x080c,
+	0x5672, 0x0178, 0x2001, 0x0001, 0x080c, 0x1c36, 0x7088, 0x9086,
+	0x001e, 0x0120, 0x7088, 0x9086, 0x0022, 0x1118, 0x708b, 0x0025,
+	0x0010, 0x708b, 0x0021, 0x012e, 0x00ee, 0x00de, 0x00ce, 0x001e,
+	0x0005, 0x0016, 0x0026, 0x2009, 0x0064, 0x2011, 0x5654, 0x080c,
+	0x654f, 0x002e, 0x001e, 0x0005, 0x00e6, 0x00f6, 0x0016, 0x080c,
+	0x7721, 0x2071, 0x1100, 0x080c, 0x55f5, 0x001e, 0x00fe, 0x00ee,
+	0x0005, 0x0026, 0x00e6, 0x2011, 0x5654, 0x2071, 0x12ef, 0x701c,
+	0x9206, 0x1118, 0x7018, 0x9005, 0x0110, 0x9085, 0x0001, 0x00ee,
+	0x002e, 0x0005, 0x6020, 0xd09c, 0x0005, 0x6803, 0x00c0, 0x0156,
+	0x20a9, 0x002d, 0x1d04, 0x567a, 0x2091, 0x6000, 0x1f04, 0x567a,
+	0x015e, 0x0005, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100, 0x2069,
+	0x0140, 0x2071, 0x1100, 0x2001, 0x1290, 0x200c, 0x9186, 0x0000,
+	0x0158, 0x9186, 0x0001, 0x0158, 0x9186, 0x0002, 0x0158, 0x9186,
+	0x0003, 0x0158, 0x0804, 0x570a, 0x708b, 0x0022, 0x0040, 0x708b,
+	0x0021, 0x0028, 0x708b, 0x0023, 0x0030, 0x708b, 0x0024, 0x9085,
+	0x0001, 0x080c, 0x5789, 0x60e3, 0x0000, 0x6887, 0x0001, 0x2001,
+	0x0001, 0x080c, 0x1cbe, 0x0026, 0x2011, 0x0003, 0x080c, 0x79c2,
+	0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf,
+	0x0036, 0x2019, 0x0000, 0x080c, 0x7936, 0x003e, 0x002e, 0x7000,
+	0x908e, 0x0004, 0x0118, 0x602b, 0x0028, 0x0010, 0x602b, 0x0020,
+	0x0156, 0x0126, 0x2091, 0x8000, 0x20a9, 0x0005, 0x6024, 0xd0ac,
+	0x0118, 0x012e, 0x015e, 0x04e0, 0x6800, 0x9084, 0x00a0, 0xc0bd,
+	0x6802, 0x080c, 0x2055, 0x6904, 0xd1d4, 0x1130, 0x6803, 0x0100,
+	0x1f04, 0x56d6, 0x080c, 0x5796, 0x012e, 0x015e, 0x080c, 0x5757,
+	0x01a8, 0x6044, 0x9005, 0x0168, 0x6050, 0x0006, 0x9085, 0x0020,
+	0x6052, 0x080c, 0x5796, 0x9006, 0x8001, 0x1df0, 0x000e, 0x6052,
+	0x0028, 0x6804, 0xd0d4, 0x1110, 0x080c, 0x5796, 0x2001, 0x1290,
+	0x2003, 0x0004, 0x080c, 0x54d6, 0x080c, 0x5757, 0x0148, 0x6804,
+	0xd0d4, 0x1130, 0xd0dc, 0x1100, 0x2001, 0x1290, 0x2003, 0x0000,
+	0x00ee, 0x00de, 0x00ce, 0x0005, 0x00c6, 0x00d6, 0x00e6, 0x2061,
+	0x0100, 0x2069, 0x0140, 0x2071, 0x1100, 0x2001, 0x128f, 0x2003,
+	0x0000, 0x2001, 0x1280, 0x2003, 0x0000, 0x708b, 0x0000, 0x60e3,
+	0x0000, 0x6887, 0x0000, 0x2001, 0x0000, 0x080c, 0x1cbe, 0x6803,
+	0x0000, 0x6043, 0x0090, 0x6043, 0x0010, 0x6027, 0xffff, 0x602b,
+	0x182f, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x0006, 0x2001, 0x128f,
+	0x2004, 0x9086, 0xaaaa, 0x000e, 0x0005, 0x0006, 0x2001, 0x1172,
+	0x2004, 0x9084, 0x0030, 0x9086, 0x0000, 0x000e, 0x0005, 0x0006,
+	0x2001, 0x1172, 0x2004, 0x9084, 0x0030, 0x9086, 0x0030, 0x000e,
+	0x0005, 0x0006, 0x2001, 0x1172, 0x2004, 0x9084, 0x0030, 0x9086,
+	0x0010, 0x000e, 0x0005, 0x0006, 0x2001, 0x1172, 0x2004, 0x9084,
+	0x0030, 0x9086, 0x0020, 0x000e, 0x0005, 0x2001, 0x110c, 0x2004,
+	0xd0a4, 0x0170, 0x080c, 0x1cde, 0x0036, 0x0016, 0x2009, 0x0000,
+	0x2019, 0x0028, 0x080c, 0x2582, 0x001e, 0x003e, 0x9006, 0x0009,
+	0x0005, 0x00e6, 0x2071, 0x110c, 0x2e04, 0x0118, 0x9085, 0x0010,
+	0x0010, 0x9084, 0xffef, 0x2072, 0x00ee, 0x0005, 0x6050, 0x0006,
+	0x60ec, 0x0006, 0x600c, 0x0006, 0x6004, 0x0006, 0x6028, 0x0006,
+	0x0016, 0x6138, 0x6050, 0x9084, 0xfbff, 0x9085, 0x2000, 0x6052,
+	0x613a, 0x20a9, 0x0012, 0x1d04, 0x57ab, 0x2091, 0x6000, 0x1f04,
+	0x57ab, 0x602f, 0x0100, 0x602f, 0x0000, 0x6050, 0x9085, 0x0400,
+	0x9084, 0xdfff, 0x6052, 0x613a, 0x001e, 0x602f, 0x0040, 0x602f,
+	0x0000, 0x000e, 0x602a, 0x000e, 0x6006, 0x000e, 0x600e, 0x000e,
+	0x60ee, 0x60e3, 0x0000, 0x6887, 0x0001, 0x2001, 0x0001, 0x080c,
+	0x1cbe, 0x6803, 0x00a0, 0x000e, 0x6052, 0x0005, 0x0156, 0x0016,
+	0x0026, 0x0036, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100, 0x2069,
+	0x0140, 0x2071, 0x1100, 0x6020, 0x9084, 0x0080, 0x0138, 0x2001,
+	0x110c, 0x200c, 0xc1c5, 0x2102, 0x0804, 0x584f, 0x2001, 0x110c,
+	0x200c, 0xc1c4, 0x2102, 0x6028, 0x9084, 0xe1ff, 0x602a, 0x6027,
+	0x0200, 0x6803, 0x0090, 0x20a9, 0x0366, 0x6024, 0xd0cc, 0x1518,
+	0x1d04, 0x57fd, 0x2091, 0x6000, 0x1f04, 0x57fd, 0x2011, 0x0003,
+	0x080c, 0x79c2, 0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3,
+	0x080c, 0x65cf, 0x2019, 0x0000, 0x080c, 0x7936, 0x6803, 0x00a0,
+	0x2001, 0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001,
+	0x9085, 0x0001, 0x0460, 0x86ff, 0x1110, 0x080c, 0x1359, 0x60e3,
+	0x0000, 0x2001, 0x1280, 0x2004, 0x080c, 0x1cbe, 0x60e2, 0x6803,
+	0x0080, 0x20a9, 0x0366, 0x6027, 0x1e00, 0x2009, 0x1e00, 0x080c,
+	0x2055, 0x6024, 0x910c, 0x0138, 0x1d04, 0x5833, 0x2091, 0x6000,
+	0x1f04, 0x5833, 0x0818, 0x6028, 0x9085, 0x1e00, 0x602a, 0x70a0,
+	0x9005, 0x1118, 0x6887, 0x0001, 0x0008, 0x6886, 0x9006, 0x00ee,
+	0x00de, 0x00ce, 0x003e, 0x002e, 0x001e, 0x015e, 0x0005, 0x0156,
+	0x0016, 0x0026, 0x0036, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100,
+	0x2071, 0x1100, 0x2069, 0x0140, 0x6020, 0x9084, 0x00c0, 0x0120,
+	0x6884, 0x9005, 0x1904, 0x58ac, 0x6803, 0x0088, 0x60e3, 0x0000,
+	0x6887, 0x0000, 0x2001, 0x0000, 0x080c, 0x1cbe, 0x2069, 0x0200,
+	0x6804, 0x9005, 0x1118, 0x6808, 0x9005, 0x01c0, 0x6028, 0x9084,
+	0xfbff, 0x602a, 0x6027, 0x0400, 0x2069, 0x12af, 0x7000, 0x206a,
+	0x708b, 0x0026, 0x7003, 0x0001, 0x20a9, 0x0002, 0x1d04, 0x588e,
+	0x2091, 0x6000, 0x1f04, 0x588e, 0x0804, 0x58dd, 0x2069, 0x0140,
+	0x20a9, 0x0384, 0x6027, 0x1e00, 0x2009, 0x1e00, 0x080c, 0x2055,
+	0x6024, 0x910c, 0x0530, 0x9084, 0x1a00, 0x1518, 0x1d04, 0x589a,
+	0x2091, 0x6000, 0x1f04, 0x589a, 0x2011, 0x0003, 0x080c, 0x79c2,
+	0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf,
+	0x2019, 0x0000, 0x080c, 0x7936, 0x6803, 0x00a0, 0x2001, 0x1290,
+	0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x9085, 0x0001,
+	0x00a0, 0x6803, 0x0080, 0x2069, 0x0140, 0x60e3, 0x0000, 0x70a0,
+	0x9005, 0x1118, 0x6887, 0x0001, 0x0008, 0x6886, 0x2001, 0x1280,
+	0x2004, 0x080c, 0x1cbe, 0x60e2, 0x9006, 0x00ee, 0x00de, 0x00ce,
+	0x003e, 0x002e, 0x001e, 0x015e, 0x0005, 0x0156, 0x0016, 0x0026,
+	0x0036, 0x00c6, 0x00d6, 0x00e6, 0x2061, 0x0100, 0x2071, 0x1100,
+	0x6020, 0x9084, 0x00c0, 0x01f0, 0x2011, 0x0003, 0x080c, 0x79c2,
+	0x2011, 0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf,
+	0x2019, 0x0000, 0x080c, 0x7936, 0x2069, 0x0140, 0x6803, 0x00a0,
+	0x2001, 0x1290, 0x2003, 0x0001, 0x2001, 0x1100, 0x2003, 0x0001,
+	0x0804, 0x5976, 0x2001, 0x110c, 0x200c, 0xd1b4, 0x1150, 0xc1b5,
+	0x2102, 0x080c, 0x5649, 0x2069, 0x0140, 0x6803, 0x0080, 0x60e3,
+	0x0000, 0x2069, 0x0200, 0x6804, 0x9005, 0x1118, 0x6808, 0x9005,
+	0x0178, 0x6028, 0x9084, 0xfdff, 0x602a, 0x6027, 0x0200, 0x2069,
+	0x12af, 0x7000, 0x206a, 0x708b, 0x0027, 0x7003, 0x0001, 0x04f0,
+	0x6027, 0x1e00, 0x2009, 0x1e00, 0x080c, 0x2055, 0x6024, 0x910c,
+	0x01c8, 0x9084, 0x1c00, 0x11b0, 0x1d04, 0x5938, 0x0006, 0x0016,
+	0x00c6, 0x00d6, 0x00e6, 0x080c, 0x64e0, 0x00ee, 0x00de, 0x00ce,
+	0x001e, 0x000e, 0x00e6, 0x2071, 0x12ef, 0x7018, 0x00ee, 0x9005,
+	0x19f8, 0x01e0, 0x0026, 0x2011, 0x5654, 0x080c, 0x655b, 0x002e,
+	0x2069, 0x0140, 0x60e3, 0x0000, 0x70a0, 0x9005, 0x1118, 0x6887,
+	0x0001, 0x0008, 0x6886, 0x2001, 0x1280, 0x2004, 0x080c, 0x1cbe,
+	0x60e2, 0x2001, 0x110c, 0x200c, 0xc1b4, 0x2102, 0x00ee, 0x00de,
+	0x00ce, 0x003e, 0x002e, 0x001e, 0x015e, 0x0005, 0x0156, 0x0016,
+	0x0026, 0x0036, 0x0046, 0x00c6, 0x00e6, 0x2061, 0x0100, 0x2071,
+	0x1100, 0x7130, 0xd184, 0x1180, 0x2011, 0x1153, 0x2214, 0xd2ec,
+	0x0138, 0xc18d, 0x7132, 0x2011, 0x1153, 0x2214, 0xd2ac, 0x1120,
+	0x7030, 0xd08c, 0x0904, 0x59e3, 0x7130, 0xc185, 0x7132, 0x2011,
+	0x1153, 0x220c, 0xd1a4, 0x0530, 0x0016, 0x2009, 0x0001, 0x2011,
+	0x0100, 0x080c, 0x66d5, 0x2019, 0x000e, 0x080c, 0xaa50, 0x0156,
+	0x20a9, 0x007f, 0x2009, 0x0000, 0x9186, 0x007e, 0x0170, 0x9186,
+	0x0080, 0x0158, 0x080c, 0x4b58, 0x1140, 0x8127, 0x9006, 0x0016,
+	0x2009, 0x000e, 0x080c, 0xaaca, 0x001e, 0x8108, 0x1f04, 0x59b4,
+	0x015e, 0x001e, 0xd1ac, 0x1148, 0x0016, 0x2009, 0x0000, 0x2019,
+	0x0004, 0x080c, 0x2582, 0x001e, 0x0070, 0x0156, 0x20a9, 0x007f,
+	0x2009, 0x0000, 0x080c, 0x4b58, 0x1110, 0x080c, 0x472d, 0x8108,
+	0x1f04, 0x59da, 0x015e, 0x2011, 0x0003, 0x080c, 0x79c2, 0x2011,
+	0x0002, 0x080c, 0x79cc, 0x080c, 0x78b3, 0x080c, 0x65cf, 0x0036,
+	0x2019, 0x0000, 0x080c, 0x7936, 0x003e, 0x60e3, 0x0000, 0x2001,
+	0x1100, 0x2003, 0x0001, 0x080c, 0x5682, 0x00ee, 0x00ce, 0x004e,
+	0x003e, 0x002e, 0x001e, 0x015e, 0x0005, 0x2071, 0x11f4, 0x7003,
+	0x0000, 0x7007, 0x0000, 0x708f, 0x0000, 0x7093, 0x0001, 0x70c7,
+	0x0000, 0x0005, 0x00e6, 0x2071, 0x0040, 0x6848, 0x9005, 0x1120,
+	0x9085, 0x0001, 0x0804, 0x5a5e, 0x6840, 0x9005, 0x01a0, 0x900e,
+	0x0156, 0x20a9, 0x0006, 0x8003, 0x81f5, 0x3e08, 0x1f04, 0x5a23,
+	0x015e, 0x6a50, 0x9200, 0x7002, 0x6854, 0x9101, 0x7006, 0x7013,
+	0x0000, 0x7017, 0x0000, 0x6850, 0x7002, 0x6854, 0x7006, 0x6858,
+	0x700a, 0x685c, 0x700e, 0x6840, 0x9005, 0x1120, 0x7013, 0x0000,
+	0x7017, 0x0000, 0x6848, 0x701a, 0x701c, 0x9085, 0x0040, 0x701e,
+	0x2001, 0x0019, 0x7036, 0x702b, 0x0001, 0x2001, 0x0004, 0x200c,
+	0x918c, 0xfff7, 0x918d, 0x8000, 0x2102, 0x00d6, 0x2069, 0x11f4,
+	0x6807, 0x0001, 0x00de, 0x080c, 0x5f52, 0x9006, 0x00ee, 0x0005,
+	0x2079, 0x0040, 0x2071, 0x11f4, 0x7004, 0x0002, 0x5a70, 0x5a71,
+	0x5aa2, 0x5afd, 0x5bfe, 0x5a6e, 0x5a6e, 0x5c27, 0x080c, 0x0cf1,
+	0x0005, 0x2079, 0x0040, 0x782c, 0x908c, 0x0780, 0x1530, 0xd0a4,
+	0x01b0, 0x7824, 0xc0d4, 0x8006, 0x8006, 0x806f, 0x6803, 0x0000,
+	0x6807, 0x0000, 0x6864, 0x9084, 0x00ff, 0x908a, 0x0040, 0x1260,
+	0x04a3, 0x7004, 0x9086, 0x0003, 0x1d30, 0x080c, 0x5afd, 0x782c,
+	0xd09c, 0x090c, 0x5f52, 0x0005, 0x9082, 0x005a, 0x1218, 0x2100,
+	0x0053, 0x0c78, 0x080c, 0x5b37, 0x0c90, 0x2011, 0x8003, 0x080c,
+	0x37dc, 0x0cf8, 0x0005, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b57,
+	0x5b37, 0x5cdc, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b57,
+	0x5d1e, 0x5d61, 0x5daa, 0x5dbe, 0x5b37, 0x5b37, 0x5b73, 0x5b57,
+	0x5b37, 0x5b37, 0x5bd7, 0x5e67, 0x5e82, 0x5b37, 0x5b73, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5bcd, 0x5e82, 0x5b37, 0x5b37, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b87, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37,
+	0x5f8e, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b9c, 0x5b37,
+	0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x5b37, 0x2079, 0x0040, 0x7004,
+	0x9086, 0x0003, 0x11b8, 0x782c, 0x080c, 0x5f83, 0xd0a4, 0x0190,
+	0x7824, 0xc0d4, 0x8006, 0x8006, 0x806f, 0x6803, 0x0000, 0x6807,
+	0x0000, 0x6864, 0x9084, 0x00ff, 0x908a, 0x001a, 0x1210, 0x002b,
+	0x0c30, 0x00e9, 0x080c, 0x5f52, 0x0005, 0x5b37, 0x5b57, 0x5cc8,
+	0x5b37, 0x5b57, 0x5b37, 0x5b57, 0x5b57, 0x5b37, 0x5b57, 0x5cc8,
+	0x5b57, 0x5b57, 0x5b57, 0x5b57, 0x5b57, 0x5b37, 0x5b57, 0x5cc8,
+	0x5b37, 0x5b37, 0x5b57, 0x5b37, 0x5b37, 0x5b37, 0x5b57, 0x00e6,
+	0x2071, 0x11f4, 0x7007, 0x0001, 0x6868, 0x9084, 0x00ff, 0xc0d5,
+	0x686a, 0x0126, 0x2091, 0x8000, 0x080c, 0x50a5, 0x012e, 0x00ee,
+	0x0005, 0x7007, 0x0001, 0x6868, 0x9084, 0x00ff, 0xc0e5, 0x686a,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x50a5, 0x012e, 0x0005, 0x7007,
+	0x0001, 0x6868, 0x9084, 0x00ff, 0xc0ed, 0x686a, 0x0126, 0x2091,
+	0x8000, 0x080c, 0x50a5, 0x012e, 0x0005, 0x7007, 0x0001, 0x6868,
+	0x9084, 0x00ff, 0xc0dd, 0x686a, 0x0126, 0x2091, 0x8000, 0x080c,
+	0x50a5, 0x012e, 0x0005, 0x6864, 0x8007, 0x9084, 0x00ff, 0x0988,
+	0x8001, 0x1120, 0x7007, 0x0001, 0x0804, 0x5c90, 0x7007, 0x0003,
+	0x7012, 0x2d00, 0x7016, 0x701a, 0x704b, 0x5c90, 0x0005, 0x6864,
+	0x8007, 0x9084, 0x00ff, 0x0904, 0x5b49, 0x8001, 0x1120, 0x7007,
+	0x0001, 0x0804, 0x5ca9, 0x7007, 0x0003, 0x7012, 0x2d00, 0x7016,
+	0x701a, 0x704b, 0x5ca9, 0x0005, 0x6864, 0x8007, 0x9084, 0x00ff,
+	0x9086, 0x0001, 0x1904, 0x5b49, 0x7007, 0x0001, 0x2009, 0x1130,
+	0x210c, 0x81ff, 0x11a8, 0x6868, 0x9084, 0x00ff, 0x686a, 0x6883,
+	0x0000, 0x080c, 0x4873, 0x1108, 0x0005, 0x0126, 0x2091, 0x8000,
+	0x6867, 0x0139, 0x687a, 0x6982, 0x080c, 0x50a5, 0x012e, 0x0ca0,
+	0x6994, 0x9186, 0x0071, 0x0d38, 0x6897, 0x4005, 0x689b, 0x0001,
+	0x2001, 0x0030, 0x2009, 0x0000, 0x0c40, 0x687c, 0x9084, 0x00c0,
+	0x9086, 0x00c0, 0x1120, 0x7007, 0x0001, 0x0804, 0x5e99, 0x2d00,
+	0x7016, 0x701a, 0x20a9, 0x0004, 0x20e1, 0x0001, 0x20e9, 0x0001,
+	0x9080, 0x0030, 0x2098, 0x20a1, 0x1221, 0x4003, 0x6888, 0x7012,
+	0x9082, 0x0401, 0x1a04, 0x5b65, 0x6ab4, 0x928a, 0x0002, 0x1a04,
+	0x5b65, 0x82ff, 0x1138, 0x68b8, 0x69bc, 0x9105, 0x0118, 0x2001,
+	0x5c63, 0x0018, 0x9280, 0x5c59, 0x2005, 0x70ce, 0x7010, 0x9015,
+	0x0904, 0x5c45, 0x080c, 0x0dc6, 0x1118, 0x7007, 0x0004, 0x0005,
+	0x2d00, 0x7022, 0x70cc, 0x2060, 0xe000, 0x6866, 0xe004, 0x9d00,
+	0x709e, 0x709b, 0x0001, 0xe008, 0x920a, 0x1210, 0x900e, 0x2200,
+	0x7112, 0xe20c, 0x8003, 0x800b, 0x9296, 0x0004, 0x0108, 0x9108,
+	0x71a2, 0x810b, 0x71a6, 0x9e90, 0x0023, 0x080c, 0x0e55, 0x7094,
+	0x908e, 0x0100, 0x0170, 0x9086, 0x0200, 0x0118, 0x7007, 0x0007,
+	0x0005, 0x7020, 0x2068, 0x080c, 0x0df6, 0x7014, 0x2068, 0x0804,
+	0x5b65, 0x7020, 0x2068, 0x7018, 0x6802, 0x6807, 0x0000, 0x2d08,
+	0x2068, 0x6906, 0x711a, 0x0804, 0x5bfe, 0x7014, 0x2068, 0x7007,
+	0x0001, 0x68b4, 0x9005, 0x1128, 0x68b8, 0x69bc, 0x9105, 0x0108,
+	0x00b1, 0x6864, 0x9084, 0x00ff, 0x9086, 0x001e, 0x0904, 0x5e99,
+	0x04b8, 0x5c5b, 0x5c5f, 0x0002, 0x001d, 0x0007, 0x0004, 0x000a,
+	0x001b, 0x0005, 0x0006, 0x000a, 0x001d, 0x0005, 0x0004, 0x00f6,
+	0x00e6, 0x00c6, 0x0076, 0x0066, 0x6fb8, 0x6ebc, 0x6804, 0x2060,
+	0x9cf0, 0x002d, 0x9cf8, 0x0033, 0x2009, 0x0005, 0x700c, 0x7816,
+	0x7008, 0x7812, 0x7004, 0x7806, 0x7000, 0x7802, 0x7e0e, 0x7f0a,
+	0x8109, 0x0128, 0x9ef2, 0x0004, 0x9ffa, 0x0006, 0x0c78, 0x6004,
+	0x9065, 0x1d30, 0x006e, 0x007e, 0x00ce, 0x00ee, 0x00fe, 0x0005,
+	0x2009, 0x1130, 0x210c, 0x81ff, 0x1178, 0x080c, 0x477e, 0x1108,
+	0x0005, 0x080c, 0x52a0, 0x0126, 0x2091, 0x8000, 0x080c, 0x9843,
+	0x080c, 0x50a5, 0x012e, 0x0ca0, 0x2001, 0x0028, 0x2009, 0x0000,
+	0x0c80, 0x2009, 0x1130, 0x210c, 0x81ff, 0x1190, 0x6888, 0x9005,
+	0x01a0, 0x6883, 0x0000, 0x080c, 0x4817, 0x1108, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x687a, 0x6982, 0x080c, 0x50a5, 0x012e, 0x0cb0,
+	0x2001, 0x0028, 0x2009, 0x0000, 0x0c90, 0x2001, 0x0000, 0x0c78,
+	0x7018, 0x6802, 0x2d08, 0x2068, 0x6906, 0x711a, 0x7010, 0x8001,
+	0x7012, 0x0118, 0x7007, 0x0003, 0x0030, 0x7014, 0x2068, 0x7007,
+	0x0001, 0x7048, 0x080f, 0x0005, 0x7007, 0x0001, 0x6974, 0x810f,
+	0x918c, 0x00ff, 0x6878, 0x9084, 0x00ff, 0x20a9, 0x0001, 0x9096,
+	0x0001, 0x01b0, 0x2009, 0x0000, 0x20a9, 0x00ff, 0x9096, 0x0002,
+	0x0178, 0x9005, 0x11f0, 0x6974, 0x810f, 0x918c, 0x00ff, 0x080c,
+	0x4b58, 0x11b8, 0x0066, 0x6e80, 0x080c, 0x4c50, 0x006e, 0x0088,
+	0x0046, 0x2011, 0x110c, 0x2224, 0xc484, 0x2412, 0x004e, 0x00c6,
+	0x080c, 0x4b58, 0x1110, 0x080c, 0x4d11, 0x8108, 0x1f04, 0x5d08,
+	0x00ce, 0x687c, 0xd084, 0x1118, 0x080c, 0x0df6, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x50a5, 0x012e, 0x0005, 0x0126, 0x2091,
+	0x8000, 0x7007, 0x0001, 0x2001, 0x1153, 0x2004, 0xd0a4, 0x0580,
+	0x2061, 0x1329, 0x6100, 0xd184, 0x0178, 0x6888, 0x9084, 0x00ff,
+	0x1550, 0x6000, 0xd084, 0x0520, 0x6004, 0x9005, 0x1538, 0x6003,
+	0x0000, 0x600b, 0x0000, 0x00c8, 0x2011, 0x0001, 0x6890, 0x9005,
+	0x1110, 0x2001, 0x001e, 0x8000, 0x6016, 0x6888, 0x9084, 0x00ff,
+	0x0178, 0x6006, 0x6888, 0x8007, 0x9084, 0x00ff, 0x0148, 0x600a,
+	0x6888, 0x8000, 0x1108, 0xc28d, 0x6202, 0x012e, 0x0804, 0x5f3c,
+	0x012e, 0x0804, 0x5f36, 0x012e, 0x0804, 0x5f30, 0x012e, 0x0804,
+	0x5f33, 0x0126, 0x2091, 0x8000, 0x7007, 0x0001, 0x2001, 0x1153,
+	0x2004, 0xd0a4, 0x05e0, 0x2061, 0x1329, 0x6000, 0xd084, 0x05b8,
+	0x6204, 0x6308, 0xd08c, 0x1530, 0x6c78, 0x9484, 0x0003, 0x0170,
+	0x6988, 0x918c, 0x00ff, 0x8001, 0x1120, 0x2100, 0x9210, 0x0620,
+	0x0028, 0x8001, 0x1508, 0x2100, 0x9212, 0x02f0, 0x9484, 0x000c,
+	0x0188, 0x6988, 0x810f, 0x918c, 0x00ff, 0x9082, 0x0004, 0x1120,
+	0x2100, 0x9318, 0x0288, 0x0030, 0x9082, 0x0004, 0x1168, 0x2100,
+	0x931a, 0x0250, 0x6890, 0x9005, 0x0110, 0x8000, 0x6016, 0x6206,
+	0x630a, 0x012e, 0x0804, 0x5f3c, 0x012e, 0x0804, 0x5f39, 0x012e,
+	0x0804, 0x5f36, 0x0126, 0x2091, 0x8000, 0x7007, 0x0001, 0x2061,
+	0x1329, 0x6300, 0xd38c, 0x1120, 0x6308, 0x8318, 0x0220, 0x630a,
+	0x012e, 0x0804, 0x5f4a, 0x012e, 0x0804, 0x5f39, 0x0126, 0x00c6,
+	0x2091, 0x8000, 0x7007, 0x0001, 0x687c, 0xd0ac, 0x0148, 0x00c6,
+	0x2061, 0x1329, 0x6000, 0x9084, 0xfcff, 0x6002, 0x00ce, 0x0448,
+	0x6888, 0x9005, 0x05d0, 0x688c, 0x9065, 0x0598, 0x2001, 0x1130,
+	0x2004, 0x9005, 0x0118, 0x080c, 0x97a3, 0x0068, 0x6017, 0x0400,
+	0x605b, 0x0000, 0x697c, 0xd1a4, 0x0110, 0x6980, 0x615a, 0x2009,
+	0x0041, 0x080c, 0x7f4e, 0x6988, 0x918c, 0xff00, 0x9186, 0x2000,
+	0x1140, 0x0026, 0x2009, 0x0000, 0x2011, 0xfdff, 0x080c, 0x66d5,
+	0x002e, 0x687c, 0xd0c4, 0x0148, 0x2061, 0x1329, 0x6000, 0xd08c,
+	0x1120, 0x6008, 0x8000, 0x0208, 0x600a, 0x00ce, 0x012e, 0x0804,
+	0x5f3c, 0x00ce, 0x012e, 0x0804, 0x5f36, 0x6984, 0x9186, 0x002e,
+	0x0d40, 0x9186, 0x002d, 0x0d28, 0x9186, 0x0045, 0x0510, 0x9186,
+	0x002a, 0x1130, 0x2001, 0x110c, 0x200c, 0xc194, 0x2102, 0x08c8,
+	0x9186, 0x0020, 0x0170, 0x9186, 0x0029, 0x1d18, 0x6974, 0x918c,
+	0xff00, 0x810f, 0x080c, 0x4b58, 0x1960, 0x6000, 0xc0e4, 0x6002,
+	0x0840, 0x688c, 0x9065, 0x09a8, 0x2001, 0x12a6, 0x2004, 0x601a,
+	0x0800, 0x688c, 0x9065, 0x0968, 0x00e6, 0x6890, 0x9075, 0x2001,
+	0x1130, 0x2004, 0x9005, 0x0150, 0x080c, 0x97a3, 0x8eff, 0x0118,
+	0x2e60, 0x080c, 0x97a3, 0x00ee, 0x0804, 0x5df9, 0x6024, 0xc0dc,
+	0xc0d5, 0x6026, 0x2e60, 0x6007, 0x003a, 0x68a0, 0x9005, 0x0130,
+	0x6007, 0x003b, 0x68a4, 0x602e, 0x68a8, 0x6016, 0x6003, 0x0001,
+	0x080c, 0x6886, 0x080c, 0x6d42, 0x00ee, 0x0804, 0x5df9, 0x2061,
+	0x1329, 0x6000, 0xd084, 0x0190, 0xd08c, 0x1904, 0x5f4a, 0x0126,
+	0x2091, 0x8000, 0x6204, 0x8210, 0x0220, 0x6206, 0x012e, 0x0804,
+	0x5f4a, 0x012e, 0x6883, 0x0016, 0x0804, 0x5f43, 0x6883, 0x0007,
+	0x0804, 0x5f43, 0x6864, 0x8007, 0x9084, 0x00ff, 0x0130, 0x8001,
+	0x1138, 0x7007, 0x0001, 0x0069, 0x0005, 0x080c, 0x5b49, 0x0040,
+	0x7007, 0x0003, 0x7012, 0x2d00, 0x7016, 0x701a, 0x704b, 0x5e99,
+	0x0005, 0x00e6, 0x0126, 0x2091, 0x8000, 0x2061, 0x1100, 0x61c0,
+	0x81ff, 0x1904, 0x5f18, 0x6130, 0xd194, 0x1904, 0x5f20, 0x6878,
+	0x2070, 0x9e82, 0x15c0, 0x0a04, 0x5f0c, 0x6058, 0x9e02, 0x1a04,
+	0x5f0c, 0x2061, 0x1329, 0x6100, 0x9184, 0x0301, 0x9086, 0x0001,
+	0x15e8, 0x7120, 0x9186, 0x0006, 0x15f0, 0x7010, 0x9005, 0x0904,
+	0x5f18, 0x2004, 0xd0e4, 0x1904, 0x5f1b, 0x7024, 0xd0dc, 0x1904,
+	0x5f23, 0x6883, 0x0000, 0x6803, 0x0000, 0x2d08, 0x7014, 0x9005,
+	0x1198, 0x7116, 0x687c, 0xd0f4, 0x1904, 0x5f26, 0x2001, 0x1153,
+	0x2004, 0xd09c, 0x1118, 0x687c, 0xc0cc, 0x687e, 0x2e60, 0x080c,
+	0x6611, 0x012e, 0x00ee, 0x0005, 0x2068, 0x6800, 0x9005, 0x1de0,
+	0x6902, 0x2168, 0x687c, 0xd0f4, 0x15c8, 0x012e, 0x00ee, 0x0005,
+	0x012e, 0x00ee, 0x6883, 0x0006, 0x0804, 0x5f43, 0xd184, 0x0dc0,
+	0xd1c4, 0x11a8, 0x00b8, 0x6974, 0x918c, 0xff00, 0x810f, 0x080c,
+	0x4b58, 0x11c8, 0x6000, 0xd0e4, 0x11b0, 0x7120, 0x9186, 0x0007,
+	0x1118, 0x6883, 0x0002, 0x0088, 0x6883, 0x0008, 0x0070, 0x6883,
+	0x000e, 0x0058, 0x6883, 0x0017, 0x0040, 0x6883, 0x0035, 0x0028,
+	0x6883, 0x0028, 0x0010, 0x6883, 0x0029, 0x012e, 0x00ee, 0x0418,
+	0x6883, 0x002a, 0x0cd0, 0x6883, 0x0045, 0x0cb8, 0x2e60, 0x2019,
+	0x0002, 0x601b, 0x0014, 0x080c, 0xa6bc, 0x012e, 0x00ee, 0x0005,
+	0x2009, 0x003e, 0x0058, 0x2009, 0x0004, 0x0040, 0x2009, 0x0006,
+	0x0028, 0x2009, 0x0016, 0x0010, 0x2009, 0x0001, 0x6884, 0x9084,
+	0xff00, 0x9105, 0x6886, 0x0126, 0x2091, 0x8000, 0x080c, 0x50a5,
+	0x012e, 0x0005, 0x080c, 0x0df6, 0x0005, 0x00d6, 0x080c, 0x6608,
+	0x00de, 0x0005, 0x00d6, 0x00e6, 0x0126, 0x2091, 0x8000, 0x2071,
+	0x0040, 0x702c, 0xd084, 0x01f0, 0x908c, 0x0780, 0x11f8, 0xd09c,
+	0x11c8, 0x2071, 0x1100, 0x70b0, 0x90ea, 0x0010, 0x0298, 0x8001,
+	0x70b2, 0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807,
+	0x0000, 0x2071, 0x0040, 0x8d07, 0x8005, 0x8005, 0xc0d5, 0x7022,
+	0x702c, 0x0c10, 0x012e, 0x00ee, 0x00de, 0x0005, 0x2011, 0x8003,
+	0x080c, 0x37dc, 0x0cf8, 0x0006, 0x9084, 0x0780, 0x0128, 0x2011,
+	0x8003, 0x080c, 0x37dc, 0x0cf8, 0x000e, 0x0005, 0x00d6, 0x00c6,
+	0x0036, 0x0026, 0x0016, 0x7007, 0x0001, 0x6a74, 0x9282, 0x0004,
+	0x1a04, 0x5fd9, 0xd284, 0x0170, 0x6a7c, 0x9290, 0x1000, 0x2204,
+	0x9065, 0x6004, 0x05e0, 0x8007, 0x9084, 0x00ff, 0x9084, 0x0006,
+	0x1108, 0x04a8, 0x2c10, 0x080c, 0x7ec8, 0x1118, 0x080c, 0x984d,
+	0x05a0, 0x6212, 0x6874, 0x0002, 0x5fb8, 0x5fbd, 0x5fc0, 0x5fc6,
+	0x2019, 0x0002, 0x080c, 0xaa50, 0x0060, 0x080c, 0xa9e7, 0x0048,
+	0x2019, 0x0002, 0x6980, 0x080c, 0xaa02, 0x0018, 0x6980, 0x080c,
+	0xa9e7, 0x080c, 0x7f1e, 0x6887, 0x0000, 0x0126, 0x2091, 0x8000,
+	0x080c, 0x50a5, 0x012e, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00de,
+	0x0005, 0x6887, 0x0006, 0x0c88, 0x6887, 0x0002, 0x0c70, 0x6887,
+	0x0005, 0x0c58, 0x6887, 0x0004, 0x0c40, 0x6887, 0x0007, 0x0c28,
+	0x0005, 0x781c, 0xd08c, 0x05f0, 0x7d44, 0x7c40, 0x9584, 0x00f6,
+	0x1500, 0x9484, 0x7000, 0x0138, 0x908a, 0x2000, 0x1250, 0x9584,
+	0x0700, 0x8007, 0x04b2, 0x7000, 0x9084, 0xff00, 0x9086, 0x8100,
+	0x0db0, 0x9484, 0x0fff, 0x1130, 0x7000, 0x9084, 0xff00, 0x9086,
+	0x8100, 0x11e0, 0x080c, 0xadbe, 0x080c, 0x6423, 0x7817, 0x0140,
+	0x00c8, 0x9584, 0x0076, 0x1118, 0x080c, 0x6481, 0x19d0, 0xd5a4,
+	0x0168, 0x080c, 0x136e, 0x7803, 0x0010, 0x78a0, 0x78a2, 0x2001,
+	0x0160, 0x2502, 0x2001, 0x0138, 0x2202, 0x0020, 0x080c, 0xadbe,
+	0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005, 0x090c, 0x6d42,
+	0x0005, 0x6042, 0x626b, 0x6039, 0x6039, 0x6039, 0x6039, 0x6039,
+	0x6039, 0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005, 0x090c,
+	0x6d42, 0x0005, 0x7000, 0x908c, 0xff00, 0x9194, 0xf000, 0x810f,
+	0x9484, 0x0fff, 0x6882, 0x9286, 0x2000, 0x1148, 0x6800, 0x9086,
+	0x0001, 0x1118, 0x080c, 0x3e5a, 0x0068, 0x00a9, 0x0058, 0x9286,
+	0x3000, 0x1118, 0x080c, 0x61b5, 0x0028, 0x9286, 0x8000, 0x1110,
+	0x080c, 0x635d, 0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005,
+	0x090c, 0x6d42, 0x0005, 0x00c6, 0x7010, 0x9084, 0xff00, 0x8007,
+	0x9096, 0x0001, 0x0120, 0x9096, 0x0023, 0x1904, 0x61af, 0x9186,
+	0x0023, 0x1550, 0x080c, 0x63f6, 0x0904, 0x61af, 0x7124, 0x610a,
+	0x7030, 0x908e, 0x0200, 0x1130, 0x2009, 0x0015, 0x080c, 0x7f4e,
+	0x0804, 0x61af, 0x908e, 0x0214, 0x0118, 0x908e, 0x0210, 0x1130,
+	0x2009, 0x0015, 0x080c, 0x7f4e, 0x0804, 0x61af, 0x908e, 0x0100,
+	0x1904, 0x61af, 0x7034, 0x9005, 0x1904, 0x61af, 0x2009, 0x0016,
+	0x080c, 0x7f4e, 0x0804, 0x61af, 0x9186, 0x0022, 0x1904, 0x61af,
+	0x7030, 0x908e, 0x0300, 0x1580, 0x68cc, 0xd0a4, 0x0528, 0xc0b5,
+	0x68ce, 0x7100, 0x918c, 0x00ff, 0x696e, 0x7004, 0x6872, 0x00f6,
+	0x2079, 0x0100, 0x79e6, 0x78ea, 0x0006, 0x9084, 0x00ff, 0x0016,
+	0x2008, 0x080c, 0x1c93, 0x7932, 0x7936, 0x001e, 0x000e, 0x00fe,
+	0x080c, 0x1c69, 0x694e, 0x703c, 0x00e6, 0x2071, 0x0140, 0x7086,
+	0x2071, 0x1100, 0x70a2, 0x00ee, 0x7034, 0x9005, 0x1904, 0x61af,
+	0x2009, 0x0017, 0x0804, 0x6175, 0x908e, 0x0400, 0x1158, 0x7034,
+	0x9005, 0x1904, 0x61af, 0x68cc, 0xc0a5, 0x68ce, 0x2009, 0x0030,
+	0x0804, 0x6175, 0x908e, 0x0500, 0x1140, 0x7034, 0x9005, 0x1904,
+	0x61af, 0x2009, 0x0018, 0x0804, 0x6175, 0x908e, 0x2010, 0x1120,
+	0x2009, 0x0019, 0x0804, 0x6175, 0x908e, 0x2110, 0x1120, 0x2009,
+	0x001a, 0x0804, 0x6175, 0x908e, 0x5200, 0x1140, 0x7034, 0x9005,
+	0x1904, 0x61af, 0x2009, 0x001b, 0x0804, 0x6175, 0x908e, 0x5000,
+	0x1140, 0x7034, 0x9005, 0x1904, 0x61af, 0x2009, 0x001c, 0x0804,
+	0x6175, 0x908e, 0x1300, 0x1120, 0x2009, 0x0034, 0x0804, 0x6175,
+	0x908e, 0x1200, 0x1140, 0x7034, 0x9005, 0x1904, 0x61af, 0x2009,
+	0x0024, 0x0804, 0x6175, 0x908c, 0xff00, 0x918e, 0x2400, 0x1120,
+	0x2009, 0x002d, 0x0804, 0x6175, 0x908c, 0xff00, 0x918e, 0x5300,
+	0x1118, 0x2009, 0x002a, 0x04c8, 0x908e, 0x0f00, 0x1118, 0x2009,
+	0x0020, 0x0498, 0x908e, 0x5300, 0x1108, 0x00d8, 0x908e, 0x6104,
+	0x11c0, 0x2011, 0x026d, 0x8208, 0x2204, 0x9082, 0x0004, 0x8004,
+	0x8004, 0x20a8, 0x2011, 0x8015, 0x211c, 0x8108, 0x0046, 0x2124,
+	0x080c, 0x37dc, 0x004e, 0x8108, 0x1f04, 0x6152, 0x2009, 0x0023,
+	0x00a0, 0x908e, 0x6000, 0x1118, 0x2009, 0x003f, 0x0070, 0x908e,
+	0x7800, 0x1118, 0x2009, 0x0045, 0x0040, 0x908e, 0x6300, 0x1118,
+	0x2009, 0x004a, 0x0010, 0x2009, 0x001d, 0x0016, 0x2011, 0x0263,
+	0x2204, 0x8211, 0x220c, 0x080c, 0x1c69, 0x1598, 0x080c, 0x4b03,
+	0x1580, 0x6612, 0x6516, 0x86ff, 0x01e8, 0x001e, 0x0016, 0x9186,
+	0x0017, 0x1158, 0x686c, 0x9606, 0x11a8, 0x6870, 0x9506, 0x9084,
+	0xff00, 0x1180, 0x6000, 0xc0f5, 0x6002, 0x9186, 0x0046, 0x1150,
+	0x686c, 0x9606, 0x1138, 0x6870, 0x9506, 0x9084, 0xff00, 0x1110,
+	0x001e, 0x0068, 0x00c6, 0x080c, 0x7ec8, 0x0168, 0x001e, 0x6112,
+	0x6023, 0x0004, 0x7120, 0x610a, 0x001e, 0x080c, 0x7f4e, 0x00ce,
+	0x0005, 0x001e, 0x0ce0, 0x00ce, 0x0ce0, 0x080c, 0x26bc, 0x1140,
+	0x7010, 0x9084, 0xff00, 0x8007, 0x908e, 0x0008, 0x1108, 0x0009,
+	0x0005, 0x00c6, 0x0046, 0x7000, 0x908c, 0xff00, 0x810f, 0x9186,
+	0x0033, 0x11e8, 0x080c, 0x63f6, 0x0904, 0x6212, 0x7124, 0x610a,
+	0x7030, 0x908e, 0x0200, 0x1140, 0x7034, 0x9005, 0x15d8, 0x2009,
+	0x0015, 0x080c, 0x7f4e, 0x04b0, 0x908e, 0x0100, 0x1598, 0x7034,
+	0x9005, 0x1580, 0x2009, 0x0016, 0x080c, 0x7f4e, 0x0458, 0x9186,
+	0x0032, 0x1540, 0x7030, 0x908e, 0x1400, 0x1520, 0x2009, 0x0038,
+	0x0016, 0x2011, 0x0263, 0x2204, 0x8211, 0x220c, 0x080c, 0x1c69,
+	0x11c0, 0x080c, 0x4b03, 0x11a8, 0x6612, 0x6516, 0x00c6, 0x080c,
+	0x7ec8, 0x0170, 0x001e, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0004,
+	0x7120, 0x610a, 0x001e, 0x080c, 0x7f4e, 0x080c, 0x6d42, 0x0010,
+	0x00ce, 0x001e, 0x004e, 0x00ce, 0x0005, 0x0046, 0x00e6, 0x00d6,
+	0x2028, 0x2130, 0x9696, 0x00ff, 0x11b0, 0x9592, 0xfffc, 0x0298,
+	0x9596, 0xfffd, 0x1120, 0x2009, 0x007f, 0x0804, 0x6266, 0x9596,
+	0xfffe, 0x1118, 0x2009, 0x007e, 0x04c8, 0x9596, 0xfffc, 0x1118,
+	0x2009, 0x0080, 0x0498, 0x2011, 0x0000, 0x2019, 0x1133, 0x231c,
+	0xd3ac, 0x0138, 0x2021, 0x0000, 0x20a9, 0x00ff, 0x2071, 0x1000,
+	0x0030, 0x2021, 0x0081, 0x20a9, 0x007e, 0x2071, 0x1081, 0x2e1c,
+	0x93ed, 0x0000, 0x1128, 0x82ff, 0x1170, 0x2410, 0xc2fd, 0x0058,
+	0x6f10, 0x2600, 0x9706, 0x6814, 0x1120, 0x9546, 0x1110, 0x2408,
+	0x0068, 0x9745, 0x0d80, 0x8420, 0x8e70, 0x1f04, 0x6247, 0x82ff,
+	0x1118, 0x9085, 0x0001, 0x0018, 0xc2fc, 0x2208, 0x9006, 0x00de,
+	0x00ee, 0x004e, 0x0005, 0x7000, 0x908c, 0xff00, 0x810f, 0x9184,
+	0x0007, 0x004a, 0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005,
+	0x090c, 0x6d42, 0x0005, 0x628b, 0x628b, 0x628b, 0x6408, 0x628b,
+	0x6294, 0x62b1, 0x6340, 0x628b, 0x628b, 0x628b, 0x628b, 0x628b,
+	0x628b, 0x628b, 0x628b, 0x7817, 0x0140, 0x2001, 0x12e5, 0x2004,
+	0x9005, 0x090c, 0x6d42, 0x0005, 0x7110, 0xd1bc, 0x0188, 0x7120,
+	0x2160, 0x9c8c, 0x0007, 0x1160, 0x9c8a, 0x15c0, 0x0248, 0x6858,
+	0x9c02, 0x1230, 0x7124, 0x610a, 0x2009, 0x0046, 0x080c, 0x7f4e,
+	0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005, 0x090c, 0x6d42,
+	0x0005, 0x00c6, 0x7110, 0xd1bc, 0x1904, 0x6316, 0x7108, 0x700c,
+	0x2028, 0x918c, 0x00ff, 0x2130, 0x9094, 0xff00, 0x15d8, 0x81ff,
+	0x15c8, 0x9080, 0x26c1, 0x200d, 0x918c, 0xff00, 0x810f, 0x9006,
+	0x1904, 0x6316, 0x080c, 0x4b03, 0x1904, 0x6316, 0x6612, 0x6516,
+	0x6000, 0xd0ec, 0x1904, 0x6316, 0x6204, 0x9294, 0xff00, 0x8217,
+	0x9286, 0x0006, 0x1190, 0x00c6, 0x080c, 0x7ec8, 0x001e, 0x0904,
+	0x6320, 0x6112, 0x6023, 0x0006, 0x7120, 0x610a, 0x7130, 0x6156,
+	0x2009, 0x0044, 0x080c, 0x7f4e, 0x0448, 0x080c, 0x5745, 0x1170,
+	0x6204, 0x9294, 0x00ff, 0x9286, 0x0006, 0x1140, 0x9295, 0x0600,
+	0x6206, 0x0c08, 0x190c, 0x6215, 0x11c8, 0x0860, 0x00c6, 0x080c,
+	0x7ec8, 0x001e, 0x0198, 0x6112, 0x6023, 0x0004, 0x7120, 0x610a,
+	0x9286, 0x0004, 0x1118, 0x6007, 0x0005, 0x0010, 0x6007, 0x0001,
+	0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x7817, 0x0140,
+	0x2001, 0x12e5, 0x2004, 0x9005, 0x090c, 0x6d42, 0x00ce, 0x0005,
+	0x2001, 0x110d, 0x2004, 0xd0ec, 0x0120, 0x2011, 0x8049, 0x080c,
+	0x37dc, 0x00c6, 0x080c, 0x984d, 0x001e, 0x0d40, 0x6112, 0x6023,
+	0x0006, 0x7120, 0x610a, 0x7130, 0x6156, 0x6017, 0x0300, 0x6003,
+	0x0001, 0x6007, 0x0041, 0x080c, 0x6886, 0x080c, 0x6d42, 0x08b0,
+	0x7110, 0xd1bc, 0x0188, 0x7020, 0x2060, 0x9c84, 0x0007, 0x1160,
+	0x9c82, 0x15c0, 0x0248, 0x6858, 0x9c02, 0x1230, 0x7124, 0x610a,
+	0x2009, 0x0045, 0x080c, 0x7f4e, 0x7817, 0x0140, 0x2001, 0x12e5,
+	0x2004, 0x9005, 0x090c, 0x6d42, 0x0005, 0x080c, 0x26bc, 0x1168,
+	0x7010, 0x9084, 0xff00, 0x8007, 0x9086, 0x0000, 0x1130, 0x9184,
+	0x000f, 0x908a, 0x0006, 0x1208, 0x000b, 0x0005, 0x6374, 0x6375,
+	0x6374, 0x6374, 0x63de, 0x63ea, 0x0005, 0x7110, 0xd1bc, 0x0120,
+	0x702c, 0xd084, 0x0904, 0x63dd, 0x700c, 0x7108, 0x080c, 0x1c69,
+	0x1904, 0x63dd, 0x080c, 0x4b03, 0x1904, 0x63dd, 0x6612, 0x6516,
+	0x6204, 0x7110, 0xd1bc, 0x01f8, 0x928c, 0x00ff, 0x9186, 0x0004,
+	0x0118, 0x9186, 0x0006, 0x15c8, 0x00c6, 0x080c, 0x63f6, 0x00ce,
+	0x0904, 0x63dd, 0x00c6, 0x080c, 0x7ec8, 0x001e, 0x05f0, 0x6112,
+	0x080c, 0x99cc, 0x6023, 0x0002, 0x7120, 0x610a, 0x2009, 0x0088,
+	0x080c, 0x7f4e, 0x0490, 0x928c, 0x00ff, 0x9186, 0x0006, 0x0160,
+	0x9186, 0x0004, 0x0148, 0x9294, 0xff00, 0x8217, 0x9286, 0x0004,
+	0x0118, 0x9286, 0x0006, 0x1188, 0x00c6, 0x080c, 0x7ec8, 0x001e,
+	0x01e0, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0005, 0x7120, 0x610a,
+	0x2009, 0x0088, 0x080c, 0x7f4e, 0x0080, 0x00c6, 0x080c, 0x7ec8,
+	0x001e, 0x0158, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0004, 0x7120,
+	0x610a, 0x2009, 0x0001, 0x080c, 0x7f4e, 0x0005, 0x7110, 0xd1bc,
+	0x0140, 0x00a1, 0x0130, 0x7124, 0x610a, 0x2009, 0x0089, 0x080c,
+	0x7f4e, 0x0005, 0x7110, 0xd1bc, 0x0140, 0x0041, 0x0130, 0x7124,
+	0x610a, 0x2009, 0x008a, 0x080c, 0x7f4e, 0x0005, 0x7020, 0x2060,
+	0x9c84, 0x0007, 0x1158, 0x9c82, 0x15c0, 0x0240, 0x2001, 0x1116,
+	0x2004, 0x9c02, 0x1218, 0x9085, 0x0001, 0x0005, 0x9006, 0x0ce8,
+	0x7110, 0xd1bc, 0x1178, 0x7024, 0x2060, 0x9c84, 0x0007, 0x1150,
+	0x9c82, 0x15c0, 0x0238, 0x6858, 0x9c02, 0x1220, 0x2009, 0x0051,
+	0x080c, 0x7f4e, 0x7817, 0x0140, 0x2001, 0x12e5, 0x2004, 0x9005,
+	0x090c, 0x6d42, 0x0005, 0x2031, 0x0105, 0x0069, 0x0005, 0x2031,
+	0x0206, 0x0049, 0x0005, 0x2031, 0x0207, 0x0029, 0x0005, 0x2031,
+	0x0213, 0x0009, 0x0005, 0x00c6, 0x00d6, 0x00f6, 0x7000, 0x9084,
+	0xf000, 0x9086, 0xc000, 0x05d0, 0x080c, 0x7ec8, 0x05b8, 0x0066,
+	0x00c6, 0x0046, 0x2011, 0x0263, 0x2204, 0x8211, 0x220c, 0x080c,
+	0x1c69, 0x15a0, 0x080c, 0x4b03, 0x1588, 0x6612, 0x6516, 0x2c00,
+	0x004e, 0x00ce, 0x6012, 0x080c, 0x99cc, 0x080c, 0x0ddf, 0x0510,
+	0x2d00, 0x605a, 0x6803, 0x0000, 0x6867, 0x0000, 0x6c6a, 0x9df8,
+	0x001b, 0x20a9, 0x000e, 0x20e9, 0x0001, 0x20e1, 0x0000, 0x2fa0,
+	0x2e98, 0x4003, 0x006e, 0x6616, 0x6007, 0x003e, 0x6023, 0x0001,
+	0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x00fe, 0x00de,
+	0x00ce, 0x0005, 0x080c, 0x7f1e, 0x006e, 0x0cc0, 0x004e, 0x00ce,
+	0x0cc8, 0x00c6, 0x7000, 0x908c, 0xff00, 0x9184, 0xf000, 0x810f,
+	0x9086, 0x2000, 0x1548, 0x9186, 0x0022, 0x11d8, 0x2001, 0x0111,
+	0x2004, 0x9005, 0x1518, 0x7030, 0x908e, 0x0400, 0x01f8, 0x908e,
+	0x6000, 0x01e0, 0x908e, 0x5400, 0x01c8, 0x908e, 0x0300, 0x1140,
+	0x2009, 0x1133, 0x210c, 0xd184, 0x0118, 0x080c, 0x5745, 0x0170,
+	0x0058, 0x9186, 0x0023, 0x1140, 0x080c, 0x63f6, 0x0128, 0x6004,
+	0x9086, 0x0002, 0x0118, 0x0000, 0x9006, 0x0010, 0x9085, 0x0001,
+	0x00ce, 0x0005, 0x2071, 0x12ef, 0x7003, 0x0003, 0x700f, 0x0361,
+	0x9006, 0x701a, 0x7012, 0x7017, 0x15c0, 0x7007, 0x0000, 0x7026,
+	0x702b, 0x772e, 0x7032, 0x7037, 0x778e, 0x703b, 0xffff, 0x703f,
+	0xffff, 0x7042, 0x7047, 0x3d63, 0x704a, 0x705b, 0x65ea, 0x2001,
+	0x1291, 0x2003, 0x0003, 0x2001, 0x1293, 0x2003, 0x0100, 0x0005,
+	0x2071, 0x12ef, 0x1d04, 0x654a, 0x2091, 0x6000, 0x700c, 0x8001,
+	0x700e, 0x1180, 0x700f, 0x0361, 0x7007, 0x0001, 0x0126, 0x2091,
+	0x8000, 0x7040, 0x900d, 0x0148, 0x8109, 0x7142, 0x1130, 0x7044,
+	0x080f, 0x0018, 0x0126, 0x2091, 0x8000, 0x7024, 0x900d, 0x0188,
+	0x7020, 0x8001, 0x7022, 0x1168, 0x7023, 0x0009, 0x8109, 0x7126,
+	0x9186, 0x03e8, 0x1110, 0x7028, 0x080f, 0x81ff, 0x1110, 0x7028,
+	0x080f, 0x7030, 0x900d, 0x0158, 0x702c, 0x8001, 0x702e, 0x1138,
+	0x702f, 0x0009, 0x8109, 0x7132, 0x1110, 0x7034, 0x080f, 0x7038,
+	0x9005, 0x0118, 0x0310, 0x8001, 0x703a, 0x703c, 0x9005, 0x0118,
+	0x0310, 0x8001, 0x703e, 0x704c, 0x900d, 0x0168, 0x7048, 0x8001,
+	0x704a, 0x1148, 0x704b, 0x0009, 0x8109, 0x714e, 0x1120, 0x7150,
+	0x714e, 0x7058, 0x080f, 0x7018, 0x900d, 0x0158, 0x7008, 0x8001,
+	0x700a, 0x1138, 0x700b, 0x0009, 0x8109, 0x711a, 0x1110, 0x701c,
+	0x080f, 0x012e, 0x7004, 0x0002, 0x6570, 0x6571, 0x6589, 0x00e6,
+	0x2071, 0x12ef, 0x7018, 0x9005, 0x1120, 0x711a, 0x721e, 0x700b,
+	0x0009, 0x00ee, 0x0005, 0x00e6, 0x0006, 0x2071, 0x12ef, 0x701c,
+	0x9206, 0x1110, 0x701a, 0x701e, 0x000e, 0x00ee, 0x0005, 0x00e6,
+	0x2071, 0x12ef, 0x6088, 0x9102, 0x0208, 0x618a, 0x00ee, 0x0005,
+	0x0005, 0x7110, 0x080c, 0x4b58, 0x1158, 0x6088, 0x8001, 0x0240,
+	0x608a, 0x1130, 0x0126, 0x2091, 0x8000, 0x080c, 0x6d42, 0x012e,
+	0x8108, 0x9182, 0x00ff, 0x0218, 0x900e, 0x7007, 0x0002, 0x7112,
+	0x0005, 0x7014, 0x2060, 0x0126, 0x2091, 0x8000, 0x6040, 0x9005,
+	0x0128, 0x8001, 0x6042, 0x1110, 0x080c, 0x9887, 0x6018, 0x9005,
+	0x0500, 0x8001, 0x601a, 0x11e8, 0x6120, 0x9186, 0x0003, 0x0118,
+	0x9186, 0x0006, 0x11a0, 0x6014, 0x2068, 0x6884, 0x908a, 0x199a,
+	0x0270, 0x9082, 0x1999, 0x6886, 0x908a, 0x199a, 0x0210, 0x2001,
+	0x1999, 0x8003, 0x800b, 0x810b, 0x9108, 0x611a, 0x0010, 0x080c,
+	0x9362, 0x012e, 0x9c88, 0x0018, 0x7116, 0x2001, 0x45c0, 0x9102,
+	0x0220, 0x7017, 0x15c0, 0x7007, 0x0000, 0x0005, 0x00e6, 0x2071,
+	0x12ef, 0x7027, 0x07d0, 0x7023, 0x0009, 0x00ee, 0x0005, 0x2001,
+	0x12f8, 0x2003, 0x0000, 0x0005, 0x00e6, 0x2071, 0x12ef, 0x7132,
+	0x702f, 0x0009, 0x00ee, 0x0005, 0x2011, 0x12fb, 0x2013, 0x0000,
+	0x0005, 0x00e6, 0x2071, 0x12ef, 0x711a, 0x721e, 0x700b, 0x0009,
+	0x00ee, 0x0005, 0x00c6, 0x0026, 0x7054, 0x8000, 0x7056, 0x2061,
+	0x1291, 0x6008, 0x9086, 0x0000, 0x0158, 0x7068, 0x6036, 0x7064,
+	0x6032, 0x7060, 0x602e, 0x705c, 0x602a, 0x2c10, 0x080c, 0x0e55,
+	0x002e, 0x00ce, 0x0005, 0x00c6, 0x2061, 0x1329, 0x00ce, 0x0005,
+	0x9184, 0x000f, 0x8003, 0x8003, 0x8003, 0x9080, 0x1329, 0x2060,
+	0x0005, 0x6884, 0x908a, 0x199a, 0x1630, 0x9005, 0x1150, 0x00c6,
+	0x2061, 0x1329, 0x6014, 0x00ce, 0x9005, 0x1130, 0x2001, 0x001e,
+	0x0018, 0x908e, 0xffff, 0x01a8, 0x8003, 0x800b, 0x810b, 0x9108,
+	0x611a, 0x687c, 0x908c, 0x00c0, 0x918e, 0x00c0, 0x0904, 0x668a,
+	0xd0b4, 0x1160, 0xd0bc, 0x15b8, 0x2009, 0x0006, 0x080c, 0x66b0,
+	0x0005, 0x900e, 0x0c68, 0x2001, 0x1999, 0x08b8, 0xd0fc, 0x0160,
+	0x908c, 0x0003, 0x0120, 0x918e, 0x0003, 0x1904, 0x66aa, 0x908c,
+	0x2020, 0x918e, 0x2020, 0x0180, 0x6024, 0xd0d4, 0x11a8, 0x2009,
+	0x1174, 0x2104, 0xd084, 0x1120, 0x2009, 0x0043, 0x0804, 0x7f4e,
+	0x2009, 0x0042, 0x0804, 0x7f4e, 0x6110, 0x210c, 0xd1ac, 0x0d60,
+	0x6024, 0xc0cd, 0x6026, 0x0c40, 0xc0d4, 0x6026, 0x6890, 0x602e,
+	0x688c, 0x6032, 0x0c20, 0xd0fc, 0x0158, 0x908c, 0x0003, 0x0118,
+	0x908e, 0x0003, 0x15b8, 0x908c, 0x2020, 0x918e, 0x2020, 0x0150,
+	0x00f6, 0x2c78, 0x080c, 0x119d, 0x00fe, 0x2009, 0x0042, 0x080c,
+	0x7f4e, 0x0005, 0x6110, 0x210c, 0xd1ac, 0x0d90, 0x6124, 0xc1cd,
+	0x6126, 0x0c70, 0xd0fc, 0x0178, 0x908c, 0x2020, 0x918e, 0x2020,
+	0x0188, 0x9084, 0x0003, 0x908e, 0x0002, 0x0138, 0x2009, 0x0041,
+	0x080c, 0x7f4e, 0x0005, 0x0091, 0x0ce8, 0x2009, 0x0043, 0x080c,
+	0x7f4e, 0x0cc0, 0x6110, 0x210c, 0xd1ac, 0x0d58, 0x6124, 0xc1cd,
+	0x6126, 0x0c38, 0x2009, 0x0004, 0x0019, 0x0005, 0x2009, 0x0001,
+	0x00d6, 0x6014, 0x90ec, 0xf000, 0x01f0, 0x2068, 0x6982, 0x6800,
+	0x6016, 0x9186, 0x0001, 0x1188, 0x697c, 0x918c, 0x8100, 0x918e,
+	0x8100, 0x1158, 0x00c6, 0x2061, 0x1329, 0x6200, 0xd28c, 0x1120,
+	0x6204, 0x8210, 0x0208, 0x6206, 0x00ce, 0x080c, 0x4ef4, 0x6014,
+	0x906d, 0x190c, 0x6611, 0x00de, 0x0005, 0x0156, 0x00c6, 0x2061,
+	0x1329, 0x6000, 0x81ff, 0x0110, 0x9205, 0x0008, 0x9204, 0x6002,
+	0x00ce, 0x015e, 0x0005, 0x6800, 0xd08c, 0x1138, 0x6808, 0x9005,
+	0x0120, 0x8001, 0x680a, 0x9085, 0x0001, 0x0005, 0x20a9, 0x0010,
+	0x9006, 0x8004, 0x80f6, 0x3e00, 0x81f6, 0x3e08, 0x1208, 0x9200,
+	0x1f04, 0x66f2, 0x80f6, 0x3e00, 0x81f6, 0x3e08, 0x0005, 0x0156,
+	0x20a9, 0x0010, 0x9005, 0x01c0, 0x911a, 0x12b0, 0x8213, 0x81f5,
+	0x3e08, 0x0228, 0x911a, 0x1220, 0x1f04, 0x6706, 0x0028, 0x911a,
+	0x2308, 0x8210, 0x1f04, 0x6706, 0x0006, 0x3200, 0x9084, 0xefff,
+	0x2080, 0x000e, 0x015e, 0x0005, 0x0006, 0x3200, 0x9085, 0x1000,
+	0x0cb8, 0x0126, 0x2091, 0x2800, 0x2079, 0x12dc, 0x012e, 0x00d6,
+	0x2069, 0x12dc, 0x6803, 0x0005, 0x0156, 0x0146, 0x01d6, 0x20e9,
+	0x0000, 0x2069, 0x0200, 0x080c, 0x7e9b, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e86, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e89, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e8c, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e8f, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e92, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e95, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x080c, 0x7e98, 0x20a9, 0x0020, 0x20a1,
+	0x0240, 0x9006, 0x4004, 0x01de, 0x014e, 0x015e, 0x2069, 0x0004,
+	0x2d04, 0x9085, 0x8001, 0x206a, 0x00de, 0x0005, 0x00c6, 0x6027,
+	0x0001, 0x7804, 0x9084, 0x0007, 0x0002, 0x678f, 0x67b3, 0x67fd,
+	0x6795, 0x67b3, 0x678f, 0x678d, 0x678d, 0x080c, 0x0cf1, 0x080c,
+	0x65cf, 0x080c, 0x6d42, 0x00ce, 0x0005, 0x62c0, 0x82ff, 0x1110,
+	0x00ce, 0x0005, 0x2011, 0x4586, 0x080c, 0x655b, 0x7828, 0x9092,
+	0x00c8, 0x1228, 0x8000, 0x782a, 0x080c, 0x45c0, 0x0c88, 0x62c0,
+	0x080c, 0x7e9f, 0x080c, 0x4586, 0x7807, 0x0003, 0x7827, 0x0000,
+	0x782b, 0x0000, 0x0c28, 0x080c, 0x65cf, 0x6220, 0xd2a4, 0x0178,
+	0x62c0, 0x82ff, 0x1160, 0x782b, 0x0000, 0x7824, 0x9065, 0x090c,
+	0x0cf1, 0x2009, 0x0013, 0x080c, 0x7f4e, 0x00ce, 0x0005, 0x00c6,
+	0x7824, 0x9065, 0x090c, 0x0cf1, 0x7804, 0x9086, 0x0004, 0x0904,
+	0x6839, 0x7828, 0x9092, 0x2710, 0x1230, 0x8000, 0x782a, 0x00ce,
+	0x080c, 0x76fd, 0x0c50, 0x2011, 0x0130, 0x2214, 0x080c, 0x7e9f,
+	0x6104, 0x9186, 0x0003, 0x1188, 0x00e6, 0x2071, 0x1100, 0x70d8,
+	0x00ee, 0xd08c, 0x0150, 0x00c6, 0x00e6, 0x2061, 0x0100, 0x2071,
+	0x1100, 0x080c, 0x45d6, 0x00ee, 0x00ce, 0x080c, 0xae07, 0x2009,
+	0x0014, 0x080c, 0x7f4e, 0x00ce, 0x0840, 0x2001, 0x12f8, 0x2003,
+	0x0000, 0x62c0, 0x82ff, 0x1160, 0x782b, 0x0000, 0x7824, 0x9065,
+	0x090c, 0x0cf1, 0x2009, 0x0013, 0x080c, 0x7fa6, 0x00ce, 0x0005,
+	0x00c6, 0x00d6, 0x7824, 0x9005, 0x090c, 0x0cf1, 0x781c, 0x906d,
+	0x090c, 0x0cf1, 0x080c, 0x7e9f, 0x6800, 0xc0dc, 0x6802, 0x7924,
+	0x2160, 0x080c, 0x7f1e, 0x693c, 0x81ff, 0x090c, 0x0cf1, 0x8109,
+	0x693e, 0x6854, 0x9015, 0x0110, 0x7a1e, 0x0010, 0x7918, 0x791e,
+	0x7807, 0x0000, 0x7827, 0x0000, 0x00de, 0x00ce, 0x080c, 0x6d42,
+	0x08a8, 0x6104, 0x9186, 0x0002, 0x0128, 0x9186, 0x0004, 0x0110,
+	0x0804, 0x67d1, 0x7808, 0x9c06, 0x0904, 0x67d1, 0x080c, 0x6c56,
+	0x080c, 0x68ce, 0x00ce, 0x080c, 0x6d42, 0x0804, 0x67c5, 0x00c6,
+	0x6024, 0x6027, 0x0002, 0xd0f4, 0x1550, 0x62c8, 0x60c4, 0x9205,
+	0x1170, 0x783c, 0x9065, 0x0130, 0x2009, 0x0049, 0x080c, 0x7f4e,
+	0x00ce, 0x0005, 0x2011, 0x12fb, 0x2013, 0x0000, 0x0cc8, 0x793c,
+	0x81ff, 0x0dc0, 0x793c, 0x9188, 0x0008, 0x210c, 0x918e, 0x0006,
+	0x1138, 0x6014, 0x9084, 0x1984, 0x9085, 0x0012, 0x6016, 0x0c40,
+	0x6014, 0x9084, 0x1984, 0x9085, 0x0016, 0x6016, 0x0c08, 0x793c,
+	0x2160, 0x2009, 0x004a, 0x080c, 0x7f4e, 0x08d0, 0x0006, 0x0016,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x600f, 0x0000, 0x2c08, 0x2061,
+	0x12dc, 0x6020, 0x8000, 0x6022, 0x6010, 0x9005, 0x0148, 0x9080,
+	0x0003, 0x2102, 0x6112, 0x012e, 0x00ce, 0x001e, 0x000e, 0x0005,
+	0x6116, 0x6112, 0x0cc0, 0x00d6, 0x2069, 0x12dc, 0x6000, 0xd0d4,
+	0x0178, 0x6820, 0x8000, 0x6822, 0x9086, 0x0001, 0x1110, 0x2c00,
+	0x681e, 0x6804, 0x9084, 0x0007, 0x0804, 0x6d59, 0x00de, 0x0005,
+	0xc0d5, 0x6002, 0x6818, 0x9005, 0x0158, 0x6056, 0x605b, 0x0000,
+	0x0006, 0x2c00, 0x681a, 0x00de, 0x685a, 0x2069, 0x12dc, 0x0c08,
+	0x6056, 0x605a, 0x2c00, 0x681a, 0x681e, 0x08d8, 0x0006, 0x0016,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x600f, 0x0000, 0x2c08, 0x2061,
+	0x12dc, 0x6020, 0x8000, 0x6022, 0x6008, 0x9005, 0x0148, 0x9080,
+	0x0003, 0x2102, 0x610a, 0x012e, 0x00ce, 0x001e, 0x000e, 0x0005,
+	0x610e, 0x610a, 0x0cc0, 0x00c6, 0x600f, 0x0000, 0x2c08, 0x2061,
+	0x12dc, 0x6034, 0x9005, 0x0130, 0x9080, 0x0003, 0x2102, 0x6136,
+	0x00ce, 0x0005, 0x613a, 0x6136, 0x00ce, 0x0005, 0x00f6, 0x00e6,
+	0x00d6, 0x00c6, 0x0076, 0x0066, 0x0026, 0x0016, 0x0006, 0x0126,
+	0x2071, 0x12dc, 0x7638, 0x2660, 0x2678, 0x2091, 0x8000, 0x8cff,
+	0x0904, 0x696a, 0x6010, 0x9080, 0x0028, 0x2004, 0x9206, 0x1904,
+	0x6965, 0x87ff, 0x0120, 0x6054, 0x9106, 0x1904, 0x6965, 0x703c,
+	0x9c06, 0x1170, 0x0036, 0x2019, 0x0001, 0x080c, 0x7936, 0x7033,
+	0x0000, 0x703f, 0x0000, 0x7043, 0x0000, 0x7047, 0x0000, 0x003e,
+	0x7038, 0x9c36, 0x1110, 0x660c, 0x763a, 0x7034, 0x9c36, 0x1140,
+	0x2c00, 0x9f36, 0x0118, 0x2f00, 0x7036, 0x0010, 0x7037, 0x0000,
+	0x660c, 0x0066, 0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008, 0x2678,
+	0x600f, 0x0000, 0x080c, 0x95d2, 0x0198, 0x6014, 0x2068, 0x6020,
+	0x9086, 0x0003, 0x1510, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000,
+	0x080c, 0x9843, 0x080c, 0xad5f, 0x080c, 0x50a5, 0x080c, 0x9797,
+	0x080c, 0x97a3, 0x00ce, 0x0804, 0x690f, 0x2c78, 0x600c, 0x2060,
+	0x0804, 0x690f, 0x012e, 0x000e, 0x001e, 0x002e, 0x006e, 0x007e,
+	0x00ce, 0x00de, 0x00ee, 0x00fe, 0x0005, 0x6020, 0x9086, 0x0006,
+	0x1128, 0x080c, 0xad5f, 0x080c, 0xaa84, 0x0c10, 0x08a0, 0x0006,
+	0x0066, 0x00c6, 0x00d6, 0x00f6, 0x2031, 0x0000, 0x0126, 0x2091,
+	0x8000, 0x2079, 0x12dc, 0x7838, 0x9065, 0x0558, 0x600c, 0x0006,
+	0x600f, 0x0000, 0x783c, 0x9c06, 0x1170, 0x0036, 0x2019, 0x0001,
+	0x080c, 0x7936, 0x7833, 0x0000, 0x783f, 0x0000, 0x7843, 0x0000,
+	0x7847, 0x0000, 0x003e, 0x080c, 0x95d2, 0x0178, 0x6014, 0x2068,
+	0x6020, 0x9086, 0x0003, 0x11b0, 0x6867, 0x0103, 0x6b7a, 0x6877,
+	0x0000, 0x080c, 0x50a5, 0x080c, 0x9797, 0x080c, 0x97a3, 0x000e,
+	0x0898, 0x7e3a, 0x7e36, 0x012e, 0x00fe, 0x00de, 0x00ce, 0x006e,
+	0x000e, 0x0005, 0x6020, 0x9086, 0x0006, 0x1118, 0x080c, 0xaa84,
+	0x0c60, 0x0c10, 0x0016, 0x0026, 0x0086, 0x2041, 0x0000, 0x0099,
+	0x080c, 0x6a8c, 0x008e, 0x002e, 0x001e, 0x0005, 0x00f6, 0x0126,
+	0x2079, 0x12dc, 0x2091, 0x8000, 0x080c, 0x6b19, 0x080c, 0x6b8b,
+	0x012e, 0x00fe, 0x0005, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0066,
+	0x0016, 0x0006, 0x0126, 0x2091, 0x8000, 0x2071, 0x12dc, 0x7614,
+	0x2660, 0x2678, 0x8cff, 0x0904, 0x6a68, 0x6010, 0x9080, 0x0028,
+	0x2004, 0x9206, 0x1904, 0x6a63, 0x88ff, 0x0120, 0x6054, 0x9106,
+	0x1904, 0x6a63, 0x7024, 0x9c06, 0x1538, 0x2069, 0x0100, 0x68c0,
+	0x9005, 0x01f0, 0x080c, 0x65cf, 0x080c, 0x7721, 0x68c3, 0x0000,
+	0x080c, 0x7b56, 0x7027, 0x0000, 0x0036, 0x2069, 0x0140, 0x6b04,
+	0x9384, 0x1000, 0x0120, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069,
+	0x0100, 0x6824, 0xd084, 0x0110, 0x6827, 0x0001, 0x003e, 0x0020,
+	0x6003, 0x0009, 0x630a, 0x04b8, 0x7014, 0x9c36, 0x1110, 0x660c,
+	0x7616, 0x7010, 0x9c36, 0x1140, 0x2c00, 0x9f36, 0x0118, 0x2f00,
+	0x7012, 0x0010, 0x7013, 0x0000, 0x660c, 0x0066, 0x2c00, 0x9f06,
+	0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000, 0x6014, 0x2068,
+	0x080c, 0x95d2, 0x0188, 0x6020, 0x9086, 0x0003, 0x1510, 0x6867,
+	0x0103, 0x6b7a, 0x6877, 0x0000, 0x080c, 0x9843, 0x080c, 0xad5f,
+	0x080c, 0x50a5, 0x080c, 0x9797, 0x080c, 0x97a3, 0x080c, 0x7a3e,
+	0x00ce, 0x0804, 0x69f2, 0x2c78, 0x600c, 0x2060, 0x0804, 0x69f2,
+	0x012e, 0x000e, 0x001e, 0x006e, 0x00ce, 0x00de, 0x00ee, 0x00fe,
+	0x0005, 0x6020, 0x9086, 0x0006, 0x1128, 0x080c, 0xad5f, 0x080c,
+	0xaa84, 0x0c10, 0x6020, 0x9086, 0x0002, 0x1128, 0x6004, 0x9086,
+	0x0085, 0x0968, 0x08c8, 0x6020, 0x9086, 0x0005, 0x19a8, 0x6004,
+	0x9086, 0x0085, 0x0d50, 0x0880, 0x00c6, 0x0006, 0x0126, 0x2091,
+	0x8000, 0x9280, 0x1000, 0x2004, 0x9065, 0x0904, 0x6b15, 0x00f6,
+	0x00e6, 0x00d6, 0x0066, 0x2071, 0x12dc, 0x6654, 0x7018, 0x9c06,
+	0x1108, 0x761a, 0x701c, 0x9c06, 0x1130, 0x86ff, 0x1118, 0x7018,
+	0x701e, 0x0008, 0x761e, 0x6058, 0x907d, 0x0108, 0x7e56, 0x96ed,
+	0x0000, 0x0110, 0x2f00, 0x685a, 0x6057, 0x0000, 0x605b, 0x0000,
+	0x6000, 0xc0d4, 0xc0dc, 0x6002, 0x080c, 0x4a97, 0x0904, 0x6b11,
+	0x7624, 0x86ff, 0x05e8, 0x9680, 0x0005, 0x2004, 0x9d06, 0x15c0,
+	0x00d6, 0x2069, 0x0100, 0x68c0, 0x9005, 0x0548, 0x080c, 0x65cf,
+	0x080c, 0x7721, 0x68c3, 0x0000, 0x080c, 0x7b56, 0x7027, 0x0000,
+	0x0036, 0x2069, 0x0140, 0x6b04, 0x9384, 0x1000, 0x0120, 0x6803,
+	0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084, 0x0110,
+	0x6827, 0x0001, 0x003e, 0x00de, 0x00c6, 0x603c, 0x9005, 0x0110,
+	0x8001, 0x603e, 0x2660, 0x080c, 0x97a3, 0x00ce, 0x0048, 0x00de,
+	0x00c6, 0x2660, 0x6003, 0x0009, 0x630a, 0x00ce, 0x0804, 0x6abc,
+	0x8dff, 0x0158, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000, 0x080c,
+	0x9843, 0x080c, 0xad5f, 0x080c, 0x50a5, 0x080c, 0x7a3e, 0x0804,
+	0x6abc, 0x006e, 0x00de, 0x00ee, 0x00fe, 0x012e, 0x000e, 0x00ce,
+	0x0005, 0x0006, 0x0066, 0x00c6, 0x00d6, 0x2031, 0x0000, 0x7814,
+	0x9065, 0x0904, 0x6b6b, 0x600c, 0x0006, 0x600f, 0x0000, 0x7824,
+	0x9c06, 0x1540, 0x2069, 0x0100, 0x68c0, 0x9005, 0x01f0, 0x080c,
+	0x65cf, 0x080c, 0x7721, 0x68c3, 0x0000, 0x080c, 0x7b56, 0x7827,
+	0x0000, 0x0036, 0x2069, 0x0140, 0x6b04, 0x9384, 0x1000, 0x0120,
+	0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084,
+	0x0110, 0x6827, 0x0001, 0x003e, 0x0028, 0x6003, 0x0009, 0x630a,
+	0x2c30, 0x00b0, 0x6014, 0x2068, 0x080c, 0x95d2, 0x0168, 0x6020,
+	0x9086, 0x0003, 0x11b8, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000,
+	0x080c, 0x50a5, 0x080c, 0x9797, 0x080c, 0x97a3, 0x080c, 0x7a3e,
+	0x000e, 0x0804, 0x6b20, 0x7e16, 0x7e12, 0x00de, 0x00ce, 0x006e,
+	0x000e, 0x0005, 0x6020, 0x9086, 0x0006, 0x1118, 0x080c, 0xaa84,
+	0x0c58, 0x6020, 0x9086, 0x0002, 0x1128, 0x6004, 0x9086, 0x0085,
+	0x09d0, 0x0c10, 0x6020, 0x9086, 0x0005, 0x19f0, 0x6004, 0x9086,
+	0x0085, 0x0d60, 0x08c8, 0x0006, 0x0066, 0x00c6, 0x00d6, 0x7818,
+	0x9065, 0x0904, 0x6bf1, 0x6054, 0x0006, 0x6057, 0x0000, 0x605b,
+	0x0000, 0x6000, 0xc0d4, 0xc0dc, 0x6002, 0x080c, 0x4a97, 0x0904,
+	0x6bee, 0x7e24, 0x86ff, 0x05e8, 0x9680, 0x0005, 0x2004, 0x9d06,
+	0x15c0, 0x00d6, 0x2069, 0x0100, 0x68c0, 0x9005, 0x0548, 0x080c,
+	0x65cf, 0x080c, 0x7721, 0x68c3, 0x0000, 0x080c, 0x7b56, 0x7827,
+	0x0000, 0x0036, 0x2069, 0x0140, 0x6b04, 0x9384, 0x1000, 0x0120,
+	0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084,
+	0x0110, 0x6827, 0x0001, 0x003e, 0x00de, 0x00c6, 0x603c, 0x9005,
+	0x0110, 0x8001, 0x603e, 0x2660, 0x080c, 0x97a3, 0x00ce, 0x0048,
+	0x00de, 0x00c6, 0x2660, 0x6003, 0x0009, 0x630a, 0x00ce, 0x0804,
+	0x6b9d, 0x8dff, 0x0138, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000,
+	0x080c, 0x50a5, 0x080c, 0x7a3e, 0x0804, 0x6b9d, 0x000e, 0x0804,
+	0x6b90, 0x781e, 0x781a, 0x00de, 0x00ce, 0x006e, 0x000e, 0x0005,
+	0x00e6, 0x00d6, 0x0066, 0x6000, 0xd0dc, 0x0188, 0x604c, 0x906d,
+	0x0170, 0x6878, 0x9606, 0x1158, 0x2071, 0x12dc, 0x7024, 0x9035,
+	0x0130, 0x9080, 0x0005, 0x2004, 0x9d06, 0x1108, 0x0021, 0x006e,
+	0x00de, 0x00ee, 0x0005, 0x00f6, 0x2079, 0x0100, 0x78c0, 0x9005,
+	0x1138, 0x00c6, 0x2660, 0x6003, 0x0009, 0x630a, 0x00ce, 0x04a0,
+	0x080c, 0x7721, 0x78c3, 0x0000, 0x080c, 0x7b56, 0x7027, 0x0000,
+	0x0036, 0x2079, 0x0140, 0x7b04, 0x9384, 0x1000, 0x0120, 0x7803,
+	0x0100, 0x7803, 0x0000, 0x2079, 0x0100, 0x7824, 0xd084, 0x0110,
+	0x7827, 0x0001, 0x080c, 0x7b56, 0x003e, 0x080c, 0x4a97, 0x00c6,
+	0x603c, 0x9005, 0x0110, 0x8001, 0x603e, 0x2660, 0x080c, 0x7f1e,
+	0x00ce, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000, 0x080c, 0x9843,
+	0x080c, 0x50a5, 0x080c, 0x7a3e, 0x00fe, 0x0005, 0x00e6, 0x00c6,
+	0x2001, 0x110c, 0x2014, 0xc2e4, 0x2202, 0x2071, 0x12dc, 0x7004,
+	0x9084, 0x0007, 0x0002, 0x6c6d, 0x6c70, 0x6c86, 0x6ca4, 0x6cdd,
+	0x6c6d, 0x6c6b, 0x6c6b, 0x080c, 0x0cf1, 0x00ce, 0x00ee, 0x0005,
+	0x7024, 0x9065, 0x0148, 0x7020, 0x8001, 0x7022, 0x600c, 0x9015,
+	0x0150, 0x7216, 0x600f, 0x0000, 0x7007, 0x0000, 0x7027, 0x0000,
+	0x00ce, 0x00ee, 0x0005, 0x7216, 0x7212, 0x0cb0, 0x6010, 0x2060,
+	0x080c, 0x4a97, 0x6000, 0xc0dc, 0x6002, 0x7007, 0x0000, 0x7027,
+	0x0000, 0x7020, 0x8001, 0x7022, 0x1118, 0x00ce, 0x00ee, 0x0005,
+	0x6054, 0x9015, 0x0120, 0x721e, 0x080c, 0x6d42, 0x0cb0, 0x7218,
+	0x721e, 0x080c, 0x6d42, 0x0c88, 0x7024, 0x9065, 0x0598, 0x700c,
+	0x9c06, 0x1160, 0x080c, 0x7a3e, 0x600c, 0x9015, 0x0120, 0x720e,
+	0x600f, 0x0000, 0x0428, 0x720e, 0x720a, 0x0410, 0x7014, 0x9c06,
+	0x1160, 0x080c, 0x7a3e, 0x600c, 0x9015, 0x0120, 0x7216, 0x600f,
+	0x0000, 0x00b0, 0x7216, 0x7212, 0x0098, 0x6010, 0x2060, 0x080c,
+	0x4a97, 0x6000, 0xc0dc, 0x6002, 0x080c, 0x7a3e, 0x701c, 0x9065,
+	0x0138, 0x6054, 0x9015, 0x0110, 0x721e, 0x0010, 0x7218, 0x721e,
+	0x7027, 0x0000, 0x00ce, 0x00ee, 0x0005, 0x7024, 0x9065, 0x0140,
+	0x080c, 0x7a3e, 0x600c, 0x9015, 0x0150, 0x720e, 0x600f, 0x0000,
+	0x080c, 0x7b56, 0x7027, 0x0000, 0x00ce, 0x00ee, 0x0005, 0x720e,
+	0x720a, 0x0cb0, 0x00d6, 0x2069, 0x12dc, 0x6830, 0x9084, 0x0003,
+	0x0002, 0x6cff, 0x6d01, 0x6d25, 0x6cfd, 0x080c, 0x0cf1, 0x00de,
+	0x0005, 0x00c6, 0x6840, 0x9086, 0x0001, 0x01b8, 0x683c, 0x9065,
+	0x0130, 0x600c, 0x9015, 0x0170, 0x6a3a, 0x600f, 0x0000, 0x6833,
+	0x0000, 0x683f, 0x0000, 0x2011, 0x12fb, 0x2013, 0x0000, 0x00ce,
+	0x00de, 0x0005, 0x683a, 0x6836, 0x0c90, 0x6843, 0x0000, 0x6838,
+	0x9065, 0x0d68, 0x6003, 0x0003, 0x0c50, 0x00c6, 0x6843, 0x0000,
+	0x6847, 0x0000, 0x683c, 0x9065, 0x0168, 0x600c, 0x9015, 0x0130,
+	0x6a3a, 0x600f, 0x0000, 0x683f, 0x0000, 0x0020, 0x683f, 0x0000,
+	0x683a, 0x6836, 0x00ce, 0x00de, 0x0005, 0xc1e5, 0x2001, 0x110c,
+	0x2102, 0x0005, 0x2001, 0x110c, 0x200c, 0xd1ec, 0x0138, 0xc1ec,
+	0x2102, 0x080c, 0x6e10, 0x2001, 0x110c, 0x200c, 0x9184, 0x0600,
+	0x9086, 0x0600, 0x0d50, 0x00d6, 0x2069, 0x12dc, 0x6804, 0x9084,
+	0x0007, 0x0002, 0x6d64, 0x6def, 0x6def, 0x6def, 0x6def, 0x6df1,
+	0x6d62, 0x6d62, 0x080c, 0x0cf1, 0x6820, 0x9005, 0x1110, 0x00de,
+	0x0005, 0x00c6, 0x680c, 0x9065, 0x0150, 0x6807, 0x0004, 0x6826,
+	0x682b, 0x0000, 0x080c, 0x6e53, 0x00ce, 0x00de, 0x0005, 0x6814,
+	0x9065, 0x0150, 0x6807, 0x0001, 0x6826, 0x682b, 0x0000, 0x080c,
+	0x6e53, 0x00ce, 0x00de, 0x0005, 0x00e6, 0x6a1c, 0x92f5, 0x0000,
+	0x0904, 0x6dec, 0x704c, 0x900d, 0x0118, 0x7088, 0x9005, 0x01a0,
+	0x7054, 0x9075, 0x0120, 0x920e, 0x0904, 0x6dec, 0x0028, 0x6818,
+	0x920e, 0x0904, 0x6dec, 0x2070, 0x704c, 0x900d, 0x0d88, 0x7088,
+	0x9005, 0x1d70, 0x2e00, 0x681e, 0x733c, 0x7038, 0x9302, 0x1e40,
+	0x080c, 0x7ef5, 0x0904, 0x6dec, 0x8318, 0x733e, 0x6116, 0x2e10,
+	0x6212, 0x9180, 0x0020, 0x2004, 0x9084, 0x00ff, 0x605e, 0x9180,
+	0x0020, 0x2003, 0x0000, 0x9180, 0x0021, 0x2004, 0x908a, 0x199a,
+	0x0210, 0x2001, 0x1999, 0x8003, 0x801b, 0x831b, 0x9318, 0x631a,
+	0x00f6, 0x2c78, 0x2061, 0x0100, 0x609b, 0x0000, 0x00d6, 0x00e6,
+	0x2069, 0x0200, 0x2071, 0x0240, 0x080c, 0x738a, 0x00ee, 0x00de,
+	0x7300, 0xc3dd, 0x7302, 0x6807, 0x0002, 0x2f18, 0x6b26, 0x682b,
+	0x0000, 0x7823, 0x0003, 0x7803, 0x0001, 0x7807, 0x0040, 0x00fe,
+	0x00ee, 0x00ce, 0x00de, 0x0005, 0x00ee, 0x00ce, 0x0cd8, 0x00de,
+	0x0005, 0x00c6, 0x680c, 0x9065, 0x0138, 0x6807, 0x0004, 0x6826,
+	0x682b, 0x0000, 0x080c, 0x6e53, 0x00ce, 0x00de, 0x0005, 0x2001,
+	0x110c, 0x2014, 0xc2ed, 0x2202, 0x00de, 0x00fe, 0x0005, 0x2001,
+	0x110c, 0x2014, 0xd2e4, 0x0120, 0xc2e4, 0x2202, 0x080c, 0x6d53,
+	0x00f6, 0x00d6, 0x2069, 0x12dc, 0x6830, 0x9086, 0x0000, 0x11e0,
+	0x2001, 0x110c, 0x200c, 0xd1c4, 0x11d0, 0x6838, 0x907d, 0x01a0,
+	0x6a04, 0x9296, 0x0000, 0x19d8, 0x6833, 0x0001, 0x683e, 0x6847,
+	0x0000, 0x0126, 0x00f6, 0x2091, 0x2400, 0x002e, 0x080c, 0x1421,
+	0x1178, 0x012e, 0x080c, 0x75b1, 0x00de, 0x00fe, 0x0005, 0xc1c4,
+	0x2102, 0x0066, 0x2031, 0x0001, 0x080c, 0x57d6, 0x006e, 0x08e8,
+	0x012e, 0x6843, 0x0000, 0x7803, 0x0002, 0x780c, 0x9015, 0x0140,
+	0x6a3a, 0x780f, 0x0000, 0x6833, 0x0000, 0x683f, 0x0000, 0x0c20,
+	0x683a, 0x6836, 0x0cc0, 0x6020, 0x9084, 0x000f, 0x000b, 0x0005,
+	0x6e66, 0x6e6b, 0x7280, 0x733f, 0x6e6b, 0x7280, 0x733f, 0x6e66,
+	0x6e6b, 0x6e66, 0x6e66, 0x6e66, 0x6e66, 0x6e66, 0x080c, 0x6c56,
+	0x080c, 0x6d42, 0x0005, 0x0156, 0x0136, 0x0146, 0x01c6, 0x01d6,
+	0x00c6, 0x00d6, 0x00e6, 0x00f6, 0x2069, 0x0200, 0x2071, 0x0240,
+	0x6004, 0x908a, 0x004c, 0x1a0c, 0x0cf1, 0x6110, 0x2178, 0x79a0,
+	0x2011, 0x1133, 0x2214, 0xd2ac, 0x1110, 0xd1bc, 0x0150, 0x7900,
+	0xd1f4, 0x0120, 0x7914, 0x918c, 0x00ff, 0x0040, 0x2009, 0x0000,
+	0x0028, 0x91f8, 0x26c1, 0x2f0d, 0x918c, 0x00ff, 0x2c78, 0x2061,
+	0x0100, 0x619a, 0x908a, 0x0040, 0x1a04, 0x6eeb, 0x0053, 0x00fe,
+	0x00ee, 0x00de, 0x00ce, 0x01de, 0x01ce, 0x014e, 0x013e, 0x015e,
+	0x0005, 0x6fc3, 0x7004, 0x7033, 0x70d5, 0x70f8, 0x70fe, 0x710c,
+	0x7115, 0x7122, 0x7128, 0x713a, 0x7128, 0x718a, 0x7115, 0x7197,
+	0x719d, 0x7122, 0x719d, 0x71aa, 0x6ee9, 0x6ee9, 0x6ee9, 0x6ee9,
+	0x6ee9, 0x6ee9, 0x6ee9, 0x6ee9, 0x6ee9, 0x6ee9, 0x6ee9, 0x7802,
+	0x7819, 0x7824, 0x7845, 0x7867, 0x710c, 0x6ee9, 0x710c, 0x7128,
+	0x6ee9, 0x7033, 0x70d5, 0x6ee9, 0x7c3b, 0x7128, 0x6ee9, 0x7c57,
+	0x7128, 0x6ee9, 0x7122, 0x6fbc, 0x6f05, 0x6ee9, 0x7c6e, 0x7cdb,
+	0x7db2, 0x6ee9, 0x7dbf, 0x7109, 0x7dd5, 0x6ee9, 0x7872, 0x7e0f,
+	0x6ee9, 0x080c, 0x0cf1, 0x2100, 0x0053, 0x00fe, 0x00ee, 0x00de,
+	0x00ce, 0x01de, 0x01ce, 0x014e, 0x013e, 0x015e, 0x0005, 0x6f03,
+	0x6f03, 0x6f03, 0x6f2b, 0x6f45, 0x6f55, 0x6f03, 0x6f03, 0x6f03,
+	0x6f8e, 0x6f9d, 0x6f03, 0x080c, 0x0cf1, 0x00d6, 0x080c, 0x71be,
+	0x7003, 0x2414, 0x7007, 0x0018, 0x700b, 0x0800, 0x7814, 0x2068,
+	0x683c, 0x700e, 0x6850, 0x7022, 0x6854, 0x7026, 0x60c3, 0x0018,
+	0x080c, 0x76f5, 0x00de, 0x0005, 0x00d6, 0x7810, 0x2068, 0x68a0,
+	0x2069, 0x1100, 0x6acc, 0xd2ac, 0x1110, 0xd0bc, 0x0110, 0x9085,
+	0x0001, 0x00de, 0x0005, 0x00d6, 0x080c, 0x71be, 0x7003, 0x0500,
+	0x7814, 0x90e8, 0x001b, 0x6808, 0x700a, 0x680c, 0x700e, 0x6810,
+	0x7012, 0x6814, 0x7016, 0x6818, 0x701a, 0x681c, 0x701e, 0x60c3,
+	0x0010, 0x080c, 0x76f5, 0x00de, 0x0005, 0x080c, 0x71be, 0x7003,
+	0x7800, 0x7007, 0x0000, 0x7808, 0x8007, 0x700a, 0x700f, 0x0000,
+	0x60c3, 0x0008, 0x080c, 0x76f5, 0x0005, 0x00d6, 0x00e6, 0x080c,
+	0x7234, 0x2073, 0x0200, 0x8e70, 0x2073, 0x0000, 0x8e70, 0x2073,
+	0xdf10, 0x8e70, 0x2073, 0x0034, 0x8e70, 0x2069, 0x1105, 0x20a9,
+	0x0004, 0x2d76, 0x8d68, 0x8e70, 0x1f04, 0x6f69, 0x2069, 0x1101,
+	0x20a9, 0x0004, 0x2d76, 0x8d68, 0x8e70, 0x1f04, 0x6f72, 0x2069,
+	0x12c2, 0x20a9, 0x001a, 0x2d04, 0x8007, 0x2072, 0x8d68, 0x8e70,
+	0x1f04, 0x6f7b, 0x2073, 0x0000, 0x8e70, 0x2073, 0x0000, 0x60c3,
+	0x004c, 0x080c, 0x76f5, 0x00ee, 0x00de, 0x0005, 0x080c, 0x71be,
+	0x7003, 0x6300, 0x7007, 0x0028, 0x700b, 0x0000, 0x7808, 0x700e,
+	0x60c3, 0x0008, 0x080c, 0x76f5, 0x0005, 0x00d6, 0x0026, 0x0016,
+	0x080c, 0x7234, 0x7003, 0x0200, 0x7814, 0x700e, 0x00e6, 0x9ef0,
+	0x0004, 0x2009, 0x0001, 0x2011, 0x000c, 0x2073, 0x0800, 0x8e70,
+	0x2073, 0x0000, 0x00ee, 0x7206, 0x710a, 0x62c2, 0x080c, 0x76f5,
+	0x001e, 0x002e, 0x00de, 0x0005, 0x2001, 0x1114, 0x2004, 0x609a,
+	0x080c, 0x76f5, 0x0005, 0x080c, 0x71be, 0x7003, 0x5200, 0x2069,
+	0x1152, 0x6804, 0xd084, 0x0130, 0x6828, 0x0016, 0x080c, 0x1c7d,
+	0x710e, 0x001e, 0x20a9, 0x0004, 0x20e1, 0x0001, 0x2099, 0x1105,
+	0x20e9, 0x0000, 0x20a1, 0x0250, 0x4003, 0x20a9, 0x0004, 0x2099,
+	0x1101, 0x20a1, 0x0254, 0x4003, 0x2001, 0x1133, 0x2004, 0xd0ac,
+	0x1138, 0x7810, 0x9080, 0x0028, 0x2004, 0x9082, 0x007f, 0x0248,
+	0x2001, 0x111b, 0x2004, 0x7032, 0x2001, 0x111c, 0x2004, 0x7036,
+	0x0030, 0x2001, 0x1114, 0x2004, 0x9084, 0x00ff, 0x7036, 0x60c3,
+	0x001c, 0x080c, 0x76f5, 0x0005, 0x080c, 0x71be, 0x7003, 0x0500,
+	0x2001, 0x1133, 0x2004, 0xd0ac, 0x1138, 0x7810, 0x9080, 0x0028,
+	0x2004, 0x9082, 0x007f, 0x0248, 0x2001, 0x111b, 0x2004, 0x700a,
+	0x2001, 0x111c, 0x2004, 0x700e, 0x0030, 0x2001, 0x1114, 0x2004,
+	0x9084, 0x00ff, 0x700e, 0x20a9, 0x0004, 0x20e1, 0x0001, 0x2099,
+	0x1105, 0x20e9, 0x0000, 0x20a1, 0x0250, 0x4003, 0x60c3, 0x0010,
+	0x080c, 0x76f5, 0x0005, 0x080c, 0x71be, 0x00c6, 0x7810, 0x2060,
+	0x2001, 0x0000, 0x080c, 0x4dea, 0x00ce, 0x7810, 0x9080, 0x0028,
+	0x2004, 0x9086, 0x007e, 0x1130, 0x7003, 0x0400, 0x620c, 0xc2b4,
+	0x620e, 0x0010, 0x7003, 0x0300, 0x7810, 0x9080, 0x0028, 0x2004,
+	0x9086, 0x007e, 0x1904, 0x70a1, 0x00d6, 0x2069, 0x127f, 0x2001,
+	0x1133, 0x2004, 0xd0a4, 0x0178, 0x6800, 0x700a, 0x6808, 0x9084,
+	0x2000, 0x7012, 0x680c, 0x7016, 0x701f, 0x2710, 0x6818, 0x7022,
+	0x681c, 0x7026, 0x0080, 0x6800, 0x700a, 0x6804, 0x700e, 0x6808,
+	0x080c, 0x5745, 0x1118, 0x9084, 0x37ff, 0x0010, 0x9084, 0x3fff,
+	0x7012, 0x680c, 0x7016, 0x00de, 0x20a9, 0x0004, 0x20e1, 0x0001,
+	0x2099, 0x1105, 0x20e9, 0x0000, 0x20a1, 0x0256, 0x4003, 0x20a9,
+	0x0004, 0x2099, 0x1101, 0x20a1, 0x025a, 0x4003, 0x00d6, 0x080c,
+	0x7e86, 0x2069, 0x1287, 0x2071, 0x024e, 0x6800, 0xc0dd, 0x7002,
+	0x2001, 0x1172, 0x2004, 0xd0e4, 0x0110, 0x680c, 0x700e, 0x00de,
+	0x0478, 0x2001, 0x1133, 0x2004, 0xd0a4, 0x0140, 0x2001, 0x1280,
+	0x2004, 0x60e3, 0x0000, 0x080c, 0x1cbe, 0x60e2, 0x20e1, 0x0001,
+	0x2099, 0x127f, 0x20e9, 0x0000, 0x20a1, 0x024e, 0x20a9, 0x0008,
+	0x4003, 0x20a9, 0x0004, 0x2099, 0x1105, 0x20a1, 0x0256, 0x4003,
+	0x20a9, 0x0004, 0x2099, 0x1101, 0x20a1, 0x025a, 0x4003, 0x080c,
+	0x7e86, 0x20a1, 0x024e, 0x20a9, 0x0008, 0x2099, 0x1287, 0x4003,
+	0x60c3, 0x0074, 0x080c, 0x76f5, 0x0005, 0x080c, 0x71be, 0x7003,
+	0x2010, 0x7007, 0x0014, 0x700b, 0x0800, 0x700f, 0x2000, 0x9006,
+	0x00f6, 0x2079, 0x1152, 0x7904, 0x00fe, 0xd1ac, 0x1110, 0x9085,
+	0x0020, 0xd1a4, 0x0110, 0x9085, 0x0010, 0x9085, 0x0002, 0x00d6,
+	0x0804, 0x716e, 0x7026, 0x60c3, 0x0014, 0x080c, 0x76f5, 0x0005,
+	0x080c, 0x71be, 0x7003, 0x5000, 0x0804, 0x704c, 0x080c, 0x71be,
+	0x7003, 0x2110, 0x7007, 0x0014, 0x60c3, 0x0014, 0x080c, 0x76f5,
+	0x0005, 0x080c, 0x722b, 0x0010, 0x080c, 0x7234, 0x7003, 0x0200,
+	0x60c3, 0x0004, 0x080c, 0x76f5, 0x0005, 0x080c, 0x7234, 0x7003,
+	0x0100, 0x700b, 0x0003, 0x700f, 0x2a00, 0x60c3, 0x0008, 0x080c,
+	0x76f5, 0x0005, 0x080c, 0x7234, 0x7003, 0x0200, 0x0804, 0x704c,
+	0x080c, 0x7234, 0x7003, 0x0100, 0x782c, 0x9005, 0x0110, 0x700a,
+	0x0010, 0x700b, 0x0003, 0x7814, 0x700e, 0x60c3, 0x0008, 0x080c,
+	0x76f5, 0x0005, 0x00d6, 0x080c, 0x7234, 0x7003, 0x0210, 0x7007,
+	0x0014, 0x700b, 0x0800, 0x7810, 0x2068, 0x6894, 0x9086, 0x0014,
+	0x1178, 0x6998, 0x9184, 0xc000, 0x1140, 0xd1ec, 0x0118, 0x700f,
+	0x2100, 0x0040, 0x700f, 0x0100, 0x0028, 0x700f, 0x0400, 0x0010,
+	0x700f, 0x0700, 0x00f6, 0x2079, 0x1152, 0x7904, 0x00fe, 0xd1ac,
+	0x1110, 0x9085, 0x0020, 0xd1a4, 0x0110, 0x9085, 0x0010, 0x2009,
+	0x1174, 0x210c, 0xd184, 0x1110, 0x9085, 0x0002, 0x0026, 0x2009,
+	0x1172, 0x210c, 0xd1e4, 0x0130, 0xc0c5, 0x9094, 0x0030, 0x9296,
+	0x0010, 0x0140, 0xd1ec, 0x0130, 0x9094, 0x0030, 0x9296, 0x0010,
+	0x0108, 0xc0bd, 0x002e, 0x7026, 0x60c3, 0x0014, 0x00de, 0x080c,
+	0x76f5, 0x0005, 0x080c, 0x7234, 0x7003, 0x0210, 0x7007, 0x0014,
+	0x700f, 0x0100, 0x60c3, 0x0014, 0x080c, 0x76f5, 0x0005, 0x080c,
+	0x7234, 0x7003, 0x0200, 0x0804, 0x6fc7, 0x080c, 0x7234, 0x7003,
+	0x0100, 0x700b, 0x0003, 0x700f, 0x2a00, 0x60c3, 0x0008, 0x080c,
+	0x76f5, 0x0005, 0x080c, 0x7234, 0x7003, 0x0100, 0x700b, 0x000b,
+	0x60c3, 0x0008, 0x080c, 0x76f5, 0x0005, 0x0026, 0x00d6, 0x0036,
+	0x0046, 0x2019, 0x3200, 0x2021, 0x0800, 0x0040, 0x0026, 0x00d6,
+	0x0036, 0x0046, 0x2019, 0x2200, 0x2021, 0x0100, 0x080c, 0x7e9b,
+	0x7810, 0x2068, 0x6810, 0x9305, 0x7002, 0x6814, 0x7006, 0x6aa0,
+	0x2069, 0x1100, 0x6850, 0x700e, 0x9286, 0x007e, 0x1168, 0x9385,
+	0x00ff, 0x7002, 0x7007, 0xfffe, 0x2001, 0x128f, 0x2004, 0x9005,
+	0x01e8, 0x6a70, 0x720e, 0x00d0, 0x9286, 0x007f, 0x1130, 0x9385,
+	0x00ff, 0x7002, 0x7007, 0xfffd, 0x0068, 0x68cc, 0xd0ac, 0x1110,
+	0xd2bc, 0x0160, 0x9286, 0x0080, 0x1128, 0x9385, 0x00ff, 0x7002,
+	0x7007, 0xfffc, 0x686c, 0x700a, 0x6870, 0x700e, 0x9485, 0x0029,
+	0x7012, 0x004e, 0x003e, 0x00de, 0x080c, 0x76e4, 0x721a, 0x9f95,
+	0x0000, 0x7222, 0x7027, 0xffff, 0x2071, 0x024c, 0x002e, 0x0005,
+	0x0026, 0x080c, 0x7e9b, 0x7003, 0x02ff, 0x7007, 0xfffc, 0x00d6,
+	0x2069, 0x1100, 0x686c, 0x700a, 0x6870, 0x700e, 0x00de, 0x7013,
+	0x2029, 0x0c10, 0x7003, 0x0100, 0x7007, 0x0000, 0x700b, 0xfc02,
+	0x700f, 0x0000, 0x0005, 0x0026, 0x00d6, 0x0036, 0x0046, 0x2019,
+	0x3300, 0x2021, 0x0800, 0x0040, 0x0026, 0x00d6, 0x0036, 0x0046,
+	0x2019, 0x2300, 0x2021, 0x0100, 0x080c, 0x7e9b, 0x7810, 0x2068,
+	0x6810, 0x9305, 0x7002, 0x6814, 0x7006, 0x68a0, 0x2069, 0x1100,
+	0x6a50, 0x720e, 0x6acc, 0xd2ac, 0x1118, 0x9092, 0x007e, 0x02a0,
+	0x7810, 0x00c6, 0x2060, 0x6010, 0x9005, 0x1140, 0x6014, 0x9005,
+	0x1128, 0x700b, 0x00ff, 0x700f, 0xfffe, 0x0020, 0x686c, 0x700a,
+	0x6870, 0x700e, 0x00ce, 0x0000, 0x9485, 0x0098, 0x7012, 0x004e,
+	0x003e, 0x00de, 0x080c, 0x76e4, 0x721a, 0x7a08, 0x7222, 0x2f10,
+	0x7226, 0x2071, 0x024c, 0x002e, 0x0005, 0x080c, 0x76e4, 0x721a,
+	0x7a08, 0x7222, 0x7814, 0x7026, 0x2071, 0x024c, 0x002e, 0x0005,
+	0x00c6, 0x00d6, 0x00e6, 0x00f6, 0x2069, 0x0200, 0x2071, 0x0240,
+	0x6004, 0x908a, 0x0085, 0x0a0c, 0x0cf1, 0x908a, 0x0090, 0x1a0c,
+	0x0cf1, 0x6110, 0x2178, 0x79a0, 0x2011, 0x1133, 0x2214, 0xd2ac,
+	0x1110, 0xd1bc, 0x0150, 0x7900, 0xd1f4, 0x0120, 0x7914, 0x918c,
+	0x00ff, 0x0040, 0x2009, 0x0000, 0x0028, 0x91f8, 0x26c1, 0x2f0d,
+	0x918c, 0x00ff, 0x2c78, 0x2061, 0x0100, 0x619a, 0x9082, 0x0085,
+	0x002b, 0x00fe, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x72c3, 0x72c9,
+	0x72d5, 0x72c1, 0x72c1, 0x72c1, 0x72c3, 0x72c1, 0x72c1, 0x72c1,
+	0x72c1, 0x080c, 0x0cf1, 0x00e1, 0x60c3, 0x0000, 0x080c, 0x76f5,
+	0x0005, 0x04a9, 0x7808, 0x700a, 0x7814, 0x700e, 0x7017, 0xffff,
+	0x60c3, 0x000c, 0x080c, 0x76f5, 0x0005, 0x080c, 0x731f, 0x7003,
+	0x0003, 0x7007, 0x0300, 0x60c3, 0x0004, 0x080c, 0x76f5, 0x0005,
+	0x0026, 0x080c, 0x7e9b, 0x7810, 0x2068, 0x6810, 0x9085, 0x8100,
+	0x7002, 0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc, 0xd2ac,
+	0x1118, 0x9092, 0x007e, 0x0240, 0x686c, 0x700a, 0x6870, 0x700e,
+	0x7013, 0x0009, 0x0804, 0x7204, 0x6a50, 0x720e, 0x0cc8, 0x0026,
+	0x080c, 0x7e9b, 0x7810, 0x2068, 0x6810, 0x9085, 0x8400, 0x7002,
+	0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc, 0xd2ac, 0x1118,
+	0x9092, 0x007e, 0x0248, 0x686c, 0x700a, 0x6870, 0x700e, 0x2001,
+	0x0099, 0x7012, 0x0804, 0x7275, 0x6a50, 0x720e, 0x0cc0, 0x0026,
+	0x080c, 0x7e9b, 0x7810, 0x2068, 0x6810, 0x9085, 0x8500, 0x7002,
+	0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc, 0xd2ac, 0x1118,
+	0x9092, 0x007e, 0x0248, 0x686c, 0x700a, 0x6870, 0x700e, 0x2001,
+	0x0099, 0x7012, 0x0804, 0x7275, 0x6a50, 0x720e, 0x0cc0, 0x00c6,
+	0x00d6, 0x00e6, 0x00f6, 0x2c78, 0x2069, 0x0200, 0x2071, 0x0240,
+	0x7804, 0x908a, 0x0040, 0x0a0c, 0x0cf1, 0x908a, 0x0054, 0x1a0c,
+	0x0cf1, 0x7910, 0x2160, 0x61a0, 0x2011, 0x1133, 0x2214, 0xd2ac,
+	0x1110, 0xd1bc, 0x0150, 0x6100, 0xd1f4, 0x0120, 0x6114, 0x918c,
+	0x00ff, 0x0040, 0x2009, 0x0000, 0x0028, 0x91e0, 0x26c1, 0x2c0d,
+	0x918c, 0x00ff, 0x2061, 0x0100, 0x619a, 0x9082, 0x0040, 0x002b,
+	0x00fe, 0x00ee, 0x00de, 0x00ce, 0x0005, 0x738a, 0x7448, 0x740f,
+	0x7550, 0x7388, 0x7388, 0x7388, 0x7388, 0x7388, 0x7388, 0x7388,
+	0x7a1a, 0x7a22, 0x7a2a, 0x7a32, 0x7388, 0x7de2, 0x7388, 0x7a12,
+	0x080c, 0x0cf1, 0x780b, 0xffff, 0x080c, 0x73dd, 0x7914, 0x2168,
+	0x6978, 0x7956, 0x7132, 0x697c, 0x9184, 0x000f, 0x1118, 0x2001,
+	0x0005, 0x0040, 0xd184, 0x0118, 0x2001, 0x0004, 0x0018, 0x9084,
+	0x0006, 0x8004, 0x2010, 0x785c, 0x9084, 0x00ff, 0x8007, 0x9205,
+	0x7042, 0xd1ac, 0x0128, 0x7047, 0x0002, 0x080c, 0x119d, 0x0050,
+	0xd1b4, 0x0118, 0x7047, 0x0001, 0x0028, 0x7047, 0x0000, 0x9016,
+	0x2230, 0x0010, 0x6ab0, 0x6eac, 0x726a, 0x766e, 0x20a9, 0x0008,
+	0x9d88, 0x0023, 0x20e1, 0x0001, 0x2198, 0x20e9, 0x0000, 0x20a1,
+	0x0252, 0x2069, 0x0200, 0x6813, 0x0018, 0x4003, 0x6813, 0x0008,
+	0x60c3, 0x0020, 0x6017, 0x0009, 0x2001, 0x12f8, 0x2003, 0x07d0,
+	0x2001, 0x12f7, 0x2003, 0x0009, 0x0005, 0x00d6, 0x6813, 0x0008,
+	0x7a10, 0x2268, 0x6a8c, 0x8210, 0x9294, 0x00ff, 0x6a8e, 0x8217,
+	0x721a, 0x6a10, 0x9295, 0x0600, 0x7202, 0x6a14, 0x7206, 0x68a0,
+	0x6900, 0x2069, 0x1100, 0x6bcc, 0xd3ac, 0x1138, 0xd0bc, 0x0188,
+	0xd1f4, 0x0118, 0x9294, 0x00ff, 0x629a, 0x6a6c, 0x720a, 0x6a70,
+	0x720e, 0x7013, 0x0829, 0x2f10, 0x7222, 0x7027, 0xffff, 0x00de,
+	0x0005, 0x9294, 0x00ff, 0x629a, 0x6a50, 0x720e, 0x0c90, 0x00d6,
+	0x0081, 0x7814, 0x2068, 0x6890, 0x7002, 0x688c, 0x7006, 0x68b0,
+	0x700a, 0x68ac, 0x700e, 0x60c3, 0x000c, 0x00de, 0x080c, 0x76f5,
+	0x0005, 0x00d6, 0x6813, 0x0008, 0x7810, 0x2068, 0x6810, 0x9085,
+	0x0500, 0x7002, 0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc,
+	0xd2ac, 0x1110, 0xd0bc, 0x0188, 0x686c, 0x700a, 0x6870, 0x700e,
+	0x7013, 0x0889, 0x080c, 0x76e4, 0x721a, 0x7a08, 0x7222, 0x2f10,
+	0x7226, 0x2071, 0x024c, 0x00de, 0x0005, 0x6a50, 0x720e, 0x0c80,
+	0x00d6, 0x080c, 0x7523, 0x7814, 0x2068, 0x7814, 0x9084, 0xf000,
+	0x1130, 0x7814, 0x9084, 0x0700, 0x8007, 0x002b, 0x0010, 0x9006,
+	0x0013, 0x00de, 0x0005, 0x7465, 0x74bd, 0x74c6, 0x74de, 0x74eb,
+	0x74fd, 0x7505, 0x7463, 0x080c, 0x0cf1, 0x0016, 0x0036, 0x697c,
+	0x918c, 0x0003, 0x0118, 0x9186, 0x0003, 0x11a0, 0x6ba8, 0x7824,
+	0xd0cc, 0x1170, 0x7316, 0x6898, 0x701a, 0x6894, 0x701e, 0x003e,
+	0x001e, 0x2001, 0x12c0, 0x2004, 0x60c2, 0x080c, 0x76f5, 0x0005,
+	0xc3e5, 0x0c80, 0x9186, 0x0001, 0x190c, 0x0cf1, 0x6ba8, 0x7824,
+	0xd0cc, 0x1588, 0x7316, 0x6898, 0x701a, 0x6894, 0x701e, 0x68a4,
+	0x7026, 0x68ac, 0x702e, 0x2009, 0x0018, 0x9384, 0x0300, 0x01e8,
+	0xd3c4, 0x0110, 0x68ac, 0x9108, 0xd3cc, 0x0110, 0x68a4, 0x9108,
+	0x2011, 0x0258, 0x0156, 0x20a9, 0x000d, 0x9d80, 0x002c, 0x201c,
+	0x831f, 0x2312, 0x8000, 0x8210, 0x1f04, 0x74a7, 0x015e, 0x9184,
+	0x0003, 0x0118, 0x2019, 0x0245, 0x201a, 0x61c2, 0x003e, 0x001e,
+	0x080c, 0x76f5, 0x0005, 0xc3e5, 0x0868, 0x2011, 0x0008, 0x7824,
+	0xd0cc, 0x1110, 0x7216, 0x0400, 0x0ce8, 0xc2e5, 0x2011, 0x0302,
+	0x7824, 0xd0cc, 0x0108, 0xc2e5, 0x7216, 0x7027, 0x0012, 0x702f,
+	0x0008, 0x7043, 0x7000, 0x7047, 0x0500, 0x704f, 0x000a, 0x705b,
+	0x2500, 0x60c3, 0x0032, 0x080c, 0x76f5, 0x0005, 0x2011, 0x0028,
+	0x7824, 0xd0cc, 0x1130, 0x7216, 0x60c3, 0x0018, 0x080c, 0x76f5,
+	0x0005, 0x0cc8, 0xc2e5, 0x2011, 0x0100, 0x7824, 0xd0cc, 0x0108,
+	0xc2e5, 0x7216, 0x702f, 0x0008, 0x7858, 0x9084, 0x00ff, 0x7036,
+	0x60c3, 0x0020, 0x080c, 0x76f5, 0x0005, 0x2011, 0x0008, 0x7824,
+	0xd0cc, 0x0108, 0xc2e5, 0x7216, 0x08f8, 0x0036, 0x7b14, 0x9384,
+	0xff00, 0x7816, 0x9384, 0x00ff, 0x8001, 0x1138, 0x7824, 0xd0cc,
+	0x0108, 0xc2e5, 0x7216, 0x003e, 0x0878, 0x0046, 0x2021, 0x0800,
+	0x0006, 0x7824, 0xd0cc, 0x000e, 0x0108, 0xc4e5, 0x7416, 0x004e,
+	0x701e, 0x003e, 0x0808, 0x00d6, 0x6813, 0x0008, 0x7a10, 0x2268,
+	0x6810, 0x9085, 0x0700, 0x7002, 0x6814, 0x7006, 0x68a0, 0x2069,
+	0x1100, 0x6acc, 0xd2ac, 0x1110, 0xd0bc, 0x01a0, 0x686c, 0x700a,
+	0x6870, 0x700e, 0x7824, 0xd0cc, 0x1180, 0x7013, 0x0898, 0x080c,
+	0x76e4, 0x721a, 0x7a08, 0x7222, 0x2f10, 0x7226, 0x2071, 0x024c,
+	0x00de, 0x0005, 0x6a50, 0x720e, 0x0c68, 0x7013, 0x0889, 0x0c78,
+	0x0016, 0x7814, 0x9084, 0x0700, 0x8007, 0x0013, 0x001e, 0x0005,
+	0x7560, 0x7560, 0x7562, 0x7560, 0x7560, 0x7560, 0x757f, 0x7560,
+	0x080c, 0x0cf1, 0x7914, 0x918c, 0xf8ff, 0x918d, 0x0600, 0x7916,
+	0x2009, 0x0003, 0x00d1, 0x00d6, 0x2069, 0x1152, 0x6804, 0xd0bc,
+	0x0130, 0x682c, 0x9084, 0x00ff, 0x8007, 0x7032, 0x0010, 0x7033,
+	0x3f00, 0x00de, 0x60c3, 0x0001, 0x080c, 0x76f5, 0x0005, 0x2009,
+	0x0003, 0x0019, 0x7033, 0x7f00, 0x0ca8, 0x00d6, 0x0016, 0x080c,
+	0x7e9b, 0x001e, 0x7810, 0x2068, 0x6810, 0x9085, 0x0100, 0x7002,
+	0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc, 0xd2ac, 0x1110,
+	0xd0bc, 0x01a0, 0x6a6c, 0x720a, 0x6a70, 0x720e, 0x7013, 0x0888,
+	0x918d, 0x0008, 0x7116, 0x080c, 0x76e4, 0x721a, 0x7a08, 0x7222,
+	0x2f10, 0x7226, 0x2071, 0x024c, 0x00de, 0x0005, 0x6a50, 0x720e,
+	0x0c68, 0x00e6, 0x00d6, 0x00c6, 0x0056, 0x0046, 0x0036, 0x2061,
+	0x0100, 0x2071, 0x1100, 0x7150, 0x7810, 0x2068, 0x68a0, 0x2028,
+	0x6910, 0x6a14, 0x76cc, 0xd6ac, 0x1130, 0xd0bc, 0x1120, 0x2019,
+	0x0000, 0x7450, 0x0010, 0x736c, 0x7470, 0x7820, 0x90be, 0x0006,
+	0x0904, 0x765a, 0x90be, 0x000a, 0x15e8, 0x9185, 0x0200, 0x6062,
+	0x6266, 0x636a, 0x646e, 0x6073, 0x2029, 0x6077, 0x0000, 0x688c,
+	0x8000, 0x9084, 0x00ff, 0x688e, 0x8007, 0x607a, 0x607f, 0x0000,
+	0x2f00, 0x6082, 0x7808, 0x6086, 0x7814, 0x2070, 0x7038, 0x608a,
+	0x7034, 0x608e, 0x7048, 0x60c6, 0x7044, 0x60ca, 0x686c, 0x60ce,
+	0x60af, 0x95d5, 0x60d7, 0x0000, 0x609f, 0x0000, 0x080c, 0x7e80,
+	0x2009, 0x07d0, 0x60c4, 0x9084, 0xfff0, 0x9005, 0x0110, 0x2009,
+	0x1b58, 0x080c, 0x65d4, 0x003e, 0x004e, 0x005e, 0x00ce, 0x00de,
+	0x00ee, 0x0005, 0x9185, 0x0100, 0x6062, 0x6266, 0x636a, 0x646e,
+	0x6073, 0x0809, 0x6077, 0x0008, 0x688c, 0x8000, 0x9084, 0x00ff,
+	0x688e, 0x8007, 0x607a, 0x607f, 0x0000, 0x2f00, 0x6082, 0x7808,
+	0x6086, 0x7814, 0x2070, 0x7038, 0x608a, 0x7034, 0x608e, 0x7048,
+	0x60c6, 0x7044, 0x60ca, 0x686c, 0x60ce, 0x60af, 0x95d5, 0x60d7,
+	0x0000, 0x9582, 0x0080, 0x0248, 0x6a00, 0xd2f4, 0x0120, 0x6a14,
+	0x9294, 0x00ff, 0x0010, 0x2011, 0x0000, 0x629e, 0x080c, 0x7e80,
+	0x2009, 0x07d0, 0x60c4, 0x9084, 0xfff0, 0x9005, 0x0110, 0x2009,
+	0x1b58, 0x080c, 0x65d4, 0x003e, 0x004e, 0x005e, 0x00ce, 0x00de,
+	0x00ee, 0x0005, 0x7814, 0x2070, 0x707c, 0x9084, 0x0003, 0x9086,
+	0x0002, 0x05f0, 0x9185, 0x0100, 0x6062, 0x6266, 0x636a, 0x646e,
+	0x6073, 0x0880, 0x6077, 0x0008, 0x688c, 0x8000, 0x9084, 0x00ff,
+	0x688e, 0x8007, 0x607a, 0x7838, 0x607e, 0x2f00, 0x6086, 0x7808,
+	0x6082, 0x7090, 0x608a, 0x708c, 0x608e, 0x70b0, 0x60c6, 0x70ac,
+	0x60ca, 0x70ac, 0x7930, 0x9108, 0x7932, 0x70b0, 0x792c, 0x9109,
+	0x792e, 0x686c, 0x60ce, 0x60af, 0x95d5, 0x60d7, 0x0000, 0x9582,
+	0x0080, 0x0248, 0x6a00, 0xd2f4, 0x0120, 0x6a14, 0x9294, 0x00ff,
+	0x0010, 0x2011, 0x0000, 0x629e, 0x080c, 0x7e5b, 0x0804, 0x7648,
+	0x9185, 0x0700, 0x6062, 0x6266, 0x636a, 0x646e, 0x7824, 0xd0cc,
+	0x7826, 0x0118, 0x6073, 0x0889, 0x0010, 0x6073, 0x0898, 0x6077,
+	0x0000, 0x688c, 0x8000, 0x9084, 0x00ff, 0x688e, 0x8007, 0x607a,
+	0x607f, 0x0000, 0x2f00, 0x6086, 0x7808, 0x6082, 0x7038, 0x608a,
+	0x7034, 0x608e, 0x7048, 0x60c6, 0x7044, 0x60ca, 0x686c, 0x60ce,
+	0x60af, 0x95d5, 0x60d7, 0x0000, 0x9582, 0x0080, 0x0248, 0x6a00,
+	0xd2f4, 0x0120, 0x6a14, 0x9294, 0x00ff, 0x0010, 0x2011, 0x0000,
+	0x629e, 0x7824, 0xd0cc, 0x0120, 0x080c, 0x7e80, 0x0804, 0x7648,
+	0x080c, 0x7e5b, 0x0804, 0x7648, 0x7a10, 0x9280, 0x0023, 0x2014,
+	0x8210, 0x9294, 0x00ff, 0x2202, 0x8217, 0x0005, 0x00d6, 0x2069,
+	0x12dc, 0x6843, 0x0001, 0x00de, 0x0005, 0x60a3, 0x0056, 0x60a7,
+	0x9575, 0x00f1, 0x080c, 0x65c6, 0x0005, 0x0016, 0x2001, 0x110c,
+	0x200c, 0x9184, 0x0600, 0x9086, 0x0600, 0x0128, 0x0089, 0x080c,
+	0x65c6, 0x001e, 0x0005, 0xc1e5, 0x2001, 0x110c, 0x2102, 0x2001,
+	0x12dd, 0x2003, 0x0000, 0x2001, 0x12e5, 0x2003, 0x0000, 0x0c88,
+	0x0006, 0x6014, 0x9084, 0x1804, 0x9085, 0x0009, 0x6016, 0x000e,
+	0x0005, 0x0006, 0x00c6, 0x2061, 0x0100, 0x6014, 0x9084, 0x1804,
+	0x9085, 0x0008, 0x6016, 0x00ce, 0x000e, 0x0005, 0x00c6, 0x00d6,
+	0x0016, 0x0026, 0x2061, 0x0100, 0x2069, 0x0140, 0x080c, 0x5745,
+	0x1198, 0x2001, 0x12f8, 0x2004, 0x9005, 0x15b8, 0x0066, 0x2031,
+	0x0001, 0x080c, 0x57d6, 0x006e, 0x1118, 0x080c, 0x65c6, 0x0468,
+	0x00c6, 0x2061, 0x12dc, 0x00d8, 0x6904, 0x9194, 0x4000, 0x0550,
+	0x0881, 0x6803, 0x1000, 0x6803, 0x0000, 0x00c6, 0x2061, 0x12dc,
+	0x6128, 0x9192, 0x00c8, 0x1258, 0x8108, 0x612a, 0x6124, 0x00ce,
+	0x81ff, 0x0198, 0x080c, 0x65c6, 0x080c, 0x7718, 0x0070, 0x6124,
+	0x91e5, 0x0000, 0x0140, 0x080c, 0xae07, 0x2009, 0x0014, 0x080c,
+	0x7f4e, 0x080c, 0x65cf, 0x00ce, 0x0000, 0x002e, 0x001e, 0x00de,
+	0x00ce, 0x0005, 0x2001, 0x12f8, 0x2004, 0x9005, 0x1db0, 0x00c6,
+	0x2061, 0x12dc, 0x6128, 0x9192, 0x0003, 0x1e08, 0x8108, 0x612a,
+	0x00ce, 0x080c, 0x65c6, 0x080c, 0x45d6, 0x0c38, 0x00c6, 0x00d6,
+	0x00e6, 0x0016, 0x0026, 0x080c, 0x65dc, 0x2071, 0x12dc, 0x713c,
+	0x81ff, 0x0590, 0x2061, 0x0100, 0x2069, 0x0140, 0x080c, 0x5745,
+	0x11a8, 0x0036, 0x2019, 0x0002, 0x080c, 0x7936, 0x003e, 0x713c,
+	0x2160, 0x080c, 0xae07, 0x2009, 0x004a, 0x080c, 0x7f4e, 0x0066,
+	0x2031, 0x0001, 0x080c, 0x57d6, 0x006e, 0x00b0, 0x6904, 0x9194,
+	0x4000, 0x01c0, 0x6803, 0x1000, 0x6803, 0x0000, 0x0036, 0x2019,
+	0x0001, 0x080c, 0x7936, 0x003e, 0x713c, 0x2160, 0x080c, 0xae07,
+	0x2009, 0x004a, 0x080c, 0x7f4e, 0x002e, 0x001e, 0x00ee, 0x00de,
+	0x00ce, 0x0005, 0x0c58, 0x00e6, 0x00d6, 0x00c6, 0x0066, 0x0056,
+	0x0046, 0x0006, 0x0126, 0x2091, 0x8000, 0x6010, 0x2068, 0x6ca0,
+	0x2071, 0x12dc, 0x7018, 0x2068, 0x8dff, 0x0198, 0x68a0, 0x9406,
+	0x0118, 0x6854, 0x2068, 0x0cc0, 0x6014, 0x2060, 0x646c, 0x6570,
+	0x6678, 0x2d60, 0x080c, 0x4c75, 0x0120, 0x080c, 0x7a3e, 0x9085,
+	0x0001, 0x012e, 0x000e, 0x004e, 0x005e, 0x006e, 0x00ce, 0x00de,
+	0x00ee, 0x0005, 0x080c, 0x71be, 0x7003, 0x1200, 0x7820, 0x9086,
+	0x0004, 0x1110, 0x6098, 0x0018, 0x2001, 0x1114, 0x2004, 0x700e,
+	0x7838, 0x7012, 0x783c, 0x7016, 0x60c3, 0x002c, 0x080c, 0x76f5,
+	0x0005, 0x080c, 0x71be, 0x7003, 0x0f00, 0x7808, 0x700e, 0x60c3,
+	0x0008, 0x080c, 0x76f5, 0x0005, 0x0156, 0x080c, 0x7234, 0x7003,
+	0x0200, 0x2011, 0x1148, 0x63f0, 0x2312, 0x20a9, 0x0006, 0x2011,
+	0x1140, 0x2019, 0x1141, 0x9ef0, 0x0002, 0x2376, 0x8e70, 0x2276,
+	0x8e70, 0x9398, 0x0002, 0x9290, 0x0002, 0x1f04, 0x7835, 0x60c3,
+	0x001c, 0x080c, 0x76f5, 0x015e, 0x0005, 0x0016, 0x0026, 0x080c,
+	0x7210, 0x080c, 0x7222, 0x9e80, 0x0004, 0x20e9, 0x0000, 0x20a0,
+	0x7814, 0x9080, 0x0000, 0x2004, 0x9080, 0x0021, 0x20e1, 0x0001,
+	0x2098, 0x7808, 0x9088, 0x0002, 0x21a8, 0x4003, 0x9080, 0x0004,
+	0x8003, 0x60c2, 0x080c, 0x76f5, 0x002e, 0x001e, 0x0005, 0x080c,
+	0x71be, 0x7003, 0x6200, 0x7808, 0x700e, 0x60c3, 0x0008, 0x080c,
+	0x76f5, 0x0005, 0x0016, 0x0026, 0x080c, 0x71be, 0x20e9, 0x0000,
+	0x20a1, 0x024c, 0x7814, 0x9080, 0x0000, 0x2004, 0x9080, 0x0023,
+	0x20e1, 0x0001, 0x2098, 0x7808, 0x9088, 0x0002, 0x21a8, 0x4003,
+	0x8003, 0x60c2, 0x080c, 0x76f5, 0x002e, 0x001e, 0x0005, 0x00e6,
+	0x00c6, 0x0006, 0x0126, 0x2091, 0x8000, 0x2071, 0x12dc, 0x700c,
+	0x2060, 0x8cff, 0x0178, 0x080c, 0x97cd, 0x1110, 0x080c, 0x8576,
+	0x600c, 0x0006, 0x080c, 0x99c4, 0x080c, 0x7f1e, 0x080c, 0x7a3e,
+	0x00ce, 0x0c78, 0x700f, 0x0000, 0x700b, 0x0000, 0x012e, 0x000e,
+	0x00ce, 0x00ee, 0x0005, 0x0126, 0x0156, 0x00f6, 0x00e6, 0x00d6,
+	0x00c6, 0x0026, 0x0016, 0x0006, 0x2091, 0x8000, 0x2069, 0x0100,
+	0x2079, 0x0140, 0x2071, 0x12dc, 0x7024, 0x2060, 0x8cff, 0x05a0,
+	0x080c, 0x7721, 0x68c3, 0x0000, 0x080c, 0x65cf, 0x2009, 0x0013,
+	0x080c, 0x7f4e, 0x20a9, 0x01f4, 0x6824, 0xd094, 0x0158, 0x6827,
+	0x0004, 0x7804, 0x9084, 0x4000, 0x01a0, 0x7803, 0x1000, 0x7803,
+	0x0000, 0x0078, 0xd084, 0x0118, 0x6827, 0x0001, 0x0010, 0x1f04,
+	0x78d4, 0x7804, 0x9084, 0x1000, 0x0120, 0x7803, 0x0100, 0x7803,
+	0x0000, 0x6824, 0x000e, 0x001e, 0x002e, 0x00ce, 0x00de, 0x00ee,
+	0x00fe, 0x015e, 0x012e, 0x0005, 0x2001, 0x1100, 0x2004, 0x9096,
+	0x0001, 0x0550, 0x9096, 0x0004, 0x0538, 0x6817, 0x0008, 0x68c3,
+	0x0000, 0x2011, 0x4586, 0x080c, 0x655b, 0x20a9, 0x01f4, 0x6824,
+	0xd094, 0x0158, 0x6827, 0x0004, 0x7804, 0x9084, 0x4000, 0x01a0,
+	0x7803, 0x1000, 0x7803, 0x0000, 0x0078, 0xd084, 0x0118, 0x6827,
+	0x0001, 0x0010, 0x1f04, 0x790f, 0x7804, 0x9084, 0x1000, 0x0120,
+	0x7803, 0x0100, 0x7803, 0x0000, 0x000e, 0x001e, 0x002e, 0x00ce,
+	0x00de, 0x00ee, 0x00fe, 0x015e, 0x012e, 0x0005, 0x0126, 0x0156,
+	0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0026, 0x0016, 0x0006, 0x2091,
+	0x8000, 0x2069, 0x0100, 0x2079, 0x0140, 0x2071, 0x12dc, 0x703c,
+	0x2060, 0x8cff, 0x0904, 0x79b8, 0x6814, 0x9084, 0x0002, 0x0904,
+	0x79b8, 0x68af, 0x95f5, 0x6817, 0x0010, 0x2009, 0x00fa, 0x8109,
+	0x1df0, 0x68c7, 0x0000, 0x68cb, 0x0008, 0x080c, 0x65dc, 0x080c,
+	0x1605, 0x0046, 0x2009, 0x017f, 0x200b, 0x00a5, 0x2021, 0x0169,
+	0x2404, 0x9084, 0x000f, 0x9086, 0x0004, 0x1500, 0x68af, 0x95f5,
+	0x68c7, 0x0000, 0x68cb, 0x0008, 0x00e6, 0x00f6, 0x2079, 0x0090,
+	0x2071, 0x131f, 0x6814, 0x9084, 0x1984, 0x9085, 0x0012, 0x6816,
+	0x782b, 0x0008, 0x7003, 0x0000, 0x00fe, 0x00ee, 0x9386, 0x0002,
+	0x1128, 0x7884, 0x9005, 0x1110, 0x7887, 0x0001, 0x200b, 0x0000,
+	0x004e, 0x939d, 0x0000, 0x1120, 0x2009, 0x0049, 0x080c, 0x7f4e,
+	0x20a9, 0x03e8, 0x6824, 0xd094, 0x0158, 0x6827, 0x0004, 0x7804,
+	0x9084, 0x4000, 0x01a0, 0x7803, 0x1000, 0x7803, 0x0000, 0x0078,
+	0xd08c, 0x0118, 0x6827, 0x0002, 0x0010, 0x1f04, 0x799a, 0x7804,
+	0x9084, 0x1000, 0x0120, 0x7803, 0x0100, 0x7803, 0x0000, 0x6824,
+	0x000e, 0x001e, 0x002e, 0x00ce, 0x00de, 0x00ee, 0x00fe, 0x015e,
+	0x012e, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x2069, 0x12dc,
+	0x6a06, 0x012e, 0x00de, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000,
+	0x2069, 0x12dc, 0x6a32, 0x012e, 0x00de, 0x0005, 0x00f6, 0x00e6,
+	0x00c6, 0x0066, 0x0006, 0x0126, 0x2071, 0x12dc, 0x7614, 0x2660,
+	0x2678, 0x2091, 0x8000, 0x8cff, 0x0530, 0x6020, 0x9206, 0x11f8,
+	0x7014, 0x9c36, 0x1110, 0x660c, 0x7616, 0x7010, 0x9c36, 0x1140,
+	0x2c00, 0x9f36, 0x0118, 0x2f00, 0x7012, 0x0010, 0x7013, 0x0000,
+	0x660c, 0x0066, 0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008, 0x2678,
+	0x600f, 0x0000, 0x080c, 0x97a3, 0x04c9, 0x00ce, 0x08e0, 0x2c78,
+	0x600c, 0x2060, 0x08c0, 0x012e, 0x000e, 0x006e, 0x00ce, 0x00ee,
+	0x00fe, 0x0005, 0x080c, 0x73dd, 0x7814, 0x7032, 0x7042, 0x7047,
+	0x1000, 0x00f8, 0x080c, 0x73dd, 0x7814, 0x7032, 0x7042, 0x7047,
+	0x4000, 0x00b8, 0x080c, 0x73dd, 0x7814, 0x7032, 0x7042, 0x7047,
+	0x2000, 0x0078, 0x080c, 0x73dd, 0x7814, 0x7032, 0x7042, 0x7047,
+	0x0400, 0x0038, 0x080c, 0x73dd, 0x7814, 0x7032, 0x7042, 0x7047,
+	0x0200, 0x60c3, 0x0020, 0x080c, 0x76f5, 0x0005, 0x00e6, 0x2071,
+	0x12dc, 0x7020, 0x9005, 0x0110, 0x8001, 0x7022, 0x00ee, 0x0005,
+	0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0076, 0x0066, 0x0006, 0x0126,
+	0x2091, 0x8000, 0x2071, 0x12dc, 0x7614, 0x2660, 0x2678, 0x2039,
+	0x0001, 0x87ff, 0x0904, 0x7ad2, 0x8cff, 0x0904, 0x7ad2, 0x6020,
+	0x9086, 0x0006, 0x1904, 0x7acd, 0x88ff, 0x0138, 0x2800, 0x9c06,
+	0x1904, 0x7acd, 0x2039, 0x0000, 0x0050, 0x6010, 0x9206, 0x1904,
+	0x7acd, 0x85ff, 0x0120, 0x6054, 0x9106, 0x1904, 0x7acd, 0x7024,
+	0x9c06, 0x1538, 0x2069, 0x0100, 0x68c0, 0x9005, 0x01f0, 0x080c,
+	0x65cf, 0x6817, 0x0008, 0x68c3, 0x0000, 0x080c, 0x7b56, 0x7027,
+	0x0000, 0x0036, 0x2069, 0x0140, 0x6b04, 0x9384, 0x1000, 0x0120,
+	0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100, 0x6824, 0xd084,
+	0x0110, 0x6827, 0x0001, 0x003e, 0x0020, 0x6003, 0x0009, 0x630a,
+	0x0460, 0x7014, 0x9c36, 0x1110, 0x660c, 0x7616, 0x7010, 0x9c36,
+	0x1140, 0x2c00, 0x9f36, 0x0118, 0x2f00, 0x7012, 0x0010, 0x7013,
+	0x0000, 0x660c, 0x0066, 0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008,
+	0x2678, 0x89ff, 0x1158, 0x600f, 0x0000, 0x6014, 0x2068, 0x080c,
+	0x95d2, 0x0110, 0x080c, 0xaa84, 0x080c, 0x97a3, 0x080c, 0x7a3e,
+	0x88ff, 0x1190, 0x00ce, 0x0804, 0x7a59, 0x2c78, 0x600c, 0x2060,
+	0x0804, 0x7a59, 0x9006, 0x012e, 0x000e, 0x006e, 0x007e, 0x00ce,
+	0x00de, 0x00ee, 0x00fe, 0x0005, 0x601b, 0x0000, 0x00ce, 0x98c5,
+	0x0001, 0x0c88, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0066, 0x0026,
+	0x0006, 0x0126, 0x2091, 0x8000, 0x2071, 0x12dc, 0x7638, 0x2660,
+	0x2678, 0x8cff, 0x0904, 0x7b46, 0x6020, 0x9086, 0x0006, 0x1904,
+	0x7b41, 0x87ff, 0x0128, 0x2700, 0x9c06, 0x1904, 0x7b41, 0x0040,
+	0x6010, 0x9206, 0x15f0, 0x85ff, 0x0118, 0x6054, 0x9106, 0x15c8,
+	0x703c, 0x9c06, 0x1170, 0x0036, 0x2019, 0x0001, 0x080c, 0x7936,
+	0x7033, 0x0000, 0x703f, 0x0000, 0x7043, 0x0000, 0x7047, 0x0000,
+	0x003e, 0x7038, 0x9c36, 0x1110, 0x660c, 0x763a, 0x7034, 0x9c36,
+	0x1140, 0x2c00, 0x9f36, 0x0118, 0x2f00, 0x7036, 0x0010, 0x7037,
+	0x0000, 0x660c, 0x0066, 0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008,
+	0x2678, 0x600f, 0x0000, 0x6014, 0x2068, 0x080c, 0x95d2, 0x0110,
+	0x080c, 0xaa84, 0x080c, 0x97a3, 0x87ff, 0x1190, 0x00ce, 0x0804,
+	0x7af1, 0x2c78, 0x600c, 0x2060, 0x0804, 0x7af1, 0x9006, 0x012e,
+	0x000e, 0x002e, 0x006e, 0x00ce, 0x00de, 0x00ee, 0x00fe, 0x0005,
+	0x601b, 0x0000, 0x00ce, 0x97bd, 0x0001, 0x0c88, 0x00e6, 0x2071,
+	0x12dc, 0x2001, 0x1100, 0x2004, 0x9086, 0x0002, 0x1118, 0x7007,
+	0x0005, 0x0010, 0x7007, 0x0000, 0x00ee, 0x0005, 0x00f6, 0x00e6,
+	0x00c6, 0x0066, 0x0026, 0x0006, 0x0126, 0x2091, 0x8000, 0x2071,
+	0x12dc, 0x2c10, 0x7638, 0x2660, 0x2678, 0x8cff, 0x0518, 0x2200,
+	0x9c06, 0x11e0, 0x7038, 0x9c36, 0x1110, 0x660c, 0x763a, 0x7034,
+	0x9c36, 0x1140, 0x2c00, 0x9f36, 0x0118, 0x2f00, 0x7036, 0x0010,
+	0x7037, 0x0000, 0x660c, 0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008,
+	0x2678, 0x600f, 0x0000, 0x9085, 0x0001, 0x0020, 0x2c78, 0x600c,
+	0x2060, 0x08d8, 0x012e, 0x000e, 0x002e, 0x006e, 0x00ce, 0x00ee,
+	0x00fe, 0x0005, 0x00f6, 0x00e6, 0x00d6, 0x00c6, 0x0066, 0x0006,
+	0x0126, 0x2091, 0x8000, 0x2071, 0x12dc, 0x760c, 0x2660, 0x2678,
+	0x8cff, 0x0904, 0x7c2c, 0x6010, 0x9080, 0x0028, 0x2004, 0x9206,
+	0x1904, 0x7c27, 0x7024, 0x9c06, 0x1508, 0x2069, 0x0100, 0x68c0,
+	0x9005, 0x0904, 0x7c03, 0x080c, 0x7721, 0x68c3, 0x0000, 0x080c,
+	0x7b56, 0x7027, 0x0000, 0x0036, 0x2069, 0x0140, 0x6b04, 0x9384,
+	0x1000, 0x0120, 0x6803, 0x0100, 0x6803, 0x0000, 0x2069, 0x0100,
+	0x6824, 0xd084, 0x0110, 0x6827, 0x0001, 0x003e, 0x700c, 0x9c36,
+	0x1110, 0x660c, 0x760e, 0x7008, 0x9c36, 0x1140, 0x2c00, 0x9f36,
+	0x0118, 0x2f00, 0x700a, 0x0010, 0x700b, 0x0000, 0x660c, 0x0066,
+	0x2c00, 0x9f06, 0x0110, 0x7e0e, 0x0008, 0x2678, 0x600f, 0x0000,
+	0x080c, 0x97bc, 0x1158, 0x080c, 0x25d1, 0x080c, 0x97cd, 0x11f0,
+	0x080c, 0x8576, 0x00d8, 0x080c, 0x7b56, 0x08c0, 0x080c, 0x97cd,
+	0x1118, 0x080c, 0x8576, 0x0090, 0x6014, 0x2068, 0x080c, 0x95d2,
+	0x0168, 0x6020, 0x9086, 0x0003, 0x11f8, 0x6867, 0x0103, 0x6b7a,
+	0x6877, 0x0000, 0x080c, 0x50a5, 0x080c, 0x9797, 0x080c, 0x99c4,
+	0x080c, 0x97a3, 0x080c, 0x7a3e, 0x00ce, 0x0804, 0x7bb0, 0x2c78,
+	0x600c, 0x2060, 0x0804, 0x7bb0, 0x012e, 0x000e, 0x006e, 0x00ce,
+	0x00de, 0x00ee, 0x00fe, 0x0005, 0x6020, 0x9086, 0x0006, 0x1d30,
+	0x080c, 0xaa84, 0x0c18, 0x00d6, 0x080c, 0x7234, 0x7003, 0x0200,
+	0x7007, 0x0014, 0x60c3, 0x0014, 0x20e1, 0x0001, 0x2099, 0x12a9,
+	0x20e9, 0x0000, 0x20a1, 0x0250, 0x20a9, 0x0004, 0x4003, 0x7023,
+	0x0004, 0x7027, 0x7878, 0x080c, 0x76f5, 0x00de, 0x0005, 0x080c,
+	0x7234, 0x7003, 0x0214, 0x7007, 0x0018, 0x700b, 0x0800, 0x7814,
+	0x9084, 0xff00, 0x700e, 0x7814, 0x9084, 0x00ff, 0x7022, 0x782c,
+	0x7026, 0x60c3, 0x0018, 0x080c, 0x76f5, 0x0005, 0x00d6, 0x0016,
+	0x00d6, 0x2f68, 0x2009, 0x0035, 0x080c, 0x9ac5, 0x00de, 0x1904,
+	0x7cd4, 0x080c, 0x71be, 0x7003, 0x1300, 0x782c, 0x2068, 0x6820,
+	0x9086, 0x0003, 0x0570, 0x7810, 0x9080, 0x0028, 0x2014, 0x2001,
+	0x1133, 0x2004, 0xd0ac, 0x11d0, 0x9286, 0x007e, 0x1128, 0x700b,
+	0x00ff, 0x700f, 0xfffe, 0x04a8, 0x9286, 0x007f, 0x1128, 0x700b,
+	0x00ff, 0x700f, 0xfffd, 0x0468, 0xd2bc, 0x0180, 0x9286, 0x0080,
+	0x1128, 0x700b, 0x00ff, 0x700f, 0xfffc, 0x0418, 0x92e8, 0x1000,
+	0x2d6c, 0x6810, 0x700a, 0x6814, 0x700e, 0x00d8, 0x6098, 0x700e,
+	0x00c0, 0x2001, 0x1133, 0x2004, 0xd0ac, 0x1138, 0x7810, 0x9080,
+	0x0028, 0x2004, 0x9082, 0x007e, 0x0250, 0x00d6, 0x2069, 0x111b,
+	0x2d04, 0x700a, 0x8d68, 0x2d04, 0x700e, 0x00de, 0x0010, 0x6034,
+	0x700e, 0x7838, 0x7012, 0x783c, 0x7016, 0x60c3, 0x000c, 0x001e,
+	0x00de, 0x080c, 0x76f5, 0x0005, 0x781b, 0x0001, 0x7803, 0x0006,
+	0x001e, 0x00de, 0x0005, 0x792c, 0x9180, 0x0008, 0x200c, 0x9186,
+	0x0006, 0x01b0, 0x9186, 0x0003, 0x0904, 0x7d4b, 0x9186, 0x0005,
+	0x0904, 0x7d34, 0x9186, 0x0004, 0x05c8, 0x9186, 0x0008, 0x0904,
+	0x7d3c, 0x7807, 0x0037, 0x7817, 0x1700, 0x080c, 0x7db2, 0x0005,
+	0x080c, 0x7d71, 0x00d6, 0x0026, 0x792c, 0x2168, 0x2009, 0x4000,
+	0x6800, 0x0002, 0x7d15, 0x7d20, 0x7d17, 0x7d20, 0x7d1c, 0x7d15,
+	0x7d15, 0x7d20, 0x7d20, 0x7d20, 0x7d20, 0x7d15, 0x7d15, 0x7d15,
+	0x7d15, 0x7d15, 0x7d20, 0x7d15, 0x7d20, 0x080c, 0x0cf1, 0x6824,
+	0xd0e4, 0x0110, 0xd0cc, 0x0110, 0x900e, 0x0010, 0x2009, 0x2000,
+	0x682c, 0x7022, 0x6830, 0x7026, 0x0804, 0x7d69, 0x080c, 0x7d71,
+	0x00d6, 0x0026, 0x792c, 0x2168, 0x2009, 0x4000, 0x6a00, 0x9286,
+	0x0002, 0x1108, 0x900e, 0x04a8, 0x04e1, 0x00d6, 0x0026, 0x792c,
+	0x2168, 0x2009, 0x4000, 0x0468, 0x04a1, 0x00d6, 0x0026, 0x792c,
+	0x2168, 0x2009, 0x4000, 0x9286, 0x0005, 0x0118, 0x9286, 0x0002,
+	0x1108, 0x900e, 0x00f0, 0x0429, 0x00d6, 0x0026, 0x792c, 0x2168,
+	0x6814, 0x2068, 0x69ac, 0x6834, 0x9112, 0x69b0, 0x6838, 0x9103,
+	0x7022, 0x7226, 0x792c, 0x9180, 0x0000, 0x2004, 0x908e, 0x0002,
+	0x0130, 0x908e, 0x0004, 0x0118, 0x2009, 0x4000, 0x0010, 0x2009,
+	0x0000, 0x712a, 0x60c3, 0x0018, 0x002e, 0x00de, 0x080c, 0x76f5,
+	0x0005, 0x0036, 0x0046, 0x0056, 0x0066, 0x080c, 0x7234, 0x9006,
+	0x7003, 0x0200, 0x7938, 0x710a, 0x793c, 0x710e, 0x7810, 0x9080,
+	0x0028, 0x2004, 0x2011, 0x1133, 0x2214, 0xd2ac, 0x1118, 0x9092,
+	0x007e, 0x0268, 0x00d6, 0x2069, 0x111b, 0x2d2c, 0x8d68, 0x2d34,
+	0x90e8, 0x1000, 0x2d6c, 0x6b10, 0x6c14, 0x00de, 0x0030, 0x2019,
+	0x0000, 0x6498, 0x2029, 0x0000, 0x6634, 0x782c, 0x9080, 0x0008,
+	0x2004, 0x9086, 0x0003, 0x1128, 0x7512, 0x7616, 0x731a, 0x741e,
+	0x0020, 0x7312, 0x7416, 0x751a, 0x761e, 0x006e, 0x005e, 0x004e,
+	0x003e, 0x0005, 0x080c, 0x7234, 0x7003, 0x0100, 0x700b, 0x0009,
+	0x7814, 0x700e, 0x60c3, 0x0008, 0x080c, 0x76f5, 0x0005, 0x080c,
+	0x71b5, 0x7003, 0x1400, 0x7838, 0x700a, 0x783c, 0x700e, 0x782c,
+	0x7012, 0x7830, 0x7016, 0x7834, 0x9084, 0x00ff, 0x8007, 0x701a,
+	0x60c3, 0x0010, 0x080c, 0x76f5, 0x0005, 0x080c, 0x722b, 0x7003,
+	0x0100, 0x782c, 0x700a, 0x7814, 0x700e, 0x60c3, 0x0008, 0x080c,
+	0x76f5, 0x0005, 0x0029, 0x60c3, 0x0000, 0x080c, 0x76f5, 0x0005,
+	0x00d6, 0x080c, 0x7e9b, 0x7810, 0x2068, 0x6810, 0x9085, 0x0300,
+	0x7002, 0x6814, 0x7006, 0x68a0, 0x2069, 0x1100, 0x6acc, 0xd2ac,
+	0x1110, 0xd0bc, 0x0188, 0x686c, 0x700a, 0x6870, 0x700e, 0x7013,
+	0x0819, 0x080c, 0x76e4, 0x721a, 0x2f10, 0x7222, 0x7a08, 0x7226,
+	0x2071, 0x024c, 0x00de, 0x0005, 0x6234, 0x720e, 0x0c80, 0x0059,
+	0x7914, 0x712a, 0x60c3, 0x0000, 0x60a7, 0x9575, 0x080c, 0x7718,
+	0x080c, 0x65c6, 0x0005, 0x0036, 0x00d6, 0x00e6, 0x7858, 0x2068,
+	0x9df0, 0x001b, 0x7210, 0x9296, 0x00c0, 0x9294, 0xfffd, 0x7212,
+	0x7214, 0x9294, 0x0300, 0x7216, 0x7100, 0x9194, 0x00ff, 0x7308,
+	0x9384, 0x00ff, 0x908d, 0xc200, 0x7102, 0x9384, 0xff00, 0x9215,
+	0x720a, 0x7004, 0x720c, 0x700e, 0x7206, 0x00d6, 0x2069, 0x0200,
+	0x080c, 0x7e9b, 0x00de, 0x20e9, 0x0000, 0x20a1, 0x0240, 0x20a9,
+	0x000a, 0x20e1, 0x0001, 0x2e98, 0x4003, 0x60a3, 0x0035, 0x6a68,
+	0x9294, 0x7000, 0x9286, 0x3000, 0x0110, 0x60a3, 0x0037, 0x00ee,
+	0x00de, 0x003e, 0x0005, 0x900e, 0x7814, 0x9080, 0x001f, 0x2004,
+	0xd0fc, 0x01d8, 0x9084, 0x0003, 0x11c0, 0x2001, 0x110c, 0x2004,
+	0xd0bc, 0x0198, 0x7824, 0xd0cc, 0x1180, 0xd0c4, 0x1170, 0x7814,
+	0x9080, 0x002a, 0x2004, 0x9005, 0x1140, 0x2001, 0x110c, 0x200c,
+	0xc1d5, 0x2102, 0x2009, 0x12c1, 0x210c, 0x918d, 0x0092, 0x0010,
+	0x2009, 0x0096, 0x60ab, 0x0036, 0x6116, 0x0005, 0x2009, 0x0009,
+	0x00a0, 0x2009, 0x000a, 0x0088, 0x2009, 0x000b, 0x0070, 0x2009,
+	0x000c, 0x0058, 0x2009, 0x000d, 0x0040, 0x2009, 0x000e, 0x0028,
+	0x2009, 0x000f, 0x0010, 0x2009, 0x0008, 0x6912, 0x0005, 0x00d6,
+	0x9290, 0x0018, 0x8214, 0x20e9, 0x0000, 0x2069, 0x0200, 0x6813,
+	0x0000, 0x22a8, 0x9284, 0x00e0, 0x0128, 0x20a9, 0x0020, 0x9292,
+	0x0020, 0x0008, 0x9016, 0x20a1, 0x0240, 0x9006, 0x4004, 0x82ff,
+	0x0120, 0x6810, 0x8000, 0x6812, 0x0c60, 0x00de, 0x0005, 0x2061,
+	0x15c0, 0x2071, 0x1100, 0x7064, 0x7046, 0x704b, 0x15c0, 0x0005,
+	0x00e6, 0x0126, 0x2071, 0x1100, 0x2091, 0x8000, 0x7544, 0x9582,
+	0x0010, 0x0608, 0x7048, 0x2060, 0x6000, 0x9086, 0x0000, 0x0148,
+	0x9ce0, 0x0018, 0x7058, 0x9c02, 0x1208, 0x0cb0, 0x2061, 0x15c0,
+	0x0c98, 0x6003, 0x0008, 0x8529, 0x7546, 0x9ca8, 0x0018, 0x7058,
+	0x9502, 0x1230, 0x754a, 0x9085, 0x0001, 0x012e, 0x00ee, 0x0005,
+	0x704b, 0x15c0, 0x0cc0, 0x9006, 0x0cc0, 0x00e6, 0x2071, 0x1100,
+	0x7544, 0x9582, 0x0010, 0x0600, 0x7048, 0x2060, 0x6000, 0x9086,
+	0x0000, 0x0148, 0x9ce0, 0x0018, 0x7058, 0x9c02, 0x1208, 0x0cb0,
+	0x2061, 0x15c0, 0x0c98, 0x6003, 0x0008, 0x8529, 0x7546, 0x9ca8,
+	0x0018, 0x7058, 0x9502, 0x1228, 0x754a, 0x9085, 0x0001, 0x00ee,
+	0x0005, 0x704b, 0x15c0, 0x0cc8, 0x9006, 0x0cc8, 0x9c82, 0x15c0,
+	0x0a0c, 0x0cf1, 0x2001, 0x1116, 0x2004, 0x9c02, 0x1a0c, 0x0cf1,
+	0x9006, 0x6006, 0x600a, 0x600e, 0x6016, 0x601a, 0x6012, 0x6023,
+	0x0000, 0x6003, 0x0000, 0x601e, 0x6056, 0x605a, 0x6026, 0x602a,
+	0x602e, 0x6032, 0x6036, 0x603a, 0x603e, 0x6042, 0x2061, 0x1100,
+	0x6044, 0x8000, 0x6046, 0x9086, 0x0001, 0x0108, 0x0005, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6d42, 0x012e, 0x0cc0, 0x6020, 0x9084,
+	0x000f, 0x0002, 0x7f60, 0x7f70, 0x7f8b, 0x7fa6, 0x9af2, 0x9b0d,
+	0x9b28, 0x7f60, 0x7f70, 0x7f60, 0x7fc2, 0x7f60, 0x7f60, 0x7f60,
+	0x9186, 0x0013, 0x1128, 0x080c, 0x6c56, 0x080c, 0x6d42, 0x0005,
+	0x9186, 0x0047, 0x1120, 0x9016, 0x080c, 0x119a, 0x0000, 0x0005,
+	0x0066, 0x6000, 0x90b2, 0x0016, 0x1a0c, 0x0cf1, 0x0013, 0x006e,
+	0x0005, 0x7f89, 0x8406, 0x85b0, 0x7f89, 0x862d, 0x8072, 0x7f89,
+	0x7f89, 0x8392, 0x8a82, 0x7f89, 0x7f89, 0x7f89, 0x7f89, 0x7f89,
+	0x7f89, 0x080c, 0x0cf1, 0x0066, 0x6000, 0x90b2, 0x0016, 0x1a0c,
+	0x0cf1, 0x0013, 0x006e, 0x0005, 0x7fa4, 0x9085, 0x7fa4, 0x7fa4,
+	0x7fa4, 0x7fa4, 0x7fa4, 0x7fa4, 0x902d, 0x91f5, 0x7fa4, 0x90b6,
+	0x9131, 0x90b6, 0x9131, 0x7fa4, 0x080c, 0x0cf1, 0x6000, 0x9082,
+	0x0016, 0x1a0c, 0x0cf1, 0x6000, 0x0002, 0x7fc0, 0x8ac3, 0x8b8c,
+	0x8caa, 0x8e09, 0x7fc0, 0x7fc0, 0x7fc0, 0x8a9d, 0x8fdd, 0x8fe0,
+	0x7fc0, 0x7fc0, 0x7fc0, 0x7fc0, 0x900a, 0x7fc0, 0x7fc0, 0x7fc0,
+	0x080c, 0x0cf1, 0x0066, 0x6000, 0x90b2, 0x0016, 0x1a0c, 0x0cf1,
+	0x0013, 0x006e, 0x0005, 0x7fdb, 0x7fdb, 0x7fdb, 0x7ffe, 0x8051,
+	0x7fdb, 0x7fdb, 0x7fdb, 0x7fdd, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+	0x7fdb, 0x7fdb, 0x7fdb, 0x080c, 0x0cf1, 0x9186, 0x0003, 0x190c,
+	0x0cf1, 0x00d6, 0x6003, 0x0003, 0x6106, 0x6014, 0x2068, 0x687f,
+	0x0040, 0x68ac, 0x6846, 0x68b0, 0x684a, 0x6837, 0x0000, 0x683b,
+	0x0000, 0x00de, 0x2c10, 0x080c, 0x13a9, 0x080c, 0x68eb, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6e10, 0x012e, 0x0005, 0x9182, 0x0047,
+	0x0002, 0x800a, 0x800a, 0x800c, 0x802b, 0x800a, 0x800a, 0x800a,
+	0x800a, 0x803d, 0x080c, 0x0cf1, 0x00d6, 0x0016, 0x080c, 0x6cf2,
+	0x080c, 0x6e10, 0x6003, 0x0004, 0x6114, 0x2168, 0x6884, 0x8003,
+	0x800b, 0x810b, 0x9108, 0x611a, 0x687f, 0x0020, 0x688c, 0x688a,
+	0x68a4, 0x68ae, 0x68a8, 0x68b2, 0x68c7, 0x0000, 0x68cb, 0x0000,
+	0x001e, 0x00de, 0x0005, 0x080c, 0x6cf2, 0x00d6, 0x6114, 0x2168,
+	0x080c, 0x95d2, 0x0120, 0x687b, 0x0006, 0x080c, 0x50a5, 0x00de,
+	0x080c, 0x7f1e, 0x080c, 0x6e10, 0x0005, 0x080c, 0x6cf2, 0x080c,
+	0x25ad, 0x00d6, 0x6114, 0x2168, 0x080c, 0x95d2, 0x0120, 0x687b,
+	0x0029, 0x080c, 0x50a5, 0x00de, 0x080c, 0x7f1e, 0x080c, 0x6e10,
+	0x0005, 0x9182, 0x0047, 0x0002, 0x8061, 0x8063, 0x8061, 0x8061,
+	0x8061, 0x8061, 0x8061, 0x8061, 0x8061, 0x8061, 0x8061, 0x8061,
+	0x8063, 0x080c, 0x0cf1, 0x00d6, 0x080c, 0x1132, 0x6114, 0x2168,
+	0x687b, 0x0000, 0x6883, 0x0000, 0x080c, 0x50a5, 0x00de, 0x080c,
+	0x7f1e, 0x0005, 0x91b6, 0x0015, 0x1118, 0x080c, 0x7f1e, 0x0030,
+	0x91b6, 0x0016, 0x190c, 0x0cf1, 0x080c, 0x7f1e, 0x0005, 0x20a9,
+	0x000e, 0x20e1, 0x0000, 0x2e98, 0x6014, 0x20e9, 0x0001, 0x20a0,
+	0x4003, 0x9080, 0x001b, 0x20a0, 0x20a9, 0x0006, 0x3310, 0x3420,
+	0x9298, 0x0001, 0x94a8, 0x0001, 0x222e, 0x2326, 0x9290, 0x0002,
+	0x95a8, 0x0002, 0x9398, 0x0002, 0x94a0, 0x0002, 0x1f04, 0x8094,
+	0x00e6, 0x080c, 0x95d2, 0x0130, 0x6014, 0x2070, 0x7007, 0x0000,
+	0x7067, 0x0103, 0x00ee, 0x080c, 0x7f1e, 0x0005, 0x00d6, 0x0036,
+	0x7330, 0x9386, 0x0200, 0x1130, 0x6010, 0x2068, 0x6813, 0x00ff,
+	0x6817, 0xfffd, 0x6014, 0x9005, 0x0130, 0x2068, 0x6807, 0x0000,
+	0x6867, 0x0103, 0x6b32, 0x080c, 0x7f1e, 0x003e, 0x00de, 0x0005,
+	0x0016, 0x20a9, 0x002a, 0x9e80, 0x000c, 0x20e1, 0x0000, 0x2098,
+	0x6014, 0x9080, 0x0002, 0x20e9, 0x0001, 0x20a0, 0x4003, 0x20a9,
+	0x002a, 0x6014, 0x9080, 0x0001, 0x2004, 0x9080, 0x0002, 0x20a0,
+	0x4003, 0x00e6, 0x6014, 0x2004, 0x2070, 0x7067, 0x0103, 0x00ee,
+	0x080c, 0x7f1e, 0x001e, 0x0005, 0x0016, 0x2009, 0x0000, 0x7030,
+	0x9086, 0x0100, 0x0140, 0x7038, 0x9084, 0x00ff, 0x800c, 0x703c,
+	0x9084, 0x00ff, 0x8004, 0x9080, 0x0004, 0x9108, 0x9192, 0x0014,
+	0x1218, 0x2011, 0x0000, 0x0010, 0x2009, 0x0014, 0x21a8, 0x9e80,
+	0x000c, 0x2098, 0x6014, 0x9080, 0x0002, 0x20a0, 0x080c, 0x4678,
+	0x82ff, 0x0170, 0x2009, 0x0205, 0x2104, 0x8000, 0x200a, 0x2e00,
+	0x2098, 0x3400, 0x9080, 0x0014, 0x20a0, 0x22a8, 0x080c, 0x4678,
+	0x00e6, 0x080c, 0x95d2, 0x0140, 0x6014, 0x2070, 0x7007, 0x0000,
+	0x7064, 0x70e2, 0x7067, 0x0103, 0x00ee, 0x080c, 0x7f1e, 0x001e,
+	0x0005, 0x0016, 0x00d6, 0x7030, 0x9086, 0x0100, 0x1118, 0x2009,
+	0x0004, 0x0010, 0x7034, 0x800c, 0x21a8, 0x9e80, 0x000c, 0x2098,
+	0x6014, 0x2068, 0x6804, 0x9005, 0x1108, 0x2d00, 0x9080, 0x000c,
+	0x20a0, 0x080c, 0x4678, 0x080c, 0x95d2, 0x0148, 0x6804, 0x9005,
+	0x1158, 0x6807, 0x0000, 0x6864, 0x68e2, 0x6867, 0x0103, 0x080c,
+	0x7f1e, 0x00de, 0x001e, 0x0005, 0x00e6, 0x2070, 0x7030, 0x8007,
+	0x9086, 0x0100, 0x1118, 0x080c, 0x8576, 0x00b8, 0x7034, 0x8007,
+	0x800c, 0x9e80, 0x000c, 0x687b, 0x0000, 0x6883, 0x0000, 0x6897,
+	0x4000, 0x6aa0, 0x6b9c, 0x6ca8, 0x6da4, 0x2031, 0x0000, 0x2039,
+	0x0001, 0x2041, 0x0f7e, 0x0019, 0x0d30, 0x00ee, 0x08c0, 0x00d6,
+	0x0006, 0x080c, 0x0dc6, 0x000e, 0x0190, 0x6812, 0x000e, 0x683e,
+	0x0006, 0x6e06, 0x2800, 0x683a, 0x6916, 0x6f0e, 0x6a2a, 0x6b2e,
+	0x6c32, 0x6d36, 0x2d10, 0x080c, 0x0e55, 0x9085, 0x0001, 0x00de,
+	0x0005, 0x00e6, 0x00d6, 0x6043, 0x0000, 0x2c68, 0x0016, 0x2009,
+	0x0035, 0x080c, 0x9ac5, 0x001e, 0x1168, 0x0026, 0x622c, 0x2268,
+	0x002e, 0x2071, 0x026c, 0x6b20, 0x9386, 0x0003, 0x0130, 0x9386,
+	0x0006, 0x0128, 0x080c, 0x7f1e, 0x0020, 0x0031, 0x0010, 0x080c,
+	0x8270, 0x00de, 0x00ee, 0x0005, 0x00f6, 0x6814, 0x2078, 0x9186,
+	0x0015, 0x0904, 0x8259, 0x918e, 0x0016, 0x1904, 0x826e, 0x700c,
+	0x9084, 0xff00, 0x9086, 0x1700, 0x1904, 0x8238, 0x8fff, 0x1138,
+	0x6800, 0x9086, 0x000f, 0x0904, 0x821c, 0x0804, 0x826c, 0x6808,
+	0x9086, 0xffff, 0x1904, 0x825b, 0x787c, 0x9084, 0x0060, 0x9086,
+	0x0020, 0x1128, 0x783c, 0x7940, 0x9105, 0x1904, 0x825b, 0x080c,
+	0x9797, 0x685c, 0x7882, 0x787c, 0xc0dc, 0xc0f4, 0xc0d4, 0x787e,
+	0x0026, 0x900e, 0x6a18, 0x2001, 0x000a, 0x080c, 0x66ff, 0x7884,
+	0x920a, 0x0208, 0x8011, 0x7a86, 0x82ff, 0x002e, 0x1138, 0x00c6,
+	0x2d60, 0x080c, 0x9389, 0x00ce, 0x0804, 0x826c, 0x00c6, 0x00d6,
+	0x2f68, 0x6868, 0xd0fc, 0x1118, 0x080c, 0x477e, 0x0010, 0x080c,
+	0x4a18, 0x00de, 0x00ce, 0x1904, 0x825b, 0x00c6, 0x2d60, 0x080c,
+	0x7f1e, 0x00ce, 0x0804, 0x826c, 0x00c6, 0x080c, 0x984d, 0x0190,
+	0x6017, 0x0000, 0x6810, 0x6012, 0x080c, 0x99cc, 0x6023, 0x0003,
+	0x6904, 0x00c6, 0x2d60, 0x080c, 0x7f1e, 0x00ce, 0x080c, 0x7f4e,
+	0x00ce, 0x04d0, 0x2001, 0x12a8, 0x2004, 0x6842, 0x00ce, 0x04a0,
+	0x7008, 0x9086, 0x000b, 0x11a0, 0x6010, 0x200c, 0xc1bc, 0x2102,
+	0x00c6, 0x2d60, 0x7883, 0x0003, 0x6007, 0x0085, 0x6003, 0x000b,
+	0x6023, 0x0002, 0x080c, 0x6886, 0x080c, 0x6d42, 0x00ce, 0x00e0,
+	0x700c, 0x9086, 0x2a00, 0x1138, 0x2001, 0x12a8, 0x2004, 0x6842,
+	0x0098, 0x0471, 0x0098, 0x8fff, 0x090c, 0x0cf1, 0x00c6, 0x00d6,
+	0x2d60, 0x2f68, 0x687b, 0x0003, 0x080c, 0x926a, 0x080c, 0x9797,
+	0x080c, 0x97a3, 0x00de, 0x00ce, 0x080c, 0x7f1e, 0x00fe, 0x0005,
+	0x9186, 0x0015, 0x1128, 0x2001, 0x12a8, 0x2004, 0x6842, 0x0068,
+	0x918e, 0x0016, 0x1160, 0x00c6, 0x2d00, 0x2060, 0x080c, 0xad19,
+	0x080c, 0x66ae, 0x080c, 0x7f1e, 0x00ce, 0x080c, 0x7f1e, 0x0005,
+	0x0026, 0x0036, 0x0046, 0x7228, 0x7cb0, 0x7bac, 0xd2f4, 0x0130,
+	0x2001, 0x12a8, 0x2004, 0x6842, 0x0804, 0x82ec, 0x00c6, 0x2d60,
+	0x080c, 0x9297, 0x00ce, 0x6804, 0x9086, 0x0050, 0x1170, 0x00c6,
+	0x2d00, 0x2060, 0x6003, 0x0001, 0x6007, 0x0050, 0x080c, 0x6886,
+	0x080c, 0x6d42, 0x00ce, 0x0804, 0x82ec, 0x6800, 0x9086, 0x000f,
+	0x01c8, 0x8fff, 0x090c, 0x0cf1, 0x6824, 0xd0dc, 0x1198, 0x6800,
+	0x9086, 0x0004, 0x1198, 0x787c, 0xd0ac, 0x0180, 0x7843, 0x0fff,
+	0x783f, 0x0fff, 0x7880, 0xc0f4, 0xc0fc, 0x7882, 0x2001, 0x0001,
+	0x6832, 0x00e8, 0x2001, 0x0007, 0x6832, 0x00c8, 0x787c, 0xd0b4,
+	0x1138, 0xd0ac, 0x0db8, 0x7838, 0x7934, 0x9105, 0x0d98, 0x0c30,
+	0xd2ec, 0x1d80, 0x7024, 0x9306, 0x1118, 0x7020, 0x9406, 0x0d50,
+	0x7020, 0x683e, 0x7024, 0x683a, 0x2001, 0x0005, 0x6832, 0x080c,
+	0x98d9, 0x080c, 0x6d42, 0x0010, 0x080c, 0x7f1e, 0x004e, 0x003e,
+	0x002e, 0x0005, 0x00e6, 0x00d6, 0x0026, 0x6038, 0x2068, 0x6a20,
+	0x9286, 0x0007, 0x0904, 0x8350, 0x9286, 0x0002, 0x0904, 0x8350,
+	0x9286, 0x0000, 0x0904, 0x8350, 0x6808, 0x633c, 0x9306, 0x1904,
+	0x8350, 0x2071, 0x026c, 0x9186, 0x0015, 0x05e0, 0x918e, 0x0016,
+	0x1190, 0x6034, 0x9084, 0x00ff, 0x9086, 0x0001, 0x1160, 0x700c,
+	0x9086, 0x2a00, 0x1140, 0x6038, 0x9080, 0x0009, 0x200c, 0xc1dd,
+	0xc1f5, 0x2102, 0x0438, 0x00c6, 0x6038, 0x2060, 0x6104, 0x9186,
+	0x004b, 0x01a0, 0x9186, 0x004c, 0x0188, 0x9186, 0x004d, 0x0170,
+	0x9186, 0x004e, 0x0158, 0x9186, 0x0052, 0x0140, 0x6014, 0x2068,
+	0x080c, 0x95d2, 0x090c, 0x0cf1, 0x6883, 0x0003, 0x6007, 0x0085,
+	0x6003, 0x000b, 0x6023, 0x0002, 0x080c, 0x6886, 0x080c, 0x6d42,
+	0x00ce, 0x0030, 0x6038, 0x2070, 0x2001, 0x12a8, 0x2004, 0x7042,
+	0x080c, 0x7f1e, 0x002e, 0x00de, 0x00ee, 0x0005, 0x00d6, 0x00f6,
+	0x6014, 0x2068, 0x6010, 0x2078, 0x91b6, 0x0015, 0x0130, 0x7a08,
+	0x7b0c, 0x7c00, 0xc48c, 0x7c02, 0x0038, 0x7238, 0x7a0a, 0x733c,
+	0x7b0e, 0x7c00, 0xc48d, 0x7c02, 0x6804, 0x9005, 0x1120, 0x00fe,
+	0x00de, 0x0804, 0x80a0, 0x9080, 0x0002, 0x00d6, 0x2068, 0x6a0a,
+	0x6b0e, 0x6c02, 0x00de, 0x2009, 0x002b, 0x6aa0, 0x6b9c, 0x6ca8,
+	0x6da4, 0x2031, 0x0000, 0x2039, 0x0001, 0x2041, 0x0f7e, 0x080c,
+	0x817f, 0x0128, 0x00fe, 0x00de, 0x080c, 0x7f1e, 0x0005, 0x080c,
+	0x8576, 0x0cc0, 0x2100, 0x91b2, 0x004c, 0x1a0c, 0x0cf1, 0x91b2,
+	0x0040, 0x1a04, 0x83f6, 0x0002, 0x83ea, 0x83de, 0x83ea, 0x83ea,
+	0x83ea, 0x83ea, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc,
+	0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc,
+	0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc,
+	0x83dc, 0x83dc, 0x83dc, 0x83ea, 0x83dc, 0x83ea, 0x83ea, 0x83dc,
+	0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83ea, 0x83dc, 0x83dc, 0x83dc,
+	0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83ea, 0x83ea,
+	0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc, 0x83dc,
+	0x83dc, 0x83ea, 0x83dc, 0x83dc, 0x080c, 0x0cf1, 0x6003, 0x0001,
+	0x6106, 0x080c, 0x68ce, 0x0126, 0x2091, 0x8000, 0x080c, 0x6d42,
+	0x012e, 0x0005, 0x6003, 0x0001, 0x6106, 0x080c, 0x68ce, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6d42, 0x012e, 0x0005, 0x2600, 0x0002,
+	0x8404, 0x8404, 0x8404, 0x83ea, 0x83ea, 0x8404, 0x8404, 0x8404,
+	0x8404, 0x83ea, 0x8404, 0x8404, 0x080c, 0x0cf1, 0x6004, 0x90b2,
+	0x004c, 0x1a0c, 0x0cf1, 0x91b6, 0x0013, 0x0904, 0x84a2, 0x91b6,
+	0x0027, 0x1904, 0x8468, 0x080c, 0x6c56, 0x6004, 0x080c, 0x97bc,
+	0x0178, 0x080c, 0x97cd, 0x0904, 0x8462, 0x908e, 0x0021, 0x0904,
+	0x8465, 0x908e, 0x0022, 0x05f0, 0x908e, 0x003d, 0x05f0, 0x0498,
+	0x080c, 0x25d1, 0x2001, 0x0007, 0x080c, 0x4ab3, 0x6010, 0x9080,
+	0x0028, 0x200c, 0x080c, 0x8576, 0x9186, 0x007e, 0x1148, 0x2001,
+	0x1133, 0x2014, 0xc285, 0x080c, 0x5745, 0x1108, 0xc2ad, 0x2202,
+	0x0016, 0x0026, 0x0036, 0x2110, 0x2019, 0x0028, 0x080c, 0x69ca,
+	0x0076, 0x2039, 0x0000, 0x080c, 0x68fe, 0x6010, 0x00c6, 0x9065,
+	0x0100, 0x00ce, 0x2c08, 0x080c, 0xa85f, 0x007e, 0x003e, 0x002e,
+	0x001e, 0x080c, 0x4b20, 0x080c, 0x99c4, 0x080c, 0x7f1e, 0x080c,
+	0x6d42, 0x0005, 0x080c, 0x8576, 0x0cb0, 0x080c, 0x85a4, 0x0c98,
+	0x9186, 0x0014, 0x1db0, 0x080c, 0x6c56, 0x080c, 0x25ad, 0x080c,
+	0x97bc, 0x1188, 0x080c, 0x25d1, 0x6010, 0x9080, 0x0028, 0x200c,
+	0x080c, 0x8576, 0x9186, 0x007e, 0x1128, 0x2001, 0x1133, 0x200c,
+	0xc185, 0x2102, 0x08c0, 0x080c, 0x97cd, 0x1118, 0x080c, 0x8576,
+	0x0890, 0x6004, 0x908e, 0x0032, 0x1158, 0x00e6, 0x00f6, 0x2071,
+	0x1193, 0x2079, 0x0000, 0x080c, 0x28cc, 0x00fe, 0x00ee, 0x0818,
+	0x6004, 0x908e, 0x0021, 0x0d50, 0x908e, 0x0022, 0x090c, 0x8576,
+	0x0804, 0x845b, 0x90b2, 0x0040, 0x1a04, 0x8565, 0x2008, 0x0002,
+	0x84ea, 0x84eb, 0x84ee, 0x84f1, 0x84f4, 0x84f7, 0x84e8, 0x84e8,
+	0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8,
+	0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8,
+	0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84fa, 0x8509,
+	0x84e8, 0x850b, 0x8509, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8,
+	0x8509, 0x8509, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8, 0x84e8,
+	0x84e8, 0x84e8, 0x8545, 0x8509, 0x84e8, 0x8505, 0x84e8, 0x84e8,
+	0x84e8, 0x8506, 0x84e8, 0x84e8, 0x84e8, 0x8509, 0x853c, 0x84e8,
+	0x080c, 0x0cf1, 0x00f0, 0x2001, 0x000b, 0x0460, 0x2001, 0x0003,
+	0x0448, 0x2001, 0x0005, 0x0430, 0x2001, 0x0001, 0x0418, 0x2001,
+	0x0009, 0x0400, 0x080c, 0x6c56, 0x6003, 0x0005, 0x2001, 0x12a8,
+	0x2004, 0x6042, 0x080c, 0x6d42, 0x00a0, 0x0018, 0x0010, 0x080c,
+	0x4ab3, 0x0804, 0x8556, 0x080c, 0x6c56, 0x2001, 0x12a6, 0x2004,
+	0x601a, 0x2001, 0x12a8, 0x2004, 0x6042, 0x6003, 0x0004, 0x080c,
+	0x6d42, 0x0005, 0x080c, 0x4ab3, 0x080c, 0x6c56, 0x6003, 0x0002,
+	0x2001, 0x12a8, 0x2004, 0x6042, 0x0036, 0x2019, 0x115d, 0x2304,
+	0x9084, 0xff00, 0x1120, 0x2001, 0x12a6, 0x201c, 0x0040, 0x8007,
+	0x909a, 0x0004, 0x0ec0, 0x8003, 0x801b, 0x831b, 0x9318, 0x631a,
+	0x003e, 0x080c, 0x6d42, 0x08e8, 0x080c, 0x6c56, 0x080c, 0x99c4,
+	0x080c, 0x7f1e, 0x080c, 0x6d42, 0x08a0, 0x00e6, 0x00f6, 0x2071,
+	0x1193, 0x2079, 0x0000, 0x080c, 0x28cc, 0x00fe, 0x00ee, 0x080c,
+	0x6c56, 0x080c, 0x7f1e, 0x080c, 0x6d42, 0x0818, 0x080c, 0x6c56,
+	0x2001, 0x12a8, 0x2004, 0x6042, 0x6003, 0x0002, 0x2001, 0x12a6,
+	0x2004, 0x601a, 0x080c, 0x6d42, 0x0005, 0x2600, 0x2008, 0x0002,
+	0x8574, 0x8574, 0x8574, 0x8556, 0x8556, 0x8574, 0x8574, 0x8574,
+	0x8574, 0x8556, 0x8574, 0x8574, 0x080c, 0x0cf1, 0x00e6, 0x0026,
+	0x0016, 0x080c, 0x95d2, 0x0508, 0x6014, 0x2070, 0x7064, 0x9086,
+	0x0139, 0x1148, 0x2001, 0x0030, 0x2009, 0x0000, 0x2011, 0x4005,
+	0x080c, 0x9a7b, 0x0090, 0x7068, 0xd0fc, 0x0178, 0x7007, 0x0000,
+	0x0016, 0x6004, 0x908e, 0x0021, 0x0160, 0x908e, 0x003d, 0x0148,
+	0x001e, 0x7067, 0x0103, 0x7033, 0x0100, 0x001e, 0x002e, 0x00ee,
+	0x0005, 0x001e, 0x0009, 0x0cc8, 0x00e6, 0x9cf0, 0x0005, 0x2e74,
+	0x7000, 0x2070, 0x7067, 0x0103, 0x7023, 0x8001, 0x00ee, 0x0005,
+	0x00d6, 0x6610, 0x2668, 0x6804, 0x9084, 0x00ff, 0x00de, 0x90b2,
+	0x000c, 0x1a0c, 0x0cf1, 0x6604, 0x96b6, 0x0043, 0x1120, 0x080c,
+	0x9a37, 0x0804, 0x861d, 0x6604, 0x96b6, 0x0033, 0x1120, 0x080c,
+	0x99e7, 0x0804, 0x861d, 0x6604, 0x96b6, 0x0028, 0x1120, 0x080c,
+	0x97fd, 0x0804, 0x861d, 0x6604, 0x96b6, 0x0029, 0x1120, 0x080c,
+	0x9816, 0x0804, 0x861d, 0x6604, 0x96b6, 0x001f, 0x1118, 0x080c,
+	0x807f, 0x04d8, 0x6604, 0x96b6, 0x0000, 0x1118, 0x080c, 0x8356,
+	0x04a0, 0x6604, 0x96b6, 0x0022, 0x1118, 0x080c, 0x80ae, 0x0468,
+	0x6604, 0x96b6, 0x0035, 0x1118, 0x080c, 0x8199, 0x0430, 0x6604,
+	0x96b6, 0x0039, 0x1118, 0x080c, 0x82f2, 0x00f8, 0x6604, 0x96b6,
+	0x003d, 0x1118, 0x080c, 0x80c8, 0x00c0, 0x6604, 0x96b6, 0x0044,
+	0x1118, 0x080c, 0x80ec, 0x0088, 0x6604, 0x96b6, 0x0049, 0x1118,
+	0x080c, 0x8131, 0x0050, 0x91b6, 0x0015, 0x1110, 0x0053, 0x0028,
+	0x91b6, 0x0016, 0x1118, 0x0804, 0x87e2, 0x0005, 0x080c, 0x7f68,
+	0x0ce0, 0x863b, 0x863e, 0x863b, 0x8682, 0x863b, 0x8762, 0x87f0,
+	0x863b, 0x863b, 0x87bc, 0x863b, 0x87d2, 0x00e6, 0x080c, 0x1132,
+	0x9cf0, 0x0005, 0x2e74, 0x7000, 0x2070, 0x7067, 0x0103, 0x00ee,
+	0x080c, 0x7f1e, 0x0005, 0xa001, 0xa001, 0x0005, 0x00e6, 0x2071,
+	0x1100, 0x7080, 0x9086, 0x0074, 0x1540, 0x080c, 0xa836, 0x11b0,
+	0x6010, 0x00d6, 0x2068, 0x7030, 0xd08c, 0x0128, 0x6800, 0xd0bc,
+	0x0110, 0xc0c5, 0x6802, 0x00e9, 0x00de, 0x2001, 0x0006, 0x080c,
+	0x4ab3, 0x080c, 0x25d1, 0x080c, 0x7f1e, 0x0088, 0x2001, 0x000a,
+	0x080c, 0x4ab3, 0x080c, 0x25d1, 0x6003, 0x0001, 0x6007, 0x0001,
+	0x080c, 0x68ce, 0x080c, 0x6d42, 0x0010, 0x080c, 0x8752, 0x00ee,
+	0x0005, 0x6800, 0xd084, 0x0168, 0x2001, 0x0000, 0x080c, 0x4aa1,
+	0x2069, 0x1152, 0x6804, 0xd0a4, 0x0120, 0x2001, 0x0006, 0x080c,
+	0x4ae0, 0x0005, 0x00d6, 0x2011, 0x1120, 0x2204, 0x9086, 0x0074,
+	0x1904, 0x874f, 0x6010, 0x2068, 0x6aa0, 0x9286, 0x007e, 0x1120,
+	0x080c, 0x88f8, 0x0804, 0x86f0, 0x080c, 0x88ee, 0x6010, 0x2068,
+	0x6aa0, 0x9286, 0x0080, 0x11c0, 0x6813, 0x00ff, 0x6817, 0xfffc,
+	0x6014, 0x9005, 0x0138, 0x2068, 0x6807, 0x0000, 0x6867, 0x0103,
+	0x6833, 0x0200, 0x2001, 0x0006, 0x080c, 0x4ab3, 0x080c, 0x25d1,
+	0x080c, 0x7f1e, 0x0804, 0x8750, 0x00e6, 0x2071, 0x1133, 0x2e04,
+	0xd09c, 0x0188, 0x2071, 0x0260, 0x7108, 0x720c, 0x918c, 0x00ff,
+	0x1118, 0x9284, 0xff00, 0x0138, 0x6010, 0x2070, 0x70a0, 0xd0bc,
+	0x1110, 0x7112, 0x7216, 0x00ee, 0x6014, 0x9005, 0x0198, 0x2068,
+	0x6868, 0xd0f4, 0x0178, 0x6864, 0x9084, 0x00ff, 0x9086, 0x0039,
+	0x1958, 0x2001, 0x0000, 0x2009, 0x0000, 0x2011, 0x4000, 0x080c,
+	0x9a7b, 0x0840, 0x2001, 0x0004, 0x080c, 0x4ab3, 0x6003, 0x0001,
+	0x6007, 0x0003, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0804, 0x8750,
+	0x685c, 0xd0e4, 0x01d8, 0x080c, 0x9966, 0x080c, 0x5745, 0x0118,
+	0xd0dc, 0x1904, 0x86aa, 0x2011, 0x1133, 0x2204, 0xc0ad, 0x2012,
+	0x2001, 0x1280, 0x2004, 0x00f6, 0x2079, 0x0100, 0x78e3, 0x0000,
+	0x080c, 0x1cbe, 0x78e2, 0x00fe, 0x0804, 0x86aa, 0x080c, 0x99a3,
+	0x2011, 0x1133, 0x2204, 0xc0a5, 0x2012, 0x0006, 0x080c, 0xa966,
+	0x000e, 0x1904, 0x86aa, 0xc0b5, 0x2012, 0x2001, 0x0000, 0x080c,
+	0x4aa1, 0x00c6, 0x2009, 0x00ef, 0x00f6, 0x2079, 0x0100, 0x79ea,
+	0x7932, 0x7936, 0x00fe, 0x080c, 0x1c93, 0x00f6, 0x2079, 0x1100,
+	0x7972, 0x2100, 0x2009, 0x0000, 0x080c, 0x1c69, 0x794e, 0x00fe,
+	0x8108, 0x080c, 0x4b03, 0x2c00, 0x00ce, 0x1904, 0x86aa, 0x6012,
+	0x2001, 0x0002, 0x080c, 0x4ab3, 0x6023, 0x0001, 0x6003, 0x0001,
+	0x6007, 0x0002, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0008, 0x0011,
+	0x00de, 0x0005, 0x2030, 0x2001, 0x1100, 0x2004, 0x9086, 0x0003,
+	0x0120, 0x2001, 0x0007, 0x080c, 0x4ab3, 0x080c, 0x25d1, 0x080c,
+	0x7f1e, 0x0005, 0x00e6, 0x0026, 0x0016, 0x2071, 0x1100, 0x7080,
+	0x9086, 0x0014, 0x1904, 0x87b4, 0x7000, 0x9086, 0x0003, 0x1178,
+	0x6014, 0x9005, 0x1160, 0x0036, 0x0046, 0x6010, 0x9080, 0x0028,
+	0x201c, 0x2021, 0x0006, 0x080c, 0x384a, 0x004e, 0x003e, 0x00d6,
+	0x6010, 0x2068, 0x080c, 0x4bf5, 0x080c, 0x8671, 0x00de, 0x080c,
+	0x89bf, 0x1550, 0x6010, 0x00d6, 0x2068, 0x6890, 0x00de, 0x9005,
+	0x0518, 0x2001, 0x0006, 0x080c, 0x4ab3, 0x00e6, 0x6014, 0x9075,
+	0x01a8, 0x7064, 0x9084, 0x00ff, 0x9086, 0x0039, 0x1148, 0x2001,
+	0x0000, 0x2009, 0x0000, 0x2011, 0x4000, 0x080c, 0x9a7b, 0x0030,
+	0x7007, 0x0000, 0x7067, 0x0103, 0x7033, 0x0200, 0x00ee, 0x080c,
+	0x25d1, 0x080c, 0x7f1e, 0x0020, 0x080c, 0x8576, 0x080c, 0x8752,
+	0x001e, 0x002e, 0x00ee, 0x0005, 0x2011, 0x1120, 0x2204, 0x9086,
+	0x0014, 0x1168, 0x2001, 0x0002, 0x080c, 0x4ab3, 0x6003, 0x0001,
+	0x6007, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0010, 0x080c,
+	0x8752, 0x0005, 0x2011, 0x1120, 0x2204, 0x9086, 0x0004, 0x1138,
+	0x2001, 0x0007, 0x080c, 0x4ab3, 0x080c, 0x7f1e, 0x0010, 0x080c,
+	0x8752, 0x0005, 0x000b, 0x0005, 0x863b, 0x87f7, 0x863b, 0x882d,
+	0x863b, 0x88a4, 0x87f0, 0x863b, 0x863b, 0x88b9, 0x863b, 0x88cb,
+	0x6604, 0x96b6, 0x001e, 0x1110, 0x080c, 0x7f1e, 0x0005, 0x00d6,
+	0x00c6, 0x080c, 0x88dd, 0x1188, 0x2001, 0x0000, 0x080c, 0x4aa1,
+	0x2001, 0x0002, 0x080c, 0x4ab3, 0x6003, 0x0001, 0x6007, 0x0002,
+	0x080c, 0x68ce, 0x080c, 0x6d42, 0x00e8, 0x2009, 0x026e, 0x2104,
+	0x9086, 0x0009, 0x1160, 0x6010, 0x2068, 0x6840, 0x9084, 0x00ff,
+	0x9005, 0x0170, 0x8001, 0x6842, 0x601b, 0x000a, 0x0058, 0x2009,
+	0x026f, 0x2104, 0x9084, 0xff00, 0x9086, 0x1900, 0x1108, 0x08c0,
+	0x080c, 0x8752, 0x00ce, 0x00de, 0x0005, 0x080c, 0x88eb, 0x00d6,
+	0x2069, 0x128f, 0x2d04, 0x9005, 0x0168, 0x6010, 0x2068, 0x68a0,
+	0x9086, 0x007e, 0x1138, 0x2069, 0x111c, 0x2d04, 0x8000, 0x206a,
+	0x00de, 0x0010, 0x00de, 0x0088, 0x2001, 0x0000, 0x080c, 0x4aa1,
+	0x2001, 0x0002, 0x080c, 0x4ab3, 0x6003, 0x0001, 0x6007, 0x0002,
+	0x080c, 0x68ce, 0x080c, 0x6d42, 0x0428, 0x080c, 0x8576, 0x2009,
+	0x026e, 0x2134, 0x96b4, 0x00ff, 0x9686, 0x0005, 0x01e0, 0x9686,
+	0x000b, 0x01b0, 0x2009, 0x026f, 0x2104, 0x9084, 0xff00, 0x1118,
+	0x9686, 0x0009, 0x0180, 0x9086, 0x1900, 0x1150, 0x9686, 0x0009,
+	0x0150, 0x2001, 0x0004, 0x080c, 0x4ab3, 0x080c, 0x7f1e, 0x0010,
+	0x080c, 0x8752, 0x0005, 0x00d6, 0x6014, 0x2068, 0x080c, 0x95d2,
+	0x0128, 0x6868, 0xd0fc, 0x0110, 0x00de, 0x0c90, 0x6010, 0x2068,
+	0x6840, 0x9084, 0x00ff, 0x9005, 0x0140, 0x8001, 0x6842, 0x601b,
+	0x000a, 0x6007, 0x0016, 0x00de, 0x0c28, 0x68a0, 0x9086, 0x007e,
+	0x1138, 0x00e6, 0x2071, 0x1100, 0x080c, 0x46bb, 0x00ee, 0x0010,
+	0x080c, 0x25ad, 0x00de, 0x08a0, 0x080c, 0x88eb, 0x1168, 0x2001,
+	0x0004, 0x080c, 0x4ab3, 0x6003, 0x0001, 0x6007, 0x0003, 0x080c,
+	0x68ce, 0x080c, 0x6d42, 0x0020, 0x080c, 0x8576, 0x080c, 0x8752,
+	0x0005, 0x0489, 0x1168, 0x2001, 0x0008, 0x080c, 0x4ab3, 0x6003,
+	0x0001, 0x6007, 0x0005, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0010,
+	0x080c, 0x8752, 0x0005, 0x00f9, 0x1168, 0x2001, 0x000a, 0x080c,
+	0x4ab3, 0x6003, 0x0001, 0x6007, 0x0001, 0x080c, 0x68ce, 0x080c,
+	0x6d42, 0x0010, 0x080c, 0x8752, 0x0005, 0x2009, 0x026e, 0x2104,
+	0x9086, 0x0003, 0x1138, 0x2009, 0x026f, 0x2104, 0x9084, 0xff00,
+	0x9086, 0x2a00, 0x0005, 0x9085, 0x0001, 0x0005, 0x00c6, 0x0016,
+	0x9c88, 0x0004, 0x2164, 0x080c, 0x4b67, 0x001e, 0x00ce, 0x0005,
+	0x00f6, 0x00e6, 0x00d6, 0x0036, 0x0016, 0x6010, 0x2068, 0x2009,
+	0x1133, 0x2104, 0x9085, 0x0003, 0x200a, 0x080c, 0x8994, 0x0570,
+	0x2009, 0x1133, 0x2104, 0xc0cd, 0x200a, 0x2001, 0x1153, 0x2004,
+	0xd0a4, 0x0158, 0x9006, 0x2020, 0x2009, 0x002a, 0x080c, 0xaaca,
+	0x2001, 0x110c, 0x200c, 0xc195, 0x2102, 0x2019, 0x002a, 0x2009,
+	0x0001, 0x080c, 0x2582, 0x00e6, 0x2071, 0x1100, 0x080c, 0x23cd,
+	0x00ee, 0x00c6, 0x0156, 0x20a9, 0x0081, 0x2009, 0x007f, 0x080c,
+	0x26a3, 0x8108, 0x1f04, 0x892f, 0x015e, 0x00ce, 0x080c, 0x88ee,
+	0x6813, 0x00ff, 0x6817, 0xfffe, 0x2071, 0x0260, 0x2079, 0x0200,
+	0x7817, 0x0001, 0x2001, 0x1133, 0x200c, 0xc1c5, 0x7018, 0xd0fc,
+	0x0110, 0xd0dc, 0x0118, 0x7038, 0xd0dc, 0x1108, 0xc1c4, 0x7817,
+	0x0000, 0x2001, 0x1133, 0x2102, 0x2079, 0x0100, 0x2e04, 0x9084,
+	0x00ff, 0x2069, 0x111b, 0x206a, 0x78e6, 0x0006, 0x8e70, 0x2e04,
+	0x2069, 0x111c, 0x206a, 0x78ea, 0x7832, 0x7836, 0x2010, 0x9084,
+	0xff00, 0x001e, 0x9105, 0x2009, 0x1127, 0x200a, 0x2200, 0x9084,
+	0x00ff, 0x2008, 0x080c, 0x1c93, 0x080c, 0x5745, 0x0170, 0x2071,
+	0x0260, 0x2069, 0x12a2, 0x7048, 0x206a, 0x704c, 0x6806, 0x7050,
+	0x680a, 0x7054, 0x680e, 0x080c, 0x9966, 0x0040, 0x2001, 0x0006,
+	0x080c, 0x4ab3, 0x080c, 0x25d1, 0x080c, 0x7f1e, 0x001e, 0x003e,
+	0x00de, 0x00ee, 0x00fe, 0x0005, 0x0026, 0x0036, 0x00e6, 0x0156,
+	0x2019, 0x1127, 0x231c, 0x83ff, 0x01e8, 0x2071, 0x0260, 0x7200,
+	0x9294, 0x00ff, 0x7004, 0x9084, 0xff00, 0x9205, 0x9306, 0x1190,
+	0x2011, 0x0276, 0x20a9, 0x0004, 0x9d98, 0x000a, 0x080c, 0x8a45,
+	0x1148, 0x2011, 0x027a, 0x20a9, 0x0004, 0x9d98, 0x0006, 0x080c,
+	0x8a45, 0x1100, 0x015e, 0x00ee, 0x003e, 0x002e, 0x0005, 0x00e6,
+	0x2071, 0x0260, 0x7034, 0x9086, 0x0014, 0x11a8, 0x7038, 0x9086,
+	0x0800, 0x1188, 0x703c, 0xd0ec, 0x0160, 0x9084, 0x0f00, 0x9086,
+	0x0100, 0x1138, 0x7054, 0xd0a4, 0x1110, 0xd0ac, 0x0110, 0x9006,
+	0x0010, 0x9085, 0x0001, 0x00ee, 0x0005, 0x00e6, 0x00d6, 0x00c6,
+	0x0076, 0x0056, 0x0046, 0x0026, 0x0006, 0x0126, 0x2091, 0x8000,
+	0x2029, 0x12e5, 0x252c, 0x2021, 0x12eb, 0x2424, 0x2061, 0x15c0,
+	0x2071, 0x1100, 0x7244, 0x7064, 0x9202, 0x16f0, 0x080c, 0xaaf2,
+	0x05a0, 0x6720, 0x9786, 0x0001, 0x0580, 0x9786, 0x0007, 0x0568,
+	0x2500, 0x9c06, 0x0550, 0x2400, 0x9c06, 0x0538, 0x00c6, 0x6000,
+	0x9086, 0x0004, 0x1110, 0x080c, 0x12c7, 0x9786, 0x0008, 0x1148,
+	0x080c, 0x97cd, 0x1130, 0x00ce, 0x080c, 0x8576, 0x080c, 0x97a3,
+	0x00a0, 0x6014, 0x2068, 0x080c, 0x95d2, 0x0160, 0x9786, 0x0003,
+	0x11e8, 0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000, 0x080c, 0x50a5,
+	0x080c, 0x9797, 0x080c, 0x97a3, 0x00ce, 0x9ce0, 0x0018, 0x7058,
+	0x9c02, 0x1210, 0x0804, 0x89f2, 0x012e, 0x000e, 0x002e, 0x004e,
+	0x005e, 0x007e, 0x00ce, 0x00de, 0x00ee, 0x0005, 0x9786, 0x0006,
+	0x1118, 0x080c, 0xaa84, 0x0c30, 0x08e0, 0x220c, 0x2304, 0x9106,
+	0x1130, 0x8210, 0x8318, 0x1f04, 0x8a45, 0x9006, 0x0005, 0x2304,
+	0x9102, 0x0218, 0x2001, 0x0001, 0x0010, 0x2001, 0x0000, 0x918d,
+	0x0001, 0x0005, 0x0136, 0x01c6, 0x0016, 0x0026, 0x080c, 0x0d7e,
+	0x2100, 0x22e0, 0x9300, 0x2098, 0x3518, 0x20a9, 0x0001, 0x002e,
+	0x220c, 0x4002, 0x910e, 0x1140, 0x8210, 0x8319, 0x1dc8, 0x9006,
+	0x001e, 0x01ce, 0x013e, 0x0005, 0x220c, 0x9102, 0x0218, 0x2001,
+	0x0001, 0x0010, 0x2001, 0x0000, 0x918d, 0x0001, 0x001e, 0x01ce,
+	0x013e, 0x0005, 0x6004, 0x908a, 0x004c, 0x1a0c, 0x0cf1, 0x080c,
+	0x97bc, 0x0120, 0x080c, 0x97cd, 0x0168, 0x0028, 0x080c, 0x25d1,
+	0x080c, 0x97cd, 0x0138, 0x080c, 0x6c56, 0x080c, 0x7f1e, 0x080c,
+	0x6d42, 0x0005, 0x080c, 0x8576, 0x0cb0, 0x9182, 0x0040, 0x0002,
+	0x8ab3, 0x8ab3, 0x8ab3, 0x8ab3, 0x8ab3, 0x8ab3, 0x8ab3, 0x8ab3,
+	0x8ab3, 0x8ab3, 0x8ab3, 0x8ab5, 0x8ab5, 0x8ab5, 0x8ab5, 0x8ab3,
+	0x8ab3, 0x8ab3, 0x8ab5, 0x080c, 0x0cf1, 0x600b, 0xffff, 0x6003,
+	0x0001, 0x6106, 0x080c, 0x6886, 0x0126, 0x2091, 0x8000, 0x080c,
+	0x6d42, 0x012e, 0x0005, 0x9186, 0x0013, 0x1128, 0x6004, 0x9082,
+	0x0040, 0x0804, 0x8b4d, 0x9186, 0x0027, 0x11e8, 0x080c, 0x6c56,
+	0x080c, 0x25ad, 0x00d6, 0x6114, 0x2168, 0x080c, 0x95d2, 0x0168,
+	0x6867, 0x0103, 0x687b, 0x0029, 0x6877, 0x0000, 0x697c, 0xc1c5,
+	0x697e, 0x080c, 0x50a5, 0x080c, 0x9797, 0x00de, 0x080c, 0x7f1e,
+	0x080c, 0x6d42, 0x0005, 0x9186, 0x0014, 0x1120, 0x6004, 0x9082,
+	0x0040, 0x0418, 0x9186, 0x0046, 0x0138, 0x9186, 0x0045, 0x0120,
+	0x9186, 0x0048, 0x190c, 0x0cf1, 0x2001, 0x0109, 0x2004, 0xd084,
+	0x0198, 0x0126, 0x2091, 0x2800, 0x0006, 0x0016, 0x0026, 0x080c,
+	0x677e, 0x002e, 0x001e, 0x000e, 0x012e, 0xa001, 0x6000, 0x9086,
+	0x0002, 0x1110, 0x0804, 0x8b8c, 0x0005, 0x0002, 0x8b2b, 0x8b29,
+	0x8b29, 0x8b29, 0x8b29, 0x8b29, 0x8b29, 0x8b29, 0x8b29, 0x8b29,
+	0x8b29, 0x8b46, 0x8b46, 0x8b46, 0x8b46, 0x8b29, 0x8b46, 0x8b29,
+	0x8b46, 0x080c, 0x0cf1, 0x080c, 0x6c56, 0x00d6, 0x6114, 0x2168,
+	0x080c, 0x95d2, 0x0168, 0x6867, 0x0103, 0x687b, 0x0006, 0x6877,
+	0x0000, 0x6880, 0xc0ec, 0x6882, 0x080c, 0x50a5, 0x080c, 0x9797,
+	0x00de, 0x080c, 0x7f1e, 0x080c, 0x6d42, 0x0005, 0x080c, 0x6c56,
+	0x080c, 0x7f1e, 0x080c, 0x6d42, 0x0005, 0x0002, 0x8b63, 0x8b61,
+	0x8b61, 0x8b61, 0x8b61, 0x8b61, 0x8b61, 0x8b61, 0x8b61, 0x8b61,
+	0x8b61, 0x8b7a, 0x8b7a, 0x8b7a, 0x8b7a, 0x8b61, 0x8b85, 0x8b61,
+	0x8b7a, 0x080c, 0x0cf1, 0x00d6, 0x080c, 0x6c56, 0x6014, 0x2068,
+	0x2001, 0x12a8, 0x2004, 0x6042, 0x697c, 0xd1ac, 0x0140, 0x6003,
+	0x0004, 0x687c, 0x9085, 0x0400, 0x687e, 0x00de, 0x0005, 0x6003,
+	0x0002, 0x0cb8, 0x080c, 0x6c56, 0x2001, 0x12a8, 0x2004, 0x6042,
+	0x6003, 0x000f, 0x080c, 0x6d42, 0x0005, 0x080c, 0x6c56, 0x080c,
+	0x7f1e, 0x080c, 0x6d42, 0x0005, 0x9182, 0x0040, 0x0002, 0x8ba3,
+	0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3, 0x8ba5, 0x8c7a, 0x8ba3, 0x8ba3,
+	0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3, 0x8ba3,
+	0x8ba3, 0x8ba3, 0x8ca9, 0x080c, 0x0cf1, 0x00d6, 0x6114, 0x2168,
+	0x7644, 0x96b4, 0x0fff, 0x86ff, 0x1508, 0x6010, 0x2004, 0xd0bc,
+	0x1904, 0x8c65, 0x687b, 0x0000, 0x6867, 0x0103, 0x6e76, 0x687c,
+	0xd0ac, 0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x080c,
+	0x4ed6, 0x6210, 0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x7044, 0xd0e4,
+	0x1904, 0x8c4b, 0x080c, 0x7f1e, 0x00de, 0x0005, 0x968c, 0x0c00,
+	0x0148, 0x6010, 0x2004, 0xd0bc, 0x1904, 0x8c4f, 0x7348, 0x6b92,
+	0x734c, 0x6b8e, 0x968c, 0x00ff, 0x9186, 0x0002, 0x0508, 0x9186,
+	0x0028, 0x1118, 0x687b, 0x001c, 0x00e8, 0xd6dc, 0x01a0, 0x687b,
+	0x0015, 0x687c, 0xd0ac, 0x0170, 0x6938, 0x6a34, 0x2100, 0x9205,
+	0x0148, 0x7048, 0x9106, 0x1118, 0x734c, 0x9206, 0x0118, 0x6992,
+	0x6a8e, 0xc6dc, 0x0038, 0xd6d4, 0x0118, 0x687b, 0x0007, 0x0010,
+	0x687b, 0x0000, 0x6867, 0x0103, 0x6e76, 0x901e, 0xd6c4, 0x01d8,
+	0x9686, 0x0100, 0x1130, 0x7064, 0x9005, 0x1118, 0xc6c4, 0x0804,
+	0x8bab, 0x735c, 0x6b86, 0x83ff, 0x0170, 0x938a, 0x0009, 0x0210,
+	0x2019, 0x0008, 0x0036, 0x2308, 0x2019, 0x0018, 0x9d90, 0x0025,
+	0x080c, 0x927a, 0x003e, 0xd6cc, 0x0904, 0x8bbf, 0x7154, 0x698a,
+	0x81ff, 0x0904, 0x8bbf, 0x9192, 0x0021, 0x1268, 0x8304, 0x9098,
+	0x0018, 0x9d90, 0x0029, 0x080c, 0x927a, 0x2011, 0x0205, 0x2013,
+	0x0000, 0x0804, 0x8bbf, 0x6868, 0xd0fc, 0x0120, 0x2009, 0x0020,
+	0x698a, 0x0c60, 0x00f6, 0x2d78, 0x080c, 0x9219, 0x00fe, 0x080c,
+	0x926a, 0x0804, 0x8bc1, 0x080c, 0x987a, 0x0804, 0x8bcc, 0x687c,
+	0xd0ac, 0x0904, 0x8bd6, 0x6024, 0xd0dc, 0x1904, 0x8bd6, 0x6880,
+	0xd0bc, 0x1904, 0x8bd6, 0x7348, 0x6838, 0x9306, 0x11b8, 0x734c,
+	0x6834, 0x9306, 0x0904, 0x8bd6, 0x0088, 0x687c, 0xd0ac, 0x0904,
+	0x8bb2, 0x6838, 0x6934, 0x9105, 0x0904, 0x8bb2, 0x6024, 0xd0dc,
+	0x1904, 0x8bb2, 0x6880, 0xd0bc, 0x1904, 0x8bb2, 0x080c, 0x98aa,
+	0x0804, 0x8bcc, 0x00f6, 0x6003, 0x0003, 0x2079, 0x026c, 0x7c04,
+	0x7b00, 0x7e0c, 0x7d08, 0x6014, 0x2078, 0x787c, 0xd0ac, 0x0138,
+	0x6003, 0x0002, 0x00fe, 0x0005, 0x2130, 0x2228, 0x0058, 0x2400,
+	0x79ac, 0x910a, 0x2300, 0x7ab0, 0x9213, 0x2600, 0x9102, 0x2500,
+	0x9203, 0x0e90, 0x7c36, 0x7b3a, 0x7e46, 0x7d4a, 0x00fe, 0x6043,
+	0x0000, 0x2c10, 0x080c, 0x13a9, 0x080c, 0x68eb, 0x080c, 0x6e10,
+	0x0005, 0x0005, 0x9182, 0x0040, 0x0002, 0x8cc0, 0x8cc0, 0x8cc0,
+	0x8cc0, 0x8cc0, 0x8cc2, 0x8d54, 0x8cc0, 0x8cc0, 0x8d6a, 0x8dd2,
+	0x8cc0, 0x8cc0, 0x8cc0, 0x8cc0, 0x8de1, 0x8cc0, 0x8cc0, 0x8cc0,
+	0x080c, 0x0cf1, 0x0076, 0x00f6, 0x00e6, 0x00d6, 0x2071, 0x0260,
+	0x6114, 0x2178, 0x7644, 0x7e76, 0x96b4, 0x0fff, 0x7f7c, 0xc7e5,
+	0x7f7e, 0x6210, 0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x86ff, 0x0904,
+	0x8d4f, 0x9694, 0xff00, 0x9284, 0x0c00, 0x0120, 0x7048, 0x7892,
+	0x704c, 0x788e, 0x9284, 0x0300, 0x0904, 0x8d4f, 0x080c, 0x0ddf,
+	0x090c, 0x0cf1, 0x2d00, 0x787a, 0x7f7c, 0xc7cd, 0x7f7e, 0x6867,
+	0x0103, 0x7868, 0x686a, 0x786c, 0x686e, 0x7870, 0x6872, 0x6e76,
+	0x968c, 0x0c00, 0x0120, 0x7348, 0x6b92, 0x734c, 0x6b8e, 0x968c,
+	0x00ff, 0x9186, 0x0002, 0x0180, 0x9186, 0x0028, 0x1118, 0x687b,
+	0x001c, 0x0060, 0xd6dc, 0x0118, 0x687b, 0x0015, 0x0038, 0xd6d4,
+	0x0118, 0x687b, 0x0007, 0x0010, 0x687b, 0x0000, 0x6f7e, 0x7880,
+	0x6882, 0x7884, 0x6886, 0x901e, 0xd6c4, 0x0190, 0x735c, 0x6b86,
+	0x83ff, 0x0170, 0x938a, 0x0009, 0x0210, 0x2019, 0x0008, 0x0036,
+	0x2308, 0x2019, 0x0018, 0x9d90, 0x0025, 0x080c, 0x927a, 0x003e,
+	0xd6cc, 0x01e8, 0x7154, 0x698a, 0x81ff, 0x01c8, 0x9192, 0x0021,
+	0x1260, 0x8304, 0x9098, 0x0018, 0x9d90, 0x0029, 0x080c, 0x927a,
+	0x2011, 0x0205, 0x2013, 0x0000, 0x0050, 0x7868, 0xd0fc, 0x0120,
+	0x2009, 0x0020, 0x698a, 0x0c68, 0x2d78, 0x080c, 0x9219, 0x00de,
+	0x00ee, 0x00fe, 0x007e, 0x0005, 0x00f6, 0x6003, 0x0003, 0x2079,
+	0x026c, 0x7c04, 0x7b00, 0x7e0c, 0x7d08, 0x6014, 0x2078, 0x7c36,
+	0x7b3a, 0x7e46, 0x7d4a, 0x00fe, 0x2c10, 0x080c, 0x13a9, 0x080c,
+	0x76ee, 0x0005, 0x00d6, 0x2001, 0x12a8, 0x2004, 0x6042, 0x6003,
+	0x0002, 0x080c, 0x6cf2, 0x080c, 0x6e10, 0x6114, 0x2168, 0x697c,
+	0xd1e4, 0x0904, 0x8dcd, 0xd1cc, 0x0570, 0x6978, 0x6868, 0xd0fc,
+	0x0500, 0x0016, 0x687c, 0x0006, 0x6880, 0x0006, 0x9d90, 0x0019,
+	0x9198, 0x0019, 0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012,
+	0x8318, 0x8210, 0x1f04, 0x8d8e, 0x015e, 0x000e, 0x6882, 0x000e,
+	0x687e, 0x001e, 0x6874, 0x0006, 0x2168, 0x080c, 0x0e06, 0x001e,
+	0x0440, 0x0016, 0x080c, 0x0e06, 0x00de, 0x6974, 0x0016, 0x080c,
+	0x926a, 0x001e, 0x00f0, 0x6867, 0x0103, 0x6974, 0x9184, 0x00ff,
+	0x90b6, 0x0002, 0x0180, 0x9086, 0x0028, 0x1118, 0x687b, 0x001c,
+	0x0060, 0xd1dc, 0x0118, 0x687b, 0x0015, 0x0038, 0xd1d4, 0x0118,
+	0x687b, 0x0007, 0x0010, 0x687b, 0x0000, 0x0016, 0x080c, 0x4ed6,
+	0x001e, 0xd1e4, 0x1120, 0x080c, 0x7f1e, 0x00de, 0x0005, 0x080c,
+	0x987a, 0x0cd8, 0x2019, 0x0001, 0x080c, 0x7936, 0x6003, 0x0002,
+	0x2001, 0x12a8, 0x2004, 0x6042, 0x080c, 0x6cf2, 0x080c, 0x6e10,
+	0x0005, 0x080c, 0x6cf2, 0x080c, 0x25ad, 0x00d6, 0x6114, 0x2168,
+	0x080c, 0x95d2, 0x0150, 0x6867, 0x0103, 0x687b, 0x0029, 0x6877,
+	0x0000, 0x080c, 0x50a5, 0x080c, 0x9797, 0x00de, 0x080c, 0x7f1e,
+	0x080c, 0x6e10, 0x0005, 0x687b, 0x0015, 0xd1fc, 0x0138, 0x687b,
+	0x0007, 0x8002, 0x8000, 0x810a, 0x9189, 0x0000, 0x6992, 0x688e,
+	0x0005, 0x9182, 0x0040, 0x0002, 0x8e20, 0x8e20, 0x8e20, 0x8e20,
+	0x8e20, 0x8e22, 0x8e20, 0x8e20, 0x8ec0, 0x8e20, 0x8e20, 0x8e20,
+	0x8e20, 0x8e20, 0x8e20, 0x8e20, 0x8e20, 0x8e20, 0x8e20, 0x8fdc,
+	0x080c, 0x0cf1, 0x0076, 0x00f6, 0x00e6, 0x00d6, 0x2071, 0x0260,
+	0x6114, 0x2178, 0x7644, 0x7e76, 0x96b4, 0x0fff, 0x7f7c, 0xc7e5,
+	0x7f7e, 0x6210, 0x2268, 0x6a3c, 0x8211, 0x6a3e, 0x86ff, 0x0904,
+	0x8eb9, 0x9694, 0xff00, 0x9284, 0x0c00, 0x0120, 0x7048, 0x7892,
+	0x704c, 0x788e, 0x9284, 0x0300, 0x0904, 0x8eb9, 0x9686, 0x0100,
+	0x1130, 0x7064, 0x9005, 0x1118, 0xc6c4, 0x7e76, 0x0c38, 0x080c,
+	0x0ddf, 0x090c, 0x0cf1, 0x2d00, 0x787a, 0x7f7c, 0x97bd, 0x0200,
+	0x7f7e, 0x6867, 0x0103, 0x7868, 0x686a, 0x786c, 0x686e, 0x7870,
+	0x6872, 0x6e76, 0x968c, 0x0c00, 0x0120, 0x7348, 0x6b92, 0x734c,
+	0x6b8e, 0x968c, 0x00ff, 0x9186, 0x0002, 0x0180, 0x9186, 0x0028,
+	0x1118, 0x687b, 0x001c, 0x0060, 0xd6dc, 0x0118, 0x687b, 0x0015,
+	0x0038, 0xd6d4, 0x0118, 0x687b, 0x0007, 0x0010, 0x687b, 0x0000,
+	0x6f7e, 0x7880, 0x6882, 0x7884, 0x6886, 0x901e, 0xd6c4, 0x0190,
+	0x735c, 0x6b86, 0x83ff, 0x0170, 0x938a, 0x0009, 0x0210, 0x2019,
+	0x0008, 0x0036, 0x2308, 0x2019, 0x0018, 0x9d90, 0x0025, 0x080c,
+	0x927a, 0x003e, 0xd6cc, 0x01e8, 0x7154, 0x698a, 0x81ff, 0x01c8,
+	0x9192, 0x0021, 0x1260, 0x8304, 0x9098, 0x0018, 0x9d90, 0x0029,
+	0x080c, 0x927a, 0x2011, 0x0205, 0x2013, 0x0000, 0x0050, 0x7868,
+	0xd0fc, 0x0120, 0x2009, 0x0020, 0x698a, 0x0c68, 0x2d78, 0x080c,
+	0x9219, 0x080c, 0x12a4, 0x00de, 0x00ee, 0x00fe, 0x007e, 0x0005,
+	0x2001, 0x12a8, 0x2004, 0x6042, 0x00d6, 0x6114, 0x2168, 0x683c,
+	0x6940, 0x9105, 0x1118, 0x687c, 0xc0dc, 0x687e, 0x6003, 0x0002,
+	0x697c, 0xd1e4, 0x0904, 0x8fd7, 0x6043, 0x0000, 0x6010, 0x2004,
+	0xd0bc, 0x11f8, 0xd1cc, 0x0904, 0x8fa6, 0x6978, 0x6868, 0xd0fc,
+	0x0904, 0x8f69, 0x0016, 0x687c, 0x0006, 0x6880, 0x0006, 0x00f6,
+	0x2178, 0x7974, 0x9184, 0x00ff, 0x90b6, 0x0002, 0x0904, 0x8f3e,
+	0x9086, 0x0028, 0x15b8, 0x687b, 0x001c, 0x787b, 0x001c, 0x0804,
+	0x8f46, 0x6024, 0xd0f4, 0x11d0, 0x6838, 0x6a34, 0x9205, 0x09d0,
+	0x6838, 0x6a90, 0x9206, 0x1120, 0x688c, 0x6a34, 0x9206, 0x0990,
+	0x6024, 0xd0d4, 0x1148, 0x69ac, 0x6834, 0x9102, 0x603a, 0x69b0,
+	0x6838, 0x9103, 0x603e, 0x6024, 0xc0f5, 0x6026, 0x6010, 0x00d6,
+	0x2068, 0x683c, 0x8000, 0x683e, 0x00de, 0x687c, 0xc0e4, 0x687e,
+	0x6877, 0x0000, 0x6893, 0x0000, 0x688f, 0x0000, 0x080c, 0x98aa,
+	0x0804, 0x8fd7, 0xd1dc, 0x0158, 0x687b, 0x0015, 0x787b, 0x0015,
+	0x080c, 0x9a64, 0x0118, 0x7974, 0xc1dc, 0x7976, 0x0078, 0xd1d4,
+	0x0128, 0x687b, 0x0007, 0x787b, 0x0007, 0x0040, 0x687c, 0xd0ac,
+	0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x6878, 0x787a,
+	0x6890, 0x7892, 0x688c, 0x788e, 0x9d90, 0x0019, 0x9f98, 0x0019,
+	0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012, 0x8318, 0x8210,
+	0x1f04, 0x8f54, 0x015e, 0x00fe, 0x000e, 0x6882, 0x000e, 0x687e,
+	0x001e, 0x6874, 0x0006, 0x2168, 0x080c, 0x0e06, 0x001e, 0x0804,
+	0x8fd3, 0x0016, 0x00f6, 0x2178, 0x7974, 0x9184, 0x00ff, 0x90b6,
+	0x0002, 0x01e0, 0x9086, 0x0028, 0x1128, 0x687b, 0x001c, 0x787b,
+	0x001c, 0x00e0, 0xd1dc, 0x0158, 0x687b, 0x0015, 0x787b, 0x0015,
+	0x080c, 0x9a64, 0x0118, 0x7974, 0xc1dc, 0x7976, 0x0078, 0xd1d4,
+	0x0128, 0x687b, 0x0007, 0x787b, 0x0007, 0x0040, 0x687c, 0xd0ac,
+	0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x6890, 0x7892,
+	0x688c, 0x788e, 0x687c, 0x787e, 0x00fe, 0x080c, 0x0e06, 0x00de,
+	0x6974, 0x0016, 0x080c, 0x926a, 0x001e, 0x0468, 0x6867, 0x0103,
+	0x6974, 0x9184, 0x00ff, 0x90b6, 0x0002, 0x01b0, 0x9086, 0x0028,
+	0x1118, 0x687b, 0x001c, 0x00d0, 0xd1dc, 0x0148, 0x687b, 0x0015,
+	0x080c, 0x9a64, 0x0118, 0x6974, 0xc1dc, 0x6976, 0x0078, 0xd1d4,
+	0x0118, 0x687b, 0x0007, 0x0050, 0x687b, 0x0000, 0x687c, 0xd0ac,
+	0x0128, 0x6834, 0x6938, 0x9115, 0x190c, 0x8dfb, 0x6974, 0x0016,
+	0x080c, 0x4ed6, 0x001e, 0xd1e4, 0x1120, 0x080c, 0x7f1e, 0x00de,
+	0x0005, 0x080c, 0x987a, 0x0cd8, 0x0005, 0x080c, 0x6c56, 0x0010,
+	0x080c, 0x6cf2, 0x080c, 0x95d2, 0x01c0, 0x00d6, 0x6114, 0x2168,
+	0x6867, 0x0103, 0x2009, 0x110c, 0x210c, 0xd18c, 0x11c0, 0xd184,
+	0x1198, 0x6108, 0x697a, 0x918e, 0x0029, 0x1110, 0x080c, 0xad5f,
+	0x6877, 0x0000, 0x080c, 0x50a5, 0x00de, 0x080c, 0x7f1e, 0x080c,
+	0x6d42, 0x080c, 0x6e10, 0x0005, 0x687b, 0x0004, 0x0c88, 0x687b,
+	0x0004, 0x0c70, 0x9182, 0x0040, 0x0002, 0x9020, 0x9020, 0x9020,
+	0x9020, 0x9020, 0x9022, 0x9020, 0x9025, 0x9020, 0x9020, 0x9020,
+	0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020, 0x9020,
+	0x080c, 0x0cf1, 0x080c, 0x7f1e, 0x0005, 0x0006, 0x0026, 0x9016,
+	0x080c, 0x119a, 0x002e, 0x000e, 0x0005, 0x9182, 0x0085, 0x0002,
+	0x903d, 0x903b, 0x903b, 0x9049, 0x903b, 0x903b, 0x903b, 0x903b,
+	0x903b, 0x903b, 0x903b, 0x080c, 0x0cf1, 0x6003, 0x0001, 0x6106,
+	0x080c, 0x6886, 0x0126, 0x2091, 0x8000, 0x080c, 0x6d42, 0x012e,
+	0x0005, 0x0026, 0x0056, 0x00d6, 0x00e6, 0x2071, 0x0260, 0x7224,
+	0x6216, 0x7220, 0x080c, 0x95c2, 0x01a0, 0x2268, 0x6800, 0x9086,
+	0x0000, 0x0178, 0x6010, 0x6d10, 0x952e, 0x1158, 0x00c6, 0x2d60,
+	0x080c, 0x9297, 0x00ce, 0x0128, 0x6803, 0x0002, 0x6007, 0x0086,
+	0x0010, 0x6007, 0x0087, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c,
+	0x6d42, 0x9280, 0x0004, 0x2004, 0xd0bc, 0x0150, 0x6824, 0xd0ec,
+	0x0138, 0x00c6, 0x2260, 0x6043, 0x0000, 0x080c, 0x98aa, 0x00ce,
+	0x00ee, 0x00de, 0x005e, 0x002e, 0x0005, 0x9186, 0x0013, 0x1160,
+	0x6004, 0x908a, 0x0085, 0x0a0c, 0x0cf1, 0x908a, 0x0090, 0x1a0c,
+	0x0cf1, 0x9082, 0x0085, 0x0072, 0x9186, 0x0027, 0x0120, 0x9186,
+	0x0014, 0x190c, 0x0cf1, 0x080c, 0x6c56, 0x080c, 0x97a3, 0x080c,
+	0x6d42, 0x0005, 0x90ad, 0x90af, 0x90af, 0x90ad, 0x90ad, 0x90ad,
+	0x90ad, 0x90ad, 0x90ad, 0x90ad, 0x90ad, 0x080c, 0x0cf1, 0x080c,
+	0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0x9186, 0x0013,
+	0x1128, 0x6004, 0x9082, 0x0085, 0x2008, 0x04a8, 0x9186, 0x0027,
+	0x11e8, 0x080c, 0x6c56, 0x080c, 0x25ad, 0x00d6, 0x6014, 0x2068,
+	0x080c, 0x95d2, 0x0150, 0x6867, 0x0103, 0x6877, 0x0000, 0x687b,
+	0x0029, 0x080c, 0x50a5, 0x080c, 0x9797, 0x00de, 0x080c, 0x7f1e,
+	0x080c, 0x6d42, 0x0005, 0x080c, 0x7f68, 0x0ce0, 0x9186, 0x0014,
+	0x1dd0, 0x080c, 0x6c56, 0x00d6, 0x6014, 0x2068, 0x080c, 0x95d2,
+	0x0d60, 0x6867, 0x0103, 0x6877, 0x0000, 0x687b, 0x0006, 0x6880,
+	0xc0ec, 0x6882, 0x08f0, 0x0002, 0x9101, 0x90ff, 0x90ff, 0x90ff,
+	0x90ff, 0x90ff, 0x9119, 0x90ff, 0x90ff, 0x90ff, 0x90ff, 0x080c,
+	0x0cf1, 0x080c, 0x6c56, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186,
+	0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12a6, 0x0010,
+	0x2001, 0x12a7, 0x2004, 0x601a, 0x6003, 0x000c, 0x080c, 0x6d42,
+	0x0005, 0x080c, 0x6c56, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186,
+	0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12a6, 0x0010,
+	0x2001, 0x12a7, 0x2004, 0x601a, 0x6003, 0x000e, 0x080c, 0x6d42,
+	0x0005, 0x9182, 0x0090, 0x1220, 0x9182, 0x0085, 0x0208, 0x001a,
+	0x080c, 0x7f68, 0x0005, 0x9146, 0x9146, 0x9146, 0x9146, 0x9148,
+	0x919b, 0x9146, 0x9146, 0x9146, 0x9146, 0x9146, 0x080c, 0x0cf1,
+	0x00d6, 0x6010, 0x2004, 0xd0bc, 0x0168, 0x6034, 0x908c, 0xff00,
+	0x810f, 0x9186, 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x00de,
+	0x0804, 0x91ac, 0x080c, 0x9797, 0x080c, 0x95d2, 0x01c8, 0x6014,
+	0x2068, 0x6867, 0x0103, 0x6880, 0xd0b4, 0x0128, 0x687b, 0x0006,
+	0xc0ec, 0x6882, 0x0048, 0xd0bc, 0x0118, 0x687b, 0x0002, 0x0020,
+	0x687b, 0x0005, 0x080c, 0x9849, 0x6877, 0x0000, 0x080c, 0x50a5,
+	0x2c68, 0x080c, 0x7ec8, 0x01d0, 0x6003, 0x0001, 0x6007, 0x001e,
+	0x600b, 0xffff, 0x2009, 0x026e, 0x210c, 0x613a, 0x2009, 0x026f,
+	0x210c, 0x613e, 0x6910, 0x6112, 0x080c, 0x99cc, 0x6954, 0x6156,
+	0x6023, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x2d60, 0x080c,
+	0x7f1e, 0x00de, 0x0005, 0x6010, 0x2004, 0xd0bc, 0x0598, 0x6034,
+	0x908c, 0xff00, 0x810f, 0x9186, 0x0035, 0x0130, 0x9186, 0x001e,
+	0x0118, 0x9186, 0x0039, 0x1530, 0x00d6, 0x2c68, 0x080c, 0x9ac5,
+	0x1904, 0x91f1, 0x080c, 0x7ec8, 0x01d8, 0x6106, 0x6003, 0x0001,
+	0x6023, 0x0001, 0x6910, 0x6112, 0x692c, 0x612e, 0x6930, 0x6132,
+	0x6934, 0x918c, 0x00ff, 0x6136, 0x6938, 0x613a, 0x693c, 0x613e,
+	0x6954, 0x6156, 0x080c, 0x99cc, 0x080c, 0x6886, 0x080c, 0x6d42,
+	0x2d60, 0x00f8, 0x00d6, 0x6014, 0x2068, 0x080c, 0x95d2, 0x01c8,
+	0x6867, 0x0103, 0x6880, 0xd0b4, 0x0128, 0xc0ec, 0x6882, 0x687b,
+	0x0006, 0x0048, 0xd0bc, 0x0118, 0x687b, 0x0002, 0x0020, 0x687b,
+	0x0005, 0x080c, 0x9849, 0x6877, 0x0000, 0x080c, 0x50a5, 0x080c,
+	0x9797, 0x00de, 0x080c, 0x7f1e, 0x0005, 0x0016, 0x00d6, 0x6014,
+	0x2068, 0x080c, 0x95d2, 0x0140, 0x6867, 0x0103, 0x687b, 0x0028,
+	0x6877, 0x0000, 0x080c, 0x50a5, 0x00de, 0x001e, 0x9186, 0x0013,
+	0x0148, 0x9186, 0x0014, 0x0130, 0x9186, 0x0027, 0x0118, 0x080c,
+	0x7f68, 0x0030, 0x080c, 0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42,
+	0x0005, 0x0056, 0x0066, 0x00d6, 0x00f6, 0x2029, 0x0001, 0x9182,
+	0x0101, 0x1208, 0x0010, 0x2009, 0x0100, 0x2130, 0x8304, 0x9098,
+	0x0018, 0x2009, 0x0020, 0x9f90, 0x0029, 0x080c, 0x927a, 0x96b2,
+	0x0020, 0x7804, 0x906d, 0x0110, 0x080c, 0x0e06, 0x080c, 0x0ddf,
+	0x0520, 0x8528, 0x6867, 0x0110, 0x686b, 0x0000, 0x2d20, 0x7c06,
+	0x968a, 0x003d, 0x1228, 0x2608, 0x9d90, 0x001b, 0x0499, 0x00a8,
+	0x96b2, 0x003c, 0x2009, 0x003c, 0x2d78, 0x9d90, 0x001b, 0x0451,
+	0x0c28, 0x2079, 0x0200, 0x7817, 0x0000, 0x00fe, 0x852f, 0x95ad,
+	0x0003, 0x7d66, 0x95ac, 0x0000, 0x0048, 0x2079, 0x0200, 0x7817,
+	0x0000, 0x00fe, 0x852f, 0x95ad, 0x0003, 0x7d66, 0x00de, 0x006e,
+	0x005e, 0x0005, 0x00f6, 0x8dff, 0x0158, 0x6804, 0x907d, 0x0130,
+	0x6807, 0x0000, 0x080c, 0x50a5, 0x2f68, 0x0cb8, 0x080c, 0x50a5,
+	0x00fe, 0x0005, 0x00f6, 0x0156, 0x2079, 0x0200, 0x9184, 0x0001,
+	0x0108, 0x8108, 0x810c, 0x21a8, 0x2300, 0x9e00, 0x2004, 0x8007,
+	0x2012, 0x8318, 0x9386, 0x0020, 0x1120, 0x2018, 0x7814, 0x8000,
+	0x7816, 0x8210, 0x1f04, 0x9284, 0x015e, 0x00fe, 0x0005, 0x0066,
+	0x0126, 0x2091, 0x8000, 0x2031, 0x0001, 0x6020, 0x9084, 0x000f,
+	0x0083, 0x012e, 0x006e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0066,
+	0x2031, 0x0000, 0x6020, 0x9084, 0x000f, 0x001b, 0x006e, 0x012e,
+	0x0005, 0x92d1, 0x92d1, 0x92cc, 0x92f3, 0x92bf, 0x92cc, 0x92f3,
+	0x92cc, 0x92bf, 0x92bf, 0x92cc, 0x92cc, 0x92cc, 0x92bf, 0x080c,
+	0x0cf1, 0x0036, 0x2019, 0x0010, 0x080c, 0xa6bc, 0x6023, 0x0006,
+	0x6003, 0x0007, 0x003e, 0x0005, 0x9006, 0x0005, 0x9085, 0x0001,
+	0x0005, 0x00d6, 0x86ff, 0x11d8, 0x6014, 0x2068, 0x080c, 0x95d2,
+	0x01c0, 0x6864, 0x9086, 0x0139, 0x1128, 0x687b, 0x0005, 0x6883,
+	0x0000, 0x0028, 0x900e, 0x2001, 0x0005, 0x080c, 0x52a0, 0x080c,
+	0x9849, 0x080c, 0x50a5, 0x080c, 0x7f1e, 0x9085, 0x0001, 0x00de,
+	0x0005, 0x9006, 0x0ce0, 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0cf1,
+	0x000b, 0x0005, 0x930a, 0x932b, 0x930c, 0x934a, 0x9328, 0x930a,
+	0x92cc, 0x92d1, 0x92d1, 0x92cc, 0x92cc, 0x92cc, 0x92cc, 0x92cc,
+	0x92cc, 0x92cc, 0x080c, 0x0cf1, 0x86ff, 0x11b8, 0x6020, 0x9086,
+	0x0006, 0x0198, 0x00d6, 0x6014, 0x2068, 0x080c, 0x95d2, 0x0110,
+	0x080c, 0x9849, 0x00de, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023,
+	0x0002, 0x080c, 0x6886, 0x080c, 0x6d42, 0x9085, 0x0001, 0x0005,
+	0x080c, 0x12c7, 0x0c08, 0x00e6, 0x2071, 0x12dc, 0x7024, 0x9c06,
+	0x1110, 0x080c, 0x78b3, 0x6020, 0x9084, 0x000f, 0x9086, 0x0006,
+	0x1150, 0x0086, 0x0096, 0x2049, 0x0001, 0x2c40, 0x080c, 0x7a48,
+	0x009e, 0x008e, 0x0010, 0x080c, 0x77d3, 0x00ee, 0x1928, 0x080c,
+	0x92cc, 0x0005, 0x0036, 0x00e6, 0x2071, 0x12dc, 0x703c, 0x9c06,
+	0x1140, 0x2019, 0x0000, 0x080c, 0x7936, 0x00ee, 0x003e, 0x0804,
+	0x930c, 0x080c, 0x7b66, 0x00ee, 0x003e, 0x1904, 0x930c, 0x080c,
+	0x92cc, 0x0005, 0x00c6, 0x6020, 0x9084, 0x000f, 0x0013, 0x00ce,
+	0x0005, 0x937e, 0x9402, 0x9530, 0x9389, 0x97a3, 0x937e, 0xa6ae,
+	0x7f1e, 0x9402, 0x9377, 0x959b, 0x9377, 0x9377, 0x9377, 0x080c,
+	0x0cf1, 0x080c, 0x97cd, 0x1110, 0x080c, 0x8576, 0x0005, 0x080c,
+	0x6c56, 0x080c, 0x6d42, 0x080c, 0x7f1e, 0x0005, 0x601b, 0x0001,
+	0x0005, 0x6014, 0x9080, 0x0025, 0x2c02, 0x6000, 0x908a, 0x0016,
+	0x1a0c, 0x0cf1, 0x000b, 0x0005, 0x93a4, 0x93a6, 0x93c6, 0x93d8,
+	0x93e5, 0x93a4, 0x937e, 0x937e, 0x937e, 0x93d8, 0x93d8, 0x93a4,
+	0x93a4, 0x93a4, 0x93a4, 0x93e2, 0x080c, 0x0cf1, 0x00e6, 0x6014,
+	0x2070, 0x7080, 0xc0b5, 0x7082, 0x2071, 0x12dc, 0x7024, 0x9c06,
+	0x0190, 0x080c, 0x77d3, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023,
+	0x0002, 0x2001, 0x12a7, 0x2004, 0x601a, 0x080c, 0x6886, 0x080c,
+	0x6d42, 0x00ee, 0x0005, 0x601b, 0x0001, 0x0cd8, 0x00d6, 0x6014,
+	0x2068, 0x6880, 0xc0b5, 0x6882, 0x00de, 0x6007, 0x0085, 0x6003,
+	0x000b, 0x6023, 0x0002, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0005,
+	0x00d6, 0x601b, 0x0001, 0x6014, 0x2068, 0x6880, 0xc0b5, 0x6882,
+	0x00de, 0x0005, 0x080c, 0x7f1e, 0x0005, 0x6014, 0x9005, 0x01b8,
+	0x9088, 0x001f, 0x210c, 0xd1e4, 0x0190, 0x9080, 0x0021, 0x2004,
+	0x601a, 0x2001, 0x0037, 0x2c08, 0x080c, 0x113b, 0x6000, 0x9086,
+	0x0004, 0x1120, 0x2009, 0x0048, 0x080c, 0x7f4e, 0x0005, 0x080c,
+	0x12c7, 0x0820, 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0cf1, 0x000b,
+	0x0005, 0x9419, 0x9386, 0x941b, 0x9419, 0x941b, 0x941b, 0x937f,
+	0x9419, 0x9379, 0x9379, 0x9419, 0x9419, 0x9419, 0x9419, 0x9419,
+	0x9419, 0x080c, 0x0cf1, 0x6010, 0x00d6, 0x2068, 0x6804, 0x9084,
+	0x00ff, 0x00de, 0x908a, 0x000c, 0x1a0c, 0x0cf1, 0x000b, 0x0005,
+	0x9434, 0x94d6, 0x9436, 0x9470, 0x9436, 0x9470, 0x9436, 0x9440,
+	0x9434, 0x9470, 0x9434, 0x945c, 0x080c, 0x0cf1, 0x6004, 0x908e,
+	0x0016, 0x0588, 0x908e, 0x0004, 0x0570, 0x908e, 0x0002, 0x0558,
+	0x6004, 0x080c, 0x97cd, 0x0904, 0x94ef, 0x908e, 0x0021, 0x0904,
+	0x94f3, 0x908e, 0x0022, 0x0904, 0x94ef, 0x908e, 0x003d, 0x0904,
+	0x94f3, 0x908e, 0x0039, 0x0904, 0x94f7, 0x908e, 0x0035, 0x0904,
+	0x94f7, 0x908e, 0x001e, 0x0188, 0x908e, 0x0001, 0x1150, 0x6010,
+	0x00d6, 0x2068, 0x6804, 0x9084, 0x00ff, 0x00de, 0x9086, 0x0006,
+	0x0110, 0x080c, 0x25ad, 0x080c, 0x8576, 0x080c, 0x97a3, 0x0005,
+	0x00c6, 0x00d6, 0x6104, 0x9186, 0x0016, 0x0904, 0x94c7, 0x9186,
+	0x0002, 0x1518, 0x6010, 0x2068, 0x2001, 0x1133, 0x2004, 0xd0ac,
+	0x1904, 0x9519, 0x68a0, 0xd0bc, 0x1904, 0x9519, 0x6840, 0x9084,
+	0x00ff, 0x9005, 0x0190, 0x8001, 0x6842, 0x6017, 0x0000, 0x6023,
+	0x0007, 0x601b, 0x0398, 0x6043, 0x0000, 0x080c, 0x7ec8, 0x0128,
+	0x2d00, 0x6012, 0x6023, 0x0001, 0x0450, 0x00de, 0x00ce, 0x6004,
+	0x908e, 0x0002, 0x11a8, 0x6010, 0x9080, 0x0028, 0x2004, 0x9086,
+	0x007e, 0x1170, 0x2009, 0x1133, 0x2104, 0xc085, 0x200a, 0x00e6,
+	0x2071, 0x1100, 0x080c, 0x46bb, 0x00ee, 0x080c, 0x8576, 0x0020,
+	0x080c, 0x8576, 0x080c, 0x25ad, 0x00e6, 0x0126, 0x2091, 0x8000,
+	0x080c, 0x25d1, 0x012e, 0x00ee, 0x080c, 0x97a3, 0x0005, 0x2001,
+	0x0002, 0x080c, 0x4ab3, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c,
+	0x68ce, 0x080c, 0x6d42, 0x00de, 0x00ce, 0x0c80, 0x00c6, 0x00d6,
+	0x6104, 0x9186, 0x0016, 0x0d58, 0x6010, 0x2068, 0x6840, 0x9084,
+	0x00ff, 0x9005, 0x0904, 0x949d, 0x8001, 0x6842, 0x6003, 0x0001,
+	0x080c, 0x68ce, 0x080c, 0x6d42, 0x00de, 0x00ce, 0x08b8, 0x080c,
+	0x8576, 0x0804, 0x946d, 0x080c, 0x85a4, 0x0804, 0x946d, 0x00d6,
+	0x2c68, 0x6104, 0x080c, 0x9ac5, 0x00de, 0x0118, 0x080c, 0x7f1e,
+	0x00b8, 0x6004, 0x8007, 0x6134, 0x918c, 0x00ff, 0x9105, 0x6036,
+	0x6007, 0x0085, 0x6003, 0x000b, 0x6023, 0x0002, 0x603c, 0x600a,
+	0x2001, 0x12a7, 0x2004, 0x601a, 0x080c, 0x6886, 0x080c, 0x6d42,
+	0x0005, 0x00de, 0x00ce, 0x080c, 0x8576, 0x080c, 0x25ad, 0x00e6,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x25d1, 0x6017, 0x0000, 0x6023,
+	0x0007, 0x601b, 0x0398, 0x6043, 0x0000, 0x012e, 0x00ee, 0x0005,
+	0x6000, 0x908a, 0x0016, 0x1a0c, 0x0cf1, 0x000b, 0x0005, 0x9547,
+	0x9547, 0x9547, 0x9547, 0x9547, 0x9547, 0x9547, 0x9547, 0x9547,
+	0x937e, 0x9547, 0x9386, 0x9549, 0x9386, 0x9556, 0x9547, 0x080c,
+	0x0cf1, 0x6004, 0x9086, 0x008b, 0x0148, 0x6007, 0x008b, 0x6003,
+	0x000d, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0005, 0x080c, 0x9797,
+	0x080c, 0x95d2, 0x0580, 0x080c, 0x25ad, 0x00d6, 0x080c, 0x95d2,
+	0x0168, 0x6014, 0x2068, 0x6867, 0x0103, 0x687b, 0x0006, 0x6877,
+	0x0000, 0x6880, 0xc0ed, 0x6882, 0x080c, 0x50a5, 0x2c68, 0x080c,
+	0x7ec8, 0x0150, 0x6810, 0x6012, 0x080c, 0x99cc, 0x00c6, 0x2d60,
+	0x080c, 0x97a3, 0x00ce, 0x0008, 0x2d60, 0x00de, 0x6017, 0x0000,
+	0x6023, 0x0001, 0x6007, 0x0001, 0x6003, 0x0001, 0x080c, 0x68ce,
+	0x080c, 0x6d42, 0x0078, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186,
+	0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x080c, 0x25ad, 0x08b0,
+	0x080c, 0x97a3, 0x0005, 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0cf1,
+	0x000b, 0x0005, 0x95b2, 0x95b2, 0x95b2, 0x95b4, 0x95b5, 0x95b2,
+	0x95b2, 0x95b2, 0x95b2, 0x95b2, 0x95b2, 0x95b2, 0x95b2, 0x95b2,
+	0x95b2, 0x95b2, 0x080c, 0x0cf1, 0x0005, 0x080c, 0x7b66, 0x190c,
+	0x0cf1, 0x6114, 0x2168, 0x687b, 0x0006, 0x080c, 0x50a5, 0x080c,
+	0x7f1e, 0x0005, 0x9284, 0x0007, 0x1158, 0x9282, 0x15c0, 0x0240,
+	0x2001, 0x1116, 0x2004, 0x9202, 0x1218, 0x9085, 0x0001, 0x0005,
+	0x9006, 0x0ce8, 0x0026, 0x6214, 0x9294, 0xf000, 0x002e, 0x0005,
+	0x00e6, 0x00c6, 0x0036, 0x0006, 0x0126, 0x2091, 0x8000, 0x2061,
+	0x15c0, 0x2071, 0x1100, 0x7344, 0x7064, 0x9302, 0x12a8, 0x6020,
+	0x9206, 0x1160, 0x080c, 0x9946, 0x0148, 0x080c, 0x97cd, 0x1110,
+	0x080c, 0x8576, 0x00c6, 0x080c, 0x7f1e, 0x00ce, 0x9ce0, 0x0018,
+	0x7058, 0x9c02, 0x1208, 0x0c38, 0x012e, 0x000e, 0x003e, 0x00ce,
+	0x00ee, 0x0005, 0x00e6, 0x00c6, 0x0016, 0x9188, 0x1000, 0x210c,
+	0x81ff, 0x0170, 0x2061, 0x15c0, 0x2071, 0x1100, 0x0016, 0x080c,
+	0x7ec8, 0x001e, 0x0138, 0x6112, 0x080c, 0x25ad, 0x080c, 0x7f1e,
+	0x9006, 0x0010, 0x9085, 0x0001, 0x001e, 0x00ce, 0x00ee, 0x0005,
+	0x00c6, 0x0056, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x7ec8,
+	0x005e, 0x0180, 0x6616, 0x6512, 0x080c, 0x99cc, 0x6023, 0x0003,
+	0x2009, 0x004b, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x012e, 0x005e,
+	0x00ce, 0x0005, 0x9006, 0x0cd0, 0x00c6, 0x0056, 0x0126, 0x2091,
+	0x8000, 0x62a0, 0x00c6, 0x080c, 0x7ec8, 0x005e, 0x01f8, 0x6017,
+	0x0000, 0x6512, 0x080c, 0x99cc, 0x6023, 0x0003, 0x00c6, 0x2560,
+	0x00ce, 0x080c, 0x69ca, 0x0076, 0x2039, 0x0000, 0x080c, 0x68fe,
+	0x2c08, 0x080c, 0xa85f, 0x007e, 0x2009, 0x004c, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x005e, 0x00ce, 0x0005, 0x9006, 0x0cd0,
+	0x00f6, 0x00c6, 0x0046, 0x00c6, 0x080c, 0x7ec8, 0x2c78, 0x00ce,
+	0x0180, 0x7e16, 0x2c00, 0x7812, 0x7823, 0x0003, 0x2021, 0x0005,
+	0x080c, 0x96bd, 0x2f60, 0x2009, 0x004d, 0x080c, 0x7f4e, 0x9085,
+	0x0001, 0x004e, 0x00ce, 0x00fe, 0x0005, 0x00f6, 0x00c6, 0x0046,
+	0x00c6, 0x080c, 0x7ec8, 0x2c78, 0x00ce, 0x0178, 0x7e16, 0x2c00,
+	0x7812, 0x7823, 0x0003, 0x2021, 0x0005, 0x0439, 0x2f60, 0x2009,
+	0x004e, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x004e, 0x00ce, 0x00fe,
+	0x0005, 0x00f6, 0x00c6, 0x0046, 0x00c6, 0x080c, 0x7ec8, 0x2c78,
+	0x00ce, 0x0178, 0x7e16, 0x2c00, 0x7812, 0x7823, 0x0003, 0x2021,
+	0x0004, 0x0059, 0x2f60, 0x2009, 0x0052, 0x080c, 0x7f4e, 0x9085,
+	0x0001, 0x004e, 0x00ce, 0x00fe, 0x0005, 0x0096, 0x0076, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x4c77, 0x0158, 0x2001, 0x96c2, 0x0006,
+	0x900e, 0x2400, 0x080c, 0x52a0, 0x080c, 0x50a5, 0x000e, 0x0807,
+	0x2418, 0x080c, 0x6bf8, 0x62a0, 0x0086, 0x2041, 0x0001, 0x2039,
+	0x0001, 0x2608, 0x080c, 0x69e3, 0x008e, 0x080c, 0x68fe, 0x2f08,
+	0x2648, 0x080c, 0xa85f, 0x613c, 0x81ff, 0x090c, 0x6a8c, 0x012e,
+	0x007e, 0x009e, 0x0005, 0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6,
+	0x080c, 0x7ec8, 0x001e, 0x0188, 0x660a, 0x6112, 0x080c, 0x99cc,
+	0x6023, 0x0001, 0x2d00, 0x6016, 0x2009, 0x001f, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x00c6,
+	0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x7ec8, 0x001e, 0x01b0,
+	0x660a, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0008, 0x2d00, 0x6016,
+	0x00f6, 0x2c78, 0x080c, 0x119d, 0x00fe, 0x2009, 0x0021, 0x080c,
+	0x7f4e, 0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x7ec8, 0x001e,
+	0x0188, 0x660a, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0001, 0x2d00,
+	0x6016, 0x2009, 0x003d, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x012e,
+	0x00ce, 0x0005, 0x9006, 0x0cd8, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x00c6, 0x080c, 0x984d, 0x001e, 0x0180, 0x6112, 0x080c, 0x99cc,
+	0x6023, 0x0001, 0x2d00, 0x6016, 0x2009, 0x0000, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x00c6,
+	0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x7ec8, 0x001e, 0x0188,
+	0x660a, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0001, 0x2d00, 0x6016,
+	0x2009, 0x0044, 0x080c, 0x7f4e, 0x9085, 0x0001, 0x012e, 0x00ce,
+	0x0005, 0x9006, 0x0cd8, 0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6,
+	0x080c, 0x7ec8, 0x001e, 0x0188, 0x660a, 0x6112, 0x080c, 0x99cc,
+	0x6023, 0x0001, 0x2d00, 0x6016, 0x2009, 0x0049, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x0026,
+	0x00d6, 0x6210, 0x2268, 0x6a3c, 0x82ff, 0x0110, 0x8211, 0x6a3e,
+	0x00de, 0x002e, 0x0005, 0x0006, 0x6000, 0x9086, 0x0000, 0x0190,
+	0x6017, 0x0000, 0x6023, 0x0007, 0x2001, 0x12a6, 0x2004, 0x0006,
+	0x9082, 0x0051, 0x000e, 0x0208, 0x8004, 0x601a, 0x080c, 0xad19,
+	0x6043, 0x0000, 0x000e, 0x0005, 0x0006, 0x0016, 0x6004, 0x908e,
+	0x0002, 0x0140, 0x908e, 0x0003, 0x0128, 0x908e, 0x0004, 0x0110,
+	0x9085, 0x0001, 0x001e, 0x000e, 0x0005, 0x0006, 0x00d6, 0x6014,
+	0x906d, 0x0148, 0x6864, 0x9086, 0x0139, 0x0138, 0x6868, 0xd0fc,
+	0x0110, 0x9006, 0x0010, 0x9085, 0x0001, 0x00de, 0x000e, 0x0005,
+	0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, 0x7ec8, 0x001e,
+	0x0190, 0x6112, 0x080c, 0x99cc, 0x6023, 0x0001, 0x2d00, 0x6016,
+	0x080c, 0x25ad, 0x2009, 0x0028, 0x080c, 0x7f4e, 0x9085, 0x0001,
+	0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x9186, 0x0015, 0x1188,
+	0x2011, 0x1120, 0x2204, 0x9086, 0x0074, 0x1158, 0x080c, 0x88ee,
+	0x6003, 0x0001, 0x6007, 0x0029, 0x080c, 0x68ce, 0x080c, 0x6d42,
+	0x0020, 0x080c, 0x8576, 0x080c, 0x7f1e, 0x0005, 0x9186, 0x0016,
+	0x1128, 0x2001, 0x0004, 0x080c, 0x4ab3, 0x00e8, 0x9186, 0x0015,
+	0x11e8, 0x2011, 0x1120, 0x2204, 0x9086, 0x0014, 0x11b8, 0x6010,
+	0x00d6, 0x2068, 0x080c, 0x4bf5, 0x00de, 0x080c, 0x89bf, 0x1170,
+	0x6010, 0x00d6, 0x2068, 0x6890, 0x00de, 0x9005, 0x0138, 0x2001,
+	0x0006, 0x080c, 0x4ab3, 0x080c, 0x80a0, 0x0020, 0x080c, 0x8576,
+	0x080c, 0x7f1e, 0x0005, 0x6878, 0x9086, 0x0005, 0x1108, 0x0009,
+	0x0005, 0x6880, 0xc0ad, 0x6882, 0x0005, 0x00e6, 0x0126, 0x2071,
+	0x1100, 0x2091, 0x8000, 0x7544, 0x9582, 0x0001, 0x0608, 0x7048,
+	0x2060, 0x6000, 0x9086, 0x0000, 0x0148, 0x9ce0, 0x0018, 0x7058,
+	0x9c02, 0x1208, 0x0cb0, 0x2061, 0x15c0, 0x0c98, 0x6003, 0x0008,
+	0x8529, 0x7546, 0x9ca8, 0x0018, 0x7058, 0x9502, 0x1230, 0x754a,
+	0x9085, 0x0001, 0x012e, 0x00ee, 0x0005, 0x704b, 0x15c0, 0x0cc0,
+	0x9006, 0x0cc0, 0x6043, 0x0000, 0x6017, 0x0000, 0x6003, 0x0001,
+	0x6007, 0x0050, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0005, 0x00c6,
+	0x6010, 0x2004, 0xd0bc, 0x0120, 0x6020, 0x9084, 0x000f, 0x0013,
+	0x00ce, 0x0005, 0x937e, 0x98a2, 0x98a5, 0x98a8, 0xab09, 0xab24,
+	0xab27, 0x937e, 0x937e, 0x937e, 0x937e, 0x937e, 0x937e, 0x937e,
+	0x080c, 0x0cf1, 0xa001, 0xa001, 0x0005, 0xa001, 0xa001, 0x0005,
+	0x0009, 0x0005, 0x6010, 0x2004, 0xd0bc, 0x0550, 0x00f6, 0x2c78,
+	0x080c, 0x7ec8, 0x1128, 0x2001, 0x12a8, 0x2004, 0x7842, 0x00f8,
+	0x7810, 0x6012, 0x080c, 0x99cc, 0x7820, 0x9086, 0x0003, 0x0128,
+	0x7808, 0x603a, 0x2f00, 0x603e, 0x0020, 0x7808, 0x603e, 0x2f00,
+	0x603a, 0x602e, 0x6023, 0x0001, 0x6007, 0x0035, 0x6003, 0x0001,
+	0x7954, 0x6156, 0x080c, 0x6886, 0x080c, 0x6d42, 0x2f60, 0x00fe,
+	0x0005, 0x0016, 0x00f6, 0x6830, 0x6036, 0x908e, 0x0001, 0x0148,
+	0x6803, 0x0002, 0x9086, 0x0005, 0x0168, 0x9006, 0x602e, 0x6032,
+	0x00c8, 0x681c, 0xc085, 0x681e, 0x6803, 0x0004, 0x6824, 0xc0f4,
+	0xc0d5, 0x6826, 0x6814, 0x2078, 0x78ac, 0x6938, 0x9102, 0x78b0,
+	0x693c, 0x9103, 0x1e50, 0x683c, 0x602e, 0x6838, 0x9084, 0xfffc,
+	0x683a, 0x6032, 0x2d00, 0x603a, 0x6808, 0x603e, 0x6910, 0x6112,
+	0x6954, 0x6156, 0x6023, 0x0001, 0x6007, 0x0039, 0x6003, 0x0001,
+	0x080c, 0x6886, 0x080c, 0x6d42, 0x00fe, 0x001e, 0x0005, 0x6024,
+	0xd0d4, 0x0510, 0xd0f4, 0x11f8, 0x6038, 0x940a, 0x603c, 0x9303,
+	0x0230, 0x9105, 0x0120, 0x6024, 0xc0d4, 0xc0f5, 0x0098, 0x643a,
+	0x633e, 0x6c3e, 0x6b42, 0x0046, 0x0036, 0x2400, 0x6cac, 0x9402,
+	0x6836, 0x2300, 0x6bb0, 0x9303, 0x683a, 0x003e, 0x004e, 0x6024,
+	0xc0d4, 0x0000, 0x6026, 0x0005, 0xd0f4, 0x1138, 0x683c, 0x603a,
+	0x6840, 0x603e, 0x6024, 0xc0f5, 0x6026, 0x0005, 0x0006, 0x0016,
+	0x6004, 0x908e, 0x0034, 0x01b8, 0x908e, 0x0035, 0x01a0, 0x908e,
+	0x0036, 0x0188, 0x908e, 0x0037, 0x0170, 0x908e, 0x0038, 0x0158,
+	0x908e, 0x0039, 0x0140, 0x908e, 0x003a, 0x0128, 0x908e, 0x003b,
+	0x0110, 0x9085, 0x0001, 0x001e, 0x000e, 0x0005, 0x0006, 0x0016,
+	0x0026, 0x0036, 0x00e6, 0x2001, 0x12a2, 0x200c, 0x8000, 0x2014,
+	0x2001, 0x0032, 0x080c, 0x66ff, 0x2001, 0x12a6, 0x82ff, 0x1110,
+	0x2011, 0x0002, 0x2202, 0x2001, 0x12a4, 0x200c, 0x8000, 0x2014,
+	0x2071, 0x127f, 0x711a, 0x721e, 0x2001, 0x0064, 0x080c, 0x66ff,
+	0x2001, 0x12a7, 0x82ff, 0x1110, 0x2011, 0x0002, 0x2202, 0x2001,
+	0x12a8, 0x9288, 0x000a, 0x2102, 0x2001, 0x1340, 0x2102, 0x2001,
+	0x0032, 0x080c, 0x113b, 0x080c, 0x4df8, 0x00ee, 0x003e, 0x002e,
+	0x001e, 0x000e, 0x0005, 0x0006, 0x0016, 0x00e6, 0x2001, 0x12a6,
+	0x2003, 0x0028, 0x2001, 0x12a7, 0x2003, 0x0014, 0x2071, 0x127f,
+	0x701b, 0x0000, 0x701f, 0x07d0, 0x2001, 0x12a8, 0x2009, 0x001e,
+	0x2102, 0x2001, 0x1340, 0x2102, 0x2001, 0x0032, 0x080c, 0x113b,
+	0x00ee, 0x001e, 0x000e, 0x0005, 0x00d6, 0x6058, 0x906d, 0x0110,
+	0x080c, 0x0df6, 0x00de, 0x0005, 0x0005, 0x00c6, 0x0126, 0x2091,
+	0x8000, 0x00c6, 0x080c, 0x7ec8, 0x001e, 0x0178, 0x6112, 0x0ca1,
+	0x6023, 0x0001, 0x2d00, 0x6016, 0x2009, 0x0033, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x00d6,
+	0x00e6, 0x00f6, 0x2071, 0x1100, 0x9186, 0x0015, 0x1500, 0x7080,
+	0x9086, 0x0018, 0x11e0, 0x6014, 0x2068, 0x6a3c, 0xd2e4, 0x1160,
+	0x2c78, 0x080c, 0x6f1c, 0x01d8, 0x706c, 0x6a50, 0x9206, 0x1160,
+	0x7070, 0x6a54, 0x9206, 0x1140, 0x6210, 0x9290, 0x0028, 0x2214,
+	0x2009, 0x0000, 0x080c, 0x25f0, 0x080c, 0x80a0, 0x0020, 0x080c,
+	0x8576, 0x080c, 0x7f1e, 0x00fe, 0x00ee, 0x00de, 0x0005, 0x7050,
+	0x6a54, 0x9206, 0x0d48, 0x0c80, 0x00c6, 0x0126, 0x2091, 0x8000,
+	0x00c6, 0x080c, 0x7ec8, 0x001e, 0x0180, 0x6112, 0x080c, 0x99cc,
+	0x6023, 0x0001, 0x2d00, 0x6016, 0x2009, 0x0043, 0x080c, 0x7f4e,
+	0x9085, 0x0001, 0x012e, 0x00ce, 0x0005, 0x9006, 0x0cd8, 0x00d6,
+	0x00e6, 0x00f6, 0x2071, 0x1100, 0x9186, 0x0015, 0x11c0, 0x7080,
+	0x9086, 0x0004, 0x11a0, 0x6014, 0x90e8, 0x001b, 0x2c78, 0x080c,
+	0x6f1c, 0x01a8, 0x706c, 0x6a08, 0x9206, 0x1130, 0x7070, 0x6a0c,
+	0x9206, 0x1110, 0x080c, 0x25ad, 0x080c, 0x80a0, 0x0020, 0x080c,
+	0x8576, 0x080c, 0x7f1e, 0x00fe, 0x00ee, 0x00de, 0x0005, 0x7050,
+	0x6a0c, 0x9206, 0x0d78, 0x0c80, 0x0016, 0x0026, 0x687c, 0xd0ac,
+	0x0178, 0x6938, 0x6a34, 0x2100, 0x9205, 0x0150, 0x6890, 0x9106,
+	0x1118, 0x688c, 0x9206, 0x0120, 0x6992, 0x6a8e, 0x9085, 0x0001,
+	0x002e, 0x001e, 0x0005, 0x00d6, 0x0036, 0x6314, 0x2368, 0x687a,
+	0x6982, 0x929e, 0x4000, 0x1560, 0x6310, 0x00c6, 0x2360, 0x2009,
+	0x0000, 0x6868, 0xd0f4, 0x1140, 0x080c, 0x4d21, 0x1108, 0xc185,
+	0x6000, 0xd0bc, 0x0108, 0xc18d, 0x6a96, 0x699a, 0x20a9, 0x0004,
+	0x20e1, 0x0001, 0x20e9, 0x0001, 0x9d80, 0x0031, 0x20a0, 0x9c80,
+	0x0006, 0x2098, 0x080c, 0x4678, 0x20a9, 0x0004, 0x9d80, 0x0035,
+	0x20a0, 0x9c80, 0x000a, 0x2098, 0x080c, 0x4678, 0x00ce, 0x0080,
+	0x6a96, 0x3918, 0x9398, 0x0006, 0x231c, 0x689b, 0x0004, 0x6ba2,
+	0x6310, 0x00c6, 0x2360, 0x6004, 0x00ce, 0x9084, 0x00ff, 0x689e,
+	0x080c, 0x50a5, 0x003e, 0x00de, 0x0005, 0x00c6, 0x0026, 0x0016,
+	0x9186, 0x0035, 0x0110, 0x6a38, 0x0008, 0x6a2c, 0x080c, 0x95c2,
+	0x01f0, 0x2260, 0x6120, 0x9186, 0x0003, 0x0118, 0x9186, 0x0006,
+	0x1190, 0x6838, 0x9206, 0x0140, 0x683c, 0x9206, 0x1160, 0x6108,
+	0x6838, 0x9106, 0x1140, 0x0020, 0x6008, 0x693c, 0x9106, 0x1118,
+	0x6010, 0x6910, 0x9106, 0x001e, 0x002e, 0x00ce, 0x0005, 0x9085,
+	0x0001, 0x0cc8, 0x0066, 0x6000, 0x90b2, 0x0016, 0x1a0c, 0x0cf1,
+	0x0013, 0x006e, 0x0005, 0x9b0b, 0x9fed, 0xa14f, 0x9b0b, 0x9b0b,
+	0x9b0b, 0x9b0b, 0x9b0b, 0x9b42, 0xa1cd, 0x9b0b, 0x9b0b, 0x9b0b,
+	0x9b0b, 0x9b0b, 0x9b0b, 0x080c, 0x0cf1, 0x0066, 0x6000, 0x90b2,
+	0x0016, 0x1a0c, 0x0cf1, 0x0013, 0x006e, 0x0005, 0x9b26, 0xa64b,
+	0x9b26, 0x9b26, 0x9b26, 0x9b26, 0x9b26, 0x9b26, 0xa60b, 0xa69b,
+	0x9b26, 0xac51, 0xac85, 0xac51, 0xac85, 0x9b26, 0x080c, 0x0cf1,
+	0x6000, 0x9082, 0x0016, 0x1a0c, 0x0cf1, 0x6000, 0x000a, 0x0005,
+	0x9b40, 0xa307, 0xa3dc, 0xa3fe, 0xa4a6, 0x9b40, 0xa57d, 0xa528,
+	0xa1d9, 0xa5e1, 0xa5f6, 0x9b40, 0x9b40, 0x9b40, 0x9b40, 0x9b40,
+	0x080c, 0x0cf1, 0x91b2, 0x004c, 0x1a0c, 0x0cf1, 0x2100, 0x91b2,
+	0x0040, 0x1a04, 0x9f4e, 0x0002, 0x9b8c, 0x9d57, 0x9b8c, 0x9b8c,
+	0x9b8c, 0x9d60, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c,
+	0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c,
+	0x9b8c, 0x9b8c, 0x9b8c, 0x9b8e, 0x9bea, 0x9bf9, 0x9c47, 0x9c65,
+	0x9ce3, 0x9d42, 0x9b8c, 0x9b8c, 0x9d63, 0x9b8c, 0x9b8c, 0x9d78,
+	0x9d85, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9b8c, 0x9dfd, 0x9b8c,
+	0x9b8c, 0x9e0c, 0x9b8c, 0x9b8c, 0x9dd3, 0x9b8c, 0x9b8c, 0x9b8c,
+	0x9e24, 0x9b8c, 0x9b8c, 0x9b8c, 0x9ea0, 0x9b8c, 0x9b8c, 0x9b8c,
+	0x9b8c, 0x9b8c, 0x9b8c, 0x9f15, 0x080c, 0x0cf1, 0x080c, 0x4de0,
+	0x1150, 0x2001, 0x1133, 0x2004, 0xd0cc, 0x1128, 0x9084, 0x0009,
+	0x9086, 0x0008, 0x1140, 0x6007, 0x0009, 0x602f, 0x0009, 0x6017,
+	0x0000, 0x0804, 0x9d50, 0x080c, 0x4dd0, 0x00e6, 0x00c6, 0x0036,
+	0x0026, 0x0016, 0x6210, 0x2270, 0x72a0, 0x0026, 0x2019, 0x0029,
+	0x080c, 0x69ca, 0x0076, 0x2039, 0x0000, 0x080c, 0x68fe, 0x2c08,
+	0x080c, 0xa85f, 0x007e, 0x001e, 0x2e60, 0x001e, 0x002e, 0x003e,
+	0x00ce, 0x00ee, 0x6610, 0x00c6, 0x2660, 0x080c, 0x4b67, 0x00ce,
+	0x96b0, 0x0001, 0x2634, 0x9684, 0x00ff, 0x9082, 0x0006, 0x0278,
+	0x080c, 0xa7a3, 0x1904, 0x9c41, 0x080c, 0xa740, 0x1120, 0x6007,
+	0x0008, 0x0804, 0x9d50, 0x6007, 0x0009, 0x0804, 0x9d50, 0x080c,
+	0xa966, 0x0128, 0x080c, 0xa7a3, 0x0d78, 0x0804, 0x9c41, 0x6017,
+	0x1900, 0x0c88, 0x080c, 0x26bc, 0x1904, 0x9f4b, 0x6106, 0x080c,
+	0xa6fc, 0x6007, 0x0006, 0x0804, 0x9d50, 0x6007, 0x0007, 0x0804,
+	0x9d50, 0x080c, 0xacbf, 0x1904, 0x9f4b, 0x080c, 0x26bc, 0x1904,
+	0x9f4b, 0x00d6, 0x6610, 0x2668, 0x6e04, 0x9684, 0x00ff, 0x9082,
+	0x0006, 0x1220, 0x2001, 0x0001, 0x080c, 0x4aa1, 0x96b4, 0xff00,
+	0x8637, 0x9686, 0x0006, 0x0188, 0x9686, 0x0004, 0x0170, 0x6e04,
+	0x96b4, 0x00ff, 0x9686, 0x0006, 0x0140, 0x9686, 0x0004, 0x0128,
+	0x9686, 0x0005, 0x0110, 0x00de, 0x00e0, 0x080c, 0xa801, 0x11a0,
+	0x9686, 0x0006, 0x1150, 0x0026, 0x6210, 0x9290, 0x0028, 0x2214,
+	0x2009, 0x0000, 0x080c, 0x25f0, 0x002e, 0x080c, 0x4bf5, 0x6007,
+	0x000a, 0x00de, 0x0804, 0x9d50, 0x6007, 0x000b, 0x00de, 0x0804,
+	0x9d50, 0x080c, 0x25ad, 0x6007, 0x0001, 0x0804, 0x9d50, 0x080c,
+	0xacbf, 0x1904, 0x9f4b, 0x080c, 0x26bc, 0x1904, 0x9f4b, 0x6610,
+	0x00d6, 0x2668, 0x6e04, 0x00de, 0x9686, 0x0707, 0x0d50, 0x0026,
+	0x6210, 0x9290, 0x0028, 0x2214, 0x2009, 0x0000, 0x080c, 0x25f0,
+	0x002e, 0x6007, 0x000c, 0x0804, 0x9d50, 0x080c, 0x4de0, 0x1140,
+	0x2001, 0x1133, 0x2004, 0x9084, 0x0009, 0x9086, 0x0008, 0x1110,
+	0x0804, 0x9b9b, 0x080c, 0x4dd0, 0x6610, 0x96b0, 0x0001, 0x2634,
+	0x9684, 0x00ff, 0x9082, 0x0006, 0x06e8, 0x1138, 0x0026, 0x2001,
+	0x0006, 0x080c, 0x4ae0, 0x002e, 0x0050, 0x96b4, 0xff00, 0x8637,
+	0x9686, 0x0004, 0x0120, 0x9686, 0x0006, 0x1904, 0x9c41, 0x080c,
+	0xa80e, 0x1120, 0x6007, 0x000e, 0x0804, 0x9d50, 0x0046, 0x6410,
+	0x94a0, 0x0028, 0x2424, 0x94a4, 0x00ff, 0x8427, 0x0046, 0x080c,
+	0x25ad, 0x004e, 0x0016, 0x9006, 0x2009, 0x1153, 0x210c, 0xd1a4,
+	0x0158, 0x2009, 0x0029, 0x080c, 0xaaca, 0x6010, 0x00d6, 0x2068,
+	0x6800, 0xc0e5, 0x6802, 0x00de, 0x001e, 0x004e, 0x6007, 0x0001,
+	0x0804, 0x9d50, 0x2001, 0x0001, 0x080c, 0x4aa1, 0x0156, 0x0016,
+	0x0026, 0x0036, 0x20a9, 0x0004, 0x2019, 0x1105, 0x2011, 0x0270,
+	0x080c, 0x8a45, 0x003e, 0x002e, 0x001e, 0x015e, 0x9005, 0x0168,
+	0x96b4, 0xff00, 0x8637, 0x9682, 0x0004, 0x0a04, 0x9c41, 0x9682,
+	0x0007, 0x0a04, 0x9c8f, 0x0804, 0x9c41, 0x6017, 0x1900, 0x6007,
+	0x0009, 0x0804, 0x9d50, 0x080c, 0x4de0, 0x1140, 0x2001, 0x1133,
+	0x2004, 0x9084, 0x0009, 0x9086, 0x0008, 0x1110, 0x0804, 0x9b9b,
+	0x080c, 0x4dd0, 0x6610, 0x96b0, 0x0001, 0x2634, 0x9684, 0x00ff,
+	0x9082, 0x0006, 0x06b8, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0004,
+	0x0120, 0x9686, 0x0006, 0x1904, 0x9c41, 0x080c, 0xa836, 0x1138,
+	0x080c, 0xa740, 0x1120, 0x6007, 0x0010, 0x0804, 0x9d50, 0x0046,
+	0x6410, 0x94a0, 0x0028, 0x2424, 0x94a4, 0x00ff, 0x8427, 0x0046,
+	0x080c, 0x25ad, 0x004e, 0x0016, 0x9006, 0x2009, 0x1153, 0x210c,
+	0xd1a4, 0x0158, 0x2009, 0x0029, 0x080c, 0xaaca, 0x6010, 0x00d6,
+	0x2068, 0x6800, 0xc0e5, 0x6802, 0x00de, 0x001e, 0x004e, 0x6007,
+	0x0001, 0x00f0, 0x080c, 0xa966, 0x0140, 0x96b4, 0xff00, 0x8637,
+	0x9686, 0x0006, 0x0950, 0x0804, 0x9c41, 0x6017, 0x1900, 0x6007,
+	0x0009, 0x0070, 0x080c, 0x26bc, 0x1904, 0x9f4b, 0x080c, 0xacbf,
+	0x1904, 0x9f4b, 0x080c, 0x9f86, 0x1904, 0x9c41, 0x6007, 0x0012,
+	0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0005, 0x6007,
+	0x0001, 0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0cb0,
+	0x6007, 0x0005, 0x0c68, 0x080c, 0xacbf, 0x1904, 0x9f4b, 0x080c,
+	0x26bc, 0x1904, 0x9f4b, 0x080c, 0x9f86, 0x1904, 0x9c41, 0x6007,
+	0x0020, 0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x0005,
+	0x080c, 0x26bc, 0x1904, 0x9f4b, 0x6007, 0x0023, 0x6003, 0x0001,
+	0x080c, 0x68ce, 0x080c, 0x6d42, 0x0005, 0x080c, 0xacbf, 0x1904,
+	0x9f4b, 0x080c, 0x26bc, 0x1904, 0x9f4b, 0x080c, 0x9f86, 0x1904,
+	0x9c41, 0x0016, 0x0026, 0x00e6, 0x2071, 0x0260, 0x7244, 0x9286,
+	0xffff, 0x0180, 0x2c08, 0x080c, 0x95c2, 0x01b0, 0x2260, 0x7240,
+	0x6008, 0x9206, 0x1188, 0x6010, 0x9190, 0x0004, 0x2214, 0x9206,
+	0x01b8, 0x0050, 0x7240, 0x2c08, 0x9006, 0x080c, 0xaa9c, 0x1180,
+	0x7244, 0x9286, 0xffff, 0x0190, 0x2160, 0x6007, 0x0026, 0x6017,
+	0x1700, 0x7214, 0x9296, 0xffff, 0x1160, 0x6007, 0x0025, 0x0048,
+	0x6020, 0x9086, 0x0007, 0x1d80, 0x080c, 0x7f1e, 0x2160, 0x6007,
+	0x0025, 0x6003, 0x0001, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x00ee,
+	0x002e, 0x001e, 0x0005, 0x2001, 0x0001, 0x080c, 0x4aa1, 0x0156,
+	0x0016, 0x0026, 0x0036, 0x20a9, 0x0004, 0x2019, 0x1105, 0x2011,
+	0x0276, 0x080c, 0x8a45, 0x003e, 0x002e, 0x001e, 0x015e, 0x0120,
+	0x6007, 0x0031, 0x0804, 0x9d50, 0x080c, 0x8752, 0x080c, 0x5745,
+	0x1158, 0x0006, 0x0026, 0x0036, 0x080c, 0x5761, 0x0110, 0x080c,
+	0x571c, 0x003e, 0x002e, 0x000e, 0x0005, 0x080c, 0x26bc, 0x1904,
+	0x9f4b, 0x6106, 0x080c, 0x9fa2, 0x6007, 0x002b, 0x0804, 0x9d50,
+	0x6007, 0x002c, 0x0804, 0x9d50, 0x080c, 0xacbf, 0x1904, 0x9f4b,
+	0x080c, 0x26bc, 0x1904, 0x9f4b, 0x080c, 0x9f86, 0x1904, 0x9c41,
+	0x6106, 0x080c, 0x9fa6, 0x1120, 0x6007, 0x002e, 0x0804, 0x9d50,
+	0x6007, 0x002f, 0x0804, 0x9d50, 0x080c, 0x26bc, 0x1904, 0x9f4b,
+	0x00e6, 0x00d6, 0x00c6, 0x6010, 0x9080, 0x0001, 0x200c, 0x9184,
+	0x00ff, 0x9086, 0x0006, 0x0158, 0x9184, 0xff00, 0x8007, 0x9086,
+	0x0006, 0x0128, 0x00ce, 0x00de, 0x00ee, 0x0804, 0x9d57, 0x2001,
+	0x1172, 0x2004, 0xd0e4, 0x0904, 0x9e9d, 0x2071, 0x026c, 0x7010,
+	0x603a, 0x7014, 0x603e, 0x7108, 0x720c, 0x2001, 0x1153, 0x2004,
+	0xd0a4, 0x0140, 0x6010, 0x2068, 0x6810, 0x9106, 0x1118, 0x6814,
+	0x9206, 0x0508, 0x2001, 0x1153, 0x2004, 0xd0ac, 0x15a0, 0x2069,
+	0x1100, 0x6870, 0x9206, 0x1578, 0x686c, 0x9106, 0x1560, 0x7210,
+	0x080c, 0x95c2, 0x0568, 0x080c, 0xab36, 0x0550, 0x622e, 0x6007,
+	0x0036, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x00ce,
+	0x00de, 0x00ee, 0x0005, 0x7214, 0x9286, 0xffff, 0x0150, 0x080c,
+	0x95c2, 0x01b0, 0x9280, 0x0002, 0x2004, 0x7110, 0x9106, 0x1180,
+	0x08f8, 0x7210, 0x2c08, 0x9085, 0x0001, 0x080c, 0xaa9c, 0x2c10,
+	0x2160, 0x0130, 0x08a8, 0x6007, 0x0037, 0x6017, 0x1500, 0x08c8,
+	0x6007, 0x0037, 0x6017, 0x1700, 0x08a0, 0x6007, 0x0012, 0x0888,
+	0x080c, 0x26bc, 0x1904, 0x9f4b, 0x6010, 0x9080, 0x0001, 0x2004,
+	0x9084, 0xff00, 0x8007, 0x9086, 0x0006, 0x1904, 0x9d57, 0x00e6,
+	0x00d6, 0x00c6, 0x2001, 0x1172, 0x2004, 0xd0e4, 0x0904, 0x9f0d,
+	0x2069, 0x1100, 0x2071, 0x026c, 0x7008, 0x603a, 0x720c, 0x623e,
+	0x9286, 0xffff, 0x1150, 0x7208, 0x00c6, 0x2c08, 0x9085, 0x0001,
+	0x080c, 0xaa9c, 0x2c10, 0x00ce, 0x0598, 0x080c, 0x95c2, 0x0580,
+	0x00c6, 0x0026, 0x2260, 0x080c, 0x9297, 0x002e, 0x00ce, 0x7118,
+	0x918c, 0xff00, 0x810f, 0x9186, 0x0001, 0x0158, 0x9186, 0x0005,
+	0x0118, 0x9186, 0x0007, 0x1178, 0x9280, 0x0005, 0x2004, 0x9005,
+	0x0150, 0x0056, 0x7510, 0x7614, 0x080c, 0xab4f, 0x005e, 0x00ce,
+	0x00de, 0x00ee, 0x0005, 0x6007, 0x003b, 0x602f, 0x0009, 0x6017,
+	0x2a00, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0c78,
+	0x6007, 0x003b, 0x602f, 0x0009, 0x6017, 0x1700, 0x6003, 0x0001,
+	0x080c, 0x6886, 0x080c, 0x6d42, 0x0c10, 0x6007, 0x003b, 0x602f,
+	0x000b, 0x6017, 0x0000, 0x0804, 0x9e71, 0x00e6, 0x0026, 0x080c,
+	0x4de0, 0x0558, 0x080c, 0x4dd0, 0x080c, 0xad2a, 0x1520, 0x2071,
+	0x1100, 0x70cc, 0xc085, 0x70ce, 0x00f6, 0x2079, 0x0100, 0x729c,
+	0x9284, 0x00ff, 0x706e, 0x78e6, 0x9284, 0xff00, 0x7270, 0x9205,
+	0x7072, 0x78ea, 0x00fe, 0x70d7, 0x0000, 0x2001, 0x1153, 0x2004,
+	0xd0a4, 0x0120, 0x2011, 0x12f5, 0x2013, 0x07d0, 0xd0ac, 0x1128,
+	0x080c, 0x23cd, 0x0010, 0x080c, 0xad56, 0x002e, 0x00ee, 0x080c,
+	0x7f1e, 0x0804, 0x9d56, 0x080c, 0x7f1e, 0x0005, 0x2600, 0x0002,
+	0x9f5b, 0x9f5b, 0x9f5b, 0x9f5b, 0x9f5b, 0x9f5d, 0x9f5b, 0x9f5b,
+	0x9f5b, 0x9f5b, 0x9f75, 0x080c, 0x0cf1, 0x080c, 0xacbf, 0x1d58,
+	0x080c, 0x26bc, 0x1d40, 0x0411, 0x1138, 0x6007, 0x0045, 0x6003,
+	0x0001, 0x080c, 0x68ce, 0x0005, 0x080c, 0x25ad, 0x6007, 0x0001,
+	0x6003, 0x0001, 0x080c, 0x68ce, 0x0005, 0x080c, 0xacbf, 0x1998,
+	0x080c, 0x26bc, 0x1980, 0x0051, 0x1d78, 0x703c, 0x6016, 0x6007,
+	0x004a, 0x6003, 0x0001, 0x080c, 0x68ce, 0x0005, 0x00d6, 0x0066,
+	0x6610, 0x2668, 0x6e04, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0006,
+	0x0170, 0x9686, 0x0004, 0x0158, 0x6e04, 0x96b4, 0x00ff, 0x9686,
+	0x0006, 0x0128, 0x9686, 0x0004, 0x0110, 0x9085, 0x0001, 0x006e,
+	0x00de, 0x0005, 0x00d6, 0x0449, 0x00de, 0x0005, 0x00d6, 0x0491,
+	0x11f0, 0x680c, 0x908c, 0xff00, 0x6820, 0x9084, 0x00ff, 0x9115,
+	0x6216, 0x6824, 0x602e, 0xd1e4, 0x0118, 0x2009, 0x0001, 0x0060,
+	0xd1ec, 0x0168, 0x6920, 0x918c, 0x00ff, 0x6824, 0x080c, 0x1c69,
+	0x1130, 0x2110, 0x2009, 0x0000, 0x080c, 0x25f0, 0x0018, 0x9085,
+	0x0001, 0x0008, 0x9006, 0x00de, 0x0005, 0x2069, 0x026d, 0x6800,
+	0x9082, 0x0010, 0x1228, 0x6017, 0x0000, 0x9085, 0x0001, 0x0008,
+	0x9006, 0x0005, 0x6017, 0x0000, 0x2069, 0x026c, 0x6808, 0x9084,
+	0xff00, 0x9086, 0x0800, 0x1140, 0x6800, 0x9084, 0x00ff, 0x908e,
+	0x0014, 0x0110, 0x908e, 0x0010, 0x0005, 0x6004, 0x90b2, 0x004c,
+	0x1a0c, 0x0cf1, 0x91b6, 0x0013, 0x1130, 0x2008, 0x91b2, 0x0040,
+	0x1a04, 0xa11e, 0x0092, 0x91b6, 0x0027, 0x0120, 0x91b6, 0x0014,
+	0x190c, 0x0cf1, 0x2001, 0x0007, 0x080c, 0x4ae0, 0x080c, 0x6c56,
+	0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0xa04d, 0xa04f, 0xa04d,
+	0xa04d, 0xa04d, 0xa04f, 0xa061, 0xa117, 0xa0b9, 0xa117, 0xa0cd,
+	0xa117, 0xa061, 0xa117, 0xa10f, 0xa117, 0xa10f, 0xa117, 0xa117,
+	0xa04d, 0xa04d, 0xa04d, 0xa04d, 0xa04d, 0xa04d, 0xa04d, 0xa04d,
+	0xa04d, 0xa04d, 0xa04d, 0xa04f, 0xa04d, 0xa117, 0xa04d, 0xa04d,
+	0xa117, 0xa04d, 0xa114, 0xa117, 0xa04d, 0xa04d, 0xa04d, 0xa04d,
+	0xa117, 0xa117, 0xa04d, 0xa117, 0xa117, 0xa04d, 0xa05b, 0xa04d,
+	0xa04d, 0xa04d, 0xa04d, 0xa113, 0xa117, 0xa04d, 0xa04d, 0xa117,
+	0xa117, 0xa04d, 0xa04d, 0xa04d, 0xa04d, 0x080c, 0x0cf1, 0x080c,
+	0x6c56, 0x2001, 0x12a6, 0x2004, 0x601a, 0x6003, 0x0002, 0x080c,
+	0x6d42, 0x0804, 0xa11d, 0x2001, 0x0000, 0x080c, 0x4aa1, 0x0804,
+	0xa117, 0x00f6, 0x2079, 0x1152, 0x7804, 0x00fe, 0xd0ac, 0x1904,
+	0xa117, 0x2001, 0x0000, 0x080c, 0x4aa1, 0x6010, 0x9080, 0x0004,
+	0x2004, 0x9086, 0x00ff, 0x1140, 0x00f6, 0x2079, 0x1100, 0x7894,
+	0x8000, 0x7896, 0x00fe, 0x0418, 0x6010, 0x00c6, 0x2060, 0x6000,
+	0xd0f4, 0x1178, 0x6010, 0x9005, 0x0160, 0x0036, 0x0046, 0x63a0,
+	0x2021, 0x0007, 0x080c, 0x384a, 0x004e, 0x003e, 0x00ce, 0x0804,
+	0xa117, 0x00ce, 0x2001, 0x1100, 0x2004, 0x9086, 0x0002, 0x1138,
+	0x00f6, 0x2079, 0x1100, 0x7894, 0x8000, 0x7896, 0x00fe, 0x2001,
+	0x0002, 0x080c, 0x4ab3, 0x080c, 0x6c56, 0x6023, 0x0001, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x6110,
+	0x00c6, 0x2160, 0x2009, 0x0001, 0x080c, 0x6567, 0x00ce, 0x0804,
+	0xa11d, 0x6610, 0x00d6, 0x2668, 0x6e04, 0x00de, 0x96b4, 0xff00,
+	0x8637, 0x9686, 0x0006, 0x0904, 0xa117, 0x9686, 0x0004, 0x0904,
+	0xa117, 0x2001, 0x0004, 0x0804, 0xa115, 0x2001, 0x1100, 0x2004,
+	0x9086, 0x0003, 0x1160, 0x0036, 0x0046, 0x6010, 0x9080, 0x0028,
+	0x201c, 0x2021, 0x0006, 0x080c, 0x384a, 0x004e, 0x003e, 0x2001,
+	0x0006, 0x080c, 0xa134, 0x6610, 0x00d6, 0x2668, 0x6e04, 0x00de,
+	0x0066, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0006, 0x006e, 0x0120,
+	0x2001, 0x0006, 0x080c, 0x4ae0, 0x2001, 0x1153, 0x2004, 0xd0ac,
+	0x11f0, 0x2001, 0x1133, 0x2004, 0xd0a4, 0x01c8, 0x96b4, 0x00ff,
+	0x9686, 0x0006, 0x01a0, 0x00f6, 0x2079, 0x1100, 0x7894, 0x8000,
+	0x7896, 0x00fe, 0x0804, 0xa09f, 0x2001, 0x0004, 0x0030, 0x2001,
+	0x0006, 0x0411, 0x0020, 0x0018, 0x0010, 0x080c, 0x4ae0, 0x080c,
+	0x6c56, 0x080c, 0x7f1e, 0x080c, 0x6d42, 0x0005, 0x2600, 0x0002,
+	0xa12b, 0xa12b, 0xa12b, 0xa12b, 0xa12b, 0xa12d, 0xa12b, 0xa12b,
+	0xa12b, 0xa12b, 0xa12d, 0x080c, 0x0cf1, 0x080c, 0x6c56, 0x080c,
+	0x7f1e, 0x080c, 0x6d42, 0x0005, 0x0016, 0x00d6, 0x6110, 0x2168,
+	0x6900, 0xd184, 0x0188, 0x6104, 0x918e, 0x000a, 0x1128, 0x699c,
+	0xd1a4, 0x1110, 0x2001, 0x0007, 0x080c, 0x4ab3, 0x2001, 0x0000,
+	0x080c, 0x4aa1, 0x080c, 0x25d1, 0x00de, 0x001e, 0x0005, 0x6610,
+	0x00d6, 0x2668, 0x6804, 0x9084, 0xff00, 0x8007, 0x00de, 0x90b2,
+	0x000c, 0x1a0c, 0x0cf1, 0x91b6, 0x0015, 0x1110, 0x003b, 0x0028,
+	0x91b6, 0x0016, 0x190c, 0x0cf1, 0x006b, 0x0005, 0x863b, 0x863b,
+	0x863b, 0x863b, 0x863b, 0x863b, 0xa1b7, 0xa17e, 0x863b, 0x863b,
+	0x863b, 0x863b, 0x863b, 0x863b, 0x863b, 0x863b, 0x863b, 0x863b,
+	0xa1b7, 0xa1be, 0x863b, 0x863b, 0x863b, 0x863b, 0x00f6, 0x2079,
+	0x1152, 0x7804, 0xd0ac, 0x11e0, 0x6010, 0x907d, 0x01c8, 0x7800,
+	0xd0f4, 0x1118, 0x7810, 0x9005, 0x1198, 0x2001, 0x0000, 0x080c,
+	0x4aa1, 0x2001, 0x0002, 0x080c, 0x4ab3, 0x6023, 0x0001, 0x6003,
+	0x0001, 0x6007, 0x0002, 0x080c, 0x68ce, 0x080c, 0x6d42, 0x00a8,
+	0x2011, 0x0263, 0x2204, 0x8211, 0x220c, 0x080c, 0x1c69, 0x1168,
+	0x00c6, 0x080c, 0x4b58, 0x0120, 0x00ce, 0x080c, 0x7f1e, 0x0028,
+	0x080c, 0x472d, 0x00ce, 0x080c, 0x7f1e, 0x00fe, 0x0005, 0x6604,
+	0x96b6, 0x001e, 0x1110, 0x080c, 0x7f1e, 0x0005, 0x080c, 0x88eb,
+	0x1148, 0x6003, 0x0001, 0x6007, 0x0001, 0x080c, 0x68ce, 0x080c,
+	0x6d42, 0x0010, 0x080c, 0x7f1e, 0x0005, 0x6004, 0x908a, 0x004c,
+	0x1a0c, 0x0cf1, 0x080c, 0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42,
+	0x0005, 0x9182, 0x0040, 0x0002, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef,
+	0xa1f1, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef,
+	0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0xa1ef, 0x080c,
+	0x0cf1, 0x00d6, 0x00e6, 0x00f6, 0x0046, 0x0026, 0x6210, 0x9280,
+	0x002b, 0x2004, 0x9005, 0x1190, 0x6106, 0x2071, 0x0260, 0x7444,
+	0x94a4, 0xff00, 0x0904, 0xa256, 0x9486, 0x2000, 0x1160, 0x2009,
+	0x0001, 0x2011, 0x0200, 0x080c, 0x66d5, 0x0028, 0x2021, 0x0000,
+	0x080c, 0xacfb, 0x0c48, 0x080c, 0x0ddf, 0x090c, 0x0cf1, 0x6003,
+	0x0007, 0x2d00, 0x6867, 0x010d, 0x6803, 0x0000, 0x686b, 0x0000,
+	0x6c8a, 0x2c00, 0x688e, 0x6008, 0x68e2, 0x6010, 0x2078, 0x78a0,
+	0x8007, 0x7130, 0x697a, 0x0016, 0x9084, 0xff00, 0x6876, 0x687f,
+	0x0000, 0x6883, 0x0000, 0x6887, 0x0036, 0x080c, 0x50a5, 0x001e,
+	0x9486, 0x2000, 0x1130, 0x2019, 0x0017, 0x080c, 0xaa50, 0x0804,
+	0xa2a9, 0x9486, 0x0400, 0x1130, 0x2019, 0x0002, 0x080c, 0xaa02,
+	0x0804, 0xa2a9, 0x9486, 0x0200, 0x1110, 0x080c, 0xa9e7, 0x9486,
+	0x1000, 0x1110, 0x080c, 0xaa35, 0x0804, 0xa2a9, 0x2069, 0x1329,
+	0x6a00, 0xd284, 0x0904, 0xa303, 0x9284, 0x0300, 0x1904, 0xa2fc,
+	0x6804, 0x9005, 0x0904, 0xa2e4, 0x2d78, 0x6003, 0x0007, 0x080c,
+	0x0dc6, 0x0904, 0xa2b3, 0x7800, 0xd08c, 0x1118, 0x7804, 0x8001,
+	0x7806, 0x6017, 0x0000, 0x6803, 0x0000, 0x6867, 0x0116, 0x686b,
+	0x0000, 0x6008, 0x68e2, 0x2c00, 0x687a, 0x6010, 0x2078, 0x78a0,
+	0x8007, 0x7130, 0x69b6, 0x6876, 0x6883, 0x003d, 0x7044, 0x9084,
+	0x0003, 0x9080, 0xa2af, 0x2005, 0x687e, 0x20a9, 0x000a, 0x2001,
+	0x0270, 0x9d90, 0x0021, 0x2009, 0x0205, 0x200b, 0x0080, 0x20e1,
+	0x0000, 0x20e9, 0x0001, 0x2098, 0x22a0, 0x4003, 0x200b, 0x0000,
+	0x2001, 0x027a, 0x200c, 0x69b2, 0x8000, 0x200c, 0x69ae, 0x080c,
+	0x50a5, 0x002e, 0x004e, 0x00fe, 0x00ee, 0x00de, 0x0005, 0x0000,
+	0x0080, 0x0040, 0x0000, 0x6017, 0x0100, 0x6003, 0x0001, 0x6007,
+	0x0041, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0c58, 0x2069, 0x0260,
+	0x6848, 0x9084, 0xff00, 0x9086, 0x1200, 0x1198, 0x686c, 0x9084,
+	0x00ff, 0x0016, 0x6114, 0x918c, 0x0700, 0x910d, 0x6116, 0x001e,
+	0x6003, 0x0001, 0x6007, 0x0043, 0x080c, 0x6886, 0x080c, 0x6d42,
+	0x0880, 0x6017, 0x0200, 0x6003, 0x0001, 0x6007, 0x0041, 0x080c,
+	0x6886, 0x080c, 0x6d42, 0x0828, 0x2001, 0x110d, 0x2004, 0xd0ec,
+	0x0120, 0x2011, 0x8049, 0x080c, 0x37dc, 0x6017, 0x0300, 0x0010,
+	0x6017, 0x0100, 0x6003, 0x0001, 0x6007, 0x0041, 0x080c, 0x6886,
+	0x080c, 0x6d42, 0x0804, 0xa2a9, 0x6017, 0x0500, 0x0c98, 0x6017,
+	0x0600, 0x0804, 0xa2be, 0x6017, 0x0200, 0x0804, 0xa2be, 0x9186,
+	0x0013, 0x1160, 0x6004, 0x908a, 0x0054, 0x1a0c, 0x0cf1, 0x9082,
+	0x0040, 0x0a0c, 0x0cf1, 0x2008, 0x0804, 0xa38f, 0x9186, 0x0051,
+	0x0138, 0x9186, 0x0047, 0x11d8, 0x6004, 0x9086, 0x0041, 0x0518,
+	0x2001, 0x0109, 0x2004, 0xd084, 0x01f0, 0x0126, 0x2091, 0x2800,
+	0x0006, 0x0016, 0x0026, 0x080c, 0x677e, 0x002e, 0x001e, 0x000e,
+	0x012e, 0x6000, 0x9086, 0x0002, 0x1170, 0x0804, 0xa3dc, 0x9186,
+	0x0027, 0x0120, 0x9186, 0x0014, 0x190c, 0x0cf1, 0x6004, 0x9082,
+	0x0040, 0x2008, 0x001a, 0x080c, 0x7f68, 0x0005, 0xa359, 0xa35b,
+	0xa35b, 0xa37f, 0xa359, 0xa359, 0xa359, 0xa359, 0xa359, 0xa359,
+	0xa359, 0xa359, 0xa359, 0xa359, 0xa359, 0xa359, 0xa359, 0xa359,
+	0xa359, 0x080c, 0x0cf1, 0x080c, 0x6c56, 0x080c, 0x6d42, 0x0036,
+	0x00d6, 0x6014, 0x906d, 0x01c0, 0x9d84, 0xf000, 0x01a8, 0x6003,
+	0x0002, 0x6010, 0x2004, 0xd0bc, 0x1178, 0x2019, 0x0004, 0x080c,
+	0xaa84, 0x6017, 0x0000, 0x6018, 0x9005, 0x1120, 0x2001, 0x12a7,
+	0x2004, 0x601a, 0x6003, 0x0007, 0x00de, 0x003e, 0x0005, 0x00d6,
+	0x080c, 0x6c56, 0x080c, 0x6d42, 0x080c, 0x95d2, 0x0120, 0x6014,
+	0x2068, 0x080c, 0x0df6, 0x080c, 0x97a3, 0x00de, 0x0005, 0x0002,
+	0xa3a3, 0xa3c0, 0xa3ac, 0xa3d6, 0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3,
+	0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3, 0xa3a3,
+	0xa3a3, 0xa3a3, 0xa3a3, 0x080c, 0x0cf1, 0x6014, 0x9088, 0x001f,
+	0x2104, 0x9085, 0x0400, 0x200a, 0x080c, 0x6c56, 0x6014, 0x9080,
+	0x001f, 0x2004, 0xd0b4, 0x0138, 0x6003, 0x0007, 0x2009, 0x0043,
+	0x080c, 0x7f4e, 0x0010, 0x6003, 0x0004, 0x080c, 0x6d42, 0x0005,
+	0x080c, 0x6c56, 0x6114, 0x9184, 0xf000, 0x0128, 0x9180, 0x001f,
+	0x200c, 0xd1ec, 0x1138, 0x080c, 0x66ae, 0x080c, 0x7f1e, 0x080c,
+	0x6d42, 0x0005, 0x080c, 0xacc6, 0x0db0, 0x0cc8, 0x080c, 0x6c56,
+	0x2009, 0x0041, 0x0804, 0xa528, 0x9182, 0x0040, 0x0002, 0xa3f2,
+	0xa3f4, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2,
+	0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2,
+	0xa3f5, 0xa3f2, 0x080c, 0x0cf1, 0x0005, 0x00d6, 0x080c, 0x66ae,
+	0x00de, 0x080c, 0xad19, 0x080c, 0x7f1e, 0x0005, 0x9182, 0x0040,
+	0x0002, 0xa414, 0xa414, 0xa414, 0xa414, 0xa414, 0xa414, 0xa414,
+	0xa416, 0xa414, 0xa419, 0xa471, 0xa414, 0xa414, 0xa414, 0xa414,
+	0xa471, 0xa414, 0xa414, 0xa414, 0x080c, 0x0cf1, 0x080c, 0x7f68,
+	0x0005, 0x2001, 0x0105, 0x2004, 0x9084, 0x1800, 0x1904, 0xa471,
+	0x2001, 0x1172, 0x2004, 0xd0e4, 0x1528, 0x603b, 0x0000, 0x080c,
+	0x6cf2, 0x6014, 0x00d6, 0x2068, 0x687c, 0xd0fc, 0x0188, 0x908c,
+	0x0003, 0x918e, 0x0002, 0x0508, 0x2001, 0x110c, 0x2004, 0xd0d4,
+	0x11e0, 0x080c, 0x6e07, 0x2009, 0x0041, 0x00de, 0x0804, 0xa528,
+	0x080c, 0x6e07, 0x6003, 0x0007, 0x601b, 0x0000, 0x080c, 0x66ae,
+	0x00de, 0x0005, 0x2001, 0x0100, 0x2004, 0x9082, 0x0005, 0x0aa8,
+	0x2001, 0x011f, 0x2004, 0x603a, 0x0890, 0x2001, 0x110c, 0x200c,
+	0xc1d4, 0x2102, 0xd1cc, 0x0110, 0x080c, 0x2069, 0x080c, 0x6e07,
+	0x6014, 0x9080, 0x001f, 0x200c, 0xd1ec, 0x1130, 0x080c, 0x66ae,
+	0x080c, 0x7f1e, 0x00de, 0x0005, 0x080c, 0xacc6, 0x0db8, 0x00de,
+	0x0005, 0x2001, 0x110c, 0x200c, 0xc1d4, 0x2102, 0x0036, 0x080c,
+	0x6cf2, 0x080c, 0x6e07, 0x6014, 0x00d6, 0x2068, 0x6010, 0x2004,
+	0xd0bc, 0x0188, 0x687c, 0x9084, 0x0003, 0x9086, 0x0002, 0x0140,
+	0x68ac, 0x6330, 0x931a, 0x6332, 0x68b0, 0x632c, 0x931b, 0x632e,
+	0x6003, 0x0002, 0x0080, 0x2019, 0x0004, 0x080c, 0xaa84, 0x6018,
+	0x9005, 0x1128, 0x2001, 0x12a7, 0x2004, 0x8003, 0x601a, 0x6017,
+	0x0000, 0x6003, 0x0007, 0x00de, 0x003e, 0x0005, 0x9182, 0x0040,
+	0x0002, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd,
+	0xa4bd, 0xa4bf, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd,
+	0xa4bd, 0xa4bd, 0xa4bd, 0xa4bd, 0xa504, 0x080c, 0x0cf1, 0x6014,
+	0x00d6, 0x2068, 0x6834, 0x6a38, 0x6110, 0x210c, 0xd1bc, 0x1190,
+	0x920d, 0x1518, 0x687c, 0xd0fc, 0x0128, 0x2009, 0x0041, 0x00de,
+	0x0804, 0xa528, 0x6003, 0x0007, 0x601b, 0x0000, 0x080c, 0x66ae,
+	0x00de, 0x0005, 0x6124, 0xd1f4, 0x1d58, 0x0006, 0x0046, 0x6cac,
+	0x9422, 0x69b0, 0x2200, 0x910b, 0x6030, 0x9420, 0x6432, 0x602c,
+	0x9109, 0x612e, 0x004e, 0x000e, 0x08d8, 0x6110, 0x210c, 0xd1bc,
+	0x1178, 0x2009, 0x110d, 0x210c, 0xd19c, 0x0118, 0x6003, 0x0007,
+	0x0010, 0x6003, 0x0006, 0x00e9, 0x080c, 0x66b0, 0x00de, 0x0005,
+	0x6003, 0x0002, 0x00de, 0x0005, 0x6024, 0xd0f4, 0x0128, 0x080c,
+	0x1132, 0x1904, 0xa4bf, 0x0005, 0x00d6, 0x6014, 0x2068, 0x6834,
+	0x6938, 0x00de, 0x9105, 0x1120, 0x080c, 0x1132, 0x1904, 0xa4bf,
+	0x0005, 0xd2fc, 0x0140, 0x8002, 0x8000, 0x8212, 0x9291, 0x0000,
+	0x2009, 0x0009, 0x0010, 0x2009, 0x0015, 0x6a9a, 0x6896, 0x0005,
+	0x9182, 0x0040, 0x0208, 0x0062, 0x9186, 0x0013, 0x0120, 0x9186,
+	0x0014, 0x190c, 0x0cf1, 0x6024, 0xd0dc, 0x090c, 0x0cf1, 0x0005,
+	0xa54b, 0xa552, 0xa55e, 0xa56a, 0xa54b, 0xa54b, 0xa54b, 0xa579,
+	0xa54b, 0xa54d, 0xa54d, 0xa54b, 0xa54b, 0xa54b, 0xa54b, 0xa54d,
+	0xa54b, 0xa54d, 0xa54b, 0x080c, 0x0cf1, 0x6024, 0xd0dc, 0x090c,
+	0x0cf1, 0x0005, 0x6003, 0x0001, 0x6106, 0x080c, 0x6886, 0x0126,
+	0x2091, 0x8000, 0x080c, 0x6d42, 0x012e, 0x0005, 0x6003, 0x0001,
+	0x6106, 0x080c, 0x6886, 0x0126, 0x2091, 0x8000, 0x080c, 0x6d42,
+	0x012e, 0x0005, 0x6003, 0x0003, 0x6106, 0x2c10, 0x080c, 0x13a9,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x68eb, 0x080c, 0x6e10, 0x012e,
+	0x0005, 0x9016, 0x080c, 0x119a, 0x0005, 0x0126, 0x2091, 0x8000,
+	0x0036, 0x00d6, 0x9182, 0x0040, 0x0023, 0x00de, 0x003e, 0x012e,
+	0x0005, 0xa599, 0xa59b, 0xa5ad, 0xa5c8, 0xa599, 0xa599, 0xa599,
+	0xa5dd, 0xa599, 0xa599, 0xa599, 0xa599, 0xa599, 0xa599, 0xa599,
+	0xa599, 0x080c, 0x0cf1, 0x6014, 0x2068, 0x687c, 0xd0fc, 0x01f8,
+	0x909c, 0x0003, 0x939e, 0x0003, 0x01d0, 0x6003, 0x0001, 0x6106,
+	0x080c, 0x6886, 0x080c, 0x6d42, 0x0498, 0x6014, 0x2068, 0x687c,
+	0xd0fc, 0x0168, 0x909c, 0x0003, 0x939e, 0x0003, 0x0140, 0x6003,
+	0x0001, 0x6106, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0408, 0x6017,
+	0x0000, 0x601b, 0x0000, 0x2019, 0x0004, 0x080c, 0xaa84, 0x00c0,
+	0x6014, 0x2068, 0x687c, 0xd0fc, 0x0d90, 0x909c, 0x0003, 0x939e,
+	0x0003, 0x0d68, 0x6003, 0x0003, 0x6106, 0x2c10, 0x080c, 0x13a9,
+	0x080c, 0x68eb, 0x080c, 0x6e10, 0x0018, 0x9016, 0x080c, 0x119a,
+	0x0005, 0x080c, 0x6c56, 0x6114, 0x81ff, 0x0158, 0x00d6, 0x2168,
+	0x080c, 0xad5f, 0x0036, 0x2019, 0x0029, 0x080c, 0xaa84, 0x003e,
+	0x00de, 0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0x080c, 0x6cf2,
+	0x6114, 0x81ff, 0x0158, 0x00d6, 0x2168, 0x080c, 0xad5f, 0x0036,
+	0x2019, 0x0029, 0x080c, 0xaa84, 0x003e, 0x00de, 0x080c, 0x97a3,
+	0x080c, 0x6e10, 0x0005, 0x9182, 0x0085, 0x0002, 0xa61b, 0xa619,
+	0xa619, 0xa627, 0xa619, 0xa619, 0xa619, 0xa619, 0xa619, 0xa619,
+	0xa619, 0x080c, 0x0cf1, 0x6003, 0x000b, 0x6106, 0x080c, 0x6886,
+	0x0126, 0x2091, 0x8000, 0x080c, 0x6d42, 0x012e, 0x0005, 0x0026,
+	0x00e6, 0x080c, 0xacbf, 0x0118, 0x080c, 0x7f1e, 0x00c8, 0x2071,
+	0x0260, 0x7224, 0x6216, 0x7220, 0x080c, 0xa91c, 0x0118, 0x6007,
+	0x0086, 0x0040, 0x6007, 0x0087, 0x7224, 0x9296, 0xffff, 0x1110,
+	0x6007, 0x0086, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42,
+	0x00ee, 0x002e, 0x0005, 0x9186, 0x0013, 0x1160, 0x6004, 0x908a,
+	0x0085, 0x0a0c, 0x0cf1, 0x908a, 0x0090, 0x1a0c, 0x0cf1, 0x9082,
+	0x0085, 0x00a2, 0x9186, 0x0027, 0x0130, 0x9186, 0x0014, 0x0118,
+	0x080c, 0x7f68, 0x0050, 0x2001, 0x0007, 0x080c, 0x4ae0, 0x080c,
+	0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0xa679, 0xa67b,
+	0xa67b, 0xa679, 0xa679, 0xa679, 0xa679, 0xa679, 0xa679, 0xa679,
+	0xa679, 0x080c, 0x0cf1, 0x080c, 0x6c56, 0x080c, 0x97a3, 0x080c,
+	0x6d42, 0x0005, 0x9182, 0x0085, 0x0a0c, 0x0cf1, 0x9182, 0x0090,
+	0x1a0c, 0x0cf1, 0x9182, 0x0085, 0x0002, 0xa698, 0xa698, 0xa698,
+	0xa69a, 0xa698, 0xa698, 0xa698, 0xa698, 0xa698, 0xa698, 0xa698,
+	0x080c, 0x0cf1, 0x0005, 0x9186, 0x0013, 0x0148, 0x9186, 0x0014,
+	0x0130, 0x9186, 0x0027, 0x0118, 0x080c, 0x7f68, 0x0030, 0x080c,
+	0x6c56, 0x080c, 0x97a3, 0x080c, 0x6d42, 0x0005, 0x0036, 0x080c,
+	0xad19, 0x6043, 0x0000, 0x2019, 0x000b, 0x0031, 0x6023, 0x0006,
+	0x6003, 0x0007, 0x003e, 0x0005, 0x0126, 0x0036, 0x2091, 0x8000,
+	0x0086, 0x2c40, 0x0096, 0x2049, 0x0000, 0x080c, 0x7a48, 0x009e,
+	0x008e, 0x1578, 0x0076, 0x2c38, 0x080c, 0x7ae2, 0x007e, 0x1548,
+	0x6000, 0x9086, 0x0000, 0x0528, 0x6020, 0x9086, 0x0007, 0x0508,
+	0x00d6, 0x6000, 0x9086, 0x0004, 0x1150, 0x080c, 0xad19, 0x6023,
+	0x0007, 0x2001, 0x12a6, 0x2004, 0x601a, 0x080c, 0x12c7, 0x6014,
+	0x2068, 0x080c, 0x95d2, 0x0110, 0x080c, 0xaa84, 0x00de, 0x6017,
+	0x0000, 0x080c, 0xad19, 0x6023, 0x0007, 0x2001, 0x12a6, 0x2004,
+	0x601a, 0x003e, 0x012e, 0x0005, 0x00f6, 0x00c6, 0x0036, 0x0156,
+	0x2079, 0x0260, 0x7938, 0x783c, 0x080c, 0x1c69, 0x15a0, 0x0016,
+	0x00c6, 0x080c, 0x4b58, 0x1568, 0x001e, 0x002e, 0x0026, 0x0016,
+	0x2019, 0x0029, 0x080c, 0x7ba2, 0x080c, 0x69ca, 0x0076, 0x2039,
+	0x0000, 0x080c, 0x68fe, 0x007e, 0x001e, 0x0076, 0x2039, 0x0000,
+	0x080c, 0xa85f, 0x007e, 0x0026, 0x6204, 0x9294, 0xff00, 0x8217,
+	0x9286, 0x0006, 0x0118, 0x9286, 0x0004, 0x1118, 0x62a0, 0x080c,
+	0x2661, 0x002e, 0x001e, 0x080c, 0x472d, 0x6612, 0x6516, 0x9006,
+	0x0010, 0x00ce, 0x001e, 0x015e, 0x003e, 0x00ce, 0x00fe, 0x0005,
+	0x00c6, 0x00d6, 0x00e6, 0x0016, 0x2009, 0x1120, 0x2104, 0x9086,
+	0x0074, 0x1904, 0xa798, 0x2069, 0x0260, 0x6944, 0x9182, 0x0100,
+	0x06d8, 0x6940, 0x9184, 0x8000, 0x0904, 0xa795, 0x2001, 0x128f,
+	0x2004, 0x9005, 0x1160, 0x6010, 0x2070, 0x7010, 0x9084, 0x00ff,
+	0x0118, 0x7000, 0xd0f4, 0x0118, 0x9184, 0x0800, 0x0570, 0x6948,
+	0x918a, 0x0001, 0x0620, 0x694c, 0x2009, 0x0205, 0x200b, 0x0001,
+	0x693c, 0x81ff, 0x1198, 0x6944, 0x9182, 0x0100, 0x02a8, 0x6940,
+	0x81ff, 0x1178, 0x6948, 0x918a, 0x0001, 0x0288, 0x6950, 0x918a,
+	0x0001, 0x0298, 0x00d0, 0x6017, 0x0100, 0x00a0, 0x6017, 0x0300,
+	0x0088, 0x6017, 0x0500, 0x0070, 0x6017, 0x0700, 0x0058, 0x6017,
+	0x0900, 0x0040, 0x6017, 0x0b00, 0x0028, 0x6017, 0x0f00, 0x0010,
+	0x6017, 0x2d00, 0x9085, 0x0001, 0x0008, 0x9006, 0x001e, 0x00ee,
+	0x00de, 0x00ce, 0x0005, 0x00c6, 0x00d6, 0x0026, 0x0036, 0x0156,
+	0x6210, 0x2268, 0x6b04, 0x9394, 0x00ff, 0x9286, 0x0006, 0x0190,
+	0x9286, 0x0004, 0x0178, 0x9394, 0xff00, 0x8217, 0x9286, 0x0006,
+	0x0148, 0x9286, 0x0004, 0x0130, 0x00c6, 0x2d60, 0x080c, 0x4b67,
+	0x00ce, 0x04c0, 0x2011, 0x0276, 0x20a9, 0x0004, 0x9d98, 0x000a,
+	0x080c, 0x8a45, 0x1580, 0x2011, 0x027a, 0x20a9, 0x0004, 0x9d98,
+	0x0006, 0x080c, 0x8a45, 0x1538, 0x0046, 0x0016, 0x6aa0, 0x9294,
+	0x00ff, 0x8227, 0x9006, 0x2009, 0x1153, 0x210c, 0xd1a4, 0x0138,
+	0x2009, 0x0029, 0x080c, 0xaaca, 0x6800, 0xc0e5, 0x6802, 0x2019,
+	0x0029, 0x080c, 0x69ca, 0x0076, 0x2039, 0x0000, 0x080c, 0x68fe,
+	0x2c08, 0x080c, 0xa85f, 0x007e, 0x2001, 0x0007, 0x080c, 0x4ae0,
+	0x001e, 0x004e, 0x9006, 0x015e, 0x003e, 0x002e, 0x00de, 0x00ce,
+	0x0005, 0x00d6, 0x2069, 0x026e, 0x6800, 0x9086, 0x0800, 0x0118,
+	0x6017, 0x0000, 0x0008, 0x9006, 0x00de, 0x0005, 0x00c6, 0x00f6,
+	0x0016, 0x0026, 0x0036, 0x0156, 0x2079, 0x026c, 0x7930, 0x7834,
+	0x080c, 0x1c69, 0x11a0, 0x080c, 0x4b58, 0x1188, 0x2011, 0x0270,
+	0x20a9, 0x0004, 0x9c98, 0x000a, 0x080c, 0x8a45, 0x1140, 0x2011,
+	0x0274, 0x20a9, 0x0004, 0x9c98, 0x0006, 0x080c, 0x8a45, 0x015e,
+	0x003e, 0x002e, 0x001e, 0x00fe, 0x00ce, 0x0005, 0x00c6, 0x0006,
+	0x0016, 0x0026, 0x0036, 0x0156, 0x2011, 0x0263, 0x2204, 0x8211,
+	0x220c, 0x080c, 0x1c69, 0x11a0, 0x080c, 0x4b58, 0x1188, 0x2011,
+	0x0276, 0x20a9, 0x0004, 0x9c98, 0x000a, 0x080c, 0x8a45, 0x1140,
+	0x2011, 0x027a, 0x20a9, 0x0004, 0x9c98, 0x0006, 0x080c, 0x8a45,
+	0x015e, 0x003e, 0x002e, 0x001e, 0x000e, 0x00ce, 0x0005, 0x00e6,
+	0x00c6, 0x0086, 0x0076, 0x0066, 0x0056, 0x0046, 0x0026, 0x0126,
+	0x2091, 0x8000, 0x2740, 0x2029, 0x12e5, 0x252c, 0x2021, 0x12eb,
+	0x2424, 0x2061, 0x15c0, 0x2071, 0x1100, 0x7644, 0x7064, 0x81ff,
+	0x0128, 0x8001, 0x9602, 0x1a04, 0xa8db, 0x0018, 0x9606, 0x0904,
+	0xa8db, 0x2100, 0x9c06, 0x0904, 0xa8d2, 0x080c, 0xaaf2, 0x0904,
+	0xa8d2, 0x6720, 0x9786, 0x0001, 0x0904, 0xa8f3, 0x9786, 0x0004,
+	0x0904, 0xa8f3, 0x9786, 0x0007, 0x05e8, 0x2500, 0x9c06, 0x05d0,
+	0x2400, 0x9c06, 0x05b8, 0x080c, 0xab02, 0x15a0, 0x88ff, 0x0118,
+	0x6054, 0x9906, 0x1578, 0x00d6, 0x6000, 0x9086, 0x0004, 0x1120,
+	0x0016, 0x080c, 0x12c7, 0x001e, 0x9786, 0x0008, 0x1148, 0x080c,
+	0x97cd, 0x1130, 0x080c, 0x8576, 0x00de, 0x080c, 0x97a3, 0x00d0,
+	0x6014, 0x2068, 0x080c, 0x95d2, 0x0190, 0x9786, 0x0003, 0x1528,
+	0x6867, 0x0103, 0x6b7a, 0x6877, 0x0000, 0x080c, 0xad5f, 0x0016,
+	0x080c, 0x9843, 0x080c, 0x50a5, 0x001e, 0x080c, 0x9797, 0x00de,
+	0x080c, 0x97a3, 0x9ce0, 0x0018, 0x2001, 0x1116, 0x2004, 0x9c02,
+	0x1210, 0x0804, 0xa873, 0x012e, 0x002e, 0x004e, 0x005e, 0x006e,
+	0x007e, 0x008e, 0x00ce, 0x00ee, 0x0005, 0x9786, 0x0006, 0x19c0,
+	0x9386, 0x0005, 0x0128, 0x080c, 0xad5f, 0x080c, 0xaa84, 0x08f8,
+	0x00de, 0x0c00, 0x0868, 0x080c, 0xab02, 0x19e0, 0x81ff, 0x09d0,
+	0x9180, 0x0001, 0x2004, 0x9086, 0x0018, 0x0130, 0x9180, 0x0001,
+	0x2004, 0x9086, 0x002d, 0x1970, 0x6000, 0x9086, 0x0002, 0x1950,
+	0x080c, 0x97bc, 0x0130, 0x080c, 0x97cd, 0x1920, 0x080c, 0x8576,
+	0x0038, 0x080c, 0x25d1, 0x080c, 0x97cd, 0x1110, 0x080c, 0x8576,
+	0x080c, 0x97a3, 0x0804, 0xa8d2, 0x00c6, 0x00e6, 0x0016, 0x2c08,
+	0x2170, 0x9006, 0x080c, 0xaa9c, 0x001e, 0x0120, 0x6020, 0x9084,
+	0x000f, 0x001b, 0x00ee, 0x00ce, 0x0005, 0xa93b, 0xa93b, 0xa93b,
+	0xa93b, 0xa93b, 0xa93b, 0xa93d, 0xa93b, 0xa93b, 0xa93b, 0xa93b,
+	0x97a3, 0x97a3, 0xa93b, 0x9006, 0x0005, 0x0046, 0x0016, 0x7010,
+	0x9080, 0x0028, 0x2024, 0x94a4, 0x00ff, 0x8427, 0x2c00, 0x2009,
+	0x0020, 0x080c, 0xaaca, 0x001e, 0x004e, 0x0036, 0x2019, 0x0002,
+	0x080c, 0xa6bc, 0x003e, 0x9085, 0x0001, 0x0005, 0x00d6, 0x6014,
+	0x906d, 0x9084, 0xf000, 0x0130, 0x080c, 0x92a4, 0x687b, 0x0005,
+	0x080c, 0x50a5, 0x00de, 0x080c, 0x97a3, 0x0005, 0x2001, 0x0001,
+	0x080c, 0x4aa1, 0x0156, 0x0016, 0x0026, 0x0036, 0x20a9, 0x0004,
+	0x2019, 0x1105, 0x2011, 0x0276, 0x080c, 0x8a45, 0x003e, 0x002e,
+	0x001e, 0x015e, 0x9005, 0x0005, 0x00f6, 0x00e6, 0x00c6, 0x0086,
+	0x0076, 0x0066, 0x0026, 0x0126, 0x2091, 0x8000, 0x2740, 0x2061,
+	0x15c0, 0x2079, 0x0001, 0x8fff, 0x0904, 0xa9da, 0x2071, 0x1100,
+	0x7644, 0x7064, 0x8001, 0x9602, 0x1a04, 0xa9da, 0x88ff, 0x0128,
+	0x2800, 0x9c06, 0x15b0, 0x2079, 0x0000, 0x080c, 0xaaf2, 0x0588,
+	0x2400, 0x9c06, 0x0570, 0x6720, 0x9786, 0x0006, 0x1550, 0x9786,
+	0x0007, 0x0538, 0x88ff, 0x1140, 0x6010, 0x9206, 0x1510, 0x85ff,
+	0x0118, 0x6054, 0x9106, 0x11e8, 0x00d6, 0x6000, 0x9086, 0x0004,
+	0x1150, 0x080c, 0xad19, 0x6023, 0x0007, 0x2001, 0x12a6, 0x2004,
+	0x601a, 0x080c, 0x12c7, 0x6014, 0x2068, 0x080c, 0x95d2, 0x0120,
+	0x0046, 0x080c, 0xaa84, 0x004e, 0x00de, 0x080c, 0x97a3, 0x88ff,
+	0x1198, 0x9ce0, 0x0018, 0x2001, 0x1116, 0x2004, 0x9c02, 0x1210,
+	0x0804, 0xa98b, 0x9006, 0x012e, 0x002e, 0x006e, 0x007e, 0x008e,
+	0x00ce, 0x00ee, 0x00fe, 0x0005, 0x98c5, 0x0001, 0x0ca0, 0x0076,
+	0x0056, 0x0086, 0x2041, 0x0000, 0x2029, 0x0001, 0x2c20, 0x2019,
+	0x0002, 0x6210, 0x0096, 0x2049, 0x0000, 0x080c, 0x7a48, 0x009e,
+	0x008e, 0x2039, 0x0000, 0x080c, 0x7ae2, 0x080c, 0xa97c, 0x005e,
+	0x007e, 0x0005, 0x0026, 0x0046, 0x0056, 0x0076, 0x00c6, 0x0156,
+	0x2c20, 0x2128, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x0036,
+	0x080c, 0x4b58, 0x11b0, 0x2c10, 0x0056, 0x0086, 0x2041, 0x0000,
+	0x2508, 0x2029, 0x0001, 0x0096, 0x2049, 0x0000, 0x080c, 0x7a48,
+	0x009e, 0x008e, 0x2039, 0x0000, 0x080c, 0x7ae2, 0x080c, 0xa97c,
+	0x005e, 0x003e, 0x001e, 0x8108, 0x1f04, 0xaa0e, 0x015e, 0x00ce,
+	0x007e, 0x005e, 0x004e, 0x002e, 0x0005, 0x0076, 0x0056, 0x6210,
+	0x0086, 0x2041, 0x0000, 0x2029, 0x0001, 0x2019, 0x0048, 0x0096,
+	0x2049, 0x0000, 0x080c, 0x7a48, 0x009e, 0x008e, 0x2039, 0x0000,
+	0x080c, 0x7ae2, 0x2c20, 0x080c, 0xa97c, 0x005e, 0x007e, 0x0005,
+	0x0026, 0x0046, 0x0056, 0x0076, 0x00c6, 0x0156, 0x2c20, 0x20a9,
+	0x007f, 0x2009, 0x0000, 0x0016, 0x0036, 0x080c, 0x4b58, 0x11c0,
+	0x2c10, 0x0086, 0x2041, 0x0000, 0x2828, 0x0046, 0x2021, 0x0001,
+	0x080c, 0xacfb, 0x004e, 0x0096, 0x2049, 0x0000, 0x080c, 0x7a48,
+	0x009e, 0x008e, 0x2039, 0x0000, 0x080c, 0x7ae2, 0x080c, 0xa97c,
+	0x003e, 0x001e, 0x8108, 0x1f04, 0xaa5b, 0x015e, 0x00ce, 0x007e,
+	0x005e, 0x004e, 0x002e, 0x0005, 0x0016, 0x00f6, 0x9d82, 0x45c0,
+	0x0280, 0x9d82, 0xffff, 0x1268, 0x6800, 0x907d, 0x0138, 0x6803,
+	0x0000, 0x6b82, 0x080c, 0x50a5, 0x2f68, 0x0cb0, 0x6b82, 0x080c,
+	0x50a5, 0x00fe, 0x001e, 0x0005, 0x00e6, 0x0046, 0x0036, 0x2061,
+	0x15c0, 0x9005, 0x1138, 0x2071, 0x1100, 0x7444, 0x7064, 0x8001,
+	0x9402, 0x12d8, 0x2100, 0x9c06, 0x0168, 0x6000, 0x9086, 0x0000,
+	0x0148, 0x6008, 0x9206, 0x1130, 0x6010, 0x91a0, 0x0004, 0x2424,
+	0x9406, 0x0140, 0x9ce0, 0x0018, 0x2001, 0x1116, 0x2004, 0x9c02,
+	0x1220, 0x0c40, 0x9085, 0x0001, 0x0008, 0x9006, 0x003e, 0x004e,
+	0x00ee, 0x0005, 0x00d6, 0x0006, 0x080c, 0x0ddf, 0x000e, 0x090c,
+	0x0cf1, 0x6867, 0x010d, 0x688e, 0x0026, 0x2010, 0x080c, 0x95c2,
+	0x2001, 0x0000, 0x0120, 0x2200, 0x9080, 0x0015, 0x2004, 0x002e,
+	0x687a, 0x6986, 0x6c76, 0x687f, 0x0000, 0x2001, 0x12ae, 0x2004,
+	0x6882, 0x9006, 0x68e2, 0x6802, 0x686a, 0x688a, 0x080c, 0x50a5,
+	0x00de, 0x0005, 0x6700, 0x9786, 0x0000, 0x0158, 0x9786, 0x0001,
+	0x0140, 0x9786, 0x000a, 0x0128, 0x9786, 0x0009, 0x0110, 0x9085,
+	0x0001, 0x0005, 0x00e6, 0x6010, 0x2070, 0x70a0, 0x9206, 0x00ee,
+	0x0005, 0x0016, 0x6004, 0x908e, 0x001e, 0x11a0, 0x8007, 0x6134,
+	0x918c, 0x00ff, 0x9105, 0x6036, 0x6007, 0x0085, 0x6003, 0x000b,
+	0x6023, 0x0005, 0x2001, 0x12a7, 0x2004, 0x601a, 0x080c, 0x6886,
+	0x080c, 0x6d42, 0x001e, 0x0005, 0xa001, 0xa001, 0x0005, 0x6024,
+	0xd0e4, 0x0158, 0xd0cc, 0x0118, 0x080c, 0x98aa, 0x0030, 0x080c,
+	0xad19, 0x080c, 0x66ae, 0x080c, 0x7f1e, 0x0005, 0x9280, 0x0008,
+	0x2004, 0x9084, 0x000f, 0x0002, 0xab4a, 0xab4a, 0xab4a, 0xab4c,
+	0xab4a, 0xab4c, 0xab4c, 0xab4a, 0xab4c, 0xab4a, 0xab4a, 0xab4a,
+	0xab4a, 0xab4a, 0x9006, 0x0005, 0x9085, 0x0001, 0x0005, 0x9280,
+	0x0008, 0x2004, 0x9084, 0x000f, 0x0002, 0xab63, 0xab63, 0xab63,
+	0xab63, 0xab63, 0xab63, 0xab70, 0xab63, 0xab63, 0xab63, 0xab63,
+	0xab63, 0xab63, 0xab63, 0x6007, 0x003b, 0x602f, 0x0009, 0x6017,
+	0x2a00, 0x6003, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x0005,
+	0x00c6, 0x2260, 0x080c, 0xad19, 0x6043, 0x0000, 0x6024, 0xc0f4,
+	0xc0e4, 0x6026, 0x603b, 0x0000, 0x00ce, 0x00d6, 0x2268, 0x9186,
+	0x0007, 0x1904, 0xabcb, 0x6814, 0x9005, 0x0138, 0x9080, 0x001f,
+	0x2004, 0xd0fc, 0x1110, 0x00de, 0x08b0, 0x6007, 0x003a, 0x6003,
+	0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x00c6, 0x2d60, 0x6100,
+	0x9186, 0x0002, 0x1904, 0xac4e, 0x6014, 0x9005, 0x1138, 0x6000,
+	0x9086, 0x0007, 0x190c, 0x0cf1, 0x0804, 0xac4e, 0x908c, 0xf000,
+	0x1130, 0x0028, 0x2068, 0x6800, 0x9005, 0x1de0, 0x2d00, 0x9080,
+	0x001f, 0x2004, 0x9084, 0x0003, 0x9086, 0x0002, 0x1180, 0x6014,
+	0x2068, 0x687c, 0xc0dc, 0xc0f4, 0x687e, 0x6880, 0xc0f4, 0xc0fc,
+	0x6882, 0x2009, 0x0043, 0x080c, 0xa528, 0x0804, 0xac4e, 0x2009,
+	0x0041, 0x0804, 0xac48, 0x9186, 0x0005, 0x15c0, 0x6814, 0x9080,
+	0x001f, 0x2004, 0xd0bc, 0x1118, 0x00de, 0x0804, 0xab63, 0xd0b4,
+	0x0128, 0xd0fc, 0x090c, 0x0cf1, 0x0804, 0xab83, 0x6007, 0x003a,
+	0x6003, 0x0001, 0x080c, 0x6886, 0x080c, 0x6d42, 0x00c6, 0x2d60,
+	0x6100, 0x9186, 0x0002, 0x0120, 0x9186, 0x0004, 0x1904, 0xac4e,
+	0x6814, 0x9080, 0x001f, 0x200c, 0xc1f4, 0xc1dc, 0x2102, 0x8000,
+	0x200c, 0xc1f4, 0xc1fc, 0xc1bc, 0x2102, 0x00f6, 0x2c78, 0x080c,
+	0x119d, 0x00fe, 0x2009, 0x0042, 0x0804, 0xac48, 0x0036, 0x00d6,
+	0x00d6, 0x080c, 0x0ddf, 0x003e, 0x090c, 0x0cf1, 0x6867, 0x010d,
+	0x6803, 0x0000, 0x686b, 0x0000, 0x688b, 0x0000, 0x6b8e, 0x6887,
+	0x0045, 0x2c00, 0x6892, 0x6038, 0x68a2, 0x2360, 0x6024, 0xc0dd,
+	0x6026, 0x6010, 0x9080, 0x0028, 0x2004, 0x9084, 0x00ff, 0x8007,
+	0x6354, 0x6b7a, 0x6876, 0x687f, 0x0000, 0x6883, 0x0000, 0x6d9a,
+	0x6e96, 0x689f, 0x0001, 0x080c, 0x50a5, 0x2019, 0x0045, 0x6008,
+	0x2068, 0x080c, 0xa6bc, 0x2d00, 0x600a, 0x6023, 0x0006, 0x6003,
+	0x0007, 0x601b, 0x0000, 0x6043, 0x0000, 0x00de, 0x003e, 0x0038,
+	0x6043, 0x0000, 0x6003, 0x0007, 0x080c, 0xa528, 0x00ce, 0x00de,
+	0x0005, 0x9186, 0x0013, 0x1128, 0x6004, 0x9082, 0x0085, 0x2008,
+	0x00c2, 0x9186, 0x0027, 0x1178, 0x080c, 0x6c56, 0x0036, 0x00d6,
+	0x6014, 0x2068, 0x2019, 0x0004, 0x080c, 0xaa84, 0x00de, 0x003e,
+	0x080c, 0x6d42, 0x0005, 0x9186, 0x0014, 0x0d70, 0x080c, 0x7f68,
+	0x0005, 0xac7e, 0xac7c, 0xac7c, 0xac7c, 0xac7c, 0xac7c, 0xac7e,
+	0xac7c, 0xac7c, 0xac7c, 0xac7c, 0x080c, 0x0cf1, 0x080c, 0x6c56,
+	0x6003, 0x000c, 0x080c, 0x6d42, 0x0005, 0x9182, 0x0090, 0x1220,
+	0x9182, 0x0085, 0x0208, 0x001a, 0x080c, 0x7f68, 0x0005, 0xac9a,
+	0xac9a, 0xac9a, 0xac9a, 0xac9c, 0xacbc, 0xac9a, 0xac9a, 0xac9a,
+	0xac9a, 0xac9a, 0x080c, 0x0cf1, 0x00d6, 0x2c68, 0x080c, 0x7ec8,
+	0x01b0, 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, 0x026e, 0x210c,
+	0x613a, 0x2009, 0x026f, 0x210c, 0x613e, 0x600b, 0xffff, 0x6910,
+	0x6112, 0x6023, 0x0004, 0x080c, 0x6886, 0x080c, 0x6d42, 0x2d60,
+	0x080c, 0x7f1e, 0x00de, 0x0005, 0x080c, 0x7f1e, 0x0005, 0x00e6,
+	0x6010, 0x2070, 0x7000, 0xd0ec, 0x00ee, 0x0005, 0x2009, 0x1172,
+	0x210c, 0xd1ec, 0x0578, 0x6003, 0x0002, 0x6024, 0xc0e5, 0x6026,
+	0xd0cc, 0x0150, 0x2001, 0x12a8, 0x2004, 0x6042, 0x2009, 0x1172,
+	0x210c, 0xd1f4, 0x11e8, 0x0080, 0x2009, 0x1172, 0x210c, 0xd1f4,
+	0x0128, 0x6024, 0xc0e4, 0x6026, 0x9006, 0x00a0, 0x2001, 0x12a8,
+	0x200c, 0x8103, 0x9100, 0x6042, 0x6010, 0x9088, 0x002b, 0x2104,
+	0x9005, 0x0118, 0x9088, 0x0003, 0x0cd0, 0x2c0a, 0x600f, 0x0000,
+	0x9085, 0x0001, 0x0005, 0x0016, 0x00c6, 0x00e6, 0x6154, 0x92f0,
+	0x002b, 0x2e04, 0x2060, 0x8cff, 0x0180, 0x84ff, 0x1118, 0x6054,
+	0x9106, 0x1138, 0x600c, 0x2072, 0x080c, 0x66ae, 0x080c, 0x7f1e,
+	0x0010, 0x9cf0, 0x0003, 0x2e64, 0x0c70, 0x00ee, 0x00ce, 0x001e,
+	0x0005, 0x00d6, 0x6010, 0x90e8, 0x002b, 0x2d04, 0x9005, 0x0140,
+	0x9c06, 0x0120, 0x2d04, 0x90e8, 0x0003, 0x0cb8, 0x600c, 0x206a,
+	0x00de, 0x0005, 0x0026, 0x0036, 0x0156, 0x2011, 0x1127, 0x2204,
+	0x9084, 0x00ff, 0x2019, 0x026e, 0x2334, 0x9636, 0x11d8, 0x8318,
+	0x2334, 0x2204, 0x9084, 0xff00, 0x9636, 0x11a0, 0x2011, 0x0270,
+	0x20a9, 0x0004, 0x6010, 0x9098, 0x000a, 0x080c, 0x8a45, 0x1150,
+	0x2011, 0x0274, 0x20a9, 0x0004, 0x6010, 0x9098, 0x0006, 0x080c,
+	0x8a45, 0x1100, 0x015e, 0x003e, 0x002e, 0x0005, 0x00e6, 0x2071,
+	0x1100, 0x080c, 0x46bb, 0x080c, 0x23cd, 0x00ee, 0x0005, 0x00e6,
+	0x6010, 0x2070, 0x7000, 0xd0fc, 0x0108, 0x0011, 0x00ee, 0x0005,
+	0x6880, 0xc0e5, 0x6882, 0x0005, 0x00e6, 0x00c6, 0x0076, 0x0066,
+	0x0056, 0x0046, 0x0026, 0x0016, 0x0126, 0x2091, 0x8000, 0x2029,
+	0x12e5, 0x252c, 0x2021, 0x12eb, 0x2424, 0x2061, 0x15c0, 0x2071,
+	0x1100, 0x7644, 0x7064, 0x9606, 0x0578, 0x6720, 0x9786, 0x0001,
+	0x0118, 0x9786, 0x0008, 0x1500, 0x2500, 0x9c06, 0x01e8, 0x2400,
+	0x9c06, 0x01d0, 0x080c, 0xaaf2, 0x01b8, 0x080c, 0xab02, 0x11a0,
+	0x6000, 0x9086, 0x0004, 0x1120, 0x0016, 0x080c, 0x12c7, 0x001e,
+	0x080c, 0x97bc, 0x1110, 0x080c, 0x25d1, 0x080c, 0x97cd, 0x1110,
+	0x080c, 0x8576, 0x080c, 0x97a3, 0x9ce0, 0x0018, 0x2001, 0x1116,
+	0x2004, 0x9c02, 0x1208, 0x0858, 0x012e, 0x001e, 0x002e, 0x004e,
+	0x005e, 0x006e, 0x007e, 0x00ce, 0x00ee, 0x0005, 0x0126, 0x0006,
+	0x00e6, 0x2091, 0x8000, 0x2071, 0x1140, 0xd5a4, 0x0118, 0x7034,
+	0x8000, 0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac,
+	0x0118, 0x2071, 0x114a, 0x0451, 0x00ee, 0x000e, 0x012e, 0x0005,
+	0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, 0x1140, 0xd5a4,
+	0x0118, 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0118, 0x7030, 0x8000,
+	0x7032, 0xd5ac, 0x0118, 0x2071, 0x114a, 0x0081, 0x00ee, 0x000e,
+	0x012e, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071,
+	0x1142, 0x0021, 0x00ee, 0x000e, 0x012e, 0x0005, 0x2e04, 0x8000,
+	0x2072, 0x1220, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x0005, 0x00e6,
+	0x2071, 0x1140, 0x0c99, 0x00ee, 0x0005, 0x00e6, 0x2071, 0x1144,
+	0x0c69, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000,
+	0x2071, 0x1140, 0x7044, 0x8000, 0x7046, 0x00ee, 0x000e, 0x012e,
+	0x0005, 0x8064, 0x0008, 0x0010, 0x0000, 0x8066, 0x0000, 0x0101,
+	0x0008, 0x4404, 0x0003, 0x8060, 0x0000, 0x0400, 0x0000, 0x580a,
+	0x0003, 0x791e, 0x0003, 0x507c, 0x0003, 0x4c07, 0x000b, 0xbac0,
+	0x0009, 0x0082, 0x0008, 0x0c07, 0x0003, 0x15fe, 0x0008, 0x3407,
+	0x000b, 0x808c, 0x0008, 0x0001, 0x0000, 0x0000, 0x0007, 0x4047,
+	0x000a, 0x808c, 0x0008, 0x0002, 0x0000, 0x0819, 0x000b, 0x4022,
+	0x0000, 0x001a, 0x0003, 0x4122, 0x0008, 0x0bfe, 0x0008, 0x11a0,
+	0x0001, 0x11a5, 0x000b, 0x0ca0, 0x0001, 0x11a5, 0x000b, 0x9180,
+	0x0001, 0x0005, 0x0008, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0019,
+	0x0000, 0x4424, 0x000b, 0x0240, 0x0002, 0x099f, 0x000b, 0x00fe,
+	0x0000, 0x31a2, 0x000b, 0x112a, 0x0000, 0x002e, 0x0008, 0x022c,
+	0x0008, 0x3a44, 0x0002, 0x0c07, 0x0003, 0x1734, 0x0000, 0x1530,
+	0x0000, 0x1632, 0x0008, 0x0d2a, 0x0008, 0x9a80, 0x0009, 0x000f,
+	0x0008, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0011, 0x0008, 0x4437,
+	0x0003, 0x808c, 0x0008, 0x0002, 0x0000, 0x01fe, 0x0008, 0x42e0,
+	0x0009, 0x0d98, 0x000b, 0x00fe, 0x0000, 0x43e0, 0x0001, 0x0d98,
+	0x000b, 0x9880, 0x0001, 0x0010, 0x0000, 0x7f62, 0x0008, 0x8066,
+	0x0000, 0x1e0a, 0x0008, 0x4445, 0x0003, 0x808a, 0x0008, 0x0003,
+	0x0008, 0x9a80, 0x0009, 0x0002, 0x0000, 0x7f62, 0x0008, 0x584b,
+	0x0003, 0x8066, 0x0000, 0x3679, 0x0000, 0x444e, 0x000b, 0x584f,
+	0x000b, 0x8054, 0x0008, 0x0011, 0x0008, 0x8074, 0x0000, 0x1010,
+	0x0008, 0x1efe, 0x0000, 0x3007, 0x0003, 0x0058, 0x000c, 0x0007,
+	0x0003, 0x1cfe, 0x0008, 0x1b80, 0x0009, 0x7f62, 0x0008, 0x8066,
+	0x0000, 0x0231, 0x0008, 0x445d, 0x0003, 0x585e, 0x000b, 0x0140,
+	0x0008, 0x0140, 0x0008, 0x0242, 0x0000, 0x0242, 0x0000, 0x1f43,
+	0x0002, 0x0c6e, 0x0003, 0x0d44, 0x0000, 0x0d44, 0x0000, 0x0d46,
+	0x0008, 0x0d46, 0x0008, 0x0348, 0x0008, 0x0348, 0x0008, 0x044a,
+	0x0008, 0x044a, 0x0008, 0x0076, 0x0003, 0x0344, 0x0008, 0x0344,
+	0x0008, 0x0446, 0x0008, 0x0446, 0x0008, 0x0548, 0x0008, 0x0548,
+	0x0008, 0x064a, 0x0000, 0x064a, 0x0000, 0x5876, 0x000b, 0x8054,
+	0x0008, 0x0001, 0x0000, 0x8074, 0x0000, 0x2020, 0x0008, 0x4000,
+	0x000f, 0x3a40, 0x000a, 0x0c0a, 0x000b, 0x2b24, 0x0008, 0x2b24,
+	0x0008, 0x5880, 0x000b, 0x8054, 0x0008, 0x0002, 0x0000, 0x1242,
+	0x0002, 0x08ca, 0x0003, 0x3a45, 0x000a, 0x08bb, 0x0003, 0x1e10,
+	0x000a, 0x7f3c, 0x0000, 0x08b8, 0x0003, 0x1d00, 0x0002, 0x7f3a,
+	0x0000, 0x0d60, 0x0000, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0009,
+	0x0008, 0x4490, 0x000b, 0x8060, 0x0000, 0x0400, 0x0000, 0x00fe,
+	0x0000, 0x34b5, 0x000b, 0x1cfe, 0x0008, 0xff80, 0x0009, 0x0001,
+	0x0000, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0009, 0x0008, 0x449b,
+	0x0003, 0x00fe, 0x0000, 0x318b, 0x0003, 0x0038, 0x0000, 0x00fe,
+	0x0000, 0xff80, 0x0009, 0x0019, 0x0000, 0x7f62, 0x0008, 0x8066,
+	0x0000, 0x0009, 0x0008, 0x44a5, 0x000b, 0x80c0, 0x0009, 0x00ff,
+	0x0008, 0x7f3e, 0x0008, 0x0d60, 0x0000, 0x0efe, 0x0008, 0x1f80,
+	0x0001, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0009, 0x0008, 0x44af,
+	0x000b, 0x8060, 0x0000, 0x0400, 0x0000, 0x003a, 0x0008, 0x1dfe,
+	0x0000, 0x008c, 0x0003, 0x0036, 0x0008, 0x0058, 0x000c, 0x00ca,
+	0x000b, 0x8074, 0x0000, 0x2000, 0x0000, 0x00ca, 0x000b, 0x3a44,
+	0x0002, 0x09a8, 0x0003, 0x8074, 0x0000, 0x1000, 0x0000, 0x2d0e,
+	0x0000, 0x2d0e, 0x0000, 0x358b, 0x000b, 0x26fe, 0x0008, 0x26fe,
+	0x0008, 0x2700, 0x0008, 0x2700, 0x0008, 0x00d0, 0x0009, 0x0cd8,
+	0x000b, 0x8074, 0x0000, 0x4040, 0x0008, 0x58ca, 0x0003, 0x507c,
+	0x0003, 0x3a46, 0x000a, 0x0cd8, 0x000b, 0x3a47, 0x0002, 0x08d5,
+	0x000b, 0x8054, 0x0008, 0x0004, 0x0000, 0x8074, 0x0000, 0x8000,
+	0x0000, 0x0112, 0x0003, 0x92c0, 0x0009, 0x0f88, 0x0008, 0x0807,
+	0x000b, 0x9a80, 0x0009, 0x0002, 0x0000, 0x7f62, 0x0008, 0x8066,
+	0x0000, 0x362a, 0x0000, 0x44dd, 0x000b, 0x2000, 0x0000, 0x2000,
+	0x0000, 0x2102, 0x0000, 0x2102, 0x0000, 0x2204, 0x0000, 0x2204,
+	0x0000, 0x2306, 0x0000, 0x2306, 0x0000, 0x2408, 0x0000, 0x2408,
+	0x0000, 0x250a, 0x0000, 0x250a, 0x0000, 0x260c, 0x0000, 0x260c,
+	0x0000, 0x270e, 0x0000, 0x270e, 0x0000, 0x2810, 0x0000, 0x2810,
+	0x0000, 0x2912, 0x0000, 0x2912, 0x0000, 0x9a80, 0x0009, 0x0007,
+	0x0000, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0052, 0x0000, 0x44f7,
+	0x0003, 0x92c0, 0x0009, 0x0780, 0x0008, 0x0d92, 0x000b, 0x124b,
+	0x0002, 0x0900, 0x000b, 0x2e4d, 0x0002, 0x2e4d, 0x0002, 0x098b,
+	0x000b, 0x5900, 0x000b, 0x8054, 0x0008, 0x0004, 0x0000, 0x3a46,
+	0x000a, 0x0d0d, 0x000b, 0x1243, 0x000a, 0x0910, 0x0003, 0x8010,
+	0x0008, 0x000d, 0x0000, 0x017c, 0x0004, 0x1810, 0x0000, 0x017c,
+	0x0004, 0x0110, 0x000b, 0x0173, 0x0004, 0x1810, 0x0000, 0x017c,
+	0x0004, 0x8074, 0x0000, 0xf000, 0x0008, 0x3a42, 0x0002, 0x0d18,
+	0x0003, 0x15fe, 0x0008, 0x342e, 0x0003, 0x0d30, 0x0000, 0x0007,
+	0x0003, 0x8074, 0x0000, 0x0501, 0x0000, 0x8010, 0x0008, 0x000c,
+	0x0008, 0x017c, 0x0004, 0x0007, 0x0003, 0xbbe0, 0x0009, 0x0030,
+	0x0008, 0x0d2e, 0x0003, 0x18fe, 0x0000, 0x3ce0, 0x0009, 0x092b,
+	0x000b, 0x15fe, 0x0008, 0x3ce0, 0x0009, 0x092b, 0x000b, 0x016e,
+	0x0004, 0x8076, 0x0008, 0x0040, 0x0000, 0x016b, 0x000b, 0x8076,
+	0x0008, 0x0041, 0x0008, 0x016b, 0x000b, 0xbbe0, 0x0009, 0x0032,
+	0x0000, 0x0d33, 0x0003, 0x3c1e, 0x0008, 0x016b, 0x000b, 0xbbe0,
+	0x0009, 0x0037, 0x0000, 0x0d50, 0x0003, 0x18fe, 0x0000, 0x3ce0,
+	0x0009, 0x0d2b, 0x0003, 0x1afe, 0x0008, 0xff80, 0x0009, 0x000d,
+	0x0000, 0x7f62, 0x0008, 0x2604, 0x0008, 0x2604, 0x0008, 0x2706,
+	0x0008, 0x2706, 0x0008, 0x2808, 0x0000, 0x2808, 0x0000, 0x290a,
+	0x0000, 0x290a, 0x0000, 0x8066, 0x0000, 0x0422, 0x0000, 0x4547,
+	0x0003, 0x0173, 0x0004, 0x8054, 0x0008, 0x0004, 0x0000, 0x8074,
+	0x0000, 0xf000, 0x0008, 0x8072, 0x0000, 0x8000, 0x0000, 0x0112,
+	0x0003, 0xbbe0, 0x0009, 0x0038, 0x0000, 0x0d62, 0x000b, 0x18fe,
+	0x0000, 0x3ce0, 0x0009, 0x095f, 0x000b, 0x15fe, 0x0008, 0x3ce0,
+	0x0009, 0x0d27, 0x0003, 0x016e, 0x0004, 0x8076, 0x0008, 0x0040,
+	0x0000, 0x8072, 0x0000, 0x8000, 0x0000, 0x019f, 0x0003, 0x8076,
+	0x0008, 0x0042, 0x0008, 0x016b, 0x000b, 0xbbe0, 0x0009, 0x0016,
+	0x0000, 0x0d6b, 0x000b, 0x3a44, 0x0002, 0x0c09, 0x000b, 0x8072,
+	0x0000, 0x8000, 0x0000, 0x8000, 0x000f, 0x0007, 0x0003, 0x8072,
+	0x0000, 0x8000, 0x0000, 0x0007, 0x0003, 0x3d30, 0x000a, 0x7f00,
+	0x0000, 0xbc80, 0x0001, 0x0007, 0x0000, 0x0177, 0x0003, 0x1930,
+	0x000a, 0x7f00, 0x0000, 0x9880, 0x0001, 0x0007, 0x0000, 0x7f62,
+	0x0008, 0x8066, 0x0000, 0x000a, 0x0008, 0x457a, 0x000b, 0x4000,
+	0x000f, 0x217c, 0x0003, 0x0870, 0x0008, 0x4000, 0x000f, 0xbac0,
+	0x0009, 0x0090, 0x0008, 0x0985, 0x0003, 0x8074, 0x0000, 0x0706,
+	0x0000, 0x0187, 0x0003, 0x8074, 0x0000, 0x0703, 0x0000, 0x4000,
+	0x000f, 0x8010, 0x0008, 0x0008, 0x0000, 0x01ad, 0x000b, 0x0173,
+	0x0004, 0x8010, 0x0008, 0x0007, 0x0000, 0x017c, 0x0004, 0x1810,
+	0x0000, 0x017c, 0x0004, 0x01b7, 0x0003, 0x8010, 0x0008, 0x0009,
+	0x0008, 0x01ad, 0x000b, 0x8010, 0x0008, 0x0005, 0x0008, 0x01ad,
+	0x000b, 0x808c, 0x0008, 0x0001, 0x0000, 0x8010, 0x0008, 0x0004,
+	0x0000, 0x4143, 0x000a, 0x0840, 0x000b, 0x01ad, 0x000b, 0x8010,
+	0x0008, 0x0003, 0x0008, 0x01af, 0x0003, 0x8010, 0x0008, 0x000b,
+	0x0000, 0x01af, 0x0003, 0x8010, 0x0008, 0x0002, 0x0000, 0x01af,
+	0x0003, 0x3a47, 0x0002, 0x0cca, 0x000b, 0x8010, 0x0008, 0x0006,
+	0x0008, 0x01af, 0x0003, 0x8074, 0x0000, 0xf000, 0x0008, 0x017c,
+	0x0004, 0x017f, 0x0004, 0x3a40, 0x000a, 0x0807, 0x000b, 0x8010,
+	0x0008, 0x000c, 0x0008, 0x017c, 0x0004, 0x0007, 0x0003, 0x8074,
+	0x0000, 0xf080, 0x0000, 0x0d30, 0x0000, 0x2e4d, 0x0002, 0x2e4d,
+	0x0002, 0x09c0, 0x000b, 0x8054, 0x0008, 0x0019, 0x0000, 0x0007,
+	0x0003, 0x8054, 0x0008, 0x0009, 0x0008, 0x0007, 0x0003, 0x0001,
+	0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100,
+	0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0xbb4d
+};
+#ifdef UNIQUE_FW_NAME
+unsigned short fw2300tp_length01 = 0xa9b8;
+#else
+unsigned short risc_code_length01 = 0xa9b8;
+#endif
+
diff -urN linux-2.4.16/drivers/scsi/qla1280.c lia64-2.4/drivers/scsi/qla1280.c
--- linux-2.4.16/drivers/scsi/qla1280.c	Wed Oct 10 16:32:03 2001
+++ lia64-2.4/drivers/scsi/qla1280.c	Wed Oct 10 16:35:07 2001
@@ -1,162 +1,110 @@
 /********************************************************************************
- *                  QLOGIC LINUX SOFTWARE
- *
- * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.X).
- *
- * COPYRIGHT (C) 1999-2000 QLOGIC CORPORATION    
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the Qlogic's Linux Software License. See below.
- *
- * This program is WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistribution's or source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- ********************************************************************************/
- 
-/*****************************************************************************************
-			QLOGIC CORPORATION SOFTWARE
-           "GNU" GENERAL PUBLIC LICENSE
-    TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION
-                 AND MODIFICATION
-
-This GNU General Public License ("License") applies solely to QLogic Linux 
-Software ("Software") and may be distributed under the terms of this License.  
- 
-1. You may copy and distribute verbatim copies of the Software's source code as 
-you receive it, in any medium, provided that you conspicuously and appropriately 
-publish on each copy an appropriate copyright notice and disclaimer of warranty;
-keep intact all the notices that refer to this License and to the absence of any
-warranty; and give any other recipients of the Software a copy of this License along
-with the Software. 
-
-You may charge a fee for the physical act of transferring a copy, and you may at your
-option offer warranty protection in exchange for a fee.
- 
-2. You may modify your copy or copies of the Software or any portion of it, thus forming
-a work based on the Software, and copy and distribute such modifications or work under
-the terms of Section 1 above, provided that you also meet all of these conditions:
- 
-* a) You must cause the modified files to carry prominent notices stating that you
-changed the files and the date of any change. 
-
-* b) You must cause any work that you distribute or publish that in whole or in part
-contains or is derived from the Software or any part thereof, to be licensed as a
-whole at no charge to all third parties under the terms of this License. 
-
-* c) If the modified Software normally reads commands interactively when run, you
-must cause it, when started running for such interactive use in the most ordinary way,
-to print or display an announcement including an appropriate copyright notice and a 
-notice that there is no warranty (or else, saying that you provide a warranty) and that
-users may redistribute the Software under these conditions, and telling the user how to
-view a copy of this License. (Exception:if the Software itself is interactive but does 
-not normally print such an announcement, your work based on the Software is not required
-to print an announcement.) 
-
-These requirements apply to the modified work as a whole. If identifiable sections of
-that work are not derived from the Software, and can be reasonably considered independent
-and separate works in themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works. But when you distribute the same
-sections as part of a whole which is a work based on the Software, the distribution of the
-whole must be on the terms of this License, whose permissions for other licensees extend
-to the entire whole, and thus to each and every part regardless of who wrote it. 
-
-3. You may copy and distribute the Software (or a work based on it, under Section 2) in 
-object code or executable form under the terms of Sections 1 and 2 above provided that
-you also do one of the following: 
-
-* a) Accompany it with the complete corresponding machine-readable source code, which must
-be distributed under the terms of Sections 1 and 2 above on a medium customarily used for
-software interchange; or, 
-
-* b) Accompany it with a written offer, valid for at least three years, to give any third
-party, for a charge no more than your cost of physically performing source distribution,
-a complete machine-readable copy of the corresponding source code, to be distributed under
-the terms of Sections 1 and 2 above on a medium customarily used for software interchange;
-or,
-
-* c) Accompany it with the information you received as to the offer to distribute 
-corresponding source code. (This alternative is allowed only for noncommercial distribution
-and only if you received the Software in object code or executable form with such an offer,
-in accord with Subsection b above.) 
-
-The source code for a work means the preferred form of the work for making modifications
-to it. For an executable work, complete source code means all the source code for all 
-modules it contains, plus any associated interface definition files, plus the scripts used
-to control compilation and installation of the executable.     
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-If distribution of executable or object code is made by offering access to copy from a 
-designated place, then offering equivalent access to copy the source code from the same
-place counts as distribution of the source code, even though third parties are not 
-compelled to copy the source along with the object code. 
-
-4. You may not copy, modify, sublicense, or distribute the Software except as expressly 
-provided under this License. Any attempt otherwise to copy, modify, sublicense or 
-distribute the Software is void, and will automatically terminate your rights under this
-License. However, parties who have received copies, or rights, from you under this License
-will not have their licenses terminated so long as such parties remain in full compliance. 
-
-5. This license grants you world wide, royalty free non-exclusive rights to modify or 
-distribute the Software or its derivative works. These actions are prohibited by law 
-if you do not accept this License. Therefore, by modifying or distributing the Software
-(or any work based on the Software), you indicate your acceptance of this License to do
-so, and all its terms and conditions for copying, distributing or modifying the Software
-or works based on it.
- 
-6. Each time you redistribute the Software (or any work based on the Software), the 
-recipient automatically receives a license from the original licensor to copy, distribute
-or modify the Software subject to these terms and conditions. You may not impose any 
-further restrictions on the recipients' exercise of the rights granted herein. You are
-not responsible for enforcing compliance by third parties to this License.
- 
-7. If, as a consequence of a court judgment or allegation of patent infringement or for
-any other reason (not limited to patent issues), conditions are imposed on you 
-(whether by court order, agreement or otherwise) that contradict the conditions of this
-License, they do not excuse you from the conditions of this License. If you cannot 
-distribute so as to satisfy simultaneously your obligations under this License 
-and any other pertinent obligations, then as a consequence you may not distribute the
-Software at all.    
-
-If any portion of this section is held invalid or unenforceable under any particular 
-circumstance, the balance of the section is intended to apply and the section as a whole
-is intended to apply in other circumstances. 
-NO WARRANTY
-
-11. THE SOFTWARE IS PROVIDED WITHOUT A WARRANTY OF ANY KIND. THERE IS NO 
-WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. 
-EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR 
-OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, 
-EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 
-ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU. 
-SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 
-NECESSARY SERVICING, REPAIR OR CORRECTION.
- 
-12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 
-REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 
-DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 
-DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING 
-BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR 
-LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO 
-OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS 
-BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
-END OF TERMS AND CONDITIONS 
-
-*******************************************************************************************/ 
-
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic  QLA1280 (Ultra2)  and  QLA12160 (Ultra3) SCSI driver
+* Copyright (C) 2000 Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+**
+******************************************************************************/
+#define QLA1280_VERSION      "3.23 Beta"
 /****************************************************************************
     Revision History:
-    Rev. 3.00       Jan 17, 1999    DG  Qlogic
+    Rev  3.23 Beta January 11, 2001 BN Qlogic
+        - Added check of device_id when handling non 
+          QLA12160s during detect().
+    Rev  3.22 Beta January 5, 2001 BN Qlogic
+        - Changed queue_task() to schedule_task()
+          for kernels 2.4.0 and higher. 
+          Note: 2.4.0-testxx kernels released prior to
+                the actual 2.4.0 kernel release on January 2001
+                will get compile/link errors with schedule_task().
+                Please update your kernel to released 2.4.0 level,
+                or comment lines in this file flagged with  3.22 
+                to resolve compile/link error of schedule_task().
+        - Added -DCONFIG_SMP in addition to -D__SMP__ 
+          in Makefile for 2.4.0 builds of driver as module.
+    Rev  3.21 Beta January 4, 2001 BN Qlogic
+        - Changed criteria of 64/32 Bit mode of HBA
+          operation according to BITS_PER_LONG rather
+          than HBA's NVRAM setting of >4Gig memory bit;
+          so that the HBA auto-configures without the need
+          to setup each system individually.
+    Rev  3.20 Beta December 5, 2000 BN Qlogic
+        - Added priority handling to IA-64  onboard SCSI
+          ISP12160 chip for kernels greater than 2.3.18.
+        - Added irqrestore for qla1280_intr_handler.
+        - Enabled /proc/scsi/qla1280 interface.
+        - Clear /proc/scsi/qla1280 counters in detect().
+    Rev  3.19 Beta October 13, 2000 BN Qlogic
+        - Declare driver_template for new kernel
+          (2.4.0 and greater) scsi initialization scheme.
+        - Update /proc/scsi entry for 2.3.18 kernels and
+          above as qla1280
+    Rev  3.18 Beta October 10, 2000 BN Qlogic
+        - Changed scan order of adapters to map 
+          the QLA12160 followed by the QLA1280.
+    Rev  3.17 Beta September 18, 2000 BN Qlogic
+        - Removed warnings for 32 bit 2.4.x compiles
+        - Corrected declared size for request and response
+          DMA addresses that are kept in each ha
+    Rev. 3.16 Beta  August 25, 2000   BN  Qlogic
+        - Corrected 64 bit addressing issue on IA-64
+          where the upper 32 bits were not properly
+          passed to the RISC engine.
+    Rev. 3.15 Beta  August 22, 2000   BN  Qlogic
+        - Modified qla1280_setup_chip to properly load
+          ISP firmware for greater that 4 Gig memory on IA-64
+    Rev. 3.14 Beta  August 16, 2000   BN  Qlogic
+        - Added setting of dma_mask to full 64 bit
+          if flags.enable_64bit_addressing is set in NVRAM
+    Rev. 3.13 Beta  August 16, 2000   BN  Qlogic
+        - Use new PCI DMA mapping APIs for 2.4.x kernel
+    Rev. 3.12       July 18, 2000    Redhat & BN Qlogic
+        - Added check of pci_enable_device to detect() for 2.3.x
+        - Use pci_resource_start() instead of 
+          pdev->resource[0].start in detect() for 2.3.x
+        - Updated driver version
+    Rev. 3.11       July 14, 2000    BN  Qlogic
+	- Updated SCSI Firmware to following versions:
+	  qla1x80:   8.13.08
+	  qla1x160:  10.04.08
+	- Updated driver version to 3.11
+    Rev. 3.10    June 23, 2000   BN Qlogic
+        - Added filtering of AMI SubSys Vendor ID devices 
+    Rev. 3.9 
+        - DEBUG_QLA1280 undefined and  new version  BN Qlogic 
+    Rev. 3.08b      May 9, 2000    MD Dell
+        - Added logic to check against AMI subsystem vendor ID
+	Rev. 3.08       May 4, 2000    DG  Qlogic
+        - Added logic to check for PCI subsystem ID.
+	Rev. 3.07       Apr 24, 2000    DG & BN  Qlogic
+	   - Updated SCSI Firmware to following versions:
+	     qla12160:   10.01.19
+		 qla1280:     8.09.00
+	Rev. 3.06       Apr 12, 2000    DG & BN  Qlogic
+	   - Internal revision; not released
+    Rev. 3.05       Mar 28, 2000    DG & BN  Qlogic
+       - Edit correction for virt_to_bus and PROC.
+    Rev. 3.04       Mar 28, 2000    DG & BN  Qlogic
+       - Merge changes from ia64 port.
+    Rev. 3.03       Mar 28, 2000    BN  Qlogic
+       - Increase version to reflect new code drop with compile fix
+         of issue with inclusion of linux/spinlock for 2.3 kernels
+    Rev. 3.02       Mar 15, 2000    BN  Qlogic
+       - Merge qla1280_proc_info from 2.10 code base
+    Rev. 3.01       Feb 10, 2000    BN  Qlogic
+       - Corrected code to compile on a 2.2.x kernel.
+    Rev. 3.00       Jan 17, 2000    DG  Qlogic
 	   - Added 64-bit support.
     Rev. 2.07       Nov 9, 1999     DG  Qlogic
 	   - Added new routine to set target parameters for ISP12160. 
@@ -183,12 +131,11 @@
 *****************************************************************************/
 
 
+#include <linux/config.h>       
 #ifdef MODULE
 #include <linux/module.h>
 #endif
 
-#define QLA1280_VERSION      " 3.00-Beta"
-
 #include <stdarg.h>
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -207,8 +154,16 @@
 #include <linux/proc_fs.h>
 #include <linux/blk.h>
 #include <linux/tqueue.h>
-/* MRS #include <linux/tasks.h> */
+#ifndef KERNEL_VERSION
+#  define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
+#endif
+ 
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+#include <linux/pci_ids.h>
+#endif
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+#include <linux/tasks.h>
 # include <linux/bios32.h>
 #endif
 #include "sd.h"
@@ -216,23 +171,16 @@
 #include "hosts.h"
 #define UNIQUE_FW_NAME
 #include "qla1280.h"
-#include "ql12160_fw.h"                     /* ISP RISC code */
+#include "ql12160_fw.h"   /* ISP RISC codes */
 #include "ql1280_fw.h"
 
 #include <linux/stat.h>
-#include <linux/slab.h>        /* for kmalloc() */
-
-
-#ifndef KERNEL_VERSION
-#  define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
-#endif
-
+#include <linux/slab.h> 
 
 /*
  * Compile time Options: 
  *            0 - Disable and 1 - Enable 
  */
-#define  QLA1280_64BIT_SUPPORT         1   /* 64-bit Support */
 #define  QL1280_TARGET_MODE_SUPPORT    0   /* Target mode support */
 #define  WATCHDOGTIMER                 0
 #define  MEMORY_MAPPED_IO              0
@@ -244,15 +192,9 @@
 #define  AUTO_ESCALATE_ABORT           0   /* Automatically escalate aborts */
 #define  STOP_ON_ERROR                 0   /* Stop on aborts and resets  */
 #define  STOP_ON_RESET                 0 
-#define  STOP_ON_ABORT                 0 
-#undef   DYNAMIC_MEM_ALLOC
-
-#define  DEBUG_QLA1280                 0    /* Debugging  */
-/* #define CHECKSRBSIZE */
-
-/*
- * These macros to assist programming
- */
+#define  STOP_ON_ABORT                 0
+#define  QLA1280_PROFILE               1   /* 3.20 */ 
+#define  DEBUG_QLA1280                 0
 
 #define	BZERO(ptr, amt)		memset(ptr, 0, amt)
 #define	BCOPY(src, dst, amt)	memcpy(dst, src, amt)
@@ -260,19 +202,28 @@
 #define	KMFREE(ip,siz)	kfree((ip))
 #define	SYS_DELAY(x)		udelay(x);barrier()
 #define QLA1280_DELAY(sec)  mdelay(sec * 1000)
-#define VIRT_TO_BUS(a) virt_to_bus((a))
-#if  QLA1280_64BIT_SUPPORT
+
+/* 3.16 */
+#if  BITS_PER_LONG > 32
+#define pci_dma_lo32(a) (a & 0xffffffff)
+#define pci_dma_hi32(a) ((a >> 32) & 0xffffffff)
+#else
+#define pci_dma_lo32(a) (a & 0xffffffff)
+#define pci_dma_hi32(a) 0
+#endif
+
+#define  VIRT_TO_BUS(a)  virt_to_bus(((void *)a))
+
 #if  BITS_PER_LONG <= 32
-#define  VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus((a))
+#define  VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus(((void *)a))
 #define  VIRT_TO_BUS_HIGH(a) (uint32_t)(0x0)
 #else
-#define  VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((a)))
-#define  VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((a))>>32))
+#define  VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((void *)(a)))
+#define  VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((void *)(a))>>32))
 #endif
-#endif  /* QLA1280_64BIT_SUPPORT */
 
-#define STATIC     
 
+#define STATIC     
 #define NVRAM_DELAY() udelay(500) /* 2 microsecond delay */
 void qla1280_device_queue_depth(scsi_qla_host_t *, Scsi_Device *);
 
@@ -285,11 +236,11 @@
 #define  LSB(x)          (uint8_t)(x)
 
 #if  BITS_PER_LONG <= 32
-#define  LS_64BITS(x) (uint32_t)(x)
-#define  MS_64BITS(x) (uint32_t)(0x0)
+#define  LS_64BITS(x) (uint32_t)((unsigned long) x)
+#define  MS_64BITS(x) (uint32_t)((unsigned long) 0x0)
 #else
-#define  LS_64BITS(x) (uint32_t)(0xffffffff & (x))
-#define  MS_64BITS(x) (uint32_t)(0xffffffff & ((x)>>32) )
+#define  LS_64BITS(x) (uint32_t)(0xffffffff & ((unsigned long)x))
+#define  MS_64BITS(x) (uint32_t)(0xffffffff & (((unsigned long)x)>>32) )
 #endif
 
 /*
@@ -300,9 +251,6 @@
 STATIC void   qla1280_putq_t(scsi_lu_t *, srb_t *);
 STATIC void   qla1280_done_q_put(srb_t *, srb_t **, srb_t **);
 STATIC void qla1280_select_queue_depth(struct Scsi_Host *, Scsi_Device *);
-#ifdef  QLA1280_UNUSED 
-static void qla1280_dump_regs(struct Scsi_Host *host);
-#endif
 #if  STOP_ON_ERROR 
 static void qla1280_panic(char *, struct Scsi_Host *host);
 #endif
@@ -312,10 +260,7 @@
 STATIC int qla1280_return_status( sts_entry_t *sts, Scsi_Cmnd       *cp);
 STATIC void qla1280_removeq(scsi_lu_t *q, srb_t *sp);
 STATIC void qla1280_mem_free(scsi_qla_host_t *ha);
-static void qla1280_do_dpc(void *p);
-#ifdef  QLA1280_UNUSED 
-static void qla1280_set_flags(char * s);
-#endif
+void qla1280_do_dpc(void *p);
 static char	*qla1280_get_token(char *, char *);
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)
 STATIC inline void mdelay(int);
@@ -339,9 +284,7 @@
 STATIC uint8_t   qla1280_device_reset(scsi_qla_host_t *, uint8_t, uint32_t);
 STATIC uint8_t   qla1280_abort_device(scsi_qla_host_t *, uint8_t, uint32_t, uint32_t);
 STATIC uint8_t   qla1280_abort_command(scsi_qla_host_t *, srb_t *),
-#if  QLA1280_64BIT_SUPPORT
                  qla1280_64bit_start_scsi(scsi_qla_host_t *, srb_t *),
-#endif
                  qla1280_32bit_start_scsi(scsi_qla_host_t *, srb_t *),
                  qla1280_abort_isp(scsi_qla_host_t *);
 STATIC void      qla1280_nv_write(scsi_qla_host_t *, uint16_t),
@@ -374,12 +317,12 @@
                  qla1280_notify_ack(scsi_qla_host_t *, notify_entry_t *),
                  qla1280_immed_notify(scsi_qla_host_t *, notify_entry_t *),
                  qla1280_accept_io(scsi_qla_host_t *, ctio_ret_entry_t *),
-#if  QLA1280_64BIT_SUPPORT
-                 qla1280_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t,
-                                     paddr32_t *),
-#endif
-                 qla1280_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t,
-                                     paddr32_t *),
+                 qla1280_64bit_continue_io(scsi_qla_host_t *, 
+                                 atio_entry_t *, uint32_t,
+                                 paddr32_t *),
+                 qla1280_32bit_continue_io(scsi_qla_host_t *, 
+                                 atio_entry_t *, uint32_t,
+                                 paddr32_t *),
                  qla1280_atio_entry(scsi_qla_host_t *, atio_entry_t *),
                  qla1280_notify_entry(scsi_qla_host_t *, notify_entry_t *);
 #endif  /* QLA1280_TARGET_MODE_SUPPORT */
@@ -400,7 +343,7 @@
                 qla1280_dump_buffer(caddr_t, uint32_t);
 
 char          debug_buff[80];
-#if DEBUG_QLA1280 
+#if  DEBUG_QLA1280 
 STATIC uint8_t ql_debug_print = 1;
 #else
 STATIC uint8_t ql_debug_print = 0;
@@ -426,6 +369,22 @@
 
 #endif
 
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+/*
+ * Our directory Entry in /proc/scsi for the user to 
+ * access the driver. 
+ */
+/* Need to add in proc_fs.h     PROC_SCSI_QL1280 */
+#define PROC_SCSI_QL1280  PROC_SCSI_QLOGICISP
+
+struct proc_dir_entry proc_scsi_qla1280 = {
+    PROC_SCSI_QL1280, 7, "qla1280",                           
+    S_IFDIR | S_IRUGO | S_IXUGO, 2,
+    0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+};
+#endif
+
 /* We use the Scsi_Pointer structure that's included with each command
  * SCSI_Cmnd as a scratchpad for our SRB.
  *
@@ -471,17 +430,17 @@
    unsigned char   *fwver;          /* Ptr to F/W version array    */
 } qla_boards_t;
 
-struct _qlaboards   QLBoardTbl[NUM_OF_ISP_DEVICES] = 
+struct _qlaboards   QL1280BoardTbl[NUM_OF_ISP_DEVICES] = 
 {
    /* Name ,  Board PCI Device ID,         Number of ports */
+  {"QLA12160 ", QLA12160_DEVICE_ID,          2,      
+               &fw12160i_code01[0],  (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] },       
   {"QLA1080 ", QLA1080_DEVICE_ID,           1,        
                &fw1280ei_code01[0],  (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] },       
   {"QLA1240 ", QLA1240_DEVICE_ID,           2,       
                &fw1280ei_code01[0],  (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] },       
   {"QLA1280 ", QLA1280_DEVICE_ID,           2,      
                &fw1280ei_code01[0],  (unsigned long *)&fw1280ei_length01,&fw1280ei_addr01, &fw1280ei_version_str[0] },       
-  {"QLA12160 ", QLA12160_DEVICE_ID,          2,      
-               &fw12160i_code01[0],  (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] },       
   {"QLA10160 ", QLA10160_DEVICE_ID,          1,      
                &fw12160i_code01[0],  (unsigned long *)&fw12160i_length01,&fw12160i_addr01, &fw12160i_version_str[0] },       
   {"        ",                 0,           0}
@@ -489,7 +448,7 @@
 
 static unsigned long qla1280_verbose = 1L;
 static scsi_qla_host_t *qla1280_hostlist = NULL;
-#ifdef QLA1280_PROFILE
+#if QLA1280_PROFILE
 static int qla1280_buffer_size = 0;
 static char *qla1280_buffer = NULL;
 #endif
@@ -567,152 +526,153 @@
  *
  * Returns:
  *************************************************************************/
-#ifdef QLA1280_PROFILE
-#define	PROC_BUF	(&qla1280_buffer[size])
-#define LUN_ID       (targ_lun>>(MAX_T_BITS+MAX_L_BITS)),((targ_lun>>MAX_L_BITS)&0xf), targ_lun&0x7 
-#endif
+#define	PROC_BUF	(&qla1280_buffer[len])
 int
-qla1280_proc_info ( char *buffer, char **start, off_t offset, int length, 
-                    int hostno, int inout)
-{
-#ifdef QLA1280_PROFILE
+qla1280_proc_info( char *buffer, char **start, off_t offset, int length, 
+                    int hostno, int inout) {
+#if QLA1280_PROFILE
   struct Scsi_Host *host;
   scsi_qla_host_t *ha;
   int    size = 0;
-  int  targ_lun;
   scsi_lu_t  *up;
-  int   no_devices;
-
-  printk("Entering proc_info 0x%p,0x%lx,0x%x,0x%x\n",buffer,offset,length,hostno);
+  int   len = 0;
+  qla_boards_t   *bdp; 
+  uint32_t        b, t, l;
+  uint8_t  *temp;
   host = NULL;
-  /* find the host they want to look at */
-  for(ha=qla1280_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next)
+
+    /* Find the host that was specified */
+    for( ha=qla1280_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next )
     ;
 
-  if (!ha)
-  {
-    size += sprintf(buffer, "Can't find adapter for host number %d\n", hostno);
-    if (size > length)
-    {
+    /* if host wasn't found then exit */
+    if( !ha ) {
+        size = sprintf(buffer, "Can't find adapter for host number %d\n", hostno);
+        if( size > length ) {
       return (size);
-    }
-    else
-    {
-      return (length);
+        } else {
+            return (0);
     }
   }
 
   host = ha->host;
-  if (inout == TRUE) /* Has data been written to the file? */ 
-  {
-    return (qla1280_set_info(buffer, length, host));
-  }
 
-  /* compute number of active devices */
-  no_devices = 0;
-  for (targ_lun = 0; targ_lun < MAX_EQ; targ_lun++)
+    if( inout == TRUE ) /* Has data been written to the file? */
   {
-          if( (up = ha->dev[targ_lun]) == NULL )
-              continue;
-          no_devices++;
+        printk("qla1280_proc: has data been written to the file. \n");
+        return (qla1280_set_info(buffer, length, host));
   }
-  /* size = 112 * no_devices; */
-  size = 4096;
-  /* round up to the next page */
   
   /* 
    * if our old buffer is the right size use it otherwise 
    * allocate a new one.
    */
-  if (qla1280_buffer_size != size)
-  {
+    size = 4096;  /* get a page */
+    if( qla1280_buffer_size != size ) {
     /* deallocate this buffer and get a new one */
-    if (qla1280_buffer != NULL) 
-    {
+        if( qla1280_buffer != NULL ) {
       kfree(qla1280_buffer);
       qla1280_buffer_size = 0;
     }
     qla1280_buffer = kmalloc(size, GFP_KERNEL);
   }
-  if (qla1280_buffer == NULL)
-  {
+    if( qla1280_buffer == NULL ) {
     size = sprintf(buffer, "qla1280 - kmalloc error at line %d\n",
         __LINE__);
     return size;
   }
+    /* save the size of our buffer */
   qla1280_buffer_size = size;
 
-  size = 0;
-  size += sprintf(PROC_BUF, "Qlogic 1280/1080 SCSI driver version: ");   /* 43 bytes */
-  size += sprintf(PROC_BUF, "%5s, ", QLA1280_VERSION);                         /* 5        */
-  size += sprintf(PROC_BUF, "Qlogic Firmware version: ");                     /* 25       */
-  size += sprintf(PROC_BUF, "%2d.%2d.%2d",_firmware_version[0],           /* 8        */
-                                          ql12_firmware_version[1],
-                                          ql12_firmware_version[2]);
-  size += sprintf(PROC_BUF, "\n");                                             /* 1       */
-                           
-  size += sprintf(PROC_BUF, "SCSI Host Adapter Information: %s\n", QLBoardTbl[ha->devnum].bdName);
-  size += sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n",
-                        ha->request_dma,
-                        ha->response_dma);
-  size += sprintf(PROC_BUF, "Request Queue count= 0x%x, Response Queue count= 0x%x\n",
+  /* 3.20 clear the buffer we use for proc display */
+  temp = qla1280_buffer;
+  for (b=0 ; b < size; b++)     *(temp+b) = 0; 
+
+    /* start building the print buffer */ 
+    bdp = &QL1280BoardTbl[ha->devnum];
+    size =  sprintf(PROC_BUF,
+            "QLogic PCI to SCSI Adapter for ISP 1280/12160:\n"
+            "        Firmware version: %2d.%02d.%02d, Driver version %s\n",                bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA1280_VERSION);
+
+    len += size;
+
+    size = sprintf(PROC_BUF, "SCSI Host Adapter Information: %s\n", bdp->bdName);
+    len += size;
+    size = sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n",
+                        (unsigned long) ha->request_dma,
+                        (unsigned long) ha->response_dma);
+    len += size;
+    size = sprintf(PROC_BUF, "Request Queue count= 0x%x, Response Queue count= 0x%x\n",
                         REQUEST_ENTRY_CNT,
                         RESPONSE_ENTRY_CNT);
-  size += sprintf(PROC_BUF,"Number of pending commands = 0x%lx\n", ha->actthreads);
-  size += sprintf(PROC_BUF,"Number of queued commands = 0x%lx\n", ha->qthreads);
-  size += sprintf(PROC_BUF,"Number of free request entries = %d\n",ha->req_q_cnt);
-  size += sprintf(PROC_BUF, "\n");                                             /* 1       */
+    len += size; 
+    size = sprintf(PROC_BUF, "Number of pending commands = 0x%lx\n", ha->actthreads);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of queued commands = 0x%lx\n", ha->qthreads);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of free request entries = %d\n",ha->req_q_cnt);
+    len += size;
+    size = sprintf(PROC_BUF, "\n");                                             /* 1       */
+    len += size;
                         
-  size += sprintf(PROC_BUF, "Attached devices:\n");
+    size = sprintf(PROC_BUF, "SCSI device Information:\n");
+    len += size; 
   /* scan for all equipment stats */ 
-  for (targ_lun = 0; targ_lun < MAX_EQ; targ_lun++)
-  {
-      if( (up = ha->dev[targ_lun]) == NULL )
+	for (b = 0; b < MAX_BUSES; b++) 
+	for (t = 0; t < MAX_TARGETS; t++) {
+        for( l = 0; l < MAX_LUNS; l++ ) {
+           up = (scsi_lu_t *) LU_Q(ha, b, t, l);
+           if( up == NULL ) 
            continue;
-      if( up->io_cnt == 0 )
-      {
-          size += sprintf(PROC_BUF,"(%2d:%2d:%2d) No stats\n",LUN_ID);
+           /* unused device/lun */
+           if( up->io_cnt == 0 || up->io_cnt < 2 )
            continue;
-      }
       /* total reads since boot */
       /* total writes since boot */
       /* total requests since boot  */
-      size += sprintf(PROC_BUF, "Total requests %ld,",up->io_cnt);
+           size = sprintf(PROC_BUF, "(%2d:%2d:%2d): Total reqs %ld,",b,t,l,up->io_cnt);
+           len += size;
       /* current number of pending requests */
-      size += sprintf(PROC_BUF, "(%2d:%2d:%2d) pending requests %d,",LUN_ID,up->q_outcnt);
+           size = sprintf(PROC_BUF, " Pend reqs %d,",up->q_outcnt);
+           len += size;
+#if 0
       /* avg response time */
-      size += sprintf(PROC_BUF, "Avg response time %ld%%,",(up->resp_time/up->io_cnt)*100);
+           size = sprintf(PROC_BUF, " Avg resp time %ld%%,",(up->resp_time/up->io_cnt)*100);
+           len += size;
       
       /* avg active time */
-      size += sprintf(PROC_BUF, "Avg active time %ld%%\n",(up->act_time/up->io_cnt)*100);
+           size = sprintf(PROC_BUF, " Avg active time %ld%%\n",(up->act_time/up->io_cnt)*100);
+#else
+           size = sprintf(PROC_BUF, "\n");
+#endif
+           len += size; 
+        }
+        if( len >= qla1280_buffer_size ) 
+          break;
   }
 
-  if (size >= qla1280_buffer_size)
-  {
+    if( len >= qla1280_buffer_size ) {
     printk(KERN_WARNING "qla1280: Overflow buffer in qla1280_proc.c\n");
   }
 
-  if (offset > size - 1)
-  {
+    if( offset > len - 1 ) {
     kfree(qla1280_buffer);
     qla1280_buffer = NULL;
     qla1280_buffer_size = length = 0;
     *start = NULL;
-  }
-  else
-  {
+    } else {
     *start = &qla1280_buffer[offset];   /* Start of wanted data */
-    if (size - offset < length)
-    {
-      length = size - offset;
+        if( len - offset < length ) {
+            length = len - offset;
     }
   }
+    return (length);
+#else
+    return (0);
 #endif
 
-  return (length);
 }
 
-
 /**************************************************************************
  * qla1280_detect
  *    This routine will probe for Qlogic 1280 SCSI host adapters.
@@ -734,7 +694,10 @@
     struct Scsi_Host *host;
     scsi_qla_host_t *ha, *cur_ha;
     struct _qlaboards  *bdp;
-    int i, j;
+    int i,j;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+    unsigned short subsys;
+#endif
 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,95)
     unsigned int piobase;
     unsigned char pci_bus, pci_devfn, pci_irq;
@@ -747,13 +710,19 @@
 #else
     int index;
 #endif
+#ifndef PCI_VENDOR_ID_AMI
+#define PCI_VENDOR_ID_AMI               0x101e
+#endif
 
     ENTER("qla1280_detect");
 
+    if (sizeof(srb_t) > sizeof(Scsi_Pointer) )
+      printk("qla1280_detect: [WARNING] srb_t Must Be Redefined");
+
 #ifdef CHECKSRBSIZE
     if (sizeof(srb_t) > sizeof(Scsi_Pointer) )
     {
-      printk("Redefine SRB - its too big");
+      printk("qla1280_detect:  srb_t Must Be Redefined - its too big");
       return 0;
     }
 #endif
@@ -784,45 +753,174 @@
                 "qla1280: insmod or else it might trash certain memory areas.\n");
 #endif
 
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
     if ((int) !pcibios_present())
+#else
+    if (!pci_present())
+#endif
     {
-		printk("scsi: PCI not present\n");
-		return 0;
-    } /* end of IF */
-    bdp = &QLBoardTbl[0];
+	printk("scsi: PCI not present\n");
+	return 0;
+    } 
+
+    bdp = &QL1280BoardTbl[0];
     qla1280_hostlist = NULL;
-#if 0
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
     template->proc_dir = &proc_scsi_qla1280;
 #else
     template->proc_name = "qla1280";
 #endif
+
+        /* 3.20 */
+        /* First Initialize QLA12160 on PCI Bus 1 Dev 2 */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+        while ((pdev = pci_find_subsys(QLA1280_VENDOR_ID,
+                               bdp->device_id,  /* QLA12160 first in list */ 
+                               PCI_ANY_ID, 
+                               PCI_ANY_ID,pdev))) {
+
+                /* find QLA12160 device on PCI bus=1 slot=2 */
+                if ((pdev->bus->number     != 1)   ||
+                    (PCI_SLOT(pdev->devfn) != 2))  continue;
+
+                if (pci_enable_device(pdev)) goto find_devices;
+                printk("qla1x160: Initializing ISP12160 on PCI Bus 1, Dev 2\n");
+		host = scsi_register(template, sizeof(scsi_qla_host_t));
+                if (!host) { 
+			printk(KERN_WARNING "qla1280: Failed to register host, aborting.\n");
+                        return 0;
+                }
+		scsi_set_pci_device(host, pdev);
+		ha = (scsi_qla_host_t *) host->hostdata;
+		/* Clear our data area */
+		for( j =0, cp = (char *)ha;  j < sizeof(scsi_qla_host_t); j++)
+			*cp++ = 0;
+		/* Sanitize the information from PCI BIOS.  */
+		host->irq = pdev->irq;
+		host->io_port = pci_resource_start(pdev, 0);
+		ha->pci_bus = pdev->bus->number;
+		ha->pci_device_fn = pdev->devfn;
+		ha->pdev = pdev;
+		ha->device_id = bdp->device_id; /* QLA12160 first in list */
     
+                ha->devnum = 0; // This priority ISP12160 is always devnum zero
+		if( qla1280_mem_alloc(ha) ) {
+  	          printk(KERN_INFO "qla1x160: Failed to get memory\n");
+		}                
+                ha->ports = bdp->numPorts; 
+                /* following needed for all cases of OS versions */
+                host->io_port &= PCI_BASE_ADDRESS_IO_MASK; 
+                ha->iobase = (device_reg_t *) host->io_port;
+                ha->host = host;
+                ha->host_no = host->host_no;
+                /* 3.20 zero out /proc/scsi/qla1280 counters */
+                ha->actthreads = 0;
+                ha->qthreads = 0;
+                ha->isr_count = 0; 
+
+                /* load the F/W, read paramaters, and init the H/W */
+                ha->instance = num_hosts;
+                if (qla1280_initialize_adapter(ha))
+                {
+                   printk(KERN_INFO "qla1x160: Failed to initialize QLA12160 on PCI Bus 1 Dev 2 \n");
+                   qla1280_mem_free(ha);
+                   scsi_unregister(host);
+                   goto find_devices;
+                }                
+                host->max_channel = bdp->numPorts-1; 
+		/* Register our resources with Linux */
+		if( qla1280_register_with_Linux(ha, bdp->numPorts-1) ) {
+		  printk(KERN_INFO "qla1x160: Failed to register resources for QLA12160 on PCI Bus 1 Dev 2\n");
+		  qla1280_mem_free(ha);
+		  scsi_unregister(host);
+		  goto find_devices;
+		}
+                reg = ha->iobase;
+                /* Disable ISP interrupts. */
+		qla1280_disable_intrs(ha);
+                /* Insure mailbox registers are free. */
+                WRT_REG_WORD(&reg->semaphore, 0);
+                WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
+                WRT_REG_WORD(&reg->host_cmd, HC_CLR_HOST_INT);
+
+                /* Enable chip interrupts. */
+		qla1280_enable_intrs(ha);
+                /* Insert new entry into the list of adapters */
+                ha->next = NULL;
+                /* this preferred device will always be the first one found */
+                cur_ha = qla1280_hostlist = ha;
+                num_hosts++;
+        }
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+ find_devices:
+#endif
+
+        pdev = NULL;
 	/* Try and find each different type of adapter we support */
-	for( i=0; bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES; i++, bdp++ ) {
+	for(i=0;bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES;i++,bdp++) {
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+                /* PCI_SUBSYSTEM_IDS supported */ 
+		while ((pdev = pci_find_subsys(QLA1280_VENDOR_ID,
+			bdp->device_id, PCI_ANY_ID, PCI_ANY_ID, pdev) )) {
+ 			if (pci_enable_device(pdev)) continue;
+#else
 		while ((pdev = pci_find_device(QLA1280_VENDOR_ID,
 			bdp->device_id, pdev ) ))  {
-		if (pci_enable_device(pdev)) continue;
-#else
+#endif /* 2,3,18 */
+#else  /* less than 2,1,95 */  
 		while (!(pcibios_find_device(QLA1280_VENDOR_ID,
 			bdp->device_id,
 			index++, &pci_bus, &pci_devfn)) )  {
-#endif
+#endif /* 2,1,95 */ 
                 /* found a adapter */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+		  /* If it's an AMI SubSys Vendor ID adapter, skip it. */
+                  if (pdev->subsystem_vendor == PCI_VENDOR_ID_AMI) 
+                    { 
+                      printk("qla1x160: Skip AMI SubSys Vendor ID Chip\n");
+                      continue;
+                    }
+
+                  /* 3.20 and 3.23 */
+		  /* skip QLA12160 already initialized on PCI Bus 1 Dev 2 */
+                  /* since we already initialized and presented it */
+                  if ((bdp->device_id        == QLA12160_DEVICE_ID) &&
+                      (pdev->bus->number     == 1)   &&
+                      (PCI_SLOT(pdev->devfn) == 2))  continue;
+
+ 		  printk("qla1x160: Supported Device Found VID=%x DID=%x SSVID=%x SSDID=%x\n",
+			pdev->vendor, pdev->device,
+			pdev->subsystem_vendor, pdev->subsystem_device); 
+
+#else
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+                  printk("qla1x160: Supported Device Found\n");
+		  pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
+                                       &subsys);
+		  /* Bypass all AMI SUBSYS VENDOR IDs */
+                  if (subsys == PCI_VENDOR_ID_AMI) 
+                    { 
+                      printk("qla1x160: Skip AMI SubSys Vendor ID  Chip\n");
+                      continue;
+                    }
+#endif /* 2,1,95 */
+#endif /* 2,3,18 */
 		host = scsi_register(template, sizeof(scsi_qla_host_t));
-                if (!host) { 
-			printk(KERN_WARNING "qla1280: Failed to register host, aborting.\n");
-                        return 0;
-                }
-		scsi_set_pci_device(host, pdev);
 		ha = (scsi_qla_host_t *) host->hostdata;
 		/* Clear our data area */
 		for( j =0, cp = (char *)ha;  j < sizeof(scsi_qla_host_t); j++)
-			*cp = 0;
+			*cp++ = 0;
 		/* Sanitize the information from PCI BIOS.  */
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
 		host->irq = pdev->irq;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                host->io_port = (unsigned int) pdev->base_address[0];
+#else
 		host->io_port = pci_resource_start(pdev, 0);
+#endif
 		ha->pci_bus = pdev->bus->number;
 		ha->pci_device_fn = pdev->devfn;
 		ha->pdev = pdev;
@@ -836,38 +934,38 @@
 		ha->pci_device_fn = pci_devfn;
 #endif
 		ha->device_id = bdp->device_id;
-    
-                ha->devnum = i;
+                ha->devnum = i; // specifies microcode load address
+
 		if( qla1280_mem_alloc(ha) ) {
-			printk(KERN_INFO "qla1280: Failed to allocate memory for adapter\n");
+  	          printk(KERN_INFO "qla1x160: Failed to get memory\n");
 		}
                 
                 ha->ports = bdp->numPorts; 
+                /* following needed for all cases of OS versions */
+                host->io_port &= PCI_BASE_ADDRESS_IO_MASK; 
                 ha->iobase = (device_reg_t *) host->io_port;
                 ha->host = host;
                 ha->host_no = host->host_no;
 
                 /* load the F/W, read paramaters, and init the H/W */
+                ha->instance = num_hosts;
                 if (qla1280_initialize_adapter(ha))
                 {
-
-                    printk(KERN_INFO "qla1280: Failed to initialized adapter\n");
-                    qla1280_mem_free(ha);
-                    scsi_unregister(host);
-                    continue;
+                   printk(KERN_INFO "qla1x160:Failed to initialize adapter\n");
+                   qla1280_mem_free(ha);
+                   scsi_unregister(host);
+                   continue;
                 }
                 
                 host->max_channel = bdp->numPorts-1; 
-                ha->instance = num_hosts;
 		/* Register our resources with Linux */
 		if( qla1280_register_with_Linux(ha, bdp->numPorts-1) ) {
-			printk(KERN_INFO "qla1280: Failed to register our resources\n");
-			qla1280_mem_free(ha);
-			scsi_unregister(host);
-			continue;
+		  printk(KERN_INFO "qla1x160: Failed to register resources\n");
+		  qla1280_mem_free(ha);
+		  scsi_unregister(host);
+		  continue;
 		}
 
-
                 reg = ha->iobase;
                 /* Disable ISP interrupts. */
 		qla1280_disable_intrs(ha);
@@ -924,8 +1022,11 @@
 	host->can_queue = 0xfffff;  /* unlimited  */
 	host->cmd_per_lun = 1;
        host->select_queue_depths = qla1280_select_queue_depth;
-	host->n_io_port = 0xFF;
-	host->base = (unsigned long) ha->mmpbase;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        host->base = (unsigned char *) ha->mmpbase;
+#else
+        host->base = (u_long) ha->mmpbase;
+#endif
 	host->max_channel = maxchannels; 
        host->max_lun = MAX_LUNS-1; 
 	host->unique_id = ha->instance;
@@ -1016,10 +1117,10 @@
 
     bp = &qla1280_buffer[0];
     ha = (scsi_qla_host_t *)host->hostdata;
-    bdp = &QLBoardTbl[ha->devnum];
+    bdp = &QL1280BoardTbl[ha->devnum];
     memset(bp, 0, sizeof(qla1280_buffer));
     sprintf(bp,
-            "QLogic %sPCI to SCSI Host Adapter: bus %d device %d irq %d\n"
+            "QLogic %s PCI to SCSI Host Adapter: bus %d device %d irq %d\n"
             "       Firmware version: %2d.%02d.%02d, Driver version %s",
             (char *)&bdp->bdName[0], ha->pci_bus, (ha->pci_device_fn & 0xf8) >> 3, host->irq,
             bdp->fwver[0],bdp->fwver[1],bdp->fwver[2],
@@ -1051,8 +1152,8 @@
     scsi_lu_t       *q;
     u_long          handle;
 
-    ENTER("qla1280_queuecommand");
-    COMTRACE('C') 
+    /*ENTER("qla1280_queuecommand");
+      COMTRACE('C')*/ 
 
     host = cmd->host;
     ha = (scsi_qla_host_t *) host->hostdata;
@@ -1079,7 +1180,7 @@
         {
            LU_Q(ha, b, t, l) = q;
            BZERO(q,sizeof(struct scsi_lu));
-           DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q));
+           DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n\r",q));
            DEBUG(qla1280_print(debug_buff));
            DRIVER_UNLOCK
         }
@@ -1087,8 +1188,12 @@
         {
             CMD_RESULT(cmd) = (int) (DID_BUS_BUSY << 16);
             qla1280_done_q_put(sp, &ha->done_q_first, &ha->done_q_last);
-
-            schedule_task(&ha->run_qla_bh);
+/* 3.22 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) /* 3.22 */
+            queue_task(&ha->run_qla_bh,&tq_scheduler);
+#else  /* 3.22 */ 
+            schedule_task(&ha->run_qla_bh); /* 3.22 */
+#endif /* 3.22 */
             ha->flags.dpc_sched = TRUE;
             DRIVER_UNLOCK
             return(0);
@@ -1099,15 +1204,13 @@
     handle = INVALID_HANDLE;  
     CMD_HANDLE(cmd) = (unsigned char *)handle;
 
-    /* Bookkeeping information */
-    sp->r_start = jiffies;       /* time the request was received */
-    sp->u_start = 0;              
-
     /* add the command to our queue */
     ha->qthreads++;
     qla1280_putq_t(q,sp);
     
-    DEBUG(sprintf(debug_buff,"qla1280_queuecmd: queue pid=%d, hndl=0x%x\n\r",cmd->pid,handle));
+    DEBUG(sprintf(debug_buff,
+     "qla1280_QC: t=%x CDB=%x I/OSize=0x%x haQueueCount=0x%x\n\r",
+     t,cmd->cmnd[0],CMD_XFRLEN(cmd),ha->qthreads));
     DEBUG(qla1280_print(debug_buff));
 
     /* send command to adapter */
@@ -1117,7 +1220,7 @@
     DRIVER_UNLOCK
     
     
-    LEAVE("qla1280_queuecommand");
+    /*LEAVE("qla1280_queuecommand");*/
     return (0);
 }
 
@@ -1556,6 +1659,7 @@
     {
           COMTRACE('X')
           printk(KERN_INFO "scsi(%d): Already in interrupt - returning \n", (int)ha->host_no);
+          spin_unlock_irqrestore(&io_request_lock, cpu_flags);
           return;
     }
     set_bit(QLA1280_IN_ISR_BIT, (int *)&ha->flags);
@@ -1587,7 +1691,7 @@
             ha->run_qla_bh.routine = qla1280_do_dpc; 
 
              COMTRACE('P') 
-            schedule_task(&ha->run_qla_bh);
+            queue_task_irq(&ha->run_qla_bh,&tq_scheduler); 
             ha->flags.dpc_sched = TRUE;
         }
         clear_bit(QLA1280_IN_ISR_BIT, (int *)&ha->flags);
@@ -1611,7 +1715,7 @@
  * "host->can_queue". This can cause a panic if we were in our interrupt
  * code .
  **************************************************************************/
-static void qla1280_do_dpc(void *p)
+void qla1280_do_dpc(void *p)
 {
     scsi_qla_host_t *ha = (scsi_qla_host_t *) p;
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
@@ -1729,6 +1833,7 @@
     scsi_lu_t       *q;
     uint32_t        b, t, l;
     Scsi_Cmnd  *cmd;
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
     unsigned long cpu_flags = 0;
 #endif
@@ -1745,7 +1850,8 @@
             *done_q_last = NULL;
         else
             (*done_q_first)->s_prev = NULL;
-                cmd = sp->cmd;
+
+        cmd = sp->cmd;
         b = SCSI_BUS_32(cmd);
         t = SCSI_TCN_32(cmd);
         l = SCSI_LUN_32(cmd);
@@ -1759,8 +1865,6 @@
             q->q_flag &= ~QLA1280_QBUSY;
         }
         
-        q->resp_time += jiffies - sp->r_start;                /* Lun bookkeeping information */
-        q->act_time += jiffies - sp->u_start;
         q->io_cnt++;
         if( sp->dir & BIT_5 )
          q->r_cnt++;
@@ -1783,7 +1887,28 @@
             default:
                 break;
         }
-
+        /* 3.13   64 and 32 bit */
+        /* Release memory used for this I/O */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+        if (cmd->use_sg) {
+            DEBUG(sprintf(debug_buff,
+            "S/G unmap_sg cmd=%x\n\r",cmd);)
+            DEBUG(qla1280_print(debug_buff));
+            pci_unmap_sg(ha->pdev, cmd->request_buffer,
+                         cmd->use_sg,
+                         scsi_to_pci_dma_dir(cmd->sc_data_direction));
+        }
+        else if (cmd->request_bufflen) {
+          /*DEBUG(sprintf(debug_buff,
+                 "No S/G unmap_single cmd=%x saved_dma_handle=%lx\n\r",
+                  cmd,sp->saved_dma_handle);)
+                  DEBUG(qla1280_print(debug_buff);)*/
+
+                  pci_unmap_single(ha->pdev,sp->saved_dma_handle,
+                                  cmd->request_bufflen,
+                                  scsi_to_pci_dma_dir(cmd->sc_data_direction));
+       }
+#endif 
         /* Call the mid-level driver interrupt handler */
         CMD_HANDLE(sp->cmd) = (unsigned char *) 0;
         ha->actthreads--;
@@ -1797,8 +1922,6 @@
         qla1280_next(ha, q, b);
     }
     DRIVER_UNLOCK 
-
-
     COMTRACE('d') 
     LEAVE("qla1280_done");
 }
@@ -1970,7 +2093,7 @@
             if (q->q_outcnt >= ha->bus_settings[b].hiwat)
                 q->q_flag |= QLA1280_QBUSY;
 
-#if  QLA1280_64BIT_SUPPORT
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
             if (ha->flags.enable_64bit_addressing)
                 status = qla1280_64bit_start_scsi(ha, sp);
             else
@@ -1987,7 +2110,7 @@
                     /* Wait for 30 sec for command to be accepted. */
                     for (cnt = 6000000; cnt; cnt--)
                     {
-#if  QLA1280_64BIT_SUPPORT
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
                         if (ha->flags.enable_64bit_addressing)
                             status = qla1280_64bit_start_scsi(ha, sp);
                         else
@@ -2078,7 +2201,7 @@
     ENTER("qla1280_putq_t");
 #endif
     DRIVER_LOCK
-    DEBUG(sprintf(debug_buff,"Adding to device 0x%p<-(0x%p)\n\r",q,sp));
+    DEBUG(sprintf(debug_buff,"Adding to device q=0x%p<-(0x%p)sp\n\r",q,sp));
     DEBUG(qla1280_print(debug_buff));
     sp->s_next = NULL;
     if (!q->q_first)                  /* If queue empty */
@@ -2163,28 +2286,33 @@
 {
 
 	uint8_t   status = 1;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+        dma_addr_t     dma_handle;
+#endif
 
 #ifdef QL_DEBUG_LEVEL_3
 	ENTER("qla1280_mem_alloc");
 #endif
 
-#ifdef DYNAMIC_MEM_ALLOC
-	ha->request_ring = qla1280_alloc_phys(REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT,
-	&ha->request_dma);
-	if(ha->request_ring) {
-		ha->response_ring = qla1280_alloc_phys(RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT,
-		&ha->response_dma);
-		if(ha->response_ring) {
-			status = 0;
-		}
-	}
-#else
+        /* 3.13 */
+        /* get consistent memory allocated for request and response rings */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
 	ha->request_ring = &ha->req[0];
 	ha->request_dma = VIRT_TO_BUS(&ha->req[0]);
 	ha->response_ring = &ha->res[0];
 	ha->response_dma = VIRT_TO_BUS(&ha->res[0]);
 	status = 0;
-#endif
+#else
+        ha->request_ring  = pci_alloc_consistent(ha->pdev,
+                               ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))),
+                               &dma_handle);
+        ha->request_dma    = dma_handle;
+        ha->response_ring  = pci_alloc_consistent(ha->pdev,
+                               ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))),
+                               &dma_handle);
+        ha->response_dma   = dma_handle;
+        status = 0; 
+#endif 
 
 	if(status) {
 #if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
@@ -2228,6 +2356,16 @@
             ha->dev[b] =  (scsi_lu_t  *)NULL;
     }
 
+    /* 3.13 */
+    /* free consistent memory allocated for request and response rings */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    pci_free_consistent(ha->pdev, ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))),
+                        ha->request_ring, ha->request_dma);
+
+    pci_free_consistent(ha->pdev,((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))),
+    ha->response_ring, ha->response_dma); 
+#endif 
+
     LEAVE("qlc1280_mem_free");
 }
 
@@ -2488,7 +2626,7 @@
         /* Verify checksum of loaded RISC code. */
         mb[0] = MBC_VERIFY_CHECKSUM;
         /* mb[1] = ql12_risc_code_addr01; */
-        mb[1] = *QLBoardTbl[ha->devnum].fwstart;  
+        mb[1] = *QL1280BoardTbl[ha->devnum].fwstart;  
 
         if (!(status = qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0])))
         {
@@ -2498,7 +2636,7 @@
 #endif
             mb[0] = MBC_EXECUTE_FIRMWARE;
             /* mb[1] = ql12_risc_code_addr01; */
-            mb[1] = *QLBoardTbl[ha->devnum].fwstart;  
+            mb[1] = *QL1280BoardTbl[ha->devnum].fwstart;  
             qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
         }
         else
@@ -2533,18 +2671,69 @@
 qla1280_pci_config(scsi_qla_host_t *ha)
 {
     uint8_t      status = 1;
-    uint32_t     command;
 #if MEMORY_MAPPED_IO
     uint32_t  page_offset, base;
     uint32_t   mmapbase;
 #endif
-    config_reg_t *creg = 0;
     uint16_t     buf_wd;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+    uint32_t     command;
+    config_reg_t *creg = 0;
+#endif
+
 
     ENTER("qla1280_pci_config");
 
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    /*
+     * Set Bus Master Enable, Memory Address Space Enable and
+     * reset any error bits, in the command register.
+     */
+    pci_read_config_word(ha->pdev, PCI_COMMAND, &buf_wd);
+    buf_wd &= ~0x7;
+#if MEMORY_MAPPED_IO
+    DEBUG(printk("qla1280: MEMORY MAPPED IO is enabled.\n"));
+    buf_wd |= BIT_2 + BIT_1 + BIT_0;
+#else
+    buf_wd |= BIT_2 + BIT_0;
+#endif
+    pci_write_config_word(ha->pdev, PCI_COMMAND, buf_wd);
+    /*
+     * Reset expansion ROM address decode enable.
+     */
+    pci_read_config_word(ha->pdev, PCI_ROM_ADDRESS, &buf_wd);
+    buf_wd &= ~PCI_ROM_ADDRESS_ENABLE;
+    pci_write_config_word(ha->pdev, PCI_ROM_ADDRESS, buf_wd);
+#if MEMORY_MAPPED_IO
+    /*
+     * Get memory mapped I/O address. 
+     */
+    pci_read_config_word(ha->pdev, PCI_BASE_ADDRESS_1, &mmapbase);
+    mmapbase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+    /*
+     * Find proper memory chunk for memory map I/O reg.
+     */
+    base = mmapbase & PAGE_MASK;
+    page_offset = mmapbase - base;
+    /*
+     * Get virtual address for I/O registers.
+     */
+    ha->mmpbase = ioremap_nocache(base, page_offset + 256);
+    if( ha->mmpbase )
+    {
+        ha->mmpbase += page_offset;
+        /* ha->iobase = ha->mmpbase; */
+        status = 0;
+    }
+#else /* MEMORY_MAPPED_IO */
+    status = 0;
+#endif /* MEMORY_MAPPED_IO */
+
+#else /*LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18) */
+
     /* Get command register. */
-    if (pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL)
+    if (pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL)
     {
         command = buf_wd;
         /*
@@ -2558,20 +2747,20 @@
 #else
         buf_wd |= BIT_2 + BIT_0;
 #endif
-        if( pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd) )
+        if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), buf_wd) )
         {
             printk(KERN_WARNING "qla1280: Could not write config word.\n");
         }
         /* Get expansion ROM address. */
-        if (pci_read_config_word(ha->pdev,OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL)
+        if (pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL)
         {
             /* Reset expansion ROM address decode enable. */
             buf_wd &= ~BIT_0;
-            if (pci_write_config_word(ha->pdev,OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL)
+            if (pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL)
             {
 #if MEMORY_MAPPED_IO
                 /* Get memory mapped I/O address. */
-                pci_read_config_dword(ha->pdev,OFFSET(cfgp->mem_base_addr), &mmapbase);
+                pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase);
                 mmapbase &= PCI_BASE_ADDRESS_MEM_MASK;
 
                 /* Find proper memory chunk for memory map I/O reg. */
@@ -2595,6 +2784,7 @@
             }
         }
     }
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18) */
 
     LEAVE("qla1280_pci_config");
     return(status);
@@ -2725,6 +2915,7 @@
  * Returns:
  *      0 = success.
  */
+#define DUMP_IT_BACK 0   /* for debug of RISC loading */
 STATIC uint8_t
 qla1280_setup_chip(scsi_qla_host_t *ha)
 {
@@ -2733,37 +2924,52 @@
     uint16_t     *risc_code_address;
     long         risc_code_size;
     uint16_t     mb[MAILBOX_REGISTER_COUNT];
-#ifdef QLA1280_UNUSED
-    uint8_t	*sp;
-    int i;
-#endif
     uint16_t     cnt;
     int          num;
+#if DUMP_IT_BACK
+    int     i;
+    uint8_t *sp;
     uint8_t    *tbuf;
-    u_long     p_tbuf;
+#if BITS_PER_LONG > 32
+    dma_addr_t     p_tbuf;
+#else
+    uint32_t   p_tbuf;
+#endif
+#endif
 
 #ifdef QL_DEBUG_LEVEL_3
     ENTER("qla1280_setup_chip");
 #endif
 
-	if( (tbuf = (uint8_t *)KMALLOC(8000) ) == NULL )
-        {
-            printk("setup_chip: couldn't alloacte memory\n");
-            return(1);
-        }
-        p_tbuf =  VIRT_TO_BUS(tbuf);
+    /* 3.13 */
+#if DUMP_IT_BACK
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+    if( (tbuf = (uint8_t *)KMALLOC(8000) ) == NULL )
+    {
+        printk("setup_chip: couldn't alloacte memory\n");
+        return(1);
+    }
+    p_tbuf =  VIRT_TO_BUS(tbuf);
+#else
+    /* get consistent memory allocated for setup_chip */
+    tbuf   = pci_alloc_consistent(ha->pdev, 8000, &p_tbuf);
+#endif
+#endif
+
     /* Load RISC code. */
     /* 
     risc_address      = ql12_risc_code_addr01;
     risc_code_address = &ql12_risc_code01[0];
     risc_code_size    = ql12_risc_code_length01;
     */
-    risc_address = *QLBoardTbl[ha->devnum].fwstart;  
-    risc_code_address = QLBoardTbl[ha->devnum].fwcode;  
-    risc_code_size    = (long)(*QLBoardTbl[ha->devnum].fwlen & 0xffff);  
-
-    DEBUG(printk("qla1280: DMAing RISC code (%d) words.\n",(int)risc_code_size));
-    DEBUG(sprintf(debug_buff,"qla1280_setup_chip:  Loading RISC code size =(%ld).\n\r",risc_code_size);)
+    risc_address = *QL1280BoardTbl[ha->devnum].fwstart;  
+    risc_code_address = QL1280BoardTbl[ha->devnum].fwcode;  
+    risc_code_size    = (long)(*QL1280BoardTbl[ha->devnum].fwlen & 0xffff);  
+
+    DEBUG(printk("qla1280_setup_chip: DMA RISC code (%d) words\n",
+         (int)risc_code_size));
+    DEBUG(sprintf(debug_buff,
+       "qla1280_setup_chip: DMA RISC code (%d) words\n\r",risc_code_size);)
     DEBUG(qla1280_print(debug_buff));
     num =0;
     while (risc_code_size > 0 && !status)
@@ -2773,29 +2979,31 @@
         if ( cnt > risc_code_size ) 
             cnt = risc_code_size;
 
-        DEBUG(sprintf(debug_buff,"qla1280_setup_chip:  loading risc @ =(0x%p),%d,%d(0x%x).\n\r",risc_code_address,cnt,num,risc_address);)
+        DEBUG(sprintf(debug_buff,
+         "qla1280_setup_chip:  loading risc @ =(0x%p),%d,%d(0x%x).\n\r",
+          risc_code_address,cnt,num,risc_address);)
         DEBUG(qla1280_print(debug_buff));
-        DEBUG(printk("qla1280_setup_chip:  loading risc @ =code=(0x%p),cnt=%d,seg=%d,addr=0x%x\n\r",risc_code_address,cnt,num,risc_address));
-        BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring, (cnt <<1));
+        BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring,
+              (cnt <<1));
+
+        flush_cache_all(); 
+
         mb[0] = MBC_LOAD_RAM; 
-        /* mb[0] = MBC_LOAD_RAM_A64; */
         mb[1] = risc_address;
         mb[4] = cnt;
         mb[3] = (uint16_t)  ha->request_dma & 0xffff;
         mb[2] = (uint16_t) (ha->request_dma >> 16) & 0xffff;
         mb[7] = (uint16_t) (MS_64BITS(ha->request_dma) & 0xffff);
         mb[6] = (uint16_t) (MS_64BITS(ha->request_dma) >> 16) & 0xffff;
-        DEBUG(printk("qla1280_setup_chip: op=%d  0x%lx = 0x%4x,0x%4x,0x%4x,0x%4x\n",mb[0],ha->request_dma,mb[6],mb[7],mb[2],mb[3]));
+        DEBUG(printk("qla1280_setup_chip: op=%d  0x%p = 0x%4x,0x%4x,0x%4x,0x%4x\n",mb[0],ha->request_dma,mb[6],mb[7],mb[2],mb[3]));
         if( (status = qla1280_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,
             &mb[0]))  )
         {
             printk("Failed to load partial segment of f/w\n");
             break;
         }
-        /* dump it back */
-
-#if 0
-        mb[0] = MBC_DUMP_RAM_A64;
+#if DUMP_IT_BACK
+        mb[0] = MBC_READ_RAM_WORD;
         mb[1] = risc_address;
         mb[4] = cnt;
         mb[3] = (uint16_t)  p_tbuf & 0xffff;
@@ -2803,10 +3011,13 @@
         mb[7] = (uint16_t) (p_tbuf >> 32) & 0xffff;
         mb[6] = (uint16_t) (p_tbuf >> 48) & 0xffff;
 
-        if( (status = qla1280_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,
-            &mb[0]))  )
+        if( (status = qla1280_mailbox_command(ha, 
+                      BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,&mb[0]))  )
         {
             printk("Failed to dump partial segment of f/w\n");
+            DEBUG(sprintf(debug_buff,
+               "setup_chip: Failed to dump partial segment of f/w\n\r");)
+            DEBUG(qla1280_print(debug_buff));
             break;
         }
         sp =  (uint8_t *)ha->request_ring;
@@ -2814,51 +3025,20 @@
         {
             if( tbuf[i] != sp[i] )
             {
-               printk("qla1280 : firmware compare error @ byte (0x%x)\n",i);
-                break;
+               printk("qla1280_setup_chip: FW compare error @ byte(0x%x) loop#=%x\n",i,num);
+               printk("setup_chip: FWbyte=%x  FWfromChip=%x\n",sp[i],tbuf[i]); 
+               DEBUG(sprintf(debug_buff,
+                "qla1280_setup_chip: FW compare error @ byte(0x%x) loop#=%x\n\r",i);)
+               DEBUG(qla1280_print(debug_buff);)
+               /*break;*/
             }
         }
-
 #endif
         risc_address += cnt;
         risc_code_size = risc_code_size - cnt;
         risc_code_address = risc_code_address + cnt;
         num++;
     }
-#ifdef QLA1280_UNUSED
-    DEBUG(ql_debug_print = 0;)
-    {
-        for (i = 0; i < ql12_risc_code_length01; i++)
-        {
-            mb[0] = 0x4;
-            mb[1] = ql12_risc_code_addr01 + i;
-            mb[2] = ql12_risc_code01[i];
-
-            status = qla1280_mailbox_command(ha, BIT_2|BIT_1|BIT_0,
-                    &mb[0]);
-            if (status)
-            {
-                printk("qla1280 : firmware load failure\n");
-                break;
-            }
-
-            mb[0] = 0x5;
-            mb[1] = ql12_risc_code_addr01 + i;
-            mb[2] = 0;
-
-            status = qla1280_mailbox_command(ha, BIT_2|BIT_1|BIT_0,
-                    &mb[0]);
-            if (status)
-            {
-                printk("qla1280 : firmware dump failure\n");
-                break;
-            }
-            if( mb[2] != ql12_risc_code01[i] )
-                printk("qla1280 : firmware compare error @ (0x%x)\n",ql12_risc_code_addr01+i);
-        }
-    }
-    DEBUG(ql_debug_print = 1;)
-#endif
 
     /* Verify checksum of loaded RISC code. */
     if (!status)
@@ -2866,22 +3046,29 @@
         DEBUG(printk("qla1280_setup_chip: Verifying checksum of loaded RISC code.\n");)
         mb[0] = MBC_VERIFY_CHECKSUM;
         /* mb[1] = ql12_risc_code_addr01; */
-        mb[1] = *QLBoardTbl[ha->devnum].fwstart;  
+        mb[1] = *QL1280BoardTbl[ha->devnum].fwstart;  
         
         if (!(status = qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0])))
         {
             /* Start firmware execution. */
             DEBUG(qla1280_print("qla1280_setup_chip: start firmware running.\n\r");)
             mb[0] = MBC_EXECUTE_FIRMWARE;
-            /* mb[1] = ql12_risc_code_addr01; */
-            mb[1] = *QLBoardTbl[ha->devnum].fwstart;  
+            mb[1] = *QL1280BoardTbl[ha->devnum].fwstart;  
             qla1280_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
         }
         else
             printk("qla1280_setup_chip: Failed checksum.\n");
     }
 
-	KMFREE(tbuf,8000);
+    /* 3.13 */
+#if DUMP_IT_BACK
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+    KMFREE(tbuf,8000);
+#else
+    /* free consistent memory allocated for setup_chip */
+    pci_free_consistent(ha->pdev, 8000, tbuf, p_tbuf);
+#endif
+#endif
 
 #if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
     if (status)
@@ -3158,9 +3345,29 @@
     /* Disable RISC load of firmware. */
     ha->flags.disable_risc_code_load =
             nv->cntr_flags_1.disable_loading_risc_code;
-    /* Enable 64bit addressing. */
-    ha->flags.enable_64bit_addressing =
-            nv->cntr_flags_1.enable_64bit_addressing;
+
+#if BITS_PER_LONG > 32
+    /* Enable 64bit addressing for OS/System combination supporting it   */
+    /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing     */ 
+    /* but we will ignore it and use BITS_PER_LONG macro to setup for    */
+    /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */
+    ha->flags.enable_64bit_addressing = 1;
+#else
+    ha->flags.enable_64bit_addressing = 0;
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    if (ha->flags.enable_64bit_addressing) {
+      printk("[[[ qla1x160: 64 Bit PCI Addressing Enabled ]]]\n");
+
+#if BITS_PER_LONG > 32
+           /* Update our PCI device dma_mask for full 64 bit mask */
+           //ha->pdev->dma_mask = (pci_dma_t) 0xffffffffffffffffull;
+           ha->pdev->dma_mask =  0xffffffffffffffff;
+
+#endif
+    }
+#endif
 
     /* Set ISP hardware DMA burst */
     mb[0] = nv->isp_config.c;
@@ -3844,7 +4051,7 @@
 #endif
 }
 
-#if  QLA1280_64BIT_SUPPORT
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
 /*
  * qla1280_64bit_start_scsi
  *      The start SCSI is responsible for building request packets on
@@ -3869,10 +4076,13 @@
     uint16_t        seg_cnt;
     struct scatterlist    *sg = (struct scatterlist *) NULL;
     uint32_t        *dword_ptr;
+    dma_addr_t       dma_handle;
 
-#ifdef QL_DEBUG_LEVEL_3
     ENTER("qla1280_64bit_start_scsi:");
-#endif
+
+    DEBUG(sprintf(debug_buff,
+          "64bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);)
+    DEBUG(qla1280_print(debug_buff));
 
     if( qla1280_check_for_dead_scsi_bus(ha, sp) )
     {
@@ -3883,9 +4093,10 @@
     seg_cnt = 0;
     req_cnt = 1;
     if (cmd->use_sg)
-    {
-        seg_cnt =  cmd->use_sg;
+    {   /* 3.13 64 bit */
         sg = (struct scatterlist *) cmd->request_buffer;
+        seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, 
+                    scsi_to_pci_dma_dir(cmd->sc_data_direction));
             
         if (seg_cnt > 2)
         {
@@ -3896,7 +4107,7 @@
     }
     else if (cmd->request_bufflen)  /* If data transfer. */
     {
-        DEBUG(printk("Single data transfer (0x%x)\n",cmd->request_bufflen));
+      /*DEBUG(printk("Single data transfer len=0x%x\n",cmd->request_bufflen));*/
         seg_cnt = 1;
     }
 
@@ -3957,7 +4168,7 @@
             /* Load SCSI command packet. */
             pkt->cdb_len = (uint16_t)CMD_CDBLEN(cmd);
             BCOPY(&(CMD_CDBP(cmd)), pkt->scsi_cdb, pkt->cdb_len);
-            DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0]));
+            //DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0]));
 
             /*
             * Load data segments.
@@ -3983,12 +4194,17 @@
                     /* Load command entry data segments. */
                     for (cnt = 0; cnt < 2 && seg_cnt; cnt++, seg_cnt--)
                     {
-                        DEBUG(sprintf(debug_buff,"SG Segment ap=0x%p, len=0x%x\n\r",sg->address,sg->length));
-                        DEBUG(qla1280_print(debug_buff));
-                        *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(sg->address));
-                        *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(sg->address));
-                        *dword_ptr++ = sg->length;
+                        /* 3.13 64 bit */
+                        *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                        *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg)));
+                        *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
                         sg++;
+                        DEBUG(sprintf(debug_buff,
+                         "S/G Segment phys_addr=%x %x, len=0x%x\n\r",
+                          cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))),
+                          cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                                      cpu_to_le32(sg_dma_len(sg)));)
+                        DEBUG(qla1280_print(debug_buff));
                     }
 #ifdef QL_DEBUG_LEVEL_5
                     qla1280_print(
@@ -4005,6 +4221,10 @@
                     /*
                     * Build continuation packets.
                     */
+                    DEBUG(sprintf(debug_buff,
+                    "S/G Building Continuation...seg_cnt=0x%x remains\n\r",
+                    seg_cnt);)
+                    DEBUG(qla1280_print(debug_buff));
                     while (seg_cnt > 0)
                     {
                         /* Adjust ring index. */
@@ -4038,10 +4258,17 @@
                         /* Load continuation entry data segments. */
                         for (cnt = 0; cnt < 5 && seg_cnt; cnt++, seg_cnt--)
                         {
-                            *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(sg->address));
-                            *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(sg->address));
-                            *dword_ptr++ = sg->length;
-                            sg++;
+                           /* 3.13 64 bit */
+                           *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                           *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg)));
+                           *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                           DEBUG(sprintf(debug_buff,
+                            "S/G Segment Cont. phys_addr=%x %x, len=0x%x\n\r",
+                             cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))),
+                             cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                             cpu_to_le32(sg_dma_len(sg)));)
+                           DEBUG(qla1280_print(debug_buff));
+                           sg++;
                         }
 #ifdef QL_DEBUG_LEVEL_5
                         qla1280_print(
@@ -4058,11 +4285,21 @@
 #endif
                     }
                 }
-                else                    /* No scatter gather data transfer */
-                {
-                    *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_LOW(cmd->request_buffer));
-                    *dword_ptr++ = cpu_to_le32(VIRT_TO_BUS_HIGH(cmd->request_buffer));
-                    *dword_ptr = (uint32_t) cmd->request_bufflen;
+                else         /* No scatter gather data transfer */
+                {   /* 3.13 64 bit */
+                    dma_handle = pci_map_single(ha->pdev, 
+                                                cmd->request_buffer,
+                                                cmd->request_bufflen,
+                                                scsi_to_pci_dma_dir(cmd->sc_data_direction));
+                    /* save dma_handle for pci_unmap_single */
+                    sp->saved_dma_handle = dma_handle;
+
+                    *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle));
+                    *dword_ptr++ = cpu_to_le32(pci_dma_hi32(dma_handle));
+                    *dword_ptr   = (uint32_t) cmd->request_bufflen;
+                    /*DEBUG(sprintf(debug_buff,
+                    "No S/G map_single saved_dma_handle=%lx\n\r",dma_handle));
+                    DEBUG(qla1280_print(debug_buff));*/
 #ifdef QL_DEBUG_LEVEL_5
                     qla1280_print(
                             "qla1280_64bit_start_scsi: No scatter/gather command packet data - c");
@@ -4077,12 +4314,12 @@
 #endif
                 }
             }
-#ifdef QL_DEBUG_LEVEL_5
-            else                            /* No data transfer */
+            else         /* No data transfer */
             {
                 *dword_ptr++ = (uint32_t) 0;
                 *dword_ptr++ = (uint32_t) 0;
                 *dword_ptr = (uint32_t)  0;
+#ifdef QL_DEBUG_LEVEL_5
                 qla1280_print(
                         "qla1280_64bit_start_scsi: No data, command packet data - c");
                 qla1280_print(" b ");
@@ -4093,8 +4330,8 @@
                 qla1280_output_number((uint32_t)SCSI_LUN_32(cmd), 10);
                 qla1280_print("\n\r");
                 qla1280_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE);
-            }
 #endif
+            }
             /* Adjust ring index. */
             ha->req_ring_index++;
             if (ha->req_ring_index == REQUEST_ENTRY_CNT)
@@ -4106,6 +4343,10 @@
                 ha->request_ring_ptr++;
 
             /* Set chip new ring index. */
+            DEBUG(qla1280_print("qla1280_64bit_start_scsi: Wakeup RISC for pending command\n\r"));
+            ha->qthreads--;
+            sp->flags |= SRB_SENT;
+            ha->actthreads++;
             WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
         }
         else
@@ -4146,7 +4387,7 @@
 #endif
     return(status);
 }
-#endif  /* QLA1280_64BIT_SUPPORT */
+#endif
 
 /*
  * qla1280_32bit_start_scsi
@@ -4181,8 +4422,15 @@
     uint8_t        *data_ptr;
     uint32_t        *dword_ptr;
 
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    dma_addr_t       dma_handle;
+#endif
+
     ENTER("qla1280_32bit_start_scsi");
 
+    DEBUG(sprintf(debug_buff,
+          "32bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);)
+    DEBUG(qla1280_print(debug_buff));
 
     if( qla1280_check_for_dead_scsi_bus(ha, sp) )
     {
@@ -4199,8 +4447,15 @@
         * differences and the kernel SG list uses virtual addresses where
         * we need physical addresses.
         */
-        seg_cnt =  cmd->use_sg;
         sg = (struct scatterlist *) cmd->request_buffer;
+        /* 3.13 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        seg_cnt =  cmd->use_sg;
+#else
+        seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, 
+                    scsi_to_pci_dma_dir(cmd->sc_data_direction));
+#endif
+
         /* 
         * if greater than four sg entries then we need to allocate
         * continuation entries
@@ -4211,17 +4466,22 @@
             if ((uint16_t)(seg_cnt - 4) % 7)
                 req_cnt++;
         }
-        DEBUG(sprintf(debug_buff,"S/G for data transfer -num segs(%d), req blk cnt(%d)\n\r",seg_cnt,req_cnt));
+        DEBUG(sprintf(debug_buff,
+         "S/G Transfer cmd=%x seg_cnt=0x%x, req_cnt=%x\n\r",
+          cmd,seg_cnt,req_cnt));
         DEBUG(qla1280_print(debug_buff));
     }
     else if (cmd->request_bufflen)  /* If data transfer. */
     {
-        DEBUG(printk("Single data transfer (0x%x)\n",cmd->request_bufflen));
+        DEBUG(sprintf(debug_buff,
+         "No S/G transfer t=%x cmd=%x len=%x CDB=%x\n\r",
+         SCSI_TCN_32(cmd),cmd,cmd->request_bufflen,cmd->cmnd[0]));
+        DEBUG(qla1280_print(debug_buff));
         seg_cnt = 1;
     }
     else
     {
-        DEBUG(printk("No data transfer \n"));
+      //DEBUG(printk("No data transfer \n"));
         seg_cnt = 0;
     }
 
@@ -4238,7 +4498,8 @@
             ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
     }
 
-    DEBUG(sprintf(debug_buff,"Number of free entries = (%d)\n\r",ha->req_q_cnt));
+    DEBUG(sprintf(debug_buff,"Number of free entries=(%d) seg_cnt=0x%x\n\r",
+          ha->req_q_cnt,seg_cnt));
     DEBUG(qla1280_print(debug_buff));
     /* If room for request in request ring. */
     if ((uint16_t)(req_cnt + 2) < ha->req_q_cnt)
@@ -4286,20 +4547,15 @@
             data_ptr = (uint8_t *) &(CMD_CDBP(cmd));
             for (cnt = 0; cnt < pkt->cdb_len; cnt++)
                 pkt->scsi_cdb[cnt] = *data_ptr++;
-            DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0]));
+            //DEBUG(printk("Build packet for command[0]=0x%x\n",pkt->scsi_cdb[0]));
             /*
             * Load data segments.
             */
             if (seg_cnt)
             {
-                DEBUG(printk("loading data segments..\n"));
                 /* Set transfer direction (READ and WRITE) */
                 /* Linux doesn't tell us                   */
-
                 /*
-                * 3/10 dg - Normally, we should need this check with our F/W
-                * but because of a small issue with it we do.
-                *
                 * For block devices, cmd->request.cmd has the operation 
                 * For character devices, this isn't always set properly, so
                 * we need to check data_cmnd[0].  This catches the conditions
@@ -4325,15 +4581,32 @@
                     /* Load command entry data segments. */
                     for (cnt = 0; cnt < 4 && seg_cnt; cnt++, seg_cnt--)
                     {
+                        /* 3.13 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
                         *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(sg->address));
                         *dword_ptr++ = sg->length;
-                        DEBUG(sprintf(debug_buff,"SG Segment ap=0x%p, len=0x%x\n\r",sg->address,sg->length));
+                        DEBUG(sprintf(debug_buff,
+                         "S/G Segment phys_addr=0x%x, len=0x%x\n\r",
+                          cpu_to_le32(VIRT_TO_BUS(sg->address)),sg->length));
+                        DEBUG(qla1280_print(debug_buff));
+#else
+                        *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                        *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                        DEBUG(sprintf(debug_buff,
+                         "S/G Segment phys_addr=0x%x, len=0x%x\n\r",
+                          cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                          cpu_to_le32(sg_dma_len(sg)));)
                         DEBUG(qla1280_print(debug_buff));
+#endif 
                         sg++;
                     }
                     /*
                     * Build continuation packets.
                     */
+                    DEBUG(sprintf(debug_buff,
+                    "S/G Building Continuation...seg_cnt=0x%x remains\n\r",
+                    seg_cnt);)
+                    DEBUG(qla1280_print(debug_buff));
                     while (seg_cnt > 0)
                     {
                         /* Adjust ring index. */
@@ -4368,9 +4641,25 @@
                         /* Load continuation entry data segments. */
                         for (cnt = 0; cnt < 7 && seg_cnt; cnt++, seg_cnt--)
                         {
-                            *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address));
-                            *dword_ptr++ = sg->length;
-                            sg++;
+                           /* 3.13 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                           *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address));
+                           *dword_ptr++ = sg->length;
+                           DEBUG(sprintf(debug_buff,
+                           "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r",
+                           cpu_to_le32(pci_dma_lo32(VIRT_TO_BUS(sg->address))),
+                           sg->length);)
+                           DEBUG(qla1280_print(debug_buff));
+#else
+                           *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                           *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                           DEBUG(sprintf(debug_buff,
+                            "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r",
+                             cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                             cpu_to_le32(sg_dma_len(sg)));)
+                           DEBUG(qla1280_print(debug_buff));
+#endif
+                           sg++;
                         }
 #ifdef QL_DEBUG_LEVEL_5
                         qla1280_print(
@@ -4385,14 +4674,28 @@
 #endif
                     }
                 }
-                else                    /* No scatter gather data transfer */
+                else     /* No S/G data transfer */
                 {
+                    /* 3.13 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
                     *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(cmd->request_buffer));
                     *dword_ptr = (uint32_t) cmd->request_bufflen;
-                    DEBUG(printk("Single Segment ap=0x%p, len=0x%x\n",cmd->request_buffer,cmd->request_bufflen));
+#else
+                    dma_handle = pci_map_single(ha->pdev, 
+                                                cmd->request_buffer,
+                                                cmd->request_bufflen,
+                                                scsi_to_pci_dma_dir(cmd->sc_data_direction));
+                    sp->saved_dma_handle = dma_handle;
+
+                    *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle));
+                    *dword_ptr   = (uint32_t) cmd->request_bufflen;
+                    /*DEBUG(sprintf(debug_buff,
+                    "No S/G map_single saved_dma_handle=%lx\n\r",dma_handle));
+                    DEBUG(qla1280_print(debug_buff));*/
+#endif 
                 }
             }
-            else                            /* No data transfer */
+            else         /* No data transfer at all */
             {
                 *dword_ptr++ = (uint32_t) 0;
                 *dword_ptr = (uint32_t)  0;
@@ -4420,10 +4723,8 @@
             /* Set chip new ring index. */
             DEBUG(qla1280_print("qla1280_32bit_start_scsi: Wakeup RISC for pending command\n\r"));
             ha->qthreads--;
-            sp->u_start = jiffies;
             sp->flags |= SRB_SENT;
             ha->actthreads++;
-            /* qla1280_output_number((uint32_t)ha->actthreads++, 16); */
             WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
         }
         else
@@ -4431,7 +4732,7 @@
             status = 1;
 #ifdef QL_DEBUG_LEVEL_2
             qla1280_print(
-                    "qla1280_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r");
+            "qla1280_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r");
             qla1280_print(" req_q_cnt=");
             qla1280_output_number((uint32_t)ha->req_q_cnt, 16);
             qla1280_print("\n\r");
@@ -4465,6 +4766,7 @@
     return(status);
 }
 
+
 /*
  * qla1280_req_pkt
  *      Function is responsible for locking ring and
@@ -4895,7 +5197,7 @@
 {
     device_reg_t    *reg = ha->iobase;
     response_t      *pkt;
-    srb_t           *sp;
+    srb_t           *sp = 0; 
     uint16_t        mailbox[MAILBOX_REGISTER_COUNT];
     uint16_t        *wptr;
     uint32_t        index;
@@ -4909,9 +5211,11 @@
     /* Check for mailbox interrupt. */
 
     mailbox[0] = RD_REG_WORD(&reg->semaphore);
+
     if (mailbox[0] & BIT_0)
     {
         /* Get mailbox data. */
+        //DEBUG(qla1280_print("qla1280_isr: In Get mailbox data \n\r");)
 
         wptr = &mailbox[0];
         *wptr++ = RD_REG_WORD(&reg->mailbox0);
@@ -4944,7 +5248,7 @@
         {
             case MBA_SCSI_COMPLETION:   /* Response completion */
 #ifdef QL_DEBUG_LEVEL_5
-                qla1280_print("qla1280_isr: mailbox response completion\n\r");
+                qla1280_print("qla1280_isr: mailbox SCSI response completion\n\r");
 #endif
                 if (ha->flags.online)
                 {
@@ -4973,9 +5277,11 @@
                         else
                             (*done_q_last)->s_next = sp;
                         *done_q_last = sp;
+
                     }
                     else
                     {
+
 #ifdef QL_DEBUG_LEVEL_2
                             qla1280_print("qla1280_isr: ISP invalid handle\n\r");
 #endif
@@ -5047,6 +5353,7 @@
 #endif
                 break;
             default:
+              //DEBUG(qla1280_print("qla1280_isr: default case of switch MB \n\r");)
                 if (mailbox[0] < MBA_ASYNC_EVENT)
                 {
                         wptr = &mailbox[0];
@@ -5063,9 +5370,9 @@
                 break;
         }
     }
-    else
+    else {
         WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
-
+    }
     /*
     * Response ring
     */
@@ -5129,6 +5436,7 @@
                         qla1280_error_entry(ha, pkt,
                                 done_q_first, done_q_last);
 
+
                     /* Adjust ring index. */
                     ha->rsp_ring_index++;
                     if (ha->rsp_ring_index == RESPONSE_ENTRY_CNT)
@@ -5312,9 +5620,12 @@
             }
             pkt->scsi_status = S_CKCON;
             pkt->option_flags |= (uint32_t)OF_SSTS | (uint32_t)OF_NO_DATA;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
             if (ha->flags.enable_64bit_addressing)
                 qla1280_64bit_continue_io(ha, pkt, 0, 0);
             else
+#endif
                 qla1280_32bit_continue_io(ha, pkt, 0, 0);
             break;
         case 0x16:                  /* Requested Capability Not Available */
@@ -5673,10 +5984,12 @@
                             (uint32_t)OF_NO_DATA;
                     break;
             }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
             if (ha->flags.enable_64bit_addressing)
-                qla1280_64bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr);
+               qla1280_64bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr);
             else
-                qla1280_32bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr);
+#endif
+               qla1280_32bit_continue_io(ha, pkt, len, (paddr32_t *)&phy_addr);
             break;
         default:
             break;
@@ -5750,11 +6063,13 @@
         ha->outstanding_cmds[pkt->handle] = 0;
 
         cp = sp->cmd;
+
         /* Generate LU queue on cntrl, target, LUN */
         b = SCSI_BUS_32(cp);
         t = SCSI_TCN_32(cp);
         l = SCSI_LUN_32(cp);
         q = LU_Q(ha, b, t, l);
+
         if( pkt->comp_status || pkt->scsi_status )
         {
             DEBUG(qla1280_print( "scsi: comp_status = ");)
@@ -5885,7 +6200,7 @@
         /* Place command on done queue. */
         qla1280_done_q_put(sp, done_q_first, done_q_last);
     }
-#if  QLA1280_64BIT_SUPPORT
+#if  BITS_PER_LONG > 32
     else if (pkt->entry_type == COMMAND_A64_TYPE)
     {
 #ifdef QL_DEBUG_LEVEL_2
@@ -5962,7 +6277,6 @@
                 sp->timeout += 2; */
 
                 /* Place request back on top of device queue. */
-                /* sp->flags &= ~(SRB_SENT | SRB_TIMEOUT); */ 
                 sp->flags = 0;
                 qla1280_putq_t(q, sp);
             }
@@ -6080,7 +6394,7 @@
                 }
             }
 #ifdef QL_DEBUG_LEVEL_3
-            qla1280_print("qla1280_restart_queues: exiting normally\n");
+            qla1280_print("qla1280_restart_queues: exiting normally\n\r");
 #endif
 }
 
@@ -6166,13 +6480,15 @@
     return(ret);
 }
 
-
-/*
- * Declarations for load module
- */
-static Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE;
-
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
+#ifdef MODULE
+Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE;
 #include "scsi_module.c"
+#endif
+#else   /* new kernel scsi initialization scheme */
+static  Scsi_Host_Template driver_template = QLA1280_LINUX_TEMPLATE;
+#include "scsi_module.c"
+#endif
 
 /************************************************************************
  * qla1280_check_for_dead_scsi_bus                                      *
@@ -6283,13 +6599,13 @@
 #if MEMORY_MAPPED_IO
     ret = *port;
 #else
-    ret = inb((int)port);
+    ret = inb((long)port);
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_getbyte: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)ret, 16);
         qla1280_print("\n\r");
@@ -6309,13 +6625,13 @@
 #if MEMORY_MAPPED_IO
     ret = *port;
 #else
-    ret = inw((int)port);
+    ret = inw((unsigned long)port);
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_getword: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)ret, 16);
         qla1280_print("\n\r");
@@ -6335,13 +6651,13 @@
 #if MEMORY_MAPPED_IO
     ret = *port;
 #else
-    ret = inl((int)port);
+    ret = inl((unsigned long)port);
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_getdword: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)ret, 16);
         qla1280_print("\n\r");
@@ -6359,13 +6675,13 @@
 #if MEMORY_MAPPED_IO
     *port = data;
 #else
-    outb(data, (int)port);
+    outb(data, (unsigned long)port);
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_putbyte: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)data, 16);
         qla1280_print("\n\r");
@@ -6384,14 +6700,14 @@
 #ifdef _LINUX_IOPORTS
     outw(data, (int)port);
 #else
-    outw((int)port, data);
+    outw((unsigned long)port, data);
 #endif
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_putword: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)data, 16);
         qla1280_print("\n\r");
@@ -6410,14 +6726,14 @@
 #ifdef _LINUX_IOPORTS
     outl(data,(int)port);
 #else
-    outl((int)port, data);
+    outl((unsigned long)port, data);
 #endif
 #endif
 
     if (ql_debug_print)
     {
         qla1280_print("qla1280_putdword: address = ");
-        qla1280_output_number((uint32_t)port, 16);
+        qla1280_output_number((unsigned long)port, 16);
         qla1280_print(" data = 0x");
         qla1280_output_number((uint32_t)data, 16);
         qla1280_print("\n\r");
@@ -6441,8 +6757,7 @@
 
 /*
  *  Out character to COM2 port.
- *      PORT must be at standard address for COM2 = 0x2F8,
- *      or COM1 = 0x3F8
+ *      PORT must be at standard address for COM1 = 0x3f8
  */
 #define OUTB(addr,data)   outb((data),(addr))
 
@@ -6452,7 +6767,7 @@
 #ifdef QL_DEBUG_CONSOLE
     printk("%c", c);
 #else
-    int     com_addr              = 0x2f8;
+    int     com_addr              = 0x3f8;
     int     hardware_flow_control = 1;
     int     software_flow_control = 0;
     uint8_t data;
@@ -6464,7 +6779,7 @@
     }while (!(data & BIT_6));
 
     /*
-    * Set BAUD rate for COM2 to 19200 (0x6)
+    * Set BAUD rate for COM2 to 9600 (0x6)
     */
 
     /* Select rate divisor. */
@@ -6660,8 +6975,6 @@
     qla1280_print(debug_buff);
     sprintf(debug_buff,"  Pid=%d, SP=0x%p\n\r", (int)cmd->pid, CMD_SP(cmd));
     qla1280_print(debug_buff);
-    sprintf(debug_buff,"  r_start=0x%lx, u_start=0x%lx\n\r",sp->r_start,sp->u_start);
-    qla1280_print(debug_buff);
     sprintf(debug_buff," underflow size = 0x%x, direction=0x%x, req.cmd=0x%x \n\r", cmd->underflow, sp->dir,cmd->request.cmd);    
     qla1280_print(debug_buff);
 }
@@ -6689,23 +7002,6 @@
 }
 #endif
 
-#ifdef  QLA1280_UNUSED 
-/**************************************************************************
- *   ql1280_dump_regs
- *
- **************************************************************************/
-static void qla1280_dump_regs(struct Scsi_Host *host)
-{
-    printk("Mailbox registers:\n");
-    printk("qla1280 : mbox 0 0x%04x \n", inw(host->io_port + 0x70));
-    printk("qla1280 : mbox 1 0x%04x \n", inw(host->io_port + 0x72));
-    printk("qla1280 : mbox 2 0x%04x \n", inw(host->io_port + 0x74));
-    printk("qla1280 : mbox 3 0x%04x \n", inw(host->io_port + 0x76));
-    printk("qla1280 : mbox 4 0x%04x \n", inw(host->io_port + 0x78));
-    printk("qla1280 : mbox 5 0x%04x \n", inw(host->io_port + 0x7a));
-}
-#endif
-
 
 
 #if  STOP_ON_ERROR 
@@ -6732,9 +7028,6 @@
     printk("HA flags =0x%lx\n", *fp);
     DEBUG2(ql_debug_print = 1;)
     /* DEBUG2(ql1280_dump_device((scsi_qla_host_t *) host->hostdata)); */
-#ifdef  QLA1280_UNUSED 
-    qla1280_dump_regs(host);
-#endif
     sti();  
     panic("Ooops");  
     /* cli(); 
@@ -6747,11 +7040,6 @@
 }
 #endif
 
-#ifdef  QLA1280_UNUSED 
-static void qla1280_set_flags(char * s)
-{
-}
-#endif
 
 /**************************************************************************
  *   qla1280_setup
@@ -6765,24 +7053,6 @@
 {
     char *end, *str, *cp;
 
-#ifdef  QLA1280_UNUSED 
-    static struct
-    {
-        const char *name;
-        int      siz;
-        void  (*func)();
-        int   arg;
-    } options[] =
-    {
-        { "dump_regs", 9,  &qla1280_dump_regs, 0 
-        },
-        { "verbose", 7, &qla1280_set_flags, 0x1 
-        },
-        { "",    0, NULL, 0 
-        }
-    };
-#endif
-
     printk("scsi: Processing Option str = %s\n", s);
     end = strchr(s, '\0');
     /* locate command */
@@ -6832,4 +7102,3 @@
  * tab-width: 8
  * End:
  */
-
diff -urN linux-2.4.16/drivers/scsi/qla1280.h lia64-2.4/drivers/scsi/qla1280.h
--- linux-2.4.16/drivers/scsi/qla1280.h	Mon Sep 24 15:07:46 2001
+++ lia64-2.4/drivers/scsi/qla1280.h	Mon Nov 26 18:11:19 2001
@@ -1,169 +1,35 @@
-/*************************************************************************
- *                  QLOGIC LINUX SOFTWARE
- *
- * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.x).
- *
- * COPYRIGHT (C) 1996-2000 QLOGIC CORPORATION    
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the Qlogic's Linux Software License.
- *
- * This program is WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistribution's or source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- *****************************************************************************/
- 
-/*************************************************************************************
-			QLOGIC CORPORATION SOFTWARE
-           "GNU" GENERAL PUBLIC LICENSE
-    TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION
-                 AND MODIFICATION
-
-This GNU General Public License ("License") applies solely to QLogic Linux 
-Software ("Software") and may be distributed under the terms of this License.  
- 
-1. You may copy and distribute verbatim copies of the Software's source code as 
-you receive it, in any medium, provided that you conspicuously and appropriately 
-publish on each copy an appropriate copyright notice and disclaimer of warranty;
-keep intact all the notices that refer to this License and to the absence of any
-warranty; and give any other recipients of the Software a copy of this License along
-with the Software. 
-
-You may charge a fee for the physical act of transferring a copy, and you may at your
-option offer warranty protection in exchange for a fee.
- 
-2. You may modify your copy or copies of the Software or any portion of it, thus forming
-a work based on the Software, and copy and distribute such modifications or work under
-the terms of Section 1 above, provided that you also meet all of these conditions:
- 
-* a) You must cause the modified files to carry prominent notices stating that you
-changed the files and the date of any change. 
-
-* b) You must cause any work that you distribute or publish that in whole or in part
-contains or is derived from the Software or any part thereof, to be licensed as a
-whole at no charge to all third parties under the terms of this License. 
-
-* c) If the modified Software normally reads commands interactively when run, you
-must cause it, when started running for such interactive use in the most ordinary way,
-to print or display an announcement including an appropriate copyright notice and a 
-notice that there is no warranty (or else, saying that you provide a warranty) and that
-users may redistribute the Software under these conditions, and telling the user how to
-view a copy of this License. (Exception:if the Software itself is interactive but does 
-not normally print such an announcement, your work based on the Software is not required
-to print an announcement.) 
-
-These requirements apply to the modified work as a whole. If identifiable sections of
-that work are not derived from the Software, and can be reasonably considered independent
-and separate works in themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works. But when you distribute the same
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-whole must be on the terms of this License, whose permissions for other licensees extend
-to the entire whole, and thus to each and every part regardless of who wrote it. 
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-3. You may copy and distribute the Software (or a work based on it, under Section 2) in 
-object code or executable form under the terms of Sections 1 and 2 above provided that
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-party, for a charge no more than your cost of physically performing source distribution,
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-or,
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-* c) Accompany it with the information you received as to the offer to distribute 
-corresponding source code. (This alternative is allowed only for noncommercial distribution
-and only if you received the Software in object code or executable form with such an offer,
-in accord with Subsection b above.) 
-
-The source code for a work means the preferred form of the work for making modifications
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-If distribution of executable or object code is made by offering access to copy from a 
-designated place, then offering equivalent access to copy the source code from the same
-place counts as distribution of the source code, even though third parties are not 
-compelled to copy the source along with the object code. 
-
-4. You may not copy, modify, sublicense, or distribute the Software except as expressly 
-provided under this License. Any attempt otherwise to copy, modify, sublicense or 
-distribute the Software is void, and will automatically terminate your rights under this
-License. However, parties who have received copies, or rights, from you under this License
-will not have their licenses terminated so long as such parties remain in full compliance. 
-
-5. This license grants you world wide, royalty free non-exclusive rights to modify or 
-distribute the Software or its derivative works. These actions are prohibited by law 
-if you do not accept this License. Therefore, by modifying or distributing the Software
-(or any work based on the Software), you indicate your acceptance of this License to do
-so, and all its terms and conditions for copying, distributing or modifying the Software
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-6. Each time you redistribute the Software (or any work based on the Software), the 
-recipient automatically receives a license from the original licensor to copy, distribute
-or modify the Software subject to these terms and conditions. You may not impose any 
-further restrictions on the recipients' exercise of the rights granted herein. You are
-not responsible for enforcing compliance by third parties to this License.
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-7. If, as a consequence of a court judgment or allegation of patent infringement or for
-any other reason (not limited to patent issues), conditions are imposed on you 
-(whether by court order, agreement or otherwise) that contradict the conditions of this
-License, they do not excuse you from the conditions of this License. If you cannot 
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-Software at all.    
-
-If any portion of this section is held invalid or unenforceable under any particular 
-circumstance, the balance of the section is intended to apply and the section as a whole
-is intended to apply in other circumstances. 
-NO WARRANTY
-
-11. THE SOFTWARE IS PROVIDED WITHOUT A WARRANTY OF ANY KIND. THERE IS NO 
-WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW. 
-EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR 
-OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND, 
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-SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 
-NECESSARY SERVICING, REPAIR OR CORRECTION.
- 
-12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 
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-OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS 
-BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
-END OF TERMS AND CONDITIONS 
+/********************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
+* Copyright (C) 2000 Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+**
+******************************************************************************/
 
-*************************************************************************************/ 
-
- 
 #ifndef _IO_HBA_QLA1280_H           /* wrapper symbol for kernel use */
 #define _IO_HBA_QLA1280_H           /* subject to change without notice */
 
+
+#ifndef LINUX_VERSION_CODE 
+#include <linux/version.h>
+#endif  /* LINUX_VERSION_CODE not defined */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
-#include <linux/version.h>
-
+#ifndef HOSTS_C                     /* included in hosts.c */
 /*
  * Enable define statement to ignore Data Underrun Errors,
  * remove define statement to enable detection.
@@ -173,15 +39,18 @@
 /*
  * Driver debug definitions.
  */
-/* #define QL_DEBUG_LEVEL_1 */       /* Output register accesses to COM2. */
-/* #define QL_DEBUG_LEVEL_2 */           /* Output error msgs to COM2. */
-/* #define QL_DEBUG_LEVEL_3 */          /* Output function trace msgs to COM2. */
-/* #define QL_DEBUG_LEVEL_4 */       /* Output NVRAM trace msgs to COM2. */
-/* #define QL_DEBUG_LEVEL_5 */         /* Output ring trace msgs to COM2. */
-/* #define QL_DEBUG_LEVEL_6 */      /* Output WATCHDOG timer trace to COM2. */
-/* #define QL_DEBUG_LEVEL_7 */      /* Output RISC load trace msgs to COM2. */
+/* #define QL_DEBUG_LEVEL_1 */      /* Output register accesses to COM1 */
+/* #define QL_DEBUG_LEVEL_2 */       /* Output error msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_3 */      /* Output function trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_4 */       /* Output NVRAM trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_5 */      /* Output ring trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_6 */      /* Output WATCHDOG timer trace to COM1 */
+/* #define QL_DEBUG_LEVEL_7 */      /* Output RISC load trace msgs to COM1 */
+
+#define QL_DEBUG_CONSOLE    /* Output to console instead of COM1   */
+  /* comment this #define to get output of qla1280_print to COM1         */
+  /* if COM1 is not connected to a host system, the driver hangs system! */
 
-#define QL_DEBUG_CONSOLE              /* Output to console instead of COM2. */
 
 #ifndef TRUE
 #  define TRUE 1
@@ -206,7 +75,11 @@
  * Locking
  */
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
-#  include <linux/spinlock.h>
+#  if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+#    include <asm/spinlock.h>
+#  else
+#    include <linux/spinlock.h>
+#  endif
 #  include <linux/smp.h>
 #  define cpuid smp_processor_id()
 #  if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
@@ -314,12 +187,12 @@
 #define WRT_REG_DWORD(addr, data) qla1280_putdword((uint32_t *)addr, data)
 #else  /* QL_DEBUG_LEVEL_1 */
 #ifdef MEMORY_MAPPED_IO
-       #define RD_REG_BYTE(addr)         readb((unsigned long) (addr)
-       #define RD_REG_WORD(addr)         readw((unsigned long) (addr)
-       #define RD_REG_DWORD(addr)        readl((unsigned long) (addr)
-       #define WRT_REG_BYTE(addr, data)  writeb((data), (unsigned long) (addr))
-       #define WRT_REG_WORD(addr, data)  writew((data), (unsigned long) (addr))
-       #define WRT_REG_DWORD(addr, data) writel((data), (unsigned long) (addr))
+      #define RD_REG_BYTE(addr)         (*((volatile uint8_t *)addr))
+       #define RD_REG_WORD(addr)         (*((volatile uint16_t *)addr))
+       #define RD_REG_DWORD(addr)        (*((volatile uint32_t *)addr))
+       #define WRT_REG_BYTE(addr, data)  (*((volatile uint8_t *)addr) = data)
+       #define WRT_REG_WORD(addr, data)  (*((volatile uint16_t *)addr) = data)
+       #define WRT_REG_DWORD(addr, data) (*((volatile uint32_t *)addr) = data) 
 #else   /* MEMORY_MAPPED_IO */
 #define RD_REG_BYTE(addr)         (inb((unsigned long)addr))
 #define RD_REG_WORD(addr)         (inw((unsigned long)addr))
@@ -372,7 +245,8 @@
 
 
 /*
- * SCSI Request Block structure
+ * SCSI Request Block structure  (sp)  that is placed
+ * on cmd->SCp location of every I/O
  */
 typedef struct srb
 {
@@ -381,10 +255,11 @@
     struct srb  *s_prev;             /* (4) Previous block on LU queue */
     uint8_t     flags;               /* (1) Status flags. */
     uint8_t     dir;                 /* direction of transfer */
-    uint8_t     unused[2];
-    u_long      r_start;             /* jiffies at start of request */
-    u_long      u_start;             /* jiffies when sent to F/W    */
-}srb_t;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    dma_addr_t  saved_dma_handle;    /* for unmap of single transfers */
+#endif
+   
+} srb_t;
 
 /*
  * SRB flag definitions
@@ -1562,22 +1437,35 @@
 
     request_t       req[REQUEST_ENTRY_CNT+1];
     response_t      res[RESPONSE_ENTRY_CNT+1];
-    unsigned long   request_dma;        /* Physical address. */
+#if BITS_PER_LONG > 32
+    dma_addr_t      request_dma;        /* Physical Address */
+#else
+    uint32_t        request_dma;        /* Physical address. */
+#endif
     request_t       *request_ring;      /* Base virtual address */
     request_t       *request_ring_ptr;  /* Current address. */
     uint16_t        req_ring_index;     /* Current index. */
     uint16_t        req_q_cnt;          /* Number of available entries. */
 
-    unsigned long   response_dma;       /* Physical address. */
+#if BITS_PER_LONG > 32
+    dma_addr_t      response_dma;       /* Physical address. */
+#else
+    uint32_t        response_dma;       /* Physical address. */
+#endif
     response_t      *response_ring;     /* Base virtual address */
     response_t      *response_ring_ptr; /* Current address. */
     uint16_t        rsp_ring_index;     /* Current index. */
 
 #if QL1280_TARGET_MODE_SUPPORT
     /* Target buffer and sense data. */
+#if BITS_PER_LONG > 32
+    dma_addr_t      tbuf_dma;           /* Physical address. */
+    dma_addr_t      tsense_dma;         /* Physical address. */
+#else
     uint32_t        tbuf_dma;           /* Physical address. */
-    tgt_t           *tbuf;
     uint32_t        tsense_dma;         /* Physical address. */
+#endif
+    tgt_t           *tbuf;
     uint8_t         *tsense;
 #endif
 
@@ -1614,8 +1502,13 @@
        uint32_t     dpc                     :1;   /* 15 */
        uint32_t     dpc_sched               :1;   /* 16 */
        uint32_t     interrupts_on               :1;   /* 17 */
+       uint32_t     bios_enabled               :1;   /* 18 */
     }flags;
 
+  /* needed holders for PCI ordered list of hosts */
+  unsigned long io_port;
+  uint32_t irq;
+
 }scsi_qla_host_t;
 
 /*
@@ -1644,6 +1537,8 @@
 #define QLA1280_RING_LOCK(ha)  
 #define QLA1280_RING_UNLOCK(ha)   
 
+#endif  /* HOSTS_C */
+
 #if defined(__cplusplus)
 }
 #endif
@@ -1661,49 +1556,20 @@
 int qla1280_biosparam(Disk *, kdev_t, int[]);
 void qla1280_intr_handler(int, void *, struct pt_regs *);
 void qla1280_setup(char *s, int *dummy);
-#if defined(__386__)
+
 #  define QLA1280_BIOSPARAM  qla1280_biosparam
-#else
-#  define QLA1280_BIOSPARAM  NULL
-#endif
 
 /*
  * Scsi_Host_template (see hosts.h) 
  * Device driver Interfaces to mid-level SCSI driver.
  */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
-/* This interface is now obsolete !!! */ 
-#define QLA1280_LINUX_TEMPLATE {		                 \
-        next:           NULL,                                    \
-        usage_count:    NULL,                                    \
-	proc_dir:		NULL,          	                 \
-	proc_info:		NULL,	                         \
-	name:			"Qlogic ISP 1280",               \
-	detect:			qla1280_detect,	                 \
-	release:		qla1280_release,                 \
-	info:			qla1280_info,	                 \
-        command:        NULL,                                    \
-	queuecommand:	qla1280_queuecommand,	                 \
-	abort:			qla1280_abort,	                 \
-	reset:			qla1280_reset,	                 \
-        slave_attach:   NULL,                                    \
-	bios_param:		QLA1280_BIOSPARAM,               \
-	can_queue:		255, /* MAX_OUTSTANDING_COMMANDS */   \
-	this_id:		-1,  /* scsi id of host adapter */        \
-	sg_tablesize:	SG_ALL,	 \
-	cmd_per_lun:	3,	  /* max commands per lun */	       \
-	present:	    0,    /* number of 1280s present */	       \
-	unchecked_isa_dma: 0, /* no memeory DMA restrictions */    \
-	use_clustering:	ENABLE_CLUSTERING			               \
-}
-#else
 
-#define QLA1280_LINUX_TEMPLATE {		                 \
+#define QLA1280_LINUX_TEMPLATE {		                \
 	next: NULL,						\
 	module: NULL,						\
 	proc_dir: NULL,						\
 	proc_info: qla1280_proc_info,				\
-	name:			"Qlogic ISP 1280\1080",               \
+	name:			"Qlogic ISP 1280\12160",        \
 	detect: qla1280_detect,					\
 	release: qla1280_release,				\
 	info: qla1280_info,					\
@@ -1723,13 +1589,14 @@
 	this_id: -1,		/* scsi id of host adapter    */\
 	sg_tablesize: SG_ALL,	/* max scatter-gather cmds    */\
 	cmd_per_lun: 3,		/* cmds per lun (linked cmds) */\
-	present: 0,		/* number of 7xxx's present   */\
+	present: 0,		/* number of 1280's present   */\
 	unchecked_isa_dma: 0,	/* no memory DMA restrictions */\
 	use_clustering: ENABLE_CLUSTERING,			\
 	use_new_eh_code: 0,					\
 	emulated: 0					        \
 }
-#endif
+
 
 
 #endif /* _IO_HBA_QLA1280_H */
+
diff -urN linux-2.4.16/drivers/scsi/qla2x00.c lia64-2.4/drivers/scsi/qla2x00.c
--- linux-2.4.16/drivers/scsi/qla2x00.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qla2x00.c	Mon Jul 23 14:12:22 2001
@@ -0,0 +1,12823 @@
+/********************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic QLA2x00 device driver for Linux 2.2.x and 2.4.x 
+* Copyright (C) 2000 and 2001         Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+**
+******************************************************************************/
+#define QLA2100_VERSION      "4.31.7b"
+/****************************************************************************
+Revision History:
+    Rev. 4.31.7b		June 8, 2001		DG QLogic
+	- Fixed issue when loop id for target is changed to a different
+	 loop id.
+    Rev. 4.31.6		June 1, 2001		DG QLogic
+        - Official 2200 firmware: v2.01.34
+        - Official 2300 firmware: v3.00.24
+    Rev. 4.31.5b	May 30, 2001		DG QLogic
+	- Reset SRB_SENT flag in all isr routines.
+	- Fix displaying garbage when using /proc.
+    Rev. 4.31.3b	May 15, 2001		DG QLogic
+        - Using test 2200 firmware: v204.01.33
+    Rev. 4.31.2b	May 15, 2001		DG QLogic
+        - Using test 2200 firmware: v203.01.33
+    Rev. 4.31.1b	May 15, 2001		DG QLogic
+        - Upgrade FC firmware to: 2200 v209.01.27
+	- Changed logic to handle a topology of 4 after issuing the
+	  "Get Host loop id".
+    Rev. 4.31b		May 15, 2001		RL QLogic
+	- Added code to export PCI device info via a new ioctl function
+	  in kernel 2.4.4.
+	- Redirect console messages to the OS messages file only.
+	- Additional fix in ioctl functions for node/port name endianess
+	  problem.
+    Rev. 4.30b		May 3, 2001		RL QLogic
+	- Moved the allocation of host database to outside of the adapter
+	  structure allocation to avoid the allocation size limitation in the
+	  scsi_register function.
+    Rev. 4.29b		April 27, 2001		RL QLogic
+	- Fixed endianess of the node and port names read from the config
+	  file for persistent binding entries.
+    Rev. 4.28b		April 26, 2001		DG QLogic
+	- Fixed persistent binding of target devices.
+    Rev. 4.27		April 26, 2001		DG QLogic
+	- Fixed Mailbox timeout logic
+	- Fixed to compile on 2.4.x RedHat systems.
+    Rev. 4.25 	         March 15, 2001    DG QLogic
+	- released
+    Rev. 4.25 Beta       March 9, 2001    DG QLogic
+	- incl new qlavendor.c file.
+    Rev. 4.24 Beta Test32  February 22, 2001    BN QLogic
+        - Added code for scanning of missing LUN to let the
+          SCSI layer skip it.
+        - Revised init_cb_t structure in qla2x00.h for the new
+          QLA2300 as well as QLA2200 devices.
+        - Changed criteria of 64/32 Bit mode of HBA
+          operation according to BITS_PER_LONG rather
+          than HBA's NVRAM setting of >4Gig memory bit;
+          so that the HBA auto-configures without the need
+          to setup each system individually.
+        - Merged changes for proper compile and operation in Alpha systems.
+        - Upgrade FC firmware to: QLA2300 v3.00.18 *new
+          and enabled FC Loopback test on QLA2300 HBAs.
+        - Add statistics counters and IOCTL support for
+          HBA Error Count, LIP Resets, and total ISR count.
+        - Changed qla2100_reinit on loop down after 4 minutes 
+          specific to QLA2100 HBAs only.
+        - Added code and Makefile option to handle RISC code 
+          download differently for ia-64 platforms than x86 or alpha.
+    Rev. 4.23 Beta       January 12, 2001    BN QLogic
+        - Use cmd->sc_data_direction for setting of HBA data transfer
+          direction for 2.4.0 and higher kernels.
+          Note: Users must set the reply_len in sg_header.
+                For Writes and no data transfer; reply_len should
+                be the lenght of sg_header.
+                For Reads, reply_len should be the length of sg_header
+                plus the number of bytes to be read.
+        - Added check of SCSI_RESET_SUGGEST_BUS_RESET during 
+          qla2100_reset() and perform BUS_RESET. 
+          Also perform DEVICE_RESET on else of flag checking.
+        - Added new /proc/scsi/qla2x00/HbaApiNode for IOCTL interface
+          for 2.4.x kernels; so driver can be accessed with out need
+          to have at least one mapped scsi drive.
+        - Modified qla2100_mailbox_command's second parameter
+          to 32 bits for use by Loop-Back Diagnostic function
+        - Increase MAILBOX_REGISTER_COUNT to 32
+        - Added Loop-Back Diagnostic function to qla2x00ioctl.c
+          for QLA2200 HBAs only.
+        - Order HBA detection as follows:
+          QLA2300, QLA2200, QLA2100.
+        - Changed queue_task() to queue_task_irq() in 
+          qla2100_intr_handler() for proper usage.
+        - In qla2100_register_with_Linux() put check and getting 
+          device iobase before registering of interrupt with Linux;
+          to help with driver loading/unloading when ramdisk is also loaded.
+        - Change IOCTL support to SDM_VERSION 5 in qla2x00ioctl.c
+          to be support SNIA HBA API 1.0 Library
+        - Upgrade FC firmware to: QLA2200 v2.01.27 *new
+                                  QLA2300 v3.00.17 *new
+        - Added copy of HBA Serial Number to /proc entry
+        - Added sigmask(SIGKILL) as second parameter to 
+          siginitsetinv() function called during qla2100_do_dpc();
+          so that the driver can be unloaded for 2.4.0 kernels.
+    Rev. 4.22 Beta       November 22, 2000    BN QLogic
+        - Change IOCTL support to SDM_VERSION 4 in qla2x00_v4_ioctl.c
+          to be compatible with ln_rel-1.0Beta API library
+    Rev. 4.21 Beta       November 15, 2000    BN QLogic
+        - Upgrade FC firmware to: 2100 v1.19.16
+                                  2200 v2.01.24
+                                  2300 v3.00.12
+        - Merge of qla2x00 driver 2.19.16Beta changes.
+        - Updated qlavendor.c for vendor unique command
+          decoding. 
+    Rev. 4.20 Beta       October 17, 2000    BN QLogic
+        - QLA2300 Support added.
+    Rev. 4.14 Beta       October 16, 2000    BN QLogic
+        - Added setting of higher address bits for
+          MBC_INITIALIZE_FIRMWARE operation.
+        - Release also contains newer qlavendor.c file
+        - Move to the new SCSI initialization scheme
+          and always declare the static driver_template
+          for kernels 2.4.0 and higher
+    Rev. 4.13 Beta       September 21, 2000    BN QLogic
+        - Added "quiet" option to keep from printing LIP
+          occurred messages on systems that specify it.
+        - Added option to choose tp or ef, FC firmware
+    Rev. 4.12 Beta       September 18, 2000    BN QLogic
+        - Added pci_set_master() to qla2100_pci_config
+          function to make sure all systems are supported
+    Rev. 4.11 Beta       September 6, 2000    BN QLogic
+        - Enabled IOCTLs for external IOCTL and APIs
+    Rev. 4.10 Beta       August 28, 2000      BN Qlogic
+        - Use new PCI DMA mapping APIs for 2.4.x kernel
+        - Added driver IOCTL support code; but disabled
+          it with #if 0 for next release
+        - Verified correct 64 bit addressing with NVRAM:
+          enable_64bit_addressing (>4GByte Addressing)
+          enabled in BIOS advanced settings option.
+    Rev. 4.0           July  24, 2000      BN Qlogic
+        - Added FC Tape Support by use of new FC Firmware
+             ql2100_fw.h   must be  v1.19.12  or greater
+             ql2200_fw.h   must be  v2.01.16  or greater
+        - Corrected HBA Node Name equal to zero 
+        - Changed QLBoardTbl to QLBoardTbl_fc to avoid
+          double definition error with regards to qla1280
+          on new 2.4.0 kernel build tools
+    Rev. 3.90 Beta     July  21, 2000      BN Qlogic
+	- Added 64 bit OS and IA-64 hardware support
+        - Move to new major revision number
+    Rev. 2.22         July  14, 2000      BN Qlogic
+	- Updated 2100 FW to  1.19.10
+	- Updated 2200 FW to  2.01.14
+	- Move version to 2.22 for release to DVT
+    Rev. 2.19.8       July  11, 2000      DG Qlogic
+    - Fixed 2100 issue of login retry when no fabric is attached.
+    Rev. 2.19.7       July  6, 2000      DG
+    - Set queue depth per lun to 16 instead of throttle which is a
+      port max queue size and added an option "ql2xmaxqdepth=xx"
+      to allow user to change queue depth. This prevents us from
+      exceeding the adapter's throttle size which causes requests
+      to sit in the input queue for long periods of time.
+    Rev. 2.19.6       June  28, 2000      DG Qlogic
+    - GA release 
+    - Fixed panic in putq_t routine when called from abort.
+    Rev. 2.19.5b7     June  27, 2000      DG
+    - Add logic to wait reset delay if no fabric devices are found.
+    Rev. 2.19.5b6     June  26, 2000      DG
+    - Fixed Fw ready issue.
+    - Clear sent flag in SRB, so we will abort commands in Lun
+      queue that were previously sent.
+    - Flush input queue when an isp_abort occurs.
+    Rev. 2.19.5b5     June  16, 2000      DG
+    - Fixed issue of not holding off request if multiple RSCN or
+      PORT updates occur while process the currect RSCN.
+    Rev. 2.19.5b4     June  16, 2000      DG
+    - Added lock for done_q to prevent losing requests in timer.
+    Rev. 2.19.5b3     June  16, 2000      DG
+    - Added routine to set the correct direction for vendor specific
+      commands. Set the new option "QLA_SCSI_VENDOR_DIR".
+    - Fixed issue of retrying continuously on a Missing SCSI device.
+    - Fixed multiple adapter issue. Only login into adapter node 
+      once and never again. 
+    - Change code not to use loop id 0 for Fabric nodes. 
+    Rev. 2.19.5b2     June  15, 2000      DG
+    - Added code to reset port down count on good requests.
+    Rev. 2.19.5       June  8, 2000      DG
+    - Added code to display the connection type F, FL, or N.
+    - Reaarange code in DPC routine to put "retry login"
+      further  down in the routine and skip is loop is down.
+    - Check the returned status after GAN (qla2100_sns_device)
+      and retry on ISP TX timeout (0x4005).
+    Rev. 2.19.4       June  6, 2000      DG
+    - Fixed for panic that occurs when system is shutdown.
+    Rev. 2.19.3       June  5, 2000      DG
+    - Fixed retry logic for user configured targets.
+    Rev. 2.19.2       May  31, 2000      DG
+    - Remove spinlock in qla2100_timer.
+    - Change the jiffies timer to loop timer in fw_ready. 
+    Rev. 2.19.1       May  6, 2000      DG
+    - Change risc code 2200 from 2.1.12 to 2.1.13 to correct issue
+      of getting mailbox timeouts.
+    - Change mailbox timer to get correct timeout.
+    - Added qla2100_cmd_wait to wait for outstanding commands to
+      complete before querying the name server after a LIP.  
+    Rev. 2.19         May  6, 2000      DG
+    - Fixed mailbox timeout recovery logic.
+    Rev. 2.18         May  1, 2000      DG
+    - Changes from Fabric testing
+    Rev. 2.18b4       Apr 21, 2000      DG
+    - Fixed login retry count to retry count.
+    - If the loop is down for more than 4 minutes then restart 
+      queues and reset adpater if enabled.
+    - In qla2100_queuecommand we no longer return new requests 
+      immediately back to kernel when loop is down. This causes
+      SYSTEM to HANG when a lot of requests are outstanding. We 
+      now put them in the done queue and let the DPC routine 
+      return them to kernel.
+    - Fixed panic cause by changing the timeout value of new request
+      when the loop is down. 
+    - Cleanup qla2100_next.
+    Rev. 2.18b3       Apr 18, 2000      DG
+    - After the GAN, check returned status in resp buffer.
+    Rev. 2.18b2       Apr 12, 2000      DG
+    - Added handling of firmware bug when we use connection mode
+      1 (P2P). The firmware tries to change to loop mode after
+      encountering some IO failures/resets.
+    - Added logic to reset all modules during a chip reset.
+    - After the GAN, if we lost devices or have a device that was 
+      configured by the user then retry the login. This is a 
+      work-a-round for Brocade switches. It sometimes does
+      not return all the devices in the port list.
+    Rev. 2.18b1     Apr 1, 2000      DG
+    - Added logic to ignore device types other than FL/F 
+      from gan list. Mcdata switch returns a bogus port of
+      type 85 in the list.
+    - Added firmware 2.1.11 to fix issues with reusing loop ids.
+    Rev. 2.17       Mar 21, 2000      DG
+    - Fixed mailbox timeout timer.
+    - Added counters to record timeouts and aborts.
+    Rev. 2.16       Mar 8, 2000      DG
+    - Fixed Profiling code to reduced output of inactive devices.
+    - Fixed driver name in "/proc/scsi/qla2x00" instead of "qla".
+    - Fixed extended timeout value for loop down retries.
+    - Fixed code that search for target binding in command line to search
+      for all occurences instead of the first four.
+    - Disable the reinit of adapter when the LOOP is DOWN
+      for more than 4 minutes. It can be enabled with the command
+      line option "reinit_on_loopdown".
+    - Fixed issue of not setting HBA instance number before
+      calling HBA initialized.
+    Rev. 2.15       Feb 19, 2000      DG
+    - Fixed 2100 issue of driver not seeing storage when switch is connected
+      to loop.
+    Rev. 2.14       Feb 11, 2000      DG
+    - Added new logic to accept persistent binding information from the command line.
+    - Modified command parser to handle properties on the command line after
+      the regular options.
+    Rev. 2.13       Jan 27, 2000      TT
+    - Modify to use makefile parameter "IP=1" to enanle IP support.
+    - Fix SNS mailbox cmd parameter in qla2x00_register_ip_device.
+    - Reverse byte order on ha->port_id to match NT and fix compare bugs.
+    Rev. 2.12       Jan 26, 2000      TT+DG
+    - Updated Qlogic Linux sofware license.
+    - Added IP support for qla2xip driver.
+    - Fix host adapter structure initialization in qla2100_detect.
+    - Fix port name byte order in qla2100_update_fc_db.
+    - Fix the issue of not returning "NO_CONNECT" back to the user
+      when the loop is down after the loop down timer has expired.
+    - Added option QLA2100_EXT_TIMEOUT to extend timeout of each command.
+      default if OFF.
+    - Change device high water mark (hiwat) to execution throttle.
+    Rev. 2.11       Dec 8, 1999       DG
+    - Added Qlogic Linux sofware license.
+    Rev. 2.10       Oct 31, 1999      DG
+    - Fixed issue of not releasing requests if port is down (DPC issue).
+    - Ignore BIOS setting for MAX number of luns unless USE_BIOS_MAX_LUNS
+    is set.
+*****************************************************************************/
+  
+/*
+* Compile time Options:
+*            0 - Disable and 1 - Enable
+*/
+#define  QL2100_TARGET_MODE_SUPPORT    0   /* Target mode support */
+#define  MEMORY_MAPPED_IO              0
+#define  DEBUG_QLA2100_INTR            0
+#define  USE_NVRAM_DEFAULTS	       0
+#define  DEBUG_PRINT_NVRAM             0
+#define  LOADING_RISC_ACTIVITY         0
+#define  AUTO_ESCALATE_RESET           0   /* Automatically escalate resets */
+#define  AUTO_ESCALATE_ABORT           0   /* Automatically escalate aborts */
+#define  STOP_ON_ERROR                 0   /* Stop on aborts and resets  */
+#define  STOP_ON_RESET                 0
+#define  STOP_ON_ABORT                 0
+#define  QLA2100_COMTRACE              0    /* One char tracing  */
+#define  WATCH_THREADS_SIZ             0    /* watch size of pending queue */
+#define  USE_PORTNAME                  1    /* option to use port names for targets */
+#define  QLA2100_EXT_TIMEOUT           0    /* Extend timeout for commands up to 1 min*/
+#define  LUN_MASKING                   0
+#define  USE_FLASH                     0
+#define  QLA2100_PROFILE               1
+#define  QLA_SCSI_VENDOR_DIR           0 /* Decode vendor specific opcodes for direction */
+#define QLA2100_LIPTEST    	       0
+#define REQ_TRACE    		       1
+
+#undef   TRACECODE                       /* include tracing code in watchdog routines */
+#define  CHECK_BINDING
+
+#define  DEBUG_QLA2100                 0  /* For Debug of qla2x00 */
+#define  DEBUG_GET_FW_DUMP             0  /* also set DEBUG_QLA2100 and 
+                                             use COM1 and capture it */
+#define  USE_TP_FW                     1  /* use tp or ef firmware */
+
+/* The following WORD_FW_LOAD is defined in Makefile for ia-64 builds
+   and can also be decommented here for Word by Word confirmation of
+   RISC code download operation */
+/* #define  WORD_FW_LOAD               0  */
+
+/*
+* String arrays
+*/
+#define LINESIZE    256
+#define MAXARGS      26
+ 
+/*
+* Include files
+*/
+#include <linux/config.h>
+#ifdef MODULE
+#include <linux/module.h>
+#endif
+
+#ifndef LINUX_VERSION_CODE
+#include <linux/version.h>
+#endif  /* LINUX_VERSION_CODE not defined */
+
+static int num_hosts;           /* ioctl related  */
+static int apiHBAInstance = 0;  /* ioctl related keeps track of API HBA Instance */
+
+
+#include <stdarg.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/segment.h>
+#include <asm/byteorder.h>
+#include <asm/pgtable.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/blk.h>
+#include <linux/tqueue.h>
+#include <linux/interrupt.h>
+
+
+#ifndef KERNEL_VERSION
+#  define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+#define  APIDEV        1
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+#include <linux/tasks.h>
+# include <linux/bios32.h>
+#else
+/*#include <asm/spinlock.h>*/
+
+#define __KERNEL_SYSCALLS__
+
+#include <linux/unistd.h>
+#include <linux/smp_lock.h>
+
+#include <asm/system.h>
+#define SHUTDOWN_SIGS	(sigmask(SIGKILL)|sigmask(SIGINT)|sigmask(SIGTERM))
+#endif
+#include "sd.h"
+#include "scsi.h"
+#include "hosts.h"
+
+#ifdef FC_IP_SUPPORT
+#include <linux/skbuff.h>
+#include "qlcommon.h"
+#endif
+
+#include "qla2x00.h"
+#define UNIQUE_FW_NAME                 /* unique F/W array names */
+#ifdef UNIQUE_FW_NAME
+#include "ql2100_fw.h"                     /* ISP RISC code */
+#ifdef FC_IP_SUPPORT
+#include "ql2200ip_fw.h"                   /* ISP RISC 2200 code */
+#include "ql2300ip_fw.h"                   /* ISP RISC 2300 code */
+#else
+#include "ql2200_fw.h"                     /* ISP RISC 2200 code */
+#include "ql2300_fw.h"                     /* ISP RISC 2300 code */
+#endif
+#else
+#include "isp_fw.h"                     /* ISP RISC code */
+#include "isp1_fw.h"                     /* ISP RISC 2200 code */
+#endif
+#include <linux/stat.h>
+#include <linux/malloc.h>       
+
+
+#define  BZERO(ptr, amt)	memset((void *)(ptr), 0, amt)
+#define  BCMP(s1, s2, amt)	memcmp((void *)(s1), (void *)(s2), amt)
+#define  BCOPY(src, dst, amt)	memcpy((void *)(dst), (void *)(src), amt)
+#define  KMALLOC(siz)		kmalloc((siz), GFP_ATOMIC | GFP_DMA)
+#define  KMFREE(ip,siz)		kfree((ip))
+#define  SYS_DELAY(x)		udelay(x);barrier()
+#define  QLA2100_DELAY(sec)	mdelay(sec * HZ)
+
+/* 4.10 */
+#if  BITS_PER_LONG > 32
+#define pci_dma_lo32(a) (a & 0xffffffff)
+#define pci_dma_hi32(a) ((a >> 32) & 0xffffffff)
+#else
+#define pci_dma_lo32(a) (a & 0xffffffff)
+#define pci_dma_hi32(a) 0
+#endif
+
+#define  VIRT_TO_BUS(a) virt_to_bus((a))
+
+#if  BITS_PER_LONG <= 32
+#define  VIRT_TO_BUS_LOW(a) (uint32_t)virt_to_bus(((void *)a))
+#define  VIRT_TO_BUS_HIGH(a) (uint32_t)(0x0)
+#else
+#define  VIRT_TO_BUS_LOW(a) (uint32_t)(0xffffffff & virt_to_bus((void *)(a)))
+#define  VIRT_TO_BUS_HIGH(a) (uint32_t)(0xffffffff & (virt_to_bus((void *)(a))>>32))
+#endif
+
+#define  CACHE_FLUSH(a) (RD_REG_WORD(a))
+#define  INVALID_HANDLE    (MAX_OUTSTANDING_COMMANDS+1)
+
+#define  STATIC
+
+#if  BITS_PER_LONG <= 32
+#define  LS_64BITS(x) (uint32_t)((unsigned long)x)
+#define  MS_64BITS(x) (uint32_t)((unsigned long) 0x0)
+#else
+#define  LS_64BITS(x) (uint32_t)(0xffffffff & ((unsigned long)x))
+#define  MS_64BITS(x) (uint32_t)(0xffffffff & (((unsigned long)x)>>32) )
+#endif
+
+#if  BITS_PER_LONG <= 32
+#define  MSB(x)          (uint8_t)(((uint16_t)(x) >> 8) & 0xff)
+#define  LSB(x)          (uint8_t)(x & 0xff)
+#define  MSW(x)          (uint16_t)(((uint32_t)(x) >> 16) & 0xffff)
+#define  LSW(x)          (uint16_t)(x & 0xffff)
+#define  QL21_64BITS_3RDWD(x)   ((uint16_t) 0)
+#define  QL21_64BITS_4THWD(x)   ((uint16_t) 0)
+#else
+#define  MSB(x)          (uint8_t)(((uint16_t)(x) >> 8) & 0xff)
+#define  LSB(x)          (uint8_t)(x & 0xff)
+#define  MSW(x)          (uint16_t)(((uint32_t)(x) >> 16) & 0xffff)
+#define  LSW(x)          (uint16_t)(x & 0xffff)
+#define  QL21_64BITS_3RDWD(x)   ((uint16_t) (x >> 32) & 0xffff)
+#define  QL21_64BITS_4THWD(x)   ((uint16_t) (x >> 48) & 0xffff)
+#endif
+
+#define  OFFSET(w)   (((u_long) &w) & 0xFFFF)  /* 256 byte offsets */
+#define  SCSI_BUS_32(scp)   ((scp)->channel)
+#define  SCSI_TCN_32(scp)    ((scp)->target)
+#define  SCSI_LUN_32(scp)    ((scp)->lun)
+
+/*
+* TIMER MACROS
+*/
+#define  QLA2100_TIMER_LOCK(ap)   spin_lock_irqsave(&(ap)->retry_lock, cpu_flags);
+#define  QLA2100_TIMER_UNLOCK(ap) spin_unlock_irqrestore(&(ap)->retry_lock, cpu_flags);
+
+
+#define	WATCH_INTERVAL		1       /* number of seconds */
+#define	START_TIMER(f, h, w)	\
+{ \
+init_timer(&(h)->timer); \
+(h)->timer.expires = jiffies + w * HZ;\
+(h)->timer.data = (unsigned long) h; \
+(h)->timer.function = (void (*)(unsigned long))f; \
+(h)->flags.start_timer = FALSE; \
+add_timer(&(h)->timer); \
+(h)->timer_active = 1;\
+}
+
+#define	RESTART_TIMER(f, h, w)	\
+{ \
+(h)->timer.expires = jiffies + w * HZ;\
+(h)->flags.start_timer = FALSE; \
+add_timer(&(h)->timer); \
+}
+
+#define	STOP_TIMER(f, h)	\
+{ \
+del_timer(&(h)->timer); \
+(h)->timer_active = 0;\
+}
+
+#define NVRAM_DELAY() udelay(500) /* 2 microsecond delay */
+
+typedef unsigned long paddr32_t;
+
+/*
+*  Qlogic Driver support Function Prototypes.
+*/
+STATIC uint8_t  qla2100_register_with_Linux(scsi_qla_host_t *ha, uint8_t maxchannels);
+STATIC void   qla2100_done(scsi_qla_host_t *, srb_t **, srb_t **),
+qla2100_next(scsi_qla_host_t *, scsi_lu_t *),
+qla2100_select_queue_depth(struct Scsi_Host *, Scsi_Device *);
+
+STATIC void      qla2100_done_q_put(scsi_qla_host_t *, srb_t *, srb_t **, srb_t **),
+qla2100_putq_b(scsi_lu_t *, srb_t *),
+qla2100_putq_t(scsi_lu_t *, srb_t *),
+qla2100_removeq(scsi_lu_t *, srb_t *),
+qla2100_timer(scsi_qla_host_t *),
+qla2100_timeout_insert(scsi_qla_host_t *, srb_t *),
+qla2100_timeout_remove(scsi_qla_host_t *, srb_t *);
+
+STATIC uint8_t   qla2100_mem_alloc(scsi_qla_host_t *);
+
+static void qla2100_dump_regs(struct Scsi_Host *host);
+#if  STOP_ON_ERROR
+static void qla2100_panic(char *, struct Scsi_Host *host);
+#endif
+void qla2100_print_scsi_cmd(Scsi_Cmnd *cmd);
+STATIC void qla2100_abort_queue_single(scsi_qla_host_t *,uint32_t,uint32_t,uint32_t,uint32_t);
+
+STATIC int qla2100_return_status(scsi_qla_host_t *ha, sts_entry_t *sts, Scsi_Cmnd       *cp);
+STATIC void qla2100_removeq(scsi_lu_t *q, srb_t *sp);
+STATIC void qla2100_mem_free(scsi_qla_host_t *ha);
+void qla2100_do_dpc(void *p);
+
+static inline void qla2100_callback(scsi_qla_host_t *ha, srb_t *sp, uint8_t dec),
+qla2100_tgt_dealloc(scsi_qla_host_t *, tgt_t *),
+qla2100_lun_dealloc(scsi_lu_t *);
+static inline tgt_t     *qla2100_tgt_alloc(scsi_qla_host_t *);
+static inline scsi_lu_t *qla2100_lun_alloc(void);
+
+static inline void qla2100_enable_intrs(scsi_qla_host_t *);
+static inline void qla2100_disable_intrs(scsi_qla_host_t *);
+#if QLA2100_EXT_TIMEOUT
+static void qla2100_extend_timeout(Scsi_Cmnd *cmd, int timeout);
+#endif
+static int  qla2100_get_tokens(char *line, char **argv, int maxargs );
+
+/*
+*  QLogic ISP2100 Hardware Support Function Prototypes.
+*/
+STATIC  uint8_t  qla2100_initialize_adapter(scsi_qla_host_t *),
+qla2100_isp_firmware(scsi_qla_host_t *),
+qla2100_pci_config(scsi_qla_host_t *),
+qla2100_set_cache_line(scsi_qla_host_t *),
+qla2100_chip_diag(scsi_qla_host_t *),
+qla2100_setup_chip(scsi_qla_host_t *),
+qla2100_init_rings(scsi_qla_host_t *),
+qla2100_fw_ready(scsi_qla_host_t *),
+qla2100_nvram_config(scsi_qla_host_t *),
+qla2200_nvram_config(scsi_qla_host_t *),
+qla2100_mailbox_command(scsi_qla_host_t *, uint32_t, uint16_t *),
+qla2100_update_device_data(scsi_qla_host_t *, device_data_t *, u_char),
+qla2100_sns_device(scsi_qla_host_t *, u_char),
+qla2100_update_fc_db(scsi_qla_host_t *, u_char),
+qla2100_map_targets(scsi_qla_host_t *),
+#if USE_FLASH
+qla2100_get_database(scsi_qla_host_t *),
+qla2100_save_database(scsi_qla_host_t *),
+qla2100_program_flash_address(scsi_qla_host_t *, uint32_t, u_char),
+qla2100_erase_flash_sector(scsi_qla_host_t *, uint32_t),
+qla2100_poll_flash(scsi_qla_host_t *, uint32_t, u_char),
+#endif
+qla2100_loop_reset(scsi_qla_host_t *),
+qla2100_device_reset(scsi_qla_host_t *, uint32_t, uint32_t),
+qla2100_abort_device(scsi_qla_host_t *, uint32_t, uint32_t, uint32_t),
+qla2100_abort_command(scsi_qla_host_t *, srb_t *),
+qla2100_64bit_start_scsi(scsi_qla_host_t *, srb_t *),
+qla2100_32bit_start_scsi(scsi_qla_host_t *, srb_t *),
+qla2100_abort_isp(scsi_qla_host_t *),
+qla2100_loop_resync(scsi_qla_host_t *);
+STATIC uint8_t qla2100_cmd_wait(scsi_qla_host_t *ha);
+
+STATIC void      qla2100_nv_write(scsi_qla_host_t *, uint16_t),
+qla2100_nv_delay(void),
+qla2100_poll(scsi_qla_host_t *),
+qla2100_init_fc_db(scsi_qla_host_t *),
+qla2100_init_tgt_map(scsi_qla_host_t *),
+#if USE_FLASH
+qla2100_flash_enable(scsi_qla_host_t *),
+qla2100_flash_disable(scsi_qla_host_t *),
+qla2100_write_flash_byte(scsi_qla_host_t *, uint32_t, u_char),
+#endif
+qla2100_reset_adapter(scsi_qla_host_t *),
+qla2100_marker(scsi_qla_host_t *, uint32_t, uint32_t, uint32_t,
+u_char),
+qla2100_enable_lun(scsi_qla_host_t *),
+qla2100_notify_ack(scsi_qla_host_t *, notify_entry_t *),
+qla2100_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *,
+                                           uint32_t, u_long *),
+qla2100_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *,
+                                           uint32_t, u_long *),
+qla2100_isp_cmd(scsi_qla_host_t *),
+qla2100_isr(scsi_qla_host_t *, srb_t **, srb_t **),
+qla2100_rst_aen(scsi_qla_host_t *),
+qla2100_atio_entry(scsi_qla_host_t *, atio_entry_t *),
+qla2100_status_entry(scsi_qla_host_t *, sts_entry_t *, srb_t **,
+srb_t **),
+qla2100_error_entry(scsi_qla_host_t *, response_t *, srb_t **,
+srb_t **),
+qla2100_restart_queues(scsi_qla_host_t *, uint8_t),
+qla2100_restart_watchdog_queue(scsi_qla_host_t *),
+qla2100_abort_queues(scsi_qla_host_t *, uint8_t);
+
+STATIC uint16_t  qla2100_get_nvram_word(scsi_qla_host_t *, uint32_t),
+qla2100_nvram_request(scsi_qla_host_t *, uint32_t),
+qla2100_read_flash_byte(scsi_qla_host_t *, uint32_t),
+qla2100_debounce_register(volatile uint16_t *);
+
+STATIC request_t *qla2100_req_pkt(scsi_qla_host_t *);
+STATIC request_t *qla2100_ms_req_pkt(scsi_qla_host_t *, srb_t *);
+uint8_t          qla2100_update_config(scsi_qla_host_t *ha);
+STATIC uint8_t qla2100_configure_hba(scsi_qla_host_t *ha);
+STATIC uint8_t qla2100_configure_loop(scsi_qla_host_t *ha, uint8_t );
+STATIC void qla2100_reset_chip(scsi_qla_host_t *ha);
+#if QL2100_TARGET_MODE_SUPPORT
+qla2100_enable_lun(scsi_qla_host_t *, uint8_t, uint32_t),
+qla2100_notify_ack(scsi_qla_host_t *, notify_entry_t *),
+qla2100_immed_notify(scsi_qla_host_t *, notify_entry_t *),
+qla2100_accept_io(scsi_qla_host_t *, ctio_ret_entry_t *),
+qla2100_64bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t,
+                                     u_long *),
+qla2100_32bit_continue_io(scsi_qla_host_t *, atio_entry_t *, uint32_t,
+                                     u_long *),
+qla2100_atio_entry(scsi_qla_host_t *, atio_entry_t *),
+qla2100_notify_entry(scsi_qla_host_t *, notify_entry_t *),
+
+#endif  /* QLA2100_TARGET_MODE_SUPPORT */
+STATIC uint8_t qla2100_sns_get_name( scsi_qla_host_t *ha, device_data_t *device, uint8_t flag );
+STATIC void qla2100_display_fc_names(scsi_qla_host_t *ha);
+void ql2100_dump_requests(scsi_qla_host_t *ha);
+static void qla2100_get_properties(scsi_qla_host_t *ha, char *string);
+STATIC uint8_t qla2100_find_propname(scsi_qla_host_t *ha, char *propname, char *propstr, char *db);
+static int qla2100_get_prop_16chars(scsi_qla_host_t *ha, char *propname, char *propval, char *cmdline);
+static char	*qla2100_get_line(char *str, char *line);
+void qla2100_check_fabric_devices(scsi_qla_host_t *ha);
+
+#ifdef FC_IP_SUPPORT
+
+/* Entry points for IP network driver */
+int  qla2x00_ip_inquiry(uint16_t wAdapterNumber, BD_INQUIRY_DATA *pInquiryData);
+int  qla2x00_ip_enable(scsi_qla_host_t *ha, BD_ENABLE_DATA *pEnableData);
+void qla2x00_ip_disable(scsi_qla_host_t *ha);
+void qla2x00_add_buffers(scsi_qla_host_t *ha, uint16_t wBufferCount);
+int  qla2x00_send_packet(scsi_qla_host_t *ha, SEND_CB *pSendCB);
+
+static int qla2x00_ip_initialize(scsi_qla_host_t *ha);
+static int qla2x00_add_new_ip_device(scsi_qla_host_t *ha,
+uint16_t wLoopId,
+uint8_t *pPortId,
+uint8_t *pPortName,
+int bForceAdd);
+static int qla2x00_convert_to_arp(scsi_qla_host_t *ha, SEND_CB *pSendCB);
+static void qla2x00_free_ip_block(scsi_qla_host_t *ha,
+IP_DEVICE_BLOCK *pIpDevice);
+static int qla2x00_get_ip_loopid(scsi_qla_host_t *ha,
+uint8_t *pNodeName,
+uint8_t *pLoopId);
+static int qla2x00_send_farp_request(scsi_qla_host_t *ha,
+uint8_t *pPortName);
+static int qla2x00_register_ip_device(scsi_qla_host_t *ha);
+static int qla2x00_reserve_ip_block(scsi_qla_host_t *ha,
+PIP_DEVICE_BLOCK *pIpDevBlk);
+static int qla2x00_update_ip_device_data(scsi_qla_host_t *ha,
+device_data_t *pDeviceData);
+static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId);
+static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId);
+static int qla2x00_login_public_device(scsi_qla_host_t *ha,
+uint16_t *pLoopId,
+uint8_t  *pPortID,
+uint16_t wOptions);
+static int qla2x00_logout_public_device(scsi_qla_host_t *ha,
+uint16_t wLoopId,
+uint16_t wOptions);
+#else
+/* v2.19.8 */
+static int qla2x00_login_public_device(scsi_qla_host_t *ha,
+uint16_t *pLoopId,
+uint8_t  *pPortID,
+uint16_t wOptions);
+static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId);
+static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId);
+#endif
+
+#if  APIDEV
+static int apidev_init(struct Scsi_Host*);
+static int apidev_cleanup(void);
+#endif
+
+void qla2100_print_q_info(scsi_lu_t *q);
+
+#if  DEBUG_QLA2100
+#ifndef QL_DEBUG_ROUTINES
+#define QL_DEBUG_ROUTINES
+#endif
+#endif
+#ifdef QL_DEBUG_ROUTINES
+/*
+*  Driver Debug Function Prototypes.
+*/
+STATIC uint8_t  qla2100_getbyte(uint8_t *);
+STATIC uint16_t qla2100_getword(uint16_t *);
+STATIC uint32_t qla2100_getdword(uint32_t *);
+STATIC void     qla2100_putbyte(uint8_t *, uint8_t),
+qla2100_putword(uint16_t *, uint16_t),
+qla2100_putdword(uint32_t *, uint32_t),
+qla2100_print(int8_t *),
+qla2100_output_number(u_long, uint8_t),
+qla2100_putc(int8_t);
+#endif
+#if DEBUG_GET_FW_DUMP
+STATIC void qla2300_dump_isp(scsi_qla_host_t *ha),
+qla2100_dump_word(uint8_t *, uint32_t, uint32_t);
+#endif
+
+/* Debug print buffer */
+char          debug_buff[LINESIZE];
+#if DEBUG_QLA2100
+STATIC uint8_t ql2x_debug_print = 1;
+#else
+STATIC uint8_t ql2x_debug_print = 0;
+#endif
+
+/*
+* insmod needs to find the variable and make it point to something
+*/
+static char *ql2xdevconf = NULL;
+static int ql2xretrycount = 8;
+#ifdef MODULE
+static char *ql2xopts = NULL;
+static int ql2xmaxqdepth = 0;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,18)
+
+/* insmod qla2100 ql2xopts=verbose" */
+MODULE_PARM(ql2xopts, "s");
+MODULE_PARM(ql2xmaxqdepth, "i");
+#endif
+/*
+* Just in case someone uses commas to separate items on the insmod
+* command line, we define a dummy buffer here to avoid having insmod
+* write wild stuff into our code segment
+*/
+static char dummy_buffer[60] = "Please don't add commas in your insmod command!!\n";
+
+#endif
+
+/*
+* Macros to change names of OS remapping routines.
+*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)
+#define ioremap vremap
+#define iounmap vfree
+#endif
+
+
+/*
+* This is the pointer to the /proc/scsi/qla2100 code.
+* access the driver.
+*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+#if CONFIG_PROC_FS
+/* this definition is normally in proc_fs.h     PROC_SCSI_QL2100 */
+#define PROC_SCSI_QL2100  PROC_SCSI_QLOGICISP
+
+struct proc_dir_entry proc_scsi_qla2100 = {
+PROC_SCSI_QL2100, 7, "qla2x00",
+S_IFDIR | S_IRUGO | S_IXUGO, 2,
+0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+};
+#endif
+#endif
+static int qla2100_lip = 0;
+
+#include <linux/ioctl.h>
+#include <scsi/scsi_ioctl.h>
+
+/* multi-OS QLOGIC IOCTL definition file */
+#include "qla2x00exioct.h"
+
+
+#if QLA_SCSI_VENDOR_DIR
+/* Include routine to set direction for vendor specific commands */
+#include "qlavendor.c"
+#endif 
+/***********************************************************************
+* We use the Scsi_Pointer structure that's included with each command
+* SCSI_Cmnd as a scratchpad for our SRB. This allows us to accept
+* an unlimited number of commands.
+*
+* SCp will always point to the SRB structure (defined in qla2100.h).
+* It is defined as follows:
+*  - SCp.ptr  -- > pointer back to the cmd
+*  - SCp.this_residual --> used as forward pointer to next srb
+*  - SCp.buffer --> used as backward pointer to next srb
+*  - SCp.buffers_residual --> used as flags field
+*  - SCp.have_data_in --> not used
+*  - SCp.sent_command --> not used
+*  - SCp.phase --> not used
+***********************************************************************/
+#define	CMD_SP(Cmnd)		(&(Cmnd)->SCp)
+#define	CMD_XFRLEN(Cmnd)	(Cmnd)->request_bufflen
+#define	CMD_CDBLEN(Cmnd)	(Cmnd)->cmd_len
+#define	CMD_CDBP(Cmnd)		(Cmnd)->cmnd
+#define	CMD_SNSP(Cmnd)		(Cmnd)->sense_buffer
+#define	CMD_SNSLEN(Cmnd)	(sizeof (Cmnd)->sense_buffer)
+#define	CMD_RESULT(Cmnd)	((Cmnd)->result)
+#define	CMD_HANDLE(Cmnd)	((Cmnd)->host_scribble)
+#define	CMD_TIMEOUT(Cmnd)	((Cmnd)->timeout_per_command)
+
+#define DID_RETRY		DID_ERROR
+
+
+/*
+* Macros use for debugging the driver.
+*/
+#ifdef QL_DEBUG_LEVEL_3
+#define ENTER(x)	sprintf(debug_buff,"qla2100 : Entering %s()\n\r", x); \
+qla2100_print(debug_buff);
+#define LEAVE(x)	sprintf(debug_buff,"qla2100 : Leaving %s()\n\r", x); \
+qla2100_print(debug_buff);
+#define ENTER_INTR(x)	sprintf(debug_buff,"qla2100 : Entering %s()\n\r", x); \
+qla2100_print(debug_buff);
+#define LEAVE_INTR(x)	sprintf(debug_buff,"qla2100 : Leaving %s()\n\r", x); \
+qla2100_print(debug_buff);
+#define DEBUG3(x)	x
+#else
+#define ENTER(x)
+#define LEAVE(x)
+#define ENTER_INTR(x)
+#define LEAVE_INTR(x)
+#define DEBUG3(x)
+#endif
+
+#if  QLA2100_COMTRACE
+#define COMTRACE(x)     qla2100_putc(x);
+#else
+#define COMTRACE(x)
+#endif
+
+#if  DEBUG_QLA2100
+#define DEBUG(x)	x
+#define DEBUG4(x)
+#else
+#define DEBUG(x)
+#define DEBUG4(x)
+#endif
+
+#ifdef QL_DEBUG_LEVEL_2
+#define DEBUG2(x)          x
+#else
+#define DEBUG2(x)
+#endif
+#ifdef QL_DEBUG_LEVEL_5
+#define DEBUG5(x)          x
+#else
+#define DEBUG5(x)
+#endif
+
+uint8_t copyright[48] = "Copyright 1999-2001, Qlogic Corporation";
+
+/****************************************************************************/
+/*  LINUX -  Loadable Module Functions.                                     */
+/****************************************************************************/
+
+/*****************************************/
+/*   ISP Boards supported by this driver */
+/*****************************************/
+#define QLA2100_VENDOR_ID   0x1077
+#define QLA2100_DEVICE_ID   0x2100
+#define QLA2200_DEVICE_ID   0x2200
+#define QLA2200A_DEVICE_ID  0x2200A
+#define QLA2300_DEVICE_ID   0x2300
+#define QLA2200A_RISC_ROM_VER  4
+
+#define NUM_OF_ISP_DEVICES     4
+
+typedef struct _qlaboards
+{
+unsigned char   bdName[9];       /* Board ID String             */
+unsigned long   device_id;       /* Device ID                   */
+int   numPorts;                  /* number of loops on adapter  */
+unsigned short   *fwcode;        /* pointer to FW array         */
+unsigned long    *fwlen;         /* number of words in array    */
+unsigned short   *fwstart;       /* start address for F/W       */
+unsigned char   *fwver;          /* Ptr to F/W version array    */
+} qla_boards_t;
+
+
+#if USE_TP_FW
+struct _qlaboards   QLBoardTbl_fc[NUM_OF_ISP_DEVICES] =
+{
+/* Name ,  Board PCI Device ID,         Number of ports */
+{"QLA2300 ", QLA2300_DEVICE_ID,           MAX_BUSES,
+#ifdef FC_IP_SUPPORT
+&fw2300ip_code01[0],  (unsigned long *)&fw2300ip_length01, &fw2300ip_addr01, &fw2300ip_version_str[0] },
+#else
+&fw2300tp_code01[0],  (unsigned long *)&fw2300tp_length01, &fw2300tp_addr01, &fw2300tp_version_str[0] },
+#endif
+{"QLA2200 ", QLA2200_DEVICE_ID,           MAX_BUSES,
+#ifdef FC_IP_SUPPORT
+&fw2200ip_code01[0],  (unsigned long *)&fw2200ip_length01, &fw2200ip_addr01, &fw2200ip_version_str[0] },
+#else
+&fw2200tp_code01[0],  (unsigned long *)&fw2200tp_length01, &fw2200tp_addr01, &fw2200tp_version_str[0] },
+#endif
+{"QLA2100 ", QLA2100_DEVICE_ID,           MAX_BUSES,
+&fw2100tp_code01[0],  (unsigned long *)&fw2100tp_length01,&fw2100tp_addr01, &fw2100tp_version_str[0] },
+{"        ",                 0,           0}
+};
+
+#else  /* USE_TP_FW */
+
+struct _qlaboards   QLBoardTbl_fc[NUM_OF_ISP_DEVICES] =
+{
+/* Name ,  Board PCI Device ID,         Number of ports */
+{"QLA2300 ", QLA2300_DEVICE_ID,           MAX_BUSES,
+#ifdef FC_IP_SUPPORT
+&fw2300ip_code01[0],  (unsigned long *)&fw2300ip_length01, &fw2300ip_addr01, &fw2300ip_version_str[0] },
+#else
+&fw2300ef_code01[0],  (unsigned long *)&fw2300ef_length01, &fw2300ef_addr01, &fw2300ef_version_str[0] },
+#endif
+{"QLA2200 ", QLA2200_DEVICE_ID,           MAX_BUSES,
+#ifdef FC_IP_SUPPORT
+&fw2200ip_code01[0],  (unsigned long *)&fw2200ip_length01, &fw2200ip_addr01, &fw2200ip_version_str[0] },
+#else
+&fw2200ef_code01[0],  (unsigned long *)&fw2200ef_length01, &fw2200ef_addr01, &fw2200ef_version_str[0] },
+#endif
+{"QLA2100 ", QLA2100_DEVICE_ID,           MAX_BUSES,
+&fw2100ef_code01[0],  (unsigned long *)&fw2100ef_length01,&fw2100ef_addr01, &fw2100ef_version_str[0] },
+{"        ",                 0,           0}
+};
+#endif /* USE_TP_FW  */
+
+/*
+* Stat info
+*/
+static struct _qla2100stats  {
+unsigned long   mboxtout;            /* mailbox timeouts */
+unsigned long   mboxerr;             /* mailbox errors */
+unsigned long   ispAbort;            /* ISP aborts */
+unsigned long   debugNo;
+unsigned long   loop_resync;
+unsigned long   outarray_full;
+unsigned long   retry_q_cnt;
+unsigned long   done_q_cnt;
+scsi_qla_host_t *irqhba;
+} qla2100_stats;
+
+/*
+* Command line options
+*/
+static unsigned long qla2100_verbose = 1L;
+static unsigned long qla2100_quiet   = 0L;
+static unsigned long qla2100_reinit = 1L;
+static unsigned long qla2100_req_dmp = 0L;
+static scsi_qla_host_t *qla2100_hostlist = NULL;
+
+#ifdef QLA2100_PROFILE
+static int qla2100_buffer_size = 0;
+static char *qla2100_buffer = NULL;
+#endif
+
+#include <linux/ioctl.h>
+#include <scsi/scsi_ioctl.h>
+#include <asm/uaccess.h>
+
+/*************************************************************************
+*   qla2100_set_info
+*
+* Description:
+*   Set parameters for the driver from the /proc filesystem.
+*
+* Returns:
+*************************************************************************/
+int
+qla2100_set_info(char *buffer, int length, struct Scsi_Host *HBAptr) {
+    return (-ENOSYS);  /* Currently this is a no-op */
+}
+
+
+#include "qla2x00ioctl.c"
+
+
+/*************************************************************************
+* qla2100_proc_info
+*
+* Description:
+*   Return information to handle /proc support for the driver.
+*
+* inout : decides on the direction of the dataflow and the meaning of the
+*         variables
+* buffer: If inout==FALSE data is being written to it else read from it
+*         (ptrs to a page buffer)
+* *start: If inout==FALSE start of the valid data in the buffer
+* offset: If inout==FALSE offset from the beginning of the imaginary file
+*         from which we start writing into the buffer
+* length: If inout==FALSE max number of bytes to be written into the buffer
+*         else number of bytes in the buffer
+* Returns:
+*************************************************************************/
+#define	PROC_BUF	(&qla2100_buffer[len])
+int
+qla2100_proc_info( char *buffer, char **start, off_t offset, int length,
+int hostno, int inout) {
+#if QLA2100_PROFILE
+    struct Scsi_Host *host;
+    scsi_qla_host_t *ha;
+    int    size = 0;
+    scsi_lu_t  *up;
+    int   len = 0;
+    qla_boards_t   *bdp;
+    uint32_t        t, l;
+
+#if REQ_TRACE
+    Scsi_Cmnd       *cp;
+    srb_t           *sp;
+    int i;
+#endif
+    
+    DEBUG5(printk("Entering proc_info 0x%x,0x%lx,0x%x,0x%x\n",(int)buffer,offset,length,hostno);)
+    host = NULL;
+
+    /* Find the host that was specified */
+    for( ha=qla2100_hostlist; (ha != NULL) && ha->host->host_no != hostno; ha=ha->next )
+        ;
+
+    /* if host wasn't found then exit */
+    if( !ha ) {
+        size = sprintf(buffer, "Can't find adapter for host number %d\n", hostno);
+        if( size > length ) {
+            return (size);
+        } else {
+            return (0);
+        }
+    }
+
+    host = ha->host;
+
+    if( inout == TRUE ) /* Has data been written to the file? */
+    {
+        printk(KERN_INFO "qla2100_proc: has data been written to the file. \n");
+        return (qla2100_set_info(buffer, length, host));
+    }
+
+
+    /*
+    * if our old buffer is the right size use it otherwise
+    * allocate a new one.
+    */
+    size = 4096;  /* get a page */
+    if( qla2100_buffer_size != size ) {
+        /* deallocate this buffer and get a new one */
+        if( qla2100_buffer != NULL ) {
+            kfree(qla2100_buffer);
+            qla2100_buffer_size = 0;
+        }
+        qla2100_buffer = kmalloc(size, GFP_KERNEL);
+    }
+    if( qla2100_buffer == NULL ) {
+        size = sprintf(buffer, "qla2100 - kmalloc error at line %d\n",
+        __LINE__);
+        return size;
+    }
+    /* save the size of our buffer */
+    qla2100_buffer_size = size;
+
+    /* start building the print buffer */
+    bdp = &QLBoardTbl_fc[ha->devnum];
+    qla2100_lip = 1;
+    size =  sprintf(PROC_BUF,
+    "QLogic PCI to Fibre Channel Host Adapter for ISP2100/ISP2200/ISP2300:\n"     /* 72 */
+    "        Firmware version: %2d.%02d.%02d, Driver version %s\n",                /* 66 */
+    bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA2100_VERSION);
+    len += size;
+
+#if 0
+    size = sprintf(PROC_BUF, 
+           "FC HBA: %s; HBA Serial# %x%x%x\n", 
+            bdp->bdName,
+            ha->serial0,
+            ha->serial1,
+            ha->serial2);
+    len += size;
+
+    size = sprintf(PROC_BUF, 
+           "[%c%c%c%c%c%c]; Part#%c%c%c%c%c%c%c%c; FRU#%c%c%c%c%c%c%c%c; EC#%c%c%c%c%c%c%c%c\n", 
+            ha->oem_string[0],
+            ha->oem_string[1],
+            ha->oem_string[2],
+            ha->oem_string[3],
+            ha->oem_string[4],
+            ha->oem_string[5],
+
+            ha->oem_part[0],
+            ha->oem_part[1],
+            ha->oem_part[2],
+            ha->oem_part[3],
+            ha->oem_part[4],
+            ha->oem_part[5],
+            ha->oem_part[6],
+            ha->oem_part[7],
+
+            ha->oem_fru[0],
+            ha->oem_fru[1],
+            ha->oem_fru[2],
+            ha->oem_fru[3],
+            ha->oem_fru[4],
+            ha->oem_fru[5],
+            ha->oem_fru[6],
+            ha->oem_fru[7],
+
+            ha->oem_ec[0],
+            ha->oem_ec[1],
+            ha->oem_ec[2],
+            ha->oem_ec[3],
+            ha->oem_ec[4],
+            ha->oem_ec[5],
+            ha->oem_ec[6],
+            ha->oem_ec[7]);
+    len += size;
+#endif
+
+    size = sprintf(PROC_BUF, "Request Queue = 0x%lx, Response Queue = 0x%lx\n",
+    (long unsigned int)ha->request_dma,
+    (long unsigned int)ha->response_dma);
+    len += size;
+    size = sprintf(PROC_BUF, "Request Queue count= %ld, Response Queue count= %ld\n",
+    (long)REQUEST_ENTRY_CNT,
+    (long)RESPONSE_ENTRY_CNT);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of pending commands = 0x%lx\n", ha->actthreads);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of queued commands = 0x%lx\n", ha->qthreads);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of free request entries = %d\n",ha->req_q_cnt);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of mailbox timeouts = %ld\n",qla2100_stats.mboxtout);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of ISP aborts = %ld\n",qla2100_stats.ispAbort);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of loop resyncs = %ld\n",qla2100_stats.ispAbort);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of retries for empty slots = %ld\n",qla2100_stats.outarray_full);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of reqs in retry_q = %ld\n",qla2100_stats.retry_q_cnt);
+    len += size;
+    size = sprintf(PROC_BUF, "Number of reqs in done_q = %ld\n",qla2100_stats.done_q_cnt);
+    len += size;
+
+#if REQ_TRACE
+    if ( qla2100_req_dmp ) {
+    	size  = sprintf(PROC_BUF,"Outstanding Commands on controller:\n");
+    	len += size;
+    	for( i=0; i < MAX_OUTSTANDING_COMMANDS; i++ ) {
+      	if( (sp = ha->outstanding_cmds[i]) == NULL )
+                 	continue;
+      	if( (cp = sp->cmd) == NULL )
+               continue;
+        size = sprintf(PROC_BUF,
+           "(%d): Pid=%ld, sp flags=0x%x, cmd=0x%p, state=%x handle=%x\n\r",
+           i, (int)sp->cmd->pid, (long)sp->flags,
+           CMD_SP(sp->cmd),(int)sp->state,CMD_HANDLE(sp->cmd));
+
+      	len += size;
+        if( len >= qla2100_buffer_size )
+                goto profile_stop;
+    	}
+    }
+#endif
+
+    /* 2.25 node/port display to proc */
+    /* Display the node name for adapter */
+    size = sprintf(PROC_BUF, "\nSCSI Device Information:\n");
+    len += size;
+    size = sprintf(PROC_BUF,
+           "scsi-qla%d-adapter-node=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+           (int)ha->instance,
+           ha->init_cb->node_name[0],
+           ha->init_cb->node_name[1],
+           ha->init_cb->node_name[2],
+           ha->init_cb->node_name[3],
+           ha->init_cb->node_name[4],
+           ha->init_cb->node_name[5],
+           ha->init_cb->node_name[6],
+           ha->init_cb->node_name[7]);
+    len += size;
+
+    /* display the port name for adapter */
+    size = sprintf(PROC_BUF,
+           "scsi-qla%d-adapter-port=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+           (int)ha->instance,
+           ha->init_cb->port_name[0],
+           ha->init_cb->port_name[1],
+           ha->init_cb->port_name[2],
+           ha->init_cb->port_name[3],
+           ha->init_cb->port_name[4],
+           ha->init_cb->port_name[5],
+           ha->init_cb->port_name[6],
+           ha->init_cb->port_name[7]);
+    len += size;
+
+    /* Print out device port names */
+    for (i = 0; i < MAX_FIBRE_DEVICES; i++) {
+         if (ha->fc_db[i].loop_id == PORT_UNUSED)
+                        continue;
+
+#if USE_PORTNAME
+		size = sprintf(PROC_BUF,
+		    	"scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+		    	(int)ha->instance, i,
+		    	ha->fc_db[i].wwn[0],
+		    	ha->fc_db[i].wwn[1],
+		    	ha->fc_db[i].wwn[2],
+		    	ha->fc_db[i].wwn[3],
+		    	ha->fc_db[i].wwn[4],
+		    	ha->fc_db[i].wwn[5],
+		    	ha->fc_db[i].wwn[6],
+		    	ha->fc_db[i].wwn[7]);
+#else
+         size = sprintf(PROC_BUF,
+                    "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+                    (int)ha->instance, i,
+                    ha->fc_db[i].name[0],
+                    ha->fc_db[i].name[1],
+                    ha->fc_db[i].name[2],
+                    ha->fc_db[i].name[3],
+                    ha->fc_db[i].name[4],
+                    ha->fc_db[i].name[5],
+                    ha->fc_db[i].name[6],
+                    ha->fc_db[i].name[7]);
+#endif
+         len += size;
+    } /* 2.25 node/port display to proc */
+
+    size = sprintf(PROC_BUF, "\nSCSI LUN Information:\n");
+    len += size;
+    size = sprintf(PROC_BUF, "(Id:Lun)\n");
+    len += size;
+    /* scan for all equipment stats */
+    for (t = 0; t < MAX_FIBRE_DEVICES; t++) {
+        /* valid target */
+        if (ha->fc_db[t].loop_id == PORT_UNUSED)
+            continue;
+        /* scan all luns */
+        for( l = 0; l < ha->max_luns; l++ ) {
+            up = (scsi_lu_t *) GET_LU_Q(ha, 0, t, l);
+            if( up == NULL )
+                continue;
+            if( up->io_cnt == 0 || up->io_cnt < 5)
+                continue;
+            /* total reads since boot */
+            /* total writes since boot */
+            /* total requests since boot  */
+            size = sprintf(PROC_BUF, "(%2d:%2d): Total reqs %ld,",t,l,up->io_cnt);
+            len += size;
+            /* current number of pending requests */
+            size = sprintf(PROC_BUF, " Pending reqs %d,",up->q_outcnt);
+            len += size;
+
+            /* current number of pending requests */
+            size = sprintf(PROC_BUF, " Queued reqs %d,",(int)up->q_incnt);
+            len += size;
+            size = sprintf(PROC_BUF, "\n");
+            len += size;
+            if( len >= qla2100_buffer_size )
+                goto profile_stop;
+        }
+        if( len >= qla2100_buffer_size )
+            break;
+    }
+
+    profile_stop:
+    if( len >= qla2100_buffer_size ) {
+        printk(KERN_WARNING "qla2100: Overflow buffer in qla2100_proc.c\n");
+    }
+
+    if( offset > len - 1 ) {
+        kfree(qla2100_buffer);
+        qla2100_buffer = NULL;
+        qla2100_buffer_size = length = 0;
+        *start = NULL;
+    } else {
+        if( len - offset < length ) {
+            length = len - offset;
+        }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        *start = &qla2100_buffer[offset];   /* Start of wanted data */
+#else
+		*start = buffer;
+		memcpy(buffer, &qla2100_buffer[offset], length);
+#endif
+    }
+    return (length);
+#else
+    return (0);
+#endif
+
+}
+
+/**************************************************************************
+* qla2100_detect
+*
+* Description:
+*    This routine will probe for Qlogic FC SCSI host adapters.
+*    It returns the number of host adapters of a particular
+*    type that were found.	 It also initialize all data necessary for
+*    the driver.  It is passed-in the host number, so that it
+*    knows where its first entry is in the scsi_hosts[] array.
+*
+* Input:
+*     template - pointer to SCSI template
+*
+* Returns:
+*  num - number of host adapters found.
+**************************************************************************/
+int
+qla2100_detect(Scsi_Host_Template *template)
+{
+	struct Scsi_Host *host;
+	scsi_qla_host_t *ha, *cur_ha;
+	struct _qlaboards  *bdp;
+	int i, j;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	unsigned short subsys;
+#endif
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,95)
+	unsigned int piobase;
+	unsigned char pci_bus, pci_devfn, pci_irq;
+	config_reg_t   *cfgp = 0;
+#endif
+	device_reg_t   *reg;
+	char   *cp;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+	struct pci_dev *pdev = NULL;
+#else
+	int index;
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	struct semaphore sem = MUTEX_LOCKED;
+#else
+	DECLARE_MUTEX_LOCKED(sem);
+#endif
+
+	unsigned long wait_switch = 0; 
+
+	ENTER("qla2100_detect");
+
+	if( sizeof(srb_t) > sizeof(Scsi_Pointer) ) 
+		printk(KERN_WARNING "qla2x00: srb_t must be re-defined "
+		    "- it's too big");
+
+#ifdef CODECHECK
+ 	if( sizeof(srb_t) > sizeof(Scsi_Pointer) ) {
+		printk(KERN_WARNING "Redefine srb_t - its too big");
+		return 0;
+	}
+#endif
+
+#ifdef MODULE
+	DEBUG2(sprintf(debug_buff,
+	    "DEBUG: qla2100_detect starts at address = 0x%8lx\n",
+	    (uint32_t)qla2100_detect);)
+	DEBUG2(qla2100_print(debug_buff);)
+	/*
+	* If we are called as a module, the qla2100 pointer may not be null
+	* and it would point to our bootup string, just like on the lilo
+	* command line.  IF not NULL, then process this config string with
+	* qla2100_setup
+	*
+	* Boot time Options
+	* To add options at boot time add a line to your lilo.conf file like:
+	* append="qla2100=verbose,tag_info:{{32,32,32,32},{32,32,32,32}}"
+	* which will result in the first four devices on the first two
+	* controllers being set to a tagged queue depth of 32.
+	*/
+	if( ql2xopts )
+		qla2100_setup(ql2xopts, NULL);
+	if( dummy_buffer[0] != 'P' )
+		printk(KERN_WARNING "qla2100: Please read the file "
+		    "/usr/src/linux/drivers/scsi/README.qla2100\n"
+		    "qla2100: to see the proper way to specify options to "
+		    "the qla2100 module\n"
+		    "qla2100: Specifically, don't use any commas when passing "
+		    "arguments to\n"
+		    "qla2100: insmod or else it might trash certain memory "
+		    "areas.\n");
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	if( (int) !pcibios_present() ) 
+#else 
+	if (!pci_present())
+#endif
+	{
+		printk(KERN_WARNING "scsi: [ERROR] PCI not present\n");
+		return 0;
+	} /* end of IF */
+
+	bdp = &QLBoardTbl_fc[0];
+	qla2100_hostlist = NULL;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	template->proc_dir = &proc_scsi_qla2100;
+#else
+	template->proc_name = "qla2x00";
+#endif
+
+	/* Try and find each different type of adapter we support */
+	for( i=0; bdp->device_id != 0 && i < NUM_OF_ISP_DEVICES; i++, bdp++ ) {
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+		/* PCI_SUBSYSTEM_IDS supported */ 
+		while ((pdev = pci_find_subsys(QLA2100_VENDOR_ID,
+		    bdp->device_id, PCI_ANY_ID, PCI_ANY_ID, pdev) )) {
+			if (pci_enable_device(pdev)) continue;
+#else
+		while ((pdev = pci_find_device(QLA2100_VENDOR_ID,
+		    bdp->device_id, pdev ) ))  {
+#endif /* 2,3,18 */
+
+#else  /* less than 2,1,95 */  
+		while (!(pcibios_find_device(QLA2100_VENDOR_ID,
+		    bdp->device_id, index++, &pci_bus, &pci_devfn)) )  {
+#endif /* 2,1,95 */ 
+
+			/* found an adapter */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+			printk(KERN_INFO "qla2x00: detect() found an HBA\n");
+			printk(KERN_INFO
+			    "qla2x00: VID=%x DID=%x SSVID=%x SSDID=%x\n",
+			    pdev->vendor, pdev->device,
+			    pdev->subsystem_vendor,
+			    pdev->subsystem_device); 
+
+			/* If it's an XXX SubSys Vendor ID adapter, skip it. */
+			/* if (pdev->subsystem_vendor == PCI_VENDOR_ID_XXX) 
+			{ 
+				printk(KERN_INFO "qla2x00: Skip XXX SubSys "
+				    "Vendor ID Controller\n");
+				continue;
+			}
+			*/
+#else
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+			pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
+			    &subsys);
+
+			/* Bypass all XXX SUBSYS VENDOR IDs */
+			/* if (subsys == PCI_VENDOR_ID_XXX) 
+			{ 
+				printk(KERN_INFO "qla2x00:Skip XXX SubSys "
+				    "Vendor ID Controller\n");
+				continue;
+			}
+			*/
+#endif /* 2,1,95 */
+#endif /* 2,3,18 */
+			host = scsi_register(template, sizeof(scsi_qla_host_t));
+			ha = (scsi_qla_host_t *) host->hostdata;
+
+			/* Clear our data area */
+			for( j = 0, cp = (char *)ha;
+			    j < sizeof(scsi_qla_host_t); j++, cp++ )
+				*cp = 0;
+
+			/* Sanitize the information from PCI BIOS.  */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+			host->irq = pdev->irq;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+			host->io_port = (unsigned long) pdev->base_address[0];
+#else
+			host->io_port = pdev->resource[0].start;
+#endif
+			ha->pci_bus = pdev->bus->number;
+			ha->pci_device_fn = pdev->devfn;
+			ha->pdev = pdev;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,4)
+			scsi_set_pci_device(host, pdev);
+#endif
+#else
+			pcibios_read_config_byte(pci_bus, pci_devfn,
+			    OFFSET(cfgp->interrupt_line), &pci_irq);
+			pcibios_read_config_dword(pci_bus, pci_devfn,
+			    OFFSET(cfgp->base_port), &piobase);
+			host->irq = pci_irq;
+			host->io_port = (unsigned int) piobase;
+			ha->pci_bus = pci_bus;
+			ha->pci_device_fn = pci_devfn;
+#endif
+			ha->device_id = bdp->device_id;
+			host->io_port &= PCI_BASE_ADDRESS_IO_MASK;
+			ha->devnum = i;
+			if( qla2100_verbose ) {
+				printk(KERN_INFO "(scsi): Found a %s @ bus %d, "
+				    "device 0x%x, irq %d, iobase 0x%lx\n",
+				    bdp->bdName, ha->pci_bus,
+				    (ha->pci_device_fn & 0xf8) >> 3,
+				    host->irq, (unsigned long)host->io_port);
+			}
+
+			ha->iobase     = (device_reg_t *)     host->io_port;
+			ha->iobase2300 = (device2300_reg_t *) host->io_port;
+			ha->host = host;
+
+			/* 4.23 Initialize /proc/scsi/qla2x00 counters */
+			ha->actthreads = 0;
+			ha->qthreads   = 0;
+			ha->dump_done  = 0;
+			ha->isp_aborts = 0;
+			ha->lip_count = 0;
+
+			if( qla2100_mem_alloc(ha) ) {
+				printk(KERN_INFO "qla2100: Failed to allocate "
+				    "memory for adapter\n");
+			}
+			ha->prev_topology = 0;
+			ha->ports = bdp->numPorts;
+			ha->host_no = host->host_no;
+
+			/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+			ha->ioctl_mem      = (void *)KMALLOC(PAGE_SIZE);
+			ha->ioctl_mem_phys =  VIRT_TO_BUS(ha->ioctl_mem);
+#else
+			/* get consistent memory allocated for ioctl I/O
+			 * operations
+			 */
+			ha->ioctl_mem = pci_alloc_consistent(ha->pdev,
+			    PAGE_SIZE, &ha->ioctl_mem_phys);
+#endif
+
+			if (ha->ioctl_mem == NULL) {
+				printk(KERN_WARNING "qla2100: ERROR in ioctl "
+				    "physical memory allocation\n");
+				return(0);
+			}
+
+			if( ha->device_id == QLA2100_DEVICE_ID )
+				ha->max_targets = MAX_TARGETS_2100;
+			else
+				ha->max_targets = MAX_TARGETS_2200;
+	
+			/* load the F/W, read paramaters, and init the H/W */
+			ha->instance = num_hosts;
+
+			if( qla2100_initialize_adapter(ha) ) {
+				printk(KERN_WARNING
+				    "qla2100_detect: [ERROR] Failed to "
+				    "initialize adapter\n");
+
+				qla2100_mem_free(ha);
+				scsi_unregister(host);
+				continue;
+			}
+
+			ha->next = NULL;
+			/*  Mark preallocated Loop IDs in use. */
+			ha->fabricid[SNS_FL_PORT].in_use = TRUE;
+			ha->fabricid[FABRIC_CONTROLLER].in_use = TRUE;
+			ha->fabricid[SIMPLE_NAME_SERVER].in_use = TRUE;
+
+			/* Register our resources with Linux */
+			if( qla2100_register_with_Linux(ha, bdp->numPorts-1) ) {
+				printk(KERN_WARNING 
+				    "qla2100: [ERROR] Failed to register our "
+				    "resources\n");
+				qla2100_mem_free(ha);
+				scsi_unregister(host);
+				continue;
+			}
+
+			/* reg uses here in detect() are common: 
+			 * 2100/2200/2300
+			 */
+			reg = ha->iobase;
+
+			/* Disable ISP interrupts. */
+			qla2100_disable_intrs(ha);
+
+			/*
+			 * Startup the kernel thread for this host adapter
+			 */
+
+			ha->dpc_notify = &sem;
+			kernel_thread((int (*)(void *))qla2100_do_dpc,
+			(void *) ha, 0);
+
+			/*
+			 * Now wait for the kernel dpc thread to initialize 
+			 * and go to sleep.
+			 */
+			down(&sem);
+			ha->dpc_notify = NULL;
+
+			/*
+			 * These locks are used to prevent more than one 
+			 * CPU from modifying the queue at the same time. 
+			 * The higher level "io_request_lock" will reduce 
+			 * most contention for these locks.
+			 */
+			ha->retry_lock = SPIN_LOCK_UNLOCKED;
+
+			/* Insure mailbox registers are free. */
+			WRT_REG_WORD(&reg->semaphore, 0);
+			WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
+			WRT_REG_WORD(&reg->host_cmd, HC_CLR_HOST_INT);
+
+			/* Wait around max 5 secs for the devices to come 
+			 * on-line we don't want Linux scanning before we 
+			 * are ready.
+			 */
+			/* v2.19.5b6 */
+			for (wait_switch = jiffies+(ha->loop_reset_delay * HZ); 
+			    wait_switch > jiffies &&
+			    !(ha->device_flags & DFLG_FABRIC_DEVICES) ; ) {
+
+				qla2100_check_fabric_devices(ha);
+			}
+			/* just in case we turned it on */
+			ha->dpc_flags &= ~COMMAND_WAIT_NEEDED;
+
+			/* List the target we have found */
+			qla2100_display_fc_names(ha);
+
+			/* Enable chip interrupts. */
+			qla2100_enable_intrs(ha);
+
+			/* Insert new entry into the list of adapters */
+			ha->next = NULL;
+			if( qla2100_hostlist == NULL ) {
+				qla2100_hostlist = ha;
+			} else {
+				cur_ha = qla2100_hostlist;
+
+				while( cur_ha->next != NULL )
+					cur_ha = cur_ha->next;
+
+				cur_ha->next = ha;
+			}
+			num_hosts++;
+		}
+	} /* end of FOR */
+
+	LEAVE("qla2100_detect");
+	return num_hosts;
+}
+
+/**************************************************************************
+*   qla2100_register_with_Linux
+*
+* Description:
+*   Free the passed in Scsi_Host memory structures prior to unloading the
+*   module.
+*
+* Input:
+*     ha - pointer to host adapter structure
+*     maxchannels - MAX number of channels.
+*
+* Returns:
+*  0 - Sucessfully reserved resources.
+*  1 - Failed to reserved a resource.
+**************************************************************************/
+STATIC uint8_t  qla2100_register_with_Linux(scsi_qla_host_t *ha, uint8_t maxchannels) {
+
+        struct Scsi_Host *host = ha->host;
+        char drvname[9];
+
+        host->can_queue = 0xfffff;  /* unlimited  */
+        host->cmd_per_lun = 1;
+        host->select_queue_depths = qla2100_select_queue_depth;
+        host->n_io_port = 0xFF;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        host->base = (unsigned char *) ha->mmpbase;
+#else
+        host->base = (u_long) ha->mmpbase;
+#endif
+        host->max_channel = maxchannels;
+        /* fix: 07/31 host->max_lun = MAX_LUNS-1; */
+        host->max_lun = ha->max_luns;
+        host->unique_id = ha->instance;
+        host->max_id = ha->max_targets;
+
+        /* set our host ID  (need to do something about our two IDs) */
+        host->this_id = 255;
+
+        /* Register the I/O space with Linux */
+        if( check_region(host->io_port, 0xff) ) {
+            printk(KERN_WARNING "qla2100 : [ERROR] Failed to reserved i/o region "
+		"0x%04lx-0x%04lx already in use\n",
+            host->io_port, host->io_port + 0xff);
+            /* 4.31.5 - deleted free_irq(host->irq, NULL); */
+            return 1;
+        }
+
+        /* ER# 4368 */
+        sprintf(drvname,"qla2x00#%02d",host->unique_id);
+
+        request_region(host->io_port, 0xff, drvname);
+
+
+        /* Register the IRQ with Linux (sharable) */
+        if( request_irq(host->irq, qla2100_intr_handler, SA_INTERRUPT| SA_SHIRQ, "qla2x00", ha) ) {
+            printk(KERN_WARNING "qla2100 : [ERROR] Failed to reserved interrupt %d "
+		"already in use\n", host->irq);
+            return 1;
+        }
+
+        /* Initialized the timer */
+        START_TIMER(qla2100_timer,ha,WATCH_INTERVAL);
+
+        return 0;
+}
+
+
+/**************************************************************************
+*   qla2100_release
+*
+* Description:
+*   Free the passed in Scsi_Host memory structures prior to unloading the
+*   module.
+*
+* Input:
+*     ha - pointer to host adapter structure
+*
+* Returns:
+*  0 - Always returns good status
+**************************************************************************/
+int
+qla2100_release(struct Scsi_Host *host) {
+        scsi_qla_host_t *ha = (scsi_qla_host_t *) host->hostdata;
+
+        ENTER("qla2100_release");
+        /* if adpater is running and online */
+        if( !ha->flags.online )
+            return(0);
+
+        /* turn-off interrupts on the card */
+        qla2100_disable_intrs(ha);
+
+        /* Detach interrupts */
+        if( host->irq )
+            free_irq(host->irq, ha);
+
+        /* release io space registers  */
+        if( host->io_port )
+            release_region(host->io_port, 0xff);
+
+        /* Disable timer */
+        if( ha->timer_active )
+            STOP_TIMER(qla2100_timer,ha)
+
+            /* Kill the kernel thread for this host */
+            if( ha->dpc_handler != NULL ) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                struct semaphore sem = MUTEX_LOCKED;
+#else
+                DECLARE_MUTEX_LOCKED(sem);
+#endif
+
+                ha->dpc_notify = &sem;
+                send_sig(SIGKILL, ha->dpc_handler, 1);
+                down(&sem);
+                ha->dpc_notify = NULL;
+            }
+#if USE_FLASH
+            /* Move driver database to flash, if enabled. */
+            if( ha->flags.enable_flash_db_update && ha->flags.updated_fc_db ) {
+                ha->flags.updated_fc_db = FALSE;
+                qla2100_save_database(ha);
+            }
+#endif
+#if MEMORY_MAPPED_IO
+            if( ha->mmpbase ) {
+                iounmap((void *) (((unsigned long) ha->mmpbase) & PAGE_MASK));
+            }
+#endif /* MEMORY_MAPPED_IO */
+
+#if  APIDEV
+            apidev_cleanup();
+#endif
+
+            qla2100_mem_free(ha);
+            ha->flags.online = FALSE;
+
+            LEAVE("qla2100_release");
+            return(0);
+}
+
+/**************************************************************************
+*   qla2100_info
+*
+* Description:
+*
+* Input:
+*     host - pointer to Scsi host adapter structure
+*
+* Returns:
+*     Return a text string describing the driver.
+**************************************************************************/
+const char *
+qla2100_info(struct Scsi_Host *host) {
+        static char qla2100_buffer[255];
+        char *bp;
+        scsi_qla_host_t *ha;
+        qla_boards_t   *bdp;
+
+#if  APIDEV
+/* We must create the api node here instead of qla2100_detect since we want
+   the api node to be subdirectory of /proc/scsi/qla2x00 which will not
+   have been created when qla2100_detect exits, but which will have been
+   created by this point. */
+
+        apidev_init(host);
+#endif
+        bp = &qla2100_buffer[0];
+        ha = (scsi_qla_host_t *)host->hostdata;
+        bdp = &QLBoardTbl_fc[ha->devnum];
+        memset(bp, 0, sizeof(qla2100_buffer));
+        sprintf(bp,
+        "QLogic %sPCI to Fibre Channel Host Adapter: bus %d device %d irq %d\n"
+        "        Firmware version: %2d.%02d.%02d, Driver version %s",
+        (char *)&bdp->bdName[0], ha->pci_bus, (ha->pci_device_fn & 0xf8) >> 3, host->irq,
+        bdp->fwver[0], bdp->fwver[1], bdp->fwver[2], QLA2100_VERSION);
+        return(bp);
+}
+
+/**************************************************************************
+*   qla1200_queuecommand
+*
+* Description:
+*     Queue a command to the controller.
+*
+* Input:
+*     cmd - pointer to Scsi cmd structure
+*     fn - pointer to Scsi done function
+*
+* Returns:
+*   0 - Always
+*
+* Note:
+* The mid-level driver tries to ensures that queuecommand never gets invoked
+* concurrently with itself or the interrupt handler (although the
+* interrupt handler may call this routine as part of request-completion
+* handling).
+**************************************************************************/
+int
+qla2100_queuecommand(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *)) {
+        scsi_qla_host_t *ha;
+        srb_t  *sp;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+        unsigned long cpu_flags = 0;
+#endif
+        struct Scsi_Host *host;
+        uint32_t        b, t, l;
+        scsi_lu_t       *q;
+        u_long          handle;
+
+        ENTER("qla2100_queuecommand");
+        COMTRACE('C') 
+
+        host = cmd->host;
+        ha = (scsi_qla_host_t *) host->hostdata;
+        /* Get our SCSI request pointer
+        * SCp always point to it - see definition in qla2100.h.
+        */
+        sp = (srb_t *) CMD_SP(cmd);
+        sp->cmd =  cmd;
+        cmd->scsi_done = fn;
+
+        /* If we not trying to do a recovery procedure of some sort
+        * then this is probably a new command.
+        */
+        if( cmd->flags == 0 &&
+        cmd->retries == 0 )
+            sp->flags = 0;
+
+        /* Generate LU queue on bus, target, LUN */
+        b = SCSI_BUS_32(cmd);
+        t = SCSI_TCN_32(cmd);
+        l = SCSI_LUN_32(cmd);
+
+        DEBUG5(qla2100_print_scsi_cmd(cmd);)
+        DEBUG5(sprintf(debug_buff,"qla2100_queuecmd: pid=%d, opcode=%d, timeout=%d\n",cmd->pid,cmd->cmnd[0],CMD_TIMEOUT(cmd));)
+        DEBUG5(qla2100_print(debug_buff);)
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+        /*DEBUG(sprintf(debug_buff,"\n\nQC: t=%x CDB=%x Size=%x\n\r",
+        t,cmd->cmnd[0],CMD_XFRLEN(cmd));)
+        DEBUG(qla2100_print(debug_buff)); */ 
+#endif
+        /*
+        * We found all the devices at LIP time, and created a device
+        * table for them, so we only need to check the table to see
+        * if the device is present. if PORT_AVAILABLE or PORT_UNUSED
+        * then no target exists.
+        *
+        * We return DID_NO_CONNECT if the loop is down after loop down
+        * timer has expired.
+        */
+        if( TGT_Q(ha,b,t) == NULL ||
+           (TGT_Q(ha,b,t) && TGT_Q(ha,b,t)->loop_id > LAST_SNS_LOOP_ID)  ) {
+            /* DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): port unavailable\n",
+            (int)ha->host_no,b,t,l);) */ 
+            CMD_RESULT(sp->cmd) = DID_NO_CONNECT << 16;
+            qla2100_callback(ha,sp,FALSE);
+            LEAVE("qla2100_queuecommand");
+            return(0);
+        }
+        /* v218b4 */ 
+        if (ha->loop_down_timer == 0 && 
+            ha->loop_state == LOOP_DOWN ){  /* 01/21/00 DG */
+            DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): Loop down - returning pid=%ld \n",(int)ha->host_no,b,t,l,cmd->pid);)
+            CMD_RESULT(sp->cmd) = DID_NO_CONNECT << 16;
+            ha->flags.done_requests_needed = TRUE;
+            qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+            LEAVE("qla2100_queuecommand");
+            return(0);
+        }
+
+        /*
+        * Allocate a LUN/DEVICE queue from this request if we haven't
+        * already did it on a previous command.
+        */
+        if( (q = GET_LU_Q(ha, b, t,l)) == NULL ) {
+            DRIVER_LOCK
+            if( (q = qla2100_lun_alloc()) == NULL ) {
+                CMD_RESULT(sp->cmd) = DID_RETRY << 16;
+                qla2100_callback(ha,sp,FALSE);
+                return(0);
+            }
+            LU_Q(ha, b, t, l) = q;
+            DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q));
+            DEBUG(qla2100_print(debug_buff));
+            DRIVER_UNLOCK
+        }
+
+        /* Set an invalid handle until we issue the command to ISP */
+        /* then we will set the real handle value.                 */
+        handle = INVALID_HANDLE;
+        CMD_HANDLE(cmd) = (unsigned char *)handle;
+
+#if QLA2100_EXT_TIMEOUT
+        /* Extend timeout for this request */
+        qla2100_extend_timeout(cmd,60*HZ);
+#endif
+
+        /*
+        * SCSI Kluge
+        * ========
+        * Whenever, we need to wait for an event such as loop down
+        * (i.e. loop_down_timer ) or port down (i.e. LUN request qeueue is
+        * suspended) then we will recycle new commands back to the SCSI layer.
+        * We do this because this is normally a temporary condition and we don't
+        * want the mid-level scsi.c driver to get upset and start aborting
+        * commands.
+
+        * The timeout value is extracted from the command minus 1-second
+        * and put on a retry queue (watchdog). Once the command timeout it
+        * is returned to the mid-level with a BUSY status, so the mid-level
+        * will retry it. This process continues until the LOOP DOWN time
+        * expires or the condition goes away.
+        */
+        if( ha->loop_down_timer ||
+        ha->loop_state ==  LOOP_DOWN ||
+        (PORT_DOWN(ha,t) > 0) ||
+        ha->loop_state != LOOP_READY ||
+        (q->q_flag & QLA2100_QSUSP) ) {
+            /* Insert command into watchdog queue */
+            qla2100_timeout_insert(ha, sp);
+            LEAVE("qla2100_queuecommand");
+            return (0);
+        }
+        /* Set retry count if this is a new command */
+        if( sp->flags == 0 &&
+        !(q->q_flag & QLA2100_QSUSP) ) {
+            sp->retry_count = ha->retry_count;
+            if( TGT_Q(ha, b, t)->down_timer == 0 ) 
+	    	sp->port_down_retry_count = ha->port_down_retry_count;
+        }
+
+        /* No timeout necessary, because the upper layer is doing it for us */
+        sp->wdg_time = 0;
+
+        /* add the command to our queue */
+        ha->qthreads++;
+        qla2100_putq_t(q,sp);
+
+        DEBUG5(sprintf(debug_buff,"\nQC: queue pid=%d, hndl=0x%x\n\r",
+               cmd->pid,handle));
+        DEBUG5(qla2100_print(debug_buff));
+
+        /* send command to adapter */
+        qla2100_restart_queues(ha,FALSE);
+
+        COMTRACE('c')
+        LEAVE("qla2100_queuecommand"); 
+        return (0);
+}
+
+/**************************************************************************
+*   qla1200_abort
+*
+* Description:
+*     Abort the specified SCSI command.
+*
+* Input:
+*     cmd - pointer to Scsi cmd structure
+*
+* Returns:
+**************************************************************************/
+int
+qla2100_abort(Scsi_Cmnd *cmd) {
+        scsi_qla_host_t *ha;
+        srb_t  *sp;
+        srb_t  *rp, *rp_next;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+        unsigned long cpu_flags = 0;
+#endif
+        struct Scsi_Host *host;
+        uint32_t        b, t, l;
+        scsi_lu_t       *q;
+        int return_status = SCSI_ABORT_SUCCESS;
+        int found = 0;
+        int i;
+        u_long          handle;
+
+        uint16_t    data;
+
+        ENTER("qla2100_abort");
+        COMTRACE('A')
+
+        ha = (scsi_qla_host_t *) cmd->host->hostdata;
+        host = cmd->host;
+
+#if DEBUG_GET_FW_DUMP
+        if (ha->device_id == QLA2300_DEVICE_ID)
+        {  
+          if (ha->dump_done != 1) {
+              DEBUG(sprintf(debug_buff,"\nqla2100_abort handle=%x: >>>>>>> DUMP 2300 FW <<<<<<<\n",CMD_HANDLE(cmd));)
+              DEBUG(qla2100_print(debug_buff);)
+              qla2300_dump_isp(ha);
+              ha->dump_done = 1;
+          }
+        }
+#endif
+
+        DRIVER_LOCK
+        /* Get the SCSI request ptr */
+        sp = (srb_t *) CMD_SP(cmd);
+
+        /*
+        * if the handle is NULL then we already completed the command.
+        * We always give the handle a value of "INVALID_HANDLE" when
+        * we received it.
+        */
+        if( (u_long)   CMD_HANDLE(cmd) == 0L ) {
+
+            DRIVER_UNLOCK
+#if  STOP_ON_ABORT
+            qla2100_panic("qla2100_abort",ha->host);
+#endif
+            return(SCSI_ABORT_NOT_RUNNING);  /* no action - we don't have command */
+        }
+
+        /* Check for a pending interrupt. */
+        if (ha->device_id == QLA2300_DEVICE_ID) 
+             data = qla2100_debounce_register((uint16_t *)&ha->iobase2300->host_status) &   RISC_2300_INT;
+        else data = qla2100_debounce_register(&ha->iobase->istatus) & 
+                    RISC_INT;
+
+        /* Check for pending interrupts. */
+        if( !(ha->flags.in_isr) && (data)) {
+            /* Add any completed commands in the done queue */
+            DEBUG(qla2100_print("qla2100_abort: Calling isr\n");)
+            qla2100_isr(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+        }
+
+        /*
+        * if no LUN queue then something is very wrong!!!
+        */
+        handle = (u_long) CMD_HANDLE(cmd);
+
+        /* Generate LU queue on bus, target, LUN */
+        b = SCSI_BUS_32(cmd);
+        t = SCSI_TCN_32(cmd);
+        l = SCSI_LUN_32(cmd);
+        if( (q = GET_LU_Q(ha, b, t, l)) == NULL ) {
+            COMTRACE('a')
+
+            DRIVER_UNLOCK
+            printk(KERN_WARNING "qla2100 (%d:%d:%d): No LUN queue for the specified device\n",(int)b,(int)t,(int)l);
+            return(SCSI_ABORT_NOT_RUNNING);  /* no action - we don't have command */
+        }
+
+#if AUTO_ESCALATE_ABORT
+        if( (sp->flags & SRB_ABORTED) ) {
+            DRIVER_UNLOCK
+            DEBUG(qla2100_print("qla2100_abort: Abort escalayted - returning SCSI_ABORT_SNOOZE.\n\r"));
+            return(SCSI_ABORT_SNOOZE);
+        }
+#endif
+        /*
+        * if the command ahs a abort pending then tell the upper layer
+        */
+        if( (sp->flags & SRB_ABORT_PENDING) ) {
+            COMTRACE('a')
+            DRIVER_UNLOCK
+            if( qla2100_verbose )
+                printk(KERN_INFO "scsi(): Command has a pending abort "
+		    "message - ABORT_PENDING.\n");
+            DEBUG(qla2100_print("qla2100: Command has a pending abort message - ABORT_PENDING.\n\r"));
+            return(SCSI_ABORT_PENDING);
+        }
+
+        DEBUG(sprintf(debug_buff,"ABORTing command= 0x%x, sp=%x sp->state=%x\n",
+        (int)cmd,sp,sp->state);)
+        DEBUG(qla2100_print(debug_buff);)
+        DEBUG(qla2100_print_scsi_cmd(cmd));
+
+        for( rp = ha->retry_q_first; (rp); rp = rp_next ) {
+            rp_next = rp->s_next;
+            if( sp != rp )
+                continue;
+            qla2100_timeout_remove(ha, sp);
+            CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+            CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+            qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+            found++;
+        }
+
+        /*
+        * Our SP pointer points at the command we want to remove from the
+        * LUN queue providing we haven't already sent it to the adapter.
+        */
+        if( found )
+            return_status = SCSI_ABORT_SUCCESS;
+        else if( !(sp->flags&SRB_SENT) ) {
+            found++;
+            DEBUG(sprintf(debug_buff,"qla2100: Cmd in LUN queue aborted pid %d.\n\r",sp->cmd->pid);)
+            DEBUG(qla2100_print(debug_buff);)
+            /* Remove srb from SCSI LU queue. */
+            qla2100_removeq(q, sp);
+            sp->flags |=  SRB_ABORTED;
+            CMD_RESULT(cmd) = DID_ABORT << 16;
+            qla2100_done_q_put(ha, sp, &ha->done_q_first, &ha->done_q_last);
+            return_status = SCSI_ABORT_SUCCESS;
+            found++;
+        } else {  /* find the command in our active list */
+            for( i = 1; i < MAX_OUTSTANDING_COMMANDS; i++ ) {
+                if( sp == ha->outstanding_cmds[i] ) {
+                    found++;
+                    DEBUG(sprintf(debug_buff,
+                          "qla2100: RISC aborting pid %d sp->state=%x\n\r",
+                          sp->cmd->pid,sp->state);)
+                    DEBUG(qla2100_print(debug_buff);)
+                    /* DEBUG(qla2100_print_scsi_cmd(cmd)); */
+                    DEBUG(qla2100_print_q_info(q);)
+                    /* v2.19.8 Ignore abort request if port is down */
+                        if ( qla2100_abort_command(ha,sp) ) {
+                            DEBUG(printk("qla2100: Failed to abort pid %ld.\n",sp->cmd->pid);)
+                            return_status = SCSI_ABORT_NOT_RUNNING;  /* no action */
+                        }
+                    else
+                        return_status = SCSI_ABORT_PENDING;
+                    break;
+                }
+            }
+        }
+
+#if  STOP_ON_ABORT
+        qla2100_panic("qla2100_abort",ha->host);
+#endif
+        if( found == 0 )
+            return_status = SCSI_ABORT_NOT_RUNNING;  /* no action */
+
+        DEBUG(sprintf(debug_buff, "qla2100_abort: Aborted status returned = 0x%x.\n\r",return_status));
+        DEBUG(qla2100_print(debug_buff));
+        /*
+        * Complete any commands
+        */
+        if( ha->done_q_first )
+            qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+
+        if( found ) {
+            qla2100_restart_queues(ha,TRUE);
+        }
+        DRIVER_UNLOCK
+
+        LEAVE("qla2100_abort");
+        COMTRACE('a')
+        return(return_status);
+}
+
+/**************************************************************************
+* qla1200_reset
+*
+* Description:
+*    The reset function will reset the SCSI bus and abort any executing
+*    commands.
+*
+* Input:
+*      cmd = Linux SCSI command packet of the command that cause the
+*            bus reset.
+*      flags = SCSI bus reset option flags (see scsi.h)
+*
+* Returns:
+*      DID_RESET in cmd.host_byte of aborted command(s)
+*
+* Note:
+*      Resetting the bus always succeeds - is has to, otherwise the
+*      kernel will panic! Try a surgical technique - sending a BUS
+*      DEVICE RESET message - on the offending target before pulling
+*      the SCSI bus reset line.
+**************************************************************************/
+int
+qla2100_reset(Scsi_Cmnd *cmd, unsigned int flags) {
+        scsi_qla_host_t *ha;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+        unsigned long cpu_flags = 0;
+#endif
+        uint32_t        b, t, l;
+        srb_t  *sp;
+        typedef enum {
+            ABORT_DEVICE = 1,
+            DEVICE_RESET = 2,
+            BUS_RESET    = 3,
+            ADAPTER_RESET= 4,
+            RESET_DELAYED= 5,
+            FAIL         = 6
+        } action_t;
+        action_t     action = ADAPTER_RESET;
+        uint16_t    data;
+        scsi_lu_t       *q;
+        int result;
+
+
+        ENTER("qla2100_reset");
+        COMTRACE('R')
+        if( cmd == NULL ) {
+            printk(KERN_WARNING "(scsi?:?:?:?) Reset called with NULL Scsi_Cmnd "
+            "pointer, failing.\n");
+            return(SCSI_RESET_SNOOZE);
+        }
+        ha = (scsi_qla_host_t *) cmd->host->hostdata;
+        sp = (srb_t *) CMD_SP(cmd);
+
+#if  STOP_ON_RESET
+        sprintf(debug_buff,"ABORTing command= 0x%x\n",(int)cmd);
+        qla2100_print(debug_buff);
+        qla2100_print_scsi_cmd(cmd);
+        qla2100_panic("qla2100_reset",ha->host);
+#endif
+
+
+        DRIVER_LOCK
+        if (ha->device_id == QLA2300_DEVICE_ID) 
+             data = qla2100_debounce_register((uint16_t *)&ha->iobase2300->host_status) &
+                    RISC_2300_INT;
+        else data = qla2100_debounce_register(&ha->iobase->istatus) & 
+                    RISC_INT;
+
+        /* Check for pending interrupts. */
+        if( !(ha->flags.in_isr) && (data) ) {
+            DEBUG(qla2100_print("qla2100_reset: Calling isr\n");)
+            qla2100_isr(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+        }
+        DRIVER_UNLOCK
+
+        /*
+        * Determine the suggested action that the mid-level driver wants
+        * us to perform.
+        */
+        if( CMD_HANDLE(cmd) == (unsigned char *) 0 ) {
+            /*
+            * if mid-level driver called reset with a orphan SCSI_Cmnd
+            * (i.e. a command that's not pending ), so perform the
+            * function specified.
+            */
+            /* 4.23 */
+            if( (flags & SCSI_RESET_SUGGEST_HOST_RESET) )
+                action = ADAPTER_RESET;
+            else if( flags & SCSI_RESET_SUGGEST_BUS_RESET )
+                action = BUS_RESET;
+            else
+                action = DEVICE_RESET;
+        } else { /*
+            * Mid-level driver has called reset with this SCSI_Cmnd and
+            * its pending.
+            */
+            if( flags & SCSI_RESET_SUGGEST_HOST_RESET )
+                action = ADAPTER_RESET;
+            else if( flags & SCSI_RESET_SUGGEST_BUS_RESET )
+                action = BUS_RESET;
+            else
+                action = DEVICE_RESET;
+        }
+
+        b = SCSI_BUS_32(cmd);
+        t = SCSI_TCN_32(cmd);
+        l = SCSI_LUN_32(cmd);
+        q = GET_LU_Q(ha, b, t, l);
+
+#if AUTO_ESCALATE_RESET
+        if( (action & DEVICE_RESET) && (q->q_flag & QLA2100_QRESET) ) {
+            printk(KERN_INFO "qla2100(%d): Bus device reset already sent to " "device, escalating.\n", (int)ha->host_no);
+            action = BUS_RESET;
+        }
+        if( (action & DEVICE_RESET) && (sp->flags & SRB_ABORT_PENDING) ) {
+            printk(KERN_INFO "qla2100(%d):Have already attempted to reach " "device with abort device\n", (int)ha->host_no);
+            printk(KERN_INFO "qla2100(%d):message, will escalate to BUS " "RESET.\n",(int) ha->host_no);
+            action = BUS_RESET;
+        }
+#endif
+
+        /*
+        *  By this point, we want to already know what we are going to do,
+        *  so we only need to perform the course of action.
+        */
+
+        DRIVER_LOCK
+        result = SCSI_RESET_ERROR;
+        switch( action ) {
+            case FAIL:
+                break;
+
+            case RESET_DELAYED:
+                result = SCSI_RESET_PENDING;
+                break;
+
+            case ABORT_DEVICE:
+                if( qla2100_verbose )
+                    printk(KERN_INFO "scsi(%d:%d:%d:%d): ABORT DEVICE ISSUED.\n", (int)ha->host_no,(int)b,(int)t,(int)l);
+                qla2100_abort_queue_single(ha,b,t,l,DID_ABORT);
+                if( !ha->loop_down_timer )
+                    if( qla2100_abort_device(ha, b, t, l) == 0 )
+                        result = SCSI_RESET_PENDING;
+                    break;
+
+                case DEVICE_RESET:
+                    if( qla2100_verbose )
+                        printk(KERN_INFO "scsi(%d:%d:%d:%d): DEVICE RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l);
+                    for( l = 0; l <  ha->max_luns; l++ )
+                        qla2100_abort_queue_single(ha,b,t,l,DID_ABORT);
+                    if( !ha->loop_down_timer )
+                        if( qla2100_device_reset(ha, b, t) == 0 )
+                            result = SCSI_RESET_PENDING;
+                        q->q_flag |= QLA2100_QRESET;
+                        break;
+
+                    case BUS_RESET:
+                        if( qla2100_verbose )
+                            printk(KERN_INFO "scsi(%d:%d:%d:%d): LOOP RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l);
+                        for( t = 0; t < ha->max_targets; t++ )
+                            for( l = 0; l <  ha->max_luns; l++ )
+                                qla2100_abort_queue_single(ha,b,t,l,DID_RESET);
+                            if( !ha->loop_down_timer )
+                                if( qla2100_loop_reset(ha) == 0 )
+                                    result = SCSI_RESET_SUCCESS | SCSI_RESET_BUS_RESET;
+                                /*
+                                * The reset loop routine returns all the outstanding commands back
+                                * with "DID_RESET" in the status field.
+                                */
+                                if( flags & SCSI_RESET_SYNCHRONOUS ) {
+                                    CMD_RESULT(cmd) = (int) (DID_BUS_BUSY << 16);
+                                    (*(cmd)->scsi_done)(cmd);
+                                }
+
+                                /* ha->reset_start = jiffies; */
+                                break;
+
+                            case ADAPTER_RESET:
+                            default:
+                                if( qla2100_verbose ) {
+                                        printk(KERN_INFO "scsi(%d:%d:%d:%d): ADAPTER RESET ISSUED.\n",(int) ha->host_no,(int)b,(int)t,(int)l);
+                                }
+                                ha->flags.reset_active = TRUE;
+                                /*
+                                * We restarted all of the commands automatically, so the mid-level code can expect
+                                * completions momentitarily.
+                                */
+                                if( qla2100_abort_isp(ha) == 0 )
+                                    result = SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET;
+
+                                ha->flags.reset_active = FALSE;
+        }
+
+        if( ha->done_q_first )
+            qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+        qla2100_restart_queues(ha,TRUE);
+        DRIVER_UNLOCK
+
+        COMTRACE('r')
+        LEAVE("qla2100_reset");
+        return(result);
+}
+
+/**************************************************************************
+* qla1200_biosparam
+*
+* Description:
+*   Return the disk geometry for the given SCSI device.
+**************************************************************************/
+int
+qla2100_biosparam(Disk *disk, kdev_t dev, int geom[]) {
+        int heads, sectors, cylinders;
+
+        heads = 64;
+        sectors = 32;
+        cylinders = disk->capacity / (heads * sectors);
+        if( cylinders > 1024 ) {
+            heads = 255;
+            sectors = 63;
+            cylinders = disk->capacity / (heads * sectors);
+        }
+
+        geom[0] = heads;
+        geom[1] = sectors;
+        geom[2] = cylinders;
+
+        return (0);
+}
+
+/**************************************************************************
+* qla2100_intr_handler
+*
+* Description:
+*   Handles the actual interrupt from the adapter.
+*
+* Context: Interrupt
+**************************************************************************/
+void
+qla2100_intr_handler(int irq, void *dev_id, struct pt_regs *regs) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,95)
+        unsigned long cpu_flags = 0;
+#endif
+        scsi_qla_host_t *ha;
+        uint16_t    data;
+        device_reg_t *reg;
+        device2300_reg_t *reg2300;
+
+        ENTER_INTR("qla2100_intr_handler");
+        COMTRACE('I')
+        ha = (scsi_qla_host_t *) dev_id;
+        if( !ha ) {
+            printk(KERN_INFO "qla2100_intr_handler: NULL host ptr\n");
+            COMTRACE('X')
+            return;
+        }
+        ha->isr_count++;
+        qla2100_stats.irqhba = ha;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,95)
+        /* Prevent concurrent access to adapters register */
+        spin_lock_irqsave(&io_request_lock, cpu_flags);
+        qla2100_disable_intrs(ha);
+
+        if (ha->device_id == QLA2300_DEVICE_ID) {
+             reg2300 = ha->iobase2300;
+             data    = qla2100_debounce_register(
+                       (uint16_t *)&reg2300->host_status) &  RISC_2300_INT;
+        } else {
+              reg     = ha->iobase;
+              data    = qla2100_debounce_register(&reg->istatus) & 
+                        RISC_INT;
+         }
+
+        /* Check for pending interrupts. */
+        if( data ) {
+         /*DEBUG(qla2100_print("qla2100_intr_handler: Int active, Calling isr\n");)*/
+          qla2100_isr(ha, 
+                     (srb_t **)&ha->done_q_first, 
+                     (srb_t **)&ha->done_q_last);
+        }
+
+        if( ha->done_q_first )
+            qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+
+        spin_unlock_irqrestore(&io_request_lock, cpu_flags);
+        qla2100_enable_intrs(ha);
+
+        /* Wakeup the DPC routine */
+        if( (!ha->flags.mbox_busy && (ha->flags.isp_abort_needed   ||
+        ha->flags.reset_marker       ||
+        ha->flags.update_config_needed       ||
+        ( !ha->flags.loop_resync_active &&
+        ha->flags.loop_resync_needed)  ) )
+        && ha->dpc_wait && !ha->dpc_active ) {  /* v2.19.4 */
+            up(ha->dpc_wait);
+        }
+
+#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95) */
+
+        /* Prevent concurrent access to istatus register */
+        if( test_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags) ) {
+            COMTRACE('X')
+            DEBUG(printk("scsi%d: Already in interrupt - returning \n", (int)ha->host_no);)
+            return;
+        }
+        set_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags);
+        qla2100_disable_intrs(ha);
+
+        if (ha->device_id == QLA2300_DEVICE_ID) { 
+           reg2300 = ha->iobase2300;
+           data = qla2100_debounce_register(
+                  (uint16_t *)&reg2300->host_status) & RISC_2300_INT;
+        } else {
+           reg  = ha->iobase;
+           data = qla2100_debounce_register(&reg->istatus) & 
+                  RISC_INT;
+        }
+
+        /* Check for pending interrupts. */
+        if( data ) {
+            DEBUG(qla2100_print("qla2100_intr_handler_2: Int active, Calling isr\n");)
+            qla2100_isr(ha, 
+                        (srb_t **)&ha->done_q_first, 
+                        (srb_t **)&ha->done_q_last);
+        }
+
+        if( ha->done_q_first )
+            qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+
+
+        /* Schedule the DPC routine */
+        if( (ha->flags.isp_abort_needed   ||
+        ha->flags.reset_marker       ||
+        ( !ha->flags.loop_resync_active &&
+        ha->flags.loop_resync_needed) ||
+        ha->done_q_first ) && !ha->flags.dpc_sched ) {
+
+            ha->run_qla_bh.data = (void *) ha;
+            ha->run_qla_bh.routine = qla2100_do_dpc;
+
+            COMTRACE('P')
+            queue_task_irq(&ha->run_qla_bh,&tq_scheduler);
+            ha->flags.dpc_sched = TRUE;
+        }
+        clear_bit(QLA2100_IN_ISR_BIT, (int *)&ha->flags);
+        qla2100_enable_intrs(ha);
+#endif
+
+        COMTRACE('i')
+        LEAVE_INTR("qla2100_intr_handler");
+}
+
+/**************************************************************************
+* qla2100_do_dpc
+*   This kernel thread is a task that is schedule by the interrupt handler
+*   to perform the background processing for interrupts.
+*
+* Notes:
+* This task always run in the context of a kernel thread.  It
+* is kick-off by the driver's detect code and starts up
+* up one per adapter. It immediately goes to sleep and waits for
+* some fibre event.  When either the interrupt handler or
+* the timer routine detects a event it will one of the task
+* bits then wake us up.
+**************************************************************************/
+void
+qla2100_do_dpc(void *p) {
+        scsi_qla_host_t *ha = (scsi_qla_host_t *) p;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        struct semaphore sem = MUTEX_LOCKED;
+#else 
+        DECLARE_MUTEX_LOCKED(sem);
+#endif
+        unsigned long flags;
+        srb_t *sp, *sp_next;
+        uint32_t        b, t, l;
+        scsi_lu_t       *q;
+        int status;
+
+        lock_kernel();
+
+        /*
+        * If we were started as result of loading a module, close all of the
+        * user space pages.  We don't need them, and if we didn't close them
+        * they would be locked into memory.
+        */
+        exit_mm(current);
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+
+        daemonize();
+
+#endif
+        current->session = 1;
+        current->pgrp = 1;
+        /*
+        * FIXME(dg) this is still a child process of the one that did the insmod.
+        * This needs to be attached to task[0] instead.
+        */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+        siginitsetinv(&current->blocked, SHUTDOWN_SIGS);
+#else
+        siginitsetinv(&current->blocked, sigmask(SIGKILL));  
+#endif
+        current->fs->umask = 0;
+
+        /*
+        * Set the name of this process.
+        */
+        sprintf(current->comm, "qla2100_dpc_%d", (int)ha->host_no);
+
+        ha->dpc_wait = &sem;
+        ha->dpc_handler = current;
+
+        unlock_kernel();
+
+        /*
+        * Wake up the thread that created us.
+        */
+        DEBUG(printk("qla2100_dpc: Wake up parent %d\n", ha->dpc_notify->count.counter));
+
+        up(ha->dpc_notify);
+
+        while( 1 ) {
+            /*
+            * If we get a signal, it means we are supposed to go
+            * away and die.  This typically happens if the user is
+            * trying to unload a module.
+            */
+            DEBUG(printk("qla2100 %d: DPC handler sleeping\n",(int)ha->host_no));
+            down_interruptible(&sem);
+
+            if( signal_pending(current) )
+                break;   /* get out */
+
+            DEBUG(printk("qla2100 %d: DPC handler waking up\n",(int)ha->host_no);)
+
+	    if (ha->dpc_flags & COMMAND_WAIT_NEEDED) {
+		    /* Release task daemon lock. */
+                    DEBUG(printk("Waiting on commands to complete\n");)
+		    if( qla2100_cmd_wait(ha) )
+                       continue;
+		    /* Acquire task daemon lock. */
+	    }
+            spin_lock_irqsave(&io_request_lock, flags);
+            ha->dpc_active = 1;
+
+            /* Determine what action is necessary */
+
+            /* Flush all commands in watchdog queue */
+            if( ha->flags.port_restart_needed ) {
+                DEBUG(qla2100_print("qla2100: DPC port restarting - flushing all cmds in watchdog queue.\n");)
+                ha->flags.port_restart_needed = FALSE;
+                for( sp = ha->retry_q_first; (sp != NULL); sp =  sp_next ) {
+                    sp_next = sp->s_next;
+                    b = SCSI_BUS_32(sp->cmd);
+                    t = SCSI_TCN_32(sp->cmd);
+                    l = SCSI_LUN_32(sp->cmd);
+                    if( (q = GET_LU_Q(ha, b, t,l)) == NULL ||
+                    !(q->q_flag & QLA2100_QSUSP) )
+                        continue;
+                    q->q_flag &= ~QLA2100_QSUSP;
+                    qla2100_timeout_remove(ha, sp);
+                    CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                    CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                    qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+                }
+
+                /* v2.19 -  We want to wait until the end to 
+                 * return all requests back to OS.
+                 */ 
+                /* deleted: qla2100_restart_queues(ha, FALSE); */
+                ha->flags.restart_queues_needed = TRUE;
+            }
+
+            /* Process any pending mailbox commands */
+            if( !ha->flags.mbox_busy ) {
+                if( ha->flags.isp_abort_needed ) {
+                    DEBUG(printk("dpc: qla2100_abort_isp ha = %p\n", ha);)
+                    ha->flags.isp_abort_needed = FALSE;
+                    qla2100_abort_isp(ha);
+                }
+
+                if( ha->flags.reset_marker ) {
+                    DEBUG(printk("dpc: qla2100_reset_marker \n");)
+                    qla2100_rst_aen(ha);
+                }
+
+                if( ha->flags.update_config_needed ) {
+                    DEBUG(printk("dpc: qla2100_update_config\n");)
+                    qla2100_update_config(ha);
+                }
+
+                /* v2.19.8 Retry each device up to login retry count */
+                if ( (ha->device_flags & RELOGIN_NEEDED) &&
+                     !ha->loop_state != LOOP_DOWN ) { /* v2.19.5 */
+                    DEBUG(printk("dpc: qla2100_login\n");)
+                    ha->device_flags &= ~RELOGIN_NEEDED;
+                    for (t = 0; t < MAX_FIBRE_DEVICES; t++) {
+					    /* check if fabric logic retry needed */
+						if ( (ha->fc_db[t].flag & DEV_PUBLIC) &&
+						     (ha->fc_db[t].flag & DEV_RELOGIN) ) {
+							if ( PORT_DOWN(ha,t) ) {
+                                PORT_DOWN(ha,t)--;
+                                if ( (status = qla2x00_login_public_device(ha,
+                                  &ha->fc_db[t].loop_id,
+                                  &ha->fc_db[t].port_id[0],
+                                  (uint16_t) MBC_NO_PLOGI_IF_LOGGED_IN)) == QL_STATUS_SUCCESS ) {
+                                    DEBUG(printk("dpc: logged in ID %x\n",ha->fc_db[t].loop_id);)
+							        /* restart ports */
+						            ha->fc_db[t].flag &= ~DEV_RELOGIN;
+                                    PORT_DOWN(ha,t) = 0;
+                                  } else if ( status == QL_STATUS_FATAL_ERROR ) {
+                                    ha->flags.isp_abort_needed = TRUE;
+						            ha->fc_db[t].flag &= ~DEV_RELOGIN;
+                                    PORT_DOWN(ha,t) = 0;
+                                  } else {
+								    /* retry the login again */
+                                    ha->device_flags |= RELOGIN_NEEDED;
+                                    DEBUG(printk("dpc: Retry %d logged in ID %x\n",PORT_DOWN(ha,t),
+									      ha->fc_db[t].loop_id);)
+								  }
+							}
+						}
+                    }
+                    DEBUG(printk("dpc: qla2100_login_end.\n");)
+                }
+
+                /* v2.19.5 */
+                if ( (ha->device_flags & LOGIN_RETRY_NEEDED) &&
+                     !ha->loop_state != LOOP_DOWN ) { /* v2.19.5 */
+                    ha->device_flags &= ~LOGIN_RETRY_NEEDED;
+                    DEBUG(printk("dpc: qla2100_login_retry\n");)
+                    qla2100_loop_resync(ha);
+                    DEBUG(printk("dpc: qla2100_login_retry end.\n");)
+                }
+
+                 /* v2.19.5b5 */
+                if( ha->flags.loop_resync_needed ) {
+                   if( (ha->device_flags & RSCN_UPDATE ) ) {
+                     DEBUG(printk("dpc: qla2100_rscn_update\n");)
+                     ha->device_flags &= ~RSCN_UPDATE;
+                   }
+                   else
+                     DEBUG(printk("dpc: qla2100_loop_resync\n");)
+                     qla2100_loop_resync(ha);
+                    DEBUG(printk("dpc: qla2100_loop_resync/rscn_update done\n");)
+                }
+
+                if( ha->flags.restart_queues_needed ) {
+                    DEBUG(printk("dpc: calling qla2100_restart_queues\n");)
+                    qla2100_restart_queues(ha,FALSE);
+                }
+
+                if( ha->flags.abort_queue_needed ) {
+                    DEBUG(printk("dpc: qla2100_abort_queues\n");)
+                    qla2100_abort_queues(ha, FALSE);
+                }
+                if( !ha->interrupts_on )
+                    qla2100_enable_intrs(ha);
+            }
+
+            if( ha->flags.done_requests_needed )
+                ha->flags.done_requests_needed = FALSE;
+
+            if( ha->done_q_first ) {
+                qla2100_done(ha, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+            }
+
+            ha->dpc_active = 0;
+
+            /* The spinlock is really needed up to this point. (DB) */
+            spin_unlock_irqrestore(&io_request_lock, flags);
+        }
+        DEBUG(qla2100_print("dpc: DPC handler exiting\n");)
+
+        /*
+        * Make sure that nobody tries to wake us up again.
+        */
+        ha->dpc_wait = NULL;
+        ha->dpc_handler = NULL;
+        ha->dpc_active = 0;
+
+        /*
+        * If anyone is waiting for us to exit (i.e. someone trying to unload
+        * a driver), then wake up that process to let them know we are on
+        * the way out the door.  This may be overkill - I *think* that we
+        * could probably just unload the driver and send the signal, and when
+        * the error handling thread wakes up that it would just exit without
+        * needing to touch any memory associated with the driver itself.
+        */
+        if( ha->dpc_notify != NULL )
+            up(ha->dpc_notify);
+
+
+}
+
+/**************************************************************************
+* qla2100_device_queue_depth
+*   Determines the queue depth for a given device.  There are two ways
+*   a queue depth can be obtained for a tagged queueing device.  One
+*   way is the default queue depth which is determined by whether
+*   If it is defined, then it is used
+*   as the default queue depth.  Otherwise, we use either 4 or 8 as the
+*   default queue depth (dependent on the number of hardware SCBs).
+**************************************************************************/
+STATIC void qla2100_device_queue_depth(scsi_qla_host_t *p, Scsi_Device *device) {
+        int default_depth = 16;
+         
+        device->queue_depth = default_depth;
+        if( device->tagged_supported ) {
+            device->tagged_queue = 1;
+            device->current_tag = 0;
+#ifdef MODULE
+            if( !(ql2xmaxqdepth == 0 || ql2xmaxqdepth > 256) )
+              device->queue_depth = ql2xmaxqdepth;
+#endif
+
+            printk(KERN_INFO "scsi(%d:%d:%d:%d): Enabled tagged queuing, queue depth %d.\n",
+            (int)p->host_no, device->channel, device->id,
+            device->lun, device->queue_depth);
+        } else {
+            printk(KERN_WARNING "scsi(%d:%d:%d:%d):Device does not supoort tags queuing!!!.\n",
+            (int)p->host_no, device->channel, device->id,
+            device->lun);
+        }
+}
+
+/**************************************************************************
+*   qla2100_select_queue_depth
+*
+* Description:
+*   Sets the queue depth for each SCSI device hanging off the input
+*   host adapter.  We use a queue depth of 2 for devices that do not
+*   support tagged queueing.
+**************************************************************************/
+STATIC void
+qla2100_select_queue_depth(struct Scsi_Host *host, Scsi_Device *scsi_devs) {
+        Scsi_Device *device;
+        scsi_qla_host_t  *p = (scsi_qla_host_t *) host->hostdata;
+
+        ENTER("qla2100_select_queue_depth");
+        for( device = scsi_devs; device != NULL; device = device->next ) {
+            if( device->host == host )
+                qla2100_device_queue_depth(p, device);
+        }
+        LEAVE("qla2100_select_queue_depth");
+}
+
+/**************************************************************************
+* ** Driver Support Routines **
+*
+* qla2100_enable_intrs
+* qla2100_disable_intrs
+**************************************************************************/
+static inline void qla2100_enable_intrs(scsi_qla_host_t *ha) {
+        device_reg_t *reg;
+
+        reg = ha->iobase;
+        ha->interrupts_on = 1;
+        /* enable risc and host interrupts */
+        WRT_REG_WORD(&reg->ictrl, (ISP_EN_INT+ ISP_EN_RISC));
+}
+
+static inline void qla2100_disable_intrs(scsi_qla_host_t *ha) {
+        device_reg_t *reg;
+
+        reg = ha->iobase;
+        ha->interrupts_on = 0;
+        /* disable risc and host interrupts */
+        WRT_REG_WORD(&reg->ictrl, 0);
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)
+/**************************************************************************
+*  mdelay
+*     Delay in milliseconds
+*
+**************************************************************************/
+STATIC inline void
+mdelay(int milliseconds) {
+        int i;
+
+        for( i=0; i<milliseconds; i++ ) {
+            SYS_DELAY(HZ);
+        }
+}
+#endif
+
+/**************************************************************************
+* qla2100_done
+*      Process completed commands.
+*
+* Input:
+*      ha           = adapter block pointer.
+*      done_q_first = done queue first pointer.
+*      done_q_last  = done queue last pointer.
+*
+* Returns:
+*     None
+**************************************************************************/
+STATIC void
+qla2100_done(scsi_qla_host_t *ha, srb_t **done_q_first, srb_t **done_q_last) {
+        srb_t           *sp;
+        scsi_lu_t       *q;
+        uint32_t        b, t, l;
+        Scsi_Cmnd  *cmd;
+        unsigned long cpu_flags = 0; 
+
+        /* ENTER("qla2100_done"); */
+        COMTRACE('D')
+
+        while( *done_q_first ) {
+            /* remove command from done list */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#endif
+            QLA2100_TIMER_LOCK(ha);
+            sp = *done_q_first;
+            if( !(*done_q_first = sp->s_next) )
+                *done_q_last = NULL;
+            else
+                (*done_q_first)->s_prev = NULL;
+            qla2100_stats.done_q_cnt--;
+            DEBUG(sp->state = 5;)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_UNLOCK
+#endif
+            QLA2100_TIMER_UNLOCK(ha);
+            cmd = sp->cmd;
+            b = SCSI_BUS_32(cmd);
+            t = SCSI_TCN_32(cmd);
+            l = SCSI_LUN_32(cmd);
+            q = GET_LU_Q(ha, b, t, l);
+
+            /* Decrement outstanding commands on device. */
+            if( q->q_outcnt )
+                q->q_outcnt--;
+            if( q->q_outcnt < ha->hiwat ) {
+                q->q_flag &= ~QLA2100_QBUSY;
+            }
+
+            q->io_cnt++;
+
+            switch( (CMD_RESULT(cmd)>>16) ) {
+                case DID_RESET:
+                    q->q_flag &= ~QLA2100_QRESET;
+                    /* Issue marker command. */
+                    qla2100_marker(ha, b, t, 0, MK_SYNC_ID);
+                    break;
+                case DID_ABORT:
+                    sp->flags &= ~SRB_ABORT_PENDING;
+                    sp->flags |= SRB_ABORTED;
+                    if( sp->flags & SRB_TIMEOUT )
+                        CMD_RESULT(sp->cmd)= DID_TIME_OUT << 16;
+                    break;
+                default:
+                    break;
+            }
+
+        /* 4.10   64 and 32 bit */
+        /* Release memory used for this I/O */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+        if (cmd->use_sg) {
+            /* DEBUG(sprintf(debug_buff,
+            "S/G unmap_sg cmd=%x\n\r",cmd);)
+            DEBUG(qla2100_print(debug_buff)); */
+            pci_unmap_sg(ha->pdev, cmd->request_buffer,
+                         cmd->use_sg,
+                         scsi_to_pci_dma_dir(cmd->sc_data_direction));
+        }
+        else if (cmd->request_bufflen) {
+                 /* DEBUG(sprintf(debug_buff,
+                 "No S/G unmap_single cmd=%x saved_dma_handle=%lx\n\r",
+                  cmd,sp->saved_dma_handle);)
+                  DEBUG(qla2100_print(debug_buff);) */
+                  pci_unmap_single(ha->pdev,sp->saved_dma_handle,
+                                  cmd->request_bufflen,
+                                  scsi_to_pci_dma_dir(cmd->sc_data_direction));
+       }
+#endif 
+            /* Call the mid-level driver interrupt handler */
+            /* DEBUG(sprintf(debug_buff," [%d] ",cmd->pid);)
+               DEBUG(qla2100_print(debug_buff);) */
+
+            qla2100_callback(ha,sp,TRUE);
+            qla2100_next(ha, q);
+        }
+
+
+        COMTRACE('d')
+        /* LEAVE("qla2100_done"); */
+}
+
+/**************************************************************************
+* qla2100_return_status
+* 	Translates a ISP error to a Linux SCSI error
+**************************************************************************/
+STATIC int qla2100_return_status(scsi_qla_host_t *ha, 
+    sts_entry_t *sts, Scsi_Cmnd *cp) {
+        int host_status = DID_ERROR;
+        int scsi_status;
+        int comp_status;
+        unsigned resid;
+        srb_t  *sp;
+        uint32_t        t;
+        uint8_t  *strp;
+        scsi_lu_t *up;
+
+#if DEBUG_QLA2100_INTR
+        STATIC char *reason[] = {
+            "DID_OK",
+            "DID_NO_CONNECT",
+            "DID_BUS_BUSY",
+            "DID_TIME_OUT",
+            "DID_BAD_TARGET",
+            "DID_ABORT",
+            "DID_PARITY",
+            "DID_ERROR",
+            "DID_RESET",
+            "DID_BAD_INTR"
+        };
+#endif /* DEBUG_QLA2100_INTR */
+
+        ENTER("qla2100_return_status");
+
+#if DEBUG_QLA2100_INTR
+        /*
+        DEBUG(printk("qla2100: compl status = 0x%04x\n", sts->comp_status));
+        */
+#endif
+        scsi_status = sts->scsi_status;
+        comp_status = sts->comp_status;
+        sp = (srb_t *) CMD_SP(cp);
+
+        if( (scsi_status & SS_RESIDUAL_OVER) )
+            comp_status = CS_DATA_OVERRUN;
+        else if( (scsi_status & SS_RESPONSE_INFO_LEN_VALID) &&
+        sts->rsp_info[3] == (uint8_t) 0 )
+            comp_status = CS_COMPLETE;
+
+	/* If scanning and missing lun then let the scsi layer skip it */
+	/* 4.24   dg 01/18/2001 */
+        if( cp->cmnd[0] == 0x12 && 
+              	cp->lun == 0 ) { /* inquiry */
+		strp = (uint8_t *)cp->request_buffer;
+        	up = (scsi_lu_t *) GET_LU_Q(ha, 0, cp->target, cp->lun);
+		if( *strp == 0x7f && up->io_cnt < 5) {
+			/* Make lun unassigned and wrong type */
+			*strp = 0x23;
+		}
+	   }
+
+        switch( comp_status ) {
+            case CS_COMPLETE:
+                host_status = DID_OK;
+		        /* v2.19.5b2 Reset port down retry on success. */
+			sp->port_down_retry_count = ha->port_down_retry_count;
+                break;
+            case CS_PORT_UNAVAILABLE:
+                /* release target data structure */
+                host_status = DID_NO_CONNECT;
+                DEBUG(sprintf(debug_buff,"scsi: Unavail port detected 0x%x-0x%x.\n",
+                sts->comp_status, sts->scsi_status); )
+                DEBUG(qla2100_print(debug_buff);)
+                break;
+            case CS_PORT_LOGGED_OUT:
+            case CS_PORT_CONFIG_CHG:
+            case CS_PORT_BUSY:
+            case CS_INCOMPLETE:
+                host_status = DID_NO_CONNECT;
+                DEBUG(sprintf(debug_buff,"scsi: Port Error detected 0x%x-0x%x.\n",
+                sts->comp_status, sts->scsi_status); )
+                DEBUG(qla2100_print(debug_buff);)
+                break;
+            case CS_RESET:
+                host_status = DID_RESET;
+                break;
+            case CS_ABORTED:
+                /* v2.19.12 - DID_ABORT does not retry the request */
+				/* if we aborted this request then abort otherwise it must be a reset */
+                   if ( (sp->flags & SRB_ABORT_PENDING) )
+                host_status = DID_ABORT;
+		   else
+                	host_status = DID_RESET;
+                break;
+            case CS_TIMEOUT:
+                  host_status = DID_ERROR;
+                  /* v2.19.8 if timeout then check to see if logout occurred*/
+                  t = SCSI_TCN_32(cp);
+		  if ( (ha->fc_db[t].flag & DEV_PUBLIC)  &&
+                       (sts->status_flags & IOCBSTAT_SF_LOGO) ) {
+				ha->fc_db[t].flag |= DEV_RELOGIN;
+                    DEBUG(printk("scsi: Timeout occurred with Logo, status flag (%x) with public device loop id (%x), attempt new recovery\n",
+                    sts->status_flags, ha->fc_db[t].loop_id);)
+					/* Suspend port */
+                    PORT_DOWN(ha,t) = ha->port_down_retry_count;
+                    ha->device_flags |= RELOGIN_NEEDED;
+                }
+                break;
+            case CS_DATA_UNDERRUN:
+                resid = sts->residual_length;
+                /* if RISC reports underrun and target does not report it
+                * then we must have a lost frame, so tell upper layer
+                * to retry it by reporting an error.
+                */
+                if( !(sts->scsi_status & SS_RESIDUAL_UNDER) ) {
+                    resid = (unsigned)(CMD_XFRLEN(cp));
+                }
+
+                if( (unsigned)(CMD_XFRLEN(cp) - resid) < cp->underflow ) {
+                        host_status = DID_ERROR;
+                        DEBUG3(sprintf(debug_buff,"scsi: Underflow detected - retrying command.\n");)
+                        DEBUG3(qla2100_print(debug_buff);)
+                } else {
+	            /* v2.19.5b2 Reset port down retry on success. */
+	            sp->port_down_retry_count = ha->port_down_retry_count;
+                    host_status = DID_OK;
+                }
+                break;
+
+            default:
+                DEBUG3(printk("scsi: Error detected 0x%x-0x%x.\n",
+                sts->comp_status, sts->scsi_status);)
+                host_status = DID_ERROR;
+                break;
+        }
+
+#if DEBUG_QLA2100_INTR
+        sprintf(debug_buff, "qla2100 ISP status: host status (%s) scsi status %x\n\r", reason[host_status], scsi_status);
+        DEBUG(qla2100_print(debug_buff);)
+#endif
+
+        LEAVE("qla2100_return_status");
+
+        return ((scsi_status & STATUS_MASK) | (host_status << 16) );
+}
+
+/*
+* qla2100_done_q_put
+*      Place SRB command on done queue.
+*
+* Input:
+*      ha           = host pointer
+*      sp           = srb pointer.
+*      done_q_first = done queue first pointer.
+*      done_q_last  = done queue last pointer.
+*/
+STATIC void
+qla2100_done_q_put(scsi_qla_host_t *ha, srb_t *sp, srb_t **done_q_first, srb_t **done_q_last) {
+    
+        unsigned long cpu_flags = 0; 
+
+#ifdef QL_DEBUG_LEVEL_3
+        ENTER("qla2100_put_done_q");
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#else
+            QLA2100_TIMER_LOCK(ha);
+#endif
+        /* Place block on done queue */
+        sp->s_next = NULL;
+        sp->s_prev = *done_q_last;
+        if( !*done_q_first )
+            *done_q_first = sp;
+        else
+            (*done_q_last)->s_next = sp;
+        *done_q_last = sp;
+
+        qla2100_stats.done_q_cnt++;
+        DEBUG(sp->state = 3;)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#else
+            QLA2100_TIMER_UNLOCK(ha);
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+        LEAVE("qla2100_put_done_q");
+#endif
+}
+
+
+/**************************************************************************
+*   qla2100_timer
+*
+* Description:
+*   One second timer 
+*
+* Context: Interrupt
+**************************************************************************/
+STATIC void
+qla2100_timer(scsi_qla_host_t *ha) {
+
+        srb_t *sp, *sp_next;
+        int  stop_timer, kick_off = 0;
+        int  cnt;
+	int t;
+        /* unsigned long cpu_flags = 0; */
+
+
+        /* ENTER("qla2100_timer"); */
+
+        /* v2.19.02 spin_lock_irqsave(&io_request_lock, cpu_flags); */
+
+        stop_timer = 0;
+
+        for( t = 0; t < ha->max_targets; t++ ) {
+            if( TGT_Q(ha, 0, t)  == NULL )
+                   continue;
+            if( TGT_Q(ha, 0, t)->down_timer > 0 )
+            	TGT_Q(ha, 0, t)->down_timer--;
+	}
+
+        /* Port Down Handler. */
+        if( ha->queue_restart_timer > 0 ) {
+            ha->queue_restart_timer--;
+#ifdef TRACECODE
+            sprintf(debug_buff,"timer: Port down time in secs %d\n",ha->queue_restart_timer);
+            qla2100_print(debug_buff);
+#endif
+            /*
+             * When a port goes DOWN, we suspend the queue and wait 1 second
+             * (one timer tick) before trying to kick off the commands again.
+             * We will do this for "port_down_retry_count" times per
+             * command before giving up on the command altogether.
+             */
+             if( !ha->queue_restart_timer ) {
+                 ha->flags.port_restart_needed = TRUE;
+                 DEBUG(qla2100_print("qla2100_timer: Port Down complete - restarting commands in the queues\n");)
+                 stop_timer++;
+             }
+         }
+            /* Loop down handler. */
+            if( ha->loop_down_timer > 0 &&
+            !ha->flags.abort_isp_active &&
+            ha->flags.online ) {
+                if( ha->loop_down_timer == LOOP_DOWN_TIME ) {
+                    DEBUG(printk("qla2100_timer: Loop Down time expired - aborting the queues before time expire\n");)
+#ifdef TRACECODE
+                    qla2100_print("qla2100_timer: Loop Down - aborting the queues before time expire\n");
+#endif
+#if 1
+                    ha->flags.abort_queue_needed = TRUE;
+#else
+                    qla2100_abort_queues(ha, TRUE);
+#endif
+                }
+
+                ha->loop_down_timer--;
+#ifdef TRACECODE
+                sprintf(debug_buff,"qla2100_timer: Loop Down - seconds remainning %d\n",ha->loop_down_timer);
+                qla2100_print(debug_buff);
+#endif
+                /* if the loop has been down for 4 minutes on QLA2100,
+                   reinit adapter */
+                if( !ha->loop_down_timer ) {
+#ifdef TRACECODE
+                    qla2100_print("qla2100_timer: Loop down for 4 mins \n");
+#endif
+                    DEBUG(printk("qla2100_timer: Loop down exceed 4 mins -restarting queues and abort ISP.\n");)
+                    ha->flags.restart_queues_needed = TRUE;
+                    if ( (ha->device_id  == QLA2100_DEVICE_ID) &&
+                          (qla2100_reinit == 1 ))
+                        ha->flags.isp_abort_needed = TRUE;
+                    stop_timer++;
+                }
+            }
+
+            /*
+            * Retry Handler -- This handler will recycle queued requests until the
+            * temporary loop down condition terminates.
+            */
+            if( !ha->flags.abort_isp_active ) {
+#ifdef TRACECODE
+                if( ha->retry_q_first )
+                    qla2100_print("qla2100_timer: Scanning for timed out commands\n");
+#endif
+                for( cnt=0, sp = ha->retry_q_first; (sp); sp =  sp_next ) {
+                    if( sp->wdg_time )
+                        sp->wdg_time--;
+                    sp_next = sp->s_next;
+                    if( sp->wdg_time ==  0 ) {
+                        kick_off++;
+                        DEBUG3(sprintf(debug_buff,"timer: CMD timeout %p,  pid %d\n",sp, sp->cmd->pid);)
+                        DEBUG3(qla2100_print(debug_buff);)
+                        cnt++;
+                        qla2100_timeout_remove(ha, sp);
+                        CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                        CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                        qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+                    }
+                }
+
+                if( cnt > 0 ) {
+                    DEBUG2(sprintf(debug_buff,"timer: found %d requests\n",cnt);)
+                    DEBUG2(qla2100_print(debug_buff);)
+                }
+            }
+
+            if( ha->done_q_first )
+                ha->flags.done_requests_needed = TRUE;
+
+            if( ha->dpc_flags & ISP_RESET_NEEDED) {
+               ha->dpc_flags &= ~ISP_RESET_NEEDED;
+               ha->flags.isp_abort_needed = TRUE;
+	    }
+
+
+#if QLA2100_LIPTEST
+            if( (ha->forceLip++) == (60*3) && qla2100_lip) {
+                /* qla2100_loop_reset(ha); */
+                qla2100_abort_isp(ha);
+                ha->forceLip = 0;
+            }
+#endif
+            /* v2.19.02 spin_unlock_irqrestore(&io_request_lock, cpu_flags); */
+
+            /* Schedule the DPC routine if needed */
+            if( ( ha->flags.isp_abort_needed ||
+            (!ha->flags.loop_resync_active && ha->flags.loop_resync_needed) ||
+            ha->flags.restart_queues_needed ||
+            ha->flags.port_restart_needed ||
+            ha->flags.done_requests_needed ||
+            (ha->device_flags & RELOGIN_NEEDED) ||
+		    (ha->dpc_flags & COMMAND_WAIT_NEEDED) ||
+            (ha->device_flags & LOGIN_RETRY_NEEDED) ||
+            kick_off > 0  ||
+            ha->flags.abort_queue_needed ) &&
+            ha->dpc_wait && !ha->dpc_active ) {  /* v2.19.4 */
+                up(ha->dpc_wait);
+            }
+
+            /* IOCTL SCSI Pass Thru Handler. */
+            if (ha->IoctlPassThru_InProgress)  {
+               if (ha->ioctl_timer) ha->ioctl_timer--;
+            }
+
+            /* IOCTL FCCT Pass Thru Handler. */
+            if (ha->IoctlPassFCCT_InProgress)  {
+               if (ha->ioctl_timer) ha->ioctl_timer--;
+            }
+
+            /* ha->flags.watchdog_enabled = FALSE; */
+            RESTART_TIMER(qla2100_timer,ha,WATCH_INTERVAL);
+
+            /* LEAVE("qla2100_timer");  */
+}
+
+/*
+* qla2100_timeout_insert
+*      Function used to insert a command block onto the
+*      watchdog timer queue.
+*
+*      Note: Must insure that sc_time is not zero
+*            before calling qla2100_timeout_insert.
+*
+* Input:
+*      ha = adapter block pointer.
+*      sp = srb pointer.
+*/
+STATIC void
+qla2100_timeout_insert(scsi_qla_host_t *ha, srb_t *sp) {
+            unsigned long cpu_flags = 0;
+            uint8_t timeoutcnt;
+
+#ifdef QL_DEBUG_LEVEL_3
+            /* ENTER("qla2100_timeout_insert"); */
+#endif
+
+            /* Compute number of time intervals */
+            timeoutcnt = (uint8_t) (CMD_TIMEOUT(sp->cmd)/(WATCH_INTERVAL * HZ));
+            if( timeoutcnt >= 3 )  /* 3 or more */
+                /* sp->wdg_time = timeoutcnt - 3;  */
+                sp->wdg_time = 3;
+            else
+                sp->wdg_time = 1;
+
+            DEBUG3(sprintf(debug_buff,"Watchdog (insert) - pid=%d, tmo=%d \n",sp->cmd->pid,sp->wdg_time);)
+            DEBUG3(qla2100_print(debug_buff);)
+
+            /* Acquire watchdoq queue specific lock */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#else
+            QLA2100_TIMER_LOCK(ha);
+#endif
+            /* Add command to queue */
+            if (ha->retry_q_first == NULL) {
+                ha->retry_q_first = sp;
+                ha->retry_q_last = sp;
+            } else {
+                ha->retry_q_last->s_next = sp;
+                ha->retry_q_last = sp;
+            }
+            sp->s_next = NULL;
+            qla2100_stats.retry_q_cnt++;
+            sp->state = 0xd0;
+
+            sp->flags |= SRB_WATCHDOG;
+            ha->flags.watchdog_enabled = TRUE;
+
+            /* Release watchdog queue specific lock */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_UNLOCK
+#else
+            QLA2100_TIMER_UNLOCK(ha);
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+            /*  LEAVE("qla2100_timeout_insert"); */
+#endif
+}
+
+/*
+* qla2100_timeout_remove
+*      Function used to remove a command block from the
+*      watchdog timer queue.
+*
+*      Note: Must insure that command is on watchdog
+*            list before calling qla2100_timeout_remove.
+*            if (sp->flags & SRB_WATCHDOG)
+*
+* Input:
+*      ha = adapter block pointer.
+*      sp = srb pointer.
+*/
+STATIC void
+qla2100_timeout_remove(scsi_qla_host_t *ha, srb_t *sp) {
+            unsigned long cpu_flags = 0;
+            srb_t *nextsp;
+
+#ifdef QL_DEBUG_LEVEL_3
+            /* ENTER("qla2100_timeout_remove"); */
+#endif
+
+            DEBUG3(sprintf(debug_buff,"Watchdog (remove) pid=%d time%d\n",sp->cmd->pid,sp->wdg_time);)
+            DEBUG3(qla2100_print(debug_buff);)
+
+            /* Acquire watchdoq queue specific lock */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#else
+            QLA2100_TIMER_LOCK(ha);
+#endif
+            /* Remove command block from watchdog queue. */
+            if (ha->retry_q_first != NULL) {
+                if (ha->retry_q_first == sp) {
+                    /* Remove from top of queue */
+                    ha->retry_q_first = sp->s_next;
+                    if (ha->retry_q_first == NULL) {
+
+                        ha->retry_q_last = NULL;
+                        ha->flags.watchdog_enabled = FALSE;
+                    }
+                } else {
+                    /* Remove from middle of queue or bottom of queue */
+                    for (nextsp = ha->retry_q_first; nextsp->s_next != NULL;
+                    nextsp = nextsp->s_next) {
+                        if (nextsp->s_next == sp) {
+                            nextsp->s_next = sp->s_next;
+                            if (nextsp->s_next == NULL)
+                                ha->retry_q_last = nextsp;
+                            break;
+                        }
+                    }
+                }
+                sp->flags &= ~SRB_WATCHDOG;
+                qla2100_stats.retry_q_cnt--;
+            }
+
+            /* Release watchdog queue specific lock */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_UNLOCK
+#else
+            QLA2100_TIMER_UNLOCK(ha);
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+            /* LEAVE("qla2100_timeout_remove"); */
+#endif
+}
+
+/*
+* qla2100_next
+*      Retrieve and process next job in the queue.
+*
+* Input:
+*      ha = adapter block pointer.
+*      q  = SCSI LU pointer.
+*      SCSI_LU_Q lock must be already obtained and no other locks.
+*
+* Output:
+*      Releases SCSI_LU_Q upon exit.
+*/
+STATIC void
+qla2100_next(scsi_qla_host_t *ha, scsi_lu_t *q) {
+            srb_t    *sp;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            unsigned long cpu_flags = 0;
+#endif
+            uint8_t  status;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_next"); 
+#endif
+
+            DRIVER_LOCK
+            COMTRACE('N')
+            while( ((sp = q->q_first) != NULL) &&   /* we have a pending cmds */
+            !(q->q_flag & QLA2100_QBUSY) &&     /* device can accept more cmds */
+            !((q->q_flag & QLA2100_QSUSP) &&    /* device queue not suspended */
+            !ha->flags.abort_isp_active &&      /* adapter abort active */
+            !ha->loop_down_timer) )             /* down timer not active */
+            {
+                /* Remove srb from SCSI LU queue. */
+                qla2100_removeq(q, sp);
+                sp->state = 0x32;
+                /* Set busy flag if reached high water mark. */
+                q->q_outcnt++;
+                if( q->q_outcnt >= ha->hiwat ) {
+                    q->q_flag |= QLA2100_QBUSY;
+                }
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+                if( ha->flags.enable_64bit_addressing )
+                    status = qla2100_64bit_start_scsi(ha, sp);
+                else
+#endif
+                    status = qla2100_32bit_start_scsi(ha, sp);
+
+                if( status ) {
+                    qla2100_putq_t(q, sp);
+
+                    if( q->q_outcnt )
+                        q->q_outcnt--;
+                    if( q->q_outcnt < ha->hiwat )
+                       q->q_flag &= ~QLA2100_QBUSY;
+                      break;
+                }
+            }
+
+            COMTRACE('n')
+            DRIVER_UNLOCK
+            /* Release SCSI LU queue specific lock */
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_next");
+#endif
+}
+#if 0
+/*******************************************************
+v4.10
+* This function has been de-implemented 
+* All DMAable memory is allocated on the spot
+* according to what kernel version is in effect.
+********************************************************  
+* qla2100_alloc_phys
+*      Function used to allocate physical memory
+*      and zero it.
+*
+* Input:
+*      size     = size in bytes.
+*      flag     = sleep flag.
+*      phy_addr = physical address pointer.
+*
+* Returns:
+*      not NULL = success
+*/
+STATIC void *
+qla2100_alloc_phys(int siz, u_long *phy_addr) {
+            void        *mem = NULL;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_alloc_phys");
+#endif
+            mem = KMALLOC(siz);
+            if( mem != NULL ) {
+                *phy_addr = VIRT_TO_BUS(mem);
+                BZERO((caddr_t)mem, siz);
+                DEBUG5(sprintf(debug_buff,"qla2100: get phys mem =0x%lx\n\r",(long)*phy_addr));
+                DEBUG5(qla2100_print(debug_buff);)
+            }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( mem == NULL )
+                qla2100_print("qla2100_alloc_phys: **** FAILED ****\n\r");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_alloc_phys");
+#endif
+            return(mem);
+}
+#endif
+
+/*
+* qla2100_putq_t
+*      Add the standard SCB job to the top of standard SCB commands.
+*
+* Input:
+*      q  = SCSI LU pointer.
+*      sp = srb pointer.
+*      SCSI_LU_Q lock must be already obtained.
+*/
+STATIC void
+qla2100_putq_t(scsi_lu_t *q, srb_t *sp) {
+            srb_t *srb_p;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            unsigned long cpu_flags = 0;
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+            /* ENTER("qla2100_putq_t"); */
+#endif
+            DRIVER_LOCK
+            DEBUG5(sprintf(debug_buff,"Adding to queue 0x%x<-(0x%x)\n\r",q,sp));
+            DEBUG5(qla2100_print(debug_buff));
+            sp->s_next = NULL;
+            q->q_incnt++;
+            sp->state = 2;
+            /* v2.19.6 */
+            if( !q->q_first || !q->q_last)  /* If queue empty */
+            {
+                sp->s_prev = NULL;
+                q->q_first = sp;
+                q->q_last = sp;
+            } else {
+                srb_p = q->q_first;
+                while( srb_p )
+                    srb_p = srb_p->s_next;
+
+                if( srb_p ) {
+                    sp->s_prev = srb_p->s_prev;
+                    if( srb_p->s_prev )
+                        srb_p->s_prev->s_next = sp;
+                    else
+                        q->q_first = sp;
+                    srb_p->s_prev = sp;
+                    sp->s_next = srb_p;
+                } else {
+                    sp->s_prev = q->q_last;
+                    q->q_last->s_next = sp;
+                    q->q_last = sp;
+                }
+            }
+
+            DRIVER_UNLOCK
+#ifdef QL_DEBUG_LEVEL_3
+            /* LEAVE("qla2100_putq_t"); */
+#endif
+}
+
+/*
+* qla2100_removeq
+*      Function used to remove a command block from the
+*      LU queue.
+*
+* Input:
+*      q  = SCSI LU pointer.
+*      sp = srb pointer.
+*      SCSI_LU_Q lock must be already obtained.
+*/
+STATIC void
+qla2100_removeq(scsi_lu_t *q, srb_t *sp) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            unsigned long cpu_flags = 0;
+#endif
+            DEBUG5(sprintf(debug_buff,"Removing from device_q (0x%x)->(0x%x)\n\r",q,sp));
+            DEBUG5(qla2100_print(debug_buff));
+            DRIVER_LOCK
+            if( sp->s_prev ) {
+                if( (sp->s_prev->s_next = sp->s_next) != NULL )
+                    sp->s_next->s_prev = sp->s_prev;
+                else
+                    q->q_last = sp->s_prev;
+            } else if( !(q->q_first = sp->s_next) )
+                q->q_last = NULL;
+            else
+                q->q_first->s_prev = NULL;
+            q->q_incnt--;
+            DRIVER_UNLOCK
+}
+
+/*
+* qla2100_callback
+*      Returns the completed SCSI command to LINUX.
+*
+* Returns:
+*      None
+*/
+static inline void qla2100_callback(scsi_qla_host_t *ha, srb_t *sp, uint8_t dec) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            unsigned long cpu_flags = 0;
+#endif
+
+            CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+            sp->flags &= ~SRB_SENT;
+            
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_LOCK
+#endif
+#if 0
+            if( dec )
+                ha->actthreads--;
+#endif
+
+	/* v2.19.14 
+  	 * Perform internal retries, if needed.
+	 */
+          switch( (CMD_RESULT(sp->cmd)>>16) ) {
+                case DID_ERROR:
+			if( sp->retry_count > 0 ) {
+				sp->retry_count--;
+            			DEBUG3(printk("qla2100: RETRY - os retry %d, drv retry %d, port retry %d\n\r",sp->cmd->retries,sp->retry_count,sp->port_down_retry_count));
+                        	CMD_RESULT(sp->cmd) = (int) DID_BUS_BUSY << 16;
+			} else {
+            	  		sp->retry_count = ha->retry_count;
+				/* all resetted commands must return with RESET */
+				if(sp->cmd->flags & IS_RESETTING ) {
+                        		CMD_RESULT(sp->cmd) = (int) DID_RESET << 16;
+            				DEBUG3(printk("qla2100: RESET cmd %p\n",sp->cmd));
+				}
+            			DEBUG3(printk("qla2100: OSerr = %p\n\r",sp->cmd));
+			}
+                    break;
+                default:
+                    break;
+            }
+
+            /* Call the mid-level driver interrupt handler */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            sti();
+            (*(sp->cmd)->scsi_done)(sp->cmd);
+            cli();
+#else
+            (*(sp->cmd)->scsi_done)(sp->cmd);
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+            DRIVER_UNLOCK
+#endif
+}
+
+/*
+* qla2100_mem_alloc
+*      Allocates adapter memory.
+*
+* Returns:
+*      0  = success.
+*      1  = failure.
+*/
+STATIC uint8_t
+qla2100_mem_alloc(scsi_qla_host_t *ha) {
+
+            uint8_t   status = 1;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_mem_alloc");
+#endif
+
+            /* 4.10 */
+            /* get consistent memory allocated for request/response rings */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+            ha->request_ring  = &ha->req[0];
+            ha->request_dma   = VIRT_TO_BUS(&ha->req[0]);
+            ha->response_ring = &ha->res[0];
+            ha->response_dma  = VIRT_TO_BUS(&ha->res[0]);
+#ifdef FC_IP_SUPPORT
+            ha->pIpBufferQueue          = &ha->asIpBuffers[0];
+            ha->ppIpBufferQueueLow      = VIRT_TO_BUS_LOW(&ha->asIpBuffers[0]);
+            ha->ppIpBufferQueueHigh     = VIRT_TO_BUS_HIGH(&ha->asIpBuffers[0]);
+#endif /* FC_IP_SUPPORT */
+#else  /* KERNEL >= 2.3.18 */ 
+            ha->request_ring   = pci_alloc_consistent(ha->pdev,
+                                 ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))),
+                                 &ha->request_dma);
+            ha->response_ring  = pci_alloc_consistent(ha->pdev,
+                                 ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))),
+                                 &ha->response_dma);
+#ifdef FC_IP_SUPPORT 
+            /* not ported yet to new pci_alloc_consistent */
+            ha->pIpBufferQueue          = &ha->asIpBuffers[0];
+            ha->ppIpBufferQueueLow      = VIRT_TO_BUS_LOW(&ha->asIpBuffers[0]);
+            ha->ppIpBufferQueueHigh     = VIRT_TO_BUS_HIGH(&ha->asIpBuffers[0]);
+#endif 
+#endif
+            /* 4.10 */
+            /* get consistent memory allocated for init control block */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+            ha->init_cb = KMALLOC(sizeof(init_cb_t));
+            if( ha->init_cb != NULL ) {
+                ha->init_cb_dma = VIRT_TO_BUS(ha->init_cb);
+                BZERO((caddr_t)ha->init_cb, sizeof(init_cb_t));
+            }
+#else
+            ha->init_cb  = pci_alloc_consistent(ha->pdev,
+                                                sizeof(init_cb_t),
+                                                &ha->init_cb_dma);
+            BZERO((caddr_t)ha->init_cb, sizeof(init_cb_t));
+#endif
+            if( ha->init_cb ) status = 0;
+
+            if( status ) 
+                printk(KERN_WARNING "qla2100_mem_alloc: **** FAILED ****\n");
+
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_mem_alloc");
+#endif
+            return(status);
+}
+
+/*
+* qla2100_mem_free
+*      Frees all adapter allocated memory.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_mem_free(scsi_qla_host_t *ha) {
+	tgt_t    *tgt;
+	uint32_t b, t;
+
+#ifdef QL_DEBUG_LEVEL_3
+	ENTER("qla2100_mem_free");
+#endif
+	if( ha ) {
+		/* Free the target queues */
+		b = 0;
+		for( t = 0; t < MAX_FIBRE_DEVICES; t++ ) {
+			tgt = TGT_Q(ha, b, t);
+			if( tgt )
+				qla2100_tgt_dealloc(ha, tgt);
+		}
+
+		/* Free host database. */
+		if (ha->phost_db != NULL) {
+			KMFREE(ha->phost_db, sizeof(fcdev_t) * MAX_HOST_COUNT);
+		}
+
+		/* 4.10 */
+		/* free consistent memory allocated for request and response rings */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+		pci_free_consistent(ha->pdev,
+		    ((REQUEST_ENTRY_CNT+1)*(sizeof(request_t))),
+		    ha->request_ring, ha->request_dma);
+
+		pci_free_consistent(ha->pdev,
+		    ((RESPONSE_ENTRY_CNT+1)*(sizeof(response_t))),
+		    ha->response_ring, ha->response_dma); 
+#endif 
+		/* free memory allocated for ioctl operations */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+		KMFREE(ha->ioctl_mem, PAGE_SIZE);
+#else
+		pci_free_consistent(ha->pdev, PAGE_SIZE,
+		    ha->ioctl_mem, ha->ioctl_mem_phys);
+#endif
+		/* free memory allocated for init_cb */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+		KMFREE(ha->init_cb, sizeof(init_cb_t));
+#else
+		pci_free_consistent(ha->pdev, sizeof(init_cb_t),
+		    ha->init_cb, ha->init_cb_dma);
+#endif
+	}
+
+#ifdef QL_DEBUG_LEVEL_3
+	LEAVE("qla2100_mem_free");
+#endif
+}
+
+/*
+* qla2100_tgt_alloc
+*      Allocates a target queue structure.
+*
+* Input:
+*      ha  = adapter block pointer.
+*
+* Returns
+*      target queue structure = success:
+*      NULL = otherwise
+*/
+static inline tgt_t *
+qla2100_tgt_alloc(scsi_qla_host_t *ha) {
+            tgt_t    *tgt;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_tgt_alloc");
+#endif
+
+            tgt = (tgt_t *)KMALLOC(sizeof(tgt_t));   /* Could Sleep here */
+            if( tgt != NULL ) {
+                BZERO(tgt,sizeof(tgt_t));
+                DEBUG(sprintf(debug_buff,"Alloc Target @ %08x \n",tgt);)
+                DEBUG(qla2100_print(debug_buff);)
+            }
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_tgt_alloc");
+#endif
+            return(tgt);
+}
+
+/*
+* qla2100_lun_alloc
+*      Allocates a logical device queue structure and lock
+*
+* Returns:
+*      SCSI LU structure pointer
+*/
+STATIC inline scsi_lu_t *
+qla2100_lun_alloc(void) {
+            scsi_lu_t *q;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_lun_alloc");
+#endif
+
+            q = (scsi_lu_t *)KMALLOC(sizeof(scsi_lu_t));  /* Sleep */
+            BZERO(q,sizeof(struct scsi_lu));
+            DEBUG(sprintf(debug_buff,"Alloc Lun @ %08x \n",q);)
+            DEBUG(qla2100_print(debug_buff);)
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_lun_alloc");
+#endif
+            return(q);
+}
+
+/*
+* qla2100_tgt_dealloc
+*      Deallocates a target and all logical device queue structures.
+*
+* Input:
+*      ha  = adapter block pointer.
+*      tgt = Target queue structure pointer
+*/
+static inline void
+qla2100_tgt_dealloc(scsi_qla_host_t *ha, tgt_t *tgt) {
+            uint32_t  l;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_tgt_dealloc");
+#endif
+
+            if( tgt != NULL ) {
+                /* Insure all LUN memory is released. */
+                for( l = 0; l <  ha->max_luns; l++ ) {
+                    if( tgt->luns[l] )
+                        qla2100_lun_dealloc(tgt->luns[l]);
+                }
+                KMFREE(tgt, sizeof(tgt_t));
+            }
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_tgt_dealloc");
+#endif
+}
+
+/*
+* qla2100_lun_dealloc
+*      Deallocates a logical unit queue structure.
+*
+* Input:
+*      q = SCSI LU structure pointer
+*/
+static inline void
+qla2100_lun_dealloc(scsi_lu_t *q) {
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_lun_dealloc");
+#endif
+            if( q != NULL ) {
+                DEBUG(sprintf(debug_buff,"Dealloc Lun @ %08x -- deleted\n",q);)
+                DEBUG(qla2100_print(debug_buff);)
+                KMFREE(q, sizeof(scsi_lu_t));
+            }
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_lun_dealloc");
+#endif
+
+}
+
+/*
+*  qla2100_abort_queue_single
+*      Abort all commands on a device queues.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void qla2100_abort_queue_single(scsi_qla_host_t *ha,uint32_t b,uint32_t t,uint32_t l,uint32_t stat) {
+            scsi_lu_t *q;
+            srb_t     *sp;
+
+            ENTER("qla2100_abort_queue_single");
+            /* dg - 08/23/99
+            * We don't want to try and abort queues that don't exists
+            * (i.e. the device is not configure on the loop )
+            */
+            if( ha->loop_down_timer > 0 ) {
+                return;
+            }
+            DEBUG5(sprintf(debug_buff,"Abort queue single %2d:%2d:%2d:%2d\n",
+            ha->host_no,b,t,l);)
+            DEBUG5(qla2100_print(debug_buff);)
+            q = (scsi_lu_t * )GET_LU_Q(ha, b, t, l);
+            while( q != NULL && (sp = q->q_first) != NULL ) {
+                /* Acquire LU queue specific lock */
+
+                qla2100_removeq(q, sp);
+
+                /* Release LU queue specific lock */
+                CMD_RESULT(sp->cmd) = stat;
+                qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+            }
+            LEAVE("qla2100_abort_queue_single");
+}
+
+/****************************************************************************/
+/*                QLogic ISP2100 Hardware Support Functions.                */
+/****************************************************************************/
+
+/*
+* qla2100_initialize_adapter
+*      Initialize board.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+uint8_t
+qla2100_initialize_adapter(scsi_qla_host_t *ha)
+{
+	uint8_t      status = QL_STATUS_SUCCESS;
+	uint8_t      isp_init = 0;
+	uint8_t      restart_risc = 0;
+	uint8_t      retry;
+
+#ifdef QL_DEBUG_LEVEL_3
+	ENTER("qla2100_initialize_adapter");
+#endif
+
+	/* Clear adapter flags. */
+	ha->forceLip = 0;
+	ha->flags.online = FALSE;
+	ha->flags.isp_abort_needed = FALSE;
+	ha->flags.disable_host_adapter = FALSE;
+	ha->flags.loop_resync_active = FALSE;
+	ha->flags.reset_active = FALSE;
+	ha->flags.abort_isp_active = FALSE;
+	ha->flags.watchdog_enabled = FALSE;
+	ha->loop_down_timer = LOOP_DOWN_TIME;
+	ha->loop_state = LOOP_DOWN;
+	ha->flags.start_timer  = FALSE;
+	ha->flags.done_requests_needed = FALSE;
+	ha->device_flags = 0;
+	ha->dpc_flags = 0;
+	ha->sns_retry_cnt = 0;
+	ha->host_db_ptr = 0;
+	ha->device_flags = 0;
+	/* 4.11 */
+	ha->flags.managment_server_logged_in = 0;
+
+	/* Allocate host database */
+	ha->phost_db = (fcdev_t *)KMALLOC(sizeof(fcdev_t) * MAX_HOST_COUNT);
+	if (ha->phost_db != NULL) {
+		BZERO(ha->phost_db, sizeof(fcdev_t) * MAX_HOST_COUNT);
+		DEBUG(sprintf(debug_buff,"Alloc Host DB success. Max Cnt=%d.",
+		    MAX_HOST_COUNT);)
+		DEBUG(qla2100_print(debug_buff);)
+	} else {
+		status = QL_STATUS_RESOURCE_ERROR;
+	}
+
+	DEBUG(printk("Configure PCI space for adapter...\n"));
+
+	if ( status == QL_STATUS_SUCCESS &&
+	    (status = qla2100_pci_config(ha)) == QL_STATUS_SUCCESS ) {
+
+		qla2100_reset_chip(ha);
+
+		/* Initialize Fibre Channel database. */
+		qla2100_init_fc_db(ha);
+
+		/* Initialize target map database. */
+		qla2100_init_tgt_map(ha);
+		if( qla2100_verbose )
+			printk(KERN_INFO
+			    "scsi(%d): Configure NVRAM parameters...\n",
+			    (int)ha->host_no);
+
+		if( ha->device_id == QLA2100_DEVICE_ID )
+			qla2100_nvram_config(ha);
+		else
+			qla2200_nvram_config(ha);
+
+		/* v2.19.12 */
+		ha->retry_count = ql2xretrycount;
+
+		if( qla2100_verbose )
+			printk(KERN_INFO
+			    "scsi(%d): Verifying loaded RISC code...\n",
+			    (int)ha->host_no);
+
+		qla2100_set_cache_line(ha);
+
+		/* If the user specified a device configuration on
+		* the command line then use it as the configuration.
+		* Otherwise, we scan for all devices.
+		*/
+		if ( ql2xdevconf ) {
+			qla2100_get_properties(ha, ql2xdevconf);
+		}
+
+		retry = 10; 
+		/*
+		* Try an configure the loop.
+		*/
+		do {
+			DEBUG(qla2100_print("qla2100_initialize_adapter: check "
+			    "if firmware needs to be loaded\n");)
+
+			/* If firmware needs to be loaded */
+			if( qla2100_isp_firmware(ha) ) {
+				if( qla2100_verbose )
+					printk(KERN_INFO
+					    "scsi(%d): Verifying chip...\n",
+					    (int)ha->host_no);
+
+				if( (status = qla2100_chip_diag(ha)) ==
+				    QL_STATUS_SUCCESS )
+					status = qla2100_setup_chip(ha);
+
+				if( status == QL_STATUS_SUCCESS )
+					DEBUG(printk("scsi(%d): Chip verified "
+					    "and RISC loaded...\n",
+					    (int)ha->host_no));
+			}
+
+			if ( status != QL_STATUS_SUCCESS )
+				continue;
+
+			status = qla2100_init_rings(ha);
+
+			if ( status != QL_STATUS_SUCCESS )
+				continue;
+
+			/* dg - 7/3/1999
+			* Wait for a successful LIP up to a maximum of 
+			* (in seconds): RISC login timeout value, RISC 
+			* retry count value, and port down retry value
+			* OR a minimum of 4 seconds OR If no cable,
+			* only 5 seconds.
+			*/
+			DEBUG(printk("scsi(%d): qla2100_init_rings OK, "
+			    "call qla2100_fw_ready...\n",
+			    (int)ha->host_no));
+			DEBUG(qla2100_print("qla2100_init_rings OK, "
+			    "call qla2100_fw_ready...\n");)
+
+			if ( qla2100_fw_ready(ha) == QL_STATUS_SUCCESS ) {
+				ha->flags.reset_marker = FALSE;
+
+				/* Go setup flash database devices
+				 * with proper Loop ID's.
+				 */
+				do {
+					ha->flags.loop_resync_needed = FALSE;
+					status = qla2100_update_fc_db(ha,
+					    FALSE);
+				} while( !ha->loop_down_timer &&
+				    ha->flags.loop_resync_needed );
+
+				/* If database was full and a device
+				 * was not configured, try and reuse
+				 * the slots.
+				 */
+
+				if( status == QL_STATUS_FATAL_ERROR ) {
+					do {
+						ha->flags.loop_resync_needed =
+						    FALSE;
+						status =
+						    qla2100_update_fc_db(ha,
+						    TRUE); 
+					} while( !ha->loop_down_timer &&
+					    ha->flags.loop_resync_needed );
+				}
+			}
+			if( ha->flags.update_config_needed ) {
+				ha->init_cb->additional_firmware_options.connection_options = ha->operating_mode;
+				restart_risc = 1;
+			}
+			isp_init = 1;
+
+		} while( restart_risc && retry-- );
+
+		if( isp_init ) {
+			ha->flags.reset_marker = FALSE;
+			qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+			ha->flags.online = TRUE;
+
+			/* Enable target response to SCSI bus. */
+			if( ha->flags.enable_target_mode )
+			    qla2100_enable_lun(ha);
+		} 
+	}
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+	if ( status != QL_STATUS_SUCCESS )
+		qla2100_print("qla2100_initialize_adapter: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+	else
+		LEAVE("qla2100_initialize_adapter");
+#endif
+
+	return(status);
+}
+
+/*
+* ISP Firmware Test
+*      Checks if present version of RISC firmware is older than
+*      driver firmware.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = firmware does not need to be loaded.
+*/
+STATIC uint8_t
+qla2100_isp_firmware(scsi_qla_host_t *ha) {
+            uint8_t  status;
+            uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2x00_isp_firmware");
+#endif
+
+            if( ha->flags.disable_risc_code_load ) {
+                /* Verify checksum of loaded RISC code. */
+                mb[0] = MBC_VERIFY_CHECKSUM;
+                mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart;
+                if( !(status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0])) ) {
+                    /* Start firmware execution. */
+                    mb[0] = MBC_EXECUTE_FIRMWARE;
+                    mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart;
+                    qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+                }
+            } else
+                status = 1;
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print(
+                "qla2100_isp_firmware: **** Return status=1; RISC Load Needed ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2x00_isp_firmware");
+#endif
+            return(status);
+}
+
+/*
+* (08/05/99)
+*
+* PCI configuration
+*      Setup device PCI configuration registers.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+STATIC uint8_t
+qla2100_pci_config(scsi_qla_host_t *ha) {
+            uint8_t      status = 1;
+            uint32_t     command;
+#if MEMORY_MAPPED_IO
+            uint32_t  page_offset, base;
+            uint32_t   mmapbase;
+#endif
+            config_reg_t *creg = 0;
+            uint16_t     buf_wd;
+
+            ENTER("qla2100_pci_config");
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+/* 4.12 */
+           /* turn on PCI master; for system BIOSes that don't turn
+              it on by default */
+            pci_set_master(ha->pdev);
+
+           if (ha->device_id == QLA2300_DEVICE_ID) {
+               pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd);
+               buf_wd = buf_wd | 
+                        PCI_COMMAND_IO |
+                        PCI_COMMAND_MEMORY | 
+                        PCI_COMMAND_MASTER | 
+                        PCI_COMMAND_INVALIDATE |
+                        PCI_COMMAND_PARITY | 
+                        PCI_COMMAND_SERR;
+               buf_wd = buf_wd & ~PCI_COMMAND_INVALIDATE;
+               pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd);
+               /* temporary: set upper 32 bits of 64 bit address to 0 */
+               buf_wd = 0;
+               pci_write_config_word(ha->pdev,PCI_BASE_ADDRESS_2, buf_wd);
+           }
+#endif
+            pci_read_config_word(ha->pdev,OFFSET(creg->revision_id), &buf_wd);
+            ha->revision = buf_wd;
+            if( !ha->iobase ) {
+                /* Get command register. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                if( pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) {
+#else
+                if( pci_read_config_word(ha->pdev,OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) {
+#endif
+                    command = buf_wd;
+                    /*
+                    * Set Bus Master Enable (bit-2), Memory Address Space Enable and
+                    * reset any error bits.
+                    */
+                    buf_wd &= ~0x7;
+#if MEMORY_MAPPED_IO
+                    DEBUG(printk("qla2100: I/O SPACE and MEMORY MAPPED IO is enabled.\n"));
+                    buf_wd |= BIT_2 + BIT_1 + BIT_0;
+#else
+                    DEBUG(printk("qla2100: I/O SPACE Enabled and MEMORY MAPPED IO is disabled.\n"));
+                    buf_wd |= BIT_2 + BIT_0;
+#endif
+                    if( pci_write_config_word(ha->pdev,OFFSET(creg->command), buf_wd) ) {
+                        printk(KERN_WARNING "qla2100: Could not write config word.\n");
+                    }
+                    /* Get expansion ROM address. */
+                    if( pci_read_config_word(ha->pdev, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL ) {
+                        /* Reset expansion ROM address decode enable. */
+                        buf_wd &= ~BIT_0;
+                        if( pci_write_config_word(ha->pdev, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL ) {
+#if MEMORY_MAPPED_IO
+                            /* Get memory mapped I/O address. */
+                            pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase);
+                            mmapbase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+                            /* Find proper memory chunk for memory map I/O reg. */
+                            base = mmapbase & PAGE_MASK;
+                            page_offset = mmapbase - base;
+                            /* Get virtual address for I/O registers. */
+                            ha->mmpbase = ioremap(base,page_offset + 256);
+                            if( ha->mmpbase ) {
+                                ha->mmpbase += page_offset;
+                                /* ha->iobase = ha->mmpbase; */
+                                status = 0;
+                            }
+#else /* MEMORY_MAPPED_IO */
+                            status = 0;
+#endif /* MEMORY_MAPPED_IO */
+                        }
+                    }
+                }
+            } else
+                status = 0;
+
+
+            LEAVE("qla2100_pci_config");
+            return(status);
+}
+#else
+STATIC uint8_t
+qla2100_pci_config(scsi_qla_host_t *ha) {
+            uint8_t      status = 1;
+            uint32_t     command;
+#if MEMORY_MAPPED_IO
+            uint32_t  page_offset, base;
+            uint32_t   mmapbase;
+#endif
+            config_reg_t *creg = 0;
+            uint16_t     buf_wd;
+
+            ENTER("qla2100_pci_config");
+
+            pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->revision_id), &buf_wd);
+            ha->revision = buf_wd;
+            if( !ha->iobase ) {
+                /* Get command register. */
+                if( pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), &buf_wd) == PCIBIOS_SUCCESSFUL ) {
+                    command = buf_wd;
+
+                    /*
+                    * Set Bus Master Enable (bit-2), Memory Address Space Enable and
+                    * reset any error bits.
+                    */
+                    buf_wd &= ~0x7;
+#if MEMORY_MAPPED_IO
+                    DEBUG(printk("qla2100: I/O SPACE and MEMORY MAPPED IO is enabled.\n"));
+                    buf_wd |= BIT_2 + BIT_1 + BIT_0;
+#else
+                    DEBUG(printk("qla2100: I/O SPACE Enabled and MEMORY MAPPED IO is disabled.\n"));
+                    buf_wd |= BIT_2 + BIT_0;
+#endif
+                    if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->command), buf_wd) ) {
+                        printk(KERN_WARNING "qla2100: Could not write config word.\n");
+                    }
+                    /* Get expansion ROM address. */
+                    if( pcibios_read_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), &buf_wd) == PCIBIOS_SUCCESSFUL ) {
+                        /* Reset expansion ROM address decode enable. */
+                        buf_wd &= ~BIT_0;
+                        if( pcibios_write_config_word(ha->pci_bus,ha->pci_device_fn, OFFSET(creg->expansion_rom), buf_wd) == PCIBIOS_SUCCESSFUL ) {
+#if MEMORY_MAPPED_IO
+                            /* Get memory mapped I/O address. */
+                            pcibios_read_config_dword(ha->pci_bus, ha->pci_device_fn,OFFSET(cfgp->mem_base_addr), &mmapbase);
+                            mmapbase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+                            /* Find proper memory chunk for memory map I/O reg. */
+                            base = mmapbase & PAGE_MASK;
+                            page_offset = mmapbase - base;
+                            /* Get virtual address for I/O registers. */
+                            ha->mmpbase = ioremap(base,page_offset + 256);
+                            if( ha->mmpbase ) {
+                                ha->mmpbase += page_offset;
+                                /* ha->iobase = ha->mmpbase; */
+                                status = 0;
+                            }
+#else /* MEMORY_MAPPED_IO */
+                            status = 0;
+#endif /* MEMORY_MAPPED_IO */
+                        }
+                    }
+                }
+            } else
+                status = 0;
+
+
+            LEAVE("qla2100_pci_config");
+            return(status);
+}
+#endif
+
+
+/*
+* qla2100_set_cache_line
+*      Sets PCI cache line parameter.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_set_cache_line(scsi_qla_host_t *ha) {
+            int          status = 0;
+            uint8_t      buf;
+            config_reg_t *creg = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_set_cache_line");
+#endif
+            /* Set the cache line. */
+            if( ha->flags.set_cache_line_size_1 ) {
+                buf = 1;
+                if( pcibios_write_config_byte(ha->pci_bus,
+                    ha->pci_device_fn,
+                    (u_long)&creg->cache_line,buf) != PCIBIOS_SUCCESSFUL )
+                    status = 1;
+            }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2100_set_cache_line: **** FAILED ****\n\r");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_set_cache_line");
+#endif
+            return(status);
+}
+
+/*
+* Chip diagnostics
+*      Test chip for proper operation.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_chip_diag(scsi_qla_host_t *ha) {
+            device_reg_t     *reg       = ha->iobase;
+            device2300_reg_t *reg2300   = ha->iobase2300;
+            uint8_t      status = 0;
+            uint16_t     data;
+            uint32_t     cnt;
+            uint16_t     mb[MAILBOX_REGISTER_COUNT];
+
+            ENTER("qla2100_chip_diag");
+#ifdef QL_DEBUG_LEVEL_3
+            qla2100_print("qla2100_chip_diag: testing device at ");
+        qla2100_output_number((u_long)&reg->flash_address, 16);
+            qla2100_print("\n");
+#endif
+
+            /* Reset ISP chip. */
+            WRT_REG_WORD(&reg->ctrl_status, ISP_RESET);
+            data = qla2100_debounce_register(&reg->ctrl_status);
+            for( cnt = 6000000 ; cnt && (data & ISP_RESET); cnt-- ) {
+                SYS_DELAY(5);
+                data = RD_REG_WORD(&reg->ctrl_status);
+            }
+
+            if( cnt ) {
+#if defined(QL_DEBUG_LEVEL_2)
+                qla2100_print("{{{qla2100_chip_diag: Reset register cleared by chip}}}\n\r");
+#endif
+                /* Reset RISC processor. */
+                WRT_REG_WORD(&reg->host_cmd, HC_RESET_RISC);
+                WRT_REG_WORD(&reg->host_cmd, HC_RELEASE_RISC);
+                data = qla2100_debounce_register(&reg->mailbox0);
+                for( cnt = 6000000; cnt && (data == MBS_BUSY); cnt-- ) {
+                    SYS_DELAY(5);
+                    data = RD_REG_WORD(&reg->mailbox0);
+                }
+
+                if( cnt ) {
+                    /* Check product ID of chip */
+#if defined(QL_DEBUG_LEVEL_2)
+                    qla2100_print("{{{qla2100_chip_diag: Checking product ID of chip}}}\n\r");
+#endif
+                if (ha->device_id != QLA2300_DEVICE_ID) {
+                    if( RD_REG_WORD(&reg->mailbox1) != PROD_ID_1 ||
+                       (RD_REG_WORD(&reg->mailbox2) != PROD_ID_2 &&
+                        RD_REG_WORD(&reg->mailbox2) != PROD_ID_2a) ||
+                        RD_REG_WORD(&reg->mailbox3) != PROD_ID_3 ||
+                        qla2100_debounce_register(&reg->mailbox4) != PROD_ID_4 ) {
+                        printk(KERN_WARNING "qla2100: [ERROR] Wrong product ID = 0x%x,0x%x,0x%x,0x%x\n",
+                        RD_REG_WORD(&reg->mailbox1),
+                        RD_REG_WORD(&reg->mailbox2),
+                        RD_REG_WORD(&reg->mailbox3),
+                        RD_REG_WORD(&reg->mailbox4));
+                        status = 1;
+                    } else {
+                        /* Now determine if we have a 2200A board */
+                        if( ( ha->device_id == QLA2200_DEVICE_ID   ||
+                              ha->device_id == QLA2200A_DEVICE_ID ) &&
+                              RD_REG_WORD(&reg->mailbox7) ==
+                              QLA2200A_RISC_ROM_VER ) {
+                                  ha->device_id = QLA2200A_DEVICE_ID;
+#if defined(QL_DEBUG_LEVEL_2)
+                                  qla2100_print("qla2100_chip_diag: Found QLA2200A chip.\n\r");
+#endif
+                        }
+                    }
+                } else {  /* check prod id of 2300 here */
+                    if( RD_REG_WORD(&reg2300->mailbox1) != PROD_ID_1 ||
+                       (RD_REG_WORD(&reg2300->mailbox2) != PROD_ID_2 &&
+                        RD_REG_WORD(&reg2300->mailbox2) != PROD_ID_2a) ||
+                        RD_REG_WORD(&reg2300->mailbox3) != PROD_ID_3 ||
+                        qla2100_debounce_register(&reg2300->mailbox4) != PROD_ID_4 ) {
+                        printk(KERN_WARNING "qla2300: [ERROR] Wrong product ID = 0x%x,0x%x,0x%x,0x%x\n",
+                        RD_REG_WORD(&reg2300->mailbox1),
+                        RD_REG_WORD(&reg2300->mailbox2),
+                        RD_REG_WORD(&reg2300->mailbox3),
+                        RD_REG_WORD(&reg2300->mailbox4));
+                        status = 1;
+                }
+                DEBUG(printk("qla2100_chip_diag: Do MBC_MAILBOX_REGISTER_TEST\n"));
+#if defined(QL_DEBUG_LEVEL_2)
+                qla2100_print("qla2100_chip_diag: Do MBC_MAILBOX_REGISTER_TEST\n\r");
+#endif
+                        /* Wrap Incoming Mailboxes Test. */
+                        mb[0] = MBC_MAILBOX_REGISTER_TEST;
+                        mb[1] = 0xAAAA;
+                        mb[2] = 0x5555;
+                        mb[3] = 0xAA55;
+                        mb[4] = 0x55AA;
+                        mb[5] = 0xA5A5;
+                        mb[6] = 0x5A5A;
+                        mb[7] = 0x2525;
+                        if( !(status = qla2100_mailbox_command(ha,
+                        BIT_7|BIT_6|BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,
+                        &mb[0])) ) {
+                            if( mb[1] != 0xAAAA || mb[2] != 0x5555 ||
+                            mb[3] != 0xAA55 || mb[4] != 0x55AA )
+                                status = 1;
+                            if( mb[5] != 0xA5A5 || mb[6] != 0x5A5A ||
+                            mb[7] != 0x2525 )
+                                status = 1;
+                            if( status ) {
+                                printk(KERN_WARNING "qla2100_chip_diag: [ERROR] *** Failed mailbox register test ***\n\r");
+                                DEBUG(qla2100_print("qla2100_chip_diag: *** Failed mailbox register test ***\n\r");)
+                            }
+                        } else {
+                                printk(KERN_WARNING "qla2100_chip_diag: [ERROR] failed mailbox send register test\n");
+                                DEBUG(qla2100_print("qla2100_chip_diag: Failed mailbox send register test\n\r");)
+                        }
+                    }
+                } else
+                    status = 1;
+            } else
+                status = 1;
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                 qla2100_print("qla2100_chip_diag: **** FAILED ****\n");
+            else qla2100_print("qla2100_chip_diag: Returning Good Status \n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_chip_diag");
+#endif
+            return(status);
+}
+
+/*
+* Setup chip
+*      Load and start RISC firmware.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_setup_chip(scsi_qla_host_t *ha) {
+            uint16_t cnt;
+            uint16_t risc_address;
+            uint16_t *risc_code_address;
+            long risc_code_size;
+            uint16_t mb[MAILBOX_REGISTER_COUNT];
+            uint8_t  status = 0;
+            int num, temp;
+#ifdef WORD_FW_LOAD
+            uint16_t *ql21_risc_code_addr01;
+            uint16_t  ql21_risc_code_length01;
+            uint8_t   dump_status;
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_setup_chip");
+#endif
+
+            /* Load RISC code. */
+            risc_address = *QLBoardTbl_fc[ha->devnum].fwstart;
+            risc_code_address = QLBoardTbl_fc[ha->devnum].fwcode;
+            risc_code_size    = (long)(*QLBoardTbl_fc[ha->devnum].fwlen & 0xffff);
+
+            DEBUG(printk("qla2100_setup_chip: Loading RISC code size =(0x%lx)\n",risc_code_size);)
+            DEBUG(qla2100_print("qla2100_setup_chip: Loading RISC code now in silent mode!\n\r");)
+            num = 0;
+            DEBUG(sprintf(debug_buff,"virt=%x phys=%x\n\r",ha->request_ring,ha->request_dma);)
+            DEBUG(qla2100_print(debug_buff);)
+            /* go into silent mode */
+            temp =  ql2x_debug_print;
+            if( ql2x_debug_print )    ql2x_debug_print = 0;
+
+            while( risc_code_size > 0 && !status ) {
+                /* for 2200A set transfer size to 128 bytes */
+                if( ha->device_id == QLA2200A_DEVICE_ID )
+                    cnt = 128 >> 1;
+                else
+                    cnt = REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT >> 1;
+                if( cnt > risc_code_size )
+                    cnt = risc_code_size;
+
+                DEBUG(sprintf(debug_buff,"qla2100_setup_chip:loading risc segment@ addr 0x%x, number of bytes 0x%x, offset 0x%x.\n\r",risc_code_address,cnt,risc_address);)
+                DEBUG(qla2100_print(debug_buff);)
+
+                BCOPY((caddr_t) risc_code_address,(caddr_t) ha->request_ring, (cnt <<1));
+
+                flush_cache_all(); /* flush written firmware to the
+                                      ha->request_ring buffer before DMA */
+
+                mb[0] = MBC_LOAD_RAM;
+                mb[1] = risc_address;
+                mb[3] = (uint16_t)(ha->request_dma & 0xffff);
+                mb[2] = (uint16_t)((ha->request_dma >> 16) & 0xffff);
+                mb[4] = cnt;
+                status = qla2100_mailbox_command(ha, BIT_4|BIT_3|BIT_2|BIT_1|BIT_0,
+                &mb[0]);
+
+                if( status ) {
+                    qla2100_dump_regs(ha->host);
+                    printk(KERN_WARNING "qla2x00: [ERROR] Failed to load segment %d of FW\n",num);
+                    DEBUG(qla2100_print("qla2100_setup_chip: Failed to load segment of FW\n");)
+                    break;
+                }
+                risc_address += cnt;
+                risc_code_size -= cnt;
+                risc_code_address += cnt;
+                num++;
+            }
+            ql2x_debug_print = temp;
+
+#ifdef WORD_FW_LOAD
+            {
+                int i;
+                uint8_t temp;
+
+                temp =  ql2x_debug_print;
+                if( ql2x_debug_print )   ql2x_debug_print = 0;
+                risc_address = *QLBoardTbl_fc[ha->devnum].fwstart;
+                ql21_risc_code_addr01  = QLBoardTbl_fc[ha->devnum].fwcode;
+                ql21_risc_code_length01= (long)(*QLBoardTbl_fc[ha->devnum].fwlen & 0xffff);
+
+                for( i = 0; i < ql21_risc_code_length01 ; i++ ) {
+
+                    mb[0] = MBC_WRITE_RAM_WORD;
+                    mb[1] = risc_address + i;
+                    mb[2] = *(ql21_risc_code_addr01 + i);
+
+                    dump_status = qla2100_mailbox_command(ha,BIT_2|BIT_1|BIT_0,
+                    &mb[0]);
+                    if( dump_status ) {
+                        printk(KERN_WARNING "qla2x00 : [ERROR] firmware load failure\n");
+                        break;
+                    }
+
+                    mb[0] = MBC_READ_RAM_WORD;
+                    mb[1] = risc_address + i;
+                    mb[2] = 0;
+
+                    dump_status = qla2100_mailbox_command(ha,BIT_2|BIT_1|BIT_0,
+                    &mb[0]);
+                    if( dump_status ) {
+                        printk(KERN_WARNING "qla2x00: [ERROR] RISC FW Read Failure\n");
+                        break;
+                    }
+                    if( mb[2] != *(ql21_risc_code_addr01 + i) )
+                        printk(KERN_WARNING "qla2x00: [ERROR] RISC FW Compare ERROR @ (0x%p)\n",
+                        (void *) (ql21_risc_code_addr01+i));
+                }
+                ql2x_debug_print = temp;
+                printk(KERN_INFO "qla2x00: RISC FW download confirmed... \n");
+            }
+#endif
+            /* Verify checksum of loaded RISC code. */
+            if( !status ) {
+                DEBUG(printk("qla2100_setup_chip: Verifying Check Sum of loaded RISC code.\n");)
+                mb[0] = MBC_VERIFY_CHECKSUM;
+                mb[1] = *QLBoardTbl_fc[ha->devnum].fwstart;
+                if( !(status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0])) ) {
+                    /* Start firmware execution. */
+                    DEBUG(qla2100_print("qla2100_setup_chip: CS Ok, Start firmware running\n\r");)
+                    mb[0] = MBC_EXECUTE_FIRMWARE;
+                    mb[1]= *QLBoardTbl_fc[ha->devnum].fwstart;
+                    status = qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+                }
+#if defined(QL_DEBUG_LEVEL_2)
+                else
+                    qla2100_print("qla2100_setup_chip: ISP FW Failed Check Sum\n");
+#endif
+            }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2100_setup_chip: **** FAILED ****\n");
+            else qla2100_print("qla2100_setup_chip: Returning Good Status\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_setup_chip");
+#endif
+            return(status);
+}
+
+/*
+* qla2100_init_rings
+*      Initializes firmware.
+*
+*      Beginning of request ring has initialization control block
+*      already built by nvram config routine.
+*
+* Input:
+*      ha                = adapter block pointer.
+*      ha->request_ring  = request ring virtual address
+*      ha->response_ring = response ring virtual address
+*      ha->request_dma   = request ring physical address
+*      ha->response_dma  = response ring physical address
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_init_rings(scsi_qla_host_t *ha) {
+            uint8_t  status;
+            uint16_t mb[MAILBOX_REGISTER_COUNT];
+            int cnt;
+            device2300_reg_t *reg2300   = ha->iobase2300;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_init_rings");
+#endif
+            /* Clear outstanding commands array. */
+            for( cnt = 0; cnt < MAX_OUTSTANDING_COMMANDS; cnt++ )
+                ha->outstanding_cmds[cnt] = 0;
+
+#ifdef RSCN
+            /* Clear RSCN queue. */
+            ha->rscn_in_ptr = 0;
+            ha->rscn_out_ptr = 0;
+#endif
+
+            /* Initialize firmware. */
+            ha->request_ring_ptr  = ha->request_ring;
+            ha->req_ring_index    = 0;
+            ha->req_q_cnt         = REQUEST_ENTRY_CNT;
+            ha->response_ring_ptr = ha->response_ring;
+            ha->rsp_ring_index    = 0;
+            mb[0] = MBC_INITIALIZE_FIRMWARE;
+            mb[3] = LSW(ha->init_cb_dma);
+            mb[2] = MSW(ha->init_cb_dma);
+            mb[4] = 0; /* set request queue in ptr   for 2100/2200 */
+            mb[5] = 0; /* set response queue out ptr for 2100/2200*/
+            mb[7] = QL21_64BITS_3RDWD(ha->init_cb_dma);
+            mb[6] = QL21_64BITS_4THWD(ha->init_cb_dma);
+
+            if (ha->device_id == QLA2300_DEVICE_ID) {
+            /* set request queue in ptr , response queue out ptr for 2300 */ 
+               WRT_REG_WORD(&reg2300->req_q_in,  0);
+               WRT_REG_WORD(&reg2300->rsp_q_out, 0);
+            }
+
+            DEBUG(qla2100_print("qla2100_init_rings: Issue MBC_INIT_FIRMWARE op\n");)
+            status = qla2100_mailbox_command(ha,
+            BIT_7|BIT_6|BIT_5|BIT_4|BIT_3|BIT_2|BIT_0,
+            &mb[0]);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2100_init_rings: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_init_rings");
+#endif
+            return(status);
+}
+
+/*
+* qla2100_fw_ready
+*      Waits for firmware ready.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_fw_ready(scsi_qla_host_t *ha) {
+        uint8_t  status = 0;
+        uint32_t cnt, cnt1;
+        uint16_t mb[MAILBOX_REGISTER_COUNT];
+        uint16_t timeout;
+
+#ifdef QL_DEBUG_LEVEL_3
+        ENTER("qla2100_fw_ready");
+#endif
+        timeout = (ha->retry_count * ha->login_timeout) + 5;
+        cnt1 = 0x350;   /* 25 secs */ 
+        /* Wait for ISP to finish LIP */
+        if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): Waiting for LIP to complete...\n", (int)ha->host->host_no);
+        if( timeout )
+          cnt = 36 * timeout;
+        else
+          cnt = 0x700;
+
+        for( ; cnt; cnt-- ) {
+            mb[0] = MBC_GET_FIRMWARE_STATE;
+            if( !(status = qla2100_mailbox_command(ha, BIT_0, &mb[0])) ) {
+                if( ha->loop_down_timer || mb[1] != FSTATE_READY ) {
+                    status = 1;
+                    /* Exit if no cable connected after 10 seconds. */
+                    if( !cnt1-- )
+                        if( mb[1] == FSTATE_CONFIG_WAIT || mb[1] == FSTATE_LOSS_OF_SYNC ) {
+
+                            break;   
+                        }
+                } else {
+                    DEBUG(printk("qla2100_fw_ready: F/W Ready - OK \n");)
+                    status = 0;   /* dg 09/15/99 */
+                    break;
+                }
+            }
+
+            if( ha->flags.online ) {
+                status = 0;   /* dg 09/15/99 */
+                break;
+            }
+
+            /* Delay for a while */
+            udelay(10);
+
+#ifdef QL_DEBUG_LEVEL_2
+/*            qla2100_print("qla2100_fw_ready: mailbox_out[1] = ");
+            qla2100_output_number((uint32_t)mb[1], 16);
+            qla2100_print("\n");*/
+#endif
+        }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+        if( status )
+            qla2100_print("qla2100_fw_ready: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+        else
+            LEAVE("qla2100_fw_ready");
+#endif
+        return(status);
+}
+
+/*
+*  qla2100_configure_hba
+*      Setup adapter context.
+*
+* Input:
+*      ha = adapter state pointer.
+*
+* Returns:
+*      0 = success
+*      1 = failed
+*
+* Context:
+*      Kernel context.
+*/
+STATIC uint8_t
+qla2100_configure_hba(scsi_qla_host_t *ha) {
+            uint8_t       rval;
+            uint16_t    mb[MAILBOX_REGISTER_COUNT];
+            uint8_t       connect_type[22];
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_configure_hba");
+#endif
+
+            /* Get host addresses. */
+            mb[0] = MBC_GET_ADAPTER_LOOP_ID;
+            rval = qla2100_mailbox_command(ha, BIT_0, &mb[0]);
+            if( !rval ) {
+                if( mb[6] == 4 ) {
+                	printk(KERN_INFO "scsi%d: Can't get topology - retrying\n",(int)ha->host_no);
+			return(1);
+                }
+                ha->loop_id = mb[1];
+
+                /* Get loop topology. */
+                if( ha->device_id == QLA2100_DEVICE_ID ) {
+                    mb[6] = 0;
+                }
+                ha->min_external_loopid = SNS_FIRST_LOOP_ID;
+                ha->operating_mode = LOOP;
+                switch( mb[6] ) {
+                    case 0:
+                        ha->current_topology = ISP_CFG_NL;
+                        strcpy((char *)&connect_type[0],"(Loop)");
+                        break;
+                    case 1:
+                        ha->current_topology = ISP_CFG_FL;
+                        strcpy((char *)&connect_type[0],"(FL_Port)");
+                        break;
+                    case 2:
+                        ha->operating_mode = P2P;
+                        ha->current_topology = ISP_CFG_N;
+                        ha->min_external_loopid = 1;  /* v2.19.5b3 */
+                        strcpy((char *)&connect_type[0],"(N_Port-to-N_Port)");
+                        break;
+                    case 3:
+                        ha->operating_mode = P2P;
+                        ha->current_topology = ISP_CFG_F;
+                        ha->min_external_loopid = 1;  /* v2.19.5b3 */
+                        strcpy((char *)&connect_type[0],"(F_Port)");
+                        break;
+                    default:
+                        ha->current_topology = ISP_CFG_NL;
+                        strcpy((char *)&connect_type[0],"(Loop)");
+                        break;
+                }
+
+                /* Save Host port and loop ID. */
+                /* Reverse byte order - TT */
+                ha->port_id[2] = LSB(mb[2]);
+                ha->port_id[1] = MSB(mb[2]);
+                ha->port_id[0] = LSB(mb[3]);
+                if (!qla2100_quiet) printk(KERN_INFO "scsi%d: Topology - %s, Host Loop address  0x%x\n",(int)ha->host_no,connect_type, ha->loop_id);
+            } else
+                printk(KERN_WARNING "qla2100_configure_hba: [ERROR] Get host loop ID  failed\n");
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( rval != 0 )
+                qla2100_print("qla2100_configure_hba: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_configure_hba");
+#endif
+            return(rval);
+}
+
+/*
+* NVRAM configuration for 2100.
+*
+* Input:
+*      ha                = adapter block pointer.
+*      ha->request_ring  = request ring virtual address
+*      ha->response_ring = response ring virtual address
+*      ha->request_dma   = request ring physical address
+*      ha->response_dma  = response ring physical address
+*
+* Output:
+*      initialization control block in response_ring
+*      host adapters parameters in host adapter block
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_nvram_config(scsi_qla_host_t *ha) {
+            uint8_t   status = 0;
+            uint16_t  cnt;
+            caddr_t   dptr1, dptr2;
+            init_cb_t *icb   = ha->init_cb;
+            nvram21_t   *nv    = (nvram21_t *)ha->request_ring;
+            uint16_t  *wptr  = (uint16_t *)ha->request_ring;
+            uint8_t   chksum = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_nvram_config");
+#endif
+
+            /* Verify valid NVRAM checksum. */
+            for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ ) {
+                *wptr = qla2100_get_nvram_word(ha, cnt);
+                chksum += (uint8_t)*wptr;
+                chksum += (uint8_t)(*wptr >> 8);
+                wptr++;
+            }
+
+#if  DEBUG_PRINT_NVRAM
+            qla2100_print(
+            "qla2100_nvram_config: Contents of NVRAM ");
+            qla2100_print("\n\r");
+            qla2100_dump_buffer((uint8_t *)ha->request_ring, sizeof(nvram21_t));
+#endif
+
+            /* Bad NVRAM data, set defaults parameters. */
+            if( chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' ||
+            nv->id[3] != ' ' || nv->nvram_version < 1 ) {
+                /* Reset NVRAM data. */
+                DEBUG(printk("Using defaults for NVRAM: \n"));
+                DEBUG(printk("checksum=0x%x, Id=%c, version=0x%x\n",chksum,nv->id[0],nv->nvram_version));
+                wptr = (uint16_t *)ha->request_ring;
+                for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ )
+                    *wptr++ = 0;
+
+                /*
+                * Set default initialization control block.
+                */
+                nv->parameter_block_version = ICB_VERSION;
+                nv->firmware_options.enable_fairness = 1;
+                nv->firmware_options.enable_fast_posting = 1;
+                nv->firmware_options.enable_full_login_on_lip = 1;
+
+                nv->frame_payload_size  = 1024;
+                nv->max_iocb_allocation = 256;
+                nv->execution_throttle  = 16;
+                nv->retry_count         = 8;
+                nv->retry_delay         = 1;
+                nv->node_name[0]        = 32;
+                nv->node_name[3]        = 224;
+                nv->node_name[4]        = 139;
+                nv->login_timeout       = 4;
+
+                /*
+                * Set default host adapter parameters
+                */
+                nv->host_p.enable_lip_full_login = 1;
+                nv->reset_delay = 5;
+                nv->port_down_retry_count = 8;
+                nv->maximum_luns_per_target = 8;
+                status = 1;
+            }
+
+            /*
+            * Copy over NVRAM RISC parameter block
+            * to initialization control block.
+            */
+            dptr1 = (caddr_t)icb;
+            dptr2 = (caddr_t)&nv->parameter_block_version;
+            cnt = (caddr_t)&nv->host_p - (caddr_t)&nv->parameter_block_version;
+            while( cnt-- )
+                *dptr1++ = *dptr2++;
+
+            /* HBA node name 0 correction */
+            for (cnt=0 ; cnt<8 ; cnt++) {
+                if (icb->node_name[cnt] != 0)
+                   break;
+            }
+            if (cnt == 8) {
+               for ( cnt= 0 ; cnt < 8 ; cnt++) 
+                    icb->node_name[cnt] = icb->port_name[cnt];
+               icb->node_name[0] = icb->node_name[0] & ~BIT_0;
+               icb->port_name[0] = icb->port_name[0] |  BIT_0;
+            }
+
+            /*
+            * Setup driver firmware options.
+            */
+#if  QL2100_TARGET_MODE_SUPPORT
+            icb->firmware_options.enable_target_mode       = 1;
+#else
+            icb->firmware_options.enable_target_mode       = 0;
+#endif
+            icb->firmware_options.disable_initiator_mode   = 0;
+            icb->firmware_options.enable_port_update_event = 1;
+            icb->firmware_options.enable_full_login_on_lip = 1;
+
+            /*
+            * Set host adapter parameters
+            */
+            ha->flags.enable_target_mode = icb->firmware_options.enable_target_mode;
+            ha->flags.disable_luns            = nv->host_p.disable_luns;
+            ha->flags.disable_risc_code_load  = nv->host_p.disable_risc_code_load;
+            ha->flags.set_cache_line_size_1   = nv->host_p.set_cache_line_size_1;
+            ha->flags.enable_64bit_addressing = nv->host_p.enable_64bit_addressing;
+
+#if BITS_PER_LONG > 32
+    /* Enable 64bit addressing for OS/System combination supporting it   */
+    /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing     */ 
+    /* but we will ignore it and use BITS_PER_LONG macro to setup for    */
+    /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */
+    ha->flags.enable_64bit_addressing = 1;
+#else
+    ha->flags.enable_64bit_addressing = 0;
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+        if (ha->flags.enable_64bit_addressing)
+           printk(KERN_INFO "[[[ qla2x00: 64 Bit PCI Addressing Enabled ]]]\n");
+
+#if BITS_PER_LONG > 32
+           /* Update our PCI device dma_mask for full 64 bit mask */
+           /* ha->pdev->dma_mask = (pci_dma_t) 0xffffffffffffffffull; */
+           ha->pdev->dma_mask = 0xffffffffffffffff;
+#endif
+#endif
+            ha->flags.enable_lip_reset        = nv->host_p.enable_lip_reset;
+            ha->flags.enable_lip_full_login   = nv->host_p.enable_lip_full_login;
+            ha->flags.enable_target_reset     = nv->host_p.enable_target_reset;
+            ha->flags.enable_flash_db_update  = nv->host_p.enable_database_storage;
+
+            /* new for IOCTL support of APIs */
+            ha->node_name[0] = icb->node_name[0];
+            ha->node_name[1] = icb->node_name[1];
+            ha->node_name[2] = icb->node_name[2];
+            ha->node_name[3] = icb->node_name[3];
+            ha->node_name[4] = icb->node_name[4];
+            ha->node_name[5] = icb->node_name[5];
+            ha->node_name[6] = icb->node_name[6];
+            ha->node_name[7] = icb->node_name[7];
+            ha->nvram_version = nv->nvram_version;
+
+            /* empty data for QLA2100s OEM stuff */
+            ha->oem_id          = 0;
+            ha->oem_spare0      = 0;
+            for ( cnt= 0 ; cnt < 8 ; cnt++) {
+                 ha->oem_string[cnt] = 0; 
+                 ha->oem_part[cnt]   = 0; 
+                 ha->oem_fru[cnt]    = 0; 
+                 ha->oem_ec[cnt]     = 0; 
+            }
+
+            ha->hiwat                 = icb->iocb_allocation;
+            ha->execution_throttle  = nv->execution_throttle;
+
+            ha->retry_count           = nv->retry_count;
+            ha->login_timeout         = nv->login_timeout;
+            /* Set minimum login_timeout to 4 seconds. */
+            if( ha->login_timeout < 4 )
+                ha->login_timeout = 4;
+            ha->port_down_retry_count = nv->port_down_retry_count;
+            ha->minimum_timeout       = (ha->login_timeout * ha->retry_count)
+            + ha->port_down_retry_count;
+            ha->loop_reset_delay      = nv->reset_delay;
+            /* Will get the value from nvram. */
+            ha->loop_down_timeout     = LOOP_DOWN_TIMEOUT;
+            ha->loop_down_abort_time  = LOOP_DOWN_TIME - ha->loop_down_timeout;
+
+            /* save HBA serial number */
+            ha->serial0 = nv->node_name[5];
+            ha->serial1 = nv->node_name[6];
+            ha->serial2 = nv->node_name[7];
+
+#if  USE_BIOS_MAX_LUNS
+            if( !nv->maximum_luns_per_target )
+                ha->max_luns = MAX_LUNS-1;
+            else
+                ha->max_luns = nv->maximum_luns_per_target;
+#else
+            ha->max_luns = MAX_LUNS-1;
+#endif
+
+            /*
+            * Setup ring parameters in initialization control block
+            */
+            icb->request_q_outpointer  = 0;
+            icb->response_q_inpointer  = 0;
+            icb->request_q_length      = REQUEST_ENTRY_CNT;
+            icb->response_q_length     = RESPONSE_ENTRY_CNT;
+            icb->request_q_address[0]  = LS_64BITS(ha->request_dma);
+            icb->request_q_address[1]  = MS_64BITS(ha->request_dma);
+            icb->response_q_address[0] = LS_64BITS(ha->response_dma);
+            icb->response_q_address[1] = MS_64BITS(ha->response_dma);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2100_nvram_config: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_nvram_config");
+#endif
+            return(status);
+}
+
+/*
+* NVRAM configuration for the 2200.
+*
+* Input:
+*      ha                = adapter block pointer.
+*      ha->request_ring  = request ring virtual address
+*      ha->response_ring = response ring virtual address
+*      ha->request_dma   = request ring physical address
+*      ha->response_dma  = response ring physical address
+*
+* Output:
+*      initialization control block in response_ring
+*      host adapters parameters in host adapter block
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2200_nvram_config(scsi_qla_host_t *ha) {
+            uint8_t   status = 0;
+            uint16_t  cnt;
+            caddr_t   dptr1, dptr2;
+            init_cb_t *icb   = ha->init_cb;
+            nvram22_t   *nv    = (nvram22_t *)ha->request_ring;
+            uint16_t  *wptr  = (uint16_t *)ha->request_ring;
+            uint8_t   chksum = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2200/2300_nvram_config");
+#endif
+
+            if( !ha->flags.nvram_config_done ) {
+
+                /* Verify valid NVRAM checksum. */
+                for( cnt = 0; cnt < sizeof(nvram22_t)/2; cnt++ ) {
+                    *wptr = qla2100_get_nvram_word(ha, cnt);
+                    chksum += (uint8_t)*wptr;
+                    chksum += (uint8_t)(*wptr >> 8);
+                    wptr++;
+                }
+
+#if  DEBUG_PRINT_NVRAM
+                qla2100_print(
+                "qla2200_nvram_config: Contents of NVRAM ");
+                qla2100_print("\n\r");
+                qla2100_dump_buffer((uint8_t *)ha->request_ring, sizeof(nvram22_t));
+#endif
+
+                /* Bad NVRAM data, set defaults parameters. */
+                if( chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' ||
+                nv->id[3] != ' ' || nv->nvram_version < 1 ) {
+                    /* Reset NVRAM data. */
+                    DEBUG(printk("Using defaults for 2200/2300 NVRAM: \n"));
+                    DEBUG(printk("checksum=0x%x, Id0=%c Id1=%c Id2=%x, version=0x%x\n",chksum,nv->id[0],nv->id[1],nv->id[2],nv->nvram_version));
+                    wptr = (uint16_t *)nv;
+                    for( cnt = 0; cnt < sizeof(nvram21_t)/2; cnt++ )
+                        *wptr++ = 0;
+
+                    /*
+                    * Set default initialization control block.
+                    */
+                    nv->parameter_block_version = ICB_VERSION;
+                    nv->firmware_options.enable_fairness = 1;
+                    nv->firmware_options.enable_fast_posting = 1;
+                    nv->firmware_options.enable_full_login_on_lip = 1;
+                    nv->firmware_options.enable_name_change = 1;
+                    nv->firmware_options.expanded_ifwcb = 1;
+
+                    nv->frame_payload_size  = 1024;
+                    nv->max_iocb_allocation = 256;
+                    nv->execution_throttle  = 16;
+                    nv->retry_count         = 8;
+                    nv->retry_delay         = 1;
+                    nv->port_name[0]        = 32;
+                    nv->port_name[3]        = 224;
+                    nv->port_name[4]        = 139;
+                    nv->login_timeout       = 4;
+                    nv->additional_firmware_options.connection_options = P2P_LOOP;
+                    /*
+                    * Set default host adapter parameters
+                    */
+                    nv->host_p.enable_lip_full_login = 1;
+                    nv->reset_delay = 5;
+                    nv->port_down_retry_count = 8;
+                    nv->maximum_luns_per_target = 8;
+                    status = 1;
+                }
+
+                /* Reset icb data */
+                BZERO((caddr_t)icb, sizeof(init_cb_t));
+                /*
+                * Copy over NVRAM RISC parameter block
+                * to initialization control block.
+                */
+                dptr1 = (caddr_t)icb;
+                dptr2 = (caddr_t)&nv->parameter_block_version;
+                cnt = (caddr_t)&nv->additional_firmware_options - (caddr_t)&nv->parameter_block_version;
+                while( cnt-- )
+                    *dptr1++ = *dptr2++;
+
+                dptr1 += (caddr_t)&icb->additional_firmware_options - (caddr_t)&icb->request_q_outpointer;
+                cnt = (caddr_t)&nv->host_p - (caddr_t)&nv->additional_firmware_options;
+                while( cnt-- )
+                    *dptr1++ = *dptr2++;
+
+                /* HBA node name 0 correction */
+                for (cnt=0 ; cnt<8 ; cnt++) {
+                    if (icb->node_name[cnt] != 0)
+                       break;
+                }
+                if (cnt == 8) {
+                   for ( cnt= 0 ; cnt < 8 ; cnt++) 
+                       icb->node_name[cnt] = icb->port_name[cnt];
+                   icb->node_name[0] = icb->node_name[0] & ~BIT_0;
+                   icb->port_name[0] = icb->port_name[0] |  BIT_0;
+                }
+
+                /*
+                * Setup driver firmware options.
+                */
+                icb->firmware_options.enable_full_duplex       = 0;
+#if  QL2100_TARGET_MODE_SUPPORT
+                icb->firmware_options.enable_target_mode       = 1;
+#else
+                icb->firmware_options.enable_target_mode       = 0;
+#endif
+                icb->firmware_options.disable_initiator_mode   = 0;
+                icb->firmware_options.enable_port_update_event = 1;
+                icb->firmware_options.enable_full_login_on_lip = 1;
+#if USE_TP_FW
+                icb->firmware_options.enable_name_change = 1;
+                icb->firmware_options.expanded_ifwcb = 1;
+#endif
+                /*
+                * Set host adapter parameters
+                */
+                ha->flags.enable_target_mode = icb->firmware_options.enable_target_mode;
+                ha->flags.disable_luns            = nv->host_p.disable_luns;
+                ha->flags.disable_risc_code_load  = nv->host_p.disable_risc_code_load;
+                ha->flags.set_cache_line_size_1   = nv->host_p.set_cache_line_size_1;
+                ha->flags.enable_64bit_addressing = nv->host_p.enable_64bit_addressing;
+
+#if BITS_PER_LONG > 32
+    /* Enable 64bit addressing for OS/System combination supporting it   */
+    /* actual NVRAM bit is: nv->cntr_flags_1.enable_64bit_addressing     */ 
+    /* but we will ignore it and use BITS_PER_LONG macro to setup for    */
+    /* 64 or 32 bit access of host memory in all x86/ia-64/Alpha systems */
+    ha->flags.enable_64bit_addressing = 1;
+#else
+    ha->flags.enable_64bit_addressing = 0;
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+        if (ha->flags.enable_64bit_addressing)
+           printk(KERN_INFO "[[[ qla2x00: 64 Bit PCI Addressing Enabled ]]]\n");
+
+#if BITS_PER_LONG > 32
+           /* Update our PCI device dma_mask for full 64 bit mask */
+           ha->pdev->dma_mask = 0xffffffffffffffff;
+#endif
+#endif
+                ha->flags.enable_lip_reset        = nv->host_p.enable_lip_reset;
+                ha->flags.enable_lip_full_login   = nv->host_p.enable_lip_full_login;
+                ha->flags.enable_target_reset     = nv->host_p.enable_target_reset;
+                ha->flags.enable_flash_db_update  = nv->host_p.enable_database_storage;
+                ha->operating_mode = icb->additional_firmware_options.connection_options;
+
+            /* new for IOCTL support of APIs */
+            ha->node_name[0] = icb->node_name[0];
+            ha->node_name[1] = icb->node_name[1];
+            ha->node_name[2] = icb->node_name[2];
+            ha->node_name[3] = icb->node_name[3];
+            ha->node_name[4] = icb->node_name[4];
+            ha->node_name[5] = icb->node_name[5];
+            ha->node_name[6] = icb->node_name[6];
+            ha->node_name[7] = icb->node_name[7];
+            ha->nvram_version = nv->nvram_version;
+ 
+
+                ha->hiwat                 = icb->iocb_allocation;
+                ha->execution_throttle  = nv->execution_throttle;
+
+                ha->retry_count           = nv->retry_count;
+                ha->login_timeout         = nv->login_timeout;
+                /* Set minimum login_timeout to 4 seconds. */
+                if( ha->login_timeout < 4 )
+                    ha->login_timeout = 4;
+                ha->port_down_retry_count = nv->port_down_retry_count;
+                ha->minimum_timeout       = (ha->login_timeout * ha->retry_count)
+                + ha->port_down_retry_count;
+                ha->loop_reset_delay      = nv->reset_delay;
+                /* Will get the value from nvram. */
+                ha->loop_down_timeout     = LOOP_DOWN_TIMEOUT;
+                ha->loop_down_abort_time  = LOOP_DOWN_TIME - ha->loop_down_timeout;
+
+                /* save HBA serial number */
+                ha->serial0 = nv->port_name[5];
+                ha->serial1 = nv->port_name[6];
+                ha->serial2 = nv->port_name[7];
+
+                /* save OEM related items for QLA2200s and QLA2300s */
+                ha->oem_id     = nv->oem_id;
+                ha->oem_spare0 = nv->oem_spare0;
+
+                for ( cnt= 2 ; cnt < 8 ; cnt++ ) 
+                  ha->oem_string[cnt] = nv->oem_string[cnt]; 
+
+                for ( cnt= 0 ; cnt < 8 ; cnt++ ) {
+                  ha->oem_part[cnt]   = nv->oem_part[cnt]; 
+                  ha->oem_fru[cnt]    = nv->oem_fru[cnt]; 
+                  ha->oem_ec[cnt]     = nv->oem_ec[cnt]; 
+                }
+
+#ifdef FC_IP_SUPPORT
+                for (cnt = 0; cnt < 8; cnt++)
+                    ha->acPortName[cnt] = nv->port_name[cnt];
+#endif
+
+#if  USE_BIOS_MAX_LUNS
+                if( !nv->maximum_luns_per_target )
+                    ha->max_luns = MAX_LUNS;
+                else if( nv->maximum_luns_per_target < MAX_LUNS )
+                    ha->max_luns = nv->maximum_luns_per_target;
+                else
+                    ha->max_luns = MAX_LUNS;
+#else
+                ha->max_luns = MAX_LUNS;
+#endif
+
+                /*
+                * Setup ring parameters in initialization control block
+                */
+                icb->request_q_outpointer  = 0;
+                icb->response_q_inpointer  = 0;
+                icb->request_q_length      = REQUEST_ENTRY_CNT;
+                icb->response_q_length     = RESPONSE_ENTRY_CNT;
+                icb->request_q_address[0]  = LS_64BITS(ha->request_dma);
+                icb->request_q_address[1]  = MS_64BITS(ha->request_dma);
+                icb->response_q_address[0] = LS_64BITS(ha->response_dma);
+                icb->response_q_address[1] = MS_64BITS(ha->response_dma);
+
+                icb->lun_enables = 0;
+                icb->command_resource_count = 0;
+                icb->immediate_notify_resource_count = 0;
+                icb->timeout = 0;
+                icb->reserved_2 = 0;
+
+                ha->flags.nvram_config_done = 1;
+            }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2200_nvram_config: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2200_nvram_config");
+#endif
+            return(status);
+}
+
+/*
+* Get NVRAM data word
+*      Calculates word position in NVRAM and calls request routine to
+*      get the word from NVRAM.
+*
+* Input:
+*      ha      = adapter block pointer.
+*      address = NVRAM word address.
+*
+* Returns:
+*      data word.
+*/
+STATIC uint16_t
+qla2100_get_nvram_word(scsi_qla_host_t *ha, uint32_t address) {
+            uint32_t nv_cmd;
+            uint16_t data;
+
+#ifdef QL_DEBUG_ROUTINES
+            uint8_t  saved_print_status = ql2x_debug_print;
+#endif
+#ifdef QL_DEBUG_LEVEL_4
+            qla2100_print("qla2100_get_nvram_word: entered\n");
+#endif
+
+            nv_cmd = address << 16;
+            nv_cmd |= NV_READ_OP;
+
+#ifdef QL_DEBUG_ROUTINES
+            ql2x_debug_print = FALSE;
+#endif
+            data = qla2100_nvram_request(ha, nv_cmd);
+#ifdef QL_DEBUG_ROUTINES
+            ql2x_debug_print = saved_print_status;
+#endif
+
+#ifdef QL_DEBUG_LEVEL_4
+            qla2100_print("qla2100_get_nvram_word: exiting normally NVRAM data = ");
+        qla2100_output_number((u_long)data, 16);
+            qla2100_print("\n");
+#endif
+            return(data);
+}
+
+/*
+* NVRAM request
+*      Sends read command to NVRAM and gets data from NVRAM.
+*
+* Input:
+*      ha     = adapter block pointer.
+*      nv_cmd = Bit 26     = start bit
+*               Bit 25, 24 = opcode
+*               Bit 23-16  = address
+*               Bit 15-0   = write data
+*
+* Returns:
+*      data word.
+*/
+STATIC uint16_t
+qla2100_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) {
+            uint8_t      cnt;
+            device_reg_t *reg = ha->iobase;
+            uint16_t     data = 0;
+            uint16_t     reg_data;
+
+            /* Send command to NVRAM. */
+
+            nv_cmd <<= 5;
+            for( cnt = 0; cnt < 11; cnt++ ) {
+                if( nv_cmd & BIT_31 )
+                    qla2100_nv_write(ha, NV_DATA_OUT);
+                else
+                    qla2100_nv_write(ha, 0);
+                nv_cmd <<= 1;
+            }
+
+            /* Read data from NVRAM. */
+
+            for( cnt = 0; cnt < 16; cnt++ ) {
+                WRT_REG_WORD(&reg->nvram, NV_SELECT+NV_CLOCK);
+                /* qla2100_nv_delay(ha); */
+                NVRAM_DELAY();
+                data <<= 1;
+                reg_data = RD_REG_WORD(&reg->nvram);
+                if( reg_data & NV_DATA_IN )
+                    data |= BIT_0;
+                WRT_REG_WORD(&reg->nvram, NV_SELECT);
+                /* qla2100_nv_delay(ha); */
+                NVRAM_DELAY();
+            }
+
+            /* Deselect chip. */
+
+            WRT_REG_WORD(&reg->nvram, NV_DESELECT);
+            /* qla2100_nv_delay(ha); */
+            NVRAM_DELAY();
+
+            return(data);
+}
+
+STATIC void
+qla2100_nv_write(scsi_qla_host_t *ha, uint16_t data) {
+            device_reg_t *reg = ha->iobase;
+
+            WRT_REG_WORD(&reg->nvram, data | NV_SELECT);
+            NVRAM_DELAY();
+            /* qla2100_nv_delay(ha); */
+            WRT_REG_WORD(&reg->nvram, data | NV_SELECT | NV_CLOCK);
+            /* qla2100_nv_delay(ha); */
+            NVRAM_DELAY();
+            WRT_REG_WORD(&reg->nvram, data | NV_SELECT);
+            /* qla2100_nv_delay(ha); */
+            NVRAM_DELAY();
+}
+
+STATIC void
+qla2100_nv_delay(void) {
+            SYS_DELAY(NV_DELAY_COUNT);
+}
+
+
+/*
+* Mailbox Command
+*      Issue mailbox command and waits for completion.
+*
+* Input:
+*      ha = adapter block pointer.
+*      mr = mailbox registers to load.
+*      mb = data pointer for mailbox registers.
+*
+* Output:
+*      mb[MAILBOX_REGISTER_COUNT] = returned mailbox data.
+*
+* Returns:
+*      0 = success
+*      1 = failed    (mbox status != 0x4000)
+*/
+STATIC uint8_t
+qla2100_mailbox_command(scsi_qla_host_t *ha, uint32_t mr, uint16_t *mb) {
+            device_reg_t     *reg       = ha->iobase;
+            device2300_reg_t *reg2300   = ha->iobase2300;
+            uint8_t      status = 0;
+            uint32_t     cnt;
+            uint16_t     *optr, *iptr;
+            uint16_t     data, command, intreq;
+            srb_t        *done_q_first = 0;
+            srb_t        *done_q_last = 0;
+            uint32_t     longdata = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_mailbox_command");
+#endif
+
+            /* Acquire interrupt specific lock */
+            QLA2100_INTR_LOCK(ha);
+
+            DRIVER_LOCK
+            ha->flags.mbox_busy = TRUE;
+
+#ifdef QL_DEBUG_LEVEL_5
+            sprintf(debug_buff,"scsi%d ",(int)ha->host_no);
+            qla2100_print(debug_buff);
+            qla2100_print("qla2100_mailbox_command: [[Start]] mbox_out[0] = ");
+            qla2100_output_number((u_long)*mb, 16);
+            qla2100_print("\n");  
+#endif
+            /* Load mailbox registers. */
+            if (ha->device_id != QLA2300_DEVICE_ID) 
+                optr = (uint16_t *)&reg->mailbox0;
+            else
+                optr = (uint16_t *)&reg2300->mailbox0;
+
+#ifdef QL_DEBUG_LEVEL_5
+            qla2100_print(
+            "qla2100_mailbox_command: Load MB word registers (displayed in bytes) = \n");
+            qla2100_dump_buffer((uint8_t *)mb, 16);
+            qla2100_print("\n");
+            qla2100_dump_buffer(((uint8_t *)mb + 0x10), 16);
+            qla2100_print("\n");
+            qla2100_dump_buffer(((uint8_t *)mb + 0x20), 8);
+            qla2100_print("\n");
+            qla2100_print("qla2100_mailbox_command: I/O address = ");
+            qla2100_output_number((u_long)optr, 16);
+            qla2100_print("\n");
+#endif
+            iptr = mb;
+            command = *(mb);
+            for( cnt = 0; cnt < MAILBOX_REGISTER_COUNT; cnt++ ) {
+                if( mr & BIT_0 ) {
+                    WRT_REG_WORD(optr, (*iptr));
+                }
+                mr >>= 1;
+                optr++;
+                iptr++;
+            }
+#ifdef QL_DEBUG_LEVEL_5
+            qla2100_dump_regs(ha->host);
+#endif
+
+            /* Issue set host interrupt command. */
+            ha->flags.mbox_int = FALSE;
+            WRT_REG_WORD(&reg->host_cmd, HC_SET_HOST_INT);
+
+            /* Wait for 30 seconds for command to finish.  */
+            if (ha->device_id == QLA2300_DEVICE_ID) 
+               data = qla2100_debounce_register((uint16_t *)&reg2300->host_status);
+            else data = qla2100_debounce_register(&reg->istatus);
+
+            cnt = 0x100000*2;   /* 22 secs */
+
+            for( ; cnt > 0 && !ha->flags.mbox_int; cnt-- ) {
+                /* Check for pending interrupts. */
+                if (ha->device_id == QLA2300_DEVICE_ID) {
+                   switch (*mb) { 
+                     case MBC_LOAD_RAM:
+                     case MBC_EXECUTE_FIRMWARE:
+                     case MBC_MAILBOX_REGISTER_TEST:
+                     case MBC_VERIFY_CHECKSUM:
+                     case MBC_ABOUT_FIRMWARE:
+                       /* handle ROM commands the old way */
+                       data     = RD_REG_WORD(&reg->istatus);
+                       intreq   = data & RISC_INT;
+                       break;
+                     default:
+                       /* handle non-ROM commands the new way */
+                       data     = RD_REG_WORD(&reg->istatus);
+                       longdata = RD_REG_DWORD(&reg2300->host_status);
+                       intreq   = longdata & RISC_2300_INT;
+                       break;
+                   }
+                } else {
+                   /* QLA2100 or QLA2200 */
+                   data     = RD_REG_WORD(&reg->istatus);
+                   intreq   = data & RISC_INT;
+                }
+                if ( intreq != 0 ) {
+                   qla2100_isr(ha,
+                              (srb_t **)&done_q_first,
+                              (srb_t **)&done_q_last); 
+                	/* udelay(10); */
+                }
+                udelay(10); /* v4.27 */
+            } /* for */
+
+            /* Check for mailbox command timeout. */
+            if( !cnt ) {
+#ifdef QL_DEBUG_LEVEL_2
+                qla2100_print(
+                "qla2100_mailbox_command: **** MB Command Timeout for cmd = ");
+                qla2100_output_number((u_long)mb[0], 16);
+                qla2100_print(" ****\n");
+                qla2100_print(
+                "qla2100_mailbox_command: **** icontrol = ");
+                qla2100_output_number(RD_REG_WORD(&reg->ictrl), 16);
+                qla2100_print(" ****\n");
+                qla2100_print(
+                "qla2100_mailbox_command: **** istatus = ");
+                qla2100_output_number((u_long)data, 16);
+                qla2100_print(" ****\n");
+                qla2100_print(
+                "qla2100_mailbox_command: **** chip mailbox[0] = ");
+                qla2100_output_number((u_long)RD_REG_WORD(optr), 16);
+                qla2100_print(" ****\n");
+                qla2100_dump_regs(ha->host);
+#endif
+                ha->flags.isp_abort_needed = TRUE;
+                qla2100_stats.mboxtout++;
+                status = 1;
+            } else if( ha->mailbox_out[0] != MBS_CMD_CMP ) {
+                qla2100_stats.mboxerr++;
+                status = 1;
+            }
+
+            /* Load return mailbox registers. */
+            optr = mb;
+            iptr = (uint16_t *)&ha->mailbox_out[0];
+
+            mr = MAILBOX_REGISTER_COUNT;
+            while( mr-- )
+                *optr++ = *iptr++;
+
+            /* Go check for any response interrupts pending. */
+            ha->flags.mbox_busy = FALSE;
+
+            qla2100_isr(ha,(srb_t **)&done_q_first,(srb_t **)&done_q_last); 
+
+            /* Release interrupt specific lock */
+            QLA2100_INTR_UNLOCK(ha);
+            DRIVER_UNLOCK
+
+            if( ha->flags.isp_abort_needed )
+                qla2100_abort_isp(ha);
+
+            if( ha->flags.reset_marker )
+                qla2100_rst_aen(ha);
+            if( ha->flags.update_config_needed )
+                qla2100_update_config(ha);
+            if( ha->flags.loop_resync_needed )
+                qla2100_loop_resync(ha);
+
+            if( done_q_first )
+                qla2100_done(ha, (srb_t **)&done_q_first, (srb_t **)&done_q_last);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+        if( status ) {
+            qla2100_print("qla2100_mailbox_command: **** FAILED, mailbox0 = ");
+            qla2100_output_number((u_long)mb[0], 16);
+            qla2100_print(" ****\n");
+        } else {
+/* DEBUG(qla2100_print("qla2100_mbc: Completed OK operation=");)
+DEBUG(qla2100_output_number((u_long)command, 16);)
+DEBUG(qla2100_print(" \n");)
+DEBUG(qla2100_print("qla2100_mbc: mailbox[1]=");)
+DEBUG(qla2100_output_number((u_long)mb[1], 16);)
+DEBUG(qla2100_print(" \n");)
+DEBUG(qla2100_print("mbc: +++ rsp_q_in= ");)
+DEBUG(qla2100_output_number(RD_REG_WORD(&ha->iobase2300->rsp_q_in), 16);)
+DEBUG(qla2100_print(" +++ \n");)
+DEBUG(qla2100_print("mbc: +++ rsp_q_out= ");)
+DEBUG(qla2100_output_number(RD_REG_WORD(&ha->iobase2300->rsp_q_out), 16);)
+DEBUG(qla2100_print(" +++ \n\n");)
+DEBUG(printk("qla2100_mbc: Completed OK operation=%x\n\n",command);) */
+        }
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_mailbox_command");
+#endif
+            return(status);
+}
+
+
+        /*
+        * qla2100_poll
+        *      Polls ISP for interrupts.
+        *
+        * Input:
+        *      ha = adapter block pointer.
+        */
+STATIC void
+qla2100_poll(scsi_qla_host_t *ha) {
+            device_reg_t     *reg       = ha->iobase;
+            device2300_reg_t *reg2300   = ha->iobase2300;
+            uint16_t     data;
+            srb_t        *done_q_first = 0;
+            srb_t        *done_q_last = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_poll");
+#endif
+
+            /* Acquire interrupt specific lock */
+            QLA2100_INTR_LOCK(ha);
+
+            /* Check for pending interrupts. */
+            if (ha->device_id == QLA2300_DEVICE_ID) 
+              data = qla2100_debounce_register((uint16_t *)&reg2300->host_status) &
+                     RISC_2300_INT;
+            else data = qla2100_debounce_register(&reg->istatus) & 
+                         RISC_INT;
+
+            /* Check for pending interrupts. */
+            if( data ) {
+                DEBUG(qla2100_print("qla2100_poll: Calling isr\n");)
+                qla2100_isr(ha, 
+                           (srb_t **)&done_q_first,
+                           (srb_t **)&done_q_last);
+            }
+
+            /* Release interrupt specific lock */
+            QLA2100_INTR_UNLOCK(ha);
+
+            if( !ha->flags.mbox_busy ) {
+                if( ha->flags.isp_abort_needed )
+                    qla2100_abort_isp(ha);
+                if( ha->flags.reset_marker )
+                    qla2100_rst_aen(ha);
+                if( ha->flags.update_config_needed )
+                    qla2100_update_config(ha);
+                if( ha->flags.loop_resync_needed )
+                    qla2100_loop_resync(ha);
+            }
+
+            if( done_q_first )
+                qla2100_done(ha, (srb_t **)&done_q_first, (srb_t **)&done_q_last);
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_poll");
+#endif
+}
+        
+/*
+* qla2100_find_host
+*      This routine searches the host adapter database 
+*      and return either TRUE or FALSE.
+*
+* Input:
+*      ha = adapter block pointer.
+*      device = device data pointer.
+*
+* Returns:
+*    TRUE - found
+*/
+STATIC uint8_t
+qla2100_find_host(scsi_qla_host_t *ha, device_data_t *device) {
+	fcdev_t  *pdb;
+	uint16_t cnt;
+ 
+	pdb = ha->phost_db;
+	for (cnt = 0; cnt < ha->host_db_ptr; cnt++) {
+		/* if nodename/portname in database */
+#if  USE_PORTNAME
+		if (BCMP(device->wwn, pdb[cnt].name, 8) == 0) {
+#else
+		if (BCMP(device->name, pdb[cnt].name, 8) == 0) {
+#endif
+			return TRUE;
+		}
+	}
+	return FALSE;
+}
+        
+/*
+* qla2100_update_host_data
+*      This routine updates the host device database 
+*
+* Input:
+*      ha = adapter block pointer.
+*      device = device data pointer.
+*
+* Returns:
+*      0 = success, if device found or added to database.
+*      1 = error
+*      2 = database was full and device was not configured.
+*/
+STATIC uint8_t
+qla2100_update_host_data(scsi_qla_host_t *ha, device_data_t *device,
+    uint8_t enable_slot_reuse)
+{
+	fcdev_t  *pdb;
+	uint8_t  status = 0;
+	uint8_t index;
+
+#ifdef QL_DEBUG_LEVEL_3
+	ENTER("qla2100_update_host");
+#endif
+ 
+	pdb = ha->phost_db;
+	index = ha->host_db_ptr;
+	if (index != MAX_HOST_COUNT) {
+		index++;
+#if  USE_PORTNAME
+		BCOPY(device->wwn, pdb[index].name, 8);
+#else
+		BCOPY(device->name, pdb[index].name, 8);
+#endif
+	} else if ( enable_slot_reuse ) {
+		index = 0;
+		printk(KERN_INFO "qla2100_update_host: Host table Full."
+		    " Overwriting slot 0.");
+#if  USE_PORTNAME
+		BCOPY(device->wwn, pdb[index].name, 8);
+#else
+		BCOPY(device->name, pdb[index].name, 8);
+#endif
+	} else {
+		printk(KERN_INFO "qla2100_update_host: Host table Full.");
+		status = 2;
+	}
+	ha->host_db_ptr = index;
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+	if( status )
+		qla2100_print("qla2100_update_host: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+	else
+		LEAVE("qla2100_update_host");
+#endif
+	return(status);
+
+}
+
+/*
+* qla2100_update_device_data
+*      This routine updates the device data in the database and logs
+*      onto the device if necessary.
+*
+* Input:
+*      ha = adapter block pointer.
+*      device = device data pointer.
+*
+* Returns:
+*      0 = success, if device found or added to database.
+*      1 = error
+*      2 = database was full and device was not configured.
+*/
+STATIC uint8_t
+qla2100_update_device_data(scsi_qla_host_t *ha, device_data_t *device, uint8_t enable_slot_reuse) {
+            uint8_t     status = 0;
+            uint8_t     hostflag = 0;
+            uint8_t     dev_configured;
+            uint16_t    cnt, i;
+            uint16_t    mb[MAILBOX_REGISTER_COUNT];
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_update_device");
+#endif
+
+            dev_configured = FALSE;
+            if( ha->device_id == QLA2100_DEVICE_ID ) {
+                ha->min_external_loopid = 1;       /* v2.19.5b3 */
+                ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1;
+            } else {
+                ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1;
+            }
+
+            DEBUG(sprintf(debug_buff,
+	        "qla2100: Found device - portname=%02x%02x%02x%02x%02x%02x%02x%02x,"
+	        " nodename=%02x%02x%02x%02x%02x%02x%02x%02x,"
+	        " port Id=%06lx, loop id=%04x\n",
+	        device->wwn[0], device->wwn[1],
+	        device->wwn[2], device->wwn[3],
+	        device->wwn[4], device->wwn[5],
+	        device->wwn[6], device->wwn[7],
+	        device->name[0], device->name[1],
+	        device->name[2], device->name[3],
+	        device->name[4], device->name[5],
+	        device->name[6], device->name[7],
+	        device->port_id[0] << 16 | device->port_id[1] <<  8 | device->port_id[2], device->loop_id);)
+            DEBUG(qla2100_print(debug_buff);)
+
+             /* if we already login to the host adapter then skip it */
+            if ( qla2100_find_host(ha, device)  ) {
+               DEBUG(printk("update_db: Skipping host adapter..\n");)
+               return( status );
+            }
+            
+            /* Search to see if node name is already in database. If found then change loop ID in database. */
+            for( cnt = 0; cnt < MAX_FIBRE_DEVICES && !dev_configured; cnt++ ) {
+                /* if nodename/portname in database then replace it */
+#if  USE_PORTNAME  /* updated for ioctl merge */
+		if (BCMP(device->wwn, ha->fc_db[cnt].wwn, 8) == 0) {
+#else
+		if (BCMP(device->name, ha->fc_db[cnt].name, 8) == 0) {
+#endif
+                        ha->fc_db[cnt].flag &= ~DEV_MISSING;
+                        /* if device was configured by user then find and assign a loop ID for it */
+                        if( ha->fc_db[cnt].loop_id == PORT_AVAILABLE ) {
+                            DEBUG(qla2100_print("Port marked as already assigned.\n");)
+                            /* If device found is on the public loop. */
+                            /* then find the next available fabric loop ID */
+                            if( device->loop_id == 0xffff ) {
+                                status = 1;
+                                /* Search the public database for first available slot.  */
+                                for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) {
+                                    if( !ha->fabricid[i].in_use ) {
+                                        ha->fabricid[i].in_use = TRUE;
+                                        if( ha->device_id == QLA2100_DEVICE_ID )
+                                            device->loop_id = SNS_FIRST_LOOP_ID + i;
+                                        else
+                                            device->loop_id = i;
+                                        ha->fc_db[cnt].loop_id = device->loop_id;
+                                        ha->fc_db[cnt].port_id[0] = device->port_id[0];
+                                        ha->fc_db[cnt].port_id[1] = device->port_id[1];
+                                        ha->fc_db[cnt].port_id[2] = device->port_id[2];
+                                        ha->fc_db[cnt].flag |= DEV_PUBLIC;
+                                        status = 0;
+                                        break;
+                                    }
+                                } /* end of for */
+                            } else {  /* change the local loop ID in database */
+                                ha->fc_db[cnt].loop_id = device->loop_id;
+                            }
+                        } else /* loop id may have been previously used */
+                        {
+                            /* If device is on public loop. */
+                            if( device->loop_id == 0xffff ) {
+                                /* It was previously public, so use previously assigned loop id. */
+                                if( ha->fc_db[cnt].flag & DEV_PUBLIC )
+                                    if( ha->device_id == QLA2100_DEVICE_ID )
+                                        device->loop_id = ha->fc_db[cnt].loop_id;
+                                    else {
+                                        /* if the same topology and public loop */
+                                        /* search for the next avaiable public loop ID */
+                                        DEBUG(printk("update_db: topology prev %d, curr %d\n",
+                                        ha->prev_topology, ha->current_topology );)
+                                        if( ha->prev_topology == ha->current_topology ) {
+                                            if( (ha->min_external_loopid) &&
+                                            (ha->fc_db[cnt].loop_id < ha->min_external_loopid) ) {
+                                                status = 1;
+                                                /* find a loop ID for the Public device */
+                                                for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ )
+                                                    if( !ha->fabricid[i].in_use ) {
+                                                        ha->fabricid[i].in_use = TRUE;
+                                                        device->loop_id = i;
+                                                        ha->fc_db[cnt].loop_id = device->loop_id;
+                                                        status = 0;
+                                                        break;
+                                                    }
+                                            } else
+                                                device->loop_id = ha->fc_db[cnt].loop_id;
+                                        } else {
+                                            status = 1;
+                                            /* Find an unused loop ID */
+                                            for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ )
+                                                if( !ha->fabricid[i].in_use ) {
+                                                    ha->fabricid[i].in_use = TRUE;
+                                                    device->loop_id = i;
+                                                    ha->fc_db[cnt].loop_id = device->loop_id;
+                                                    status = 0;
+                                                    break;
+                                                }
+                                        }
+
+                                    } else {
+                                        /* If it moved from private to public loop, assign new public loop id. */
+                                        status = 1;
+                                            /* Find an unused loop ID */
+                                        for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ )
+                                            if( !ha->fabricid[i].in_use ) {
+                                                ha->fabricid[i].in_use = TRUE;
+                                                if( ha->device_id == QLA2100_DEVICE_ID )
+
+                                                    device->loop_id = SNS_FIRST_LOOP_ID + i;
+                                                else
+                                                    device->loop_id = i;
+                                                ha->fc_db[cnt].loop_id = device->loop_id;
+                                                ha->fc_db[cnt].flag |= DEV_PUBLIC;
+                                                ha->fc_db[cnt].port_id[0] = device->port_id[0];
+                                                ha->fc_db[cnt].port_id[1] = device->port_id[1];
+                                                ha->fc_db[cnt].port_id[2] = device->port_id[2];
+                                                status = 0;
+                                                break;
+                                            }
+                                    }
+                            } else {
+                                /* The found device is on private loop but was
+                                previously on public loop, so free public loop id. */
+                                if( ha->fc_db[cnt].flag & DEV_PUBLIC ) {
+                                    ha->fc_db[cnt].flag &= ~DEV_PUBLIC;
+                                    i = ha->fc_db[cnt].loop_id - SNS_FIRST_LOOP_ID;
+                                    ha->fabricid[i].in_use = 0;
+                                }
+                                ha->fc_db[cnt].loop_id = device->loop_id;
+                            }
+                        }
+                        
+                        /* If public device in database */
+                        if( !status && (ha->fc_db[cnt].flag) & DEV_PUBLIC ) {
+                        
+                            
+                            /* If public loop device, compare port id to see if
+                            device moves to another NL/N port. */
+                            if( ha->fc_db[cnt].port_id[0] != device->port_id[0] ||
+                            ha->fc_db[cnt].port_id[1] != device->port_id[1] ||
+                            ha->fc_db[cnt].port_id[2] != device->port_id[2] ) {
+                                if( ha->prev_topology == ha->current_topology ) {
+                                    /* Port id changed, log device out then log back
+                                    in with new port id but same loop id. */
+                                    mb[0] = MBC_LOGOUT_FABRIC_PORT;
+                                    mb[1] = ha->fc_db[cnt].loop_id << 8;
+                                    qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+                                    ha->fc_db[cnt].port_id[0] = device->port_id[0];
+                                    ha->fc_db[cnt].port_id[1] = device->port_id[1];
+                                    ha->fc_db[cnt].port_id[2] = device->port_id[2];
+                                }
+                            }
+                            /*
+                            * Try and find a loop Id for the given
+                            * fabric port. We keep trying Ids until we find
+                            * a good one.
+                            */
+                            mb[0] = 0x4008;
+                            while( !status && mb[0] == 0x4008 ) {
+                            DEBUG(printk("update_db: Trying Fabric Login @ loop id= %d, port id= %06x\n", device->loop_id,device->port_id);)
+                                mb[0] = MBC_LOGIN_FABRIC_PORT;
+                                mb[1] = device->loop_id << 8 | 0x01;
+                                mb[2] = device->port_id[0];
+                                mb[3] = device->port_id[1] << 8 | device->port_id[2];
+                                qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0,
+                                &mb[0]);
+                                /* Command parameter error or all IDS used */
+                                if ( mb[0] == 0x4006 || mb[0] == 0x4009 ) {
+                                    status = 1;
+                                    DEBUG(printk("update_db: (1) Failed Fabric login with Loop ID = %d\n", device->loop_id);)
+                                }
+                                /*
+                                * if loop Id is in use then try the next Id .
+                                */
+                                if( mb[0] == 0x4008 ) {
+                                    DEBUG(printk("update_db: Used Loop ID = %04x, port id=%06x - trying next id\n", device->loop_id,
+                                    ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)));)
+                                    if( device->loop_id++ <= LAST_SNS_LOOP_ID )
+                                        ha->fabricid[device->loop_id].in_use = TRUE;
+                                    else
+                                        status = 1;
+                                }
+                            }
+			    /* Login succuessful */
+                            if( !status ) {     
+                            	/* if different host */
+                                if( (mb[1] & 0x1) ) {     /* v2.19.05b3 */
+                                  DEBUG(printk("update_db: Warning -- Adapter found: port id=%06x, tgt=%d\n", 
+                                    ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)),cnt);)
+                                  qla2100_update_host_data(ha, device, enable_slot_reuse); 
+                                  ha->fabricid[device->loop_id].in_use = FALSE;
+                                  hostflag++;
+				} else {
+				  /* 4.31.8 update loop id in database */
+                               	  ha->fc_db[cnt].loop_id = device->loop_id;
+				}
+			    }
+#if 0
+                            /* Command error */
+                            if( !status && mb[0] != 0x4005 ) {
+                                /* Issue Abort target command to cause RISC to
+                                flush all commands outstanding for this device.
+                                Commands will be returned with "Aborted" status. */
+                                mb[0] = MBC_ABORT_TARGET;
+                                mb[1] = device->loop_id << 8;
+                                mb[2] = 1;
+                                status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]);
+                            }
+#endif
+                        }
+                        dev_configured = TRUE;
+                    }
+                }
+
+                /* Device not already in database so find */
+                /* an empty slot and loop id for it.      */
+                if( !dev_configured ) {
+                    DEBUG(printk("qla2100_db_update: New Device - not in database.\n");)
+
+                    /* If device is on public loop.        */
+                    /* First find an unused Fabric loop ID */
+                    /* then find a slot.                   */
+                    if( device->loop_id == 0xffff ) {
+                        status = 1;
+                        for( i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++ ) {
+                            if( !ha->fabricid[i].in_use ) {
+                                ha->fabricid[i].in_use = TRUE;
+                                if( ha->device_id == QLA2100_DEVICE_ID )
+                                    device->loop_id = SNS_FIRST_LOOP_ID + i;
+                                else
+                                    device->loop_id = i;
+                                status = 0;
+                                break;
+                            }
+                        }
+                        /* Preset status to Loop ID used */
+                        mb[0] = 0x4008;
+                        /* Check to insure loop ID for fabric device is good */
+                        while( !status && mb[0] == 0x4008 ) {
+                            DEBUG(printk("update_db: Trying Fabric Login @ loop id %d\n", device->loop_id);)
+                            mb[0] = MBC_LOGIN_FABRIC_PORT;
+                            mb[1] = device->loop_id << 8 | 0x01;
+                            mb[2] = device->port_id[0];
+                            mb[3] = device->port_id[1] << 8 | device->port_id[2];
+                            qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]);
+                            if ( mb[0] == 0x4006 || mb[0] == 0x4009 ) {
+                                status = 1;
+                                DEBUG(printk("update_db: (2) Failed Fabric login with Loop ID = %d\n", device->loop_id);)
+                            }
+                            if( mb[0] == 0x4008 ) {
+                                DEBUG(printk("update_db: (2) Used Fabric Loop ID = %04x, port id=%06x\n", device->loop_id,
+                                ((mb[1] << 16) | (((mb[2] >>8 ) &0xff) << 8) | (mb[2] & 0xff)));)
+                                if( device->loop_id++ <= LAST_SNS_LOOP_ID ) 
+                                    ha->fabricid[device->loop_id].in_use = TRUE;  /* v2.19.05b3 */
+                                else
+                                    status = 1;
+                            }
+                            if( (mb[1] & 0x1) ) {     /* v2.19.05b3 */
+                               qla2100_update_host_data(ha, device, enable_slot_reuse); 
+                               DEBUG(printk("update_db: Adapter found: port id=%06x\n", 
+                                        (device->port_id[0] <<16) |
+                                        (device->port_id[1] << 8) | (device->port_id[2])) );
+                               ha->fabricid[device->loop_id].in_use = FALSE; 
+                               hostflag++;
+                            }
+                        }
+                    }
+                    /* Now find an empty slot for the device */
+                    if( !status && hostflag == 0 ) {
+                        if( ha->device_id == QLA2100_DEVICE_ID )
+                            ha->min_external_loopid = SNS_FIRST_LOOP_ID;
+                        /* Find a empty slot and add device into database. */
+                        for( i = 0; i < MAX_FIBRE_DEVICES; i++ )
+                            if( ha->fc_db[i].loop_id == PORT_UNUSED ) {
+                                ha->fc_db[i].flag &= ~DEV_MISSING;
+	
+                                /* get and set both wwnn and wwpn */
+                                BCOPY(device->name, ha->fc_db[i].name, 8);
+                                BCOPY(device->wwn, ha->fc_db[i].wwn, 8);
+
+                                ha->fc_db[i].loop_id = device->loop_id;
+                                if( device->loop_id >= ha->min_external_loopid ) {
+                                    ha->fc_db[i].flag |= DEV_PUBLIC;
+                                    ha->fc_db[i].port_id[0] = device->port_id[0];
+                                    ha->fc_db[i].port_id[1] = device->port_id[1];
+                                    ha->fc_db[i].port_id[2] = device->port_id[2];
+                                }
+                                ha->flags.updated_fc_db = TRUE;
+                                dev_configured = TRUE;
+                                break;
+                            }
+                            if( !dev_configured ) {
+                                if( enable_slot_reuse ) {
+                                    for( i = 0; i < MAX_FIBRE_DEVICES; i++ )
+                                        if( ha->fc_db[i].loop_id == PORT_AVAILABLE ) {
+                                            ha->fc_db[i].flag &= ~DEV_MISSING;
+#if  USE_PORTNAME  /* ioctl support change */
+                                            BCOPY(device->wwn, ha->fc_db[i].wwn, 8);
+#else
+                                            BCOPY(device->name, ha->fc_db[i].name, 8);
+#endif
+                                            ha->fc_db[i].loop_id = device->loop_id;
+                                            if( device->loop_id >= ha->min_external_loopid ) {
+                                                ha->fc_db[i].flag |= DEV_PUBLIC;
+                                                ha->fc_db[i].port_id[0] = device->port_id[0];
+                                                ha->fc_db[i].port_id[1] = device->port_id[1];
+                                                ha->fc_db[i].port_id[2] = device->port_id[2];
+                                            }
+                                            ha->flags.updated_fc_db = TRUE;
+                                            break;
+                                        }
+                                } else {
+                                    ha->fabricid[device->loop_id].in_use = FALSE;
+                                    status = 2;
+                                }
+
+                            }
+
+                    }
+                }
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_update_device: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_update_device");
+#endif
+                return(status);
+            }
+
+/*
+* qla2100_sns_device
+*      Setup Simple Name Server devices with loop ID's.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*      1 = error
+*      2 = database was full and device was not configured.
+*/
+STATIC uint8_t
+qla2100_sns_device(scsi_qla_host_t *ha, uint8_t enable_slot_reuse) {
+                uint8_t     status = 1;
+                uint8_t     first_port_id[3];
+                uint8_t     next_port_id[3];
+                uint8_t     host_port_id[3];
+                sns_data_t  *sns;
+#if BITS_PER_LONG > 32
+                uint64_t    phys_address = 0;
+#else
+                uint32_t    phys_address = 0;
+#endif
+                uint16_t    mb[MAILBOX_REGISTER_COUNT];
+                uint8_t     use_gan = 1;
+                uint8_t     retry_count = 0;
+                gp_idnn_t   *gp_idnn;
+                uint16_t    i;
+                device_data_t device;
+                uint8_t     db_full = 0;
+                uint16_t    public_count;
+                uint32_t    fabric_devices = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_sns_device");
+#endif
+
+                /* If FL port exists, then SNS is present */
+                DEBUG(printk("qla2100_sns_device: Checking for Fabric.\n");)
+                mb[0] = MBC_GET_PORT_NAME;
+                mb[1] = SNS_FL_PORT << 8;  /* port name */
+                if( !qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) {
+
+#ifdef RCSN
+                    /* Mark devices that need re-synchronization. */
+                    qla2100_device_resync(ha);
+#endif
+
+                    /* Fl port is present */
+                    host_port_id[0] = ha->port_id[0];
+                    host_port_id[1] = ha->port_id[1];
+                    host_port_id[2] = ha->port_id[2];
+
+                    /* Calculate the max number of public ports */
+                    if( ha->device_id == QLA2100_DEVICE_ID )
+                        public_count = ha->max_public_loop_ids;
+                    else
+                        public_count = ha->max_public_loop_ids - ha->min_external_loopid;
+
+                    /* Register with name server as type fc4 device */
+
+#ifdef FC_IP_SUPPORT
+                    /* Register with name server as type 5 device */
+                    if (ha->flags.enable_ip == TRUE) {
+                        qla2x00_register_ip_device(ha);
+                    }
+
+                    /* If IP enable, skip GP_IDNN and just use GAN */
+                    if (ha->flags.enable_ip == TRUE)
+                        goto tryGan;
+#endif /* FC_IP_SUPPORT */
+
+                    /* Find out if this is a Brocade switch, if so do GP_IDNN. */
+                    /* otherwise use the GAN                                   */
+                    mb[0] = MBC_GET_PORT_NAME;
+                    mb[1] = SNS_FL_PORT << 8 | BIT_0;   /* node name */
+                    qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+                    if( mb[2] == 0x0010 && mb[3] == 0x6000 &&
+                    (mb[6] & 0x00FF) == 0x0069 ) {
+/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                        gp_idnn = KMALLOC(GP_IDNN_LENGTH);
+                        if ( gp_idnn != NULL ) {
+                            phys_address = VIRT_TO_BUS(gp_idnn);
+                            BZERO((caddr_t)gp_idnn, GP_IDNN_LENGTH);
+                        }
+#else
+                        gp_idnn  = pci_alloc_consistent(ha->pdev,
+                                                        GP_IDNN_LENGTH,
+                                                        &phys_address);
+                        BZERO((caddr_t)gp_idnn, GP_IDNN_LENGTH);
+#endif
+                        if ( gp_idnn != NULL ) {
+                            /* Retry GP_IDNN til valid list or retries done */
+                            while( retry_count++ < 10 ) {
+                                /*
+                                * Issue GP_IDNN to get list of port IDs and
+                                * node names from name server.
+                                */
+                                gp_idnn->req.buffer_length = GP_IDNN_LENGTH/2;
+                                /* 4.10 */
+                                gp_idnn->req.buffer_address[0] = 
+                                  LS_64BITS(phys_address);
+                                gp_idnn->req.buffer_address[1] = 
+                                  MS_64BITS(phys_address);
+                                gp_idnn->req.subcommand_length = 6;
+                                gp_idnn->req.subcommand = 0x173;
+                                gp_idnn->req.length = GP_IDNN_LENGTH / 4;
+                                gp_idnn->req.protocol = 0x08;
+
+                                mb[0] = MBC_SEND_SNS_COMMAND;
+                                mb[1] = 14;
+                                mb[3] = LSW(phys_address);
+                                mb[2] = MSW(phys_address);
+                                mb[7] = QL21_64BITS_3RDWD(phys_address);
+                                mb[6] = QL21_64BITS_4THWD(phys_address);
+                                if( !qla2100_mailbox_command(ha,
+                                BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0,
+                                &mb[0]) ) {
+                                    if( gp_idnn->rsp.response == SNS_ACCEPT ) {
+                                        DEBUG3(printk("Sns: Get all Fabric devices:\n");)
+                                        /* Go down device list and add devices to database. */
+                                        for( i = 0; i < public_count; i++ ) {
+                                            /* if not host port id then add it to the database */
+                                            if( gp_idnn->rsp.port_data[i].port_id[0] != host_port_id[0] ||
+                                            gp_idnn->rsp.port_data[i].port_id[1] != host_port_id[1] ||
+                                            gp_idnn->rsp.port_data[i].port_id[2] != host_port_id[2] ) {
+						BCOPY(gp_idnn->rsp.port_data[i].nodename, device.name, 8);
+                                                /* get loop id */
+                                                device.port_id[0] = gp_idnn->rsp.port_data[i].port_id[0];
+                                                device.port_id[1] = gp_idnn->rsp.port_data[i].port_id[1];
+                                                device.port_id[2] = gp_idnn->rsp.port_data[i].port_id[2];
+#if USE_PORTNAME
+                                                /* Get portname */
+                                                if( qla2100_sns_get_name(ha, &device, 0) ) {
+                                                    status =  1;  /* v2.19.5b4 */
+                                                    break;
+						}
+#endif
+                                                device.loop_id = 0xffff;
+                                                /* Update device database and login to device. */
+                                                fabric_devices++;
+                                                if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) {
+                                                    if( status == 2 )
+                                                        db_full = 1;
+                                                    else
+                                                        break;
+                                                }
+                                            }
+                                            if( gp_idnn->rsp.port_data[i].controlbyte == 0x80 )
+                                                break;
+                                        }
+                                        use_gan = 0;
+                                        break;
+                                    }
+                                }
+                                /* Wait for 100ms before retrying */
+                                for( i = 0; i <= 10000; i++ ) {
+                                    udelay(10);
+                                }
+                            }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                            KMFREE(gp_idnn, GP_IDNN_LENGTH);
+#else
+                            pci_free_consistent(ha->pdev, GP_IDNN_LENGTH,
+                                   gp_idnn, phys_address);
+#endif
+                        } else {
+                            use_gan = 0;
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_sns_device: Failed to allocate memory, No FL Port\n");
+#endif
+                        }
+                    }
+                    /* Use the GAN (GA_NXT) Name server request to discover the ports  */
+
+                    /*
+                    *	Go through GAN list to find all fabric devices.  Will perform
+                    *	necessary logout of previously existed devices that have changed
+                    *	and save new devices in a new device list.
+                    *
+                    */
+
+                    if( use_gan ) {
+#ifdef FC_IP_SUPPORT
+                        tryGan:
+#endif
+
+                        /* Find all registered ports in the Fabric */
+/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                        sns = KMALLOC(sizeof(sns_data_t));
+                        if ( sns != NULL ) {
+                            phys_address = VIRT_TO_BUS(sns);
+                            BZERO((caddr_t)sns, sizeof(sns_data_t));
+                        }
+#else
+                        sns  = pci_alloc_consistent(ha->pdev,
+                                                    sizeof(sns_data_t),
+                                                    &phys_address);
+                        BZERO((caddr_t)sns, sizeof(sns_data_t));
+#endif
+                        if ( sns != NULL ) {
+                            DEBUG(printk("qla2100_sns_device: Performing a GAN (%d)\n",public_count);)
+                            status = 0;
+                            /* start with port ID = 0 */
+                            first_port_id[0] = first_port_id[1] = first_port_id[2] = 0;
+                            next_port_id[0] = next_port_id[1] = next_port_id[2] = 0;
+                            mb[0] = 0;
+                            for( i = 0; i < public_count && !ha->loop_down_timer &&
+                            !ha->flags.loop_resync_needed; i++ ) {
+                                /* GAN Get all next entries for the selected port ID from SNS. */
+                                BZERO((caddr_t)sns, sizeof(sns_data_t));
+                                sns->p.req.hdr.buffer_length = 318; /*304*/
+                                sns->p.req.hdr.buffer_address[0] = 
+                                    LS_64BITS(phys_address);
+                                sns->p.req.hdr.buffer_address[1] = 
+                                    MS_64BITS(phys_address);
+                                sns->p.req.hdr.subcommand_length = 6;
+                                sns->p.req.subcommand = 0x100;
+                                sns->p.req.param[6] = next_port_id[2];
+                                sns->p.req.param[7] = next_port_id[1];
+                                sns->p.req.param[8] = next_port_id[0];
+
+                                mb[0] = MBC_SEND_SNS_COMMAND;
+                                mb[1] = 14;
+                                mb[3] = LSW(phys_address);
+                                mb[2] = MSW(phys_address);
+                                mb[7] = QL21_64BITS_3RDWD(phys_address);
+                                mb[6] = QL21_64BITS_4THWD(phys_address);
+                                if( !qla2100_mailbox_command(ha,
+                                     BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0,
+                                     &mb[0])  ) {
+                                    if( sns->p.rsp[8] != 0x80 ||  /* SNS_ACCEPT */
+                                        sns->p.rsp[9] != 0x02   ) { /* 04/18/00 */
+                                    printk(KERN_INFO "qla2100_sns_device: SEND_SNS_COMMAND Failed - 0x%2x%2x mb_res=%x\n",
+                                            sns->p.rsp[8],sns->p.rsp[9],mb[0]);
+                                       status = 1;
+                                       break;
+                                    }
+                                    /* save next port ID */
+                                    next_port_id[0] = sns->p.rsp[17];
+                                    next_port_id[1] = sns->p.rsp[18];
+                                    next_port_id[2] = sns->p.rsp[19];
+
+                                } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                    qla2100_print(
+                                    "qla2100_sns_device: MBC_SEND_SNS_COMMAND Failed, No FL Port\n");
+#endif
+                                    /* v2.19.5 */
+                            	   DEBUG(printk("qla2100_sns_device: Failed Performing a GAN mb0=0x%x, mb1=0x%x\n",
+                                         mb[0],mb[1]);)
+                                    status = 1;
+                                    break;
+                                }
+
+                                /* Assign loop ID for device on SNS. */
+                                if( (next_port_id[0] != first_port_id[0] ||
+                                next_port_id[1] != first_port_id[1] ||
+                                next_port_id[2] != first_port_id[2])
+                                &&  (sns->p.rsp[284] || sns->p.rsp[285] ||
+                                sns->p.rsp[286] || sns->p.rsp[287] ||
+                                sns->p.rsp[288] || sns->p.rsp[289] ||
+                                sns->p.rsp[290] || sns->p.rsp[291]) ) {
+                                    /* if port Id local loop skip this ID  */
+                                    if( next_port_id[0] != host_port_id[0] ||
+                                    next_port_id[1] != host_port_id[1] ||
+                                    next_port_id[2] != host_port_id[2] ) {
+#if USE_PORTNAME
+                                        /* Extract portname */
+					BCOPY(&sns->p.rsp[20], device.wwn, 8);
+#endif
+                                        /* Extract nodename */
+					BCOPY(&sns->p.rsp[284], device.name, 8);
+                                        /* extract port ID */
+                                        device.port_id[0] = next_port_id[0];
+                                        device.port_id[1] = next_port_id[1];
+                                        device.port_id[2] = next_port_id[2];
+                                        device.loop_id = 0xffff;
+
+                                        /* Update device database and login device in */
+
+                                        /* if McData, skip all port types except 1 (N_port) & 2 (NL_port) */
+                                        if ( !( (sns->p.rsp[16] == 0x01) ||
+                                        (sns->p.rsp[16] == 0x02)    ) ) {
+                                            DEBUG(printk("qla2100_sns_device: Skipping port type %x\n", sns->p.rsp[16]);)
+                                        }
+
+#ifdef FC_IP_SUPPORT
+                                        else if (sns->p.rsp[579] & 0x20) {
+                                            fabric_devices++;
+                                            /* Update IP device */
+                                            if (qla2x00_update_ip_device_data(ha, &device) == QL_STATUS_FATAL_ERROR) {
+                                                status = 1;
+                                                break;
+                                            }
+                                            /* Update SCSI device */
+                                        }
+#endif
+                                        else {
+                                            fabric_devices++;
+                                            if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) {
+                                                if( status == 2 )
+                                                    db_full = 1;
+                                                break;
+                                            }
+                                        }
+#ifdef FC_IP_SUPPORT
+                                    }
+#endif
+                                }
+
+                                /*
+                                * Save first port if not repeating port
+                                * on another Loop ID.
+                                */
+                                if( !(first_port_id[0] || first_port_id[1] ||
+                                first_port_id[2]) ) {
+                                    first_port_id[0] = next_port_id[0];
+                                    first_port_id[1] = next_port_id[1];
+                                    first_port_id[2] = next_port_id[2];
+                                }
+                            } else
+                                break;
+                        }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                        KMFREE(sns, sizeof(sns_data_t));
+#else
+                        pci_free_consistent(ha->pdev, sizeof(sns_data_t),
+                                   sns, phys_address);
+#endif
+
+                    }
+#ifdef QL_DEBUG_LEVEL_2
+                    else
+                        qla2100_print(
+                        "qla2100_sns_device: Failed to allocate memory, No FL Port\n");
+#endif
+                }
+            } else
+#ifdef QL_DEBUG_LEVEL_2
+                qla2100_print(
+                "qla2100_sns_device: MBC_GET_PORT_NAME Failed, No FL Port\n");
+#else
+            DEBUG(printk("No Fabric found.\n");)
+#endif
+
+            if( fabric_devices >  0)
+              ha->device_flags |= DFLG_FABRIC_DEVICES;
+
+            if( db_full )
+                status = 2;
+
+            /* Update iff F/FL found and update O.K. */
+            if( !status )
+                ha->prev_topology = ha->current_topology;
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+            if( status )
+                qla2100_print("qla2100_sns_device: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+            else
+                LEAVE("qla2100_sns_device");
+#endif
+            return(status);
+}
+
+#if USE_PORTNAME
+/*
+* qla2100_sns_get_name
+*      This routine is called tot do the SNS Get Port/Name command
+*      of the specified port.
+*
+* Input:
+*      ha = adapter block pointer.
+*      flag = 0 - port name , 1 - node name
+*
+* Output:
+*
+*/
+STATIC uint8_t qla2100_sns_get_name( scsi_qla_host_t *ha, device_data_t *device, uint8_t flag ) {
+            uint8_t     lStatus = 0;
+            uint16_t    wRetryCount;
+#if BITS_PER_LONG > 32
+            uint64_t    phys_address = 0;
+#else
+            uint32_t    phys_address = 0;
+#endif
+            uint16_t    mb[MAILBOX_REGISTER_COUNT];
+            uint16_t    subCmd, response;
+            sns_data_t  *sns;
+
+            /* Set retry count */
+            if ( flag )
+                subCmd = 0x113;
+            else
+                subCmd = 0x112;
+            DEBUG2(printk("qla2100_SnsGetName: Get opcode %x - name for port Id %06x\n", subCmd,
+            (uint32_t)(device->port_id[0] << 16 | device->port_id[1] <<  8 | device->port_id[2]));)
+
+            wRetryCount = 2;
+            while (wRetryCount--) {
+                /* Do 'Get Port/Node name' mailbox command for the FL attached device */
+/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                sns = KMALLOC(sizeof(sns_data_t));
+                if ( sns != NULL ) {
+                     phys_address = VIRT_TO_BUS(sns);
+                     BZERO((caddr_t)sns, sizeof(sns_data_t));
+                }
+#else
+                sns  = pci_alloc_consistent(ha->pdev,
+                                            sizeof(sns_data_t),
+                                            &phys_address);
+                BZERO((caddr_t)sns, sizeof(sns_data_t));
+#endif
+                if ( sns != NULL ) {
+                    BZERO((caddr_t)sns, sizeof(sns_data_t));
+                    sns->p.req.hdr.buffer_length = 12;
+                    /* 4.10 */
+                    sns->p.req.hdr.buffer_address[0] = 
+                       LS_64BITS(phys_address);
+                    sns->p.req.hdr.buffer_address[1] = 
+                       MS_64BITS(phys_address);
+                    sns->p.req.hdr.subcommand_length = 6;
+                    sns->p.req.subcommand = subCmd;
+                    sns->p.req.param[6] = device->port_id[2];
+                    sns->p.req.param[7] = device->port_id[1];
+                    sns->p.req.param[8] = device->port_id[0];
+                    sns->p.req.param[9] = 0;
+
+                    mb[0] = MBC_SEND_SNS_COMMAND;
+                    mb[1] = 14;
+                    mb[3] = LSW(phys_address);
+                    mb[2] = MSW(phys_address);
+                    mb[7] = QL21_64BITS_3RDWD(phys_address);
+                    mb[6] = QL21_64BITS_4THWD(phys_address);
+                    if( !qla2100_mailbox_command(ha,
+                    BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0,
+                    &mb[0]) ) {
+
+                        response = sns->p.rsp[8] | (sns->p.rsp[9] << 8);
+                        if( response == SNS_ACCEPT ) {
+                            if ( flag ) {
+				BCOPY(&sns->p.rsp[16], device->name, 8);
+                            } else {
+				BCOPY(&sns->p.rsp[16], device->wwn, 8);
+                            }
+                        } else {
+                            printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd response is not accept - status %x\n", mb[0]);
+                        }
+                    } else if (mb[0] == MBS_FATAL_ERROR) {
+                        printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd fatal error - status %x\n", mb[0]);
+                        lStatus = 1;
+                        break;
+                    } else {
+                        printk(KERN_WARNING "qla2100_SnsGetName: [ERROR] Get Name mb cmd failed - status %x\n", mb[0]);
+                    }
+
+                }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                KMFREE(sns, sizeof(sns_data_t));
+#else
+                pci_free_consistent(ha->pdev, sizeof(sns_data_t),
+                                    sns, phys_address);
+#endif
+            }
+            return(lStatus);
+
+}
+#endif
+
+/*
+* qla2100_init_fc_db
+*      Initializes Fibre Channel Device Database.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Output:
+*      ha->fc_db = initialized
+*/
+STATIC void
+qla2100_init_fc_db(scsi_qla_host_t *ha) {
+            uint16_t cnt;
+
+#ifdef QL_DEBUG_LEVEL_3
+            ENTER("qla2100_init_fc_db");
+#endif
+
+            /* Initialize fc database if it is not initialized. */
+            if( !ha->fc_db[0].loop_id && !ha->fc_db[1].loop_id ) {
+                ha->flags.updated_fc_db = FALSE;
+
+                /* Initialize target database. */
+                for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) {
+                    ha->fc_db[cnt].name[0] = 0L;
+                    ha->fc_db[cnt].name[1] = 0L;
+                    ha->fc_db[cnt].loop_id = PORT_UNUSED;
+                    ha->fc_db[cnt].port_login_retry_count = 8;
+                    ha->fc_db[cnt].flag = 0;   /* v2.19.5b3 */
+                    ha->fc_db[cnt].port_timer = 0;   /* v2.19.8 */
+                }
+
+#if USE_FLASH
+                /* Move flash database to driver database. */
+                qla2100_get_database(ha);
+#endif
+            }
+
+#ifdef QL_DEBUG_LEVEL_3
+            LEAVE("qla2100_init_fc_db");
+#endif
+}
+
+/*
+* qla2100_configure_fabric
+*	Setup fabric devices with loop ID's.
+*
+* Input:
+*	ha = adapter block pointer.
+*	enable_slot_reuse = allows the use of PORT_AVAILABLE slots.
+*
+* Returns:
+*	0 = success.
+*	1 = error.
+*	2 = database was full and a device was not configured.
+*
+* Context:
+*	Kernel context.
+*/
+STATIC uint8_t
+qla2100_configure_fabric(scsi_qla_host_t *ha, 
+    uint8_t enable_slot_reuse)
+{
+            uint8_t  status = 0;
+            uint16_t    i;
+
+            /* get public loop devices */
+            if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ){
+               /* Configure loop */
+               if( !qla2100_configure_hba(ha) ) {
+                   if( ha->device_id == QLA2100_DEVICE_ID ) {
+                       ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1;
+                   } else {
+                       ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1;
+                        /* dg 09/15 */
+                        /* if the topology have change then make all devices available */
+                        if( ha->prev_topology != ha->current_topology ) {
+                            /* Mark all fabric devices that where present as AVAILABLE */
+                            for( i = 0; i < ha->max_public_loop_ids; i++ )
+                                if( (i != SNS_FL_PORT) && (i != FABRIC_CONTROLLER)
+                                && (i != SIMPLE_NAME_SERVER) )
+                                    ha->fabricid[i].in_use = FALSE;
+                        }
+                }
+                status = qla2100_sns_device(ha, enable_slot_reuse);
+                qla2100_restart_queues(ha,TRUE);
+            }
+            status = 1;
+        }
+        return( status );
+}
+
+/*
+* qla2100_check_devices
+*	Check devices with loop ID's.
+*
+* Input:
+*	ha = adapter block pointer.
+*
+* Returns:
+*	0 = success.
+*   1 = retry needed
+*
+* Context:
+*	Kernel context.
+*/
+STATIC uint8_t
+qla2100_check_devices(scsi_qla_host_t *ha) {
+            int cnt;
+            uint8_t  ret = 0;
+            uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+            /*
+            * Retry any devices that wasn't found but as a WWN.
+            */
+            /* v2.19.05b6 */
+            for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) {
+                    if( (ha->fc_db[cnt].flag & DEV_MISSING) &&
+                       !(ha->fc_db[cnt].flag & DEV_OFFLINE) ) {
+                        /*
+                        * This dev was not detected but its WWN
+                        * is valid. To handle the case where
+                        * the switch may not be giving us the
+                        * device list correctly, schedule for
+                        * a login retry later if not previously
+                        * done so.
+                        */
+                        DEBUG(printk("qla2100_sns:Port login retry - target %d, count=%d\n",cnt, 
+                                        ha->fc_db[cnt].port_login_retry_count); )
+                        if( ha->fc_db[cnt].port_login_retry_count )
+                          ha->fc_db[cnt].port_login_retry_count--;
+
+                        /*
+                        * If after decrement the retry count
+                        * becomes 0, mark this device OFFLINE so
+                        * no more retries will be done based
+                        * on this device.
+                        */
+                        if (ha->fc_db[cnt].port_login_retry_count == 0) {
+                            DEBUG(printk("qla2100_sns:Port set to OFFLINE - target %d\n",cnt); )
+                            ha->fc_db[cnt].flag |= DEV_OFFLINE;
+                        }
+                        ret = 1;
+                    }
+               }
+
+                /*
+                * Mark devices as DEV_MISSING if they were present
+                * before and have a loop ID.
+                */
+                for( cnt = 0; cnt < MAX_FIBRE_DEVICES &&
+                    !ha->loop_down_timer &&
+                    !ha->flags.loop_resync_needed; cnt++ ) {
+                    /* if this slot is used (i.e. loop ID 0 - 0xfe) */
+                    if( ha->fc_db[cnt].loop_id <= LAST_SNS_LOOP_ID ) {
+                        /* Get port name */
+                        mb[0] = MBC_GET_PORT_NAME;
+                        mb[1] = ha->fc_db[cnt].loop_id << 8 | BIT_0;
+                        if( qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) {
+                            /* Flag as missing only once */
+                            if ( !(ha->fc_db[cnt].flag & DEV_MISSING) ) {
+                               if ( ha->fc_db[cnt].port_login_retry_count ) {  /* v2.19.05b3 */
+                                  ha->fc_db[cnt].port_login_retry_count--;
+                                  ha->fc_db[cnt].flag |= DEV_MISSING;
+                                  DEBUG(printk("qla2100_sns: Missing port %d @ loop ID: %x\n",
+                                     cnt, ha->fc_db[cnt].loop_id);)
+                                  ret++;
+                               }
+                            } 
+                        } else if (ha->fc_db[cnt].flag & DEV_MISSING) {
+                             ha->fc_db[cnt].flag &= ~DEV_MISSING;
+                             ha->fc_db[cnt].flag &= ~DEV_OFFLINE;
+                             ha->fc_db[cnt].flag |= DEV_RETURN;
+                             ha->fc_db[cnt].port_login_retry_count = 8;
+                             DEBUG(printk("qla2100_sns: Device %d returned\n", cnt);)
+                        } 
+                      }
+                }
+                return( ret );
+}
+
+/*
+* qla2100_update_fc_db
+*      Updates Fibre Channel Device Database with what is actually on loop.
+*
+* Input:
+*      ha                = adapter block pointer.
+*      enable_slot_reuse = allows the use of PORT_AVAILABLE slots.
+*
+* Output:
+*      ha->fc_db = updated
+*
+* Returns:
+*      0 = success.
+*      1 = error.
+*      2 = database was full and device was not configured.
+*/
+STATIC uint8_t
+qla2100_update_fc_db(scsi_qla_host_t *ha, uint8_t enable_slot_reuse) {
+	uint8_t  status = 0;
+	uint8_t  ret = 0;
+	uint8_t  db_full = 0;
+	uint16_t cnt;
+	uint16_t mb[MAILBOX_REGISTER_COUNT];
+	port_list_entry_t *gn_list, *port_entry;
+	device_data_t device;
+#if BITS_PER_LONG > 32
+	uint64_t    phys_address = 0;
+#else
+	uint32_t    phys_address = 0;
+#endif
+	uint16_t i, size;
+	uint16_t localdevices = 0;
+	int retry_needed = 0;
+	
+#ifdef FC_IP_SUPPORT
+	PIP_DEVICE_BLOCK    pIpDevice;
+#endif
+
+
+#ifdef QL_DEBUG_LEVEL_3
+	ENTER("qla2100_update_fc_db");
+#endif
+
+	/* Configure loop */
+	if( !qla2100_configure_hba(ha) ) {
+	    if( ha->device_id == QLA2100_DEVICE_ID ) {
+	        ha->max_public_loop_ids = LAST_SNS_LOOP_ID - SNS_FIRST_LOOP_ID + 1;
+	    } else {
+	        ha->max_public_loop_ids = LAST_SNS_LOOP_ID + 1;
+	        /* dg 09/15 */
+	        /* if the topology have change then make all devices available */
+	        if( ha->prev_topology != ha->current_topology ) {
+	            /* Mark all fabric devices that where present as AVAILABLE */
+	            for( i = 0; i < ha->max_public_loop_ids; i++ )
+	                if( (i != SNS_FL_PORT) && (i != FABRIC_CONTROLLER)
+	                && (i != SIMPLE_NAME_SERVER) )
+	                    ha->fabricid[i].in_use = FALSE;
+
+	                /* Mark all local devices that where present as AVAILABLE */
+	                if( ha->current_topology == ISP_CFG_F )
+	                    for( cnt = 0; cnt < MAX_FIBRE_DEVICES && !ha->loop_down_timer
+	                    && !ha->flags.loop_resync_needed; cnt++ )
+	                        if( ha->fc_db[cnt].loop_id < SNS_FIRST_LOOP_ID ) {
+	                            ha->fc_db[cnt].loop_id = PORT_AVAILABLE;
+	                            ha->fc_db[cnt].flag &= ~DEV_PUBLIC;
+	                        }
+	        }
+	    }
+	    /* v2.19.03 - Mark all devices missing if configured */
+	    for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ )
+	             if( ha->fc_db[cnt].flag & DEV_CONFIGURED)
+	                ha->fc_db[cnt].flag |= DEV_MISSING;
+	
+#ifdef FC_IP_SUPPORT
+	    /* Disable all IP devices in linked list */
+	    for (pIpDevice = ha->pIpDeviceTop; pIpDevice != NULL;
+	      pIpDevice = pIpDevice->pNextIpDevice) {
+	        pIpDevice->lDeviceFlags &= ~IP_DEV_FLAG_PRESENT;
+	    }
+#endif /* FC_IP_SUPPORT */
+
+	    /* Configure local */
+	    /* Get the port list of devices on the local loop */
+/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	    gn_list = KMALLOC(GN_LIST_LENGTH);
+	    if ( gn_list != NULL ) {
+	         phys_address = VIRT_TO_BUS(gn_list);
+	         BZERO((caddr_t)gn_list, GN_LIST_LENGTH);
+	    }
+#else
+	    gn_list  = pci_alloc_consistent(ha->pdev,
+                                    GN_LIST_LENGTH,
+                                    &phys_address);
+	    BZERO((caddr_t)gn_list, GN_LIST_LENGTH);
+#endif
+	    if( gn_list != NULL ) {
+
+	        if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ) {
+	            /* Get port list.*/
+	            mb[0] = MBC_GET_PORT_LIST;
+#ifdef FC_IP_SUPPORT
+	            if (ha->flags.enable_ip == FALSE)
+	                mb[1] = BIT_0;      /* Bit 0 - return node names */
+	            else
+	                mb[1] = BIT_0|BIT_1;/* Bit 0 - return node names, Bit 1 - loop IDs 0-255 */
+#else
+	            mb[1] = BIT_0;
+#endif
+	            mb[3] = LSW(phys_address);
+	            mb[2] = MSW(phys_address);
+	            mb[7] = QL21_64BITS_3RDWD(phys_address);
+	            mb[6] = QL21_64BITS_4THWD(phys_address);
+	            if( !qla2100_mailbox_command(ha, BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]) ) {
+	                if ( mb[0] == MBS_COMMAND_COMPLETE ) {
+	                    port_entry = gn_list;
+	                    size = mb[1];
+	                    /* dg 10/29/99 - check for empty list */
+	                    if ( size/sizeof(port_list_entry_t) == 0 ) {
+	                        /* Local devices were present, but may not be reponding,
+	                        so retry them later */
+	                        DEBUG(qla2100_print("qla2100_update_fc_db: local port list - empty\n");)
+	                    } else
+	                        /* Scan through the port list and add devices to the database */
+	                        for( ; size >= sizeof(port_list_entry_t);
+	                        size -= sizeof(port_list_entry_t), port_entry++ ) {
+	                            /* Skip the known ports. */
+#ifdef FC_IP_SUPPORT
+	                            if( ((port_entry->loop_id & LOOP_ID_MASK) == SNS_FL_PORT) ||
+	                            ((port_entry->loop_id & LOOP_ID_MASK) == FABRIC_CONTROLLER) ||
+	                            ((port_entry->loop_id & LOOP_ID_MASK) == SIMPLE_NAME_SERVER) )
+#else
+	                                if( (port_entry->loop_id == SNS_FL_PORT) ||
+	                                (port_entry->loop_id == FABRIC_CONTROLLER) ||
+	                                (port_entry->loop_id == SIMPLE_NAME_SERVER) )
+#endif
+	                                    continue;
+
+	                                /* if we are on a public loop then logout the public devices. */
+	                                if( ((ha->current_topology == ISP_CFG_FL)
+	                                || (ha->current_topology == ISP_CFG_F))
+#ifdef FC_IP_SUPPORT
+	                                && !(port_entry->loop_id & PLE_NOT_SCSI_DEVICE)
+	                                && ((port_entry->loop_id & LOOP_ID_MASK) >= ha->min_external_loopid)) {
+#else
+	                                    && (port_entry->loop_id >= ha->min_external_loopid) ) {
+#endif
+	                                        mb[0] = MBC_LOGOUT_FABRIC_PORT;
+#ifdef FC_IP_SUPPORT
+	                                        mb[1] = (port_entry->loop_id & LOOP_ID_MASK) << 8;
+#else
+	                                        mb[1] = port_entry->loop_id << 8;
+#endif
+	                                        qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+	                                    } else {
+	                                        /* We are on a local loop             */
+	                                        /* update the database with the loop  */
+	                                        /* ID and login to the device.        */
+#ifdef FC_IP_SUPPORT
+	                                        device.loop_id = port_entry->loop_id & LOOP_ID_MASK;
+#else
+	                                        device.loop_id = port_entry->loop_id;
+#endif
+
+#if USE_PORTNAME
+	                                        /* Get port name */
+	                                        mb[0] = MBC_GET_PORT_NAME;
+	                                        /* mb[1] = device.loop_id << 8 | BIT_0; */
+	                                        mb[1] = device.loop_id << 8;
+	                                        if( !qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]) ) {
+	                                            /* dg 09/15/99  */
+	                                            if ( mb[0] == MBS_COMMAND_COMPLETE ) {
+	                                                /* tt 1/18/00 */
+	                                                mb[2] = (mb[2] & 0x00FF) << 8 | mb[2] >> 8;
+	                                                mb[3] = (mb[3] & 0x00FF) << 8 | mb[3] >> 8;
+	                                                mb[6] = (mb[6] & 0x00FF) << 8 | mb[6] >> 8;
+	                                                mb[7] = (mb[7] & 0x00FF) << 8 | mb[7] >> 8;
+
+							BCOPY(&mb[7], &device.wwn[0], 2);
+							BCOPY(&mb[6], &device.wwn[2], 2);
+							BCOPY(&mb[3], &device.wwn[4], 2);
+							BCOPY(&mb[2], &device.wwn[6], 2);
+	                                            } else {
+	                                                status = 1;
+	                                                printk(KERN_WARNING "qla2100_update_fc_db: [ERROR] GET PORT NAME - bad status.\n");
+	                                                goto qla2100_update_fc_db_exit;
+	                                            }
+
+	                                        } else {   /* dg 10/29/99 */
+	                                            if ( mb[0] == MBS_FATAL_ERROR  ) {
+	                                                status = 1;
+	                                                goto qla2100_update_fc_db_exit;
+	                                            }
+	                                            continue;
+	                                        }
+#endif
+	                                        /* Get the node name */
+						BCOPY(port_entry->name, device.name, 8);
+
+
+#ifdef FC_IP_SUPPORT
+	                                        if (!(port_entry->loop_id & PLE_NOT_SCSI_DEVICE)) {
+	                                            /* SCSI type device */
+	                                            DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: SCSI device at ID %x\n\r",
+	                                            device.loop_id));
+	                                            DEBUG(qla2100_print(debug_buff));
+#endif
+	                                            if( (status = qla2100_update_device_data(ha, &device, enable_slot_reuse)) ) {
+	                                                /* if not configured or full */
+	                                                if( status == 2 )
+	                                                    db_full = 1;
+	                                                else
+	                                                    break;
+	                                            } else
+	                                                localdevices++;
+#ifdef FC_IP_SUPPORT
+	                        } else if (ha->flags.enable_ip == TRUE) {
+	                                    /* SCSI login failed, assume it is IP device */
+	                                    DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: IP device at ID %x\n\r",
+	                                    device.loop_id));
+	                                    DEBUG(qla2100_print(debug_buff));
+
+	                                    /* Update IP device database */
+	                                    if (qla2x00_update_ip_device_data(ha, &device) == QL_STATUS_SUCCESS) {
+	                                        localdevices++;
+	                                    } else {
+	                                        status = 1;
+	                                        break;
+	                                    }
+	                                 }
+#endif
+	                    }
+	                             }  /* end of For */
+	                           }
+	                        }
+	                }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+	                KMFREE(gn_list, GN_LIST_LENGTH);
+#else
+	                pci_free_consistent(ha->pdev, GN_LIST_LENGTH,
+                                    gn_list, phys_address);
+#endif
+	                /*
+	                * if topology is a direct attached local loop then
+	                * don't serach for public devices, unless its a 2100.
+	                */
+	                if( ((ha->current_topology == ISP_CFG_N) ||
+	                (ha->current_topology == ISP_CFG_NL)) &&
+	                ha->device_id != QLA2100_DEVICE_ID ) {  /* 2/21/00 - dg */
+	                    ha->prev_topology = ha->current_topology;
+	                } else {
+	                    /* dgER - we need to add logic to register 
+	                     * our adapter with the Name server, so we
+	                     * can send Command Transport commands (FC4).
+	                     * (target mode)
+	                     */
+ 
+	                    /* get public loop devices */
+	                    if( !ha->loop_down_timer && !ha->flags.loop_resync_needed ){
+	                         /* v2.19.5 */
+	                        if( (ret = qla2100_sns_device(ha, enable_slot_reuse)) == 2 )
+	                            db_full = 1;
+	                         /* v2.19.5b3 */
+	                        if( ret == 1 ) {
+	                          if( ha->device_id != QLA2100_DEVICE_ID ) {
+	                            status = ret;
+	                            ha->sns_retry_cnt++;
+	                            if( ha->sns_retry_cnt > 8 ) {
+	                               if( !(ha->dpc_flags & ISP_RESET_ONCE) )
+	                                 ha->dpc_flags |= ISP_RESET_NEEDED;
+	                            }
+	                            else
+	                              retry_needed++;
+	                          }
+				}
+	                     }
+ 
+	                }
+
+	                /* Set local loop devices present flag, clear retry flag */
+	                if (localdevices > 0 ) {
+	                    ha->device_flags |= DFLG_LOCAL_DEVICES;
+	                    ha->device_flags &= ~DFLG_RETRY_LOCAL_DEVICES;
+	                }
+
+	            if( qla2100_check_devices(ha) ){
+	               DEBUG(printk("qla2100: Devices are missing or configured - retrying\n");)
+	                retry_needed++;
+			}
+#ifdef FC_IP_SUPPORT
+	            /* Clean up active IP device list */
+	            for (pIpDevice = ha->pIpDeviceBottom; pIpDevice != NULL;
+	            pIpDevice = pIpDevice->pLastIpDevice) {
+	                if (!(pIpDevice->lDeviceFlags & IP_DEV_FLAG_PRESENT)) {
+	                    /* Device not present, remove it from list and free resources */
+	                    DEBUG(sprintf(debug_buff, "qla2100_update_fc_db: removing IP device, loop ID: %x, port ID: %x\n\r",
+	                    pIpDevice->wLoopId,
+	                    pIpDevice->acPortId[0]<<16 | pIpDevice->acPortId[1]<<8 | pIpDevice->acPortId[2]));
+	                    DEBUG(qla2100_print(debug_buff));
+
+	                    if (pIpDevice->lDeviceFlags & IP_DEV_FLAG_PUBLIC_DEVICE) {
+	                        /* Do fabric logout and free loop ID */
+	                        if (qla2x00_logout_public_device(ha, pIpDevice->wLoopId, 0) == QL_STATUS_FATAL_ERROR) {
+	                            status = 1;
+	                            break;
+	                        }
+	                        qla2x00_free_loopid(ha, pIpDevice->wLoopId);
+	                    }
+	                    qla2x00_free_ip_block(ha, pIpDevice);
+	                }
+	            }
+#endif /* FC_IP_SUPPORT */
+
+	        } else {
+#ifdef QL_DEBUG_LEVEL_2
+	            qla2100_print(
+	            "qla2100_update_fc_db: Failed to allocate memory, No local loop\n");
+#endif
+	            status = 1;
+	        }
+	        /* Map the devices to target IDs */
+	        if( !ha->loop_down_timer && !ha->flags.loop_resync_needed )
+	            qla2100_map_targets(ha);
+	    } else
+	        status = 1;
+
+	    if( db_full )
+	        status = 2;
+
+	    if( retry_needed ) {
+	        ha->device_flags |= LOGIN_RETRY_NEEDED;
+	        /* v2.19.5 */
+	        status = 1;
+	    }
+
+	    qla2100_update_fc_db_exit:
+
+	    if( status == 0 ) {
+	        ha->loop_state = LOOP_READY;
+	        ha->sns_retry_cnt = 0;
+	        for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ )
+	          ha->fc_db[cnt].port_login_retry_count = 8;
+	        DEBUG(printk("qla2100_update_fc_db: LOOP READY\n");)
+	    }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+	if( status )
+		qla2100_print("qla2100_update_fc_db: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+	else
+		LEAVE("qla2100_update_fc_db");
+#endif
+	return(status);
+}
+
+/*
+* qla2100_init_tgt_map
+*      Initializes target map.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Output:
+*      TGT_Q initialized
+*/
+STATIC void
+qla2100_init_tgt_map(scsi_qla_host_t *ha) {
+                uint32_t b, t;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_init_tgt_map");
+#endif
+
+                for( b = 0; b < MAX_BUSES; b++ )
+                    for( t = 0; t < MAX_FIBRE_DEVICES; t++ )
+                        TGT_Q(ha, b, t) = (tgt_t *) NULL;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    LEAVE("qla2100_init_tgt_map");
+#endif
+}
+
+/*
+* qla2100_map_targets
+*      Setup target queues.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_map_targets(scsi_qla_host_t *ha) {
+                tgt_t    *tgt;
+                uint32_t b;
+                uint32_t t;
+                uint8_t  status = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_map_targets");
+#endif
+
+                b = 0;
+                for( t = 0; t < MAX_FIBRE_DEVICES; t++ ) {
+                    /* if Port never been used. OR */
+                    /*  Device does not exist on port. */
+                    if( ha->fc_db[t].loop_id != PORT_UNUSED  &&
+                    ha->fc_db[t].loop_id != PORT_AVAILABLE ) {  /* dg 10/29/99 */
+
+                        if( (tgt = TGT_Q(ha, b, t)) != NULL ) {
+                            DEBUG2(sprintf(debug_buff,"Target %d already allocated\n",t));
+                            DEBUG2(qla2100_print(debug_buff));
+                        } else
+                            tgt = qla2100_tgt_alloc(ha);
+                        DEBUG(sprintf(debug_buff,"Assigning target ID %02x:%02x @ (%08x) to loop id: 0x%04x\n",b,t,tgt,ha->fc_db[t].loop_id);)
+                        DEBUG(qla2100_print(debug_buff));
+                        TGT_Q(ha, b, t) = tgt;
+                        tgt->loop_id = ha->fc_db[t].loop_id;
+                        tgt->down_timer = 0;
+                    }
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_map_targets: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_map_targets");
+#endif
+                return(status);
+}
+#if USE_FLASH
+/*
+* qla2100_get_database
+*      Copies and converts flash database to driver database.
+*      (may sleep)
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_get_database(scsi_qla_host_t *ha) {
+                flash_database_t *fptr;
+                uint8_t          status = 1;
+                uint32_t         addr;
+                uint16_t         cnt;
+                uint8_t          *bptr;
+                uint8_t          checksum;
+                uint32_t         b, t;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_get_database");
+#endif
+
+                /* Default setup. */
+                ha->flash_db = FLASH_DATABASE_0;
+                ha->flash_seq = 0;
+
+                if( (fptr = (flash_database_t *)KMALLOC(sizeof(flash_database_t))) ) {
+                    /* Enable Flash Read/Write. */
+                    qla2100_flash_enable(ha);
+
+                    /* Start with flash database with the highest sequence number. */
+                    b = qla2100_read_flash_byte(ha, FLASH_DATABASE_0);
+                    b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 8;
+                    b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 16;
+                    b |= qla2100_read_flash_byte(ha, FLASH_DATABASE_0 + 1) << 24;
+                    t = qla2100_read_flash_byte(ha, FLASH_DATABASE_1);
+                    t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 8;
+                    t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 16;
+                    t |= qla2100_read_flash_byte(ha, FLASH_DATABASE_1 + 1) << 24;
+                    if( t > b ) {
+                        ha->flash_db = FLASH_DATABASE_1;
+                    }
+
+                    /* Select the flash database with the good checksum. */
+                    for( t = 0; t < 2; t++ ) {
+                        checksum = 0;
+                        addr = ha->flash_db;
+                        bptr = (uint8_t *)fptr;
+                        fptr->hdr.size = sizeof(flash_database_t);
+
+                        /* Read flash database to driver. */
+                        for( cnt = 0; cnt < fptr->hdr.size; cnt++ ) {
+                            *bptr = (uint8_t)qla2100_read_flash_byte(ha, addr++);
+                            checksum += *bptr++;
+                            if( bptr == &fptr->hdr.spares[0] &&
+                            (fptr->hdr.size > sizeof(flash_database_t) ||
+                            fptr->hdr.size < sizeof(flash_hdr_t) ||
+                            !fptr->hdr.version) ) {
+                                checksum = 1;
+                                break;
+                            }
+                        }
+
+                        if( !checksum ) {
+                            status = 0;
+                            break;
+                        }
+                        /* trying other database */
+                        if( ha->flash_db == FLASH_DATABASE_0 ) {
+                            ha->flash_db = FLASH_DATABASE_1;
+                        } else {
+                            ha->flash_db = FLASH_DATABASE_0;
+                        }
+                    }
+
+                    if( !status ) {
+                        ha->flash_seq = fptr->hdr.seq;
+
+                        /* Convert flash database to driver database format. */
+                        if( fptr->hdr.size -= sizeof(flash_hdr_t) ) {
+                            for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) {
+                                ha->fc_db[cnt].name[0] = fptr->node[cnt].name[0];
+                                ha->fc_db[cnt].name[1] = fptr->node[cnt].name[1];
+                                cnt,
+                                ha->fc_db[cnt].name[1],
+                                ha->fc_db[cnt].name[0]);
+
+                                ha->fc_db[cnt].loop_id = PORT_AVAILABLE;
+                                ha->fc_db[cnt].flag = 0;  /* v2.19.05b3 */
+                                if( !(fptr->hdr.size -= sizeof(flash_node_t)) )
+                                    break;
+                            }
+                        }
+                    }
+
+                    qla2100_flash_disable(ha);
+
+                    KMFREE(fptr, sizeof(flash_database_t));
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_get_database: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_get_database");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_save_database
+*      Copies and converts driver database to flash database.
+*      (may sleep)
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_save_database(scsi_qla_host_t *ha) {
+                flash_database_t *fptr;
+                uint8_t          status = 1;
+                uint32_t         addr;
+                uint16_t         cnt;
+                uint8_t          *bptr;
+                uint8_t          checksum;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_save_database");
+#endif
+
+                if( (fptr = (flash_database_t *)KMALLOC(sizeof(flash_database_t)) ) ) {
+                    /* Enable Flash Read/Write. */
+                    qla2100_flash_enable(ha);
+
+                    fptr->hdr.seq     = ++ha->flash_seq;
+                    fptr->hdr.version = FLASH_DATABASE_VERSION;
+                    fptr->hdr.size    = sizeof(flash_hdr_t);
+
+                    /* Copy and convert driver database to flash database. */
+                    for( cnt = 0; cnt < MAX_FIBRE_DEVICES; cnt++ ) {
+                        if( ha->fc_db[cnt].loop_id == PORT_UNUSED )
+                            break;
+                        else {
+                            fptr->node[cnt].name[0] = ha->fc_db[cnt].name[0];
+                            fptr->node[cnt].name[1] = ha->fc_db[cnt].name[1];
+                            fptr->hdr.size += sizeof(flash_node_t);
+                        }
+                    }
+
+                    /* Calculate checksum. */
+                    checksum = 0;
+                    bptr = (uint8_t *)fptr;
+                    for( cnt = 0; cnt < fptr->hdr.size; cnt++ )
+                        checksum += *bptr++;
+                    fptr->hdr.checksum = ~checksum + 1;
+
+                    /* Setup next sector address for flash */
+                    if( ha->flash_db == FLASH_DATABASE_0 )
+                        addr = FLASH_DATABASE_1;
+                    else
+                        addr = FLASH_DATABASE_0;
+                    ha->flash_db = addr;
+
+                    /* Erase flash sector prior to write. */
+                    status = qla2100_erase_flash_sector(ha, addr);
+
+                    /* Write database to flash. */
+                    bptr = (uint8_t *)fptr;
+                    for( cnt = 0; cnt < fptr->hdr.size && !status; cnt++ )
+                        status = qla2100_program_flash_address(ha, addr++, *bptr++);
+
+                    qla2100_flash_disable(ha);
+
+                    KMFREE(fptr, sizeof(flash_database_t));
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_save_database: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_save_database");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_program_flash_address
+*      Program flash address.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      addr = flash byte address.
+*      data = data to be written to flash.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) {
+                uint8_t status;
+
+                /* Write Program Command Sequence */
+                qla2100_write_flash_byte(ha, 0x5555, 0xaa);
+                qla2100_write_flash_byte(ha, 0x2aaa, 0x55);
+                qla2100_write_flash_byte(ha, 0x5555, 0xa0);
+                qla2100_write_flash_byte(ha, addr, data);
+
+                /* Wait for write to complete. */
+                status = qla2100_poll_flash(ha, addr, data);
+
+#ifdef QL_DEBUG_LEVEL_2
+                if( status )
+                    qla2100_print("qla2100_program_flash_address: **** FAILED ****\n");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_erase_flash_sector
+*      Erases flash sector.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      addr = sector address.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr) {
+                uint8_t status;
+
+                addr &= 0x1c000;
+
+                /* Individual Sector Erase Command Sequence */
+                qla2100_write_flash_byte(ha, 0x5555, 0xaa);
+                qla2100_write_flash_byte(ha, 0x2aaa, 0x55);
+                qla2100_write_flash_byte(ha, 0x5555, 0x80);
+                qla2100_write_flash_byte(ha, 0x5555, 0xaa);
+                qla2100_write_flash_byte(ha, 0x2aaa, 0x55);
+                qla2100_write_flash_byte(ha, addr, 0x30);
+
+                SYS_DELAY(150);
+
+                /* Wait for erase to complete. */
+                status = qla2100_poll_flash(ha, addr, 0x80);
+
+#ifdef QL_DEBUG_LEVEL_2
+                if( status )
+                    qla2100_print("qla2100_erase_flash_sector: **** FAILED ****\n");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_poll_flash
+*      Polls flash for completion.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      addr = flash byte address.
+*      data = data to be polled.
+*
+* Returns:
+*      0 = success.
+*/
+STATIC uint8_t
+qla2100_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data) {
+                uint8_t  status = 1;
+                uint8_t  flash_data;
+                uint32_t cnt;
+
+                poll_data &= BIT_7;
+
+                /* Wait for 30 seconds for command to finish. */
+                for( cnt = 3000000; cnt; cnt-- ) {
+                    flash_data = (uint8_t)qla2100_read_flash_byte(ha, addr);
+
+                    if( (flash_data & BIT_7) == poll_data ) {
+                        status = 0;
+                        break;
+                    }
+                    if( flash_data & BIT_5 && cnt > 2 )
+                        cnt = 2;
+                    SYS_DELAY(10);
+                }
+
+                return(status);
+}
+
+/*
+* qla2100_flash_enable
+*      Setup flash for reading/writing.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_flash_enable(scsi_qla_host_t *ha) {
+                device_reg_t *reg = ha->iobase;
+
+                /* Setup bit 16 of flash address. */
+                WRT_REG_WORD(&reg->nvram, NV_SELECT);
+
+                /* Enable Flash Read/Write. */
+                WRT_REG_WORD(&reg->ctrl_status, ISP_FLASH_ENABLE);
+
+                /* Read/Reset Command Sequence */
+                qla2100_write_flash_byte(ha, 0x5555, 0xaa);
+                qla2100_write_flash_byte(ha, 0x2aaa, 0x55);
+                qla2100_write_flash_byte(ha, 0x5555, 0xf0);
+                qla2100_read_flash_byte(ha, FLASH_DATABASE_0);
+}
+
+/*
+* qla2100_flash_disable
+*      Disable flash and allow RISC to run.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_flash_disable(scsi_qla_host_t *ha) {
+                device_reg_t *reg = ha->iobase;
+
+                /* Restore chip registers. */
+                WRT_REG_WORD(&reg->ctrl_status, 0);
+                WRT_REG_WORD(&reg->nvram, 0);
+}
+
+/*
+* qla2100_write_flash_byte
+*      Write byte to flash.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      addr = flash byte address.
+*      data = data to be written.
+*/
+STATIC void
+qla2100_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) {
+                device_reg_t *reg = ha->iobase;
+
+                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
+                WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
+}
+
+/*
+* qla2100_read_flash_byte
+*      Reads byte from flash, but must read a word from chip.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      addr = flash byte address.
+*
+* Returns:
+*      byte from flash.
+*/
+STATIC uint16_t
+qla2100_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) {
+                device_reg_t *reg = ha->iobase;
+                uint16_t     data;
+
+                WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
+                data = qla2100_debounce_register(&reg->flash_data);
+
+                return(data);
+}
+#endif
+
+/*
+* qla2100_reset_adapter
+*      Reset adapter.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_reset_adapter(scsi_qla_host_t *ha) {
+                device_reg_t *reg = ha->iobase;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_reset_adapter");
+#endif
+
+                ha->flags.online = FALSE;
+                qla2100_disable_intrs(ha);
+                /* WRT_REG_WORD(&reg->ictrl, 0); */
+                /* Reset RISC processor. */
+                WRT_REG_WORD(&reg->host_cmd, HC_RESET_RISC);
+                WRT_REG_WORD(&reg->host_cmd, HC_RELEASE_RISC);
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_reset_adapter");
+#endif
+}
+
+/*
+* qla2100_loop_reset
+*      Issue loop reset.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_loop_reset(scsi_qla_host_t *ha) {
+                uint8_t  status = 0;
+                uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_loop_reset");
+#endif
+
+                if( ha->flags.enable_lip_reset ) {
+                    mb[0] = MBC_LIP_RESET;
+                    mb[1] = 0xff00;
+                    mb[2] = ha->loop_reset_delay;
+                    status |= qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]);
+                }
+                if( ha->flags.enable_target_reset ) {
+                    mb[0] = MBC_TARGET_RESET;
+                    mb[1] = ha->loop_reset_delay;
+                    status |= qla2100_mailbox_command(ha, BIT_1|BIT_0, &mb[0]);
+                }
+                if( (!ha->flags.enable_target_reset && !ha->flags.enable_lip_reset ) ||
+                ha->flags.enable_lip_full_login ) {
+                    mb[0] = MBC_LIP_FULL_LOGIN;
+                    status |= qla2100_mailbox_command(ha, BIT_0, &mb[0]);
+                }
+
+                /* Issue marker command. */
+                qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_loop_reset: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_loop_reset");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_device_reset
+*      Issue bus device reset message to the target.
+*
+* Input:
+*      ha = adapter block pointer.
+*      b  = BUS number.
+*      t  = SCSI ID.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_device_reset(scsi_qla_host_t *ha, uint32_t b, uint32_t t) {
+                tgt_t    *tgt;
+                uint8_t  status;
+                uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_device_reset");
+#endif
+
+                tgt =  TGT_Q(ha, b, t);
+
+                mb[0] = MBC_ABORT_TARGET;
+                mb[1] = tgt->loop_id << 8;
+                mb[2] = 1;
+                status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]);
+
+                /* Issue marker command. */
+                qla2100_marker(ha, b, t, 0, MK_SYNC_ID);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_device_reset: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_device_reset");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_abort_device
+*      Issue an abort message to the device
+*
+* Input:
+*      ha = adapter block pointer.
+*      b  = BUS number.
+*      t  = SCSI ID.
+*      l  = SCSI LUN.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_abort_device(scsi_qla_host_t *ha, uint32_t b, uint32_t t, uint32_t l) {
+                tgt_t    *tgt;
+                uint8_t  status;
+                uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_abort_device");
+#endif
+
+                tgt = TGT_Q(ha, b, t);
+
+                mb[0] = MBC_ABORT_DEVICE;
+                mb[1] = tgt->loop_id << 8;
+                mb[2] = l;
+                status = qla2100_mailbox_command(ha, BIT_2|BIT_1|BIT_0, &mb[0]);
+
+                /* Issue marker command. */
+                qla2100_marker(ha, b, t, l, MK_SYNC_ID_LUN);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2100_abort_device: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_abort_device");
+#endif
+                return(status);
+}
+
+/*
+* qla2100_abort_command
+*      Abort command aborts a specified IOCB.
+*
+* Input:
+*      ha = adapter block pointer.
+*      sp = SB structure pointer.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_abort_command(scsi_qla_host_t *ha, srb_t *sp) {
+                uint8_t        status;
+                uint16_t       mb[MAILBOX_REGISTER_COUNT];
+                uint32_t       b, t, l;
+                uint32_t       handle;
+                tgt_t          *tgt;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_abort_command");
+#endif
+		/* v2.19.8 */
+                t  = SCSI_TCN_32(sp->cmd);
+                if( ha->loop_state == LOOP_DOWN ||
+                       PORT_DOWN(ha,t) > 0 ) {
+                    return(0);
+                }
+
+                /* Locate handle number. */
+                for( handle = 0; handle < MAX_OUTSTANDING_COMMANDS; handle++ )
+                    if( ha->outstanding_cmds[handle] == sp )
+                        break;
+
+                    DEBUG(qla2100_print("qla2100_abort_command: Sending Abort Command for Handle =  ");)
+                    DEBUG(qla2100_output_number((u_long) handle, 16);)
+                    DEBUG(qla2100_print("\n");)
+
+                    /* Get a pointer to the SCSI address */
+                    b  = SCSI_BUS_32(sp->cmd);
+                    l  = SCSI_LUN_32(sp->cmd);
+
+                    tgt = TGT_Q(ha, b, t);
+
+                    mb[0] = MBC_ABORT_COMMAND;
+                    mb[1] = tgt->loop_id << 8;
+                    mb[2] = (uint16_t)handle;
+                    mb[3] = handle >> 16;
+                    mb[6] = l;
+                    if( !(status = qla2100_mailbox_command(ha, BIT_6|BIT_3|BIT_2|BIT_1|BIT_0,
+                    &mb[0])) )
+                        sp->flags |= SRB_ABORT_PENDING;
+
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                    if( status )
+                        qla2100_print("qla2100_abort_command: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                    else
+                        LEAVE("qla2100_abort_command");
+#endif
+                    return(status);
+}
+
+/*
+*  Issue marker command.
+*      Function issues marker IOCB.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      b    = BUS number.
+*      t    = SCSI ID
+*      l    = SCSI LUN
+*      type = marker modifier
+*/
+STATIC void
+qla2100_marker(scsi_qla_host_t *ha, uint32_t b, uint32_t t, uint32_t l, uint8_t type) {
+                mrk_entry_t *pkt;
+                tgt_t       *tgt;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_marker");
+#endif
+
+                tgt = TGT_Q(ha, b, t);
+
+                /* Get request packet. */
+                if( (pkt = (mrk_entry_t *)qla2100_req_pkt(ha) ) ) {
+                    pkt->entry_type = MARKER_TYPE;
+                    pkt->modifier = type;
+
+                    if( type == MK_SYNC_LIP )
+                        pkt->sequence_number = ha->lip_seq;
+                    else if( type != MK_SYNC_ALL ) {
+                        pkt->lun = l;
+                        pkt->target = (uint8_t)tgt->loop_id;
+                    }
+
+                    /* Issue command to ISP */
+                    qla2100_isp_cmd(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_marker: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_marker");
+#endif
+}
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,18)
+/*
+* qla2100_64bit_start_scsi
+*      The start SCSI is responsible for building request packets on
+*      request ring and modifying ISP input pointer.
+*
+* Input:
+*      ha = adapter block pointer.
+*      sp = SB structure pointer.
+*
+* Returns:
+*      0 = success, was able to issue command.
+*/
+STATIC uint8_t
+qla2100_64bit_start_scsi(scsi_qla_host_t *ha, srb_t *sp) {
+                device_reg_t        *reg       = ha->iobase;
+                device2300_reg_t    *reg2300   = ha->iobase2300;
+                uint8_t         status = 0;
+                Scsi_Cmnd       *cmd = sp->cmd;
+                uint32_t        cnt;
+                cmd_a64_entry_t     *pkt;
+                uint16_t        req_cnt;
+                uint16_t        seg_cnt;
+                uint16_t        cdb_len,temp;
+                struct scatterlist    *sg = (struct scatterlist *) NULL;
+                uint32_t        timeout;
+                caddr_t         data_ptr;
+                uint32_t        *dword_ptr;
+                uint64_t        dma_handle;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_64bit_start_scsi:");
+#endif
+                DEBUG(sprintf(debug_buff,
+                 "64bit_start: cmd=%x sp=%x CDB=%x\n\r",cmd,sp,cmd->cmnd[0]);)
+                DEBUG(qla2100_print(debug_buff));
+
+                /* Calculate number of entries and segments required. */
+                seg_cnt = 0;
+                req_cnt = 1;
+                if ( cmd->use_sg ) { 
+                    /* 4.10 64 bit S/G Data Transfer */
+                    sg = (struct scatterlist *) cmd->request_buffer;
+                    seg_cnt = pci_map_sg(ha->pdev,
+                               sg,cmd->use_sg, 
+                               scsi_to_pci_dma_dir(cmd->sc_data_direction));
+
+                    if( seg_cnt > 2 ) {
+                        req_cnt += (uint16_t)(seg_cnt - 2) / 5;
+                        if( (uint16_t)(seg_cnt - 2) % 5 )
+                            req_cnt++;
+                    }
+                } else if( cmd->request_bufflen )
+                {   /* no S/G Data Transfer */
+                    /* DEBUG5(printk("Single data transfer (0x%x)\n",
+                    cmd->request_bufflen)); */
+                    seg_cnt = 1;
+                }
+
+                /* Acquire ring specific lock */
+                QLA2100_RING_LOCK(ha);
+
+                if( (uint16_t)(req_cnt + 2) >= ha->req_q_cnt ) {
+                    /* Calculate number of free request q out entries. */
+                    if (ha->device_id == QLA2300_DEVICE_ID)  cnt = RD_REG_WORD(&reg2300->req_q_out);
+                    else                                     cnt = RD_REG_WORD(&reg->mailbox4);
+                    if( ha->req_ring_index < cnt )
+                        ha->req_q_cnt = cnt - ha->req_ring_index;
+                    else
+                        ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
+                }
+
+                /* If room for request in request ring. */
+                if( (uint16_t)(req_cnt + 2) < ha->req_q_cnt ) {
+                    /* Check for room in outstanding command list. */
+                    for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS &&
+                    ha->outstanding_cmds[cnt] != 0; cnt++ )
+                        ;
+
+                    if( cnt < MAX_OUTSTANDING_COMMANDS ) {
+                        ha->outstanding_cmds[cnt] = sp;
+                        ha->req_q_cnt -= req_cnt;
+                        CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt;
+
+                        /*
+                        * Build command packet.
+                        */
+                        pkt = ha->request_ring_ptr;
+
+                        pkt->entry_type = COMMAND_A64_TYPE;
+                        pkt->entry_count = (uint8_t)req_cnt;
+                        pkt->sys_define = (uint8_t)ha->req_ring_index;
+                        pkt->control_flags= 0;
+                        pkt->entry_status = 0;
+                        pkt->handle = (uint32_t)cnt;
+
+                        /* Zero out remaining portion of packet. */
+                        dword_ptr = (uint32_t *)pkt + 2;
+                        for( cnt = 2; cnt < REQUEST_ENTRY_SIZE/4; cnt++ )
+                            *dword_ptr++ = 0;
+
+                        /*
+                        * We subtract 2 sec. from the timeout value to insure
+                        * the ISP time-out before the mid-level or the driver.
+                        */
+                        timeout = (uint32_t) CMD_TIMEOUT(cmd)/HZ;
+                        if( timeout > 2 )
+                            pkt->timeout = (uint16_t) timeout - 2;
+                        else
+                            pkt->timeout = (uint16_t) timeout;
+
+                        /* Set device target ID and LUN */
+                        pkt->target = TGT_Q(ha, SCSI_BUS_32(cmd), 
+                                      SCSI_TCN_32(cmd))->loop_id;
+                        pkt->lun = SCSI_LUN_32(cmd);
+
+                        /* Enable simple tag queuing if device supports it. */
+                        if ( cmd->device->tagged_queue ) {
+                            switch (cmd->tag) {
+                                case SIMPLE_QUEUE_TAG:
+                                    pkt->control_flags = CF_SIMPLE_TAG;
+                                    break;
+                                case HEAD_OF_QUEUE_TAG:
+                                    pkt->control_flags = CF_HEAD_TAG;
+                                    break;
+                                case ORDERED_QUEUE_TAG:
+                                    pkt->control_flags = CF_ORDERED_TAG;
+                                    break;
+                                default:
+                                    pkt->control_flags = CF_SIMPLE_TAG;
+                            }
+                        } else
+                            pkt->control_flags = CF_SIMPLE_TAG;
+
+                       if (ha->device_id == QLA2300_DEVICE_ID)
+                           pkt->control_flags |= CF_NO_FAST_POSTING; 
+
+                        /* Load SCSI command packet. */
+                        cdb_len = (uint16_t)CMD_CDBLEN(cmd);
+                        if (cdb_len > MAX_CMDSZ) cdb_len = MAX_CMDSZ;
+                        data_ptr = (uint8_t *) &(CMD_CDBP(cmd));
+                        for( cnt = 0; cnt < cdb_len; cnt++ )
+                            pkt->scsi_cdb[cnt] = *data_ptr++;
+                        pkt->byte_count = (uint32_t) CMD_XFRLEN(cmd);
+
+                        /*
+                        * Load data segments.
+                        */
+                        if( seg_cnt )                /* If data transfer. */
+                        {
+                            switch( cmd->data_cmnd[0] ) {
+                                case FORMAT_UNIT:
+                                case WRITE_6:
+                                case MODE_SELECT:
+                                case SEND_DIAGNOSTIC:
+                                case WRITE_10:
+                                case WRITE_BUFFER:
+                                case WRITE_LONG:
+                                case WRITE_SAME:
+                                case MODE_SELECT_10:
+                                case WRITE_12:
+                                case WRITE_VERIFY_12:
+                                case SEND_VOLUME_TAG:
+                                    pkt->control_flags |= BIT_6; /* WRITE */
+                                    break;
+                                default:
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
+#if QLA_SCSI_VENDOR_DIR
+    				    qla2100_set_vend_direction(ha, cmd, pkt);
+#else
+                                    pkt->control_flags |= BIT_5; /* READ */
+#endif
+#else  /* kernel version is 2.4.0 or higher */
+                                    if (cmd->sc_data_direction == SCSI_DATA_WRITE)
+                                        pkt->control_flags |= BIT_6;/*WRITE*/
+                                    else 
+                                        pkt->control_flags |= BIT_5;/*READ*/
+#endif /* kernel version 2.4.0 */
+                                    break;
+                            }
+                            sp->dir = pkt->control_flags & (BIT_5|BIT_6);
+ 
+                            /* Set total data segment count. */
+                            pkt->dseg_count = seg_cnt;
+
+                            /* Setup packet address segment pointer. */
+                            dword_ptr = (uint32_t *)&pkt->dseg_0_address;
+
+                            if( cmd->use_sg )              /* If scatter gather */
+                            {
+                                /* Load command entry data segments. */
+                                for( cnt = 0; cnt < 2 && seg_cnt; cnt++, seg_cnt-- ) {
+                                    /* 4.10 64 bit */
+                                    *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                                    *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg)));
+                                    *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                                    sg++;
+                                      /* DEBUG(sprintf(debug_buff,
+                                      "S/G Segment phys_addr=%x %x, len=0x%x\n\r",
+                                      cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))),
+                                      cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                                      cpu_to_le32(sg_dma_len(sg)));)
+                                      DEBUG(qla2100_print(debug_buff)); */
+                                }
+#ifdef QL_DEBUG_LEVEL_5
+                                qla2100_print(
+                                "qla2x00_64bit_start_scsi: Scatter/gather command packet data - ");
+                                qla2100_print("b");
+                                qla2100_output_number((uint32_t)SCSI_BUS_32(cmd), 10);
+                                qla2100_print("t");
+                                qla2100_output_number((uint32_t)SCSI_TCN_32(cmd), 10);
+                                qla2100_print("d");
+                                qla2100_output_number((uint32_t)SCSI_LUN_32(cmd), 10);
+                                qla2100_print("\n\r");
+                                qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                                /*
+                                * Build continuation packets.
+                                */
+                                while( seg_cnt > 0 ) {
+                                    /* Adjust ring index. */
+                                    ha->req_ring_index++;
+                                    if( ha->req_ring_index == REQUEST_ENTRY_CNT ) {
+                                        ha->req_ring_index = 0;
+                                        ha->request_ring_ptr = ha->request_ring;
+                                    } else
+                                        ha->request_ring_ptr++;
+
+                                    pkt = (cmd_a64_entry_t *)ha->request_ring_ptr;
+
+                                    /* Zero out packet. */
+                                    dword_ptr = (uint32_t *)pkt;
+                                    for( cnt = 0;cnt < REQUEST_ENTRY_SIZE/4; cnt++ )
+                                        *dword_ptr++ = 0;
+
+                                    /* Load packet defaults. */
+                                    ((cont_a64_entry_t *)pkt)->entry_type =
+                                    CONTINUE_A64_TYPE;
+                                    ((cont_a64_entry_t *)pkt)->entry_count = 1;
+                                    ((cont_a64_entry_t *)pkt)->sys_define = (uint8_t)
+                                    ha->req_ring_index;
+
+                                    /* Setup packet address segment pointer. */
+                                    dword_ptr = (uint32_t *)
+                                    &((cont_a64_entry_t *)pkt)->dseg_0_address;
+
+                                    /* Load continuation entry data segments. */
+                                    for( cnt = 0; cnt < 5 && seg_cnt; cnt++, seg_cnt-- ) {
+                                       /* 4.10 64 bit */
+                                       *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                                       *dword_ptr++ = cpu_to_le32(pci_dma_hi32(sg_dma_address(sg)));
+                                       *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                                       sg++;
+                                      /* DEBUG(sprintf(debug_buff,
+                                      "S/G Segment Cont. phys_addr=%x %x, len=0x%x\n\r",
+                                       cpu_to_le32(pci_dma_hi32(sg_dma_address(sg))),
+                                       cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                                       cpu_to_le32(sg_dma_len(sg)));)
+                                       DEBUG(qla2100_print(debug_buff)); */
+                                    }
+#ifdef QL_DEBUG_LEVEL_5
+                                    qla2100_print(
+                                    "qla2x00_64bit_start_scsi: continuation packet data - c");
+                                    qla2100_print("b");
+                            qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+
+                            qla2100_print("t");
+                            qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                            qla2100_print("d");
+                            qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                            qla2100_print("\n\r");
+                                    qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                                }
+                            } else   /* No scatter gather data transfer */
+                            {   /* 4.10 64 bit */
+                                dma_handle = pci_map_single(ha->pdev, 
+                                                         cmd->request_buffer,
+                                                         cmd->request_bufflen,
+                                                         scsi_to_pci_dma_dir(cmd->sc_data_direction));
+                                /* save dma_handle for pci_unmap_single */
+                                sp->saved_dma_handle = dma_handle;
+
+                                *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle));
+                                *dword_ptr++ = cpu_to_le32(pci_dma_hi32(dma_handle));
+                                *dword_ptr   = (uint32_t) cmd->request_bufflen;
+                                /* DEBUG(sprintf(debug_buff,
+                                "64_bit: No S/G map_single saved_dma_handle=%lx len=%x \n\r",dma_handle, cmd->request_bufflen));
+                                DEBUG(qla2100_print(debug_buff)); */
+#ifdef QL_DEBUG_LEVEL_5
+                                qla2100_print(
+                                "qla2x00_64bit_start_scsi: No scatter/gather command packet data - c");
+                                qla2100_print("b");
+                                qla2100_output_number((uint32_t)SCSI_BUS_32(cmd), 10);
+                                qla2100_print("t");
+                                qla2100_output_number((uint32_t)SCSI_TCN_32(cmd), 10);
+                                qla2100_print("d");
+                                qla2100_output_number((uint32_t)SCSI_LUN_32(cmd), 10);
+                                qla2100_print("\n\r");
+                                qla2100_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                            }
+                        }
+                        else                            /* No data transfer */
+                        {
+                            *dword_ptr++ = (uint32_t) 0;
+                            *dword_ptr++ = (uint32_t) 0;
+                            *dword_ptr = (uint32_t)  0;
+#ifdef QL_DEBUG_LEVEL_5
+                         qla2100_print(
+                         "qla2x00_64bit_start_scsi: No data, command packet data - c");
+                         qla2100_print("b");
+                         qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+                         qla2100_print("t");
+                         qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                         qla2100_print("d");
+                         qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                         qla2100_print("\n\r");
+                         qla2x00_dump_buffer((caddr_t)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                        }
+                        DEBUG4(qla2100_print("\nqla2100_64bit_start_scsi: Wakeup RISC for pending command\n\r"));
+                        /* Adjust ring index. */
+                        ha->req_ring_index++;
+                        if( ha->req_ring_index == REQUEST_ENTRY_CNT ) {
+                            ha->req_ring_index = 0;
+                            ha->request_ring_ptr = ha->request_ring;
+                        } else
+                            ha->request_ring_ptr++;
+
+                        /* Set chip new ring index. */
+#if WATCH_THREADS_SIZE
+                        DEBUG3(qla2100_output_number((uint32_t)ha->actthreads, 16));
+#endif
+                        if (ha->device_id == QLA2300_DEVICE_ID) {
+                           temp = CACHE_FLUSH(&reg2300->req_q_in);
+                           WRT_REG_WORD(&reg2300->req_q_in, ha->req_ring_index);
+                        } else {
+                           temp = CACHE_FLUSH(&reg->mailbox4);
+                           WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
+                        }
+                    } else {
+                        status = 1;
+#ifdef QL_DEBUG_LEVEL_2
+                        qla2100_print(
+                        "qla2x00_64bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n\r");
+                        qla2100_print(" req_q_cnt=");
+                qla2100_output_number((u_long)ha->req_q_cnt, 16);
+#endif
+                    }
+                } else {
+                    status = 1;
+#ifdef QL_DEBUG_LEVEL_2
+                    qla2100_print("qla2x00_64bit_start_scsi: in-ptr=");
+            qla2100_output_number((u_long)ha->req_ring_index, 16);
+            qla2100_print(" req_q_cnt=");
+            qla2100_output_number((u_long)ha->req_q_cnt, 16);
+            qla2100_print(" req_cnt=");
+            qla2100_output_number((u_long)req_cnt, 16);
+                    qla2100_print("\n\r");
+#endif
+                }
+
+                /* Release ring specific lock */
+                QLA2100_RING_UNLOCK(ha);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                    qla2100_print("qla2x00_64bit_start_scsi: **** FAILED ****\n\r");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    qla2100_print("qla2x00_64bit_start_scsi: exiting normally\n\r");
+#endif
+                return(status);
+}
+#endif
+
+/*
+* qla2100_32bit_start_scsi
+*      The start SCSI is responsible for building request packets on
+*      request ring and modifying ISP input pointer.
+*
+*      The Qlogic firmware interface allows every queue slot to have a SCSI
+*      command and up to 4 scatter/gather (SG) entries.  If we need more
+*      than 4 SG entries, then continuation entries are used that can
+*      hold another 7 entries each.  The start routine determines if there
+*      is eought empty slots then build the combination of requests to
+*      fulfill the OS request.
+*
+* Input:
+*      ha = adapter block pointer.
+*      sp = SCSI Request Block structure pointer.
+*
+* Returns:
+*      0 = success, was able to issue command.
+*/
+STATIC uint8_t
+qla2100_32bit_start_scsi(scsi_qla_host_t *ha, srb_t *sp) {
+                device_reg_t        *reg       = ha->iobase;
+                device2300_reg_t    *reg2300   = ha->iobase2300;
+                uint8_t         status = 0;
+                Scsi_Cmnd       *cmd = sp->cmd;
+                uint16_t        cdb_len, temp;
+                uint32_t        cnt;
+                cmd_entry_t     *pkt;
+                uint16_t        req_cnt;
+                uint16_t        seg_cnt;
+                struct scatterlist    *sg = (struct scatterlist *) NULL;
+                caddr_t         data_ptr;
+                uint32_t        *dword_ptr;
+                uint32_t        timeout;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+                uint64_t       dma_handle;
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_32bit_start_scsi"); 
+#endif
+
+#if defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_3)
+                printk(
+                          "32bit_start BEGIN: cmd=%x sp=%x CDB=%x\n\r",
+                           cmd,sp,cmd->cmnd[0]);
+#endif
+#ifdef NEW
+                /*
+                * Send marker if required.
+                */
+                if (ha->marker_needed != 0) {
+                    if (qla2200_marker(ha, 0, 0, MK_SYNC_ALL) != 0) {
+                        RING_UNLOCK(ha);
+                        return (1);
+                    }
+                }
+#endif
+                COMTRACE('S')
+                /* Calculate number of entries and segments required. */
+                seg_cnt = 0;
+                req_cnt = 1;
+                if( cmd->use_sg ) {
+                    sg = (struct scatterlist *) cmd->request_buffer;
+                    /* 4.10 32 bit S/G Data Transfer */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                    seg_cnt =  cmd->use_sg;
+#else
+                    seg_cnt = pci_map_sg(ha->pdev,sg,cmd->use_sg, 
+                              scsi_to_pci_dma_dir(cmd->sc_data_direction));
+#endif
+                    /*
+                    * if greater than four sg entries then we need to allocate
+                    * continuation entries
+                    */
+                    if( seg_cnt > 2 ) {
+                        req_cnt += (uint16_t)(seg_cnt - 3) / 7;
+                        if( (uint16_t)(seg_cnt - 3) % 7 )
+                            req_cnt++;
+                    }
+                    DEBUG5(sprintf(debug_buff,
+                    "S/G for data transfer -num segs(%d), req blk cnt(%d)\n\r",seg_cnt,req_cnt));
+                    DEBUG5(qla2100_print(debug_buff));
+                } else if( CMD_XFRLEN(cmd) )  /* If data transfer. */
+                {  /* no S/G Data Transfer */
+                   /*  DEBUG5(printk("Single data transfer (0x%x)\n",
+                       cmd->request_bufflen));*/
+                    seg_cnt = 1;
+                }
+
+                /* Acquire ring specific lock */
+                QLA2100_RING_LOCK(ha);
+
+                if( (uint16_t)(req_cnt + 2) >= ha->req_q_cnt ) {
+                    /* Calculate number of free request entries. */
+                    if (ha->device_id == QLA2300_DEVICE_ID)  
+                      cnt = qla2100_debounce_register(&reg2300->req_q_out);
+                    else   
+                      cnt = qla2100_debounce_register(&reg->mailbox4);
+
+                    if( ha->req_ring_index < cnt )
+                        ha->req_q_cnt = cnt - ha->req_ring_index;
+                    else
+                        ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
+                }
+
+                DEBUG5(sprintf(debug_buff,
+                 "Number of free entries = (%d)\n\r",ha->req_q_cnt));
+                DEBUG5(qla2100_print(debug_buff));
+                /* If room for request in request ring. */
+                if( (uint16_t)(req_cnt + 2) < ha->req_q_cnt ) {
+                    /* Check for room in outstanding command list. */
+                    for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS &&
+                    (ha->outstanding_cmds[cnt] != 0); cnt++ )
+                        ;
+
+                    if( cnt < MAX_OUTSTANDING_COMMANDS ) {
+                        ha->outstanding_cmds[cnt] = sp;
+                        ha->req_q_cnt -= req_cnt;
+                        /* save the handle -- helps if we want to abort it */
+                        CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt;
+
+                        /*
+                        * Build command packet.
+                        */
+                        pkt = (cmd_entry_t *)ha->request_ring_ptr;
+
+                        pkt->entry_type = COMMAND_TYPE;
+                        pkt->entry_count = (uint8_t)req_cnt;
+                        pkt->sys_define = (uint8_t)ha->req_ring_index;
+                        pkt->entry_status = 0;
+                        pkt->control_flags= 0;
+                        pkt->handle = (uint32_t)cnt;
+
+                        /* Zero out remaining portion of packet. */
+                        dword_ptr = (uint32_t *)pkt + 2;
+                        for( cnt = 2; cnt < REQUEST_ENTRY_SIZE/4; cnt++ )
+                            *dword_ptr++ = 0;
+
+                        /*
+                        * v2.19.8
+                        * We subtract 5 sec. from the timeout value to insure
+                        * the ISP time-out before the mid-level or the driver.
+                        */
+                        timeout = (uint32_t) CMD_TIMEOUT(cmd)/HZ;
+                        if( timeout > 5 )
+                            pkt->timeout = (uint16_t) timeout - 5;
+                        else
+                            pkt->timeout = (uint16_t) timeout;
+
+                        /* Set device target ID and LUN */
+                        pkt->target = TGT_Q(ha, 
+                        SCSI_BUS_32(cmd), SCSI_TCN_32(cmd))->loop_id;
+                        pkt->lun = SCSI_LUN_32(cmd);
+
+                        /* Enable simple tag queuing if device supports it. */
+                        if ( cmd->device->tagged_queue ) {
+                            switch (cmd->tag) {
+                                case SIMPLE_QUEUE_TAG:
+                                    pkt->control_flags = CF_SIMPLE_TAG;
+                                    break;
+                                case HEAD_OF_QUEUE_TAG:
+                                    pkt->control_flags = CF_HEAD_TAG;
+                                    break;
+                                case ORDERED_QUEUE_TAG:
+                                    pkt->control_flags = CF_ORDERED_TAG;
+                                    break;
+                                default:
+                                    pkt->control_flags = CF_SIMPLE_TAG;
+                            }
+                        } else
+                            pkt->control_flags = CF_SIMPLE_TAG;
+
+                       if (ha->device_id == QLA2300_DEVICE_ID)
+                           pkt->control_flags |= CF_NO_FAST_POSTING; 
+
+                        /* Load SCSI command packet. */
+                        cdb_len = (uint16_t)CMD_CDBLEN(cmd);
+                        if( cdb_len > MAX_CMDSZ )
+                            cdb_len = MAX_CMDSZ;
+                        data_ptr = (uint8_t *) &(CMD_CDBP(cmd));
+                        for( cnt = 0; cnt < cdb_len; cnt++ )
+                            pkt->scsi_cdb[cnt] = *data_ptr++;
+                        DEBUG3(sprintf(debug_buff,
+                        "qla2100: Packet has command[0]=0x%x, hndl=0x%x\n",pkt->scsi_cdb[0],pkt->handle);)
+                        DEBUG3(qla2100_print(debug_buff);)
+                        pkt->byte_count = (uint32_t) CMD_XFRLEN(cmd);
+
+                        /*
+                        * Load data segments.
+                        */
+                        if( seg_cnt ) {
+                            /* Set transfer direction (READ and WRITE) */
+                            /* Linux doesn't tell us                   */
+
+                            switch( cmd->data_cmnd[0] ) {
+                                case FORMAT_UNIT:
+                                case WRITE_6:
+                                case MODE_SELECT:
+                                case SEND_DIAGNOSTIC:
+                                case WRITE_10:
+                                case WRITE_BUFFER:
+                                case WRITE_LONG:
+                                case WRITE_SAME:
+                                case MODE_SELECT_10:
+                                case WRITE_12:
+                                case WRITE_VERIFY_12:
+                                case SEND_VOLUME_TAG:
+                                    pkt->control_flags |= BIT_6; /* WRITE */
+                                    break;
+                                default:
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
+#if QLA_SCSI_VENDOR_DIR
+    				    qla2100_set_vend_direction(ha, cmd, pkt);
+#else
+                                    pkt->control_flags |= BIT_5; /* READ */
+#endif
+#else  /* kernel version is 2.4.0 or higher */
+                                    if (cmd->sc_data_direction == SCSI_DATA_WRITE)
+                                        pkt->control_flags |= BIT_6;/*WRITE*/
+                                    else 
+                                        pkt->control_flags |= BIT_5;/*READ*/
+#endif /* kernel version 2.4.0 */
+                                    break;
+                            }
+                            sp->dir = pkt->control_flags & (BIT_5|BIT_6);
+
+                            /* Set total data segment count. */
+                            pkt->dseg_count = seg_cnt;
+
+                            /* Setup packet address segment pointer. */
+                            dword_ptr = (uint32_t *)&pkt->dseg_0_address;
+
+                            if( cmd->use_sg )     /* If scatter gather */
+                            {
+                                DEBUG5(qla2100_print("Building S/G data segments..\n\r"));
+                                DEBUG5(qla2100_dump_buffer((caddr_t)sg, 4*16));
+                                /* Load command entry data segments. */
+                                for( cnt = 0; cnt < 3 && seg_cnt; cnt++, seg_cnt-- ) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                                   *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(sg->address));
+                                   *dword_ptr++ = sg->length;
+                                   /* DEBUG(sprintf(debug_buff,
+                                      "S/G Segment phys_addr=0x%x, len=0x%x\n\r",
+                                       cpu_to_le32(VIRT_TO_BUS(sg->address)),sg->length));
+                                       DEBUG(qla2100_print(debug_buff)); */
+#else
+                                   *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                                   *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                                      /* DEBUG(sprintf(debug_buff,
+                                      "S/G Segment phys_addr=0x%x, len=0x%x\n\r",
+                                       cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                                       cpu_to_le32(sg_dma_len(sg)));)
+                                       DEBUG(qla2100_print(debug_buff)); */
+#endif
+                                   sg++;
+                                }
+#ifdef QL_DEBUG_LEVEL_5
+                                qla2100_print(
+                                "qla2100_32bit_start_scsi: Scatter/gather command packet data - ");
+                                qla2100_output_number((u_long)ha->host_no, 10);
+                                qla2100_print(":");
+                                qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+                                qla2100_print(":");
+                                qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                                qla2100_print(":");
+                                qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                                qla2100_print("\n");
+                                qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                                /*
+                                * Build continuation packets.
+                                */
+                                while( seg_cnt > 0 ) {
+                                    /* Adjust ring index. */
+                                    ha->req_ring_index++;
+                                    if( ha->req_ring_index == REQUEST_ENTRY_CNT ) {
+                                        ha->req_ring_index = 0;
+                                        ha->request_ring_ptr = ha->request_ring;
+                                    } else
+                                        ha->request_ring_ptr++;
+
+                                    pkt = (cmd_entry_t *)ha->request_ring_ptr;
+
+                                    /* Zero out packet. */
+                                    dword_ptr = (uint32_t *)pkt;
+                                    for( cnt = 0;cnt < REQUEST_ENTRY_SIZE/4; cnt++ )
+                                        *dword_ptr++ = 0;
+
+                                    /* Load packet defaults. */
+                                    ((cont_entry_t *)pkt)->entry_type = CONTINUE_TYPE;
+                                    ((cont_entry_t *)pkt)->entry_count = 1;
+                                    ((cont_entry_t *)pkt)->sys_define = (uint8_t)
+                                    ha->req_ring_index;
+
+                                    /* Setup packet address segment pointer. */
+                                    dword_ptr = (uint32_t *)
+                                    &((cont_entry_t *)pkt)->dseg_0_address;
+
+                                    /* Load continuation entry data segments. */
+                                    for( cnt = 0; cnt < 7 && seg_cnt; cnt++, seg_cnt-- ) {
+                                       /* 4.10 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                                       *dword_ptr++ = (u_int) cpu_to_le32(VIRT_TO_BUS(sg->address));
+                                       *dword_ptr++ = sg->length;
+                                       /* DEBUG(sprintf(debug_buff,
+                                       "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r",
+                                        cpu_to_le32(pci_dma_lo32(VIRT_TO_BUS(sg->address))),sg->length);)
+                                        DEBUG(qla2100_print(debug_buff)); */
+#else
+                                       *dword_ptr++ = cpu_to_le32(pci_dma_lo32(sg_dma_address(sg)));
+                                       *dword_ptr++ = cpu_to_le32(sg_dma_len(sg));
+                                       /* DEBUG(sprintf(debug_buff,
+                                       "S/G Segment Cont. phys_addr=0x%x, len=0x%x\n\r",
+                                       cpu_to_le32(pci_dma_lo32(sg_dma_address(sg))),
+                                       cpu_to_le32(sg_dma_len(sg)));)
+                                       DEBUG(qla2100_print(debug_buff)); */
+#endif
+                                       sg++;
+                                    }
+#ifdef QL_DEBUG_LEVEL_5
+                                    qla2100_print(
+                                    "qla2100_32bit_start_scsi: continuation packet data - ");
+                                    qla2100_output_number((u_long)ha->host_no, 10);
+                                    qla2100_print(":");
+                                    qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+                                    qla2100_print(":");
+                                    qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                                    qla2100_print(":");
+                                    qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                                    qla2100_print("\n");
+                                    qla2100_dump_buffer((uint8_t *)pkt,
+                                    REQUEST_ENTRY_SIZE);
+#endif
+                                }
+                            } else  /* No scatter gather data transfer */
+                            {
+                              /* 4.10 32 bit */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                              *dword_ptr++ = (uint32_t) cpu_to_le32(VIRT_TO_BUS(cmd->request_buffer));
+                              *dword_ptr = (uint32_t) cmd->request_bufflen;
+#else
+                              dma_handle = pci_map_single(ha->pdev, 
+                                                          cmd->request_buffer,
+                                                          cmd->request_bufflen,
+                                                          scsi_to_pci_dma_dir(cmd->sc_data_direction));
+                              sp->saved_dma_handle = dma_handle;
+
+                              *dword_ptr++ = cpu_to_le32(pci_dma_lo32(dma_handle));
+                              *dword_ptr   = (uint32_t) cmd->request_bufflen;
+                              /* DEBUG(sprintf(debug_buff,
+                              "32_bit: No S/G map_single dma_handle=%lx len=%x\n\r",dma_handle,cmd->request_bufflen));
+                              DEBUG(qla2100_print(debug_buff)); */
+#endif 
+                              /* DEBUG5(printk("Single Segment ap=0x%x, len=0x%x\n",cmd->request_buffer,cmd->request_bufflen));*/
+
+#ifdef QL_DEBUG_LEVEL_5
+                              qla2100_print("qla2100_32bit_start_scsi: No scatter/gather command packet data - ");
+                              qla2100_output_number((u_long)ha->host_no, 10);
+                              qla2100_print(":");
+                              qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+                              qla2100_print(":");
+                              qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                              qla2100_print(":");
+                              qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                              qla2100_print("\n");
+                              qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                            }
+                        }
+                        else     /* No data transfer */
+                        {
+                            *dword_ptr++ = (uint32_t) 0;
+                            *dword_ptr = (uint32_t)  0;
+#ifdef QL_DEBUG_LEVEL_5
+                    qla2100_print(
+                    "qla2100_32bit_start_scsi: No data, command packet data - ");
+                    qla2100_output_number((u_long)ha->host_no, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)SCSI_BUS_32(cmd), 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)SCSI_TCN_32(cmd), 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)SCSI_LUN_32(cmd), 10);
+                    qla2100_print("\n");
+                    qla2100_dump_buffer((uint8_t *)pkt, REQUEST_ENTRY_SIZE);
+#endif
+                        }
+                        /* Adjust ring index. */
+                        ha->req_ring_index++;
+                        if( ha->req_ring_index == REQUEST_ENTRY_CNT ) {
+                            ha->req_ring_index = 0;
+                            ha->request_ring_ptr = ha->request_ring;
+                        } else
+                            ha->request_ring_ptr++;
+
+                        /* Set chip new ring index. */
+                        DEBUG4(qla2100_print("\nqla2100_32bit_start_scsi: Wakeup RISC for pending command\n\r"));
+                        ha->qthreads--;
+                        sp->flags |= SRB_SENT;
+                        sp->state = 0xde;
+                        ha->actthreads++;
+
+                     /* DEBUG(sprintf(debug_buff," Start(pid=%d) ",cmd->pid);)
+                        DEBUG(qla2100_print(debug_buff);) */
+
+#if WATCH_THREADS_SIZE
+                DEBUG3(qla2100_output_number((u_long)ha->actthreads, 16)); 
+#endif
+                        if (ha->device_id == QLA2300_DEVICE_ID) {
+                          temp = CACHE_FLUSH(&reg2300->req_q_in);
+                          WRT_REG_WORD(&reg2300->req_q_in, ha->req_ring_index);
+                        } else { 
+                          temp = CACHE_FLUSH(&reg->mailbox4);
+                          WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
+                        }
+                    } else {
+                        status = 1;
+                        qla2100_stats.outarray_full++;
+#ifdef QL_DEBUG_LEVEL_8
+                        qla2100_print(
+                        "qla2100_32bit_start_scsi: NO ROOM IN OUTSTANDING ARRAY\n");
+#endif
+                    }
+                } else {
+                    status = 1;
+#ifdef QL_DEBUG_LEVEL_8
+                    qla2100_print("qla2100_32bit_start_scsi: in-ptr=");
+                    qla2100_output_number((u_long)ha->req_ring_index, 16);
+                    qla2100_print(" req_q_cnt=");
+                    qla2100_output_number((u_long)ha->req_q_cnt, 16);   
+                    qla2100_print(" req_cnt=");
+                    qla2100_output_number((u_long)req_cnt, 16);
+                    qla2100_print("\n");
+#endif
+                }
+
+                /* Release ring specific lock */
+                QLA2100_RING_UNLOCK(ha);
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( status )
+                      qla2100_print("qla2100_32bit_start_scsi: **** FAILED ****\n");
+#ifdef QL_DEBUG_LEVEL_3
+                else  qla2100_print("qla2100_32bit_start_scsi: exiting normally\n\n\r");
+#endif
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_32bit_start_scsi"); 
+#endif
+                COMTRACE('s')
+                return(status);
+}
+
+/*
+* qla2100_ms_req_pkt
+*      Function is responsible for locking ring and
+*      getting a zeroed out Managment Server request packet.
+*
+* Input:
+*      ha  = adapter block pointer.
+*      sp  = srb_t pointer to handle post function call
+* Returns:
+*      0 = failed to get slot.
+*/
+STATIC request_t *
+qla2100_ms_req_pkt(scsi_qla_host_t *ha, srb_t  *sp) {
+                device_reg_t     *reg     = ha->iobase;
+                device2300_reg_t *reg2300 = ha->iobase2300;
+                request_t    *pkt = 0;
+                uint16_t     cnt,i;
+                uint32_t     *dword_ptr;
+                uint32_t     timer;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_ms_req_pkt");
+#endif
+
+                /* Wait for 30 seconds for slot. */
+                for( timer = 3000000; timer; timer-- ) {
+                    /* Acquire ring specific lock */
+                    QLA2100_RING_LOCK(ha);
+
+                    if( !ha->req_q_cnt ) {
+                        /* Calculate number of free request entries. */
+                        if (ha->device_id == QLA2300_DEVICE_ID) cnt = qla2100_debounce_register(&reg2300->req_q_out);
+                        else                                    cnt = qla2100_debounce_register(&reg->mailbox4);
+                        if( ha->req_ring_index < cnt )
+                            ha->req_q_cnt = cnt - ha->req_ring_index;
+                        else
+                            ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
+                    }
+
+                    /* Check for room in outstanding command list. */
+                    for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS &&
+                    (ha->outstanding_cmds[cnt] != 0); cnt++ )
+                        ;
+
+                    if( (cnt < MAX_OUTSTANDING_COMMANDS) &&
+                        ( ha->req_q_cnt != 0 )) {
+
+                        pkt = ha->request_ring_ptr;
+
+                        /* Zero out packet. */
+                        dword_ptr = (uint32_t *)pkt;
+                        for( i = 0; i < REQUEST_ENTRY_SIZE/4; i++ )
+                            *dword_ptr++ = 0;
+
+                        DEBUG(sprintf(debug_buff,
+                          "qla2100_ms_req: putting sp=%x in outstanding_cmds[%x]\n",sp,cnt));
+                        DEBUG(qla2100_print(debug_buff));
+
+                        ha->outstanding_cmds[cnt] = sp;
+                        /* save the handle */
+                        CMD_HANDLE(sp->cmd) = (unsigned char *) (u_long) cnt;
+
+                        ha->req_q_cnt--;
+                        pkt->handle = (uint32_t)cnt;
+
+                        /* Set system defined field. */
+                        pkt->sys_define = (uint8_t)ha->req_ring_index;
+                        pkt->entry_status = 0;
+
+                        break;
+                    }
+
+                    /* Release ring specific lock */
+                    QLA2100_RING_UNLOCK(ha);
+
+                    SYS_DELAY(2);  
+
+                    /* Check for pending interrupts. */
+                    qla2100_poll(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_ms_req_pkt: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_ms_req_pkt");
+#endif
+                return(pkt);
+}
+
+
+/*
+* qla2100_req_pkt
+*      Function is responsible for locking ring and
+*      getting a zeroed out request packet.
+*
+* Input:
+*      ha  = adapter block pointer.
+*
+* Returns:
+*      0 = failed to get slot.
+*/
+STATIC request_t *
+qla2100_req_pkt(scsi_qla_host_t *ha) {
+                device_reg_t     *reg     = ha->iobase;
+                device2300_reg_t *reg2300 = ha->iobase2300;
+                request_t    *pkt = 0;
+                uint16_t     cnt;
+                uint32_t     *dword_ptr;
+                uint32_t     timer;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_req_pkt");
+#endif
+
+                /* Wait for 30 seconds for slot. */
+                for( timer = 3000000; timer; timer-- ) {
+                    /* Acquire ring specific lock */
+                    QLA2100_RING_LOCK(ha);
+
+                    if( !ha->req_q_cnt ) {
+                        /* Calculate number of free request entries. */
+                        if (ha->device_id == QLA2300_DEVICE_ID) cnt = qla2100_debounce_register(&reg2300->req_q_out);
+                        else                                    cnt = qla2100_debounce_register(&reg->mailbox4);
+                        if( ha->req_ring_index < cnt )
+                            ha->req_q_cnt = cnt - ha->req_ring_index;
+                        else
+                            ha->req_q_cnt = REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
+                    }
+
+                    /* Found empty request ring slot? */
+                    if( ha->req_q_cnt ) {
+                        ha->req_q_cnt--;
+                        pkt = ha->request_ring_ptr;
+
+                        /* Zero out packet. */
+                        dword_ptr = (uint32_t *)pkt;
+                        for( cnt = 0; cnt < REQUEST_ENTRY_SIZE/4; cnt++ )
+                            *dword_ptr++ = 0;
+
+                        /* Set system defined field. */
+                        pkt->sys_define = (uint8_t)ha->req_ring_index;
+
+                        /* Set entry count. */
+                        pkt->entry_count = 1;
+
+                        break;
+                    }
+
+                    /* Release ring specific lock */
+                    QLA2100_RING_UNLOCK(ha);
+
+                    SYS_DELAY(2);   /* 10 */
+
+                    /* Check for pending interrupts. */
+                    qla2100_poll(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_req_pkt: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_req_pkt");
+#endif
+                return(pkt);
+}
+
+/*
+* qla2100_isp_cmd
+*      Function is responsible for modifying ISP input pointer.
+*      Releases ring lock.
+*
+* Input:
+*      ha  = adapter block pointer.
+*/
+STATIC void
+qla2100_isp_cmd(scsi_qla_host_t *ha) {
+                device_reg_t     *reg     = ha->iobase;
+                device2300_reg_t *reg2300 = ha->iobase2300;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_isp_cmd");
+#endif
+
+#ifdef QL_DEBUG_LEVEL_5
+                qla2100_print("qla2100_isp_cmd: IOCB data:\n");
+                qla2100_dump_buffer((uint8_t *)ha->request_ring_ptr, REQUEST_ENTRY_SIZE);
+#endif
+
+                /* Adjust ring index. */
+                ha->req_ring_index++;
+                if( ha->req_ring_index == REQUEST_ENTRY_CNT ) {
+                    ha->req_ring_index = 0;
+                    ha->request_ring_ptr = ha->request_ring;
+                } else
+                    ha->request_ring_ptr++;
+
+                /* Set chip new ring index. */
+                if (ha->device_id == QLA2300_DEVICE_ID) WRT_REG_WORD(&reg2300->req_q_in, ha->req_ring_index);
+                else                                    WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
+
+                /* Release ring specific lock */
+                QLA2100_RING_UNLOCK(ha);
+
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_isp_cmd");
+#endif
+}
+
+/*
+* qla2100_enable_lun
+*      Issue enable LUN entry IOCB.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_enable_lun(scsi_qla_host_t *ha) {
+                elun_entry_t *pkt;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_enable_lun");
+#endif
+
+                /* Get request packet. */
+                if( (pkt = (elun_entry_t *)qla2100_req_pkt(ha)) != NULL ) {
+                    pkt->entry_type = ENABLE_LUN_TYPE;
+                    pkt->command_count = 32;
+                    pkt->immed_notify_count = 1;
+                    pkt->timeout = 0xffff;
+
+                    /* Issue command to ISP */
+                    qla2100_isp_cmd(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_enable_lun: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_enable_lun");
+#endif
+}
+
+
+
+#if QL2100_TARGET_MODE_SUPPORT
+/****************************************************************************/
+/*                      Target Mode Support Functions.                      */
+/****************************************************************************/
+
+
+/*
+* qla2100_notify_ack
+*      Issue notify acknowledge IOCB.
+*      If sequence ID is zero, acknowledgement of
+*      SCSI bus reset or bus device reset is assumed.
+*
+* Input:
+*      ha      = adapter block pointer.
+*      inotify = immediate notify entry pointer.
+*/
+STATIC void
+qla2100_notify_ack(scsi_qla_host_t *ha, notify_entry_t *inotify) {
+                nack_entry_t *pkt;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_notify_ack: entered\n");
+#endif
+
+                /* Get request packet. */
+                if( pkt = (nack_entry_t *)qla2100_req_pkt(ha) ) {
+                    pkt->entry_type = NOTIFY_ACK_TYPE;
+                    pkt->initiator_id = inotify->initiator_id;
+                    pkt->target_id = inotify->target_id;
+
+                    if( (pkt->status = inotify->status) == 0xe )
+                        /* Reset LIP occurred. */
+                        pkt->flags = OF_RESET;
+                    else
+                        /* Increment Immediate Notify Resource Count. */
+                        pkt->flags = OF_INC_RC;
+
+                    pkt->task_flags = inotify->task_flags;
+                    pkt->seq_id = inotify->seq_id;
+
+                    /* Issue command to ISP */
+                    qla2100_isp_cmd(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_notify_ack: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_notify_ack: exiting normally\n");
+#endif
+}
+
+/*
+* qla2100_64bit_continue_io
+*      Issue continue target I/O IOCB.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      atio = atio pointer.
+*      len  = total bytecount.
+*      addr = physical address pointer.
+*/
+STATIC void
+qla2100_64bit_continue_io(scsi_qla_host_t *ha, atio_entry_t *atio, uint32_t len,
+        u_long    *addr) {
+                ctio_a64_entry_t *pkt;
+                uint32_t         *dword_ptr;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_64bit_continue_io: entered\n");
+#endif
+
+                /* Get request packet. */
+                if( pkt = (ctio_a64_entry_t *)qla2100_req_pkt(ha) ) {
+                    pkt->entry_type = CTIO_A64_TYPE;
+                    pkt->initiator_id = atio->initiator_id;
+                    pkt->exchange_id = atio->exchange_id;
+                    pkt->flags = atio->flags | OF_FAST_POST;
+                    pkt->scsi_status = atio->scsi_status;
+
+                    if( len ) {
+                        pkt->dseg_count = 1;
+                        pkt->transfer_length = len;
+                        pkt->dseg_0_length = len;
+                        dword_ptr = (uint32_t *)addr;
+                        pkt->dseg_0_address[0] = *dword_ptr++;
+                        pkt->dseg_0_address[1] = *dword_ptr;
+                    }
+
+                    /* Issue command to ISP */
+                    qla2100_isp_cmd(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_64bit_continue_io: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_64bit_continue_io: exiting normally\n");
+#endif
+}
+
+/*
+* qla2100_32bit_continue_io
+*      Issue continue target I/O IOCB.
+*
+* Input:
+*      ha   = adapter block pointer.
+*      atio = atio pointer.
+*      len  = total bytecount.
+*      addr = physical address pointer.
+*/
+STATIC void
+qla2100_32bit_continue_io(scsi_qla_host_t *ha, atio_entry_t *atio, uint32_t len,
+        u_long    *addr) {
+                ctio_entry_t *pkt;
+                uint32_t     *dword_ptr;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_continue_io: entered\n");
+#endif
+
+                /* Get request packet. */
+                if( pkt = (ctio_entry_t *)qla2100_req_pkt(ha) ) {
+                    pkt->entry_type = CONTINUE_TGT_IO_TYPE;
+                    pkt->initiator_id = atio->initiator_id;
+                    pkt->exchange_id = atio->exchange_id;
+                    pkt->flags = atio->flags | OF_FAST_POST;
+                    pkt->scsi_status = atio->scsi_status;
+
+                    if( len ) {
+                        pkt->dseg_count = 1;
+                        pkt->transfer_length = len;
+                        pkt->dseg_0_length = len;
+                        dword_ptr = (uint32_t *)addr;
+                        pkt->dseg_0_address = *dword_ptr;
+                    }
+
+                    /* Issue command to ISP */
+                    qla2100_isp_cmd(ha);
+                }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                if( !pkt )
+                    qla2100_print("qla2100_32bit_continue_io: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                else
+                    LEAVE("qla2100_32bit_continue_io: exiting normally\n");
+#endif
+}
+#endif /* QL2100_TARGET_MODE_SUPPORT */
+
+
+
+/****************************************************************************/
+/*                        Interrupt Service Routine.                        */
+/****************************************************************************/
+
+/*
+*  qla2100_isr
+*      Calls I/O done on command completion.
+*
+* Input:
+*      ha           = adapter block pointer.
+*      done_q_first = done queue first pointer.
+*      done_q_last  = done queue last pointer.
+*      INTR_LOCK must be already obtained.
+*/
+STATIC void
+qla2100_isr(scsi_qla_host_t *ha, srb_t **done_q_first, srb_t **done_q_last) {
+                device_reg_t     *reg     = ha->iobase;
+                device2300_reg_t *reg2300 = ha->iobase2300;
+                response_t   *pkt, response_entry;
+                srb_t        *sp;
+                uint16_t     mailbox[MAILBOX_REGISTER_COUNT];
+                uint16_t     *wptr, status2 = 0;
+                uint32_t     index, longstatus, *dptr1, *dptr2;
+                unsigned long cpu_flags = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_isr"); 
+#endif
+                if (ha->device_id != QLA2300_DEVICE_ID) { 
+                    /* Check for 2100/2200 mailbox interrupt (semaphore set) */
+                    longstatus = RD_REG_WORD(&reg->semaphore);
+                    if (longstatus & BIT_0)     status2 = SEMAPHORE_SET;
+                } else {
+                    /* Get 2300's Interrupt Status byte */
+                    longstatus = RD_REG_DWORD(&reg2300->host_status);
+/*#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                    DEBUG(qla2100_print("qla2100_isr: +++ 2300 RISC_TO_HOST reg= ");)
+                    DEBUG(qla2100_output_number((u_long)longstatus, 16);)
+                    DEBUG(qla2100_print(" +++ \n");)
+#endif */
+                    switch(longstatus & 0xff) {
+                      case 0x1:
+                      case 0x2:
+                      case 0x10:
+                      case 0x11:
+                      case 0x12:
+                      case 0x14:
+                      case 0x15:
+                      case 0x16:
+                      case 0x17:
+                        status2 = SEMAPHORE_SET;
+                        break;
+                      case 0x13:
+                      default:
+                        status2 = 0;
+                        break;
+                    }
+                }
+
+                if ( status2 == SEMAPHORE_SET ) {
+
+                    /* Get mailbox data. */
+                    wptr    = &mailbox[0];
+                    if (ha->device_id != QLA2300_DEVICE_ID) {
+                      *wptr++ = qla2100_debounce_register(&reg->mailbox0);
+                      *wptr++ = RD_REG_WORD(&reg->mailbox1);
+                      *wptr   = RD_REG_WORD(&reg->mailbox2);
+                    } else { 
+                      *wptr++ = qla2100_debounce_register(&reg2300->mailbox0);
+                      *wptr++ = RD_REG_WORD(&reg2300->mailbox1);
+                      *wptr   = RD_REG_WORD(&reg2300->mailbox2);
+                    }
+
+                    WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
+
+#if defined(QL_DEBUG_LEVEL_4)
+DEBUG(qla2100_print("qla2100_isr: SEMAPHORE SET Processing, mailbox[0]=");)
+DEBUG(qla2100_output_number((u_long)mailbox[0], 16);)
+DEBUG(qla2100_print(" \n");)
+DEBUG(qla2100_print("qla2100_isr: mailbox[1]=");)
+DEBUG(qla2100_output_number((u_long)mailbox[1], 16);)
+DEBUG(qla2100_print(" \n");)
+DEBUG(qla2100_print("qla2100_isr: mailbox[2]=");)
+DEBUG(qla2100_output_number((u_long)mailbox[2], 16);)
+DEBUG(qla2100_print(" \n");)
+DEBUG(qla2100_print("qla2100_isr: mailbox[3]=");)
+DEBUG(qla2100_output_number((u_long)mailbox[3], 16);)
+DEBUG(qla2100_print(" \n");)
+#endif 
+
+#ifdef FC_IP_SUPPORT /*******************************************/
+                    /* Handle IP send fast post */
+                    if (mailbox[0] == MBA_IP_TRANSMIT_COMPLETE) {
+                        SEND_CB *pSendCB;
+
+                        /* Clear the semaphore lock , if it was set */
+                        if (RD_REG_WORD(&reg->semaphore) & BIT_0)
+                            WRT_REG_WORD(&reg->semaphore, 0);
+
+                        /* Validate cmd handle and get packet pointer */
+                        if (mailbox[1] < MAX_SEND_PACKETS) {
+                            if ((pSendCB = (SEND_CB *)ha->apActiveIpQueue[mailbox[1]]) != NULL) {
+                                ha->apActiveIpQueue[mailbox[1]] = NULL;
+
+                                /* Complete backdoor command */
+                                (*ha->pSendCompletionRoutine)(pSendCB);
+
+                                return;
+                            }
+                        }
+
+                        /* Invalid handle from RISC, reset RISC firmware */
+                        printk(KERN_WARNING "qla2100_isr: bad IP send fast post handle %x\n",
+                        mailbox[1]);
+                        ha->flags.isp_abort_needed = TRUE;
+                        return;
+                    }
+
+                    /* Handle IP receive fast post */
+                    else if (mailbox[0] == MBA_IP_RECEIVE_COMPLETE ||
+                    mailbox[0] == MBA_IP_RECEIVE_COMPLETE_SPLIT) {
+                        PBUFFER_CB      pBufferCB, pNextBufferCB;
+                        uint32_t        lTagVal;
+                        uint32_t        lPacketSize;
+                        uint32_t        lReceiveBufferSize;
+                        volatile uint16_t *pNextMailbox;
+                        uint16_t        wBufferCount;
+
+                        pNextMailbox = &reg->mailbox10;
+
+                        /* If split buffer, set header size for 1st buffer */
+                        if (mailbox[0] == MBA_IP_RECEIVE_COMPLETE_SPLIT)
+                            lReceiveBufferSize = ha->wHeaderSize;
+                        else
+                            lReceiveBufferSize = ha->lReceiveBufferSize;
+
+                        if ((lTagVal = RD_REG_WORD(pNextMailbox)) >= ha->wReceiveBufferCount) {
+                            goto InvalidIpBufferHandle;
+                        }
+
+                        pBufferCB = &ha->pReceiveBufferCBs[lTagVal];
+
+                        if (!(pBufferCB->lFlags &  BCB_FLAGS_RISC_OWNS_BUFFER)) {
+                            goto InvalidIpBufferHandle;
+                        }
+
+                        /* Set buffer belongs to driver now */
+                        pBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER;
+
+                        lPacketSize = RD_REG_WORD(&reg->mailbox3);
+                        pBufferCB->lPacketSize = lPacketSize;
+                        pNextBufferCB = pBufferCB;
+
+                        for (wBufferCount = 1; ; wBufferCount++) {
+                            if (lPacketSize > lReceiveBufferSize) {
+                                pNextBufferCB->lBufferSize = lReceiveBufferSize;
+                                lPacketSize               -= lReceiveBufferSize;
+
+                                /* If split buffer, only use header size on 1st buffer */
+                                lReceiveBufferSize = ha->lReceiveBufferSize;
+
+                                pNextMailbox++;
+                                if ((lTagVal = RD_REG_WORD(pNextMailbox)) >=
+                                ha->wReceiveBufferCount) {
+                                    InvalidIpBufferHandle:
+                                    printk(KERN_WARNING "qla2100_isr: bad IP receive fast post handle %x\n",
+                                    lTagVal);
+                                    ha->flags.isp_abort_needed = TRUE;
+                                    return;
+                                }
+
+                                pNextBufferCB->pNextBufferCB = &ha->pReceiveBufferCBs[lTagVal];
+                                pNextBufferCB = pNextBufferCB->pNextBufferCB;
+
+                                if (!(pNextBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) {
+                                    goto InvalidIpBufferHandle;
+                                }
+
+                                /* Set buffer belongs to driver now */
+                                pNextBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER;
+                            } else {
+                                pNextBufferCB->lBufferSize = lPacketSize;
+                                pNextBufferCB->pNextBufferCB = NULL;
+                                break;
+                            }
+                        }
+
+                        /* Clear the semaphore lock , if it was set */
+                        if (RD_REG_WORD(&reg->semaphore) & BIT_0)
+                            WRT_REG_WORD(&reg->semaphore, 0);
+
+                        /* Pass received packet to IP driver */
+                        pBufferCB->wBufferCount = wBufferCount;
+
+                        (*ha->pReturnReceivePacketsRoutine)
+                        (ha->pReturnReceivePacketsContext,
+                        pBufferCB);
+
+                        /* Keep track of RISC buffer pointer (for IP reinit) */
+                        ha->wIpBufferOut += wBufferCount;
+                        if (ha->wIpBufferOut >= IP_BUFFER_QUEUE_DEPTH)
+                            ha->wIpBufferOut -= IP_BUFFER_QUEUE_DEPTH;
+
+                        return;
+                    }
+#endif /* FC_IP_SUPPORT ****************************************8*/
+
+                    if( mailbox[0] != MBA_SCSI_COMPLETION ) {
+#ifdef QL_DEBUG_LEVEL_4
+                        qla2100_print("qla2100_isr: non MBA_SCSI_COMPLETION ; Saving mailbox data\n");
+#endif
+                        wptr++;
+                        if (ha->device_id != QLA2300_DEVICE_ID) {
+                          *wptr++ = RD_REG_WORD(&reg->mailbox3);
+                          *wptr++ = qla2100_debounce_register(&reg->mailbox4);
+                          *wptr++ = qla2100_debounce_register(&reg->mailbox5);
+                          *wptr++ = RD_REG_WORD(&reg->mailbox6);
+                          *wptr   = RD_REG_WORD(&reg->mailbox7);
+                        } else {
+                          *wptr++ = RD_REG_WORD(&reg2300->mailbox3);
+                          *wptr++ = qla2100_debounce_register(&reg2300->mailbox4);
+                          *wptr++ = qla2100_debounce_register(&reg2300->mailbox5);
+                          *wptr++ = RD_REG_WORD(&reg2300->mailbox6);
+                          *wptr   = RD_REG_WORD(&reg2300->mailbox7);
+                        }
+                    }
+
+                    /* Clear the semaphore lock , if it was set */
+                    if (RD_REG_WORD(&reg->semaphore) & BIT_0)
+                        WRT_REG_WORD(&reg->semaphore, 0);
+
+#ifdef QL_DEBUG_LEVEL_4
+                    qla2100_print("qla2100_isr: +++ mailbox interrupt mailbox[0] = ");
+                    qla2100_output_number((u_long)mailbox[0], 16);
+                    qla2100_print("+++ \n");
+ #endif 
+                    /* Handle asynchronous (0x80xx) and 
+                       mailbox command completion (0x400x) events */ 
+                    switch( mailbox[0] ) {
+                        case MBA_SCSI_COMPLETION:   /* 0x8020 */
+                            if( ha->flags.online ) {
+                                /* Get outstanding command index. */
+                                index = (uint32_t)(mailbox[2] << 16 | mailbox[1]);
+                                /* Validate handle. */
+                                if( index < MAX_OUTSTANDING_COMMANDS ) {
+                                    sp = ha->outstanding_cmds[index];
+                                } else
+                                    sp = 0;
+
+                                if( sp ) {
+                                    /* Free outstanding command slot. */
+                                    ha->outstanding_cmds[index] = 0;
+
+                                    /* Save ISP completion status */
+                                    CMD_RESULT(sp->cmd) = DID_OK;
+            						sp->flags &= ~SRB_SENT;
+		                    /* v2.19.5b2 Reset port down retry on success. */
+			            sp->port_down_retry_count = ha->port_down_retry_count;
+        
+                                    QLA2100_TIMER_LOCK(ha);
+                                    ha->actthreads--;
+                                    /* Place block on done queue */
+                                    qla2100_stats.done_q_cnt++;
+                                    DEBUG(sp->state = 3;)
+                                    
+                                    sp->s_next = NULL;
+                                    sp->s_prev = *done_q_last;
+                                    if( !(*done_q_first) )
+                                        *done_q_first = sp;
+                                    else
+                                        (*done_q_last)->s_next = sp;
+                                    *done_q_last = sp;
+                                    QLA2100_TIMER_UNLOCK(ha);
+                                } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                    qla2100_print("qla2100_isr: ISP invalid handle\n");
+#endif
+                                    ha->flags.isp_abort_needed = TRUE;
+                                }
+                            }
+                            break;
+                        case MBA_RESET:                 /* Reset 0x8001*/
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: asynchronous RESET\n");
+#endif
+                            ha->flags.reset_marker = TRUE;
+                            break;
+                        case MBA_SYSTEM_ERR:        /* System Error 0x8002 */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: ISP System Error - mbx1=");
+                            qla2100_output_number((u_long)mailbox[1], 16);
+                            qla2100_print(", mbx2=");
+                            qla2100_output_number((u_long)mailbox[2], 16);
+                            qla2100_print(", mbx3=");
+                            qla2100_output_number((u_long)mailbox[3], 16);
+                            qla2100_print("\n");
+#endif
+                            printk(KERN_WARNING
+                            "!qla2100_isr: ISP System Error - mbx1=%xh, mbx2=%xh, mbx3=%xh",
+                            mailbox[1], mailbox[2], mailbox[3]);
+                            ha->flags.isp_abort_needed = TRUE;
+                            break;
+                        case MBA_REQ_TRANSFER_ERR:  /* Request Transfer Error */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: ISP Request Transfer Error\n");
+#endif
+                            printk(KERN_WARNING "qla2100: ISP Request Transfer Error\n");
+                            ha->flags.isp_abort_needed = TRUE;
+                            break;
+                        case MBA_RSP_TRANSFER_ERR:  /* Response Transfer Error */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: ISP Response Transfer Error\n");
+#endif
+                            printk(KERN_WARNING "qla2100: ISP Response Transfer Error\n");
+                            ha->flags.isp_abort_needed = TRUE;
+                            break;
+                        case MBA_WAKEUP_THRES:      /* Request Queue Wake-up */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: asynchronous WAKEUP_THRES\n");
+#endif
+                            break;
+                        case MBA_LIP_OCCURRED:      /* Loop Initialization Procedure */
+                            if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): LIP occurred.\n",(int)ha->host_no);       
+                            DEBUG(sprintf(debug_buff,"\n\nscsi(%d): LIP occurred.\n",(int)ha->host_no);)
+                            DEBUG(qla2100_print(debug_buff));
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_LIP_OCCURRED\n");
+#endif
+		                    ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED;
+                            /* Save LIP sequence. */
+                            ha->lip_seq = mailbox[1];
+                            if( ha->loop_state != LOOP_DOWN ) {
+                                    ha->loop_state = LOOP_DOWN;
+                                    ha->loop_down_timer = LOOP_DOWN_TIME;
+                            }
+                            ha->lip_count++;
+                            break;
+                        case MBA_LOOP_UP:
+                            printk(KERN_INFO "scsi(%d): LOOP UP detected\n",(int)ha->host_no);
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: asynchronous MBA_LOOP_UP\n");
+#endif
+                            ha->loop_state = LOOP_UP;
+                            break;
+                        case MBA_LOOP_DOWN:
+                            printk(KERN_INFO "scsi(%d): LOOP DOWN detected\n",(int)ha->host_no);
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr: asynchronous MBA_LOOP_DOWN\n");
+#endif
+		                    ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED;
+                            if( ha->loop_state != LOOP_DOWN ) {
+                                    ha->loop_state = LOOP_DOWN;
+                                    ha->loop_down_timer = LOOP_DOWN_TIME;
+                            }
+                            break;
+                        case MBA_LIP_RESET:         /* LIP reset occurred. */
+                            if(!qla2100_quiet) printk(KERN_INFO "scsi(%d): LIP reset occurred\n",(int)ha->host_no);
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_LIP_RESET\n");
+#endif
+		            ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED;
+                            ha->flags.reset_marker = TRUE;
+                            ha->loop_down_timer = LOOP_DOWN_TIME;
+                            ha->loop_state = LOOP_DOWN;
+                            ha->operating_mode = LOOP;
+                            break;
+                        case MBA_LINK_MODE_UP:      /* Link mode up. */
+                            DEBUG(printk(KERN_INFO "scsi(%d): Link node is up\n",(int)ha->host_no);)
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_LINK_MODE_UP\n");
+#endif
+		                    ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED;
+                            break;
+                        case MBA_UPDATE_CONFIG:      /* Update Configuration. */
+                            printk(KERN_INFO "scsi(%d): Configuration change detected: value %d.\n",(int)ha->host_no,mailbox[1]);
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_UPDATE_CONFIG\n");
+#endif
+                            ha->flags.update_config_needed = 1;
+                            ha->loop_state = LOOP_DOWN;  /* dg - 03/30 */
+                            ha->flags.isp_abort_needed = TRUE;
+                            break;
+                        case MBA_PORT_UPDATE:       /* Port database update occurred. */
+                            DEBUG(printk("scsi(%d): Port database changed\n",(int)ha->host_no);)
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_PORT_UPDATE\n");
+#endif
+                            ha->loop_down_timer = 0;
+                            ha->flags.loop_resync_needed = TRUE;
+                            ha->loop_state = LOOP_UPDATE;
+                            break;
+                        case MBA_SCR_UPDATE:        /* State Change Registration. */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_RSCR_UPDATE\n");
+#endif
+                            mailbox[1] = RD_REG_WORD(&reg->mailbox1);
+                            mailbox[2] = RD_REG_WORD(&reg->mailbox2);
+
+                            DEBUG(printk("scsi(%d): RSCN database changed - 0x%x,0x%x\n",(int)ha->host_no,mailbox[1],mailbox[2]);)
+#ifdef RCSN
+                            index = ha->rscn_in_ptr + 1;
+                            if (index == MAX_RSCN_COUNT)
+                                index = 0;
+                            if (index != ha->rscn_out_ptr) {
+                                    ha->rscn_queue[ha->rscn_in_ptr].format =
+                                    MSB(mb[1]);
+                                    ha->rscn_queue[ha->rscn_in_ptr].d_id.b.domain =
+                                    LSB(mb[1]);
+                                    ha->rscn_queue[ha->rscn_in_ptr].d_id.b.area =
+                                    MSB(mb[2]);
+                                    ha->rscn_queue[ha->rscn_in_ptr].d_id.b.al_pa =
+                                    LSB(mb[2]);
+                                    ha->rscn_in_ptr = (uint8_t)index;
+                            } else {
+                                    ha->device_flags |= RSCN_QUEUE_OVERFLOW;
+                            }
+#endif
+                            ha->device_flags |= RSCN_UPDATE;
+                            ha->loop_down_timer = 0;
+                            ha->flags.loop_resync_needed = TRUE;
+                            ha->loop_state = LOOP_UPDATE;
+		         /*    ha->dpc_flags = ha->dpc_flags | COMMAND_WAIT_NEEDED; */
+                            break;
+                        case MBA_CTIO_COMPLETION:
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print(
+                            "qla2100_isr: asynchronous MBA_CTIO_COMPLETION\n");
+#endif
+                            break;
+                        default:
+                            if( mailbox[0] < MBA_ASYNC_EVENT  /* 0x8000 */) {
+                                    wptr = &mailbox[0];
+                                    ha->mailbox_out[0] = *wptr++;
+                                    ha->mailbox_out[1] = *wptr++;
+                                    ha->mailbox_out[2] = *wptr++;
+                                    ha->mailbox_out[3] = *wptr++;
+                                    ha->mailbox_out[4] = *wptr++;
+                                    ha->mailbox_out[5] = *wptr++;
+                                    ha->mailbox_out[6] = *wptr++;
+                                    ha->mailbox_out[7] = *wptr;
+                                    ha->flags.mbox_int = TRUE;
+#ifdef QL_DEBUG_LEVEL_2
+	if (mailbox[0] != 0x4000) {
+                            qla2100_print("qla2100_isr: MBA Switch Default mailbox[0]= ");
+                            qla2100_output_number(mailbox[0] , 16);
+                            qla2100_print("\n");
+	}
+#endif 
+#ifdef QL_DEBUG_LEVEL_4
+                                    qla2100_print("qla2100_isr: Setting flags.mbox_int=1 in Default mailbox[0]= ");
+                                    qla2100_output_number(mailbox[0] , 16);
+                                    qla2100_print("\n");
+#endif
+                            }
+                            break;
+                    } /* switch */
+                } else { /* not a SEMAPHORE Set Completion */
+                   if (ha->device_id != QLA2300_DEVICE_ID) 
+                     mailbox[5]=qla2100_debounce_register(&reg->mailbox5);
+                   else 
+                     mailbox[5]=qla2100_debounce_register(&reg2300->rsp_q_in);
+
+                    WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
+                    /*
+                    * Response Ring Update
+                    */
+                    /* Clear mailbox busy flag for 2300s;
+                       so we don't ignore its Respose Ring Updates 
+                       during send of mailbox command */
+                    if (ha->device_id == QLA2300_DEVICE_ID) 
+                        ha->flags.mbox_busy = FALSE;
+
+                    if( ha->flags.online && !(ha->flags.mbox_busy) ) { 
+                        if( mailbox[5] < RESPONSE_ENTRY_CNT ) {
+                            while( ha->rsp_ring_index != mailbox[5] ) {
+                                pkt = ha->response_ring_ptr;
+
+#ifdef QL_DEBUG_LEVEL_5
+                                qla2100_print("qla2100_isr: ha->rsp_ring_index = ");
+                                qla2100_output_number((u_long)ha->rsp_ring_index, 16);
+                                qla2100_print(" mailbox[5] = ");
+                                qla2100_output_number((u_long)mailbox[5], 16);
+                                qla2100_print("\n");
+                                qla2100_print("\nqla2100_isr: response packet data\n");
+                                qla2100_dump_buffer((uint8_t *)pkt, RESPONSE_ENTRY_SIZE);
+#endif
+
+#ifdef FC_IP_SUPPORT /************************************************/
+                                /* Handle IP send completion */
+                                if (pkt->entry_type == ET_IP_COMMAND_64) {
+                                    uint32_t            lTagVal;
+                                    SEND_CB             *pSendCB;
+
+                                    /* Set packet pointer from queue entry handle */
+                                    if ((lTagVal = pkt->handle) < MAX_SEND_PACKETS) {
+                                        if ((pSendCB = (SEND_CB *)ha->apActiveIpQueue[lTagVal]) != NULL) {
+                                            ha->apActiveIpQueue[lTagVal] = NULL;
+
+                                            /* Return send packet to IP driver */
+                                            (*ha->pSendCompletionRoutine)(pSendCB);
+                                        } else {
+                                            /* Invalid handle from RISC, reset RISC firmware */
+                                            printk(KERN_WARNING "qla2100_isr: bad IP send handle %x\n", lTagVal);
+                                            ha->flags.isp_abort_needed = TRUE;
+                                        }
+                                    } else {
+                                        /* Invalid handle from RISC, reset RISC firmware */
+                                        printk(KERN_WARNING "qla2100_isr: bad IP send handle %x\n", lTagVal);
+                                        ha->flags.isp_abort_needed = TRUE;
+                                    }
+
+                                    /* Adjust ring index. */
+                                    ha->rsp_ring_index++;
+                                    if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) {
+                                        ha->rsp_ring_index = 0;
+                                        ha->response_ring_ptr = ha->response_ring;
+                                    } else
+                                        ha->response_ring_ptr++;
+                                        if (ha->device_id != QLA2300_DEVICE_ID) 
+                                             WRT_REG_WORD(&reg->mailbox5, ha->rsp_ring_index);
+                                        else     
+                                             WRT_REG_WORD(&reg2300->rsp_q_out, ha->rsp_ring_index);
+                                    continue;
+                                }
+
+                                /* Handle IP receive packet */
+                                else if (pkt->entry_type == ET_IP_RECEIVE) {
+                                    PIP_RECEIVE_ENTRY   pIpReceiveEntry = (PIP_RECEIVE_ENTRY)pkt;
+                                    PBUFFER_CB          pBufferCB, pNextBufferCB;
+                                    uint32_t            lTagVal;
+                                    uint32_t            lPacketSize;
+                                    uint16_t            wBufferCount;
+                                    uint32_t            lReceiveBufferSize;
+
+                                    /* If split buffer, set header size for 1st buffer */
+                                    if (pIpReceiveEntry->wCompletionStatus & IP_REC_STATUS_SPLIT_BUFFER)
+                                        lReceiveBufferSize = ha->wHeaderSize;
+                                    else
+                                        lReceiveBufferSize = ha->lReceiveBufferSize;
+
+                                    if ((lTagVal = pIpReceiveEntry->waBufferHandle[0]) >=
+                                    ha->wReceiveBufferCount) {
+                                        /* Invalid handle from RISC, reset RISC firmware */
+                                        printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal);
+                                        ha->flags.isp_abort_needed = TRUE;
+                                        goto InvalidIpHandle;
+                                    }
+                                    pBufferCB = &ha->pReceiveBufferCBs[lTagVal];
+
+                                    if (!(pBufferCB->lFlags &  BCB_FLAGS_RISC_OWNS_BUFFER)) {
+                                        /* Invalid handle from RISC, reset RISC firmware */
+                                        printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal);
+                                        ha->flags.isp_abort_needed = TRUE;
+                                        goto InvalidIpHandle;
+                                    }
+
+                                    /* Set buffer belongs to driver now */
+                                    pBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER;
+
+                                    lPacketSize = pIpReceiveEntry->wSequenseLength;
+                                    pBufferCB->lPacketSize = lPacketSize;
+                                    pNextBufferCB = pBufferCB;
+
+                                    for (wBufferCount = 1; ; wBufferCount++) {
+                                        if (lPacketSize > lReceiveBufferSize) {
+                                            pNextBufferCB->lBufferSize = lReceiveBufferSize;
+                                            lPacketSize               -= lReceiveBufferSize;
+
+                                            /* If split buffer, only use header size on 1st buffer */
+                                            lReceiveBufferSize = ha->lReceiveBufferSize;
+
+                                            if ((lTagVal = pIpReceiveEntry->waBufferHandle[wBufferCount]) >=
+                                            ha->wReceiveBufferCount) {
+                                                /* Invalid handle from RISC, reset RISC firmware */
+                                                printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal);
+                                                ha->flags.isp_abort_needed = TRUE;
+                                                goto InvalidIpHandle;
+                                            }
+                                            pNextBufferCB->pNextBufferCB = &ha->pReceiveBufferCBs[lTagVal];;
+                                            pNextBufferCB = pNextBufferCB->pNextBufferCB;
+
+                                            if (!(pNextBufferCB->lFlags & BCB_FLAGS_RISC_OWNS_BUFFER)) {
+                                                /* Invalid handle from RISC, reset RISC firmware */
+                                                printk(KERN_WARNING "qla2100_isr: bad IP buffer handle %x\n", lTagVal);
+                                                ha->flags.isp_abort_needed = TRUE;
+                                                goto InvalidIpHandle;
+                                            }
+
+                                            /* Set buffer belongs to driver now */
+                                            pNextBufferCB->lFlags &= ~BCB_FLAGS_RISC_OWNS_BUFFER;
+                                        } else {
+                                            pNextBufferCB->lBufferSize = lPacketSize;
+                                            pNextBufferCB->pNextBufferCB = NULL;
+                                            break;
+                                        }
+                                    }
+
+                                    /* Check for incoming ARP packet with matching IP address */
+                                    if (pIpReceiveEntry->wServiceClass == 0) {
+                                        PPACKET_HEADER  pPacket = (PPACKET_HEADER)pBufferCB->pBuffer;
+                                        PIP_DEVICE_BLOCK pIpDevice;
+                                        uint8_t     acPortId[3];
+
+                                        /* Scan list of IP devices to see if login needed */
+                                        for (pIpDevice = ha->pIpDeviceTop; pIpDevice != NULL;
+                                        pIpDevice = pIpDevice->pNextIpDevice) {
+                                            if (*(uint16_t *)(&pIpDevice->acWorldWideName[2]) ==
+                                            pPacket->sNetworkHeader.wSourceAddrHigh &&
+                                            *(uint32_t *)(&pIpDevice->acWorldWideName[4]) ==
+                                            pPacket->sNetworkHeader.lSourceAddrLow) {
+                                                /* Device already in IP list, skip login */
+                                                goto SkipDeviceLogin;
+                                            }
+                                        }
+
+                                        /* Device not in list, need to do login */
+                                        acPortId[0] = pIpReceiveEntry->cS_IDHigh;
+                                        acPortId[1] = (uint8_t)(pIpReceiveEntry->wS_IDLow >> 8);
+                                        acPortId[2] = (uint8_t)pIpReceiveEntry->wS_IDLow;
+
+                                        /* Make sure its not a local device */
+                                        if (acPortId[0] == ha->port_id[0] &&
+                                        acPortId[1] == ha->port_id[1]) {
+                                            goto SkipDeviceLogin;
+                                        }
+
+                                        if (qla2x00_add_new_ip_device(ha, PUBLIC_LOOP_DEVICE,
+                                        acPortId,
+                                        (uint8_t *)&pPacket->sNetworkHeader.wSourceNAA,
+                                        TRUE) == QL_STATUS_FATAL_ERROR) {
+                                            /* Fatal error, reinitialize */
+                                            ha->flags.isp_abort_needed = TRUE;
+                                        }
+                                    }
+                                    SkipDeviceLogin:
+                                    /* Pass received packet to IP driver */
+                                    pBufferCB->wBufferCount = wBufferCount;
+
+                                    (*ha->pReturnReceivePacketsRoutine)
+                                    (ha->pReturnReceivePacketsContext,
+                                    pBufferCB);
+
+                                    /* Keep track of RISC buffer pointer (for IP reinit) */
+                                    ha->wIpBufferOut += wBufferCount;
+                                    if (ha->wIpBufferOut >= IP_BUFFER_QUEUE_DEPTH)
+                                        ha->wIpBufferOut -= IP_BUFFER_QUEUE_DEPTH;
+                                    InvalidIpHandle:
+                                    /* Adjust ring index. */
+                                    ha->rsp_ring_index++;
+                                    if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) {
+                                        ha->rsp_ring_index = 0;
+                                        ha->response_ring_ptr = ha->response_ring;
+                                    } else
+                                        ha->response_ring_ptr++;
+                                        if (ha->device_id != QLA2300_DEVICE_ID) 
+                                            WRT_REG_WORD(&reg->mailbox5, ha->rsp_ring_index);
+                                        else
+                                            WRT_REG_WORD(&reg2300->rsp_q_out, ha->rsp_ring_index);
+                                        continue;
+                                }
+
+                                /* Handle IP FARP request */
+                                else if (pkt->entry_type == ET_IP_FARP_REQUEST) {
+                                    PIP_FARP_REQUEST_ENTRY  pIpFarpRequestEntry;
+                                    uint8_t                 acPortId[3];
+                                    uint8_t                 acPortName[8];
+
+                                    pIpFarpRequestEntry = (PIP_FARP_REQUEST_ENTRY)pkt;
+                                    acPortId[0] = pIpFarpRequestEntry->cRequesterPortIdHigh;
+                                    acPortId[1] = (uint8_t)(pIpFarpRequestEntry->wRequesterPortIdLow >> 8);
+                                    acPortId[2] = (uint8_t)pIpFarpRequestEntry->wRequesterPortIdLow;
+                                    acPortName[0] = pIpFarpRequestEntry->acRequesterPortName[7];
+                                    acPortName[1] = pIpFarpRequestEntry->acRequesterPortName[6];
+                                    acPortName[2] = pIpFarpRequestEntry->acRequesterPortName[5];
+                                    acPortName[3] = pIpFarpRequestEntry->acRequesterPortName[4];
+                                    acPortName[4] = pIpFarpRequestEntry->acRequesterPortName[3];
+                                    acPortName[5] = pIpFarpRequestEntry->acRequesterPortName[2];
+                                    acPortName[6] = pIpFarpRequestEntry->acRequesterPortName[1];
+                                    acPortName[7] = pIpFarpRequestEntry->acRequesterPortName[0];
+
+                                    /* Login and add device to IP database */
+                                    if (qla2x00_add_new_ip_device(ha, PUBLIC_LOOP_DEVICE,
+                                    acPortId,
+                                    acPortName,
+                                    TRUE) == QL_STATUS_FATAL_ERROR) {
+                                        /* Fatal error, reinitialize */
+                                        ha->flags.isp_abort_needed = TRUE;
+                                    }
+
+                                    /* Adjust ring index. */
+                                    ha->rsp_ring_index++;
+                                    if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) {
+                                        ha->rsp_ring_index = 0;
+                                        ha->response_ring_ptr = ha->response_ring;
+                                    } else
+                                        ha->response_ring_ptr++;
+                                        if (ha->device_id != QLA2300_DEVICE_ID) 
+                                          WRT_REG_WORD(&reg->mailbox5, ha->rsp_ring_index);
+                                        else
+                                          WRT_REG_WORD(&reg2300->rsp_q_out, ha->rsp_ring_index);
+
+                                    continue;
+                                }
+#endif /* FC_IP_SUPPORT *******************************************/
+
+                                if( pkt->entry_type == STATUS_TYPE ||
+                                    pkt->entry_status ) {
+                                    ha->actthreads--; 
+                                    if( pkt->entry_type == STATUS_TYPE ) {
+                                        qla2100_status_entry(ha, (sts_entry_t *)pkt,
+                                        done_q_first, done_q_last);
+                                        /* DEBUG(printk("qla2100_isr: RespRingUpdate STATUS TYPE\n");) */
+                                    } else {
+                                        qla2100_error_entry(ha, pkt,
+                                        done_q_first, done_q_last);
+                                        /* DEBUG(printk("qla2100_isr: RespRingUpdate ERROR TYPE \n");)*/
+                                    }
+                                    /* Adjust ring index. */
+                                    ha->rsp_ring_index++;
+                                    if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) {
+                                        ha->rsp_ring_index = 0;
+                                        ha->response_ring_ptr = ha->response_ring;
+                                    } else
+                                        ha->response_ring_ptr++;
+                                        if (ha->device_id != QLA2300_DEVICE_ID) 
+                                           WRT_REG_WORD(&reg->mailbox5, ha->rsp_ring_index);
+                                        else
+                                           WRT_REG_WORD(&reg2300->rsp_q_out, ha->rsp_ring_index);
+                                } else {
+                                    pkt = &response_entry;
+
+                                    /* Copy packet. */
+                                    dptr1 = (uint32_t *)ha->response_ring_ptr;
+                                    dptr2 = (uint32_t *)pkt;
+                                    for( index = 0; index < RESPONSE_ENTRY_SIZE/4;
+                                    index++ )
+                                        *dptr2++ = *dptr1++;
+
+                                    /* Adjust ring index. */
+                                    ha->rsp_ring_index++;
+                                    if( ha->rsp_ring_index == RESPONSE_ENTRY_CNT ) {
+                                        ha->rsp_ring_index = 0;
+                                        ha->response_ring_ptr = ha->response_ring;
+                                    } else
+                                        ha->response_ring_ptr++;
+                                        if (ha->device_id != QLA2300_DEVICE_ID) 
+                                          WRT_REG_WORD(&reg->mailbox5, ha->rsp_ring_index);
+                                        else
+                                          WRT_REG_WORD(&reg2300->rsp_q_out, ha->rsp_ring_index);
+
+                                    /* Release interrupt specific lock */
+                                    QLA2100_INTR_UNLOCK(ha);
+
+#if QLA2100_TARGET_MODE_SUPPORT
+                                    switch( pkt->entry_type ) {
+                                        case ACCEPT_TGT_IO_TYPE:
+                                            qla2100_atio_entry(ha, (atio_entry_t *)pkt);
+                                            break;
+                                        case IMMED_NOTIFY_TYPE:
+                                            qla2100_notify_ack(ha, (notify_entry_t *)pkt);
+                                            break;
+                                        default:
+                                            break;
+                                    }
+#endif   /**** FC_TARGET_MODE_SUPPORT */
+
+                                    /* Acquire interrupt specific lock */
+                                    QLA2100_INTR_LOCK(ha);
+                                }
+                            }
+                        } else {
+                            ha->flags.isp_abort_needed = TRUE;
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_isr:  $$$ Response Pointer Error $$$ mb5=\n");
+                            qla2100_output_number((u_long)mailbox[5], 16);
+                            qla2100_print(" \n");
+                            printk(KERN_WARNING "qla2100_isr: [ERROR] Response pointer Error mailbox[5]=%x\n",mailbox[5]);
+#endif
+                        }
+                    }  
+                }
+
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_isr"); 
+#endif
+}
+
+
+
+/*
+*  qla2100_rst_aen
+*      Processes asynchronous reset.
+*
+* Input:
+*      ha  = adapter block pointer.
+*/
+STATIC void
+qla2100_rst_aen(scsi_qla_host_t *ha) {
+#if QL2100_TARGET_MODE_SUPPORT
+                notify_entry_t nentry;
+#endif /* QL2100_TARGET_MODE_SUPPORT */
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_rst_aen");
+#endif
+
+                if( ha->flags.online && !ha->flags.reset_active &&
+                !ha->loop_down_timer && !ha->flags.abort_isp_active ) {
+                    ha->flags.reset_active = TRUE;
+                    do {
+                        ha->flags.reset_marker = FALSE;
+
+                        /* Issue marker command. */
+                        qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+#if QL2100_TARGET_MODE_SUPPORT
+                        if( !ha->loop_down_timer && !ha->flags.reset_marker ) {
+                            /* Issue notify acknowledgement command. */
+                            BZERO((caddr_t)&nentry, sizeof(notify_entry_t));
+                            nentry.initiator_id = ha->id;
+                            /* dg 7/3/99 nentry.target_id = ha->id; */
+                            nentry.task_flags = BIT_13;
+                            qla2100_notify_ack(ha, &nentry);
+                        }
+#endif /* QL2100_TARGET_MODE_SUPPORT */
+                    }while( !ha->loop_down_timer && ha->flags.reset_marker );
+                    ha->flags.reset_active = FALSE;
+                }
+
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_rst_aen");
+#endif
+}
+
+#if  QLA2100_TARGET_MODE_SUPPORT
+/*
+*  qla2100_atio_entry
+*      Processes received ISP accept target I/O entry.
+*
+* Input:
+*      ha  = adapter block pointer.
+*      pkt = entry pointer.
+*/
+STATIC void
+qla2100_atio_entry(scsi_qla_host_t *ha, atio_entry_t *pkt) {
+                uint64_t  *a64;
+                uint64_t  *end_a64;
+        u_long    phy_addr[2];
+        u_long    end_addr[2];
+                uint32_t  len;
+                uint32_t  offset;
+                uint8_t   t;
+                uint8_t   *sense_ptr;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_atio_entry: entered\n");
+#endif
+
+                t = pkt->initiator_id;
+                sense_ptr = ha->tsense + t * TARGET_SENSE_SIZE;
+                a64 = (uint64_t *)&phy_addr[0];
+                end_a64 = (uint64_t *)&end_addr[0];
+
+                switch( pkt->status & ~BIT_7 ) {
+                    case 7:                         /* Path invalid */
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                        qla2100_print("qla2100_atio_entry: Path invalid\n");
+#endif
+                        break;
+                    case 0x16:                  /* Requested Capability Not Available */
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                        qla2100_print(
+                        "qla2100_atio_entry: Requested Capability Not Available\n");
+#endif
+                        break;
+                    case 0x17:                  /* Bus Device Reset Message Received */
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                        qla2100_print(
+                        "qla2100_atio_entry: Bus Device Reset Message Received\n");
+#endif
+                        break;
+                    case 0x3D:                  /* CDB Received */
+
+                        /* Check for invalid LUN */
+                        if( pkt->lun && pkt->cdb[0] != SS_INQUIR &&
+                        pkt->cdb[0] != SS_REQSEN )
+                            pkt->cdb[0] = SS_TEST;
+
+                        switch( pkt->cdb[0] ) {
+                        case SS_TEST:
+#ifdef QL_DEBUG_LEVEL_3
+                            qla2100_print("qla2100_atio_entry: SS_TEST\n");
+#endif
+                            BZERO(sense_ptr, TARGET_SENSE_SIZE);
+                            len = 0;
+                            if( pkt->lun == 0 )
+                                pkt->scsi_status = S_GOOD;
+                            else {
+                                *sense_ptr = 0x70;
+                                *(sense_ptr+2) = SD_ILLREQ;
+                                *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                *(sense_ptr+12) = SC_INVLUN;
+                                pkt->scsi_status = S_CKCON;
+                            }
+                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_NO_DATA);
+                            break;
+                        case SS_REQSEN:
+#ifdef QL_DEBUG_LEVEL_3
+                            qla2100_print("qla2100_atio_entry: SS_REQSEN\n");
+#endif
+                            phy_addr[0] = ha->tsense_dma;
+                            phy_addr[1] = 0;
+                            *a64 += t * TARGET_SENSE_SIZE;
+                            if( pkt->cdb[4] > TARGET_SENSE_SIZE )
+                                len = TARGET_SENSE_SIZE;
+                            else
+                                len = pkt->cdb[4];
+                            pkt->scsi_status = S_GOOD;
+                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_DATA_IN);
+                            break;
+                        case SS_INQUIR:
+#ifdef QL_DEBUG_LEVEL_3
+                            qla2100_print("qla2100_atio_entry: SS_INQUIR\n");
+#endif
+                            BZERO(sense_ptr, TARGET_SENSE_SIZE);
+                            phy_addr[0] = ha->tbuf_dma;
+                            phy_addr[1] = 0;
+                            *a64 += TARGET_INQ_OFFSET;
+
+                            if( pkt->lun == 0 ) {
+                                    ha->tbuf->inq.id_type = ID_PROCESOR;
+                                    ha->tbuf->inq.id_pqual = ID_QOK;
+                            } else {
+                                    ha->tbuf->inq.id_type = ID_NODEV;
+                                    ha->tbuf->inq.id_pqual = ID_QNOLU;
+                            }
+
+                            if( pkt->cdb[4] > sizeof(struct ident) )
+                                len = sizeof(struct ident);
+                            else
+                                len = pkt->cdb[4];
+                            pkt->scsi_status = S_GOOD;
+                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_DATA_IN);
+                            break;
+                        case SM_WRDB:
+                            BZERO(sense_ptr, TARGET_SENSE_SIZE);
+                            offset = pkt->cdb[5];
+                            offset |= pkt->cdb[4] << 8;
+                            offset |= pkt->cdb[3] << 16;
+                            len = pkt->cdb[8];
+                            len |= pkt->cdb[7] << 8;
+                            len |= pkt->cdb[6] << 16;
+                            end_addr[0] = phy_addr[0] = ha->tbuf_dma;
+                            end_addr[1] = phy_addr[1] = 0;
+                            *end_a64 += TARGET_DATA_OFFSET + TARGET_DATA_SIZE;
+                            switch( pkt->cdb[1] & 7 ) {
+                                case RW_BUF_HDATA:
+#ifdef QL_DEBUG_LEVEL_3
+                                    qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_HDATA\n");
+#endif
+                                    if( len > TARGET_DATA_SIZE + 4 ) {
+#ifdef QL_DEBUG_LEVEL_2
+                                        qla2100_print("qla2100_atio_entry: SM_WRDB, length > buffer size\n");
+#endif
+                                        *sense_ptr = 0x70;
+                                        *(sense_ptr+2) = SD_ILLREQ;
+                                        *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                        *(sense_ptr+12) = SC_ILLCDB;
+                                        pkt->scsi_status = S_CKCON;
+                                        pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                        OF_NO_DATA);
+                                        len = 0;
+                                    } else if( len ) {
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags =(uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_DATA_OUT);
+                                    } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_WRDB, zero length\n");
+#endif
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    }
+
+                                    break;
+                                case RW_BUF_DATA:
+#ifdef QL_DEBUG_LEVEL_3
+                                    qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_DATA\n");
+#endif
+                                    *a64 += offset + TARGET_DATA_OFFSET;
+                                    if( pkt->cdb[2] != 0 || *a64 >= *end_a64 ||
+                                    *a64 + len > *end_a64 ) {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_WRDB, RW_BUF_DATA BAD\n");
+                                            qla2100_print("buf_id=");
+                        qla2100_output_number((u_long)pkt->cdb[2], 16);
+                        qla2100_print(", offset=");
+                        qla2100_output_number((u_long)offset, 16);
+                                            qla2100_print(", length=");
+                        qla2100_output_number((u_long)len, 16);
+                                            qla2100_print("\n");
+#endif
+                                            *sense_ptr = 0x70;
+                                            *(sense_ptr+2) = SD_ILLREQ;
+                                            *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                            *(sense_ptr+12) = SC_ILLCDB;
+                                            len = 0;
+                                            pkt->scsi_status = S_CKCON;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    } else if( len ) {
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags =(uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_DATA_OUT);
+                                    } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_WRDB, zero length\n");
+#endif
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    }
+                                    break;
+                                default:
+#ifdef QL_DEBUG_LEVEL_2
+                                    qla2100_print("qla2100_atio_entry: SM_WRDB unknown mode\n");
+#endif
+                                    *sense_ptr = 0x70;
+                                    *(sense_ptr+2) = SD_ILLREQ;
+                                    *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                    *(sense_ptr+12) = SC_ILLCDB;
+                                    len = 0;
+                                    pkt->scsi_status = S_CKCON;
+                                    pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                    OF_NO_DATA);
+                                    break;
+                            }
+                            break;
+                        case SM_RDDB:
+                            BZERO(sense_ptr, TARGET_SENSE_SIZE);
+                            offset = pkt->cdb[5];
+                            offset |= pkt->cdb[4] << 8;
+                            offset |= pkt->cdb[3] << 16;
+                            len = pkt->cdb[8];
+                            len |= pkt->cdb[7] << 8;
+                            len |= pkt->cdb[6] << 16;
+                            end_addr[0] = phy_addr[0] = ha->tbuf_dma;
+                            end_addr[1] = phy_addr[1] = 0;
+                            *end_a64 += TARGET_DATA_OFFSET + TARGET_DATA_SIZE;
+                            switch( pkt->cdb[1] & 7 ) {
+                                case RW_BUF_HDATA:
+#ifdef QL_DEBUG_LEVEL_3
+                                    qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_HDATA\n");
+#endif
+                                    if( len ) {
+                                        ha->tbuf->hdr[0] = 0;
+                                        ha->tbuf->hdr[1] =
+                                        (uint8_t)(TARGET_DATA_SIZE >> 16);
+                                        ha->tbuf->hdr[2] =
+                                        (uint8_t)(TARGET_DATA_SIZE >> 8);
+                                        ha->tbuf->hdr[3] = (uint8_t)TARGET_DATA_SIZE;
+                                        if( len > TARGET_DATA_SIZE + 4 )
+                                            len = TARGET_DATA_SIZE + 4;
+                                        pkt->scsi_status = S_GOOD;
+                                        pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                        OF_DATA_IN);
+                                    } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n");
+#endif
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    }
+                                    break;
+                                case RW_BUF_DATA:
+#ifdef QL_DEBUG_LEVEL_3
+                                    qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DATA\n");
+#endif
+                                    *a64 += offset + TARGET_DATA_OFFSET;
+                                    if( pkt->cdb[2] != 0 || *a64 >= *end_a64 ) {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DATA BAD\n");
+                                            qla2100_print("buf_id=");
+                        qla2100_output_number((u_long)pkt->cdb[2], 16);
+                        qla2100_print(", offset=");
+                        qla2100_output_number((u_long)offset, 16);
+                                            qla2100_print("\n");
+#endif
+                                            *sense_ptr = 0x70;
+                                            *(sense_ptr+2) = SD_ILLREQ;
+                                            *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                            *(sense_ptr+12) = SC_ILLCDB;
+                                            len = 0;
+                                            pkt->scsi_status = S_CKCON;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    } else {
+                                            if( *a64 + len > *end_a64 )
+                                                len = *end_a64 - *a64;
+                                            if( len ) {
+                                                pkt->scsi_status = S_GOOD;
+                                                pkt->flags = (uint16_t)(OF_SSTS |
+                                                OF_INC_RC | OF_DATA_IN);
+                                            } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                                    qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n");
+#endif
+                                                    pkt->scsi_status = S_GOOD;
+                                                    pkt->flags = (uint16_t)(OF_SSTS |
+                                                    OF_INC_RC | OF_NO_DATA);
+                                            }
+                                    }
+                                    break;
+                                case RW_BUF_DESC:
+#ifdef QL_DEBUG_LEVEL_3
+                                    qla2100_print("qla2100_atio_entry: SM_RDDB, RW_BUF_DESC\n");
+#endif
+                                    if( len ) {
+                                            if( len > 4 )
+                                                len = 4;
+
+                                            ha->tbuf->hdr[0] = 0;
+                                            if( pkt->cdb[2] != 0 ) {
+                                                ha->tbuf->hdr[1] = 0;
+                                                ha->tbuf->hdr[2] = 0;
+                                                ha->tbuf->hdr[3] = 0;
+                                            } else {
+                                                    ha->tbuf->hdr[1] =
+                                                    (uint8_t)(TARGET_DATA_SIZE >> 16);
+                                                    ha->tbuf->hdr[2] =
+                                                    (uint8_t)(TARGET_DATA_SIZE >> 8);
+                                                    ha->tbuf->hdr[3] =
+                                                    (uint8_t)TARGET_DATA_SIZE;
+                                            }
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_DATA_IN);
+                                    } else {
+#ifdef QL_DEBUG_LEVEL_2
+                                            qla2100_print("qla2100_atio_entry: SM_RDDB, zero length\n");
+#endif
+                                            pkt->scsi_status = S_GOOD;
+                                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                            OF_NO_DATA);
+                                    }
+                                    break;
+                                default:
+#ifdef QL_DEBUG_LEVEL_2
+                                    qla2100_print("qla2100_atio_entry: SM_RDDB unknown mode\n");
+#endif
+                                    *sense_ptr = 0x70;
+                                    *(sense_ptr+2) = SD_ILLREQ;
+                                    *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                                    *(sense_ptr+12) = SC_ILLCDB;
+                                    len = 0;
+                                    pkt->scsi_status = S_CKCON;
+                                    pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC |
+                                    OF_NO_DATA);
+                                    break;
+                            }
+                            break;
+                        default:
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("qla2100_atio_entry: Unknown SCSI command\n");
+                            qla2100_dump_buffer((uint8_t *)&pkt->cdb[0], MAX_CMDSZ);
+#endif
+                            BZERO(sense_ptr, TARGET_SENSE_SIZE);
+                            *sense_ptr = 0x70;
+                            *(sense_ptr+2) = SD_ILLREQ;
+                            *(sense_ptr+7) = TARGET_SENSE_SIZE-8;
+                            *(sense_ptr+12) = SC_INVOPCODE;
+                            len = 0;
+                            pkt->scsi_status = S_CKCON;
+                            pkt->flags = (uint16_t)(OF_SSTS | OF_INC_RC | OF_NO_DATA);
+                            break;
+                        }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+                        if ( ha->flags.enable_64bit_addressing )
+                            qla2100_64bit_continue_io(ha, pkt, len, &phy_addr);
+                        else
+#endif
+                        qla2100_32bit_continue_io(ha, pkt, len, &phy_addr);
+                        break;
+                    default:
+                        break;
+                }
+
+#ifdef QL_DEBUG_LEVEL_3
+                LEAVE("qla2100_atio_entry: exiting normally\n");
+#endif
+}
+#endif  /* QLA2100_TARGET_MODE_SUPPORT */
+
+/*
+*  qla2100_status_entry
+*      Processes received ISP status entry.
+*
+* Input:
+*      ha           = adapter block pointer.
+*      pkt          = entry pointer.
+*      done_q_first = done queue first pointer.
+*      done_q_last  = done queue last pointer.
+*/
+STATIC void
+qla2100_status_entry(scsi_qla_host_t *ha, sts_entry_t *pkt, srb_t **done_q_first,
+            srb_t **done_q_last) {
+                uint32_t       b, t, l;
+                uint8_t        sense_sz = 0;
+                srb_t          *sp, *sp2;
+                scsi_lu_t      *q;
+                Scsi_Cmnd       *cp;
+
+#ifdef QL_DEBUG_LEVEL_3
+                ENTER("qla2100_status_entry");
+#endif
+                /* Validate handle. */
+                if( pkt->handle < MAX_OUTSTANDING_COMMANDS )
+                    sp = ha->outstanding_cmds[pkt->handle];
+                else
+                    sp = 0;
+
+                if( sp ) {
+                    /* Free outstanding command slot. */
+                    ha->outstanding_cmds[pkt->handle] = 0;
+                    cp = sp->cmd;
+                    sp->ccode = pkt->comp_status;
+                    sp->scode = pkt->scsi_status;
+
+            sp->flags &= ~SRB_SENT;
+                    /* Generate LU queue on cntrl, target, LUN */
+                    b = SCSI_BUS_32(cp);
+                    t = SCSI_TCN_32(cp);
+                    l = SCSI_LUN_32(cp);
+                    q = GET_LU_Q(ha, b, t, l);
+
+                    /* Target busy */
+                    if( pkt->scsi_status & SS_BUSY_CONDITION &&
+                    (uint8_t)pkt->scsi_status != SS_RESERVE_CONFLICT ) {
+#ifdef QL_DEBUG_LEVEL_2
+                     qla2100_print("qla2100_status_entry: SCSI busy status, scsi(");
+                qla2100_output_number((u_long)ha->host_no, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)b, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)t, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)l, 10);
+                        qla2100_print(")\n");
+#endif
+                        sp->retry_count--;
+                        CMD_RESULT(cp) = (int) (DID_BUS_BUSY << 16) |
+                        (pkt->scsi_status & 0xff);
+
+                    }
+#if 0
+                    /* dg - 03/30      */
+                    else if( ha->loop_down_timer  ) {
+#endif
+                        else if( ha->loop_down_timer ||
+                        ha->loop_state != LOOP_READY ) {
+#ifdef QL_DEBUG_LEVEL_3
+                            qla2100_print("scsi(");
+                qla2100_output_number((u_long)ha->host_no, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)b, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)t, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)l, 10);
+                qla2100_print("): Loop Not ready - pid =");
+                qla2100_output_number((u_long)sp->cmd->pid, 16);
+                            qla2100_print("\n");
+#endif
+                            CMD_RESULT(cp) = (int) (DID_BUS_BUSY << 16);
+                        } else if( sp->port_down_retry_count > 1 &&
+                        (pkt->comp_status == CS_PORT_UNAVAILABLE ||
+                        pkt->comp_status == CS_PORT_LOGGED_OUT ||
+                        pkt->comp_status == CS_PORT_CONFIG_CHG ||
+                        pkt->comp_status == CS_PORT_BUSY) ) {
+                            /* if the port is unavaliable and we haven't exceeded the port down count */
+                            /* then send command back to the mid-level. */
+#ifdef QL_DEBUG_LEVEL_2
+                            qla2100_print("scsi(");
+                qla2100_output_number((u_long)ha->host_no, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)b, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)t, 10);
+                qla2100_print(":");
+                qla2100_output_number((u_long)l, 10);
+                            qla2100_print("): Port Down Retry Cnt =(");
+                qla2100_output_number((u_long)sp->port_down_retry_count, 10);
+                            qla2100_print("): , pid =");
+                qla2100_output_number((u_long)sp->cmd->pid, 16);
+                            qla2100_print(", status =");
+                qla2100_output_number((u_long)pkt->comp_status, 16);
+                            qla2100_print("\n");
+#endif
+                            sp->port_down_retry_count--;
+
+                            /* dg 08/17/99
+                            * Force the SCSI layer to keep retrying until our
+                            * port_down_retry_count expire. They will normally
+                            * try and reset the bus after half the retries
+                            * have completed, so double the count.
+                            */
+                            CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+
+                            /* Acquire target queue lock */
+                            if( !(q->q_flag & QLA2100_QSUSP) ) {
+                                q->q_flag |= QLA2100_QSUSP;  /* suspend starting new commands */
+
+                                /* Decrement port down count on all pending commands. */
+                                /* and return them back to OS.                        */
+                                for( sp2 = q->q_first; sp2; sp2 = sp2->s_next ) {
+#if 0
+                                    if( sp2->port_down_retry_count ) /* dg - v4.31.4 */
+                                        sp2->port_down_retry_count--;
+#endif
+                                    /*  v2.19.14  - unconditionally retry these 
+				     *	requests.
+				     */
+                                    CMD_RESULT(sp2->cmd) = DID_BUS_BUSY << 16;
+                                    qla2100_callback(ha,sp2, TRUE);
+                                }
+                                q->q_first = q->q_last = NULL;
+                                /* if port timer is not active then start it */
+                                if( !ha->queue_restart_timer ) {
+                                    ha->queue_restart_timer = PORT_RETRY_TIME;
+                                }
+                                if( TGT_Q(ha, b, t)->down_timer == 0 ) {
+                		    TGT_Q(ha, b, t)->down_timer = 
+                                        ha->port_down_retry_count * PORT_RETRY_TIME;
+				}
+                            }
+
+                            /* Release LU queue specific lock */
+                        } else {
+#ifdef QL_DEBUG_LEVEL_2
+                            if( pkt->comp_status ) {
+                                qla2100_print(
+                        "qla2100_status_entry: Compl error = ");
+                    qla2100_output_number((u_long)pkt->comp_status, 16);
+                                qla2100_print(", scsi(");
+                    qla2100_output_number((u_long)ha->host_no, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)b, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)t, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)l, 10);
+                                qla2100_print("), retry count= ");
+                    qla2100_output_number((u_long)sp->port_down_retry_count, 10);
+                                qla2100_print(", pid = ");
+                    qla2100_output_number((u_long)cp->pid, 16);
+                                qla2100_print("\n");
+                            }
+#endif
+                            /* Set ISP completion status and target status byte. */
+                            CMD_RESULT(cp) = qla2100_return_status(ha, pkt, cp);
+
+                            memset((caddr_t)cp->sense_buffer, 0,sizeof(cp->sense_buffer));
+                            if( pkt->scsi_status & SS_CHECK_CONDITION ) {
+                                /* Mid-level always zero sense buffer before giving it to us */
+                                if( pkt->scsi_status & SS_SENSE_LEN_VALID ) {
+                                    if( pkt->req_sense_length < CMD_SNSLEN(cp) )
+                                        sense_sz = pkt->req_sense_length;
+                                    else
+                                        sense_sz = CMD_SNSLEN(cp) - 1;
+
+                                    BCOPY((caddr_t)&pkt->req_sense_data, cp->sense_buffer, sense_sz);
+
+                                }
+
+#ifdef QL_DEBUG_LEVEL_2
+                                qla2100_print(
+                                "qla2100_status_entry: Check condition Sense data, scsi(");
+                    qla2100_output_number((u_long)ha->host_no, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)b, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)t, 10);
+                    qla2100_print(":");
+                    qla2100_output_number((u_long)l, 10);
+                                qla2100_print(")\n");
+                                if( sense_sz )
+                                    qla2100_dump_buffer(cp->sense_buffer, sense_sz);
+#endif
+                            }
+                        }
+                        /* Place command on done queue. */
+                        qla2100_done_q_put(ha, sp, done_q_first, done_q_last);
+                    } else {
+#ifdef QL_DEBUG_LEVEL_2
+                        qla2100_print("qla2100_status_entry: ISP Invalid handle\n");
+#endif
+                        printk(KERN_WARNING "!qla2100: Status Entry invalid handle");
+                        ha->flags.isp_abort_needed = TRUE;
+                    }
+#ifdef QL_DEBUG_LEVEL_3
+                    LEAVE("qla2100_status_entry");
+#endif
+}
+
+/*
+*  qla2100_error_entry
+*      Processes error entry.
+*
+* Input:
+*      ha           = adapter block pointer.
+*      pkt          = entry pointer.
+*      done_q_first = done queue first pointer.
+*      done_q_last  = done queue last pointer.
+*/
+STATIC void
+qla2100_error_entry(scsi_qla_host_t *ha, response_t *pkt, srb_t **done_q_first,
+                srb_t **done_q_last) {
+                    srb_t *sp;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    ENTER("qla2100_error_entry");
+#endif
+
+#ifdef QL_DEBUG_LEVEL_2
+                    if( pkt->entry_status & BIT_5 )
+                        qla2100_print("qla2100_error_entry: Invalid Entry Order\n");
+                    else if( pkt->entry_status & BIT_4 )
+                        qla2100_print("qla2100_error_entry: Invalid Entry Count\n");
+                    else if( pkt->entry_status & BIT_3 )
+                        qla2100_print("qla2100_error_entry: Invalid Entry Parameter\n");
+                    else if( pkt->entry_status & BIT_2 )
+                        qla2100_print("qla2100_error_entry: Invalid Entry Type\n");
+                    else if( pkt->entry_status & BIT_1 )
+                        qla2100_print("qla2100_error_entry: Busy\n");
+                    else
+                        qla2100_print("qla2100_error_entry: UNKNOWN flag error\n");
+#endif
+
+                    /* Validate handle. */
+                    if( pkt->handle < MAX_OUTSTANDING_COMMANDS )
+                        sp = ha->outstanding_cmds[pkt->handle];
+                    else
+                        sp = 0;
+
+                    if( sp ) {
+                        /* Free outstanding command slot. */
+                        ha->outstanding_cmds[pkt->handle] = 0;
+
+            sp->flags &= ~SRB_SENT;
+                        /* Bad payload or header */
+                        if( pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2) ) {
+                            /* Bad payload or header, set error status. */
+                            CMD_RESULT(sp->cmd) = (int) DID_ERROR << 16;
+
+                        } else if( pkt->entry_status & BIT_1 && sp->retry_count ) /* FULL flag */
+                        {
+                            sp->retry_count--;
+                            CMD_RESULT(sp->cmd) = (int) DID_BUS_BUSY << 16;
+                        } else {
+                            /* Set error status. */
+                            CMD_RESULT(sp->cmd) =(int)  DID_ERROR << 16;
+                        }
+                        /* Place command on done queue. */
+                        qla2100_done_q_put(ha, sp, done_q_first, done_q_last);
+                    } else if( pkt->entry_type == COMMAND_A64_TYPE ||
+                    pkt->entry_type == COMMAND_TYPE ) {
+#ifdef QL_DEBUG_LEVEL_2
+                        qla2100_print("qla2100_error_entry: ISP Invalid handle\n");
+#endif
+                        printk(KERN_WARNING "!qla2100: Error Entry invalid handle");
+                        ha->flags.isp_abort_needed = TRUE;
+                    }
+
+#ifdef QL_DEBUG_LEVEL_3
+                    LEAVE("qla2100_error_entry");
+#endif
+}
+
+/*
+*  qla2100_abort_isp
+*      Resets ISP and aborts all outstanding commands.
+*
+* Input:
+*      ha           = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_abort_isp(scsi_qla_host_t *ha) {
+                    uint16_t       cnt;
+                    srb_t          *sp;
+                    scsi_lu_t      *q;
+                    uint32_t       b, t, l;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+                    unsigned long cpu_flags = 0;
+#endif
+                    uint8_t        status = 0;
+
+                    ENTER("qla2100_abort_isp");
+
+                    DRIVER_LOCK
+                    ha->flags.isp_abort_needed = FALSE;
+                    if( !ha->flags.abort_isp_active && ha->flags.online ) {
+                        ha->flags.abort_isp_active = TRUE;
+                        ha->flags.online = FALSE;
+	                ha->dpc_flags &= ~COMMAND_WAIT_NEEDED;
+	                ha->dpc_flags &= ~COMMAND_WAIT_ACTIVE;
+                        qla2100_stats.ispAbort++;
+                        ha->isp_aborts++; 
+                        ha->sns_retry_cnt = 0;
+                        printk(KERN_INFO
+                        "qla2100: Performing ISP error recovery - ha= %p\n",
+                         (void *) ha);
+                        qla2100_reset_chip(ha);
+
+                        if( ha->loop_state != LOOP_DOWN ) {
+                            ha->loop_state = LOOP_DOWN;
+                            ha->loop_down_timer = LOOP_DOWN_TIME;
+                        }
+
+#ifdef FC_IP_SUPPORT
+                        /* Return all IP send packets */
+                        for (cnt = 0; cnt < MAX_SEND_PACKETS; cnt++) {
+                            if (ha->apActiveIpQueue[cnt] != NULL) {
+                                (*ha->pSendCompletionRoutine)(ha->apActiveIpQueue[cnt]);
+
+                                ha->apActiveIpQueue[cnt] = NULL;
+                            }
+                        }
+#endif
+
+                        /* Requeue all commands in outstanding command list. */
+                        for( cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++ ) {
+                            sp = ha->outstanding_cmds[cnt];
+                            if( sp ) {
+                                ha->outstanding_cmds[cnt] = 0;
+                                /* Generate LU queue on controller, target, LUN */
+                                b = SCSI_BUS_32(sp->cmd);
+                                t = SCSI_TCN_32(sp->cmd);
+                                l = SCSI_LUN_32(sp->cmd);
+                                if ((q = (scsi_lu_t *)GET_LU_Q(ha, b, t, l))) {
+                                    /* Reset outstanding command count. */
+                                    q->q_outcnt = 0;
+                                    q->q_flag &= ~QLA2100_QBUSY;
+                                }
+                                /* sp->flags &= ~(SRB_SENT | SRB_TIMEOUT); */
+                                sp->flags = 0;
+                                /* we need to send the command back to OS */
+                                CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                                CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                                qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+                            }
+                        }
+
+                        if( ha->device_id == QLA2100_DEVICE_ID )
+                            qla2100_nvram_config(ha);
+                        else
+                            qla2200_nvram_config(ha);
+
+						/* v2.19.12 */	
+		        		ha->retry_count = ql2xretrycount;
+                        if( !qla2100_configure_loop(ha, TRUE) ) {
+                            ha->flags.reset_marker = FALSE;
+
+                            if( !ha->loop_down_timer )
+                                qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+                            ha->flags.online = TRUE;
+
+                            /* Enable target response to SCSI bus. */
+                            if( ha->flags.enable_target_mode )
+                                qla2100_enable_lun(ha);
+
+#ifdef FC_IP_SUPPORT
+                            /* Reenable IP support */
+                            if (ha->flags.enable_ip)
+                                qla2x00_ip_initialize(ha);
+#endif
+                            /* Enable ISP interrupts. */
+                            qla2100_enable_intrs(ha);
+
+                            /* v2.19.5b6 Return all commands */
+                            qla2100_abort_queues(ha, TRUE);
+                            
+                            /* Restart queues that may have been stopped. */
+                            ha->flags.abort_isp_active = FALSE;
+                            /* 6/9 if( !ha->loop_down_timer ) */
+                                qla2100_restart_queues(ha,TRUE);
+                        } else {
+                            printk(KERN_WARNING
+                            "qla2100: ISP error recovery failed, board disabled");
+                            qla2100_reset_adapter(ha);
+                            qla2100_abort_queues(ha, FALSE);
+                        }
+                    }
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                    if( status )
+                        qla2100_print("qla2100_abort_isp: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                    else
+                        LEAVE("qla2100_abort_isp");
+#endif
+                    return(status);
+}
+/*
+*  qla2100_restart_watchdog_queue
+*      Restart device queues.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_restart_watchdog_queue(scsi_qla_host_t *ha) {
+                    srb_t  *sp, *sp_next;
+
+                    for( sp = ha->retry_q_first; (sp); sp = sp_next ) {
+                        sp_next = sp->s_next;
+                        /* when time expire return request back to OS as BUSY */
+                        qla2100_timeout_remove(ha, sp);
+                        CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                        CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                        qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+                    }
+
+}
+
+/*
+*  qla2100_restart_queues
+*      Restart device queues.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_restart_queues(scsi_qla_host_t *ha, uint8_t flush) {
+                    scsi_lu_t *q;
+                    uint32_t  b, t, l;
+                    srb_t  *sp, *sp_next;
+                    srb_t        *done_q_first = (srb_t *) NULL;
+                    srb_t        *done_q_last = (srb_t *) NULL;
+                    int cnt;
+                    unsigned long cpu_flags = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    ENTER("qla2100_restart_queues");
+#endif
+
+                    ha->flags.restart_queues_needed = FALSE;
+
+                    /*
+                    * start all queues working again.
+                    */
+                    for( b = 0; b < MAX_BUSES; b++ )
+                        for( t = 0; t < ha->max_targets; t++ ) {
+                            if( TGT_Q(ha, b, t)  == NULL )
+                                continue;
+                            for( l = 0; l < ha->max_luns; l++ ) {
+                                q = (scsi_lu_t *) GET_LU_Q(ha, b, t, l);
+                                if( q != NULL ) {
+                                    q->q_flag &= ~QLA2100_QSUSP;
+                                    if( q->q_first )
+                                        qla2100_next(ha, q);
+                                }
+                            }
+                        }
+
+                        /*
+                        * Clear out our retry queue
+                        */
+                        if( flush ) {
+                            for( sp = ha->retry_q_first; (sp); sp = sp_next ) {
+                                sp_next = sp->s_next;
+                                /* when time expire return request back to OS as BUSY */
+                                qla2100_timeout_remove(ha, sp);
+                                CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                                CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                                qla2100_done_q_put(ha, sp, (srb_t **)&done_q_first, (srb_t **)&done_q_last);
+                            }
+
+                            /* Callback everything in done queue */
+                    	    cnt = 0;
+                            while( done_q_first ) {
+                                QLA2100_TIMER_LOCK(ha);
+                                /* remove command from done list */
+                                sp = done_q_first;
+                                if( !(done_q_first = sp->s_next) )
+                                    done_q_last = NULL;
+                                else
+                                    (done_q_first)->s_prev = NULL;
+                                cnt++;
+                                qla2100_stats.done_q_cnt--;
+                                DEBUG(sp->state = 5;)
+                                QLA2100_TIMER_UNLOCK(ha);
+                                /* DEBUG(sprintf(debug_buff,
+                                  "qla2100_restart_queues: callback pid %d\n",
+                                  sp->cmd->pid);)
+                                  DEBUG(qla2100_print(debug_buff);) */
+                                qla2100_callback(ha,sp,FALSE);
+                            }
+                            DEBUG(sprintf(debug_buff,"qla2100_restart_queues: callback %d commands.\n",cnt);)
+                            DEBUG(qla2100_print(debug_buff);)
+                      }
+
+#ifdef QL_DEBUG_LEVEL_3
+                            LEAVE("qla2100_restart_queues");
+#endif
+}
+
+/*
+*  qla2100_abort_queues
+*      Abort all commands on device queues.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_abort_queues(scsi_qla_host_t *ha, uint8_t doneqflg) {
+                    scsi_lu_t   *q;
+                    uint32_t    b, t, l;
+                    srb_t       *sp, *sp_next;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    ENTER("qla2100_abort_queues");
+#endif
+                    ha->flags.abort_queue_needed = FALSE;
+
+                    for( b = 0; b < MAX_BUSES; b++ )
+                        for( t = 0; t < ha->max_targets; t++ ) {
+                            if( TGT_Q(ha, b, t) == NULL )
+                                continue;
+                            for( l = 0; l < MAX_LUNS; l++ ) {
+                                q = GET_LU_Q(ha, b, t, l);
+                                if( q != NULL ) {
+                                    /* Try to acquire LU queue specific lock */
+                                    /* if( queue is not busy )
+                                    { */
+                                    sp = q->q_first;
+                                    q->q_first = q->q_last = NULL;
+
+                                    while( sp ) {
+                                        q->q_incnt--;
+                                        sp_next = sp->s_next;
+                                        CMD_RESULT(sp->cmd) = DID_BUS_BUSY << 16;
+                                        if ( doneqflg ) {
+                                            CMD_HANDLE(sp->cmd) = (unsigned char *) NULL;
+                                            qla2100_done_q_put(ha, sp, (srb_t **)&ha->done_q_first, (srb_t **)&ha->done_q_last);
+                                        } else
+                                            qla2100_callback(ha,sp,FALSE);
+                                        sp = sp_next;
+                                    }
+                                    /* }
+                                    else
+                                    ha->flags.abort_queue_needed = TRUE;
+                                    */
+                                }
+                            }
+                        }
+
+#ifdef QL_DEBUG_LEVEL_3
+                        LEAVE("qla2100_abort_queues");
+#endif
+}
+
+/*
+*  qla2100_update_config
+*      Restart RISC in order to update the connection mode.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+uint8_t
+qla2100_update_config(scsi_qla_host_t *ha) {
+                    uint8_t   status = 0;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    qla2100_print("qla2100_update_config: entered\n");
+#endif
+                    /* Turn-off flag, so we don't get called again */
+                    ha->flags.update_config_needed = FALSE;
+
+                    /* get the new topology */
+                    qla2100_configure_hba(ha);
+
+                    ha->init_cb->additional_firmware_options.connection_options = ha->operating_mode;
+                    DEBUG(printk("qla2100_update_config: Setting new topology to %d\n" , ha->operating_mode);)
+
+                    qla2100_reset_chip(ha);
+
+                    if( ha->loop_state != LOOP_DOWN ) {
+                        ha->loop_state = LOOP_DOWN;
+                        ha->loop_down_timer = LOOP_DOWN_TIME;
+                    }
+
+                    if( !(status = qla2100_configure_loop(ha, TRUE)) ) {
+                        ha->flags.reset_marker = FALSE;
+                        if( !ha->loop_down_timer )
+                            qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+                        ha->flags.online = TRUE;
+
+                        /* Enable target response to SCSI bus. */
+                        if( ha->flags.enable_target_mode )
+                            qla2100_enable_lun(ha);
+
+                    }
+
+                    /* Enable ISP interrupts. */
+                    qla2100_enable_intrs(ha);
+                    /* WRT_REG_WORD(&reg->ictrl, ISP_EN_INT + ISP_EN_RISC); */
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                    if( status )
+                        qla2100_print("qla2100_update_config: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                    else
+                        qla2100_print("qla2100_update_config: exiting normally\n");
+#endif
+                    return(status);
+}
+
+/*
+*  qla2100_loop_resync
+*      Resync with fibre channel devices.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+STATIC uint8_t
+qla2100_loop_resync(scsi_qla_host_t *ha) {
+                    uint8_t   status;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    ENTER("qla2100_loop_resync");
+#endif
+
+                    ha->loop_state = LOOP_UPDATE;
+                    if( ha->flags.online && !ha->flags.loop_resync_active &&
+                    !ha->flags.abort_isp_active ) {
+                        ha->flags.loop_resync_active = TRUE;
+                        if( !(status = qla2100_fw_ready(ha)) ) {
+                            do {
+                                ha->flags.loop_resync_needed = FALSE;
+                                /* v2.19.05b6 */
+                                ha->loop_state = LOOP_UPDATE;
+
+                                /* Issue marker command. */
+                                qla2100_marker(ha, 0, 0, 0, MK_SYNC_ALL);
+
+                                /* Remap devices on Loop. */
+                                qla2100_update_fc_db(ha, TRUE);
+
+                            }while( !ha->loop_down_timer && ha->flags.loop_resync_needed );
+                        }
+                        ha->flags.loop_resync_active = FALSE;
+                        /* v2.19 - we don't want to call this if we are already
+                         * in the loop resync code
+                         */
+                        qla2100_restart_queues(ha,TRUE);
+                    } else
+                        status = 0;
+
+                    /* Restart queues that may have been stopped. */
+                    /* 04/10 if( !ha->loop_down_timer ) {
+                        qla2100_restart_queues(ha,TRUE);
+                    } */
+                    /* v2.19 */ 
+                    /* deleted qla2100_restart_queues(ha,TRUE); */
+
+#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
+                    if( status )
+                        qla2100_print("qla2100_loop_resync: **** FAILED ****\n");
+#endif
+#ifdef QL_DEBUG_LEVEL_3
+                    else
+                        LEAVE("qla2100_loop_resync");
+#endif
+                    return(status);
+}
+
+/*
+* qla2100_debounce_register
+*      Debounce register.
+*
+* Input:
+*      port = register address.
+*
+* Returns:
+*      register value.
+*/
+STATIC uint16_t
+qla2100_debounce_register(volatile uint16_t *addr) {
+                    volatile uint16_t ret;
+                    volatile uint16_t ret2;
+
+                    do {
+                        ret = RD_REG_WORD(addr);
+                        ret2 = RD_REG_WORD(addr);
+                    }while( ret != ret2 );
+
+                    return(ret);
+}
+                
+/* qla2100_cmd_wait
+*	Stall driver until all outstanding commands are returned.
+*
+* Input:
+*	ha = adapter state pointer.
+*
+* Return;
+*  0 -- Done
+*  1 -- continue;
+*
+* Context:
+*	Kernel context.
+*/
+STATIC uint8_t
+qla2100_cmd_wait(scsi_qla_host_t *ha) {
+	    uint16_t index;
+	    uint8_t stat = 1;
+
+	    ENTER("qla2200_cmd_wait: started\n");
+
+	    /* Wait for all outstanding commands to be returned. */
+	    for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) {
+		    if (ha->outstanding_cmds[index] == NULL)
+			    continue;
+                
+            /* if command not completed then wait for it */
+            if (ha->flags.isp_abort_needed){
+	        stat = 0;
+                break;
+            }
+                
+	    if( (ha->dpc_flags & COMMAND_WAIT_ACTIVE) &&
+		 ha->cmd_wait_cnt-- == 0 ) {
+                   ha->flags.isp_abort_needed = TRUE;
+	           DEBUG(printk("qla2200_cmd_wait: ISP abort %d\n",index);)
+	    } else {
+    	       ha->cmd_wait_cnt = 30;
+	       ha->dpc_flags |= COMMAND_WAIT_ACTIVE;
+            }
+
+	    DEBUG5( if( (ha->dpc_flags & COMMAND_WAIT_ACTIVE) ) )
+	    DEBUG5(printk("qla2200_cmd_wait: on handle %d - cnt %d\n",index,ha->cmd_wait_cnt);)
+
+            }
+
+	if (index == MAX_OUTSTANDING_COMMANDS ||
+            ha->flags.isp_abort_needed) {
+	   ha->dpc_flags &= ~COMMAND_WAIT_NEEDED;
+	   ha->dpc_flags &= ~COMMAND_WAIT_ACTIVE;
+	   stat = 0;
+        }
+        return( stat );
+}
+
+/*
+* qla2100_reset_chip
+*      Reset ISP chip.
+*
+* Input:
+*      ha = adapter block pointer.
+*/
+STATIC void
+qla2100_reset_chip(scsi_qla_host_t *ha) {
+                    uint32_t     cnt;
+                    device_reg_t *reg = ha->iobase;
+
+#ifdef QL_DEBUG_LEVEL_3
+                    ENTER("qla2100_reset_chip");
+#endif
+
+                    /* Disable ISP interrupts. */
+                    qla2100_disable_intrs(ha);
+                    /* WRT_REG_WORD(&reg->ictrl, 0); */
+
+#if 1
+                    /* Pause RISC. */
+                    WRT_REG_WORD(&reg->host_cmd, HC_PAUSE_RISC);
+                    for (cnt = 0; cnt < 30000; cnt++) {
+                        if ((RD_REG_WORD(&reg->host_cmd) & HC_RISC_PAUSE) != 0)
+                            break;
+                        else
+                            udelay(100);
+                    }
+
+                    /* Select FPM registers. */
+                    WRT_REG_WORD(&reg->ctrl_status, 0x20);
+
+                    /* FPM Soft Reset. */
+                    WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
+
+                    /* Select frame buffer registers. */
+                    WRT_REG_WORD(&reg->ctrl_status, 0x10);
+
+                    /* Reset frame buffer FIFOs. */
+                    WRT_REG_WORD(&reg->fb_cmd, 0xa000);
+
+                    /* Select RISC module registers. */
+                    WRT_REG_WORD(&reg->ctrl_status, 0);
+
+                    /* Reset RISC module. */
+                    WRT_REG_WORD(&reg->host_cmd, HC_RESET_RISC);
+
+                    /* Reset ISP semaphore. */
+                    WRT_REG_WORD(&reg->semaphore, 0);
+
+                    /* Release RISC module. */
+                    WRT_REG_WORD(&reg->host_cmd, HC_RELEASE_RISC);
+
+                    /* Wait for RISC to recover from reset. */
+                    for (cnt = 0; cnt < 30000; cnt++) {
+                        if (RD_REG_WORD(&reg->mailbox0) != MBS_BUSY)
+                            break;
+                        else
+                            udelay(100);
+                    }
+
+                    /* Disable RISC pause on FPM parity error. */
+                    WRT_REG_WORD(&reg->host_cmd, HC_DISABLE_PARITY_PAUSE);
+#else
+                    /* Insure mailbox registers are free. */
+                    WRT_REG_WORD(&reg->semaphore, 0);
+                    WRT_REG_WORD(&reg->host_cmd, HC_CLR_RISC_INT);
+                    WRT_REG_WORD(&reg->host_cmd, HC_CLR_HOST_INT);
+
+                    /* clear mailbox busy */
+                    ha->flags.mbox_busy = FALSE;
+
+                    /* Reset ISP chip. */
+                    WRT_REG_WORD(&reg->ctrl_status, ISP_RESET);
+
+                    /*
+                    * Delay after reset, for chip to recover.
+                    * Otherwise causes system PANIC
+                    */
+                    mdelay(2);
+
+                    for( cnt = 30000; cnt; cnt-- ) {
+                        if( !(RD_REG_WORD(&reg->ctrl_status) & ISP_RESET) )
+                            break;
+                        udelay(100);
+                    }
+
+                    /* Reset RISC processor. */
+                    WRT_REG_WORD(&reg->host_cmd, HC_RESET_RISC);
+                    WRT_REG_WORD(&reg->host_cmd, HC_RELEASE_RISC);
+                    for( cnt = 30000; cnt; cnt-- ) {
+                        if( RD_REG_WORD(&reg->mailbox0) != MBS_BUSY )
+                            break;
+                        udelay(100);
+                    }
+#endif
+
+#ifdef QL_DEBUG_LEVEL_3
+                    LEAVE("qla2100_reset_chip");
+#endif
+}
+                
+                
+#ifdef RCSN
+/*
+* qla2100_device_resync
+*	Marks devices in the database that needs resynchronization.
+*
+* Input:
+*	ha = adapter block pointer.
+*
+* Context:
+*	Kernel context.
+*/
+STATIC void
+qla2100_device_resync(scsi_qla_host_t *ha) {
+                    uint16_t index;
+                    uint32_t mask;
+                    rscn_t dev;
+                    port_id_t p;
+
+                    ENTERT("qla2100_device_resync:");
+                    while (ha->rscn_out_ptr != ha->rscn_in_ptr ||
+                    ha->device_flags & RSCN_QUEUE_OVERFLOW) {
+                        INTR_LOCK(ha);
+                        BCOPY(&ha->rscn_queue[ha->rscn_out_ptr],
+                          &dev,	sizeof (rscn_t));
+ 
+                        ha->rscn_out_ptr++;
+                        if (ha->rscn_out_ptr == MAX_RSCN_COUNT)
+                            ha->rscn_out_ptr = 0;
+
+                        /* Queue overflow, set switch default case. */
+                        if (ha->device_flags & RSCN_QUEUE_OVERFLOW) {
+                            dev.format = 3;
+                            ha->device_flags = ha->device_flags & ~RSCN_QUEUE_OVERFLOW;
+                        }
+
+                        switch (dev.format) {
+                            case 0:
+                                mask = 0xffffff;
+                                break;
+                            case 1:
+                                mask = 0xffff00;
+                                break;
+                            case 2:
+                                mask = 0xff0000;
+                                break;
+                            default:
+                                mask = 0x0;
+                                dev.d_id.b24 = 0;
+                                ha->rscn_out_ptr = ha->rscn_in_ptr;
+                                break;
+                        }
+                        INTR_UNLOCK(ha);
+
+                        for (index = 0; index < MAX_FIBRE_DEVICES; index++) {
+                            p.b.b24 = dev.d_id.b24;
+                            if (ha->fc_db[index].flags & DEV_PUBLIC &&
+                            ha->fc_db[index].port_id[2] == p.r.port_id[2] &&
+                            ha->fc_db[index].port_id[1] == p.r.port_id[1] &&
+                            ha->fc_db[index].port_id[0] == p.r.port_id[0]  )
+                                if (ha->fc_db[index].loop_id <= SNS_LAST_LOOP_ID)
+                                    printk(KERN_INFO "qla2100_device_resync: %d:%d:%d\n",
+                                    ha->fc_db[index].port_id[2] ,
+                                    ha->fc_db[index].port_id[1] ,
+                                    ha->fc_db[index].port_id[0] )
+                                    ha->fc_db[index].flags |= DEV_MISSING;
+                        }
+                    }
+                }
+
+                LEAVE("qla2100_device_resync: exiting normally");
+}
+#endif /* RCSN */
+
+#ifdef   GET_PORT_INFO
+
+/*
+* qla2100_get_port_database
+*	Issue enhanced get port database mailbox command
+*	and copy device name as necessary.
+*
+* Input:
+*	ha = adapter state pointer.
+*	dev = structure pointer.
+*	opt = mailbox 1 option byte.
+*
+* Returns:
+*	qla2100 local function return status code.
+*
+* Context:
+*	Kernel context.
+*/
+STATIC int
+qla2100_get_port_database(scsi_qla_host_t *ha, fcdev_t *dev, uint8_t opt) {
+                int rval = 0;
+                port_database_t *pd;
+                u_long      phys_address = 0;
+                uint16_t    mb[MAILBOX_REGISTER_COUNT];
+
+                ENTER("qla2200_get_port_database:");
+/* 4.10 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                pd = KMALLOC(PORT_DATABASE_SIZE);
+                if ( pd != NULL ) {
+                     phys_address = VIRT_TO_BUS(pd);
+                     BZERO((caddr_t)pd, PORT_DATABASE_SIZE);
+                }
+#else
+                pd  = pci_alloc_consistent(ha->pdev,
+                                           PORT_DATABASE_SIZE,
+                                           &phys_address);
+                BZERO((caddr_t)pd, PORT_DATABASE_SIZE);
+#endif
+                if( pd  == NULL ) {
+                    return 2;
+                }
+                BZERO((caddr_t)pd, PORT_DATABASE_SIZE);
+
+                mb[0] = MBC_GET_PORT_DATABASE;
+                mb[1] = dev->loop_id << 8 | opt;
+                mb[2] = MSW(phys_address);
+                mb[3] = LSW(phys_address);
+                mb[6] = 0;
+                mb[7] = 0;
+                if( !qla2100_mailbox_command(ha,
+                BIT_7|BIT_6|BIT_3|BIT_2|BIT_1|BIT_0,
+                &mb[0]) ) {
+                    /* Get d_id of device. */
+                    /*
+                    dev->d_id.b.al_pa = pd->port_id[2];
+                    dev->d_id.b.area = pd->port_id[3];
+                    dev->d_id.b.domain = pd->port_id[0];
+                    dev->d_id.b.rsvd_1 = 0;
+                    */
+
+                    /* Get initiator status of device. */
+                    pd->prli_svc_param_word_3[0] & BIT_5 ?
+                    (dev->flags = dev->flags | DEV_INITIATOR) :
+                    (dev->flags = dev->flags & ~DEV_INITIATOR);
+                } else {
+                    printk(KERN_WARNING "qla2200_get_port_database: [ERROR] failed");
+                    rval = 1;
+                }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+                KMFREE(pd, PORT_DATABASE_SIZE);
+#else
+                pci_free_consistent(ha->pdev, PORT_DATABASE_SIZE,
+                                    pd, phys_address);
+#endif
+                LEAVE("qla2200_get_port_database:");
+
+                return (rval);
+}
+#endif
+
+/*
+*  qla2100_configure_loop
+*      Resync with fibre channel devices.
+*
+* Input:
+*      ha = adapter block pointer.
+*
+* Returns:
+*      0 = success
+*/
+
+STATIC uint8_t qla2100_configure_loop(scsi_qla_host_t *ha, uint8_t reuse) {
+                uint8_t status = 0;
+
+                /* If firmware needs to be loaded */
+                if( qla2100_isp_firmware(ha) ) {
+                    ha->flags.online = FALSE;
+                    if( !(status = qla2100_chip_diag(ha)) )
+                        status = qla2100_setup_chip(ha);
+                }
+
+                if( !status && !(status = qla2100_init_rings(ha)) ) {
+                    if( !qla2100_fw_ready(ha) ) {
+                        ha->flags.reset_marker = FALSE;
+                        do {
+                            ha->flags.loop_resync_needed = FALSE;
+                            /* remap devices on loop */
+                            qla2100_update_fc_db(ha, reuse);
+                        }while( !ha->loop_down_timer && ha->flags.loop_resync_needed );
+                    }
+                }
+                return(status);
+}
+
+/*
+ * This routine will wait for fabric devices for
+ * the reset delay.
+ */ 
+void qla2100_check_fabric_devices(scsi_qla_host_t *ha) {
+               uint16_t mb[MAILBOX_REGISTER_COUNT];
+
+               mb[0] = MBC_GET_FIRMWARE_STATE;
+               qla2100_mailbox_command(ha, BIT_0, &mb[0]);
+}
+
+#if QLA2100_EXT_TIMEOUT
+/*
+* qla2100_extend_timeout
+*      This routine will extend the timeout to the specified value.
+*
+* Input:
+*      cmd = SCSI command structure
+*
+* Returns:
+*      None.
+*/
+static void qla2100_extend_timeout(Scsi_Cmnd *cmd, int timeout) {
+                del_timer(&cmd->eh_timeout);
+                cmd->eh_timeout.expires = jiffies + timeout;
+                add_timer(&cmd->eh_timeout);
+}
+#endif
+/*
+* qla2100_display_fc_names
+*      This routine will the node names of the different devices found
+*      after port inquiry.
+*
+* Input:
+*      cmd = SCSI command structure
+*
+* Returns:
+*      None.
+*/
+STATIC void qla2100_display_fc_names(scsi_qla_host_t *ha) {
+	uint16_t	index;
+
+	/* Display the node name for adapter */
+	printk(KERN_INFO
+	    "scsi-qla%d-adapter-node=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+	    (int)ha->instance,
+	    ha->init_cb->node_name[0],
+	    ha->init_cb->node_name[1],
+	    ha->init_cb->node_name[2],
+	    ha->init_cb->node_name[3],
+	    ha->init_cb->node_name[4],
+	    ha->init_cb->node_name[5],
+	    ha->init_cb->node_name[6],
+	    ha->init_cb->node_name[7]);
+
+	/* display the port name for adapter */
+	printk(KERN_INFO
+	    "scsi-qla%d-adapter-port=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+	    (int)ha->instance,
+	    ha->init_cb->port_name[0],
+	    ha->init_cb->port_name[1],
+	    ha->init_cb->port_name[2],
+	    ha->init_cb->port_name[3],
+	    ha->init_cb->port_name[4],
+	    ha->init_cb->port_name[5],
+	    ha->init_cb->port_name[6],
+	    ha->init_cb->port_name[7]);
+
+	/* Print out device port names */
+	for (index = 0; index < MAX_FIBRE_DEVICES; index++) {
+		if (ha->fc_db[index].loop_id == PORT_UNUSED ||
+		    ha->fc_db[index].loop_id == PORT_AVAILABLE )
+			continue;
+
+#if USE_PORTNAME
+		printk(KERN_INFO
+		    "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+		    (int)ha->instance, index,
+		    ha->fc_db[index].wwn[0],
+		    ha->fc_db[index].wwn[1],
+		    ha->fc_db[index].wwn[2],
+		    ha->fc_db[index].wwn[3],
+		    ha->fc_db[index].wwn[4],
+		    ha->fc_db[index].wwn[5],
+		    ha->fc_db[index].wwn[6],
+		    ha->fc_db[index].wwn[7]);
+#else
+		printk(KERN_INFO
+		    "scsi-qla%d-target-%d=%02x%02x%02x%02x%02x%02x%02x%02x;\n",
+		    (int)ha->instance, index,
+		    ha->fc_db[index].name[0],
+		    ha->fc_db[index].name[1],
+		    ha->fc_db[index].name[2],
+		    ha->fc_db[index].name[3],
+		    ha->fc_db[index].name[4],
+		    ha->fc_db[index].name[5],
+		    ha->fc_db[index].name[6],
+		    ha->fc_db[index].name[7]);
+#endif
+	}
+}
+
+/*
+* qla2100_find_propname
+*	Get property in database.
+*
+* Input:
+*	ha = adapter structure pointer.
+*      db = pointer to database
+*      propstr = pointer to dest array for string
+*	propname = name of property to search for.
+*
+* Returns:
+*	0 = no property
+*  value = index of property value.
+*
+* Context:
+*	Kernel context.
+*/
+STATIC uint8_t
+qla2100_find_propname(scsi_qla_host_t *ha,
+            char *propname, char *propstr, char *db) {
+                char	*np, *cp;
+                int   i,k,l;
+
+                /* find the specified string */
+                for( l=0, cp = db; (*cp) && l < strlen(db) ; cp = np, l++ ) {
+                    np = qla2100_get_line(cp, propstr);
+                    DEBUG5(printk("qla2100_find_propname: %d - Searching for {%s} in cmd substr: {%s}, next line: {%s} \n",l,propname,propstr, np);)
+                    /* find the property name */
+                    k = strlen(propname);
+                    for ( i = 0; (propstr[i]) && i < strlen(db); i++ ) {
+                        if( BCMP(propname,&propstr[i],k) == 0) {
+                            DEBUG5(printk("qla2100_find_propname: found at index = %d\n",i+k );)
+                            return (i+k);   /* match */
+                        }
+                    }
+                }
+                return (0);
+}
+
+
+
+/*
+* qla2100_get_prop_16chars
+*	Get an 8-byte property value for the specified property name by
+*      converting from the property string found in the configuration file.
+*      The resulting converted value is in big endian format (MSB at byte0).
+*
+* Input:
+*	ha = adapter state pointer.
+*	propname = property name pointer.
+*	propval  = pointer to location for the converted property val.
+*       db = pointer to database
+*
+* Returns:
+*	0 = value returned successfully.
+*
+* Context:
+*	Kernel context.
+*/
+static int
+qla2100_get_prop_16chars(scsi_qla_host_t *ha,  char *propname,
+    char *propval, char *db) {
+	char		*propstr;
+	int		i, k;
+	int		rval;
+	uint8_t		nval;
+	uint8_t		*pchar;
+	uint8_t		*ret_byte;
+	uint8_t		*tmp_byte;
+	uint8_t		*retval = (uint8_t*)propval;
+	uint8_t		tmpval[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+	uint16_t	max_byte_cnt = 8; /* 16 chars = 8 bytes */
+	uint16_t	max_strlen = 16;
+	char		buf[LINESIZE];
+
+	rval = qla2100_find_propname(ha, propname, buf, db);
+	if ( rval >= LINESIZE )
+		rval = 0;
+	    
+	propstr = &buf[rval];
+	if ( *propstr == '=' )
+		propstr++;   /* ignore equal sign */
+
+	if (rval == 0 ) {
+		return (1);
+	}
+
+	if (strlen(propstr) != max_strlen) {
+		printk(KERN_INFO
+		    "qla2x00: Failed to find prop for %s - rval=%d, "
+		    "strlen(propstr)=%d->(16), val=%s.\n",
+		    propname, rval, (int)strlen(propstr),propstr);
+		return (1);
+	}
+
+	/* Convert string to numbers. */
+
+	pchar = (uint8_t *)propstr;
+	tmp_byte = (uint8_t *)tmpval;
+
+	rval = 0;
+	for (i = 0; i < max_strlen; i++) {
+		/*
+		* Check for invalid character, two at a time,
+		* then convert them starting with first byte.
+		*/
+
+		if ((pchar[i] >= '0') && (pchar[i] <= '9')) {
+			nval = pchar[i] - '0';
+		} else if ((pchar[i] >= 'A') && (pchar[i] <= 'F')) {
+			nval = pchar[i] - 'A' + 10;
+		} else if ((pchar[i] >= 'a') && (pchar[i] <= 'f')) {
+			nval = pchar[i] - 'a' + 10;
+		} else {
+			/* invalid character */
+			rval = 1;
+			break;
+		}
+
+		if (i & BIT_0) {
+			*tmp_byte = *tmp_byte | nval;
+			tmp_byte++;
+		} else {
+			*tmp_byte = *tmp_byte | nval << 4;
+		}
+	}
+
+	if (rval != 0) {
+		/* Encountered invalid character. */
+		return (rval);
+	}
+
+	/* Copy over the converted value. */
+
+	ret_byte = retval;
+	tmp_byte = tmpval;
+
+	i = max_byte_cnt;
+	k = 0;
+	while (i--) {
+		*ret_byte++ = *tmp_byte++;
+	}
+
+	/* big endian retval[0]; */
+	return (0);
+}
+
+/*
+* qla2100_get_properties
+*	Find all properties for the specified adapeter in
+*      command line.
+*
+* Input:
+*	ha = adapter block pointer.
+*	cmdline = pointer to command line string
+*
+* Context:
+*	Kernel context.
+*/
+static void
+qla2100_get_properties(scsi_qla_host_t *ha, char *cmdline) {
+	char		propbuf[LINESIZE];
+	int		tmp_rval;
+	uint16_t	tgt;
+	uint8_t		tmp_name[8];
+
+	/* Adapter FC node names. */
+	sprintf(propbuf, "scsi-qla%d-adapter-node", (int) ha->instance);
+	qla2100_get_prop_16chars (ha, propbuf,
+	    (caddr_t)(&ha->init_cb->node_name), cmdline);
+	    
+	sprintf(propbuf, "scsi-qla%d-adapter-port", (int) ha->instance);
+	
+	/* DG 04/07 check portname of adapter */
+	qla2100_get_prop_16chars (ha, propbuf,
+	    (caddr_t)(tmp_name), cmdline);
+	if (BCMP(&ha->init_cb->port_name[0], &tmp_name[0], 8) != 0) {
+		/*
+		 * Adapter port name is WWN, and cannot be changed.
+		 * Inform users of the mismatch, then just continue driver
+		 * loading using the original adapter port name in NVRAM.
+		 */
+		printk(KERN_WARNING
+		    "qla2x00: qla%ld found mismatch in adapter port names.\n",
+		    ha->instance);
+		printk(KERN_INFO
+		    "       qla%ld port name found in NVRAM -> %02x%02x%02x%02x%02x%02x%02x%02x\n",
+		    ha->instance,
+		    ha->init_cb->port_name[0],
+		    ha->init_cb->port_name[1],
+		    ha->init_cb->port_name[2],
+		    ha->init_cb->port_name[3],
+		    ha->init_cb->port_name[4],
+		    ha->init_cb->port_name[5],
+		    ha->init_cb->port_name[6],
+		    ha->init_cb->port_name[7]);
+		printk(KERN_INFO
+		    "      qla%ld port name found on command line -> %02x%02x%02x%02x%02x%02x%02x%02x\n",
+		    ha->instance,
+		    tmp_name[0],
+		    tmp_name[1],
+		    tmp_name[2],
+		    tmp_name[3],
+		    tmp_name[4],
+		    tmp_name[5],
+		    tmp_name[6],
+		    tmp_name[7]);
+		printk(KERN_INFO
+		    "      Using port name from NVRAM.\n");
+	}
+
+	/* FC name for devices */
+	for (tgt = 0; tgt < MAX_FIBRE_DEVICES; tgt++) { 
+		sprintf(propbuf, "scsi-qla%d-target-%d",
+		    (int) ha->instance, tgt);
+
+		tmp_rval = qla2100_get_prop_16chars (ha, propbuf,
+		    tmp_name, cmdline);
+		if ( tmp_rval == 0 ) {
+			/* Got a name for this ID. */
+
+			/* Save to appropriate fields. */
+#if  USE_PORTNAME  /* updated for ioctl merge */
+			BCOPY(tmp_name, ha->fc_db[tgt].wwn, 8);
+#else
+			BCOPY(tmp_name, ha->fc_db[tgt].name, 8);
+#endif
+			ha->fc_db[tgt].loop_id = PORT_AVAILABLE;
+			ha->fc_db[tgt].flag = 0;  /* v2.19.05b3 */
+			ha->fc_db[tgt].flag |= DEV_CONFIGURED;
+			DEBUG(printk("Target %d - configured by user: ",tgt);)
+			DEBUG(printk("scsi-target=\"%08x%08x\"\n",
+			    tmp_name[1],
+			    tmp_name[0]);)/*ioctl support change*/
+		}
+	}
+
+}
+
+/*
+* Declarations for load module
+*/
+
+/* 2.19.15 */
+#ifndef FC_IP_SUPPORT
+/************************************************************************/
+/* qla2x00_reserve_loopid                                               */
+/*    This routine reserves an unused public loop ID.                   */
+/*                                                                      */
+/* Arguments:                                                           */
+/*    ha - adapter block pointer                                        */
+/*    pLoopID   - pointer to word for returning loop ID                 */
+/*                                                                      */
+/* Return Value:                                                        */
+/*    QL_STATUS_SUCCESS         if no error                             */
+/*    QL_STATUS_RESOURCE_ERROR  if out of loop IDs                      */
+/************************************************************************/
+
+static int qla2x00_reserve_loopid(scsi_qla_host_t *ha, uint16_t *pLoopId)
+{
+    int     i;
+
+    /* Look for unused loop ID */
+    for (i = ha->min_external_loopid; i < ha->max_public_loop_ids; i++)
+    {
+        if (!ha->fabricid[i].in_use)
+        {
+            /* Found free loop ID */
+            ha->fabricid[i].in_use = TRUE;
+            *pLoopId = i;
+
+            DEBUG(sprintf(debug_buff, "qla2x00_reserve_loopid: assigned loop ID %x\n\r", *pLoopId));
+            DEBUG(qla2100_print(debug_buff));
+            return QL_STATUS_SUCCESS;
+        }
+    }
+
+    /* Out of loop IDs */
+    *pLoopId = ha->max_public_loop_ids + 1;     /* Set out of range */
+    DEBUG(qla2100_print("qla2x00_reserve_loopid: out of loop IDs\n\r"));
+    return QL_STATUS_RESOURCE_ERROR;
+} /* qla2x00_reserve_loopid */
+
+
+/************************************************************************/
+/* qla2x00_free_loopid                                                  */
+/*    This routine frees a public loop ID.                              */
+/*                                                                      */
+/* Arguments:                                                           */
+/*    ha - adapter block pointer                                        */
+/*    wLoopID   - loop ID to free                                       */
+/*                                                                      */
+/* Return Value:                                                        */
+/*    none                                                              */
+/************************************************************************/
+
+static void qla2x00_free_loopid(scsi_qla_host_t *ha, uint16_t wLoopId)
+{
+    if (wLoopId < ha->max_public_loop_ids)
+    {
+        ha->fabricid[wLoopId].in_use = FALSE;
+        DEBUG(sprintf(debug_buff, "qla2x00_free_loopid: free loop ID %x\n\r", wLoopId));
+        DEBUG(qla2100_print(debug_buff));
+    }
+    else
+    {
+        DEBUG(sprintf(debug_buff, "qla2x00_free_loopid: loop ID %x out of range\n\r", wLoopId));
+        DEBUG(qla2100_print(debug_buff));
+    }
+} /* qla2x00_free_loopid */
+
+			
+/************************************************************************/
+/* qla2x00_login_public_device                                          */
+/*    This routine issues mailbox command to login fabric port.         */
+/*                                                                      */
+/* Arguments:                                                           */
+/*    ha - adapter block pointer                                        */
+/*    wLoopID   - public loop ID for device                             */
+/*    pPortID   - pointer to port ID for fabric login                   */
+/*    wOptions  - MBC_NO_PLOGI_IF_LOGGED_IN (bit 0)                     */
+/*                MBC_NO_PROCESS_LOGIN (bit 1)                          */
+/*                                                                      */
+/* Return Value:                                                        */
+/*    QL_STATUS_SUCCESS         if no error                             */
+/*    QL_STATUS_ERROR           if any other error                      */
+/*    QL_STATUS_RESOURCE_ERROR  if out of loop IDs                      */
+/*    QL_STATUS_FATAL_ERROR     if fatal error                          */
+/************************************************************************/
+
+static int qla2x00_login_public_device(scsi_qla_host_t *ha,
+                                       uint16_t *pLoopId,
+                                       uint8_t  *pPortID,
+                                       uint16_t wOptions)
+{
+    int         status = QL_STATUS_SUCCESS;
+    int         wRetryCount;
+    uint16_t    mb[MAILBOX_REGISTER_COUNT];
+
+    /* Set retry count */
+    wRetryCount = 2;
+
+    while (wRetryCount--)
+    {
+        DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: login loop ID: %x  port ID: %x, option: %x\n\r",
+        *pLoopId, *pPortID << 16 | *(pPortID+1) << 8 | *(pPortID+2), wOptions ));
+        DEBUG(qla2100_print(debug_buff));
+
+        /* Issue fabric login request */
+        mb[0] = MBC_LOGIN_FABRIC_PORT;
+        mb[1] = (uint16_t)(*pLoopId << 8 | (wOptions & 0x00FF));
+        mb[2] = (uint16_t)(*pPortID);
+        mb[3] = (uint16_t)(*(pPortID+1) << 8 | *(pPortID+2));
+        if (qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0, &mb[0]) == 0)
+        {
+            /* Login successful */
+            status = QL_STATUS_SUCCESS;
+            break;
+        }
+
+        /* Login failed, check status */
+        if (mb[0] == MBS_FATAL_ERROR)
+        {
+            DEBUG(qla2100_print("qla2x00_login_public_device: LOGIN_FABRIC_PORT fatal error\n\r"));
+            status = QL_STATUS_FATAL_ERROR;
+            break;
+        }
+        else if (mb[0] == MBS_LOOP_ID_IN_USE)
+        {
+            DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: loop ID %x in use by port ID %x (4008)\n\r",
+                     *pLoopId, mb[1] << 16 | mb[2]));
+            DEBUG(qla2100_print(debug_buff));
+
+            /* Allocate another loop ID and retry */
+            if ((status = qla2x00_reserve_loopid(ha, pLoopId)) == QL_STATUS_SUCCESS)
+            {
+                wRetryCount++;
+            }
+            else
+            {
+                break;
+            }
+        }
+        else if (mb[0] == MBS_PORT_ID_IN_USE)
+        {
+            DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: port ID already assigned to loop ID %x (4007)\n\r",
+                     mb[1]));
+            DEBUG(qla2100_print(debug_buff));
+
+            /* Free loop ID and use one assigned by RISC */
+            qla2x00_free_loopid(ha, *pLoopId);
+            *pLoopId = mb[1];
+
+            /* Must reissue login mailbox command with new loop ID */
+            wRetryCount++;
+        }
+        else
+        {
+            DEBUG(sprintf(debug_buff, "qla2x00_login_public_device: login error status %x, MB1: %x, MB2: %x\n\r",
+                     mb[0], mb[1], mb[2]));
+            DEBUG(qla2100_print(debug_buff));
+            status = QL_STATUS_ERROR;
+        }
+    }
+    return(status);
+} /* qla2x00_login_public_device */
+
+
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
+#ifdef MODULE
+Scsi_Host_Template driver_template = QLA2100_LINUX_TEMPLATE;
+#include "scsi_module.c"
+#endif
+#else   /* new kernel scsi initialization scheme */
+static  Scsi_Host_Template driver_template = QLA2100_LINUX_TEMPLATE;
+#include "scsi_module.c"
+#endif
+
+#ifdef QL_DEBUG_ROUTINES
+/****************************************************************************/
+/*                         Driver Debug Functions.                          */
+/****************************************************************************/
+
+            /*
+            *  Get byte from I/O port
+            */
+STATIC uint8_t
+qla2100_getbyte(uint8_t *port) {
+                uint8_t ret;
+
+#ifdef MEMORY_MAPPED_IO
+                ret = *port;
+#else
+                ret = inb((int)port);
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_getbyte: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)ret, 16);
+                    qla2100_print("\n");
+                }
+
+                return(ret);
+}
+
+            /*
+            *  Get word from I/O port
+            */
+STATIC uint16_t
+qla2100_getword(uint16_t *port) {
+                uint16_t ret;
+
+#ifdef MEMORY_MAPPED_IO
+                ret = *port;
+#else
+                ret = inw((int)port);
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_getword: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)ret, 16);
+                    qla2100_print("\n");
+                }
+
+                return(ret);
+}
+
+            /*
+            *  Get double word from I/O port
+            */
+STATIC uint32_t
+qla2100_getdword(uint32_t *port) {
+                uint32_t ret;
+
+#ifdef MEMORY_MAPPED_IO
+                ret = *port;
+#else
+                ret = inl((int)port);
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_getdword: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)ret, 16);
+                    qla2100_print("\n");
+                }
+
+                return(ret);
+}
+
+            /*
+            *  Send byte to I/O port
+            */
+STATIC void
+qla2100_putbyte(uint8_t *port, uint8_t data) {
+#ifdef MEMORY_MAPPED_IO
+                *port = data;
+#else
+                outb(data, (int)port);
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_putbyte: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)data, 16);
+                    qla2100_print("\n");
+                }
+}
+
+            /*
+            *  Send word to I/O port
+            */
+STATIC void
+qla2100_putword(uint16_t *port, uint16_t data) {
+#ifdef MEMORY_MAPPED_IO
+                *port = data;
+#else
+#ifdef _LINUX_IOPORTS
+                outw(data, (int)port);
+#else
+                outw((int)port, data);
+#endif
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_putword: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)data, 16);
+                    qla2100_print("\n");
+                }
+}
+
+            /*
+            *  Send double word to I/O port
+            */
+STATIC void
+qla2100_putdword(uint32_t *port, uint32_t data) {
+#ifdef MEMORY_MAPPED_IO
+                *port = data;
+#else
+#ifdef _LINUX_IOPORTS
+                outl(data,(int)port);
+#else
+                outl((int)port, data);
+#endif
+#endif
+
+                if( ql2x_debug_print ) {
+                    qla2100_print("qla2100_putdword: address = ");
+            qla2100_output_number((u_long)port, 16);
+            qla2100_print(" data = 0x");
+            qla2100_output_number((u_long)data, 16);
+                    qla2100_print("\n");
+                }
+}
+
+            /*
+            * Dummy function to prevent warnings for
+            * declared and unused debug functions
+            */
+void
+qla2100_debug(void) {
+                qla2100_getbyte(0);
+                qla2100_getword(0);
+                qla2100_getdword(0);
+                qla2100_putbyte(0, 0);
+                qla2100_putword(0, 0);
+                qla2100_putdword(0, 0);
+}
+
+            /*
+            *  Out character to COM1 port.
+            *      PORT must be at standard address for COM1 = 0x3F8
+            *      This port is available on both Lion and ia32 systems
+            */
+#define OUTB(addr,data)   outb((data),(addr))
+STATIC void
+qla2100_putc(int8_t c) {
+#ifdef QL_DEBUG_CONSOLE
+
+                printk("%c",c);
+
+#else /* QL_DEBUG_CONSOLE */
+
+                uint8_t data;
+                int     com_addr              = 0x3f8; /* COM1 */
+                int     hardware_flow_control = 1;
+                int     software_flow_control = 0;
+                uint8_t loop                  = TRUE;
+
+                do {
+
+                    /* Wait for transmitter holding and shift registers for empty. */
+                    do {
+                        data = inb(com_addr+5);
+                    }while( !(data & BIT_6) );
+
+                    /*
+                    * Set BAUD rate for COM1 to 9600
+                    */
+
+                    /* BAUD rate divisor LSB. */
+                    OUTB(com_addr+3, 0x83);
+
+                    /* BAUD rate divisor MSB. */
+                    OUTB(com_addr, 0xc);           /* 0xC = 9600 baud */
+
+                    /* Set No parity, 8 bits, 1 stop bit and
+                    select interrupt enable register. */
+                    OUTB(com_addr+3, 3);
+
+                    /* Disable interrupts. */
+                    OUTB(com_addr+1, 0);
+
+                    /* Set data terminal ready and request to send */
+                    OUTB(com_addr+1, 0);
+
+                    if( hardware_flow_control ) {
+                        /* Wait for clear-to-send and data-set-ready */
+                        do {
+                            data = inb(com_addr+6) & (BIT_5 + BIT_4);
+                        }while( data != (BIT_5 + BIT_4) );
+                    } else if( software_flow_control ) {
+                        /* Test for data ready. */
+                        data = inb(com_addr+5);
+                        if( data & BIT_0 ) {
+                            /* If XOFF */
+                            data = inb(com_addr);
+                            if( data == '\023' ) {
+                                /* Wait for XON */
+                                do {
+                                    /* Wait for int8_t */
+                                    do {
+                                        data = inb(com_addr+5);
+                                    }while( !(data & BIT_0) );
+                                    data = inb(com_addr);
+                                }while( data != '\021' );
+                            }
+                        }
+                    }
+
+                    /* Output character. */
+                    OUTB(com_addr, c);
+
+                    /* Add return. */
+                    if( c == '\n' )
+                        c = '\r';
+                    else
+                        loop = FALSE;
+
+                }while( loop );
+#endif  /* QL_DEBUG_CONSOLE */
+}
+
+            /*
+            *  Out NULL terminated string to COM port.
+            */
+STATIC void
+qla2100_print(int8_t *s) {
+                if( ql2x_debug_print ) {
+#ifdef QL_DEBUG_CONSOLE
+                    printk("%s",s);
+#else
+                    /* Output string. */
+                    while( *s )
+                        qla2100_putc(*s++);
+#endif
+                }
+}
+
+            /*
+            *  Output long number to COM port.
+            */
+STATIC void
+        qla2100_output_number(u_long n, uint8_t base) {
+                int8_t str[12];
+                int8_t *s      = &str[11];
+                uint8_t output = 0;
+                uint8_t hex    = FALSE;
+
+                if( ql2x_debug_print ) {
+                    if( base == 10 || base == 16 ) {
+                        if( base == 16 && n > 9 )
+                            hex = TRUE;
+
+                        *s = 0;
+                        do {
+                            s--;
+                            *s = n % base;
+                            if( *s > 9 )
+                                *s += 55;
+                            else
+                                *s += '0';
+                            n /= base;
+                        }while( n );
+
+                        for( ; *s; s++ ) {
+                            if( *s != '0' )
+                                output = 1;
+                            if( output )
+                                qla2100_putc(*s);
+                        }
+                        if( !output )
+                            qla2100_putc(*--s);
+
+                        if( hex )
+                            qla2100_putc('h');
+                    }
+                }
+}
+
+STATIC void
+qla2100_dump_buffer(uint8_t *b, uint32_t size) {
+                uint32_t cnt;
+                uint8_t c;
+
+                if( ql2x_debug_print ) {
+                    qla2100_print(
+                    " 0   1   2   3   4   5   6   7   8   9   Ah  Bh  Ch  Dh  Eh  Fh\n");
+                    qla2100_print(
+                    "---------------------------------------------------------------\n");
+
+                    for( cnt = 0; cnt < size; ) {
+                        c = *b++;
+                        if( c < 16 )
+                            qla2100_putc(' ');
+                        qla2100_output_number((uint32_t)c, 16);
+                        cnt++;
+                        if( !(cnt % 16) )
+                            qla2100_print("\n");
+                        else if( c < 10 )
+                            qla2100_print("  ");
+                        else
+                            qla2100_putc(' ');
+                    }
+                    if( cnt % 16 )
+                        qla2100_print("\n");
+                }
+}
+            /**************************************************************************
+            *   ql2100_print_scsi_cmd
+            *
+            **************************************************************************/
+void qla2100_print_scsi_cmd(Scsi_Cmnd *cmd) {
+                scsi_qla_host_t *ha;
+                struct Scsi_Host  *host = cmd->host;
+                srb_t           *sp;
+
+                int i;
+                ha = (scsi_qla_host_t *) host->hostdata;
+
+                ql2x_debug_print = 1;
+                sp = (srb_t *) CMD_SP(cmd);
+                sprintf(debug_buff,"SCSI Command=0x%p, Handle=0x%08lx pid=%x\n\r", cmd, (u_long)CMD_HANDLE(cmd),cmd->pid);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"  chan=%d, target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n\r",
+                cmd->channel, cmd->target, cmd->lun, cmd->cmd_len);
+                qla2100_print(debug_buff);
+                qla2100_print(" CDB = ");
+                for( i = 0; i < cmd->cmd_len; i++ ) {
+                    sprintf(debug_buff,"0x%02x ", cmd->cmnd[i]);
+                    qla2100_print(debug_buff);
+                }
+
+                sprintf(debug_buff,"\n\r  seg_cnt =%d, retries=%d, serial_number_at_timeout=0x%lx\n\r",cmd->use_sg,cmd->retries,cmd->serial_number_at_timeout);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"  request buffer=0x%p, request buffer len=0x%x\n\r",cmd->request_buffer,cmd->request_bufflen);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"  tag=%d, flags=0x%x, transfersize=0x%x \n\r",
+                cmd->tag, cmd->flags,cmd->transfersize);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"  Pid=%d, SP=0x%x\n\r", (int)cmd->pid, CMD_SP(cmd));
+
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"  sp flags=0x%lx, sp state=%x, wdgtime=%d\n\r",sp->flags,sp->state,sp->wdg_time);
+                qla2100_print(debug_buff);
+}
+
+
+void qla2100_print_q_info(scsi_lu_t *q) {
+                sprintf(debug_buff,"Queue info: queue in =%d, queue out= %d, flags=0x%lx\n\r", q->q_incnt, q->q_outcnt, q->q_flag);
+                qla2100_print(debug_buff);
+}
+#endif
+
+
+
+
+            /**************************************************************************
+            *   ql2100_dump_regs
+            *
+            **************************************************************************/
+static void qla2100_dump_regs(struct Scsi_Host *host) {
+                printk("Mailbox registers:\n");
+                printk("qla2100 : mbox 0 0x%04x \n", inw(host->io_port + 0x10));
+                printk("qla2100 : mbox 1 0x%04x \n", inw(host->io_port + 0x12));
+                printk("qla2100 : mbox 2 0x%04x \n", inw(host->io_port + 0x14));
+                printk("qla2100 : mbox 3 0x%04x \n", inw(host->io_port + 0x16));
+                printk("qla2100 : mbox 4 0x%04x \n", inw(host->io_port + 0x18));
+                printk("qla2100 : mbox 5 0x%04x \n", inw(host->io_port + 0x1a));
+#ifdef TRACECODE
+                sprintf(debug_buff,"qla2100 : mbox 0 0x%04x \n\r", inw(host->io_port + 0x10));
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"qla2100 : mbox 1 0x%04x \n\r", inw(host->io_port + 0x12));
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"qla2100 : mbox 2 0x%04x \n\r", inw(host->io_port + 0x14));
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"qla2100 : mbox 3 0x%04x \n\r", inw(host->io_port + 0x16));
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"qla2100 : mbox 4 0x%04x \n\r", inw(host->io_port + 0x18));
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"qla2100 : mbox 5 0x%04x \n\r", inw(host->io_port + 0x1a));
+                qla2100_print(debug_buff);
+#endif
+}
+
+
+#if  STOP_ON_ERROR
+            /**************************************************************************
+            *   ql2100_panic
+            *
+            **************************************************************************/
+static void qla2100_panic(char *cp, struct Scsi_Host *host) {
+                scsi_qla_host_t *ha;
+                long  *fp;
+
+                ha = (scsi_qla_host_t *) host->hostdata;
+                DEBUG2(ql2x_debug_print = 1;)
+                sprintf(debug_buff,"qla2100 - PANIC:  %s\n",cp);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Current time=0x%lx\n", jiffies);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Number of pending commands =0x%lx\n", ha->actthreads);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Number of queued commands =0x%lx\n", ha->qthreads);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Number of free entries = (%d)\n",ha->req_q_cnt);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Request Queue @ 0x%lx, Response Queue @ 0x%lx\n",
+                ha->request_dma,
+                ha->response_dma);
+                qla2100_print(debug_buff);
+                sprintf(debug_buff,"Request In Ptr %d\n", ha->req_ring_index);
+                qla2100_print(debug_buff);
+                fp = (long *) &ha->flags;
+                sprintf(debug_buff,"HA flags =0x%lx\n", *fp);
+                qla2100_print(debug_buff);
+                ql2100_dump_requests(ha);
+                qla2100_dump_regs(host);
+                cli();
+                for( ;; ) {
+                    QLA2100_DELAY(2); barrier();
+                }
+                sti();
+}
+#endif
+#if 0
+    static void qla2100_set_flags(int flag) {
+
+        switch( flag ) {
+        case 0x1:
+            qla2100_verbose = 1L;
+
+        }
+
+    }
+#endif
+            /**************************************************************************
+            *   ql2100_dump_requests
+            *
+            **************************************************************************/
+void
+ql2100_dump_requests(scsi_qla_host_t *ha) {
+
+                Scsi_Cmnd       *cp;
+                srb_t           *sp;
+                int i;
+#ifdef QL_DEBUG_ROUTINES
+                qla2100_print("Outstanding Commands on controller:\n\r");
+#else
+                printk(KERN_INFO "Outstanding Commands on controller:\n");
+#endif
+                for( i=0; i < MAX_OUTSTANDING_COMMANDS; i++ ) {
+                    if( (sp = ha->outstanding_cmds[i]) == NULL )
+                        continue;
+                    if( (cp = sp->cmd) == NULL )
+                        continue;
+                    sprintf(debug_buff,"(%d): Pid=%ld, sp flags=0x%x, cmd=0x%p\n\r", i, (int)sp->cmd->pid, (long)sp->flags,CMD_SP(sp->cmd));
+
+#ifdef QL_DEBUG_ROUTINES
+                    qla2100_print(debug_buff);
+#else
+                    printk(KERN_INFO "%s",debug_buff);
+#endif
+                }
+
+}
+            
+
+            /**************************************************************************
+            *   qla2100_setup
+            *
+            *   Handle Linux boot parameters. This routine allows for assigning a value
+            *   to a parameter with a ';' between the parameter and the value.
+            *   ie. qla2x00=arg0;arg1;...;argN;<properties .... properties>  OR
+            *   via the command line.
+            *   ie. qla2x00 ql2xopts=arg0;arg1;...;argN;<properties .... properties>
+            **************************************************************************/
+void qla2100_setup(char *s, int *dummy) {
+                char *cp, *np;
+                char	*slots[MAXARGS];
+                char	**argv = &slots[0];
+                char	buf[LINESIZE];
+                int	argc, opts;
+
+                /*
+                * Determine if we have any properties.
+                */
+                cp = s;
+                opts = 1;
+                while( *cp && (np = qla2100_get_line(cp, buf)) != NULL ) {
+                    if( BCMP("scsi-qla",buf,8) == 0 ) {
+                        DEBUG(printk("qla2100: devconf=%s\n",cp);)
+                        ql2xdevconf = cp;
+                        (opts > 0)? opts-- : 0;
+                        break;
+                    }
+                    opts++;
+                    cp = np;
+                }
+                /*
+                * Parse the args before the properties
+                */
+                if( opts ) {
+                    opts = (opts > MAXARGS-1)? MAXARGS-1: opts;
+                    argc = qla2100_get_tokens(s, argv, opts);
+                    while (argc > 0 ) {
+                        cp = *argv;
+                        DEBUG(printk("scsi: found cmd arg =[%s]\n", cp);)
+                        if( strcmp(cp, "verbose") == 0 ) {
+                            DEBUG(printk("qla2100: verbose\n");)
+                            qla2100_verbose++;
+                        } else if (strcmp(cp, "quiet") == 0) {
+                            qla2100_quiet = 1;
+                        } else if( strcmp(cp, "reinit_on_loopdown") == 0 ) {
+                            qla2100_reinit++;
+                            DEBUG(printk("qla2100: reinit_on_loopdown\n");)
+                        }
+                        argc--, argv++;
+                    }
+                }
+
+}
+
+            /********************** qla2100_get_line *********************
+            * qla2100_get_line
+            * Copy a substring from the specified string. The substring
+            * consists of any number of chars seperated by white spaces (i.e. spaces)
+            * and ending with a newline '\n' or a semicolon ';'.
+            *
+            * Enter:
+            * str - orig string
+            * line - substring
+            *
+            * Returns:
+            *   cp - pointer to next string
+            *     or
+            *   null - End of string
+            *************************************************************/
+static char	*qla2100_get_line(char *str, char *line) {
+                register	char 	*cp = str;
+                register	char 	*sp = line;
+
+                /* skip preceeding spaces */
+                while( *cp && *cp == ' ' )
+                    ++cp;
+                while ( (*cp) && *cp != '\n' && *cp != ';' )   /* end of line */
+                    *sp++ = *cp++;
+
+                *sp = '\0';
+                DEBUG5(printk("qla2100_get_line: %s\n",line);)
+                if( (*cp) ) {
+                    cp++;
+                    return( cp );
+                }
+                return( NULL );
+}
+
+
+            /**************************** get_tokens *********************
+            * Parse command line into argv1, argv2, ... argvX
+            * Arguments are seperated by white spaces and colons and end
+            * with a NULL.
+            *************************************************************/
+static int	qla2100_get_tokens(char *line, char **argv, int maxargs ) {
+                register	char 	*cp = line;
+                int	count = 0;
+
+                while( *cp && count < maxargs ) {
+                    /* skip preceeding spaces */
+                    while((*cp) && *cp == ' ')
+                        ++cp;
+                    /* symbol starts here */
+                    argv[count++] = cp;
+                    /* skip symbols */
+                    while ( (*cp) && !( *cp == ' ' || *cp == ';' || *cp == ':' ) )
+                        cp++;
+                    /* replace comma or space with a null */
+                    if( (*cp) && (*cp ==' ' ) && argv[count-1] != cp )
+                        *cp++ = '\0';
+                }
+                return( count );
+}
+
+#ifdef FC_IP_SUPPORT
+            /* Include routines for supporting IP */
+#include "qla2100ip.c"
+#endif /* FC_IP_SUPPORT */
+
+#if  APIDEV
+/****************************************************************************/
+/* Create character driver "HbaApiDev" w dynamically allocated major number */
+/* and create "/proc/scsi/qla2x00/HbaApiNode" as the device node associated */
+/* with the major number.                                                   */
+/****************************************************************************/
+
+#define APIDEV_NODE  "HbaApiNode"
+#define APIDEV_NAME  "HbaApiDev"
+
+static int apidev_major = 0;
+static struct Scsi_Host *apidev_host = 0;
+
+static int apidev_open(struct inode *inode, struct file *file)
+{
+    printk (KERN_INFO "qla2100_apidev: open MAJOR number = %d, MINOR number = %d\n", MAJOR (inode->i_rdev), MINOR (inode->i_rdev));
+    return 0;
+}
+static int apidev_close(struct inode *inode, struct file *file)
+{
+    printk (KERN_INFO "qla2100_apidev: closed\n");
+    return 0;
+}
+
+static int apidev_ioctl(struct inode *inode, struct file *fp, unsigned int cmd, unsigned long arg)
+{
+    Scsi_Device fake_scsi_device;
+    fake_scsi_device.host = apidev_host;
+    return(qla2100_ioctl(&fake_scsi_device, (int)cmd, (void*)arg));
+}
+
+static struct file_operations apidev_fops = {
+    ioctl:    apidev_ioctl,
+    open:     apidev_open,
+    release:  apidev_close
+};
+
+static int apidev_init(struct Scsi_Host *host)
+{
+    if(apidev_host) return 0;
+    if (0 > (apidev_major = register_chrdev(0, APIDEV_NAME, &apidev_fops)))
+    {
+        DEBUG(printk("qla2100_apidev: register_chrdev rc=%d\n",apidev_major);)
+        return apidev_major;
+    }
+    apidev_host = host;
+    DEBUG(printk("qla2x00: Created /proc/scsi/qla2x00/%s major=%d\n",APIDEV_NODE,apidev_major);)
+    proc_mknod(APIDEV_NODE, 0777+S_IFCHR,host->hostt->proc_dir,(kdev_t)MKDEV(apidev_major,0));
+    return 0;
+}
+
+static int apidev_cleanup()
+{
+    if(!apidev_host) return 0;
+    unregister_chrdev(apidev_major,APIDEV_NAME);
+    remove_proc_entry(APIDEV_NODE,apidev_host->hostt->proc_dir);
+    apidev_host = 0;
+    return 0;
+}
+#endif /* APIDEV */
+
+#ifdef QL_DEBUG_ROUTINES
+#if  DEBUG_GET_FW_DUMP
+#include  "x2300dbg.c"
+#endif
+#endif
+
+
+/*
+* Overrides for Emacs so that we almost follow Linus's tabbing style.
+* Emacs will notice this stuff at the end of the file and automatically
+* adjust the settings for this buffer only.  This must remain at the end
+* of the file.
+* ---------------------------------------------------------------------------
+* Local variables:
+* c-indent-level: 2
+* c-brace-imaginary-offset: 0
+* c-brace-offset: -2
+* c-argdecl-indent: 2
+* c-label-offset: -2
+* c-continued-statement-offset: 2
+* c-continued-brace-offset: 0
+* indent-tabs-mode: nil
+* tab-width: 8
+* End:
+*/
diff -urN linux-2.4.16/drivers/scsi/qla2x00.h lia64-2.4/drivers/scsi/qla2x00.h
--- linux-2.4.16/drivers/scsi/qla2x00.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qla2x00.h	Mon Jul 23 14:12:30 2001
@@ -0,0 +1,2492 @@
+/********************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic ISP2x00 device driver for Linux 2.2.x and 2.4.x 
+* Copyright (C) 2000 and 2001         Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+**
+******************************************************************************/
+
+#ifndef _IO_HBA_QLA2100_H          /* wrapper symbol for kernel use */
+#define _IO_HBA_QLA2100_H          /* subject to change without notice */
+
+#ifndef LINUX_VERSION_CODE 
+#include <linux/version.h>
+#endif  /* LINUX_VERSION_CODE not defined */
+
+#ifndef  HOSTS_C
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef ISP2200 
+#define ISP2200
+#endif
+
+ 
+/*
+ * Driver debug definitions.
+ */
+/* #define QL_DEBUG_LEVEL_1 */      /* Output register accesses to COM1 */
+/* #define QL_DEBUG_LEVEL_2 */       /* Output error msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_3 */      /* Output function trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_4 */      /* Output NVRAM trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_5 */      /* Output ring trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_6 */      /* Output WATCHDOG timer trace to COM1 */
+/* #define QL_DEBUG_LEVEL_7 */      /* Output RISC load trace msgs to COM1 */
+/* #define QL_DEBUG_LEVEL_8 */      /* Output ring saturation msgs to COM1 */
+
+#define QL_DEBUG_CONSOLE        /* Output to console instead of COM1 */
+  /* comment this #define to get output of qla2100_print to COM1         */
+  /* if COM1 is not connected to a host system, the driver hangs system! */
+
+/*
+ * Data bit definitions.
+ */
+#define BIT_0   0x1
+#define BIT_1   0x2
+#define BIT_2   0x4
+#define BIT_3   0x8
+#define BIT_4   0x10
+#define BIT_5   0x20
+#define BIT_6   0x40
+#define BIT_7   0x80
+#define BIT_8   0x100
+#define BIT_9   0x200
+#define BIT_10  0x400
+#define BIT_11  0x800
+#define BIT_12  0x1000
+#define BIT_13  0x2000
+#define BIT_14  0x4000
+#define BIT_15  0x8000
+#define BIT_16  0x10000
+#define BIT_17  0x20000
+#define BIT_18  0x40000
+#define BIT_19  0x80000
+#define BIT_20  0x100000
+#define BIT_21  0x200000
+#define BIT_22  0x400000
+#define BIT_23  0x800000
+#define BIT_24  0x1000000
+#define BIT_25  0x2000000
+#define BIT_26  0x4000000
+#define BIT_27  0x8000000
+#define BIT_28  0x10000000
+#define BIT_29  0x20000000
+#define BIT_30  0x40000000
+#define BIT_31  0x80000000
+
+/*
+ * Common size type definitions
+ */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)
+typedef unsigned char  uint8_t; 
+typedef unsigned short uint16_t; 
+typedef unsigned long  uint32_t; 
+typedef char  int8_t; 
+typedef short int16_t; 
+typedef long  int32_t; 
+#endif
+
+/*
+ *  Local Macro Definitions.
+ */
+#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \
+    defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \
+    defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \
+    defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8)
+    #define QL_DEBUG_ROUTINES
+#endif
+
+#ifndef TRUE
+    #define TRUE  1
+#endif
+
+#ifndef FALSE
+    #define FALSE 0
+#endif
+#ifndef KERNEL_VERSION
+#  define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
+#endif
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,92)
+#  if defined(__sparc_v9__) || defined(__powerpc__)
+#    error "PPC and Sparc platforms are only support under 2.1.92 and above"
+#  endif
+#endif
+
+
+/* 
+ * Locking
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
+#  if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,18)
+#    include <asm/spinlock.h>
+#  else
+#    include <linux/spinlock.h>
+#  endif
+#  include <linux/smp.h>
+#  define cpuid smp_processor_id()
+#  if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+#    define DRIVER_LOCK_INIT \
+       spin_lock_init(&ha->spin_lock);
+#    define DRIVER_LOCK \
+       if(!ha->cpu_lock_count[cpuid]) { \
+         spin_lock_irqsave(&ha->spin_lock, cpu_flags); \
+         ha->cpu_lock_count[cpuid]++; \
+       } else { \
+         ha->cpu_lock_count[cpuid]++; \
+       }
+#    define DRIVER_UNLOCK \
+       if(--ha->cpu_lock_count[cpuid] == 0) \
+         spin_unlock_irqrestore(&ha->spin_lock, cpu_flags);
+#  else
+#    define DRIVER_LOCK_INIT
+#    define DRIVER_LOCK
+#    define DRIVER_UNLOCK
+#  endif 
+#else
+#  define cpuid 0
+#  define DRIVER_LOCK_INIT
+#  define DRIVER_LOCK \
+       save_flags(cpu_flags); \
+       cli();
+#  define DRIVER_UNLOCK \
+       restore_flags(cpu_flags);
+#  define le32_to_cpu(x) (x)
+#  define cpu_to_le32(x) (x)
+#endif
+
+
+/*
+ * I/O register
+*/
+/* #define MEMORY_MAPPED_IO  */           /* Enable memory mapped I/O */
+#undef MEMORY_MAPPED_IO            /* Disable memory mapped I/O */
+#define LINUX_IOPORTS              /* Linux in/out routines are define*/
+                                   /* differently from other OSs      */
+
+#ifdef QL_DEBUG_LEVEL_1
+    #define RD_REG_BYTE(addr)         qla2100_getbyte((uint8_t *)addr)
+    #define RD_REG_WORD(addr)         qla2100_getword((uint16_t *)addr)
+    #define RD_REG_DWORD(addr)        qla2100_getdword((uint32_t *)addr)
+    #define WRT_REG_BYTE(addr, data)  qla2100_putbyte((uint8_t *)addr, data)
+    #define WRT_REG_WORD(addr, data)  qla2100_putword((uint16_t *)addr, data)
+    #define WRT_REG_DWORD(addr, data) qla2100_putdword((uint32_t *)addr, data)
+#else  /* QL_DEBUG_LEVEL_1 */
+#ifdef MEMORY_MAPPED_IO
+#define RD_REG_BYTE(addr)         (*((volatile uint8_t *)addr))
+#define RD_REG_WORD(addr)         (*((volatile uint16_t *)addr))
+#define RD_REG_DWORD(addr)        (*((volatile uint32_t *)addr))
+#define WRT_REG_BYTE(addr, data)  (*((volatile uint8_t *)addr) = data)
+#define WRT_REG_WORD(addr, data)  (*((volatile uint16_t *)addr) = data)
+#define WRT_REG_DWORD(addr, data) (*((volatile uint32_t *)addr) = data)
+#else   /* MEMORY_MAPPED_IO */
+#define RD_REG_BYTE(addr)         (inb((unsigned long)addr))
+#define RD_REG_WORD(addr)         (inw((unsigned long)addr))
+#define RD_REG_DWORD(addr)        (inl((unsigned long)addr))
+#define WRT_REG_BYTE(addr, data)  (outb(data,(unsigned long)addr))
+#define WRT_REG_WORD(addr, data)  (outw(data,(unsigned long)addr))
+#define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr))
+#endif  /* MEMORY_MAPPED_IO */
+#endif    /* QL_DEBUG_LEVEL_1 */
+
+#define MAX_FIBRE_DEVICES   256
+#define	MAX_RSCN_COUNT      10
+#define	MAX_HOST_COUNT      16
+
+/*
+ * Host adapter default definitions.
+ */
+#define MAX_BUSES        1         /* We only have one bus today */
+#define MAX_TARGETS_2100 255
+#define MAX_TARGETS_2200 255
+#define MAX_LUNS         255
+                                    
+/*
+ * Fibre Channel device definitions.
+ */
+#define LAST_LOCAL_LOOP_ID  0x7d
+#define SNS_FL_PORT         0x7e
+#define FABRIC_CONTROLLER   0x7f
+#define SIMPLE_NAME_SERVER  0x80
+#define SNS_FIRST_LOOP_ID   0x81
+#define LAST_SNS_LOOP_ID    0xfe
+#define MANAGEMENT_SERVER   0xfe
+#define BROADCAST           0xff
+#define SNS_ACCEPT          0x0280 /* 8002 swapped */
+#define SNS_REJECT          0x0180 /* 8001 swapped */
+
+/* Loop ID's used as database flags, must be higher than any valid Loop ID */
+#define PORT_UNUSED         0x100  /* Port never been used. */
+#define PORT_AVAILABLE      0x101  /* Device does not exist on port. */
+
+/*
+ * Timeout timer counts in seconds
+ */
+#define QLA2100_WDG_TIME_QUANTUM   1    /* In seconds */
+#define PORT_RETRY_TIME            2
+#define LOOP_DOWN_TIMEOUT          60
+#define LOOP_DOWN_TIME             240  /* 240 */
+
+/* Maximum outstanding commands in ISP queues (1-65535) */
+#define	LOOP_DOWN_RESET		(LOOP_DOWN_TIME - 30)
+
+/* Maximum outstanding commands in ISP queues (1-65535) */
+#define MAX_OUTSTANDING_COMMANDS   512*2
+
+#define REQUEST_ENTRY_CNT       256   /* # of request entries, was 512 */
+#define RESPONSE_ENTRY_CNT      256   /* # of response entries, was 16 */
+
+/*
+ * UnixWare required definitions.
+ */
+#define HBA_PREFIX qla2100
+
+/* Physical DMA memory requirements */
+#define QLA2100_MEMALIGN    4
+#define QLA2100_BOUNDARY    0x80000000  /* 2GB */
+
+/* Number of segments 1 - 65535 */
+#define SG_SEGMENTS     32             /* Cmd entry + 6 continuations */
+
+/*
+ * SCSI Request Block 
+ */
+typedef struct srb
+{
+    Scsi_Cmnd  *cmd;                 /* (4) SCSI command block */
+    struct srb  *s_next;             /* (4) Next block on LU queue */
+    struct srb  *s_prev;             /* (4) Previous block on LU queue */
+    uint8_t     flags;               /* (1) Status flags. */
+    uint8_t     dir;                 /* direction of transfer */
+    uint8_t     retry_count;            /* Retry count. */
+    uint8_t     port_down_retry_count;  /* Port down retry count. */
+    uint8_t     ccode;               /* risc completion code */
+    uint8_t     scode;               /* scsi status code */
+    uint8_t     wdg_time;            /* watchdog time in seconds */
+    uint8_t     state;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,18)
+    uint64_t         saved_dma_handle;    /* for unmap of single transfers */
+#endif
+}srb_t;
+
+/*
+ * SRB flag definitions
+ */
+#define SRB_TIMEOUT     BIT_0           /* Command timed out */
+#define SRB_SENT        BIT_1           /* Command sent to ISP */
+#define SRB_WATCHDOG    BIT_2           /* Command on watchdog list */
+#define SRB_ABORT_PENDING BIT_3     /* Command abort sent to device */
+#define SRB_ABORTED     BIT_4           /* Command aborted command already */
+#define SRB_RETRY     BIT_5           /* Command aborted command already */
+
+/*
+ * LUN - Logical Unit Queue structure
+ */
+typedef struct scsi_lu
+{
+    srb_t           *q_first;           /* First block on LU queue */
+    srb_t           *q_last;            /* Last block on LU queue */
+    u_char          q_flag;             /* LU queue state flags */
+    u_short         q_outcnt;           /* Pending jobs for this LU */
+    u_long          q_incnt;            /* queued jobs for this LU */
+    u_long          io_cnt;             /* total xfer count */
+    u_long          resp_time;          /* total response time (start - finish) */
+    u_long          act_time;           /* total actived time (minus queuing time) */
+    u_long          w_cnt;              /* total writes */
+    u_long          r_cnt;              /* total reads */
+#if QLA2X00_TARGET_MODE_SUPPORT
+    void            (*q_func)();        /* Target driver event handler */
+    long            q_param;            /* Target driver event param */
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
+    spinlock_t      *q_spin_lock;       /* Device Queue Lock */
+#endif
+    volatile unsigned char cpu_lock_count[NR_CPUS];
+    u_long          q_timeout;           /* total command timeouts */
+}scsi_lu_t;
+
+/*
+ * Logical Unit q_flag definitions
+ */
+#define QLA2100_QBUSY   BIT_0
+#define QLA2100_QWAIT   BIT_1
+#define QLA2100_QSUSP   BIT_2
+#define QLA2100_QRESET  BIT_4
+#define QLA2100_QHBA    BIT_5
+#define QLA2100_BSUSP   BIT_6           /* controller is suspended */
+#define QLA2100_BREM    BIT_7           /* controller is removed */
+
+/*
+ *  ISP PCI Configuration Register Set
+ */
+typedef volatile struct
+{
+    uint16_t vendor_id;                 /* 0x0 */
+    uint16_t device_id;                 /* 0x2 */
+    uint16_t command;                   /* 0x4 */
+    uint16_t status;                    /* 0x6 */
+    uint8_t revision_id;                /* 0x8 */
+    uint8_t programming_interface;      /* 0x9 */
+    uint8_t sub_class;                  /* 0xa */
+    uint8_t base_class;                 /* 0xb */
+    uint8_t cache_line;                 /* 0xc */
+    uint8_t latency_timer;              /* 0xd */
+    uint8_t header_type;                /* 0xe */
+    uint8_t bist;                       /* 0xf */
+    uint32_t base_port;                 /* 0x10 */
+    uint32_t mem_base_addr;             /* 0x14 */
+    uint32_t base_addr[4];              /* 0x18-0x24 */
+    uint32_t reserved_1[2];             /* 0x28-0x2c */
+    uint16_t expansion_rom;             /* 0x30 */
+    uint32_t reserved_2[2];             /* 0x34-0x38 */
+    uint8_t interrupt_line;             /* 0x3c */
+    uint8_t interrupt_pin;              /* 0x3d */
+    uint8_t min_grant;                  /* 0x3e */
+    uint8_t max_latency;                /* 0x3f */
+}config_reg_t;
+
+
+/*
+ *  2100/2200 ISP I/O Register Set structure definitions.
+ */
+typedef volatile struct
+{
+    uint16_t flash_address;             /* Flash BIOS address */
+    uint16_t flash_data;                /* Flash BIOS data */
+    uint16_t unused_1[1];               /* Gap */
+    uint16_t ctrl_status;               /* Control/Status */
+        #define ISP_FLASH_ENABLE BIT_1  /* Flash BIOS Read/Write enable */
+        #define ISP_RESET       BIT_0   /* ISP soft reset */
+    uint16_t ictrl;                     /* Interrupt control */
+        #define ISP_EN_INT      BIT_15  /* ISP enable interrupts. */
+        #define ISP_EN_RISC     BIT_3   /* ISP enable RISC interrupts. */
+    uint16_t istatus;                   /* Interrupt status @0xa*/
+        #define RISC_INT        BIT_3   /* RISC interrupt */
+    uint16_t semaphore;                 /* Semaphore */
+    uint16_t nvram;                     /* NVRAM register. @0xe */
+        #define NV_DESELECT     0
+        #define NV_CLOCK        BIT_0
+        #define NV_SELECT       BIT_1
+        #define NV_DATA_OUT     BIT_2
+        #define NV_DATA_IN      BIT_3
+
+  /* 2100 and 2200 */
+    uint16_t mailbox0;                  /* Mailbox 0 @0x10 */
+    uint16_t mailbox1;                  /* Mailbox 1 */
+    uint16_t mailbox2;                  /* Mailbox 2 */
+    uint16_t mailbox3;                  /* Mailbox 3 */
+    uint16_t mailbox4;                  /* Mailbox 4 */
+    uint16_t mailbox5;                  /* Mailbox 5 */
+    uint16_t mailbox6;                  /* Mailbox 6 */
+    uint16_t mailbox7;                  /* Mailbox 7 */
+
+    uint16_t unused_2[0x3b];	/* Gap */
+    uint16_t fpm_diag_config;
+    uint16_t unused_3[0x6];		/* Gap */
+    uint16_t pcr;		/* Processor Control Register. */
+    uint16_t unused_4[0x5];		/* Gap */
+    uint16_t mctr;		/* Memory Configuration and Timing. */
+    uint16_t unused_5[0x3];		/* Gap */
+    uint16_t fb_cmd;
+    uint16_t unused_6[0x3];		/* Gap */
+    uint16_t host_cmd;                  /* Host command and control */
+
+        #define HOST_INT      BIT_7     /* host interrupt bit */
+#ifdef FC_IP_SUPPORT
+    uint16_t unused_3[0x0F];            /* Gap */
+    uint16_t mailbox8;                  /* Mailbox 8 */
+    uint16_t mailbox9;                  /* Mailbox 9 */
+    uint16_t mailbox10;                 /* Mailbox 10 */
+    uint16_t mailbox11;                 /* Mailbox 11 */
+    uint16_t mailbox12;                 /* Mailbox 12 */
+    uint16_t mailbox13;                 /* Mailbox 13 */
+    uint16_t mailbox14;                 /* Mailbox 14 */
+    uint16_t mailbox15;                 /* Mailbox 15 */
+    uint16_t mailbox16;                 /* Mailbox 16 */
+    uint16_t mailbox17;                 /* Mailbox 17 */
+    uint16_t mailbox18;                 /* Mailbox 18 */
+    uint16_t mailbox19;                 /* Mailbox 19 */
+    uint16_t mailbox20;                 /* Mailbox 20 */
+    uint16_t mailbox21;                 /* Mailbox 21 */
+    uint16_t mailbox22;                 /* Mailbox 22 */
+    uint16_t mailbox23;                 /* Mailbox 23 */
+#endif
+
+}device_reg_t;
+
+/*
+ *  2300 ISP I/O Register Set structure definitions.
+ */
+typedef volatile struct
+{
+    uint16_t flash_address;             /* Flash BIOS address */
+    uint16_t flash_data;                /* Flash BIOS data */
+    uint16_t unused_1[1];               /* Gap */
+    uint16_t ctrl_status;               /* Control/Status */
+        #define ISP_FLASH_ENABLE BIT_1  /* Flash BIOS Read/Write enable */
+        #define ISP_RESET       BIT_0   /* ISP soft reset */
+    uint16_t ictrl;                     /* Interrupt control */
+        #define ISP_EN_INT      BIT_15  /* ISP enable interrupts. */
+        #define ISP_EN_RISC     BIT_3   /* ISP enable RISC interrupts. */
+    uint16_t istatus;                   /* Interrupt status @0xa*/
+        #define RISC_2300_INT   BIT_15  /* 2300 RISC int for non-ROM cmds */
+    uint16_t semaphore;                 /* Semaphore */
+    uint16_t nvram;                     /* NVRAM register. @0xf */
+        #define NV_DESELECT     0
+        #define NV_CLOCK        BIT_0
+        #define NV_SELECT       BIT_1
+        #define NV_DATA_OUT     BIT_2
+        #define NV_DATA_IN      BIT_3
+  /* 2300 */
+  uint16_t req_q_in    /* @0x10 */;
+  uint16_t req_q_out   /* @0x12 */;
+  uint16_t rsp_q_in    /* @0x14 */;
+  uint16_t rsp_q_out   /* @0x16 */; 
+  uint32_t host_status /* @0x18 */;
+  uint16_t unused3[0x12];
+    uint16_t mailbox0;                  /* Mailbox 0 @0x40 */
+    uint16_t mailbox1;                  /* Mailbox 1 */
+    uint16_t mailbox2;                  /* Mailbox 2 */
+    uint16_t mailbox3;                  /* Mailbox 3 */
+    uint16_t mailbox4;                  /* Mailbox 4 */
+    uint16_t mailbox5;                  /* Mailbox 5 */
+    uint16_t mailbox6;                  /* Mailbox 6 */
+    uint16_t mailbox7;                  /* Mailbox 7 @0x4E */
+    uint16_t mailbox8;                  /* Mailbox 8 */
+    uint16_t mailbox9;                  /* Mailbox 9 */
+    uint16_t mailbox10;                 /* Mailbox 10 */
+    uint16_t mailbox11;                 /* Mailbox 11 */
+    uint16_t mailbox12;                 /* Mailbox 12 */
+    uint16_t mailbox13;                 /* Mailbox 13 */
+    uint16_t mailbox14;                 /* Mailbox 14 */
+    uint16_t mailbox15;                 /* Mailbox 15 */
+    uint16_t mailbox16;                 /* Mailbox 16 */
+    uint16_t mailbox17;                 /* Mailbox 17 */
+    uint16_t mailbox18;                 /* Mailbox 18 */
+    uint16_t mailbox19;                 /* Mailbox 19 */
+    uint16_t mailbox20;                 /* Mailbox 20 */
+    uint16_t mailbox21;                 /* Mailbox 21 */
+    uint16_t mailbox22;                 /* Mailbox 22 */
+    uint16_t mailbox23;                 /* Mailbox 23 */
+    uint16_t mailbox24;                  /* Mailbox 24 */
+    uint16_t mailbox25;                  /* Mailbox 25 */
+    uint16_t mailbox26;                 /* Mailbox 26 */
+    uint16_t mailbox27;                 /* Mailbox 27 */
+    uint16_t mailbox28;                 /* Mailbox 28 */
+    uint16_t mailbox29;                 /* Mailbox 29 */
+    uint16_t mailbox30;                 /* Mailbox 30 */
+    uint16_t mailbox31;                 /* Mailbox 31 @0x7E */
+    uint16_t unused4[0xb];  /* gap */
+
+    uint16_t fpm_diag_config;
+    uint16_t unused_3[0x6];		/* Gap */
+    uint16_t pcr;		/* Processor Control Register. */
+    uint16_t unused_4[0x5];		/* Gap */
+    uint16_t mctr;		/* Memory Configuration and Timing. */
+    uint16_t unused_5[0x3];		/* Gap */
+    uint16_t fb_cmd;
+    uint16_t unused_6[0x3];		/* Gap */
+    uint16_t host_cmd;                  /* Host command and control */
+
+        #define HOST_INT      BIT_7     /* host interrupt bit */
+#ifdef FC_IP_SUPPORT
+    uint16_t unused_3[0x0F];            /* Gap */
+    uint16_t mailbox8;                  /* Mailbox 8 */
+    uint16_t mailbox9;                  /* Mailbox 9 */
+    uint16_t mailbox10;                 /* Mailbox 10 */
+    uint16_t mailbox11;                 /* Mailbox 11 */
+    uint16_t mailbox12;                 /* Mailbox 12 */
+    uint16_t mailbox13;                 /* Mailbox 13 */
+    uint16_t mailbox14;                 /* Mailbox 14 */
+    uint16_t mailbox15;                 /* Mailbox 15 */
+    uint16_t mailbox16;                 /* Mailbox 16 */
+    uint16_t mailbox17;                 /* Mailbox 17 */
+    uint16_t mailbox18;                 /* Mailbox 18 */
+    uint16_t mailbox19;                 /* Mailbox 19 */
+    uint16_t mailbox20;                 /* Mailbox 20 */
+    uint16_t mailbox21;                 /* Mailbox 21 */
+    uint16_t mailbox22;                 /* Mailbox 22 */
+    uint16_t mailbox23;                 /* Mailbox 23 */
+#endif
+
+}device2300_reg_t;
+
+
+#define MAILBOX_REGISTER_COUNT  32
+
+/*
+ *  ISP product identification definitions in mailboxes after reset.
+ */
+#define PROD_ID_1           0x4953
+#define PROD_ID_2           0x0000
+#define PROD_ID_2a          0x5020
+#define PROD_ID_3           0x2020
+#define PROD_ID_4           0x1
+
+/*
+ * ISP host command and control register command definitions
+ */
+#define HC_RESET_RISC       0x1000      /* Reset RISC */
+#define HC_PAUSE_RISC       0x2000      /* Pause RISC */
+#define HC_RELEASE_RISC     0x3000      /* Release RISC from reset. */
+#define HC_SET_HOST_INT     0x5000      /* Set host interrupt */
+#define HC_CLR_HOST_INT     0x6000      /* Clear HOST interrupt */
+#define HC_CLR_RISC_INT     0x7000      /* Clear RISC interrupt */
+#define HC_RISC_PAUSE       BIT_5
+#define	HC_DISABLE_PARITY_PAUSE	0x4001	/* Disable parity error RISC pause. */
+
+#define SEMAPHORE_SET  0x1234
+
+/*
+ * ISP mailbox Self-Test status codes
+ */
+#define MBS_FRM_ALIVE       0           /* Firmware Alive. */
+#define MBS_CHKSUM_ERR      1           /* Checksum Error. */
+#define MBS_BUSY            4           /* Busy. */
+
+/*
+ * ISP mailbox command complete status codes
+ */
+#define MBS_CMD_CMP         0x4000      /* Command Complete. */
+#define MBS_INV_CMD         0x4001      /* Invalid Command. */
+#define MBS_HOST_INF_ERR    0x4002      /* Host Interface Error. */
+#define MBS_TEST_FAILED     0x4003      /* Test Failed. */
+#define MBS_CMD_ERR         0x4005      /* Command Error. */
+#define MBS_CMD_PARAM_ERR   0x4006      /* Command Parameter Error. */
+#define MBS_FATAL_ERROR     0xF000      /* Command Fatal Error. */
+
+#define MBS_FIRMWARE_ALIVE          0x0000 
+#define MBS_COMMAND_COMPLETE        0x4000 
+#define MBS_INVALID_COMMAND         0x4001 
+
+/* QLogic subroutine status definitions */
+#define QL_STATUS_SUCCESS           0
+#define QL_STATUS_ERROR             1
+#define QL_STATUS_FATAL_ERROR       2
+#define QL_STATUS_RESOURCE_ERROR    3
+#define QL_STATUS_LOOP_ID_IN_USE    4
+#define QL_STATUS_NO_DATA           5
+
+/*
+ * ISP mailbox asynchronous event status codes
+ */
+#define MBA_ASYNC_EVENT         0x8000  /* Asynchronous event. */
+#define MBA_RESET               0x8001  /* Reset Detected. */
+#define MBA_SYSTEM_ERR          0x8002  /* System Error. */
+#define MBA_REQ_TRANSFER_ERR    0x8003  /* Request Transfer Error. */
+#define MBA_RSP_TRANSFER_ERR    0x8004  /* Response Transfer Error. */
+#define MBA_WAKEUP_THRES        0x8005  /* Request Queue Wake-up. */
+#define MBA_LIP_OCCURRED        0x8010  /* Loop Initialization Procedure */
+                                        /* occurred. */
+#define MBA_LOOP_UP             0x8011  /* FC Loop UP. */
+#define MBA_LOOP_DOWN           0x8012  /* FC Loop Down. */
+#define MBA_LIP_RESET           0x8013  /* LIP reset occurred. */
+#define MBA_PORT_UPDATE         0x8014  /* Port Database update. */
+#define MBA_SCR_UPDATE          0x8015  /* State Change Registration. */
+#define MBA_SCSI_COMPLETION     0x8020  /* SCSI Command Complete. */
+#define MBA_CTIO_COMPLETION     0x8021  /* CTIO Complete. */
+#ifdef ISP2200
+#define MBA_LINK_MODE_UP        0x8030  /* FC Link Mode UP. */
+#define MBA_UPDATE_CONFIG       0x8036  /* FC Update Configuration. */
+#endif
+
+/*
+ * ISP mailbox commands
+ */
+#define MBC_LOAD_RAM              1     /* Load RAM. */
+#define MBC_EXECUTE_FIRMWARE      2     /* Execute firmware. */
+#define MBC_WRITE_RAM_WORD        4     /* Write RAM word. */
+#define MBC_READ_RAM_WORD         5     /* Read RAM word. */
+#define MBC_MAILBOX_REGISTER_TEST 6     /* Wrap incoming mailboxes */
+#define MBC_VERIFY_CHECKSUM       7     /* Verify checksum. */
+#define MBC_ABOUT_FIRMWARE        8     /* Get firmware revision. */
+#define MBC_DUMP_RAM              0xA   /* READ BACK FW */
+#define MBC_DUMP_SRAM             0xC   /* Dump SRAM    */
+#define MBC_IOCB_EXECUTE          0x12  /* Execute an IOCB command */
+#define MBC_ABORT_COMMAND         0x15  /* Abort IOCB command. */
+#define MBC_ABORT_DEVICE          0x16  /* Abort device (ID/LUN). */
+#define MBC_ABORT_TARGET          0x17  /* Abort target (ID). */
+#define MBC_TARGET_RESET          0x18  /* Target reset. */
+#define MBC_GET_ADAPTER_LOOP_ID   0x20  /* Get loop id of ISP2100. */
+#define MBC_SET_TARGET_PARAMATERS 0x38  /* Set target parameters. */
+#define MBC_DIAGNOSTIC_LOOP_BACK  0x45  /* Perform LoopBack diagnostic */
+#define MBC_INITIALIZE_FIRMWARE   0x60  /* Initialize firmware */
+#define MBC_INITIATE_LIP          0x62  /* Initiate Loop Initialization */
+                                        /* Procedure */
+#define MBC_GET_PORT_DATABASE     0x64  /* Get port database. */
+#define MBC_GET_FIRMWARE_STATE    0x69  /* Get firmware state. */
+#define MBC_GET_PORT_NAME         0x6a  /* Get port name. */
+#define MBC_LIP_RESET             0x6c  /* LIP reset. */
+#define MBC_SEND_SNS_COMMAND      0x6e  /* Send Simple Name Server command. */
+#define MBC_LOGIN_FABRIC_PORT     0x6f  /* Login fabric port. */
+#define MBC_LOGOUT_FABRIC_PORT    0x71  /* Logout fabric port. */
+#define MBC_LIP_FULL_LOGIN        0x72  /* Full login LIP. */
+#define MBC_GET_PORT_LIST         0x75  /* Get port list. */
+
+/*
+ * Firmware state codes from get firmware state mailbox command
+ */
+#define FSTATE_CONFIG_WAIT      0
+#define FSTATE_WAIT_AL_PA       1
+#define FSTATE_WAIT_LOGIN       2
+#define FSTATE_READY            3
+#define FSTATE_LOSS_OF_SYNC     4
+#define FSTATE_ERROR            5
+#define FSTATE_REINIT           6
+#define FSTATE_NON_PART         7
+
+#define FSTATE_CONFIG_CORRECT      0
+#define FSTATE_P2P_RCV_LIP         1
+#define FSTATE_P2P_CHOOSE_LOOP     2
+#define FSTATE_P2P_RCV_UNIDEN_LIP  3
+#define FSTATE_FATAL_ERROR         4
+#define FSTATE_LOOP_BACK_CONN      5
+
+/*
+ * ISP Initialization Control Block.
+ */
+typedef struct
+{
+    uint8_t  version;
+        #define ICB_VERSION 1
+    uint8_t  reserved_1;
+    struct
+    {
+        uint8_t enable_hard_loop_id          :1; /* bit 0 */
+        uint8_t enable_fairness              :1;
+        uint8_t enable_full_duplex           :1;
+        uint8_t enable_fast_posting          :1;
+        uint8_t enable_target_mode           :1;
+        uint8_t disable_initiator_mode       :1;
+        uint8_t enable_adisc                 :1;
+        uint8_t enable_lun_response          :1; /* bit 7 */
+        uint8_t enable_port_update_event     :1;
+        uint8_t disable_initial_lip          :1;
+        uint8_t enable_decending_soft_assign :1;
+        uint8_t previous_assigned_addressing :1;
+        uint8_t enable_stop_q_on_full        :1;
+        uint8_t enable_full_login_on_lip     :1;
+        uint8_t enable_name_change           :1;
+        uint8_t expanded_ifwcb               :1; /* bit 15 */
+    }firmware_options;
+    uint16_t frame_length;
+    uint16_t iocb_allocation;
+    uint16_t execution_throttle;
+    uint8_t  retry_count;
+    uint8_t  retry_delay;
+#ifdef ISP2200
+    uint8_t  port_name[8];
+#else
+    uint8_t  node_name[8];
+#endif
+    uint16_t adapter_hard_loop_id;
+    uint8_t  inquiry_data;
+    uint8_t  login_timeout;
+#ifdef ISP2200
+    uint8_t  node_name[8];
+#else
+    uint8_t  reserved_1[8];
+#endif
+    uint16_t request_q_outpointer;
+    uint16_t response_q_inpointer;
+    uint16_t request_q_length;
+    uint16_t response_q_length;
+    uint32_t request_q_address[2];
+    uint32_t response_q_address[2];
+    uint16_t lun_enables;
+    uint8_t  command_resource_count;
+    uint8_t  immediate_notify_resource_count;
+    uint16_t timeout;
+    uint16_t reserved_2;
+    struct
+    {
+        uint8_t operation_mode               :4; /* Bits 0 1 2 3 */
+        uint8_t connection_options           :3; /* Bits 4 5 6 */
+                #define LOOP      0
+                #define P2P       1
+                #define LOOP_P2P  2
+                #define P2P_LOOP  3
+        uint8_t nonpart_if_hard_addr_failed  :1; /* Bit 7 */
+        uint8_t enable_class2                :1; /* Bit 8 */
+        uint8_t enable_ack0                  :1; /* Bit 9 */
+        uint8_t unused_10                    :1; /* bit 10 */
+        uint8_t unused_11                    :1; /* bit 11 */
+        uint8_t enable_fc_tape               :1; /* bit 12 */
+        uint8_t enable_fc_confirm            :1; /* bit 13 */
+        uint8_t enable_cmd_q_target_mode     :1; /* bit 14 */
+        uint8_t unused_15                    :1; /* bit 15 */
+    }additional_firmware_options;
+    uint8_t     response_accum_timer;
+    uint8_t     interrupt_delay_timer;
+    struct
+    {
+      uint8_t enable_read_xfr_rdy            :1; /* Bit 0 */
+      uint8_t soft_id_only                   :1; /* Bit 1 */
+      uint8_t unused_2                       :1; /* Bit 2 */
+      uint8_t unused_3                       :1; /* Bit 3 */
+      uint8_t fcp_rsp_payload                :2; /* Bits 4 5 */
+              #define send_24_bytes_0          0
+              #define send_12_bytes_0          1
+              #define second_send_24_bytes_0   2
+              #define send_32_bytes_0          3 
+      uint8_t unused_6                       :1; /* Bit 6 */
+      uint8_t unused_7                       :1; /* Bit 7 */
+      uint8_t unused_8                       :1; /* Bit 8 */
+      uint8_t unused_9                       :1; /* Bit 9 */
+      uint8_t unused_10                      :1; /* Bit 10 */
+      uint8_t unused_11                      :1; /* Bit 11 */
+      uint8_t unused_12                      :1; /* Bit 12 */
+      uint8_t set_50_ohms_term_enable        :1; /* Bit 13 */
+      uint8_t data_rate                      :2; /* Bits 14 15 */
+              #define set_1_gig_rate       0
+              #define set_2_gig_rate       1
+              #define auto_negotiate       2
+    }special_options;
+    uint16_t    reserved_3[13];
+}init_cb_t;
+
+/*
+ * ISP Get/Set Target Parameters mailbox command control flags.
+ */
+
+/*
+ * NVRAM Command values.
+ */
+#define NV_START_BIT            BIT_2
+#define NV_WRITE_OP             (BIT_26+BIT_24)
+#define NV_READ_OP              (BIT_26+BIT_25)
+#define NV_ERASE_OP             (BIT_26+BIT_25+BIT_24)
+#define NV_MASK_OP              (BIT_26+BIT_25+BIT_24)
+#define NV_DELAY_COUNT          10
+
+/*
+ *  ISP2200 NVRAM structure definitions.
+ */
+typedef struct
+{
+    /*
+     * NVRAM header
+     */
+
+    uint8_t     id[4];
+    uint8_t     nvram_version;
+    uint8_t     reserved_0;
+
+    /*
+     * NVRAM RISC parameter block
+     */
+
+    uint8_t     parameter_block_version;
+    uint8_t     reserved_1;
+
+    struct
+    {
+        uint8_t enable_hard_loop_id          :1;
+        uint8_t enable_fairness              :1;
+        uint8_t enable_full_duplex           :1;
+        uint8_t enable_fast_posting          :1;
+        uint8_t enable_target_mode           :1;
+        uint8_t disable_initiator_mode       :1;
+        uint8_t enable_adisc                 :1;
+        uint8_t enable_lun_response          :1;
+        uint8_t enable_port_update_event     :1;
+        uint8_t disable_initial_lip          :1;
+        uint8_t enable_decending_soft_assign :1;
+        uint8_t previous_assigned_addressing :1;
+        uint8_t enable_stop_q_on_full        :1;
+        uint8_t enable_full_login_on_lip     :1;
+        uint8_t enable_name_change           :1;
+        uint8_t expanded_ifwcb               :1;
+    }firmware_options;
+
+    uint16_t    frame_payload_size;
+    uint16_t    max_iocb_allocation;
+    uint16_t    execution_throttle;
+    uint8_t     retry_count;
+    uint8_t     retry_delay;
+    uint8_t     port_name[8];
+    uint16_t    adapter_hard_loop_id;
+    uint8_t     inquiry_data;
+    uint8_t     login_timeout;
+
+    uint8_t     node_name[8];
+
+    /* Expanded RISC parameter block */
+    struct
+    {
+        uint8_t operation_mode               :4;
+        uint8_t connection_options           :3;
+        uint8_t nonpart_if_hard_addr_failed  :1;
+        uint8_t enable_class2                :1;
+        uint8_t enable_ack0                  :1;
+        uint8_t unused_10                    :1;
+        uint8_t unused_11                    :1;
+        uint8_t enable_fc_tape               :1;
+        uint8_t enable_fc_confirm            :1;
+        uint8_t enable_command_reference_num :1;
+    }additional_firmware_options;
+
+    uint8_t     response_accum_timer;
+    uint8_t     interrupt_delay_timer;
+    uint16_t    reserved_2[14];
+
+    /*
+     * NVRAM host parameter block
+     */
+
+    struct
+    {
+        uint8_t unused_0                :1;
+        uint8_t disable_bios            :1;
+        uint8_t disable_luns            :1;
+        uint8_t enable_selectable_boot  :1;
+        uint8_t disable_risc_code_load  :1;
+        uint8_t set_cache_line_size_1   :1;
+        uint8_t pci_parity_disable      :1;
+        uint8_t enable_extended_logging :1;
+        uint8_t enable_64bit_addressing :1;
+        uint8_t enable_lip_reset        :1;
+        uint8_t enable_lip_full_login   :1;
+        uint8_t enable_target_reset     :1;
+        uint8_t enable_database_storage :1;
+        uint8_t unused_13               :1;
+        uint8_t unused_14               :1;
+        uint8_t unused_15               :1;
+    }host_p;
+
+    uint8_t     boot_node_name[8];
+    uint8_t     boot_lun_number;
+    uint8_t     reset_delay;
+    uint8_t     port_down_retry_count;
+    uint8_t     reserved_3;
+
+   uint16_t    maximum_luns_per_target;
+
+    uint16_t    reserved_6[7];
+
+    /* Offset 100 */
+    uint16_t    reserved_7[25];
+
+    /* Offset 150 */
+    uint16_t    reserved_8[25];
+
+    /* Offset 200 */
+    uint8_t oem_id;
+
+    uint8_t oem_spare0;
+
+    uint8_t oem_string[6];
+
+    uint8_t oem_part[8];
+
+    uint8_t oem_fru[8];
+
+    uint8_t oem_ec[8];
+
+
+    /* Offset 232 */
+    struct
+    {
+        uint8_t external_gbic           :1;
+        uint8_t risc_ram_parity         :1;
+        uint8_t buffer_plus_module      :1;
+        uint8_t multi_chip_hba          :1;
+        uint8_t unused_1                :1;
+        uint8_t unused_2                :1;
+        uint8_t unused_3                :1;
+        uint8_t unused_4                :1;
+        uint8_t unused_5                :1;
+        uint8_t unused_6                :1;
+        uint8_t unused_7                :1;
+        uint8_t unused_8                :1;
+        uint8_t unused_9                :1;
+        uint8_t unused_10               :1;
+        uint8_t unused_11               :1;
+        uint8_t unused_12               :1;
+    }hba_features;
+
+    uint16_t   reserved_9;
+    uint16_t   reserved_10;
+    uint16_t   reserved_11;
+
+    uint16_t   reserved_12;
+    uint16_t   reserved_13;
+
+    /* Subsystem ID must be at offset 244 */
+    uint16_t    subsystem_vendor_id;
+
+    uint16_t    reserved_14;
+
+    /* Subsystem device ID must be at offset 248 */
+    uint16_t    subsystem_device_id;
+
+    uint16_t    reserved_15[2];
+    uint8_t     reserved_16;
+    uint8_t     checksum;
+}nvram22_t;
+
+typedef struct
+{
+    /*
+     * NVRAM header for 2100 board.
+     */
+
+    uint8_t     id[4];
+    uint8_t     nvram_version;
+    uint8_t     reserved_0;
+
+    /*
+     * NVRAM RISC parameter block
+     */
+
+    uint8_t     parameter_block_version;
+    uint8_t     reserved_1;
+
+    struct
+    {
+        uint8_t enable_hard_loop_id          :1;
+        uint8_t enable_fairness              :1;
+        uint8_t enable_full_duplex           :1;
+        uint8_t enable_fast_posting          :1;
+        uint8_t enable_target_mode           :1;
+        uint8_t disable_initiator_mode       :1;
+        uint8_t enable_adisc                 :1;
+        uint8_t enable_lun_response          :1;
+        uint8_t enable_port_update_event     :1;
+        uint8_t disable_initial_lip          :1;
+        uint8_t enable_decending_soft_assign :1;
+        uint8_t previous_assigned_addressing :1;
+        uint8_t enable_stop_q_on_full        :1;
+        uint8_t enable_full_login_on_lip     :1;
+        uint8_t enable_name_change           :1;
+        uint8_t unused_15                    :1;
+    }firmware_options;
+
+    uint16_t    frame_payload_size;
+    uint16_t    max_iocb_allocation;
+    uint16_t    execution_throttle;
+    uint8_t     retry_count;
+    uint8_t     retry_delay;
+    uint8_t     node_name[8];
+    uint16_t    adapter_hard_loop_id;
+    uint8_t     reserved_2;
+    uint8_t     login_timeout;
+    uint16_t    reserved_3[4];
+
+    /* Reserved for expanded RISC parameter block */
+    uint16_t    reserved_4[16];
+
+    /*
+     * NVRAM host parameter block
+     */
+
+    struct
+    {
+        uint8_t unused_0                :1;
+        uint8_t disable_bios            :1;
+        uint8_t disable_luns            :1;
+        uint8_t enable_selectable_boot  :1;
+        uint8_t disable_risc_code_load  :1;
+        uint8_t set_cache_line_size_1   :1;
+        uint8_t pci_parity_disable      :1;
+        uint8_t enable_extended_logging :1;
+        uint8_t enable_64bit_addressing :1;
+        uint8_t enable_lip_reset        :1;
+        uint8_t enable_lip_full_login   :1;
+        uint8_t enable_target_reset     :1;
+        uint8_t enable_database_storage :1;
+        uint8_t unused_13               :1;
+        uint8_t unused_14               :1;
+        uint8_t unused_15               :1;
+    }host_p;
+
+    uint8_t     boot_node_name[8];
+    uint8_t     boot_lun_number;
+    uint8_t     reset_delay;
+    uint8_t     port_down_retry_count;
+    uint8_t     reserved_5;
+
+    uint16_t    maximum_luns_per_target;
+
+    uint16_t    reserved_6[7];
+
+    /* Offset 100 */
+    uint16_t    reserved_7[25];
+
+    /* Offset 150 */
+    uint16_t    reserved_8[25];
+
+    /* Offset 200 */
+    uint16_t    reserved_9[22];
+
+    /* Subsystem ID must be at offset 244 */
+    uint16_t    subsystem_vendor_id;
+
+    uint16_t    reserved_10;
+
+    /* Subsystem device ID must be at offset 248 */
+    uint16_t    subsystem_device_id;
+
+    uint16_t    reserved_11[2];
+    uint8_t     reserved_12;
+    uint8_t     checksum;
+}nvram21_t;
+
+/*
+ * ISP queue - command entry structure definition.
+ */
+#define MAX_CMDSZ   16                  /* SCSI maximum CDB size. */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define COMMAND_TYPE    0x11    /* Command entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t handle;                    /* System handle. */
+    uint8_t  reserved;
+    uint8_t  target;                    /* SCSI ID */
+    uint16_t lun;                       /* SCSI LUN */
+    uint16_t control_flags;             /* Control flags. */
+#define CF_HEAD_TAG		BIT_1
+#define CF_ORDERED_TAG		BIT_2
+#define CF_SIMPLE_TAG		BIT_3
+#define CF_READ		BIT_5
+#define CF_WRITE		BIT_6
+#define CF_NO_FAST_POSTING      BIT_7
+    uint16_t reserved_1;
+    uint16_t timeout;                   /* Command timeout. */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint8_t  scsi_cdb[MAX_CMDSZ];       /* SCSI command words. */
+    uint32_t byte_count;                /* Total byte count. */
+    uint32_t dseg_0_address;            /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address;            /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+    uint32_t dseg_2_address;            /* Data segment 2 address. */
+    uint32_t dseg_2_length;             /* Data segment 2 length. */
+}cmd_entry_t;
+
+/*
+ * ISP queue - 64-Bit addressing, command entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define COMMAND_A64_TYPE 0x19   /* Command A64 entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t handle;                    /* System handle. */
+    uint8_t  reserved;
+    uint8_t  target;                    /* SCSI ID */
+    uint16_t lun;                       /* SCSI LUN */
+    uint16_t control_flags;             /* Control flags. */
+    uint16_t reserved_1;
+    uint16_t timeout;                   /* Command timeout. */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint8_t  scsi_cdb[MAX_CMDSZ];       /* SCSI command words. */
+    uint32_t byte_count;                /* Total byte count. */
+    uint32_t dseg_0_address[2];         /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address[2];         /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+}cmd_a64_entry_t, request_t;
+
+/*
+ * ISP queue - continuation entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CONTINUE_TYPE   0x02    /* Continuation entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t reserved;
+    uint32_t dseg_0_address;            /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address;            /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+    uint32_t dseg_2_address;            /* Data segment 2 address. */
+    uint32_t dseg_2_length;             /* Data segment 2 length. */
+    uint32_t dseg_3_address;            /* Data segment 3 address. */
+    uint32_t dseg_3_length;             /* Data segment 3 length. */
+    uint32_t dseg_4_address;            /* Data segment 4 address. */
+    uint32_t dseg_4_length;             /* Data segment 4 length. */
+    uint32_t dseg_5_address;            /* Data segment 5 address. */
+    uint32_t dseg_5_length;             /* Data segment 5 length. */
+    uint32_t dseg_6_address;            /* Data segment 6 address. */
+    uint32_t dseg_6_length;             /* Data segment 6 length. */
+}cont_entry_t;
+
+/*
+ * ISP queue - 64-Bit addressing, continuation entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CONTINUE_A64_TYPE 0x0A  /* Continuation A64 entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t dseg_0_address[2];         /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address[2];         /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+    uint32_t dseg_2_address[2];         /* Data segment 2 address. */
+    uint32_t dseg_2_length;             /* Data segment 2 length. */
+    uint32_t dseg_3_address[2];         /* Data segment 3 address. */
+    uint32_t dseg_3_length;             /* Data segment 3 length. */
+    uint32_t dseg_4_address[2];         /* Data segment 4 address. */
+    uint32_t dseg_4_length;             /* Data segment 4 length. */
+}cont_a64_entry_t;
+
+/*
+ * ISP queue - status entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define STATUS_TYPE     0x03    /* Status entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+        #define RF_INV_E_ORDER  BIT_5   /* Invalid entry order. */
+        #define RF_INV_E_COUNT  BIT_4   /* Invalid entry count. */
+        #define RF_INV_E_PARAM  BIT_3   /* Invalid entry parameter. */
+        #define RF_INV_E_TYPE   BIT_2   /* Invalid entry type. */
+        #define RF_BUSY         BIT_1   /* Busy */
+    uint32_t handle;                    /* System handle. */
+    uint16_t scsi_status;               /* SCSI status. */
+    uint16_t comp_status;               /* Completion status. */
+    uint16_t state_flags;               /* State flags. */
+    uint16_t status_flags;              /* Status flags. */
+    #define IOCBSTAT_SF_LOGO   0x2000	/* logo after 2 abts w/ no response (2 sec) */
+    uint16_t rsp_info_len;              /* Response Info Length. */
+    uint16_t req_sense_length;          /* Request sense data length. */
+    uint32_t residual_length;           /* Residual transfer length. */
+    uint8_t  rsp_info[8];               /* FCP response information. */
+    uint8_t  req_sense_data[32];        /* Request sense data. */
+}sts_entry_t, response_t;
+
+/*
+ * ISP queue - marker entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define MARKER_TYPE     0x04    /* Marker entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved;
+    uint8_t  target;                    /* SCSI ID */
+    uint8_t  modifier;                  /* Modifier (7-0). */
+        #define MK_SYNC_ID_LUN      0   /* Synchronize ID/LUN */
+        #define MK_SYNC_ID          1   /* Synchronize ID */
+        #define MK_SYNC_ALL         2   /* Synchronize all ID/LUN */
+        #define MK_SYNC_LIP         3   /* Synchronize all ID/LUN, */
+                                        /* clear port changed, */
+                                        /* use sequence number. */
+    uint8_t  reserved_1;
+    uint16_t sequence_number;           /* Sequence number of event */
+    uint16_t lun;                       /* SCSI LUN */
+    uint8_t  reserved_2[48];
+}mrk_entry_t;
+
+/*
+ * ISP queue - enable LUN entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define ENABLE_LUN_TYPE 0x0B    /* Enable LUN entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  reserved_1;
+    uint16_t reserved_2;
+    uint32_t reserved_3;
+    uint8_t  status;
+    uint8_t  reserved_4;
+    uint8_t  command_count;             /* Number of ATIOs allocated. */
+    uint8_t  immed_notify_count;        /* Number of Immediate Notify */
+                                        /* entries allocated. */
+    uint16_t reserved_5;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t reserved_6[20];
+}elun_entry_t;
+
+/*
+ * ISP queue - modify LUN entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define MODIFY_LUN_TYPE 0x0C    /* Modify LUN entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  reserved_1;
+    uint8_t  operators;
+    uint8_t  reserved_2;
+    uint32_t reserved_3;
+    uint8_t  status;
+    uint8_t  reserved_4;
+    uint8_t  command_count;             /* Number of ATIOs allocated. */
+    uint8_t  immed_notify_count;        /* Number of Immediate Notify */
+                                        /* entries allocated. */
+    uint16_t reserved_5;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t reserved_7[20];
+}modify_lun_entry_t;
+
+/*
+ * ISP queue - immediate notify entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define IMMED_NOTIFY_TYPE 0x0D  /* Immediate notify entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint8_t  reserved_1;
+    uint8_t  target_id;
+    uint32_t reserved_2;
+    uint16_t status;
+    uint16_t task_flags;
+    uint16_t seq_id;
+    uint16_t reserved_5[11];
+    uint16_t scsi_status;
+    uint8_t  sense_data[18];
+}notify_entry_t;
+
+/*
+ * ISP queue - notify acknowledge entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define NOTIFY_ACK_TYPE 0x0E    /* Notify acknowledge entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint8_t  reserved_1;
+    uint8_t  target_id;
+    uint16_t flags;
+    uint16_t reserved_2;
+    uint16_t status;
+    uint16_t task_flags;
+    uint16_t seq_id;
+    uint16_t reserved_3[21];
+}nack_entry_t;
+
+/*
+ * ISP queue - Accept Target I/O (ATIO) entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define ACCEPT_TGT_IO_TYPE 0x16 /* Accept target I/O entry. */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint16_t exchange_id;
+    uint16_t flags;
+    uint16_t status;
+    uint8_t  reserved_1;
+    uint8_t  task_codes;
+    uint8_t  task_flags;
+    uint8_t  execution_codes;
+    uint8_t  cdb[MAX_CMDSZ];
+    uint32_t data_length;
+    uint16_t lun;
+    uint16_t reserved_2A;
+    uint16_t scsi_status;
+    uint8_t  sense_data[18];
+}atio_entry_t;
+
+/*
+ * ISP queue - Continue Target I/O (CTIO) entry for status mode 0
+ *             structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                  /* Entry type. */
+        #define CONTINUE_TGT_IO_TYPE 0x17 /* CTIO entry */
+    uint8_t  entry_count;                 /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint16_t exchange_id;
+    uint16_t flags;
+    uint16_t status;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint32_t relative_offset;
+    uint32_t residual;
+    uint16_t reserved_1[3];
+    uint16_t scsi_status;
+    uint32_t transfer_length;
+    uint32_t dseg_0_address;            /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address;            /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+    uint32_t dseg_2_address;            /* Data segment 2 address. */
+    uint32_t dseg_2_length;             /* Data segment 2 length. */
+}ctio_entry_t;
+
+/*
+ * ISP queue - CTIO returned entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CTIO_RET_TYPE   0x17    /* CTIO return entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint16_t exchange_id;
+    uint16_t flags;
+    uint16_t status;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint32_t relative_offset;
+    uint32_t residual;
+    uint16_t reserved_1[8];
+    uint16_t scsi_status;
+    uint8_t  sense_data[18];
+}ctio_ret_entry_t;
+
+/*
+ * ISP queue - CTIO A64 entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CTIO_A64_TYPE 0x1F      /* CTIO A64 entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint16_t exchange_id;
+    uint16_t flags;
+    uint16_t status;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint32_t relative_offset;
+    uint32_t residual;
+    uint16_t reserved_1[3];
+    uint16_t scsi_status;
+    uint32_t transfer_length;
+    uint32_t dseg_0_address[2];         /* Data segment 0 address. */
+    uint32_t dseg_0_length;             /* Data segment 0 length. */
+    uint32_t dseg_1_address[2];         /* Data segment 1 address. */
+    uint32_t dseg_1_length;             /* Data segment 1 length. */
+}ctio_a64_entry_t;
+
+/*
+ * ISP queue - CTIO returned entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CTIO_A64_RET_TYPE 0x1F  /* CTIO A64 returned entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint8_t  reserved_8;
+    uint8_t  initiator_id;
+    uint16_t exchange_id;
+    uint16_t flags;
+    uint16_t status;
+    uint16_t timeout;                   /* 0 = 30 seconds, 0xFFFF = disable */
+    uint16_t dseg_count;                /* Data segment count. */
+    uint32_t relative_offset;
+    uint32_t residual;
+    uint16_t reserved_1[8];
+    uint16_t scsi_status;
+    uint8_t  sense_data[18];
+}ctio_a64_ret_entry_t;
+
+/*
+ * ISP queue - Status Contination entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define STATUS_CONT_TYPE 0x10   /* Status contination entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  reserved;
+    uint8_t  entry_status;              /* Entry Status. */
+    uint8_t  sense_data[60];
+}status_cont_entry_t;
+
+/*
+ * ISP queue - Command Set entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CMD_SET_TYPE 0x18       /* Command set entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint16_t reserved;
+    uint16_t status;
+    uint16_t control_flags;             /* Control flags. */
+    uint16_t count;
+    uint32_t iocb_0_address;
+    uint32_t iocb_1_address;
+    uint32_t iocb_2_address;
+    uint32_t iocb_3_address;
+    uint32_t iocb_4_address;
+    uint32_t iocb_5_address;
+    uint32_t iocb_6_address;
+    uint32_t iocb_7_address;
+    uint32_t iocb_8_address;
+    uint32_t iocb_9_address;
+    uint32_t iocb_10_address;
+    uint32_t iocb_11_address;
+}cmd_set_entry_t;
+
+/*
+ * ISP queue - Command Set A64 entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define CMD_SET_TYPE 0x18       /* Command set entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t sys_define_2;              /* System defined. */
+    uint16_t reserved;
+    uint16_t status;
+    uint16_t control_flags;             /* Control flags. */
+    uint16_t count;
+    uint32_t iocb_0_address[2];
+    uint32_t iocb_1_address[2];
+    uint32_t iocb_2_address[2];
+    uint32_t iocb_3_address[2];
+    uint32_t iocb_4_address[2];
+    uint32_t iocb_5_address[2];
+}cmd_set_a64_entry_t;
+
+/* 4.11
+ * ISP queue - Command Set entry structure definition.
+ */
+typedef struct
+{
+    uint8_t  entry_type;                /* Entry type. */
+        #define MS_IOCB_TYPE 0x29       /*  Management Server IOCB entry */
+    uint8_t  entry_count;               /* Entry count. */
+    uint8_t  sys_define;                /* System defined. */
+    uint8_t  entry_status;              /* Entry Status. */
+    uint32_t handle;                    /* System handle. */
+    uint8_t  reserved;
+    uint8_t  loop_id;
+    uint16_t status;
+    uint16_t control_flags;             /* Control flags. */
+    uint16_t reserved2;
+    uint16_t timeout;
+    uint16_t DSDcount;
+    uint16_t RespDSDcount;
+    uint8_t  reserved3[10];
+    uint32_t Response_bytecount;
+    uint32_t Request_bytecount;
+    uint32_t dseg_req_address[2];         /* Data segment 0 address. */
+    uint32_t dseg_req_length;             /* Data segment 0 length. */
+    uint32_t dseg_rsp_address[2];         /* Data segment 1 address. */
+    uint32_t dseg_rsp_length;             /* Data segment 1 length. */
+}cmd_ms_iocb_entry_t;
+
+
+/*
+ * ISP request and response queue entry sizes
+ */
+#define RESPONSE_ENTRY_SIZE     (sizeof(response_t))
+#define REQUEST_ENTRY_SIZE      (sizeof(request_t))
+
+/*
+ * ISP status entry - completion status definitions.
+ */
+#define CS_COMPLETE         0x0         /* No errors */
+#define CS_INCOMPLETE       0x1         /* Incomplete transfer of cmd. */
+#define CS_DMA              0x2         /* A DMA direction error. */
+#define CS_TRANSPORT        0x3         /* Transport error. */
+#define CS_RESET            0x4         /* SCSI bus reset occurred */
+#define CS_ABORTED          0x5         /* System aborted command. */
+#define CS_TIMEOUT          0x6         /* Timeout error. */
+#define CS_DATA_OVERRUN     0x7         /* Data overrun. */
+#define CS_DATA_UNDERRUN    0x15        /* Data Underrun. */
+#define CS_ABORT_MSG        0xE         /* Target rejected abort msg. */
+#define CS_DEV_RESET_MSG    0x12        /* Target rejected dev rst msg. */
+#define CS_PORT_UNAVAILABLE 0x28        /* Port unavailable (selection timeout) */
+#define CS_PORT_LOGGED_OUT  0x29        /* Port Logged Out */
+#define CS_PORT_CONFIG_CHG  0x2A        /* Port Configuration Changed */
+#define CS_PORT_BUSY        0x2B        /* Port Busy */
+#define CS_BAD_PAYLOAD      0x80        /* Driver defined */
+#define CS_UNKNOWN          0x81        /* Driver defined */
+#define CS_RETRY            0x82        /* Driver defined */
+
+/*
+ * ISP status entry - SCSI status byte bit definitions.
+ */
+#define SS_RESIDUAL_UNDER       BIT_11
+#define SS_RESIDUAL_OVER        BIT_10
+#define SS_SENSE_LEN_VALID      BIT_9
+#ifdef ISP2200
+#define SS_RESPONSE_INFO_LEN_VALID BIT_8
+#else
+#define SS_RESIDUAL_LEN_VALID   BIT_8
+#endif
+
+#define SS_RESERVE_CONFLICT     (BIT_4 | BIT_3)
+#define SS_BUSY_CONDITION       BIT_3
+#define SS_CONDITION_MET        BIT_2
+#define SS_CHECK_CONDITION      BIT_1
+
+/*
+ * ISP target entries - Flags bit definitions.
+ */
+#define OF_RESET            BIT_5       /* Reset LIP flag */
+#define OF_DATA_IN          BIT_6       /* Data in to initiator */
+                                        /*  (data from target to initiator) */
+#define OF_DATA_OUT         BIT_7       /* Data out from initiator */
+                                        /*  (data from initiator to target) */
+#define OF_NO_DATA          (BIT_7 | BIT_6)
+#define OF_INC_RC           BIT_8       /* Increment command resource count */
+#define OF_FAST_POST        BIT_9       /* Enable mailbox fast posting. */
+#define OF_SSTS             BIT_15      /* Send SCSI status */
+
+/*
+ * Target Read/Write buffer structure.
+ */
+#define TARGET_DATA_OFFSET  4
+#define TARGET_DATA_SIZE    0x2000      /* 8K */
+#define TARGET_INQ_OFFSET   (TARGET_DATA_OFFSET + TARGET_DATA_SIZE)
+#define TARGET_SENSE_SIZE   18
+#define TARGET_BUF_SIZE     36
+
+#if  QL1280_TARGET_MODE_SUPPORT
+typedef struct
+{
+    uint8_t         hdr[4];
+    uint8_t         data[TARGET_DATA_SIZE];
+}tgt_buf_t;
+#endif  /* QL1280_TARGET_MODE_SUPPORT */
+typedef struct
+{
+    uint16_t  loop_id;
+#ifdef QL_MAPPED_TARGETS
+    uint16_t  lun_offset;
+#endif
+    uint32_t  down_timer;
+    scsi_lu_t *luns[MAX_LUNS];
+}tgt_t;
+
+/*
+ * 24 bit port ID type definition.
+ */
+typedef union {
+	struct {
+		uint8_t port_id[3];
+		uint8_t rsvd_1;
+	}r;
+#if defined(_BIT_FIELDS_LTOH)
+	uint32_t	b24  : 24,
+			rsvd : 8;
+	struct {
+		uint8_t al_pa;
+		uint8_t area;
+		uint8_t domain;
+		uint8_t rsvd_1;
+	}b;
+#else
+	uint32_t	rsvd : 8,
+			b24  : 24;
+	struct {
+		uint8_t domain;
+		uint8_t area;
+		uint8_t al_pa;
+		uint8_t rsvd_1;
+	}b;
+#endif
+} port_id_t;
+
+
+typedef struct
+{
+    uint8_t  name[8];         /* big endian node name */
+    uint8_t  wwn[8];          /* big endian port name */
+    uint16_t  loop_id;
+    uint8_t   port_id[3];            /* 24-bit port ID */
+    uint8_t   rsvd_1;
+	/*
+	 * This is used to retry login for devices specified for
+	 * persistent binding or lost devices.
+	 */
+	uint8_t   port_login_retry_count;
+    uint8_t  port_timer;
+    uint16_t   flag;
+    uint32_t  mask[8];         /* LUN Mask for this Device */
+  /* flags bits defined as follows */
+#define DEV_PUBLIC          BIT_0
+#define DEV_OFFLINE         BIT_1
+#define DEV_LUNMASK_SET     BIT_2  /* some LUNs masked for this device */
+#define DEV_MP_DISABLED     BIT_3  /* device disabled for qlmultipath  */
+#define	DEV_TAPE_DEVICE		BIT_4
+#define	DEV_CONFIGURED    	BIT_5
+#define	DEV_MISSING	        BIT_6
+#define	DEV_RETURN	        BIT_7
+#define	DEV_HOST	        BIT_8
+#define	DEV_RELOGIN	        BIT_9
+#define	DEV_PORT_DOWN	        BIT_10
+}fcdev_t;
+
+
+typedef struct
+{
+    uint8_t   in_use;
+}fabricid_t;
+
+/*
+ * Flash Database structures.
+ */
+#define FLASH_DATABASE_0        0x1c000
+#define FLASH_DATABASE_1        0x18000
+#define FLASH_DATABASE_VERSION  1
+
+typedef struct
+{
+    uint32_t seq;
+    uint8_t  version;
+    uint8_t  checksum;
+    uint16_t size;
+    uint8_t  spares[8];
+}flash_hdr_t;
+
+typedef struct
+{
+    uint32_t name[2];
+    uint8_t  spares[8];
+}flash_node_t;
+
+typedef struct
+{
+    flash_hdr_t  hdr;
+    flash_node_t node[MAX_FIBRE_DEVICES];
+}flash_database_t;
+
+/*
+ * SNS structures.
+ */
+#define SNS_DATA_SIZE       608
+
+typedef struct
+{
+    uint16_t buffer_length;
+    uint16_t reserved;
+    uint32_t buffer_address[2];
+    uint16_t subcommand_length;
+    uint16_t reserved_1;
+}sns_hdr_t;
+
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            sns_hdr_t   hdr;
+            uint16_t    subcommand;
+            uint8_t     param[SNS_DATA_SIZE - sizeof(sns_hdr_t) - 2];
+        }req;
+
+        uint8_t rsp[SNS_DATA_SIZE];
+    }p;
+}sns_data_t;
+
+/*
+ * SNS request/response structures for GP_IDNN.
+ */
+typedef struct
+{
+    uint8_t    controlbyte;
+    uint8_t    port_id[3];
+    uint32_t   reserved;
+    uint8_t    nodename[8];
+}port_data_t;
+
+#ifdef ISP2200
+#define GP_IDNN_LENGTH  (256 * sizeof(port_data_t)) + 16
+#else
+#define GP_IDNN_LENGTH  (126 * sizeof(port_data_t)) + 16
+#endif
+
+typedef union
+{
+    struct
+    {
+        uint16_t buffer_length;
+        uint16_t reserved;
+        uint32_t buffer_address[2];
+        uint16_t subcommand_length;
+        uint16_t reserved_1;
+        uint16_t subcommand;
+        uint16_t length;
+        uint32_t reserved2;
+        uint32_t protocol;
+        uint8_t  param[GP_IDNN_LENGTH - 28];
+    }req;
+
+    struct
+    {
+        uint8_t revision;
+        uint8_t inid[3];
+        uint8_t fcstype;
+        uint8_t subtype;
+        uint8_t options;
+        uint8_t reserved;
+        uint16_t response;
+        uint16_t residual;
+        uint8_t reserved1;
+        uint8_t reason_code;
+        uint8_t explanation_code;
+        uint8_t vendor_unique;
+#ifdef ISP2200
+        port_data_t  port_data[256];
+#else
+        port_data_t  port_data[126];
+#endif
+    }rsp;
+
+}gp_idnn_t;
+
+#ifdef ISP2200
+#define GN_LIST_LENGTH  256 * sizeof(port_list_entry_t)
+#else
+#define GN_LIST_LENGTH  126 * sizeof(port_list_entry_t)
+#endif
+/*
+ * Structure used in Get Port List mailbox command (0x75).
+ */
+typedef struct
+{
+    uint8_t    name[8];
+    uint16_t   loop_id;
+}port_list_entry_t;
+
+/*
+ * Structure used for device info.
+ */
+typedef struct
+{
+    uint8_t	name[8]; /* big endian node name */
+    uint8_t	wwn[8];  /* big endian port name */
+    uint16_t	loop_id;
+    uint8_t	port_id[3];
+}device_data_t;
+
+/*
+ * Port Database structure definition
+ * Little endian except where noted.
+ */
+#define	PORT_DATABASE_SIZE	128	/* bytes */
+typedef struct {
+	uint8_t options;
+	uint8_t control;
+	uint8_t master_state;
+	uint8_t slave_state;
+#define	PD_STATE_DISCOVERY			0
+#define	PD_STATE_WAIT_DISCOVERY_ACK		1
+#define	PD_STATE_PORT_LOGIN			2
+#define	PD_STATE_WAIT_PORT_LOGIN_ACK		3
+#define	PD_STATE_PROCESS_LOGIN			4
+#define	PD_STATE_WAIT_PROCESS_LOGIN_ACK		5
+#define	PD_STATE_PORT_LOGGED_IN			6
+#define	PD_STATE_PORT_UNAVAILABLE		7
+#define	PD_STATE_PROCESS_LOGOUT			8
+#define	PD_STATE_WAIT_PROCESS_LOGOUT_ACK	9
+#define	PD_STATE_PORT_LOGOUT			10
+#define	PD_STATE_WAIT_PORT_LOGOUT_ACK		11
+	uint8_t reserved[2];
+	uint8_t hard_address;
+	uint8_t reserved_1;
+	uint8_t port_id[4];
+	uint8_t node_name[8];			/* Big endian. */
+	uint8_t port_name[8];			/* Big endian. */
+	uint16_t execution_throttle;
+	uint16_t execution_count;
+	uint8_t reset_count;
+	uint8_t reserved_2;
+	uint16_t resource_allocation;
+	uint16_t current_allocation;
+	uint16_t queue_head;
+	uint16_t queue_tail;
+	uint16_t transmit_execution_list_next;
+	uint16_t transmit_execution_list_previous;
+	uint16_t common_features;
+	uint16_t total_concurrent_sequences;
+	uint16_t RO_by_information_category;
+	uint8_t recipient;
+	uint8_t initiator;
+	uint16_t receive_data_size;
+	uint16_t concurrent_sequences;
+	uint16_t open_sequences_per_exchange;
+	uint16_t lun_abort_flags;
+	uint16_t lun_stop_flags;
+	uint16_t stop_queue_head;
+	uint16_t stop_queue_tail;
+	uint16_t port_retry_timer;
+	uint16_t next_sequence_id;
+	uint16_t frame_count;
+	uint16_t PRLI_payload_length;
+	uint8_t prli_svc_param_word_0[2];	/* Big endian */
+						/* Bits 15-0 of word 0 */
+	uint8_t prli_svc_param_word_3[2];	/* Big endian */
+						/* Bits 15-0 of word 3 */
+	uint16_t loop_id;
+	uint16_t extended_lun_info_list_pointer;
+	uint16_t extended_lun_stop_list_pointer;
+} port_database_t;
+
+
+
+/*
+ * Registered State Change Notification structures.
+ */
+typedef struct {
+	port_id_t d_id; 
+	uint8_t format;
+} rscn_t;
+
+
+
+#ifdef FC_IP_SUPPORT
+/*
+ * Definitions for IP support 
+ */
+#define LOOP_ID_MASK            0x00FF
+#define PLE_NOT_SCSI_DEVICE     0x8000  /* Upper bit of loop ID set if not SCSI */
+
+/* Firmware IP initialization control block definitions */
+typedef struct  _IPInitBlock
+{
+    uint8_t     cVersion;
+    uint8_t	    cReserved1;
+    uint16_t	wIpFirmwareOptions;
+    uint16_t	wIpHeaderSize;
+    uint16_t	wIpMTUSize;
+    uint16_t	wIpBufferSize;
+    uint16_t	wReserved2;
+    uint16_t	wReserved3;
+    uint16_t	wReserved4;
+    uint16_t	wReserved5;
+    uint16_t	wIpQueueSize;
+    uint16_t	wIpLowWaterMark;
+    uint16_t	wIpQueueAddr[4];
+    uint16_t	wIpQueueInPointer;
+    uint16_t	wIpFastPostCount;
+    uint16_t	wIpBufferContainerCount;
+    uint16_t	wIpIocbResourceAllocation;
+} IP_INIT_BLOCK, *PIP_INIT_BLOCK;
+
+#define IPIB_VERSION                    0x01
+#define IPIB_LOW_WATER_MARK             0
+#define IPIB_FAST_POST_COUNT            4
+#define IPIB_BUFFER_CONTAINER_COUNT     64
+#define IPIB_IOCB_RESERVE_COUNT         250
+
+/* IP firmware options */
+#define IPIB_OPTION_64BIT_ADDRESSING            0x0001
+#define IPIB_OPTION_NO_BROADCAST_FASTPOST       0x0002
+#define IPIB_OPTION_OUT_OF_BUFFERS_EVENT        0x0004
+
+/* IP device data structure */
+typedef struct _IpDeviceBlock
+{
+    uint32_t    lDeviceFlags;       
+    uint16_t    wLoopId;            
+    uint16_t    wUnused1;
+    uint8_t     acWorldWideName[8]; 
+    uint8_t     acPortId[3];        
+    uint8_t     cUnused2;
+    struct _IpDeviceBlock *pNextIpDevice;      
+    struct _IpDeviceBlock *pLastIpDevice;      
+    uint32_t    lUnused3;
+} IP_DEVICE_BLOCK, *PIP_DEVICE_BLOCK;
+
+#define IP_DEV_FLAG_PRESENT         0x00000001 
+#define IP_DEV_FLAG_PUBLIC_DEVICE   0x00000002
+
+#define PUBLIC_LOOP_DEVICE          ((uint16_t)-1)
+
+/* Maximum number of IP connections */
+#define QLLAN_MAX_IP_DEVICES        64
+
+/* IP IOCB types */
+#define ET_IP_COMMAND_32            0x13
+#define ET_IP_COMMAND_64            0x1B
+#define ET_IP_RECEIVE               0x23
+#define ET_IP_RECEIVE_CONTINUATION  0x2B
+#define ET_IP_FARP_REQUEST          0x30
+
+/* Data segment descriptor structures */
+typedef struct
+{
+    uint32_t    lBase;
+    uint32_t    lCount;
+} DATA_SEG;
+
+typedef struct
+{
+    uint32_t    lBase[2];
+    uint32_t    lCount;
+} DATA_SEG_A64;
+
+/* IP Command IOCB structure */
+typedef struct  _IpCommandEntry
+{
+    uint32_t    lHeader;
+    uint32_t    lHandle;
+    uint8_t     cReserved1;
+    uint8_t     cLoopId;
+    uint16_t    wCompletionStatus;
+    uint16_t    wControlFlags;
+    uint16_t    wReserved2;
+    uint16_t    wTimeout;
+    uint16_t    wSegmentCount;
+    uint16_t    wServiceClass;
+    uint16_t    wReserved3[7];
+    uint32_t    lTotalByteCount;
+    union
+    {
+        DATA_SEG        asDataSeg[3];
+        DATA_SEG_A64    asDataSeg64[2];
+    } ds;
+} IP_COMMAND_ENTRY, *PIP_COMMAND_ENTRY;
+
+/* IP Receive IOCB structure */
+#define IP_RECEIVE_ENTRY_MAX_HANDLES    24
+typedef struct  _IpReceiveEntry
+{
+    uint8_t     cEntryType;
+    uint8_t     cEntryCount;
+    uint8_t     cSegmentCount;
+    uint8_t     cEntryStatus;
+    uint16_t    wS_IDLow;
+    uint8_t     cS_IDHigh;
+    uint8_t     cReserved1;
+    uint8_t     cReserved2;
+    uint8_t     cLoopId;
+    uint16_t    wCompletionStatus;
+    uint16_t    wServiceClass;
+    uint16_t    wSequenseLength;
+    uint16_t    waBufferHandle[IP_RECEIVE_ENTRY_MAX_HANDLES];
+} IP_RECEIVE_ENTRY, *PIP_RECEIVE_ENTRY;
+
+/* IP Receive IOCB completion status bits */
+#define IP_REC_STATUS_SPLIT_BUFFER              0x0001
+
+/* IP FARP Request IOCB structure */
+typedef struct  _IpFarpRequestEntry
+{
+    uint8_t     cEntryType;
+    uint8_t     cEntryCount;
+    uint8_t     cReserved1;
+    uint8_t     cEntryStatus;
+    uint16_t    wRequesterPortIdLow;
+    uint8_t     cRequesterPortIdHigh;
+    uint8_t     cReserved2;
+    uint8_t     acRequesterPortName[8];
+} IP_FARP_REQUEST_ENTRY, *PIP_FARP_REQUEST_ENTRY;
+
+/* IP mailbox commands */
+#define MBC_INITIALIZE_IP               0x0077
+#define MBC_SEND_FARP_REQUEST           0x0078
+
+/* Fabric login mailbox command option bits */
+#define MBC_NO_PLOGI_IF_LOGGED_IN       0x01
+#define MBC_NO_PROCESS_LOGIN            0x02
+
+/* Mailbox command completion status */
+#define MBS_PORT_ID_IN_USE              0x4007
+#define MBS_LOOP_ID_IN_USE              0x4008
+#define MBS_ALL_LOOP_IDS_IN_USE         0x4009
+#define MBS_NAME_SERVER_NOT_LOGGED_IN   0x400A
+
+/* IP async events */
+#define MBA_IP_TRANSMIT_COMPLETE        0x8022
+#define MBA_IP_RECEIVE_COMPLETE         0x8023
+#define MBA_IP_BROADCAST_RECEIVED       0x8024
+#define MBA_IP_RECEIVE_BUFFERS_LOW      0x8025
+#define MBA_IP_OUT_OF_BUFFERS           0x8026
+#define MBA_IP_RECEIVE_COMPLETE_SPLIT   0x8027
+
+/* FARP request payload structure */
+typedef struct  _IpSendFarpPayload
+{
+    uint8_t     cMatchAddressCode;
+    uint8_t     acReserved1[3];
+    uint8_t     cResponderFlags;
+    uint8_t     acReserved2[3];
+    uint8_t     acRequesterPortName[8];
+    uint8_t     acRequesterNodeName[8];
+    uint8_t     acResponderPortName[8];
+    uint8_t     acResponderNodeName[8];
+} IP_SEND_FARP_PAYLOAD, *PIP_SEND_FARP_PAYLOAD;
+
+#define IP_FARP_MATCH_PORTNAME  0x01
+#define IP_FARP_REQUEST_LOGIN   0x01
+#else
+/* Fabric login mailbox command option bits */
+#define MBC_NO_PLOGI_IF_LOGGED_IN       0x01
+#define MBC_NO_PROCESS_LOGIN            0x02
+
+/* Mailbox command completion status */
+#define MBS_PORT_ID_IN_USE              0x4007
+#define MBS_LOOP_ID_IN_USE              0x4008
+#define MBS_ALL_LOOP_IDS_IN_USE         0x4009
+#define MBS_NAME_SERVER_NOT_LOGGED_IN   0x400A
+
+#endif /* FC_IP_SUPPORT */
+
+/*
+ * Linux Host Adapter structure
+ */
+typedef struct scsi_qla_host
+{
+	/* ISP ring lock, rings, and indexes */
+	request_t  req[REQUEST_ENTRY_CNT+1];
+	response_t res[RESPONSE_ENTRY_CNT+1];
+
+	/* Linux adapter configuration data */
+	struct Scsi_Host     *host;   /* pointer to host data */
+	struct scsi_qla_host *next;
+	device_reg_t         *iobase; /* Base Memory-mapped or I/O address */
+	device2300_reg_t     *iobase2300;/* Base Memory-mapped or I/O address */
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
+	struct   pci_dev  *pdev;
+#endif
+	uint8_t  pci_bus;
+	uint8_t  pci_device_fn;
+	uint8_t  devnum;
+	volatile unsigned char *mmpbase; /* memory mapped address */
+	u_long   host_no;
+	u_long   instance;
+	uint8_t  revision;
+	uint8_t  ports;
+	u_long   actthreads;
+	u_long   qthreads;
+	u_long   isr_count;          /* Interrupt count */
+	u_long   isp_aborts;
+	u_long   lip_count;
+	u_long   spurious_int;
+	uint32_t device_id;
+ 
+	/* ISP connection configuration data */
+	uint16_t max_public_loop_ids;
+	uint16_t min_external_loopid; /* First external loop Id */
+	uint8_t  current_topology;   /* Current ISP configuration */
+	uint8_t  prev_topology;      /* Previous ISP configuration */
+#define ISP_CFG_NL   1
+#define ISP_CFG_N    2
+#define ISP_CFG_FL   4
+#define ISP_CFG_F    8
+
+	uint8_t  id;                 /* Host adapter SCSI id */
+	uint16_t loop_id;            /* Host adapter loop id */
+	uint8_t  port_id[3];         /* Host adapter port id */
+	uint8_t  operating_mode;     /* current F/W operating connection mode */
+	                             /* 0 - LOOP, 1 - P2P, 2 - LOOP_P2P,
+	                              * 3 - P2P_LOOP
+	                              */
+
+	/* NVRAM configuration data */
+	uint16_t loop_reset_delay;   /* Loop reset delay. */
+	uint16_t hiwat;              /* High water mark per device. */
+	uint16_t execution_throttle; /* queue depth */ 
+	uint16_t minimum_timeout;    /* Minimum timeout. */
+	uint8_t  retry_count;
+	uint8_t  login_timeout;
+	uint8_t  port_down_retry_count;
+	uint8_t  loop_down_timeout;
+	uint16_t max_luns;
+	uint16_t max_targets;
+
+	/* Device TGT/LUN queues. */
+	tgt_t    *tgt[MAX_BUSES][MAX_FIBRE_DEVICES]; /* Logical unit queues */
+
+	/* Interrupt lock, and data */
+
+	/* Fibre Channel Device Database and LIP sequence. */
+	fcdev_t    fc_db[MAX_FIBRE_DEVICES]; /* Driver database. */
+	uint32_t   flash_db;         /* Flash database address in use. */
+	fabricid_t fabricid[MAX_FIBRE_DEVICES]; /* Fabric ids table . */
+	uint32_t   flash_seq;        /* Flash database seq # in use. */
+	volatile   uint16_t lip_seq;   /* LIP sequence number. */
+    
+	/* Linux bottom half run queue */
+	struct tq_struct run_qla_bh;
+
+	/* Linux kernel thread */
+	struct task_struct *dpc_handler; /* kernel thread */
+	struct semaphore   *dpc_wait;    /* DPC waits on this semaphore */
+	struct semaphore   *dpc_notify;  /* requester waits for DPC on this
+	                                   * semaphore
+	                                   */
+	uint8_t dpc_active;               /* DPC routine is active */
+
+	/* Received ISP mailbox data. */
+	volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
+
+	/* Outstandings ISP commands. */
+	srb_t    *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
+
+#if BITS_PER_LONG > 32
+	uint64_t request_dma;        /* Physical address. */
+#else
+	uint32_t request_dma;        /* Physical address. */
+#endif
+	request_t *request_ring;     /* Base virtual address */
+	request_t *request_ring_ptr; /* Current address. */
+	uint16_t req_ring_index;     /* Current index. */
+	uint16_t req_q_cnt;          /* Number of available entries. */
+
+#if BITS_PER_LONG > 32
+	uint64_t response_dma;       /* Physical address. */
+#else
+	uint32_t response_dma;       /* Physical address. */
+#endif
+	response_t *response_ring;   /* Base virtual address */
+	response_t *response_ring_ptr; /* Current address. */
+	uint16_t rsp_ring_index;     /* Current index. */
+    
+#if QL2X00_TARGET_MODE_SUPPORT
+	/* Target buffer and sense data. */
+	u_long   tbuf_dma;           /* Physical address. */
+	tgt_buf_t *tbuf;
+	u_long   tsense_dma;         /* Physical address. */
+	uint8_t  *tsense;
+#endif
+
+#ifdef FC_IP_SUPPORT
+	/* Data for IP support */
+	uint8_t  acPortName[8];
+	IP_BUFFER_ENTRY asIpBuffers[IP_BUFFER_QUEUE_DEPTH];
+	uint32_t ppIpBufferQueueLow;
+	uint32_t ppIpBufferQueueHigh;
+	IP_BUFFER_ENTRY *pIpBufferQueue;  
+	uint16_t wIpBufferIn;
+	uint16_t wIpBufferOut;
+	uint32_t lMaximumTransferSize;
+	uint32_t lReceiveBufferSize;
+	uint16_t wReceiveBufferCount;
+	uint16_t wHeaderSize;
+	PSEND_COMPLETION_CALLBACK pSendCompletionRoutine;
+	PRECEIVE_PACKETS_CALLBACK pReturnReceivePacketsRoutine;
+	void     *pReturnReceivePacketsContext;
+	PNOTIFY_CALLBACK pNotifyRoutine;
+	void     *pNotifyContext;
+	BUFFER_CB *pReceiveBufferCBs;
+	IP_DEVICE_BLOCK asIpDeviceDatabase[QLLAN_MAX_IP_DEVICES];
+	IP_DEVICE_BLOCK *pIpDeviceFree;
+	IP_DEVICE_BLOCK *pIpDeviceTop;
+	IP_DEVICE_BLOCK *pIpDeviceBottom;
+	uint32_t lCurrentTagIndex;
+	void     *apActiveIpQueue[MAX_SEND_PACKETS];
+#endif
+
+	/* Firmware Initialization Control Block data */
+#if BITS_PER_LONG > 32
+	uint64_t init_cb_dma;        /* Physical address. */
+#else
+	uint32_t init_cb_dma;        /* Physical address. */
+#endif
+	init_cb_t *init_cb;
+  
+	/* Timeout timers. */
+	uint8_t  queue_restart_timer;   
+	uint8_t  loop_down_timer;    /* loop down timer */
+	uint8_t  loop_down_abort_time; /* port down timer */
+	uint32_t timer_active;
+	uint32_t forceLip;
+	struct   timer_list timer;
+
+	/* Watchdog queue, lock and total timer */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
+	spinlock_t retry_lock;       /* Watchdog Queue Lock */
+#endif
+	srb_t    *retry_q_first;     /* First job on watchdog queue */
+	srb_t    *retry_q_last;      /* Last job on watchdog queue */
+
+	srb_t    *done_q_first;      /* First job on done queue */
+	srb_t    *done_q_last;       /* Last job on done queue */
+
+	/* RSCN queue. */
+	rscn_t   rscn_queue[MAX_RSCN_COUNT];
+	uint8_t  rscn_in_ptr;
+	uint8_t  rscn_out_ptr;
+
+	/* Host Adapter database */
+	fcdev_t  *phost_db;
+	uint8_t  host_db_ptr;
+
+	volatile struct
+	{
+	    uint32_t online                  :1;   /* 0 */
+	    uint32_t enable_64bit_addressing :1;   /* 1 */
+	    uint32_t mbox_int                :1;   /* 2 */
+	    uint32_t mbox_busy               :1;   /* 3 */
+	    uint32_t reset_marker            :1;   /* 4 */
+	    uint32_t loop_resync_needed      :1;   /* 5 */
+	    uint32_t watchdog_enabled        :1;   /* 6 */
+	    uint32_t isp_abort_needed        :1;   /* 7 */
+	    uint32_t disable_host_adapter    :1;   /* 8 */
+	    uint32_t loop_resync_active      :1;   /* 9 */
+	    uint32_t reset_active            :1;   /* 10 */
+	    uint32_t abort_isp_active        :1;   /* 11 */
+	    uint32_t disable_risc_code_load  :1;   /* 12 */
+	    uint32_t set_cache_line_size_1   :1;   /* 13 */
+	    uint32_t enable_target_mode      :1;   /* 14 */
+	    uint32_t disable_luns            :1;   /* 15 */
+	    uint32_t enable_lip_reset        :1;   /* 16 */
+	    uint32_t enable_lip_full_login   :1;   /* 17 */
+	    uint32_t enable_target_reset     :1;   /* 18 */
+	    uint32_t updated_fc_db           :1;   /* 19 */
+	    uint32_t enable_flash_db_update  :1;   /* 20 */
+	    uint32_t abort_queue_needed      :1;   /* 21 */
+
+#define QLA2100_IN_ISR_BIT      22
+	    uint32_t in_isr                  :1;   /* 22 */
+	    uint32_t dpc_sched               :1;   /* 23 */
+	    uint32_t start_timer             :1;   /* 24 */
+	    uint32_t nvram_config_done       :1;   /* 25 */
+	    uint32_t update_config_needed    :1;   /* 26 */
+	    uint32_t done_requests_needed    :1;   /* 27 */
+	    uint32_t restart_queues_needed   :1;   /* 28 */
+	    uint32_t port_restart_needed     :1;   /* 29 */
+#ifdef FC_IP_SUPPORT
+	    uint32_t enable_ip               :1;   /* 30 */
+#endif
+	  /* 4.11 */
+	    uint32_t managment_server_logged_in:1; /* 31 */
+	} flags;
+
+	    uint32_t device_flags;
+#define DFLG_LOCAL_DEVICES       BIT_0
+#define DFLG_RETRY_LOCAL_DEVICES BIT_1
+#define	RSCN_UPDATE              BIT_2
+#define	LOGIN_RETRY_NEEDED       BIT_3
+#define	RSCN_QUEUE_OVERFLOW      BIT_4
+#define DFLG_FABRIC_DEVICES      BIT_5
+#define	RELOGIN_NEEDED           BIT_6
+
+	uint8_t  marker_needed;
+	uint8_t  missing_targets;
+	uint8_t  sns_retry_cnt;
+	uint8_t  cmd_wait_cnt;
+	uint32_t dpc_flags;
+#define MAILBOX_RETRY            BIT_0
+#define COMMAND_WAIT_NEEDED      BIT_1
+#define COMMAND_WAIT_ACTIVE      BIT_2
+#define ISP_RESET_NEEDED         BIT_3
+#define LOGOUT_DONE              BIT_4
+#define ISP_RESET_ONCE           BIT_5
+
+	uint16_t interrupts_on;
+
+	volatile uint16_t loop_state;
+/* These values are NOT used as flags. */
+#define LOOP_TIMEOUT   0x1
+#define LOOP_DOWN      0x2
+#define LOOP_UP        0x4
+#define LOOP_UPDATE    0x8
+#define LOOP_READY     0x10
+
+	/* following are new and needed for IOCTL support */
+	uint8_t  node_name[8];
+	uint8_t  nvram_version; 
+	uint8_t  ioctl_timer;
+	uint8_t  IoctlPassThru_InProgress;
+	uint8_t  IoctlPassFCCT_InProgress;
+	void     *ioctl_mem;
+#if BITS_PER_LONG > 32
+	uint64_t ioctl_mem_phys;
+#else
+	uint32_t ioctl_mem_phys;
+#endif
+
+	/* HBA serial number */
+	uint8_t  serial0;
+	uint8_t  serial1;
+	uint8_t  serial2;
+
+	/* oem related items */
+	uint8_t  oem_id;
+	uint8_t  oem_spare0;
+	uint8_t  oem_part[6];
+	uint8_t  oem_fru[8];
+	uint8_t  oem_ec[8];
+	uint8_t  oem_string[8];
+
+	uint32_t dump_done;
+
+} scsi_qla_host_t;
+
+/*
+ * Macros to help code, maintain, etc.
+ */
+#define TGT_Q(ha, b, t)    (ha->tgt[b][t])
+#define GET_LU_Q(ha, b, t, l)  ( (TGT_Q(ha,b,t) != NULL)? TGT_Q(ha, b, t)->luns[l] : NULL)
+#define LU_Q(ha, b, t, l)  (TGT_Q(ha, b, t)->luns[l])
+#define PORT_DOWN(ha, t)    ((ha)->fc_db[(t)].port_timer)
+
+/*
+ * Locking Macro Definitions
+ *
+ * LOCK/UNLOCK definitions are lock/unlock primitives for multi-processor
+ * or spl/splx for uniprocessor.
+ */
+#define QLA2100_INTR_LOCK(ha)    
+#define QLA2100_INTR_UNLOCK(ha) 
+
+#define QLA2100_RING_LOCK(ha)  
+#define QLA2100_RING_UNLOCK(ha)
+
+#if defined(__cplusplus)
+}
+#endif
+#endif
+
+#if defined(__386__)
+#  define QLA2100_BIOSPARAM  qla2100_biosparam
+#else
+#  define QLA2100_BIOSPARAM  NULL
+#endif
+
+/*
+ *  Linux - SCSI Driver Interface Function Prototypes.
+ */
+int qla2100_ioctl(Scsi_Device *, int , void *);
+int qla2100_proc_info ( char *, char **, off_t, int, int, int);
+const char * qla2100_info(struct Scsi_Host *host);
+int qla2100_detect(Scsi_Host_Template *);
+int qla2100_release(struct Scsi_Host *);
+const char * qla2100_info(struct Scsi_Host *);
+int qla2100_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *));
+int qla2100_abort(Scsi_Cmnd *);
+int qla2100_reset(Scsi_Cmnd *, unsigned int);
+int qla2100_biosparam(Disk *, kdev_t, int[]);
+void qla2100_intr_handler(int, void *, struct pt_regs *);
+//void qla2100_device_queue_depth(scsi_qla_host_t *, Scsi_Device *);
+void qla2100_setup(char *s, int *dummy);
+
+/* Number of segments 1 - 65535 */
+#define SG_SEGMENTS     32             /* Cmd entry + 6 continuations */
+
+/*
+ * Scsi_Host_template (see hosts.h) 
+ * Device driver Interfaces to mid-level SCSI driver.
+ */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
+/* This interface is now obsolete !!! */ 
+#define QLA2100_LINUX_TEMPLATE {		                 \
+        next:           NULL,                                    \
+        usage_count:    NULL,                                    \
+	proc_dir:		NULL,          	                 \
+	proc_info:		qla2100_proc_info,	                         \
+	name:			"Qlogic Fibre Channel 2100",               \
+	detect:			qla2100_detect,	                 \
+	release:		qla2100_release,                 \
+	info:			qla2100_info,	                 \
+        command:        NULL,                                    \
+	queuecommand:	qla2100_queuecommand,	                 \
+	abort:			qla2100_abort,	                 \
+	reset:			qla2100_reset,	                 \
+        slave_attach:   NULL,                                    \
+	bios_param:		QLA2100_BIOSPARAM,               \
+	can_queue:		1, /* MAX_OUTSTANDING_COMMANDS */   \
+	this_id:		-1,  /* scsi id of host adapter */        \
+	sg_tablesize:	SG_ALL,   \
+	cmd_per_lun:	1,	  /* max commands per lun */	       \
+	present:	    0,    /* number of ISP present */	       \
+	unchecked_isa_dma: 0, /* no memeory DMA restrictions */    \
+	use_clustering:	ENABLE_CLUSTERING			               \
+}
+#else
+
+#define QLA2100_LINUX_TEMPLATE {		                 \
+	next: NULL,						\
+	module: NULL,						\
+	proc_dir: NULL,						\
+	proc_info: qla2100_proc_info,	                        \
+	name:			"Qlogic Fibre Channel 2100",    \
+	detect:			qla2100_detect,	                 \
+	release:		qla2100_release,                 \
+	info:			qla2100_info,	                 \
+	ioctl: qla2100_ioctl,                                    \
+	command: NULL,						\
+	queuecommand: qla2100_queuecommand,			\
+	eh_strategy_handler: NULL,				\
+	eh_abort_handler: NULL,					\
+	eh_device_reset_handler: NULL,				\
+	eh_bus_reset_handler: NULL,				\
+	eh_host_reset_handler: NULL,				\
+	abort: qla2100_abort,					\
+	reset: qla2100_reset,					\
+	slave_attach: NULL,					\
+	bios_param: QLA2100_BIOSPARAM,				\
+	can_queue: 255,		/* max simultaneous cmds      */\
+	this_id: -1,		/* scsi id of host adapter    */\
+	sg_tablesize: SG_SEGMENTS,	/* max scatter-gather cmds    */\
+	cmd_per_lun: 3,		/* cmds per lun (linked cmds) */\
+	present: 0,		/* number of 7xxx's present   */\
+	unchecked_isa_dma: 0,	/* no memory DMA restrictions */\
+	use_clustering: ENABLE_CLUSTERING,			\
+	use_new_eh_code: 0,					\
+	emulated: 0					        \
+}
+#endif
+#endif /* _IO_HBA_QLA2100_H */
diff -urN linux-2.4.16/drivers/scsi/qla2x00exioct.h lia64-2.4/drivers/scsi/qla2x00exioct.h
--- linux-2.4.16/drivers/scsi/qla2x00exioct.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qla2x00exioct.h	Mon Jul 23 14:12:38 2001
@@ -0,0 +1,823 @@
+/*
+ * File Name: exioct.h
+ *
+ * San/Device Management Ioctl Header
+ * File is created to adhere to Solaris requirement using 8-space tabs.
+ *
+ * !!!!! PLEASE DO NOT REMOVE THE TABS !!!!!
+ * !!!!! PLEASE NO SINGLE LINE COMMENTS: // !!!!!
+ * !!!!! PLEASE NO MORE THAN 80 CHARS PER LINE !!!!!
+ *
+ * ***********************************************************************
+ * *                                                                    **
+ * *                            NOTICE                                  **
+ * *            COPYRIGHT (C) 2000 QLOGIC CORPORATION                   **
+ * *                    ALL RIGHTS RESERVED                             **
+ * *                                                                    **
+ * ***********************************************************************
+ *
+ * Revision History:
+ *
+ * Rev. 0	March 1, 2000
+ * YPL	- Created.
+ *
+ * Rev. 1	March 2, 2000
+ * RLU	- Updated with latest definitions.  Added more comments.
+ *
+ * Rev. 2	May 16, 2000		    
+ * SP	- Updated definitions and changed structures (March 27, 2000)
+ * SP   - Addded structures 
+ *
+ * Rev. 3	June 1, 2000		     
+ * THL	- Made major changes to include all changes talked in our meeting.
+ *
+ * Rev. 4	June 5, 2000
+ * RLU	- Added new definitions/structures for SDM_GET_AEN and SDM_REG_AEN 
+ *	  functions.
+ *	- Major definition/structure name changes as discussed in meetings.
+ *	- Deleted duplicated command code and structure definitions.
+ *
+ * Rev. 4.1	June 14, 2000
+ * WTR  - Moved Solaris specific defines to exioctso.h. This makes it
+ *	  possible for application developers to include only exioct.h
+ *	  in their Solaris application development.
+ *
+ * Rev. 4.2	June 15, 2000
+ * THL  - Changed UINT16 and UINT32 back to WORD and DWORD for NT; otherwise,
+ *	  NT will get a compilation error for redefining UINT16 and UINT32.
+ *	  Added RISC_CODE/FLASH_RAM macros.
+ *
+ * Rev. 4.3	June 22, 2000
+ * THL  - Changed SDM_FC_ADDR according to External Ioctls document.
+ *	  Added SDM_DEF_TYPE macros.
+ *
+ * Rev. 4.4	June 22, 2000
+ * THL  - Moved NT specific defines to exioctnt.h.
+ *
+ * Rev. 4.5     August 15, 2000
+ * SP   - Rolled back some changes made by Todd R.
+ *        Kept new status code SDM_STATUS_NO_MEMORY
+ *        Port types fabric and tape device 
+ *
+ * Rev. 4.7     Sep 6, 2000
+ * YPL  - Replace SDM_ with EXT_, _ISP with _CHIP.
+ *        Add vendor specific statuses, device update, config defines.
+ *
+ * Rev. 5.0     Sep 13, 2000
+ * YPL  - Update version to 5, remove max defines, make port type bit.
+ *        Change HBA_PORT_PROPERTY to have bus/target/lun defined as UINT16
+ *
+ * Rev. 5.1     Sep 22, 2000
+ * THL  - Add destination address for specify scsi address or FC address.
+ *        Remove "not support" comment and add more macros.
+ *
+ * Rev. 5.2     Sep 27, 2000
+ * THL  - Add new macros and structure for add and swap target device.
+ *        Create new data structure for get port database.
+ * TLE  - Merge changes needed for FailOver
+ *
+ * Rev. 5.3     Sep 29, 2000
+ * THL  - Add access mode for NVRAM.
+ * 
+ * Rev. 5.4     Oct 03, 2000
+ * THL  - Add EXT_SC_GET_FC_STATISTICS.
+ *
+ * Rev. 5.5	Oct 18, 2000
+ * THL  - Remove duplicated EXT_DEF_ADDR_MODE_32 and EXT_DEF_ADDR_MODE_16.
+ *        Reformat new data structures and defines.
+ *
+ * Rev. 5.6	Oct 19, 2000
+ * RLU	- Changed file name from ExIoct.h to exioct.h.
+ *	- Added definition of EXT_RNID_DATA for API implementation.
+ *	- Reformat some lines to conform to the format agreed
+ *	  upon in IOCTL meeting (and mentioned at beginning of
+ *	  this file).
+ *
+ * Rev. 5.7 Oct 25, 2000
+ * BN   - Added LUN bitmask structure and macros
+ *
+ * Rev. 5.8 Oct 25, 2000
+ * BN   - Added EXT_CC_DRIVER_PROP define
+ * 
+ * Rev. 5.9 Oct 26, 2000
+ * BN   - Sync with UnixApi project
+ * 
+ * Rev. 5.10 Oct 30, 2000
+ * BN   - Remove not needed #define for EXT_CC_DRIVER_PROP
+ *      - Add EXT_ to IS_LUN_BIT_SET, SET_LUN_BIT, CLR_LUN_BIT
+ * 
+ * Rev. 5.11 Nov 1, 2000
+ * BN   - Increased [1] of EXT_DEVICEDATA to [EXT_MAX_TARGET]
+ * TLE  - Decreased [EXT_MAX_TARGET] of EXT_DEVICEDATA to [1]
+ * 
+ * Rev. 5.12	Nov 7, 2000
+ * RLU	- Deleted EXT_DEF_MAX_LUNS define and changed all references
+ *	  to it to use EXT_MAX_LUN.
+ *	- Changed the revision numbers for the last 2 revisions down
+ *	  to use 5.x.
+ * 
+ * Rev. 5.13	Nov 28, 2000
+ * RLU	- Change value defines from EXT_... to EXT_DEF_...
+ * 
+ * Rev. 5.14    Jan 08, 2001
+ * BN   - Added    #define SDM_CC_LOOPBACK   SDM_CC_LOOPBACK_OS
+ * 
+ */
+
+#ifndef	_EXIOCT_H
+#define	_EXIOCT_H
+
+/*
+ * NOTE: the following version defines must be updated each time the
+ *	 changes made may affect the backward compatibility of the
+ *	 input/output relations of the SDM IOCTL functions.
+ */
+#define	EXT_VERSION					5
+
+
+/*
+ * OS independent General definitions
+ */
+#define	EXT_DEF_SIGNATURE_SIZE				8
+#define	EXT_DEF_WWN_NAME_SIZE				8
+#define	EXT_DEF_WWP_NAME_SIZE				8
+#define	EXT_DEF_SERIAL_NUM_SIZE				4
+#define	EXT_DEF_PORTID_SIZE				4
+#define	EXT_DEF_PORTID_SIZE_ACTUAL			3
+#define	EXT_DEF_MAX_STR_SIZE				128
+#define	EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH		12
+
+#define	EXT_DEF_ADDR_MODE_32				1
+#define	EXT_DEF_ADDR_MODE_64				2
+
+/*
+ * ***********************************************************************
+ * X OS type definitions
+ * ***********************************************************************
+ */
+#ifdef _MSC_VER						/* NT */
+
+#pragma pack(1)
+#include "ExIoctNT.h"
+
+#elif defined(linux)					/* Linux */
+
+#include "qla2x00exioctln.h"
+
+#elif defined(sun) || defined(__sun)			/* Solaris */
+
+#include "exioctso.h"
+
+#endif
+
+/*
+ * ***********************************************************************
+ * OS dependent General configuration defines
+ * ***********************************************************************
+ */
+#define	EXT_DEF_MAX_HBA                 EXT_DEF_MAX_HBA_OS
+#define	EXT_DEF_MAX_BUS                 EXT_DEF_MAX_BUS_OS
+#define	EXT_DEF_MAX_TARGET              EXT_DEF_MAX_TARGET_OS
+#define	EXT_DEF_MAX_LUN                 EXT_DEF_MAX_LUN_OS
+
+/*
+ * ***********************************************************************
+ * Common header struct definitions for San/Device Mgmt
+ * ***********************************************************************
+ */
+typedef struct {
+	UINT64    Signature;			/* 8 chars string */
+	UINT16    AddrMode;			/* 2 */
+	UINT16    Version;			/* 2 */
+	UINT16    SubCode;			/* 2 */
+	UINT16    Instance;			/* 2 */
+	UINT32    Status;			/* 4 */
+	UINT32    DetailStatus;			/* 4 */
+	UINT32    Reserved1;			/* 4 */
+	UINT32    RequestLen;			/* 4 */
+	UINT32    ResponseLen;			/* 4 */
+	UINT64    RequestAdr;			/* 8 */
+	UINT64    ResponseAdr;			/* 8 */
+	UINT16    HbaSelect;			/* 2 */
+	UINT16    VendorSpecificStatus[11];	/* 22 */
+	UINT64    VendorSpecificData;		/* 8 chars string */
+} EXT_IOCTL, *PEXT_IOCTL;			/* 84 / 0x54 */
+
+/*
+ * Addressing mode used by the user application
+ */
+#define	EXT_ADDR_MODE			EXT_ADDR_MODE_OS
+
+/*
+ * Status.  These macros are being used for setting Status field in
+ * EXT_IOCTL structure.
+ */
+#define	EXT_STATUS_OK				0
+#define	EXT_STATUS_ERR				1
+#define	EXT_STATUS_BUSY				2
+#define	EXT_STATUS_PENDING			3
+#define	EXT_STATUS_SUSPENDED			4
+#define	EXT_STATUS_RETRY_PENDING		5
+#define	EXT_STATUS_INVALID_PARAM		6
+#define	EXT_STATUS_DATA_OVERRUN			7
+#define	EXT_STATUS_DATA_UNDERRUN		8
+#define	EXT_STATUS_DEV_NOT_FOUND		9
+#define	EXT_STATUS_COPY_ERR			10
+#define	EXT_STATUS_MAILBOX			11
+#define	EXT_STATUS_UNSUPPORTED_SUBCODE		12
+#define	EXT_STATUS_UNSUPPORTED_VERSION		13
+#define	EXT_STATUS_MS_NO_RESPONSE		14
+#define	EXT_STATUS_SCSI_STATUS			15
+#define	EXT_STATUS_BUFFER_TOO_SMALL		16
+#define	EXT_STATUS_NO_MEMORY			17
+#define	EXT_STATUS_UNKNOWN			18
+#define	EXT_STATUS_UNKNOWN_DSTATUS		19
+#define	EXT_STATUS_INVALID_REQUEST		20
+
+/*
+ * Detail Status contains the SCSI bus status codes.
+ */
+
+#define	EXT_DSTATUS_GOOD			0x00
+#define	EXT_DSTATUS_CHECK_CONDITION		0x02
+#define	EXT_DSTATUS_CONDITION_MET		0x04
+#define	EXT_DSTATUS_BUSY			0x08
+#define	EXT_DSTATUS_INTERMEDIATE		0x10
+#define	EXT_DSTATUS_INTERMEDIATE_COND_MET	0x14
+#define	EXT_DSTATUS_RESERVATION_CONFLICT	0x18
+#define	EXT_DSTATUS_COMMAND_TERMINATED		0x22
+#define	EXT_DSTATUS_QUEUE_FULL			0x28
+
+/*
+ * Detail Status contains the needed Response buffer space(bytes)
+ * when Status = EXT_STATUS_BUFFER_TOO_SMALL
+ */
+
+
+/*
+ * Detail Status contains one of the following codes
+ * when Status = EXT_STATUS_INVALID_PARAM or
+ *             = EXT_STATUS_DEV_NOT_FOUND
+ */
+#define EXT_DSTATUS_NOADNL_INFO			0x00
+#define EXT_DSTATUS_HBA_INST			0x01
+#define EXT_DSTATUS_TARGET			0x02
+#define EXT_DSTATUS_LUN				0x03
+#define EXT_DSTATUS_REQUEST_LEN			0x04
+#define EXT_DSTATUS_PATH_INDEX			0x05
+
+/*
+ * Currently supported DeviceControl / ioctl command codes
+ */
+#define	EXT_CC_QUERY			EXT_CC_QUERY_OS
+#define	EXT_CC_SEND_FCCT_PASSTHRU	EXT_CC_SEND_FCCT_PASSTHRU_OS
+#define	EXT_CC_REG_AEN			EXT_CC_REG_AEN_OS
+#define	EXT_CC_GET_AEN			EXT_CC_GET_AEN_OS
+#define	EXT_CC_SEND_ELS_RNID		EXT_CC_SEND_ELS_RNID_OS
+#define	EXT_CC_SEND_SCSI_PASSTHRU	EXT_CC_SCSI_PASSTHRU_OS
+#define	EXT_CC_READ_HOST_PARAMS		EXT_CC_READ_HOST_PARAMS_OS    
+#define	EXT_CC_READ_RISC_PARAMS		EXT_CC_READ_RISC_PARAMS_OS    
+#define	EXT_CC_UPDATE_HOST_PARAMS	EXT_CC_UPDATE_HOST_PARAMS_OS
+#define	EXT_CC_UPDATE_RISC_PARAMS	EXT_CC_UPDATE_RISC_PARAMS_OS
+#define	EXT_CC_READ_NVRAM		EXT_CC_READ_NVRAM_OS
+#define	EXT_CC_UPDATE_NVRAM		EXT_CC_UPDATE_NVRAM_OS
+
+#define EXT_CC_LOOPBACK                 EXT_CC_LOOPBACK_OS
+/*
+ * HBA port operations
+ */
+#define	EXT_CC_GET_DATA			EXT_CC_GET_DATA_OS
+#define	EXT_CC_SET_DATA			EXT_CC_SET_DATA_OS
+
+/*
+ * The following DeviceControl / ioctl command codes currently are not
+ * supported.
+ */
+#define	EXT_CC_SEND_ELS_RTIN		EXT_CC_SEND_ELS_RTIN_OS
+
+
+/*
+ * ***********************************************************************
+ * EXT_IOCTL SubCode definition.
+ * These macros are being used for setting SubCode field in EXT_IOCTL
+ * structure.
+ * ***********************************************************************
+ */
+
+/*
+ * Query.
+ * Uses with EXT_QUERY as the ioctl code.
+ */
+#define	EXT_SC_QUERY_HBA_NODE		1
+#define	EXT_SC_QUERY_HBA_PORT		2
+#define	EXT_SC_QUERY_DISC_PORT		3
+#define	EXT_SC_QUERY_DISC_TGT		4
+#define	EXT_SC_QUERY_DISC_LUN		5	/* Currently Not Supported */
+#define	EXT_SC_QUERY_DRIVER		6
+#define	EXT_SC_QUERY_FW			7
+#define	EXT_SC_QUERY_CHIP		8
+
+/*
+ * Get.
+ * Uses with EXT_GET_DATA as the ioctl code
+ */
+/* 1 - 99 Common */
+#define	EXT_SC_GET_SCSI_ADDR		1	/* Currently Not Supported */
+#define	EXT_SC_GET_ERR_DETECTIONS	2	/* Currently Not Supported */
+#define	EXT_SC_GET_STATISTICS		3
+#define	EXT_SC_GET_BUS_MODE		4	/* Currently Not Supported */
+#define	EXT_SC_GET_DR_DUMP_BUF		5	/* Currently Not Supported */
+#define	EXT_SC_GET_RISC_CODE		6
+#define	EXT_SC_GET_FLASH_RAM		7
+
+/* 100 - 199 FC_INTF_TYPE */
+#define	EXT_SC_GET_LINK_STATUS		101	/* Currently Not Supported */
+#define	EXT_SC_GET_LOOP_ID		102	/* Currently Not Supported */
+#define	EXT_SC_GET_LUN_BITMASK		103
+#define	EXT_SC_GET_PORT_DATABASE	104	/* Currently Not Supported */
+#define	EXT_SC_GET_PORT_DATABASE_MEM	105	/* Currently Not Supported */
+#define	EXT_SC_GET_PORT_SUMMARY		106
+#define	EXT_SC_GET_POSITION_MAP		107
+#define	EXT_SC_GET_RETRY_CNT		108	/* Currently Not Supported */
+#define	EXT_SC_GET_RNID			109	
+#define	EXT_SC_GET_RTIN			110	/* Currently Not Supported */
+#define	EXT_SC_GET_FC_LUN_BITMASK	111
+#define	EXT_SC_GET_FC_STATISTICS	112
+
+/* 200 - 299 SCSI_INTF_TYPE */
+#define	EXT_SC_GET_SEL_TIMEOUT		201	/* Currently Not Supported */
+
+
+/* 
+ * Set.
+ * Uses with EXT_SET_DATA as the ioctl code
+ */
+/* 1 - 99 Common */
+#define	EXT_SC_RST_STATISTICS		3	/* Currently Not Supported */
+#define	EXT_SC_SET_BUS_MODE		4	/* Currently Not Supported */
+#define	EXT_SC_SET_DR_DUMP_BUF		5	/* Currently Not Supported */
+#define	EXT_SC_SET_RISC_CODE		6
+#define	EXT_SC_SET_FLASH_RAM		7
+
+/* 100 - 199 FC_INTF_TYPE */
+#define	EXT_SC_SET_LUN_BITMASK		103
+#define	EXT_SC_SET_RETRY_CNT		108	/* Currently Not Supported */
+#define	EXT_SC_SET_RNID			109	
+#define	EXT_SC_SET_RTIN			110	/* Currently Not Supported */
+#define	EXT_SC_SET_FC_LUN_BITMASK	111
+#define	EXT_SC_ADD_TARGET_DEVICE	112
+#define	EXT_SC_SWAP_TARGET_DEVICE	113
+
+/* 200 - 299 SCSI_INTF_TYPE */
+#define	EXT_SC_SET_SEL_TIMEOUT		201	/* Currently Not Supported */
+
+/* SCSI passthrough */
+#define	EXT_SC_SEND_SCSI_PASSTHRU	0
+#define	EXT_SC_SEND_FC_SCSI_PASSTHRU	1
+
+/* NVRAM */
+#define	EXT_SC_NVRAM_HARDWARE		0	/* Save */
+#define	EXT_SC_NVRAM_DRIVER		1	/* Driver (Apply) */
+#define	EXT_SC_NVRAM_ALL		2	/* NVRAM/Driver (Save+Apply) */
+
+/* Read */
+
+/* Write */
+
+/* Reset */
+
+/* Request struct */
+
+
+/*
+ * Response struct
+ */
+typedef struct _EXT_HBA_NODE {
+	UINT8     WWNN         [EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     Manufacturer [EXT_DEF_MAX_STR_SIZE];	/* 128; "QLOGIC" */
+	UINT8     Model        [EXT_DEF_MAX_STR_SIZE];	/* 128; "QLA2200" */
+	UINT8     SerialNum    [EXT_DEF_SERIAL_NUM_SIZE];/* 4;  123  */
+	UINT8     DriverVersion[EXT_DEF_MAX_STR_SIZE];	/* 128; "7.4.3" */
+	UINT8     FWVersion    [EXT_DEF_MAX_STR_SIZE];	/* 128; "2.1.6" */
+
+	/* The following field is currently not supported */
+	UINT8     OptRomVersion[EXT_DEF_MAX_STR_SIZE];	/* 128; "1.44" */
+
+	UINT16    PortCount;				/* 2; 1 */
+	UINT16    InterfaceType;			/* 2; FC/SCSI */
+
+	/* The following two fields are not yet supported */
+	UINT32    DriverAttr;				/* 4 */
+	UINT32    FWAttr;				/* 4 */
+
+	UINT32    Reserved[8];				/* 32 */
+} EXT_HBA_NODE, *PEXT_HBA_NODE;				/* 696 */
+
+/* HBA node query interface type */
+#define	EXT_DEF_FC_INTF_TYPE			1
+#define	EXT_DEF_SCSI_INTF_TYPE			2
+
+typedef struct _EXT_HBA_PORT {
+	UINT8     WWPN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     Id  [EXT_DEF_PORTID_SIZE];	/* 4; 3 bytes valid Port Id. */
+	UINT16    Type;				/* 2; Port Type */
+	UINT16    State;			/* 2; Port State */
+	UINT16    Mode;				/* 2 */
+	UINT16    DiscPortCount;		/* 2 */
+	UINT16    DiscPortNameType;		/* 2; USE_NODE_NAME or */
+						/* USE_PORT_NAME */
+	UINT16    DiscTargetCount;		/* 2 */
+	UINT16    Bus;				/* 1 */
+	UINT16    Target;			/* 1 */
+	UINT16    Lun;				/* 1 */
+	UINT16    Unused;			/* 1 */
+	UINT32    Reserved[6];			/* 28 */
+} EXT_HBA_PORT, *PEXT_HBA_PORT;			/* 56 */
+
+/* port type bit definitions */
+#define	EXT_DEF_INITIATOR_DEV		0x1
+#define	EXT_DEF_TARGET_DEV		0x2
+#define	EXT_DEF_TAPE_DEV		0x4
+#define	EXT_DEF_FABRIC_DEV		0x8
+
+
+/* HBA port state */
+#define	EXT_DEF_HBA_OK			0
+#define	EXT_DEF_HBA_SUSPENDED		1
+#define	EXT_DEF_HBA_LOOP_DOWN		2
+
+/* Connection mode */
+#define	EXT_DEF_P2P_MODE		1
+#define	EXT_DEF_LOOP_MODE		2
+
+/* Valid name type for Disc. port/target */
+#define	EXT_DEF_USE_NODE_NAME		1
+#define	EXT_DEF_USE_PORT_NAME		2
+
+typedef struct _EXT_DISC_PORT {
+	UINT8     WWNN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     WWPN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     Id  [EXT_DEF_PORTID_SIZE];	/* 4; 3 bytes used. big endian*/
+
+	/* The following fields currently are not supported */
+	UINT16    Type;				/* 2; Port Type */
+	UINT16    Status;			/* 2; Port Status */
+	UINT16    Bus;				/* 2; n/a for Solaris */
+
+	UINT16    TargetId;			/* 2 */
+	UINT32    Reserved[8];			/* 32 */
+} EXT_DISC_PORT, *PEXT_DISC_PORT;		/* 60 */
+
+typedef struct _EXT_DISC_TARGET {
+	UINT8     WWNN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     WWPN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+	UINT8     Id  [EXT_DEF_PORTID_SIZE];	/* 4; 3 bytes used. big endian*/
+
+	/* The following fields currently are not supported */
+	UINT16    Type;				/* 2; Target Type */
+	UINT16    Status;			/* 2; Target Status*/
+	UINT16    Bus;				/* 2; n/a for Solaris */
+
+	UINT16    TargetId;			/* 2 */
+
+	/* The following field is currently not supported */
+	UINT16    LunCount;			/* 2; n/a for nt */
+
+	UINT16    Reserved[15];			/* 30 */
+} EXT_DISC_TARGET, *PEXT_DISC_TARGET;		/* 60 */
+
+/* The following command is not supported */
+typedef struct _EXT_DISC_LUN {			/* n/a for nt */
+	UINT16    Id;				/* 2 */
+	UINT16    State;			/* 2 */
+	UINT16    IoCount;			/* 2 */
+	UINT16    Reserved[15];			/* 30 */
+} EXT_DISC_LUN, *PEXT_DISC_LUN;			/* 36 */
+
+
+/* SCSI address */
+typedef struct _EXT_SCSI_ADDR {
+	UINT16    Bus;				/* 2 */
+	UINT16    Target;			/* 2 */
+	UINT16    Lun;				/* 2 */
+	UINT16    Padding[5];			/* 10 */
+} EXT_SCSI_ADDR, *PEXT_SCSI_ADDR;		/* 16 */
+
+
+/* Fibre Channel address */
+typedef struct _EXT_FC_ADDR {
+	union {
+		UINT8    WWNN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+		UINT8    WWPN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+		UINT8    Id[EXT_DEF_PORTID_SIZE];	/* 4 */
+	} FcAddr;
+	UINT16    Type;					/* 2 */
+	UINT16    Padding[2];				/* 2 */
+} EXT_FC_ADDR, *PEXT_FC_ADDR;				/* 24 */
+
+#define	EXT_DEF_TYPE_WWNN                   1
+#define	EXT_DEF_TYPE_WWPN                   2
+#define	EXT_DEF_TYPE_PORTID                 3
+#define	EXT_DEF_TYPE_FABRIC                 4
+
+
+/* Destination address */
+typedef struct _EXT_DEST_ADDR {
+	union {
+		UINT8    WWNN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+		UINT8    WWPN[EXT_DEF_WWN_NAME_SIZE];	/* 8 */
+		UINT8    Id[EXT_DEF_PORTID_SIZE];	/* 4 */
+		struct {
+			UINT16    Bus;			/* 2 */
+			UINT16    Target;		/* 2 */
+		} ScsiAddr;
+	} DestAddr;
+	UINT16    DestType;				/* 2 */
+	UINT16    Lun;					/* 2 */
+	UINT16    Padding[2];				/* 4 */
+} EXT_DEST_ADDR, *PEXT_DEST_ADDR;			/* 20 */
+
+
+#define	EXT_DEF_DESTTYPE_WWNN			1
+#define	EXT_DEF_DESTTYPE_WWPN			2
+#define	EXT_DEF_DESTTYPE_PORTID			3
+#define	EXT_DEF_DESTTYPE_FABRIC			4
+#define	EXT_DEF_DESTTYPE_SCSI			5
+
+/* Statistic */
+typedef struct _EXT_HBA_PORT_STAT {
+	UINT32    ControllerErrorCount;		/* 4 */
+	UINT32    DeviceErrorCount;		/* 4 */
+	UINT32    TotalIoCount;			/* 4 */
+	UINT32    TotalMBytes;			/* 4; MB of data processed */
+	UINT32    TotalLipResets;		/* 4; Total no. of LIP Reset */
+	UINT32    TotalInterrupts;		/* 4; Total no. of Interrupts */
+	UINT32    TotalLinkFailures;		/* 4 */
+	UINT32    TotalLossOfSync;		/* 4 */
+	UINT32    TotalLossOfSignals;		/* 4 */
+	UINT32    PrimitiveSeqProtocolErrorCount;/* 4 */
+	UINT32    InvalidTransmissionWordCount;	/* 4 */
+	UINT32    InvalidCRCCount;		/* 4 */
+	UINT32    Reserved[16];			/* 64 */
+} EXT_HBA_PORT_STAT, *PEXT_HBA_PORT_STAT;	/* 112 */
+
+
+/* Driver property */
+typedef struct _EXT_DRIVER {
+	UINT8     Version[EXT_DEF_MAX_STR_SIZE];/* 128 */
+	UINT16    NumOfBus;			/* 2; Port Type */
+	UINT16    TargetsPerBus;		/* 2; Port Status */
+	UINT16    LunsPerTarget;		/* 2 */
+	UINT32    MaxTransferLen;		/* 4 */
+	UINT32    MaxDataSegments;		/* 4 */
+	UINT16    DmaBitAddresses;		/* 2 */
+	UINT16    IoMapType;			/* 2 */
+	UINT32    Attrib;			/* 4 */
+	UINT32    InternalFlags[4];		/* 16 */
+	UINT32    Reserved[8];			/* 32 */
+} EXT_DRIVER, *PEXT_DRIVER;			/* 198 */
+
+
+/* Firmware property */
+typedef struct _EXT_FW {
+	UINT8     Version[EXT_DEF_MAX_STR_SIZE];/* 128 */
+	UINT32    Attrib;			/* 4 */
+	UINT16    Reserved[33];			/* 66 */
+} EXT_FW, *PEXT_FW;				/* 198 */
+
+
+/* ISP/Chip property */
+typedef struct _EXT_CHIP {
+	UINT16    VendorId;			/* 2 */
+	UINT16    DeviceId;			/* 2 */
+	UINT16    SubVendorId;			/* 2 */
+	UINT16    SubSystemId;			/* 2 */
+	UINT16    PciBusNumber;			/* 2 */
+	UINT16    PciSlotNumber;		/* 2 */
+	UINT32    IoAddr;			/* 4 */
+	UINT32    IoAddrLen;			/* 4 */
+	UINT32    MemAddr;			/* 4 */
+	UINT32    MemAddrLen;			/* 4 */
+	UINT16    ChipType;			/* 2 */
+	UINT16    InterruptLevel;		/* 2 */
+	UINT16    OutMbx[8];			/* 16 */
+	UINT32    Reserved[8];			/* 32 */
+} EXT_CHIP, *PEXT_CHIP;				/* 80 */
+
+
+/* Request Buffer for RNID */
+typedef struct _EXT_RNID_REQ {
+	EXT_FC_ADDR Addr;
+	UINT8       DataFormat;
+	UINT32      Reserved[16];	
+} EXT_RNID_REQ, *PEXT_RNID_REQ;	
+
+/* Request Buffer for Set RNID */
+typedef struct _EXT_SET_RNID_REQ {
+	UINT8     IPVersion[2];
+	UINT8     UDPPortNumber[2];
+	UINT8     IPAddress[16];
+	UINT32    Reserved[16];
+} EXT_SET_RNID_REQ, *PEXT_SET_RNID_REQ;
+
+/* RNID definition and data struct */
+#define	SEND_RNID_RSP_SIZE  72
+
+typedef struct _RNID_DATA
+{
+	UINT8     WWN[16];			/* 16 */
+	UINT32    UnitType;			/* 4 */
+	UINT8     PortId[4];			/* 4 */
+	UINT32    NumOfAttachedNodes;		/* 4 */
+	UINT8     IPVersion[2];			/* 2 */
+	UINT8     UDPPortNumber[2];		/* 2 */
+	UINT8     IPAddress[16];		/* 16 */
+	UINT16    Reserved;			/* 2 */
+	UINT16    TopoDiscFlags;		/* 2 */
+} EXT_RNID_DATA, *PEXT_RNID_DATA;		/* 52 */
+
+
+/* SCSI pass-through */
+typedef struct _EXT_SCSI_PASSTHRU {
+	EXT_SCSI_ADDR   TargetAddr;
+	UINT8           Direction;
+	UINT8           CdbLength;
+	UINT8           Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH];
+	UINT32          Reserved[16];
+	UINT8           SenseData[256];
+} EXT_SCSI_PASSTHRU, *PEXT_SCSI_PASSTHRU;
+
+/* FC SCSI pass-through */
+typedef struct _EXT_FC_SCSI_PASSTHRU {
+	EXT_DEST_ADDR   FCScsiAddr;
+	UINT8           Direction;
+	UINT8           CdbLength;
+	UINT8           Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH];
+	UINT32          Reserved[16];
+	UINT8           SenseData[256];
+} EXT_FC_SCSI_PASSTHRU, *PEXT_FC_SCSI_PASSTHRU;
+
+/* SCSI pass-through direction */
+#define	EXT_DEF_SCSI_PASSTHRU_DATA_IN		1
+#define	EXT_DEF_SCSI_PASSTHRU_DATA_OUT		2
+
+
+/* EXT_REG_AEN Request struct */
+typedef struct _EXT_REG_AEN {
+	UINT32    Enable;	/* 4; non-0 to enable, 0 to disable. */
+	UINT32    Reserved;	/* 4 */
+} EXT_REG_AEN, *PEXT_REG_AEN;	/* 8 */
+
+/* EXT_GET_AEN Response struct */
+typedef struct _EXT_ASYNC_EVENT {
+	UINT32	AsyncEventCode;		/* 4 */
+	union {
+		struct {
+			UINT8   RSCNInfo[EXT_DEF_PORTID_SIZE_ACTUAL];/* 3, BE */
+			UINT8   AddrFormat;			/* 1 */
+			UINT32  Rsvd_1[2];			/* 8 */
+		} RSCN;
+
+		UINT32  Reserved[3];	/* 12 */
+	} Payload;
+} EXT_ASYNC_EVENT, *PEXT_ASYNC_EVENT;	/* 16 */
+
+/* Asynchronous Event Codes */
+#define	EXT_DEF_LIP_OCCURRED		0x8010
+#define	EXT_DEF_LINK_UP			0x8011
+#define	EXT_DEF_LINK_DOWN		0x8012
+#define	EXT_DEF_LIP_RESET		0x8013
+#define	EXT_DEF_RSCN			0x8015
+#define	EXT_DEF_DEVICE_UPDATE		0x8014
+
+/* Required # of entries in the queue buffer allocated. */
+#define	EXT_DEF_MAX_AEN_QUEUE		EXT_DEF_MAX_AEN_QUEUE_OS
+
+/* LUN BitMask structure definition, array of 32bit words,
+ * 1 bit per lun.  When bit == 1, the lun is masked.
+ * Most significant bit of mask[0] is lun 0, bit 24 is lun 7.
+ */
+typedef struct _EXT_LUN_BIT_MASK {
+#if ((EXT_MAX_LUN & 0x7) == 0)
+	UINT8	mask[EXT_DEF_MAX_LUN >> 3];
+#else
+	UINT8	mask[(EXT_DEF_MAX_LUN + 8) >> 3 ];
+#endif
+} EXT_LUN_BIT_MASK, *PEXT_LUN_BIT_MASK;
+
+/* Device type to get for EXT_SC_GET_PORT_SUMMARY */
+#define	EXT_DEF_GET_KNOWN_DEVICE	0x1
+#define	EXT_DEF_GET_VISIBLE_DEVICE	0x2
+#define	EXT_DEF_GET_HIDDEN_DEVICE	0x4
+#define	EXT_DEF_GET_FABRIC_DEVICE	0x8
+#define	EXT_DEF_GET_LOOP_DEVICE		0x10
+
+/* Each entry in device database */
+typedef struct _EXT_DEVICEDATAENTRY
+{
+	UINT8		NodeWWN[8];	/* Node World Wide Name for device */
+	UINT8		PortWWN[8];	/* Port World Wide Name for device */
+	UINT8		PortID[3];	/* Current PortId for device */
+	UINT8		ControlFlags;	/* Control flag */
+	EXT_SCSI_ADDR	TargetAddress;	/* scsi address */
+	UINT32		DeviceFlags;	/* Flags for device */
+	UINT16		LoopID;		/* Loop ID */
+	UINT16		BaseLunNumber;  
+	UINT32		Reserved[32];
+} EXT_DEVICEDATAENTRY, *PEXT_DEVICEDATAENTRY;
+
+#define	EXT_DEF_EXTERNAL_LUN_COUNT          2048
+#define	EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES  (EXT_DEF_EXTERNAL_LUN_COUNT / 8)
+
+/* Structure as used in the IOCTL. */
+
+typedef struct _EXT_EXTERNAL_LUN_BITMASK_ENTRY
+{
+	UINT8	NodeName[EXT_DEF_WWN_NAME_SIZE];
+	UINT8	PortName[EXT_DEF_WWN_NAME_SIZE];
+
+	UINT32	Reserved2;
+	UINT32	Reserved3;
+	UINT32	Reserved4;
+	UINT32	Reserved5;     /* Pad to 32-byte header.*/
+
+	UINT8	Bitmask[EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES];
+} EXT_EXTERNAL_LUN_BITMASK_ENTRY, *PEXT_EXTERNAL_LUN_BITMASK_ENTRY;
+
+
+/* Structure as it is stored in the NT registry.*/
+
+typedef struct _LUN_BITMASK_LIST
+{
+	UINT16	Version;       /* Should be LUN_BITMASK_REGISTRY_VERSION */
+	UINT16	EntryCount;    /* Count of variable entries following.*/
+	UINT32	Reserved1;
+	UINT32	Reserved2;
+	UINT32	Reserved3;
+	UINT32	Reserved4;
+	UINT32	Reserved5;
+	UINT32	Reserved6;
+	UINT32	Reserved7;     /* Pad to 32-byte header.*/
+
+	EXT_EXTERNAL_LUN_BITMASK_ENTRY BitmaskEntry[1];
+		               /* Variable-length data.*/
+
+} EXT_LUN_BITMASK_LIST, *PEXT_LUN_BITMASK_LIST;
+
+
+/* Device database information */
+typedef struct _EXT_DEVICEDATA
+{
+	UINT32	TotalDevices;          /* Set to total number of device. */
+	UINT32	ReturnListEntryCount;  /* Set to number of device entries */
+		                       /* returned in list. */
+
+	EXT_DEVICEDATAENTRY  EntryList[1]; /* Variable length */
+} EXT_DEVICEDATA, *PEXT_DEVICEDATA;
+
+
+/* Swap Target Device Data structure */
+typedef struct _EXT_SWAPTARGETDEVICE
+{
+	EXT_DEVICEDATAENTRY CurrentExistDevice;
+	EXT_DEVICEDATAENTRY NewDevice;
+} EXT_SWAPTARGETDEVICE, *PEXT_SWAPTARGETDEVICE;
+
+#define	EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES	1
+#define	EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES	256
+
+#ifdef _WIN64
+#define	EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE	32
+#else
+#define	EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE \
+    offsetof(LUN_BITMASK_LIST_BUFFER, asBitmaskEntry)
+#endif
+
+#define	EXT_DEF_LUN_BITMASK_LIST_MIN_SIZE   \
+    (EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE + \
+    (sizeof(EXT_EXTERNAL_LUN_BITMASK_ENTRY) * EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES))
+#define	EXT_LUN_BITMASK_LIST_MAX_SIZE   \
+    (EXT_LUN_BITMASK_LIST_HEADER_SIZE + \
+    (sizeof(EXT_EXTERNAL_LUN_BITMASK_ENTRY) * EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES))
+/*
+ * LUN mask bit manipulation macros
+ *
+ *   P = Pointer to an EXT_LUN_BIT_MASK union.
+ *   L = LUN number.
+ */
+#define EXT_IS_LUN_BIT_SET(P,L) \
+    ((P->mask[L/8] & (0x80 >> (L%8)))?1:0)
+
+#define EXT_SET_LUN_BIT(P,L) \
+    (P->mask[L/8] |= (0x80 >> (L%8)))
+
+#define EXT_CLR_LUN_BIT(P,L) \
+    (P->mask[L/8] &= ~(0x80 >> (L%8)))
+
+
+
+#ifdef _MSC_VER
+#pragma pack()
+#endif
+
+#endif /* _EXIOCT_H */
diff -urN linux-2.4.16/drivers/scsi/qla2x00exioctln.h lia64-2.4/drivers/scsi/qla2x00exioctln.h
--- linux-2.4.16/drivers/scsi/qla2x00exioctln.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qla2x00exioctln.h	Mon Jul 23 14:12:47 2001
@@ -0,0 +1,131 @@
+/*****************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic ISP2x00 device driver for Linux 2.2.x and 2.4.x 
+* Copyright (C) 2000 Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+****************************************************************************/
+
+/* 
+   Rev 8     Jan 08, 2001   BN
+             - Added LOOP_BACK ioctl define
+
+   Rev 7     Nov 06, 2000   BN
+             - Added EXT_DEF_MAX_AEN_QUEUE_OS define
+             - Added define for handle_hba_t
+
+   Rev 6     Oct 25, 2000   BN
+             - Added EXT_CC_DRIVER_PROP_OS define
+
+   Rev 5     Oct 25, 2000   BN
+             - Redo the copyright header and add AEN details
+
+   Rev 4     Oct 23, 2000   BN
+             - Added definition for BOOLEAN
+
+   Rev 3     Oct 23, 2000
+             BN
+             - Added definitions for EXT_ADDR_MODE_OS
+               and also include of <linux/ioctl.h>
+
+   Rev 2     Oct 18, 2000
+             BN
+             - Enable API Exention support
+
+   Rev 1     Original version Sep 7, 2000 
+             BN
+
+
+
+*/
+
+#include <linux/ioctl.h>
+
+#if BITS_PER_LONG <= 32
+#define EXT_ADDR_MODE_OS  EXT_DEF_ADDR_MODE_32
+#else
+#define EXT_ADDR_MODE_OS  EXT_DEF_ADDR_MODE_64
+#endif
+
+#define	UINT8	uint8_t
+#define	UINT16	uint16_t
+#define	UINT32	uint32_t
+#define	UINT64	void *
+#define BOOLEAN uint8_t
+
+#define uint8_t  unsigned char
+#define uint16_t unsigned short
+#define uint32_t unsigned int
+
+#if BITS_PER_LONG > 32
+#define uint64_t unsigned long
+#else
+#define uint64_t unsigned long long
+#endif
+
+typedef struct  track_instance
+{
+
+  int   handle;
+
+} track_instance_t;
+
+
+#define	EXT_DEF_MAX_HBA_OS		256	/* 0 - 0xFF */
+#define	EXT_DEF_MAX_BUS_OS		1
+#define	EXT_DEF_MAX_TARGET_OS		256	/* 0 - 0xFF */
+#define	EXT_DEF_MAX_LUN_OS		256	/* 0 - 0xFF */
+
+#define EXT_DEF_MAX_AEN_QUEUE_OS        64
+
+#define QLMULTIPATH_MAGIC 'y'
+#define _QLBUILD   /* for exioct.h to enable include of qinsdmgt.h */
+
+#define EXT_CC_STARTIOCTL   _IOWR(QLMULTIPATH_MAGIC, 0 , sizeof(EXT_IOCTL))
+#define EXT_CC_SETINSTANCE  _IOWR(QLMULTIPATH_MAGIC, 1 , sizeof(EXT_IOCTL))
+
+#define EXT_CC_QUERY_OS  _IOWR(QLMULTIPATH_MAGIC, 2 , sizeof(EXT_IOCTL))
+#define EXT_CC_SEND_FCCT_PASSTHRU_OS _IOWR(QLMULTIPATH_MAGIC, 3 , sizeof(EXT_IOCTL))
+#define EXT_CC_READ_NVRAM_OS _IOWR(QLMULTIPATH_MAGIC, 4 , sizeof(EXT_IOCTL))
+#define EXT_CC_SCSI_PASSTHRU_OS _IOWR(QLMULTIPATH_MAGIC, 5 , sizeof(EXT_IOCTL))
+#define EXT_CC_STOP_QCMD     _IOWR(QLMULTIPATH_MAGIC, 6 , sizeof(EXT_IOCTL))
+#define EXT_CC_RESUME_QCMD   _IOWR(QLMULTIPATH_MAGIC, 7 , sizeof(EXT_IOCTL))
+#define EXT_CC_GET_DATA_OS   _IOWR(QLMULTIPATH_MAGIC, 8 , sizeof(EXT_IOCTL))
+#define	EXT_CC_WWPN_TO_SCSIADDR _IOWR(QLMULTIPATH_MAGIC, 9 , sizeof(EXT_IOCTL))
+#define	EXT_CC_REG_AEN_OS  _IOWR(QLMULTIPATH_MAGIC, 10 , sizeof(EXT_IOCTL))
+#define	EXT_CC_GET_AEN_OS  _IOWR(QLMULTIPATH_MAGIC, 11 , sizeof(EXT_IOCTL))
+
+#define	EXT_CC_DRIVER_PROP_OS  _IOWR(QLMULTIPATH_MAGIC, 12 , sizeof(EXT_IOCTL))
+
+#define EXT_CC_LOOPBACK_OS   _IOWR(QLMULTIPATH_MAGIC, 20 , sizeof(EXT_IOCTL))
+
+
+
+/*
+ * Overrides for Emacs so that we almost follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-indent-level: 2
+ * c-brace-imaginary-offset: 0
+ * c-brace-offset: -2
+ * c-argdecl-indent: 2
+ * c-label-offset: -2
+ * c-continued-statement-offset: 2
+ * c-continued-brace-offset: 0
+ * indent-tabs-mode: nil
+ * tab-width: 8
+ * End:
+ */
diff -urN linux-2.4.16/drivers/scsi/qla2x00ioctl.c lia64-2.4/drivers/scsi/qla2x00ioctl.c
--- linux-2.4.16/drivers/scsi/qla2x00ioctl.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qla2x00ioctl.c	Mon Jul 23 14:12:54 2001
@@ -0,0 +1,1179 @@
+/********************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic QLA2x00 device driver for Linux 2.2.x and 2.4.x 
+* Copyright (C) 2000 Qlogic Corporation 
+* (www.qlogic.com)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2, or (at your option) any
+* later version.
+*
+* This program is distributed in the hope that it will be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+* General Public License for more details.
+**
+******************************************************************************/
+/****************************************************************************
+Revision History:
+    Rev. 1.3 Beta       February 20, 2001   BN QLogic
+        - Zero the sp used for IOCTL SCSI Passthru operations
+    Rev. 1.2 Beta       January 31, 2001   BN QLogic
+        - Added setting of scsi completion to pext->DetailStatus
+          and set pext->Status to EXT_STATUS_SCSI_STATUS.
+        - Added details to Statistics IOCTL for ispaborts,
+          lip_count, isr_count.
+
+    Rev. 1.2 Beta       January 8, 2001    BN QLogic
+        - Added loop-back diagnostic IOCTL support.
+
+    Rev. 1.1 Beta       October 27, 2000    BN QLogic
+        - Updated return status from ioctl function.
+
+    Rev. 1.0 Beta       October 20, 2000    BN QLogic
+        - Initial version check in
+  
+
+*/
+
+void copy_up_EXT( PEXT_IOCTL pext, void *arg) {
+uint32_t i;
+uint8_t  *usr_temp, *kernel_tmp;
+
+  /* copy up the EXT_IOCTL to application (api library) */
+  for (i=0 ; i < sizeof(EXT_IOCTL) ; i++) {
+    usr_temp   = (uint8_t *)arg + i;
+    kernel_tmp = (uint8_t *)pext + i;
+    __put_user(*kernel_tmp, usr_temp);
+  }
+  
+  return;
+}
+
+
+/*************************************************************************
+ *   ioctl_scsi_pt_done
+ *
+ * Description:
+ *   Sets completion flag.
+ *
+ * Returns:
+ *************************************************************************/
+void  ioctl_scsi_pt_done(Scsi_Cmnd *pscsi_cmd) {
+  struct Scsi_Host *host;
+  scsi_qla_host_t  *ha;
+
+      host = pscsi_cmd->host;
+      ha = (scsi_qla_host_t *) host->hostdata; 
+
+      ha->IoctlPassThru_InProgress = 0;
+      return;
+}
+
+
+/*************************************************************************
+ *   ioctl_fcct_done
+ *
+ * Description:
+ *   Sets completion flag.
+ *
+ * Returns:
+ *************************************************************************/
+void  ioctl_fcct_done(Scsi_Cmnd *pscsi_cmd) {
+  struct Scsi_Host *host;
+  scsi_qla_host_t  *ha;
+
+      host = pscsi_cmd->host;
+      ha = (scsi_qla_host_t *) host->hostdata; 
+      /* printk("ioctl_fcct_done post function called OK\n"); */
+      DEBUG(sprintf(debug_buff,"ioctl_fcct_done post function called OK\n"));
+      DEBUG(qla2100_print(debug_buff));
+      ha->IoctlPassFCCT_InProgress = 0;
+      return;
+}
+
+
+/*************************************************************************
+ *   qla2100_ioctl
+ *
+ * Description:
+ *   Performs ioctl requests not satified by the upper levels.
+ *
+ * Returns:
+ *   ret  = 0    Success
+ *   ret != 0    Failed; detailed status copied to EXT_IOCTL structure
+ *               if applicable     
+ *************************************************************************/
+int
+qla2100_ioctl(Scsi_Device *dev, int cmd, void *arg){
+
+  static  EXT_IOCTL    ext;
+  PEXT_IOCTL   pext = &ext;
+  struct Scsi_Host   *host;
+  scsi_qla_host_t  *ha, *search_ha; 
+  scsi_lu_t        *q;
+#if BITS_PER_LONG <= 32
+  uint32_t    handle;
+#else
+  uint64_t    handle;
+#endif
+  uint32_t    cnt, i, b, t, l, port_cnt, status;
+  uint32_t    tgt_cnt, tgt, transfer_size, inst;
+  uint8_t     *extptr, *usrsrc, *usr_temp, *kernel_tmp, *kernel_tmp1;
+  static Scsi_Cmnd          scsi_cmd;
+  Scsi_Cmnd   *pscsi_cmd = &scsi_cmd;
+  static Scsi_Device scsi_device;
+  static srb_t             ioctl_sp;
+  srb_t             *sp = &ioctl_sp;
+  static         EXT_SCSI_PASSTHRU   scsi_pass;
+  EXT_SCSI_PASSTHRU   *pscsi_pass = &scsi_pass;
+  static EXT_HBA_NODE      tmp_hba_node;
+  static EXT_HBA_PORT      tmp_hba_port;
+  static EXT_DISC_PORT     tmp_disc_port;
+  static EXT_DISC_TARGET   tmp_disc_target;
+  static EXT_CHIP          tmp_isp;
+  static EXT_HBA_PORT_STAT tmp_stat;
+  uint16_t    mb[MAILBOX_REGISTER_COUNT];
+  unsigned long cpu_flags = 0;
+  uint16_t       scratch;
+  uint16_t       *wptr = &scratch;
+  qla_boards_t   *bdp;
+  uint8_t *temp;
+  uint8_t tempbuf[8];
+  cmd_ms_iocb_entry_t  *pkt;
+ 
+  int  ret = EINVAL;  
+ 
+  BZERO((caddr_t)sp,sizeof(srb_t));
+
+  host = dev->host;
+  ha = (scsi_qla_host_t *) host->hostdata; /* midlayer chosen instance */
+
+  ret = verify_area(VERIFY_READ, (void *)arg, sizeof(EXT_IOCTL)); 
+  if (ret) {
+    DEBUG2(printk("[qla2100_ioctl: ERROR in verify_area READ ha=%8x]\n",(uint32_t)ha);)
+    return(ret);
+  }
+  /* copy in application layer EXT_IOCTL */
+  for (i=0 ; i < sizeof(EXT_IOCTL) ; i++) {
+    usrsrc = (uint8_t *)(arg + i);
+    extptr = (uint8_t *)pext + i;
+    __get_user(*extptr, usrsrc);
+  }
+
+  /* printk("[GOT QLA2100 IOCTL sig=%s cmd=%x]\n",
+     (char *)&pext->Signature,cmd); */
+
+  /* check signature of this ioctl */
+  temp = (uint8_t *) &pext->Signature;
+#if BITS_PER_LONG <= 32
+for (i=0 ; i<4 ; i++,temp++) tempbuf[i] = *temp;
+  if( (tempbuf[0] == 'Q') && (tempbuf[1] == 'L') && 
+      (tempbuf[2] == 'O') && (tempbuf[3] == 'G')) status = 0;
+  else status = 1;
+#else
+  if( (tempbuf[0] == 'Q') && (tempbuf[1] == 'L') && 
+      (tempbuf[2] == 'O') && (tempbuf[3] == 'G') &&
+      (tempbuf[4] == 'I') && (tempbuf[5] == 'C')) status = 0;
+      else status = 1; 
+#endif 
+  if ( status != 0) {
+    DEBUG2(printk("[GOT QLA2100 IOCTL but signature did not match ha=%8x]\n",
+          (uint32_t)ha);)
+    ret = EXT_STATUS_ERR;
+    return(ret);
+  }
+  /* check version of this ioctl */
+  if (pext->Version  !=  EXT_VERSION) {
+    pext->Status       = EXT_STATUS_ERR;
+    pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+    copy_up_EXT(pext,arg);
+    printk(KERN_WARNING "qla2x00: GOT QLA2100 IOCTL but version did not match.\n");
+    ret = EXT_STATUS_ERR;
+    return(ret);
+  }
+  /* check for API setting HBA Instance for subsequent operations */
+  if (cmd == (int)EXT_CC_SETINSTANCE) {
+      /* since API opens devices once and uses handle for subsequent calls */
+      /* we keep a parameter to designate the "active HBA" for ioctls */
+      if (pext->HbaSelect < num_hosts) {
+         apiHBAInstance     = pext->HbaSelect;
+         pext->Status       = EXT_STATUS_OK;
+         pext->DetailStatus = EXT_STATUS_OK;
+         copy_up_EXT(pext,arg);
+         ret = EXT_STATUS_OK;
+      } else {
+         pext->Status       = EXT_STATUS_ERR;
+         pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+         copy_up_EXT(pext,arg);
+         DEBUG2(printk("[qla2100_ioctl: ERROR in EXT_SETINSTANCE ha=%8x]\n",(uint32_t)ha);)
+         ret = EXT_STATUS_ERR;
+      }
+      return(ret); /* Instance for subsequent IOCTLs are not set */
+  }
+
+  /* check for valid  apiHBAInstance (set previously by EXT_SETINSTANCE 
+     or default 0)  and set   ha   context for this IOCTL */    
+  for (search_ha=qla2100_hostlist; 
+      (search_ha != NULL) && search_ha->instance != apiHBAInstance;
+       search_ha = search_ha->next) ;
+  if ( !search_ha ) { 
+     pext->Status       = EXT_STATUS_ERR;
+     pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+     copy_up_EXT(pext,arg);
+     DEBUG2(printk("[qla2100_ioctl: ERROR in matching apiHBAInstance to an HBA Instance]\n");)
+     ret = EXT_STATUS_ERR;
+     return(ret);
+  }
+  /* IOCTL ha context is ready to be set from apiHBAInstance */
+  ha = search_ha;
+  /* set EXT_IOCTL.HbaSelect  for reference by IOCTL caller */
+  pext->HbaSelect = apiHBAInstance;
+
+  switch (cmd) { /* switch on EXT IOCTL COMMAND CODE */
+    case EXT_CC_STARTIOCTL:
+      pext->Instance     = num_hosts;
+      pext->Status       = EXT_STATUS_OK;
+      pext->DetailStatus = EXT_STATUS_OK;
+      copy_up_EXT(pext,arg);
+      /*printk("[QLA2100 EXT_STARTIOCTL did OK ]\n");*/ 
+      ret = EXT_STATUS_OK;
+      break;
+    case EXT_CC_QUERY:
+      /* All Query type ioctls are done here */
+      switch(pext->SubCode) {
+        case EXT_SC_QUERY_HBA_NODE:
+        /* fill all available HBA NODE Information */
+          bdp = &QLBoardTbl_fc[ha->devnum];
+          for (i=0; i < 8 ;i++)   tmp_hba_node.WWNN[i] = ha->node_name[i];
+          sprintf((char *)(tmp_hba_node.Manufacturer),"Qlogic Corp.");
+          sprintf((char *)(tmp_hba_node.Model),(char *)&bdp->bdName[0]);
+          tmp_hba_node.SerialNum[0] = ha->node_name[5];
+          tmp_hba_node.SerialNum[1] = ha->node_name[6];
+          tmp_hba_node.SerialNum[2] = ha->node_name[7];
+          sprintf((char *)(tmp_hba_node.DriverVersion),QLA2100_VERSION);
+          sprintf((char *)(tmp_hba_node.FWVersion),"%2d.%02d.%02d",
+                  bdp->fwver[0], bdp->fwver[1], bdp->fwver[2]);
+          /* tmp_hba_node.NvramVersion = ha->nvram_version; */  
+          sprintf((char *)(tmp_hba_node.OptRomVersion),"0");
+          tmp_hba_node.InterfaceType = EXT_DEF_FC_INTF_TYPE;
+          tmp_hba_node.PortCount = 1;
+          
+          ret = verify_area(VERIFY_WRITE, (void  *)pext->ResponseAdr,
+                sizeof(EXT_HBA_NODE)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+          /* now copy up the HBA_NODE to user */
+          if (pext->ResponseLen < sizeof(EXT_HBA_NODE)) transfer_size = pext->ResponseLen;
+          else       transfer_size = sizeof(EXT_HBA_NODE);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_hba_node + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /*printk("[finished QLA2100 IOCTL QUERY_HBA_NODE ]\n"); */
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        case EXT_SC_QUERY_HBA_PORT:
+          /* reflect all HBA PORT related info */
+          tmp_hba_port.WWPN[7] = ha->init_cb->port_name[7];  
+          tmp_hba_port.WWPN[6] = ha->init_cb->port_name[6];
+          tmp_hba_port.WWPN[5] = ha->init_cb->port_name[5];
+          tmp_hba_port.WWPN[4] = ha->init_cb->port_name[4];
+          tmp_hba_port.WWPN[3] = ha->init_cb->port_name[3];
+          tmp_hba_port.WWPN[2] = ha->init_cb->port_name[2];
+          tmp_hba_port.WWPN[1] = ha->init_cb->port_name[1];
+	  tmp_hba_port.WWPN[0] = ha->init_cb->port_name[0];
+          tmp_hba_port.Id[1] = ha->port_id[0];
+          tmp_hba_port.Id[2] = ha->port_id[1];
+          tmp_hba_port.Id[3] = ha->port_id[2];
+          tmp_hba_port.Type =  EXT_DEF_INITIATOR_DEV;
+
+          port_cnt = 0; 
+          tgt_cnt  = 0;
+          for (tgt = 0; tgt < MAX_FIBRE_DEVICES ; tgt++) {
+          if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID) 
+               continue;
+            port_cnt++;
+
+          /* at this point the linux driver does not differentiate */
+          /* Initiator devices (ie HBAs) from Targets; so the count */
+          /* is same for both */
+          /*      if (ha->fc_db[tgt] & FC_INITIATOR_DEVICE) 
+                  continue;  */
+            tgt_cnt++;
+          }
+          tmp_hba_port.DiscPortCount   = port_cnt;
+          tmp_hba_port.DiscTargetCount = tgt_cnt;
+
+          if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN) {
+                  tmp_hba_port.State    = EXT_DEF_HBA_LOOP_DOWN;
+          } else  tmp_hba_port.State    = EXT_DEF_HBA_OK;
+          tmp_hba_port.DiscPortNameType = EXT_DEF_USE_PORT_NAME;
+
+          ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                sizeof(EXT_HBA_PORT)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+          /* now copy up the HBA_PORT to user */
+          if (pext->ResponseLen < sizeof(EXT_HBA_PORT)) transfer_size = pext->ResponseLen;
+          else         transfer_size = sizeof(EXT_HBA_PORT);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_hba_port + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /*printk("[finished QLA2100 IOCTL QUERY_HBA_PORT ports=%x tgts=%x]\n",port_cnt,tgt_cnt); */
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        case EXT_SC_QUERY_DISC_PORT:
+          for (tgt=0, inst=0; tgt < MAX_FIBRE_DEVICES; tgt++) {
+            if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID)
+               continue; 
+            if( inst != pext->Instance ) {
+              inst++;
+              continue;
+            }
+            break;
+          }
+          if (tgt == MAX_FIBRE_DEVICES) {
+            pext->Status       = ret = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+            copy_up_EXT(pext,arg);
+            return(ret); 
+          }
+
+            tmp_disc_port.WWNN[0] = ha->fc_db[tgt].name[0];
+            tmp_disc_port.WWNN[1] = ha->fc_db[tgt].name[1];
+            tmp_disc_port.WWNN[2] = ha->fc_db[tgt].name[2];
+            tmp_disc_port.WWNN[3] = ha->fc_db[tgt].name[3];
+
+            tmp_disc_port.WWNN[4] = ha->fc_db[tgt].name[4];
+            tmp_disc_port.WWNN[5] = ha->fc_db[tgt].name[5];
+            tmp_disc_port.WWNN[6] = ha->fc_db[tgt].name[6];
+            tmp_disc_port.WWNN[7] = ha->fc_db[tgt].name[7];
+
+            tmp_disc_port.WWPN[0] = ha->fc_db[tgt].wwn[0];
+            tmp_disc_port.WWPN[1] = ha->fc_db[tgt].wwn[1];
+            tmp_disc_port.WWPN[2] = ha->fc_db[tgt].wwn[2];
+            tmp_disc_port.WWPN[3] = ha->fc_db[tgt].wwn[3];
+
+            tmp_disc_port.WWPN[4] = ha->fc_db[tgt].wwn[4];
+            tmp_disc_port.WWPN[5] = ha->fc_db[tgt].wwn[5];
+            tmp_disc_port.WWPN[6] = ha->fc_db[tgt].wwn[6];
+            tmp_disc_port.WWPN[7] = ha->fc_db[tgt].wwn[7];
+
+          tmp_disc_port.Id[1] = ha->fc_db[tgt].port_id[0];
+          tmp_disc_port.Id[2] = ha->fc_db[tgt].port_id[1];
+          tmp_disc_port.Id[3] = ha->fc_db[tgt].port_id[2];
+          tmp_disc_port.Type  = EXT_DEF_TARGET_DEV;
+
+          tmp_disc_port.Status   = EXT_STATUS_OK;
+          tmp_disc_port.Bus      = 0;
+          tmp_disc_port.TargetId = tgt;
+ 
+          ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                sizeof(EXT_DISC_PORT)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+
+          /* now copy up the DISC_PORT to user */
+          if (pext->ResponseLen < sizeof(EXT_DISC_PORT)) transfer_size = pext->ResponseLen;
+          else        transfer_size = sizeof(EXT_DISC_PORT);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_disc_port + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /*printk("[finished QLA2100 IOCTL QUERY_DISC_PORT ]\n"); */
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        case EXT_SC_QUERY_DISC_TGT:
+	  /* (for multipath merge) to do: search the ha->tgt[][] data base 
+             instead of ha->fc_db[] so that we give details on Targets that
+             are visible to the OS. */
+          for (tgt=0, inst=0; tgt < MAX_FIBRE_DEVICES; tgt++) {
+            if (ha->fc_db[tgt].loop_id > LAST_SNS_LOOP_ID)
+               continue; 
+            if( inst != pext->Instance ) {
+              inst++;
+              continue;
+            }
+            break;
+          }
+          if (tgt == MAX_FIBRE_DEVICES) {
+            pext->Status       = ret = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+            copy_up_EXT(pext,arg);
+            return(ret); 
+          }
+            tmp_disc_target.WWNN[0]= ha->fc_db[tgt].name[0];
+            tmp_disc_target.WWNN[1]= ha->fc_db[tgt].name[1];
+            tmp_disc_target.WWNN[2]= ha->fc_db[tgt].name[2];
+            tmp_disc_target.WWNN[3]= ha->fc_db[tgt].name[3];
+
+            tmp_disc_target.WWNN[4]= ha->fc_db[tgt].name[4];
+            tmp_disc_target.WWNN[5]= ha->fc_db[tgt].name[5];
+            tmp_disc_target.WWNN[6]= ha->fc_db[tgt].name[6];
+            tmp_disc_target.WWNN[7]= ha->fc_db[tgt].name[7];
+
+
+            tmp_disc_target.WWPN[0]= ha->fc_db[tgt].wwn[0];
+            tmp_disc_target.WWPN[1]= ha->fc_db[tgt].wwn[1];
+            tmp_disc_target.WWPN[2]= ha->fc_db[tgt].wwn[2];
+            tmp_disc_target.WWPN[3]= ha->fc_db[tgt].wwn[3];
+
+            tmp_disc_target.WWPN[4]= ha->fc_db[tgt].wwn[4];
+            tmp_disc_target.WWPN[5]= ha->fc_db[tgt].wwn[5];
+            tmp_disc_target.WWPN[6]= ha->fc_db[tgt].wwn[6];
+            tmp_disc_target.WWPN[7]= ha->fc_db[tgt].wwn[7];
+            tmp_disc_target.Id[1] = ha->fc_db[tgt].port_id[0];
+            tmp_disc_target.Id[2] = ha->fc_db[tgt].port_id[1];
+            tmp_disc_target.Id[3] = ha->fc_db[tgt].port_id[2];
+            tmp_disc_target.Type  = EXT_DEF_TARGET_DEV;
+
+          tmp_disc_target.Status   = EXT_STATUS_OK;
+          tmp_disc_target.Bus      = 0;
+          tmp_disc_target.TargetId = tgt;
+ 
+          cnt = 0;
+          for (i=0; i < MAX_LUNS ; i++) {
+          if ((ha->tgt[0][tgt])->luns[i] !=0) 
+              cnt++;
+          }
+          tmp_disc_target.LunCount = cnt;
+
+          ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                sizeof(EXT_DISC_TARGET)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+          /* now copy up the DISC_TGT to user */
+          if (pext->ResponseLen < sizeof(EXT_DISC_PORT)) transfer_size = pext->ResponseLen;
+          else     transfer_size = sizeof(EXT_DISC_TARGET);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_disc_target + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /* printk("[finished QLA2100 IOCTL QUERY_DISC_TGT Luns=%x pid0=%x pid1=%x pid2=%x]\n",cnt,ha->fc_db[tgt].port_id[0],ha->fc_db[tgt].port_id[1],ha->fc_db[tgt].port_id[2]);*/
+ 
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        case EXT_SC_QUERY_CHIP:
+          host = ha->host;
+	  tmp_isp.VendorId       = QLA2100_VENDOR_ID;
+	  tmp_isp.DeviceId       = ha->device_id;
+	  tmp_isp.SubVendorId    = QLA2100_VENDOR_ID;
+          tmp_isp.SubSystemId    = 0;	
+	  tmp_isp.PciBusNumber   = ha->pci_bus;	
+	  tmp_isp.PciSlotNumber  = (ha->pci_device_fn & 0xf8) >> 3;
+	  tmp_isp.IoAddr         = host->io_port;	
+	  tmp_isp.IoAddrLen      = 512;	
+          tmp_isp.MemAddr        = 0; 
+          tmp_isp.MemAddrLen     = 0; 	
+          tmp_isp.ChipType       = 0; 	
+          tmp_isp.InterruptLevel = host->irq;
+          for (i=0;i<8;i++)      tmp_isp.OutMbx[i] = 0;		
+
+          ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                sizeof(EXT_CHIP)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+          /* now copy up the ISP to user */
+          if (pext->ResponseLen < sizeof(EXT_CHIP)) transfer_size = pext->ResponseLen;
+          else         transfer_size = sizeof(EXT_CHIP);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_isp + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /* printk("[finished QLA2100 IOCTL QUERY_CHIP]\n"); */ 
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+
+        case EXT_SC_QUERY_DISC_LUN:
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        default:
+          ret = EXT_STATUS_ERR;
+          break;
+      }
+      break;
+    case EXT_CC_GET_DATA:
+      switch(pext->SubCode) {
+        case EXT_SC_GET_STATISTICS:
+
+  	  tmp_stat.ControllerErrorCount   =  ha->isp_aborts;
+	  tmp_stat.DeviceErrorCount       =  0;
+	  tmp_stat.TotalIoCount           =  ha->qthreads;
+	  tmp_stat.TotalMBytes            =  0;
+	  tmp_stat.TotalLipResets         =  ha->lip_count;
+	  tmp_stat.TotalInterrupts        =  ha->isr_count;
+
+          ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr,
+                sizeof(EXT_HBA_PORT_STAT)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE ha=%8x]\n",(uint32_t)ha);)
+            return(ret);
+          }
+          /* now copy up the STATISTICS to user */
+          if (pext->ResponseLen < sizeof(EXT_HBA_PORT_STAT)) transfer_size = pext->ResponseLen;
+          else       transfer_size = sizeof(EXT_HBA_PORT_STAT);
+          for (i=0 ; i < transfer_size ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)&tmp_stat + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /*printk("[finished QLA2100 IOCTL STATISTICS ]\n");*/ 
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+          break;
+        default:
+          break;
+      }
+      break;
+    case EXT_CC_SEND_FCCT_PASSTHRU:
+    DEBUG(sprintf(debug_buff,"qla2100_ioctl: start EXT_CC_SEND_FCCT_PASSTHRU\n"));
+    DEBUG(qla2100_print(debug_buff));
+    /* Management Server type (fc switch) pass thru ioctl */
+    /* same as EXT_FCSCSI_REQ but it is going to the FC switch */
+    /* clear ioctl_sp and scsi_cmd to be used */
+    kernel_tmp = (uint8_t *)sp;
+    for (i=0;i<sizeof(srb_t);i++)  *(kernel_tmp+i) = 0; 
+    kernel_tmp = (uint8_t *)ha->ioctl_mem;
+    for (i=0;i<PAGE_SIZE;i++)      *(kernel_tmp+i) = 0; 
+    kernel_tmp = (uint8_t *)pscsi_cmd;
+    for (i=0;i<sizeof(Scsi_Cmnd);i++)   *(kernel_tmp+i) = 0; 
+    kernel_tmp = (uint8_t *)&scsi_device;
+    for (i=0;i<sizeof(Scsi_Device);i++) *(kernel_tmp+i) = 0; 
+
+      /*printk("[start EXT_CC_SEND_FCCT_PASSTHRU]\n"); */
+      if (pext->ResponseLen > PAGE_SIZE)  pext->ResponseLen = PAGE_SIZE;
+      if (pext->RequestLen  > PAGE_SIZE)  {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+        copy_up_EXT(pext,arg);
+        /*printk("[EXT_CC_SEND_FCCT_PASSTHRU too big ResponseLen=%x ReqLen=%x]\n",pext->ResponseLen,pext->RequestLen); */
+        DEBUG2(printk("[qla2100_ioctl: ERROR size of requested Resp_len in EXT_CC_SEND_FCCT_PASSTHRU]\n");)
+        return(ret);
+      }
+      ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr,
+                        pext->RequestLen); 
+      if (ret){
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_COPY_ERR;
+        copy_up_EXT(pext,arg);
+        /*printk("[EXT_CC_SEND_FCCT_PASSTHRU verify read error]\n");*/ 
+        DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_CC_SEND_FCCT_PASSTHRU]\n");)
+        return(ret);
+      }
+      for (i=0 ; i < pext->RequestLen ; i++) {
+        /* copy in from user space the fcct command to be sent */
+        usr_temp   = (uint8_t *)pext->RequestAdr + i;
+        kernel_tmp = (uint8_t *)ha->ioctl_mem + i;
+        __get_user(*kernel_tmp, usr_temp);
+        /* printk("{%x}",*kernel_tmp); */
+      }
+      /* check on current topology or loop down */
+      if ((ha->current_topology != ISP_CFG_F)  && 
+          (ha->current_topology != ISP_CFG_FL ) ) {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+        copy_up_EXT(pext,arg);
+        /*printk("[EXT_CC_SEND_FCCT_PASSTHRU wrong topology current=%x]\n",
+          ha->current_topology); */
+        DEBUG2(printk("[qla2100_ioctl: ERROR EXT_CC_SEND_FCCT_PASSTHRU not in F-Port or FL-Port mode]\n");)
+        return(ret);
+      }
+      /* check on loop down */
+      if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN)  {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+        copy_up_EXT(pext,arg);
+        /* printk("[EXT_CC_SEND_FCCT_PASSTHRU loop down]\n"); */
+        DEBUG2(printk("[qla2100_ioctl: ERROR EXT_CC_SEND_FCCT_PASSTHRU not in F-Port mode]\n");)
+        return(ret);
+      }
+      /* login to management server device */
+      if (ha->flags.managment_server_logged_in == 0) {
+          mb[0] = MBC_LOGIN_FABRIC_PORT;
+          mb[1] = MANAGEMENT_SERVER << 8;
+          mb[2] = 0xff;
+          mb[3] = 0xfffa;
+
+          ret = qla2100_mailbox_command(ha, BIT_3|BIT_2|BIT_1|BIT_0,
+                                &mb[0]);
+          if ( (ret != 0) || (mb[0] == 0x4006)  ||
+               (mb[0] == 0x4009) || (mb[0] != 0x4000) ) {
+              pext->Status       = EXT_STATUS_ERR;
+              pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+              copy_up_EXT(pext,arg);
+              /* printk("[EXT_CC_SEND_FCCT_PASSTHRU could not login to sns]\n"); */
+              DEBUG2(printk("[qla2100_ioctl: ERROR could not login to Management Server]\n");)
+              DEBUG(sprintf(debug_buff,"FCCT ioctl: call qla2100_ms_req_pkt\n"));
+              DEBUG(qla2100_print(debug_buff));
+              return(ret);
+          }
+          ha->flags.managment_server_logged_in = 1;
+      }
+
+      /* setup  sp  for this FCCT pass thru */
+      pscsi_cmd->host = ha->host;
+      sp->cmd         = pscsi_cmd;
+      sp->flags       = SRB_WATCHDOG;
+
+      /* mark this as a special delivery and collection command */
+      scsi_cmd.flags     = 0;      
+      scsi_cmd.scsi_done = ioctl_fcct_done;
+
+      DEBUG(sprintf(debug_buff,"FCCT ioctl: FABRIC_LOGIN OK, call qla2100_ms_req_pkt\n"));
+      DEBUG(qla2100_print(debug_buff));
+
+      /* get spin lock for this operation */
+      spin_lock_irqsave(&io_request_lock, cpu_flags);
+
+      /* Get MS request packet. */
+      if( (pkt = (cmd_ms_iocb_entry_t *)qla2100_ms_req_pkt(ha, sp) ) ) {
+            pkt->entry_type  = MS_IOCB_TYPE;
+            pkt->entry_count = 1;
+            pkt->loop_id     = MANAGEMENT_SERVER;
+            pkt->timeout     = 4;
+            pkt->DSDcount    = 1;
+            pkt->RespDSDcount = 2;
+            pkt->Response_bytecount = pext->ResponseLen;
+            pkt->Request_bytecount  = pext->RequestLen;
+
+            /* loading command payload address */
+            pkt->dseg_req_address[0] = LS_64BITS(ha->ioctl_mem_phys);
+            pkt->dseg_req_address[1] = MS_64BITS(ha->ioctl_mem_phys);
+            pkt->dseg_req_length = pext->RequestLen;
+  
+            /* loading command response address */
+            pkt->dseg_rsp_address[0] = LS_64BITS(ha->ioctl_mem_phys);
+            pkt->dseg_rsp_address[1] = MS_64BITS(ha->ioctl_mem_phys);
+            pkt->dseg_rsp_length = pext->ResponseLen;
+
+            /* set flag to indicate IOCTL FCCT PassThru in progress */
+            ha->IoctlPassFCCT_InProgress = 1;
+
+            ha->ioctl_timer = 6; /* 6 ticks of 1 second timer max wait */
+
+            /* Issue command to ISP */
+            qla2100_isp_cmd(ha);
+      }
+      /* release spin lock since command is issued */  
+      spin_unlock_irqrestore(&io_request_lock, cpu_flags);
+
+      DEBUG(sprintf(debug_buff,
+        "FCCT ioctl: Command issued and released spin lock\n"));
+      DEBUG(qla2100_print(debug_buff));
+
+      if (!pkt) {
+          pext->Status       = EXT_STATUS_ERR;
+          pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+          copy_up_EXT(pext,arg);
+          /* printk("[EXT_CC_SEND_FCCT_PASSTHRU could not get Request Packet]\n"); */
+          DEBUG2(printk("[qla2100_ioctl:EXT_CC_SEND_FCCT_PASSTHRU could not get Request Packet]\n");)
+          return(ret);
+      }
+
+      /* wait for post function or timer to zero the InProgress flag */
+      while (ha->IoctlPassFCCT_InProgress == 1)  {
+        udelay(35);
+      }
+
+      DEBUG(sprintf(debug_buff,
+        "FCCT ioctl: finished while(InProgress) wait loop \n"));
+      DEBUG(qla2100_print(debug_buff));
+      /* printk("[FCCT IOCTL finished while(InProgress) wait loop ]\n");*/
+
+        if (ha->IoctlPassFCCT_InProgress == 1) {
+          /* We waited and post function did not get called */ 
+          DEBUG(printk("[FCCT IOCTL post function not called]\n");)
+          DEBUG(sprintf(debug_buff,
+           "FCCT ioctl: post function not called \n"));
+          DEBUG(qla2100_print(debug_buff));
+          pext->Status       = EXT_STATUS_ERR;
+          pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;   
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_ERR;
+        } else {
+             /* getting device data and putting in pext->ResponseAdr */
+             /* printk("[post function called; start FCCT IOCTL returning up data ]\n");*/
+             ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                               pext->ResponseLen); 
+             if (ret) {
+               pext->Status       = EXT_STATUS_ERR;
+               pext->DetailStatus = EXT_STATUS_COPY_ERR;
+               copy_up_EXT(pext,arg);
+               DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE for IOCTL PT ha=%8x]\n",
+                     (uint32_t)ha);)
+               return(ret);
+             }
+             /* sending back data returned from Management Server */
+             for (i=0 ; i < pext->ResponseLen ; i++) {
+                usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+                kernel_tmp = (uint8_t *)ha->ioctl_mem + i;
+                /*printk("[%x]",*kernel_tmp);*/
+                __put_user(*kernel_tmp, usr_temp);
+             }
+          /*printk("[finished QLA2100 IOCTL EXT_CC_SEND_FCCT_PASSTHRU]\n");*/
+          pext->Status       = EXT_STATUS_SCSI_STATUS;
+          pext->DetailStatus = sp->scode;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+        }
+      break;
+
+    case EXT_CC_SEND_SCSI_PASSTHRU: 
+      /* printk("[start EXT_CC_SEND_SCSI_PASSTHRU]\n"); */
+      ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr,
+            sizeof(EXT_SCSI_PASSTHRU)); 
+      if (ret) {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_COPY_ERR;
+        copy_up_EXT(pext,arg);
+        DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_SCSI_PASSTHRU]\n");)
+        return(ret);
+      }
+      for (i=0 ; i < sizeof(EXT_SCSI_PASSTHRU) ; i++) {
+        usr_temp   = (uint8_t *)pext->RequestAdr + i;
+        kernel_tmp = (uint8_t *)pscsi_pass + i;
+        __get_user(*kernel_tmp, usr_temp);
+      }
+      if (pext->ResponseLen > PAGE_SIZE) {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+        copy_up_EXT(pext,arg);
+        DEBUG2(printk("[qla2100_ioctl: ERROR size of requested EXT_SCSI_PASSTHRU]\n");)
+        return(ret);
+      }
+      /* clear ioctl_sp and scsi_cmd and scsi_device to be used */
+      kernel_tmp = (uint8_t *)sp;
+      for (i=0;i<sizeof(srb_t);i++)       *(kernel_tmp+i) = 0; 
+      kernel_tmp = (uint8_t *)pscsi_cmd;
+      for (i=0;i<sizeof(Scsi_Cmnd);i++)   *(kernel_tmp+i) = 0; 
+      kernel_tmp = (uint8_t *)&scsi_device;
+      for (i=0;i<sizeof(Scsi_Device);i++) *(kernel_tmp+i) = 0; 
+      kernel_tmp = (uint8_t *)ha->ioctl_mem;
+      for (i=0;i<PAGE_SIZE;i++) *kernel_tmp = 0; 
+
+      pscsi_cmd->host = ha->host;
+      sp->cmd         = pscsi_cmd;
+      sp->flags       = SRB_WATCHDOG;
+
+      /* mark this as a special delivery and collection command */
+      scsi_cmd.flags     = 0;      
+      scsi_cmd.scsi_done = ioctl_scsi_pt_done;
+
+      scsi_cmd.device               = &scsi_device;     
+      scsi_cmd.device->tagged_queue = 0;
+      scsi_cmd.use_sg               = 0; /* no ScatterGather */
+      scsi_cmd.target               = pscsi_pass->TargetAddr.Target;
+      scsi_cmd.lun                  = pscsi_pass->TargetAddr.Lun;
+      scsi_cmd.request_bufflen      = pext->ResponseLen;
+      scsi_cmd.request_buffer       = ha->ioctl_mem;
+      scsi_cmd.timeout_per_command  = 0x300;
+
+      // printk("[start FCSCSI IOCTL look at direction t=%x l=%x]\n",
+      // scsi_cmd.target,scsi_cmd.lun);
+      if (pscsi_pass->Direction == EXT_DEF_SCSI_PASSTHRU_DATA_OUT) {
+          /* sending user data from pext->ResponseAdr to device */
+          ret = verify_area(VERIFY_READ, (void *)pext->ResponseAdr,
+                            pext->ResponseLen); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ EXT_SCSI_PASSTHRU]\n");)
+            return(ret);
+          }
+          for (i=0 ; i < pext->ResponseLen ; i++) {
+            usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+            kernel_tmp = (uint8_t *)ha->ioctl_mem    + i;
+            __get_user(*kernel_tmp, usr_temp);
+          }
+      }
+      if (pscsi_pass->CdbLength == 6) {
+        scsi_cmd.cmd_len = 6;
+        scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0];
+        scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1];
+        scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2];
+        scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3];
+        scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4];
+        scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5];
+        scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = 0;
+        scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = 0;
+        scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = 0;
+        scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = 0;
+      } else if (pscsi_pass->CdbLength == 10) {
+        scsi_cmd.cmd_len = 0x0A;
+        scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0];
+        scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1];
+        scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2];
+        scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3];
+        scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4];
+        scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5];
+        scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = pscsi_pass->Cdb[6];
+        scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = pscsi_pass->Cdb[7];
+        scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = pscsi_pass->Cdb[8];
+        scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = pscsi_pass->Cdb[9];
+      } else if (pscsi_pass->CdbLength == 12) {
+        scsi_cmd.cmd_len = 0x0C;
+        scsi_cmd.data_cmnd[0] = scsi_cmd.cmnd[0] = pscsi_pass->Cdb[0];
+        scsi_cmd.data_cmnd[1] = scsi_cmd.cmnd[1] = pscsi_pass->Cdb[1];
+        scsi_cmd.data_cmnd[2] = scsi_cmd.cmnd[2] = pscsi_pass->Cdb[2];
+        scsi_cmd.data_cmnd[3] = scsi_cmd.cmnd[3] = pscsi_pass->Cdb[3];
+        scsi_cmd.data_cmnd[4] = scsi_cmd.cmnd[4] = pscsi_pass->Cdb[4];
+        scsi_cmd.data_cmnd[5] = scsi_cmd.cmnd[5] = pscsi_pass->Cdb[5];
+        scsi_cmd.data_cmnd[6] = scsi_cmd.cmnd[6] = pscsi_pass->Cdb[6];
+        scsi_cmd.data_cmnd[7] = scsi_cmd.cmnd[7] = pscsi_pass->Cdb[7];
+        scsi_cmd.data_cmnd[8] = scsi_cmd.cmnd[8] = pscsi_pass->Cdb[8];
+        scsi_cmd.data_cmnd[9] = scsi_cmd.cmnd[9] = pscsi_pass->Cdb[9];
+        scsi_cmd.data_cmnd[10] = scsi_cmd.cmnd[10] = pscsi_pass->Cdb[10];
+        scsi_cmd.data_cmnd[11] = scsi_cmd.cmnd[10] = pscsi_pass->Cdb[11];
+       }
+      /* Generate LU queue on bus, target, LUN */
+      b = SCSI_BUS_32(pscsi_cmd);
+      t = SCSI_TCN_32(pscsi_cmd);
+      l = SCSI_LUN_32(pscsi_cmd);
+
+      /* set sp->target for 32bit/64bit delivery */
+      sp->wdg_time                   = 0;
+
+      /* check presense of requested target and other conditions */
+      if( TGT_Q(ha,b,t) == NULL ||
+        ( TGT_Q(ha,b,t) && TGT_Q(ha,b,t)->loop_id > LAST_SNS_LOOP_ID)  ||
+        ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN)) {  
+            printk(KERN_WARNING "qla2x00: FCSCSI IOCTL Target MISSING.\n");
+            DEBUG2(printk("scsi(%2d:%2d:%2d:%2d): SCSI PT port unavailable\n",
+                  (int)ha->host_no,b,t,l);)
+           pext->Status       = EXT_STATUS_ERR;
+           pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+           copy_up_EXT(pext,arg);
+           return(ret);
+       }  
+      /* get spin lock for this operation */
+      spin_lock_irqsave(&io_request_lock, cpu_flags);
+
+      /* Allocate a LUN/DEVICE queue from this request */
+        if( (q = GET_LU_Q(ha, b, t,l)) == NULL ) {
+            DRIVER_LOCK
+            if( (q = qla2100_lun_alloc()) == NULL ) {
+               pext->Status       = EXT_STATUS_ERR;
+               pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+               copy_up_EXT(pext,arg);
+               DEBUG2(printk("[qla2100_ioctl: ERROR in GET_LU_Q for SCSI_PASSTHRU ha=%8x]\n",
+                     (uint32_t)ha);)
+               ret = EXT_STATUS_ERR;
+               return(ret);
+            }
+            LU_Q(ha, b, t, l) = q;
+            DEBUG(sprintf(debug_buff,"Allocate new device queue 0x%x\n",q));
+            DEBUG(qla2100_print(debug_buff));
+            DRIVER_UNLOCK
+        }
+        /* Set an invalid handle until we issue the command to ISP */
+        /* then we will set the real handle value.                 */
+        handle = INVALID_HANDLE;  
+        CMD_HANDLE(pscsi_cmd) = (unsigned char *)handle;
+
+        if( sp->flags ) {
+            sp->port_down_retry_count = ha->port_down_retry_count - 1;
+            sp->retry_count = ha->retry_count; 
+            DEBUG3(sprintf(debug_buff,"qla2100: PT Set retry counts =0x%x,0x%x\n\r",
+                   sp->port_down_retry_count,sp->retry_count));
+            DEBUG3(qla2100_print(debug_buff));
+        }
+        qla2100_putq_t(q,sp); 
+
+        /* set flag to indicate IOCTL SCSI PassThru in progress */
+        ha->IoctlPassThru_InProgress = 1;
+
+        //printk("[start FCSCSI IOCTL restart queues]\n");
+        /* send command to adapter */
+        qla2100_restart_queues(ha,FALSE);
+
+        /* release spin lock since command is queued */  
+        spin_unlock_irqrestore(&io_request_lock, cpu_flags);
+
+        ha->ioctl_timer = 6; /* 6 ticks of 1 second timer max wait */
+
+        /* wait for post function or timer to zero the InProgress flag */
+        while (ha->IoctlPassThru_InProgress == 1) {
+             udelay(35);
+        }
+
+        //printk("[start FCSCSI IOCTL finished while]\n");
+        if (ha->IoctlPassThru_InProgress == 1) {
+          /* We waited and post function did not get called */ 
+          DEBUG(printk("[FCSCSI IOCTL post function not called]\n");)
+          pext->Status       = EXT_STATUS_ERR;
+          pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;   
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_ERR;
+        } else {
+          if (pscsi_pass->Direction == EXT_DEF_SCSI_PASSTHRU_DATA_IN) {
+             /* getting device data and putting in pext->ResponseAdr */
+             ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                               pext->ResponseLen); 
+             if (ret) {
+               pext->Status       = EXT_STATUS_ERR;
+               pext->DetailStatus = EXT_STATUS_COPY_ERR;
+               copy_up_EXT(pext,arg);
+               DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE for IOCTL PT ha=%8x]\n",
+                     (uint32_t)ha);)
+               return(ret);
+             }
+             /* now copy up the READ data to user */
+             for (i=0 ; i < pext->ResponseLen ; i++) {
+                usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+                kernel_tmp = (uint8_t *)ha->ioctl_mem + i;
+                /*printk("[%x]",*kernel_tmp);*/
+                __put_user(*kernel_tmp, usr_temp);
+             }
+          }
+          //printk("[[sense0=%x sense2=%x]]\n",
+          //pscsi_cmd->sense_buffer[0],
+          //pscsi_cmd->sense_buffer[2]);
+          /* copy up structure to make sense data available to user */
+          for (i=0;i<16;i++) 
+               pscsi_pass->SenseData[i] = pscsi_cmd->sense_buffer[i];
+          ret = verify_area(VERIFY_WRITE, (void *)pext->RequestAdr,
+                            sizeof(EXT_SCSI_PASSTHRU)); 
+          if (ret) {
+            pext->Status       = EXT_STATUS_ERR;
+            pext->DetailStatus = EXT_STATUS_COPY_ERR;
+            copy_up_EXT(pext,arg);
+            DEBUG2(printk("[qla2100_ioctl: ERROR verify_area WRITE of EXT_SCSI_PASSTHRU]\n");)
+            return(ret);
+          }
+          for (i=0 ; i < sizeof(EXT_SCSI_PASSTHRU) ; i++) {
+            usr_temp   = (uint8_t *)pext->RequestAdr + i;
+            kernel_tmp = (uint8_t *)pscsi_pass + i;
+            __put_user(*kernel_tmp, usr_temp);
+          }
+          /* printk("[finished QLA2100 IOCTL EXT_FCSCSI_REQ]\n"); */ 
+          pext->Status       = EXT_STATUS_SCSI_STATUS;
+          pext->DetailStatus = sp->scode;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+        }
+      break;
+ 
+   case EXT_CC_READ_NVRAM:
+      if (pext->ResponseLen < sizeof(nvram21_t)) transfer_size = pext->ResponseLen;
+      else      transfer_size = sizeof(nvram21_t)/2;
+      for( i = 0, cnt = 0; cnt < transfer_size ; cnt++ , i++ ) {
+          *wptr = qla2100_get_nvram_word(ha, cnt);
+
+          usr_temp    = (uint8_t *)pext->ResponseAdr;
+          kernel_tmp  = (uint8_t *)wptr;
+
+          usr_temp += i; /* even byte */
+          __put_user(*kernel_tmp, usr_temp);
+
+          i++;
+          usr_temp    = (uint8_t *)pext->ResponseAdr;
+          kernel_tmp1 = (uint8_t *)wptr + 1;
+          usr_temp += i; /* odd byte */
+          __put_user(*kernel_tmp1, usr_temp);
+      }
+
+      /* printk("[finished QLA2100 IOCTL EXT_NVR_RD]\n"); */ 
+      pext->Status       = EXT_STATUS_OK;
+      pext->DetailStatus = EXT_STATUS_OK;
+      copy_up_EXT(pext,arg);
+      ret = EXT_STATUS_OK;
+      break;
+
+    case EXT_CC_LOOPBACK:
+    DEBUG(sprintf(debug_buff,"qla2100_ioctl: start EXT_CC_LOOPBACK\n"));
+    DEBUG(qla2100_print(debug_buff));
+
+    /* printk("[start EXT_CC_LOOPBACK]\n"); */
+
+    if (ha->device_id == QLA2100_DEVICE_ID) {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+        copy_up_EXT(pext,arg);
+        DEBUG2(printk("[EXT_CC_SEND_LOOP_BACK not supported on QLA2100]\n");)
+        return(ret);
+    }
+
+      if (pext->ResponseLen > PAGE_SIZE)  pext->ResponseLen = PAGE_SIZE;
+      if (pext->RequestLen  > PAGE_SIZE)  {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_INVALID_PARAM;
+        copy_up_EXT(pext,arg);
+        /*printk("[EXT_CC_LOOPBACK too big ResponseLen=%x ReqLen=%x]\n",pext->ResponseLen,pext->RequestLen); */
+        DEBUG2(printk("[qla2100_ioctl: ERROR size of requested Resp_len in EXT_CC_SEND_LOOP_BACK]\n");)
+        return(ret);
+      }
+      ret = verify_area(VERIFY_READ, (void *)pext->RequestAdr,
+                        pext->RequestLen); 
+      if (ret){
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_COPY_ERR;
+        copy_up_EXT(pext,arg);
+        /*printk("[EXT_CC_LOOPBACK verify read error]\n");*/ 
+        DEBUG2(printk("[qla2100_ioctl: ERROR verify_area READ of EXT_CC_LOOPBACK]\n");)
+        return(ret);
+      }
+      for (i=0 ; i < pext->ResponseLen ; i++) {
+        /* copy in from user space the user data pattern to be sent */
+        usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+        kernel_tmp = (uint8_t *)ha->ioctl_mem + i;
+        __get_user(*kernel_tmp, usr_temp);
+	/*  printk("{%x}",*kernel_tmp); */ 
+      }
+      /* check on loop down */
+      if ( ha->loop_down_timer == 0 && ha->loop_state == LOOP_DOWN)  {
+        pext->Status       = EXT_STATUS_ERR;
+        pext->DetailStatus = EXT_STATUS_DEV_NOT_FOUND;
+        copy_up_EXT(pext,arg);
+        /* printk("[EXT_CC_LOOPBACK loop down]\n"); */
+        return(ret);
+      }
+
+      /* get spin lock for this operation */
+      spin_lock_irqsave(&io_request_lock, cpu_flags);
+
+      mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
+      mb[1] = 0x72; /* options: 64 bit, use buffer for snd/rcv on ext. loop */
+      mb[2] = mb[3] = mb[4] = mb[5] = mb[6] = mb[7] = mb[8] = mb[9] = 0;
+      mb[10] = LSW(pext->ResponseLen);
+      mb[11] = MSW(pext->ResponseLen);
+      mb[12] = 0; /* transfer segment count */
+      mb[13] = 0; /* receive segment count */
+      mb[14] = LSW(ha->ioctl_mem_phys); /* send data address */
+      mb[15] = MSW(ha->ioctl_mem_phys);
+      mb[20] = QL21_64BITS_3RDWD(ha->ioctl_mem_phys);
+      mb[21] = QL21_64BITS_4THWD(ha->ioctl_mem_phys);
+      mb[16] = LSW(ha->ioctl_mem_phys); /* recv data address */
+      mb[17] = MSW(ha->ioctl_mem_phys);
+      mb[6]  = QL21_64BITS_3RDWD(ha->ioctl_mem_phys);
+      mb[7]  = QL21_64BITS_4THWD(ha->ioctl_mem_phys); 
+      mb[18] = 1; /* iteration count lsb */
+      mb[19] = 0; /* iteration count msb */
+
+      DEBUG(sprintf(debug_buff,
+            "LoopBack ioctl: issue loop back mailbox command\n"));
+      DEBUG(qla2100_print(debug_buff));
+
+      // wait for 64 bit loopback ready firmware
+      status = qla2100_mailbox_command(ha,BIT_21|BIT_20|BIT_19|BIT_18|
+                                       BIT_17|BIT_16|BIT_15|BIT_14|
+                                       BIT_13|BIT_12|BIT_11|
+                                       BIT_10|BIT_7|BIT_6|BIT_1|BIT_0,
+                                       &mb[0]);
+
+      /* release spin lock since command is issued */  
+      spin_unlock_irqrestore(&io_request_lock, cpu_flags);
+
+        if (status) {
+          DEBUG(sprintf(debug_buff,
+           "LoopBack ioctl: issue loop back mailbox command FAILED\n"));
+          DEBUG(qla2100_print(debug_buff));
+          pext->Status       = EXT_STATUS_ERR;
+          pext->DetailStatus = EXT_STATUS_ERR;   
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_ERR;
+        } else {
+             /* put looped back data in pext->ResponseAdr */
+             /* printk("[LoopBack ioctl: LoopBack was OK ]\n");*/
+             ret = verify_area(VERIFY_WRITE, (void *)pext->ResponseAdr ,
+                               pext->ResponseLen); 
+             if (ret) {
+               pext->Status       = EXT_STATUS_ERR;
+               pext->DetailStatus = EXT_STATUS_COPY_ERR;
+               copy_up_EXT(pext,arg);
+               DEBUG2(printk("[LoopBack ioctl: ERROR verify_area WRITE ha=%x]\n",
+                     (uint32_t)ha);)
+               return(ret);
+             }
+             /* sending back looped back data */
+             for (i=0 ; i < pext->ResponseLen ; i++) {
+                usr_temp   = (uint8_t *)pext->ResponseAdr + i;
+                kernel_tmp = (uint8_t *)ha->ioctl_mem + i;
+                /*printk("[%x]",*kernel_tmp);*/
+                __put_user(*kernel_tmp, usr_temp);
+             }
+          /*printk("[finished QLA2100 IOCTL EXT_CC_LOOPBACK]\n");*/
+          pext->Status       = EXT_STATUS_OK;
+          pext->DetailStatus = EXT_STATUS_OK;
+          copy_up_EXT(pext,arg);
+          ret = EXT_STATUS_OK;
+        }
+      break;
+
+/* case EXT_CC_RSCN_REG:
+      break;
+    case EXT_CC_RSCN_GET:
+      break; 
+    case EXT_CC_ELS_RNID_SEND:
+      break;
+    case EXT_CC_ELS_RTIN_SEND:
+      break;
+    case EXT_CC_PLATFORM_REG:
+      break;
+
+all others go here */
+
+    default:
+      break;
+  }
+
+  return(ret);
+}
+
diff -urN linux-2.4.16/drivers/scsi/qlavendor.c lia64-2.4/drivers/scsi/qlavendor.c
--- linux-2.4.16/drivers/scsi/qlavendor.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/qlavendor.c	Mon Jul 23 14:13:02 2001
@@ -0,0 +1,325 @@
+/********************************************************************************
+*                  QLOGIC LINUX SOFTWARE
+*
+* QLogic ISP2x00 device driver for Linux 2.2.x (redhat 6.X).
+*
+* COPYRIGHT (C) 2000 QLOGIC CORPORATION
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the Qlogic's Linux Software License. See below.
+*
+* This program is WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistribution's or source code must retain the above copyright
+*    notice, this list of conditions, and the following disclaimer,
+*    without modification, immediately at the beginning of the file.
+* 2. The name of the author may not be used to endorse or promote products
+*    derived from this software without specific prior written permission.
+*
+********************************************************************************/
+
+/*****************************************************************************************
+                       QLOGIC CORPORATION SOFTWARE
+                      "GNU" GENERAL PUBLIC LICENSE
+             TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION
+                            AND MODIFICATION
+
+This GNU General Public License ("License") applies solely to QLogic Linux
+Software ("Software") and may be distributed under the terms of this License.
+
+1. You may copy and distribute verbatim copies of the Software's source code as
+you receive it, in any medium, provided that you conspicuously and appropriately
+publish on each copy an appropriate copyright notice and disclaimer of warranty;
+keep intact all the notices that refer to this License and to the absence of any
+warranty; and give any other recipients of the Software a copy of this License along
+with the Software.
+
+You may charge a fee for the physical act of transferring a copy, and you may at your
+option offer warranty protection in exchange for a fee.
+
+2. You may modify your copy or copies of the Software or any portion of it, thus forming
+a work based on the Software, and copy and distribute such modifications or work under
+the terms of Section 1 above, provided that you also meet all of these conditions:
+
+* a) You must cause the modified files to carry prominent notices stating that you
+changed the files and the date of any change.
+
+* b) You must cause any work that you distribute or publish that in whole or in part
+contains or is derived from the Software or any part thereof, to be licensed as a
+whole at no charge to all third parties under the terms of this License.
+
+* c) If the modified Software normally reads commands interactively when run, you
+must cause it, when started running for such interactive use in the most ordinary way,
+to print or display an announcement including an appropriate copyright notice and a
+notice that there is no warranty (or else, saying that you provide a warranty) and that
+users may redistribute the Software under these conditions, and telling the user how to
+view a copy of this License. (Exception:if the Software itself is interactive but does
+not normally print such an announcement, your work based on the Software is not required
+to print an announcement.)
+
+These requirements apply to the modified work as a whole. If identifiable sections of
+that work are not derived from the Software, and can be reasonably considered independent
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+sections when you distribute them as separate works. But when you distribute the same
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+whole must be on the terms of this License, whose permissions for other licensees extend
+to the entire whole, and thus to each and every part regardless of who wrote it.
+
+3. You may copy and distribute the Software (or a work based on it, under Section 2) in
+object code or executable form under the terms of Sections 1 and 2 above provided that
+you also do one of the following:
+
+* a) Accompany it with the complete corresponding machine-readable source code, which must
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+
+* b) Accompany it with a written offer, valid for at least three years, to give any third
+party, for a charge no more than your cost of physically performing source distribution,
+a complete machine-readable copy of the corresponding source code, to be distributed under
+the terms of Sections 1 and 2 above on a medium customarily used for software interchange;
+or,
+
+* c) Accompany it with the information you received as to the offer to distribute
+corresponding source code. (This alternative is allowed only for noncommercial distribution
+and only if you received the Software in object code or executable form with such an offer,
+in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for making modifications
+to it. For an executable work, complete source code means all the source code for all
+modules it contains, plus any associated interface definition files, plus the scripts used
+to control compilation and installation of the executable.
+
+If distribution of executable or object code is made by offering access to copy from a
+designated place, then offering equivalent access to copy the source code from the same
+place counts as distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+4. You may not copy, modify, sublicense, or distribute the Software except as expressly
+provided under this License. Any attempt otherwise to copy, modify, sublicense or
+distribute the Software is void, and will automatically terminate your rights under this
+License. However, parties who have received copies, or rights, from you under this License
+will not have their licenses terminated so long as such parties remain in full compliance.
+
+5. This license grants you world wide, royalty free non-exclusive rights to modify or
+distribute the Software or its derivative works. These actions are prohibited by law
+if you do not accept this License. Therefore, by modifying or distributing the Software
+(or any work based on the Software), you indicate your acceptance of this License to do
+so, and all its terms and conditions for copying, distributing or modifying the Software
+or works based on it.
+
+6. Each time you redistribute the Software (or any work based on the Software), the
+recipient automatically receives a license from the original licensor to copy, distribute
+or modify the Software subject to these terms and conditions. You may not impose any
+further restrictions on the recipients' exercise of the rights granted herein. You are
+not responsible for enforcing compliance by third parties to this License.
+
+7. If, as a consequence of a court judgment or allegation of patent infringement or for
+any other reason (not limited to patent issues), conditions are imposed on you
+(whether by court order, agreement or otherwise) that contradict the conditions of this
+License, they do not excuse you from the conditions of this License. If you cannot
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+Software at all.
+
+If any portion of this section is held invalid or unenforceable under any particular
+circumstance, the balance of the section is intended to apply and the section as a whole
+is intended to apply in other circumstances.
+NO WARRANTY
+
+11. THE SOFTWARE IS PROVIDEDWITHOUT A WARRANTY OF ANY KIND. THERE IS NO
+WARRANTY FOR THE SOFTWARE, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE SOFTWARE "AS IS" WITHOUT WARRANTY OF ANY KIND,
+EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
+ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOFTWARE IS WITH YOU.
+SHOULD THE SOFTWARE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
+NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE SOFTWARE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
+DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOFTWARE (INCLUDING
+BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR
+LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOFTWARE TO
+OPERATE WITH ANY OTHER SOFTWARES), EVEN IF SUCH HOLDER OR OTHER PARTY HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+END OF TERMS AND CONDITIONS
+
+******************************************************************************/
+/*
+ * vendor specific op codes.
+*/
+
+#define	UCSCSI_DCMD			0x20 /* DAC960 direct command */
+#define UCSCSI_DCMD_PASSTHRU		0x21 /* DAC960 pass-through command */
+#define	UC_SCSI_DCMD			0x22 /* DAC960 FSI direct command */
+#define DAC_CDB_LEN			12
+#define DAC_SENSE_LEN			64
+
+#define SCSI_WRITE10			0x2A	/* Required for direct disk writes */
+#define SCSI_WRITE6			0x0A	/* Required for direct disk writes */
+#define SCSI_WRITEBUFFER		0x3B	/* Required for flashing disk FW */
+#define DACMD_WRITE_CONF_ONDISK		0x4B
+#define	DACMD_WRITE_CONFIG		0x06
+#define	DACMD_WRITE_CONF2		0x3C
+#define	DACMD_WRITE_CONFLABEL		0x49 /* Write configuration label */
+#define	DACMD_WRITE_CONFIG_V3x		0x4F
+#define	DACMD_ADD_CONFIG_V2x		0x18
+#define	DACMD_ADD_CONFIG_V3x		0x4C
+#define	DACMD_STORE_IMAGE		0x21
+#define	DACMD_ADD_CAPACITY		0x2A /* add physical drives to existing array */
+#define	DACMD_WRITE_IOPORT		0x3A /* write port B */
+#define	DACMD_S2S_WRITEFULLCONF		0x60 /* write full configuration */
+#define	DACMD_S2S_ADDFULLCONF		0x62 /* add   full configuration */
+#define	DACMD_S2S_WRITELUNMAP_OLD	0x58 /* write LUN map information */
+#define DACMD_S2S_WRITELUNMAP		0xD2 /* Write LUN MAP Information */
+#define	DACMD_S2S_WRITE_IOPORT		0x66 /* write expanded IO port */
+#define	DACMD_WRITE_V3x			0x34 /* write data from plain memory */
+#define	DACMD_S2S_WRITESIG		0x4D /* write signature information */
+
+#define MDACIOCTL_STOREIMAGE		0x2C /* Store the softeware image on controller */
+#define MDACIOCTL_WRITESIGNATURE	0xA6 /* Write Controller Signature */
+#define MDACIOCTL_SETREALTIMECLOCK	0xAC /* Set real time clock value */
+#define MDACIOCTL_PASS_THRU_CDB		0xAD /* Set up a pass-through command */
+#define MDACIOCTL_PASS_THRU_INITIATE	0xAE /* Initiates a pass-through read/write command (bi-directional) */
+#define MDACIOCTL_CREATENEWCONF		0xC0 /* Create new configruation */
+#define MDACIOCTL_ADDNEWCONF		0xC4 /* Add new logical/physical device to configruation */
+#define MDACIOCTL_MORE			0xC6 /* Do MORE operation */
+#define MDACIOCTL_SETPHYSDEVPARAMETER	0xC8 /* Set physical device parameters */
+#define MDACIOCTL_SETLOGDEVPARAMETER	0xCF /* Set logical device parameters */
+#define MDACIOCTL_SETCONTROLLERPARAMTER	0xD1 /* Set controller parameter */
+#define MDACIOCTL_WRITESANMAP		0xD4 /* Set logical device LUN map */
+#define MDACIOCTL_SETMACADDRESS		0xD5 /* Set controller MAC address */
+
+    /*
+    * qla2100_set_scsi_direction
+    *      This routine will set the proper direction for vendor specific
+    *      commands. 
+    *
+    *      Note: Vendors should modify this routine to set the proper 
+    *      direction of the transfer if they used vendor specific commands.
+    *
+    * Input:
+    *      ha = adapter block pointer.
+    *      sp = SCSI Request Block structure pointer.
+    *
+    * Returns:
+    *      0 = success, was able to issue command.
+    */
+
+     void qla2100_set_vend_direction(scsi_qla_host_t *ha, 
+ 			Scsi_Cmnd       *cmd, cmd_entry_t     *pkt) {
+			/* This section added 10-JAN-2001 by Lethe. Required to facilitate SCSI
+			   pass-through for flashing disk firmware, and direct disk writes under
+			   Mylex 6.x and 5.x Firmware */
+           	if( cmd->data_cmnd[0] == UCSCSI_DCMD_PASSTHRU) {
+				pkt->control_flags = 0;
+				switch (cmd->data_cmnd[2]) {
+						case SCSI_WRITE6:
+						case SCSI_WRITE10:
+						case SCSI_WRITEBUFFER:
+							pkt->control_flags |= BIT_6;
+							break;
+						default:
+							pkt->control_flags |= BIT_5;
+			    }
+			} 
+			else if( cmd->data_cmnd[0] == UCSCSI_DCMD )
+			{
+			    pkt->control_flags = 0;
+			    switch( cmd->data_cmnd[2] )
+			    {
+				case DACMD_WRITE_CONF_ONDISK:
+				case DACMD_WRITE_CONFIG:
+				case DACMD_WRITE_CONF2:
+				case DACMD_WRITE_CONFLABEL:
+				case DACMD_WRITE_CONFIG_V3x:
+				case DACMD_ADD_CONFIG_V2x:
+				case DACMD_ADD_CONFIG_V3x:
+				case DACMD_STORE_IMAGE:
+				case DACMD_ADD_CAPACITY:
+				case DACMD_WRITE_IOPORT:
+				case DACMD_S2S_WRITEFULLCONF:
+				case DACMD_S2S_ADDFULLCONF:
+				case DACMD_S2S_WRITELUNMAP_OLD:
+				case DACMD_S2S_WRITELUNMAP:
+				case DACMD_S2S_WRITE_IOPORT:
+				case DACMD_WRITE_V3x:
+				case DACMD_S2S_WRITESIG:
+					pkt->control_flags |= BIT_6;
+					break;
+				default:
+					pkt->control_flags |= BIT_5;
+			    }
+			}
+
+/*******************************************************************************************
+* The below logic is required to operate correctly with Mylex (IBM's) DAC960 family of     *
+* external RAID controllers.                                                               *
+*                                                                                          *
+* In addition to defining whether below CDBs are Reads or Writes, Mylex, in their infinite *
+* wisdom, defined a vendor-specific CDB which can act as a Read OR a write, depending on   *
+* the parameters sent in a previous MDACIOCTL_PASS_THRU_CDB.  Instead of adding a lot of   *
+* logic to define and maintain a MDACIOCTL_PASS_THRU_CDB queue, and parse each one of them *
+* to determine direction, I took easy way out (also the low-overhead method).              *
+*                                                                                          *
+* If the high-order bit of the 32-bit UniqueID, defined in byte 3 of data_cmnd[3] is set   *
+* then I will mark that as a CDB which is going to be a write, otherwise the pass thru     *
+* operation will be a read. If somebody wishes to rewrite the driver to maintain a 30-sec  *
+* command queue, and parse the contents of each data buffer passed in to determine R or W  *
+* then they are free to do so, and it will not impact future versions of the Distributed   *
+* Array Manager, which required this fix in the first place.                               *
+*                                                                                          *
+* This configurator and patch was written by David A. Lethe of Xyratex david@santools.com. *
+* In addition, the logic to check cmd->data_cmnd[0] == UC_SCSI_DCMD, was written by        *
+* Sammy Wilborn of Silicon Graphics, Inc, and David Lethe                                  *
+* They define CDBs used by the DAC960FF family, when running FW 7.x and above.             *
+*                                                                                          *
+*******************************************************************************************/
+
+			else if ( cmd->data_cmnd[0] == UC_SCSI_DCMD ) /* Mylex DAC960 FW 7.x */
+			{
+			    pkt->control_flags = 0;
+			    switch( cmd->data_cmnd[2] )
+			    {
+				case MDACIOCTL_STOREIMAGE:
+				case MDACIOCTL_SETREALTIMECLOCK:
+				case MDACIOCTL_WRITESIGNATURE:
+			        case MDACIOCTL_CREATENEWCONF:
+			        case MDACIOCTL_ADDNEWCONF:
+			        case MDACIOCTL_MORE:
+			        case MDACIOCTL_SETPHYSDEVPARAMETER:
+			        case MDACIOCTL_SETLOGDEVPARAMETER:
+			        case MDACIOCTL_SETCONTROLLERPARAMTER:
+			        case MDACIOCTL_WRITESANMAP:
+			        case MDACIOCTL_SETMACADDRESS:
+				case MDACIOCTL_PASS_THRU_CDB:
+					pkt->control_flags |= BIT_6;
+					break;
+				default:
+					if (cmd->data_cmnd[2] == MDACIOCTL_PASS_THRU_INITIATE) {
+					/* If the high bit of the UniqueID field of the vendor-
+					   specific field is TRUE, then it is marked as a write. */
+						if (cmd->data_cmnd[3] & 0x80)
+							pkt->control_flags |= BIT_6;
+						else
+							pkt->control_flags |= BIT_5;
+					}
+					else
+						pkt->control_flags |= BIT_5;
+					break;
+			    }
+			}
+			else
+			{
+                       		pkt->control_flags |= BIT_5;
+			}
+
+    }
diff -urN linux-2.4.16/drivers/scsi/scsi_ioctl.c lia64-2.4/drivers/scsi/scsi_ioctl.c
--- linux-2.4.16/drivers/scsi/scsi_ioctl.c	Mon Aug 20 10:19:06 2001
+++ lia64-2.4/drivers/scsi/scsi_ioctl.c	Mon Aug 20 12:20:58 2001
@@ -198,6 +198,9 @@
 	unsigned int needed, buf_needed;
 	int timeout, retries, result;
 	int data_direction;
+#if __GNUC__ < 3
+        int foo;
+#endif
 
 	if (!sic)
 		return -EINVAL;
@@ -207,12 +210,21 @@
 	if (verify_area(VERIFY_READ, sic, sizeof(Scsi_Ioctl_Command)))
 		return -EFAULT;
 
-	if(__get_user(inlen, &sic->inlen))
+#if __GNUC__ < 3
+        foo = __get_user(inlen, &sic->inlen);
+	if(foo)
 		return -EFAULT;
 		
-	if(__get_user(outlen, &sic->outlen))
+        foo = __get_user(outlen, &sic->outlen);
+	if(foo)
+		return -EFAULT;
+#else
+	if(__get_user(inlen, &sic->inlen))
 		return -EFAULT;
 
+	if(__get_user(outlen, &sic->outlen))
+		return -EFAULT;
+#endif
 	/*
 	 * We do not transfer more than MAX_BUF with this interface.
 	 * If the user needs to transfer more data than this, they
diff -urN linux-2.4.16/drivers/scsi/simscsi.c lia64-2.4/drivers/scsi/simscsi.c
--- linux-2.4.16/drivers/scsi/simscsi.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/simscsi.c	Wed Feb 21 16:30:57 2001
@@ -0,0 +1,382 @@
+/*
+ * Simulated SCSI driver.
+ *
+ * Copyright (C) 1999, 2001 Hewlett-Packard Co
+ * Copyright (C) 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * 99/12/18 David Mosberger	Added support for READ10/WRITE10 needed by linux v2.3.33
+ */
+#include <linux/config.h>
+#include <linux/blk.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+
+#include <scsi/scsi.h>
+
+#include <asm/irq.h>
+
+#include "scsi.h"
+#include "sd.h"
+#include "hosts.h"
+#include "simscsi.h"
+
+#define DEBUG_SIMSCSI	1
+
+/* Simulator system calls: */
+
+#define SSC_OPEN			50
+#define SSC_CLOSE			51
+#define SSC_READ			52
+#define SSC_WRITE			53
+#define SSC_GET_COMPLETION		54
+#define SSC_WAIT_COMPLETION		55
+
+#define SSC_WRITE_ACCESS		2
+#define SSC_READ_ACCESS			1
+
+#ifdef DEBUG_SIMSCSI
+  int simscsi_debug;
+# define DBG	simscsi_debug
+#else
+# define DBG	0
+#endif
+
+#if 0
+struct timer_list disk_timer;
+#else
+static void simscsi_interrupt (unsigned long val);
+DECLARE_TASKLET(simscsi_tasklet, simscsi_interrupt, 0);
+#endif
+
+struct disk_req {
+	unsigned long addr;
+	unsigned len;
+};
+
+struct disk_stat {
+	int fd;
+	unsigned count;
+};
+
+extern long ia64_ssc (long arg0, long arg1, long arg2, long arg3, int nr);
+
+static int desc[8] = { -1, -1, -1, -1, -1, -1, -1, -1 };
+
+static struct queue_entry {
+	Scsi_Cmnd *sc;
+} queue[SIMSCSI_REQ_QUEUE_LEN];
+
+static int rd, wr;
+static atomic_t num_reqs = ATOMIC_INIT(0);
+
+/* base name for default disks */
+static char *simscsi_root = DEFAULT_SIMSCSI_ROOT;
+
+#define MAX_ROOT_LEN	128
+
+/*
+ * used to setup a new base for disk images
+ * to use /foo/bar/disk[a-z] as disk images
+ * you have to specify simscsi=/foo/bar/disk on the command line
+ */
+static int __init
+simscsi_setup (char *s)
+{
+	/* XXX Fix me we may need to strcpy() ? */
+	if (strlen(s) > MAX_ROOT_LEN) {
+		printk("simscsi_setup: prefix too long---using default %s\n", simscsi_root);
+	}
+	simscsi_root = s;
+	return 1;
+}
+
+__setup("simscsi=", simscsi_setup);
+
+static void
+simscsi_interrupt (unsigned long val)
+{
+	unsigned long flags;
+	Scsi_Cmnd *sc;
+
+	spin_lock_irqsave(&io_request_lock, flags);
+	{
+		while ((sc = queue[rd].sc) != 0) {
+			atomic_dec(&num_reqs);
+			queue[rd].sc = 0;
+			if (DBG)
+				printk("simscsi_interrupt: done with %ld\n", sc->serial_number);
+			(*sc->scsi_done)(sc);
+			rd = (rd + 1) % SIMSCSI_REQ_QUEUE_LEN;
+		}
+	}
+	spin_unlock_irqrestore(&io_request_lock, flags);
+}
+
+int
+simscsi_detect (Scsi_Host_Template *templ)
+{
+	templ->proc_name = "simscsi";
+#if 0
+	init_timer(&disk_timer);
+	disk_timer.function = simscsi_interrupt;
+#endif
+	return 1;	/* fake one SCSI host adapter */
+}
+
+int
+simscsi_release (struct Scsi_Host *host)
+{
+	return 0;	/* this is easy...  */
+}
+
+const char *
+simscsi_info (struct Scsi_Host *host)
+{
+	return "simulated SCSI host adapter";
+}
+
+int
+simscsi_abort (Scsi_Cmnd *cmd)
+{
+	printk ("simscsi_abort: unimplemented\n");
+	return SCSI_ABORT_SUCCESS;
+}
+
+int
+simscsi_reset (Scsi_Cmnd *cmd, unsigned int reset_flags)
+{
+	printk ("simscsi_reset: unimplemented\n");
+	return SCSI_RESET_SUCCESS;
+}
+
+int
+simscsi_biosparam (Disk *disk, kdev_t n, int ip[])
+{
+	int size = disk->capacity;
+
+	ip[0] = 64;
+	ip[1] = 32;
+	ip[2] = size >> 11;
+	return 0;
+}
+
+static void
+simscsi_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset, unsigned long len)
+{
+	struct disk_stat stat;
+	struct disk_req req;
+
+	req.addr = __pa(sc->request_buffer);
+	req.len  = len;			/* # of bytes to transfer */
+
+	if (sc->request_bufflen < req.len)
+		return;
+
+	stat.fd = desc[sc->target];
+	if (DBG)
+		printk("simscsi_%s @ %lx (off %lx)\n",
+		       mode == SSC_READ ? "read":"write", req.addr, offset);
+	ia64_ssc(stat.fd, 1, __pa(&req), offset, mode);
+	ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
+
+	if (stat.count == req.len) {
+		sc->result = GOOD;
+	} else {
+		sc->result = DID_ERROR << 16;
+	}
+}
+
+static void
+simscsi_sg_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset)
+{
+	int list_len = sc->use_sg;
+	struct scatterlist *sl = (struct scatterlist *)sc->buffer;
+	struct disk_stat stat;
+	struct disk_req req;
+
+	stat.fd = desc[sc->target];
+
+	while (list_len) {
+		req.addr = __pa(sl->address);
+		req.len  = sl->length;
+		if (DBG)
+			printk("simscsi_sg_%s @ %lx (off %lx) use_sg=%d len=%d\n",
+			       mode == SSC_READ ? "read":"write", req.addr, offset,
+			       list_len, sl->length);
+		ia64_ssc(stat.fd, 1, __pa(&req), offset, mode);
+		ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
+
+		/* should not happen in our case */
+		if (stat.count != req.len) {
+			sc->result = DID_ERROR << 16;
+			return;
+		}
+		offset +=  sl->length;
+		sl++;
+		list_len--;
+	}
+	sc->result = GOOD;
+}
+
+/*
+ * function handling both READ_6/WRITE_6 (non-scatter/gather mode)
+ * commands.
+ * Added 02/26/99 S.Eranian
+ */
+static void
+simscsi_readwrite6 (Scsi_Cmnd *sc, int mode)
+{
+	unsigned long offset;
+
+	offset = (((sc->cmnd[1] & 0x1f) << 16) | (sc->cmnd[2] << 8) | sc->cmnd[3])*512;
+	if (sc->use_sg > 0)
+		simscsi_sg_readwrite(sc, mode, offset);
+	else
+		simscsi_readwrite(sc, mode, offset, sc->cmnd[4]*512);
+}
+
+
+static void
+simscsi_readwrite10 (Scsi_Cmnd *sc, int mode)
+{
+	unsigned long offset;
+
+	offset = (  (sc->cmnd[2] << 24) | (sc->cmnd[3] << 16)
+		  | (sc->cmnd[4] <<  8) | (sc->cmnd[5] <<  0))*512;
+	if (sc->use_sg > 0)
+		simscsi_sg_readwrite(sc, mode, offset);
+	else
+		simscsi_readwrite(sc, mode, offset, ((sc->cmnd[7] << 8) | sc->cmnd[8])*512);
+}
+
+int
+simscsi_queuecommand (Scsi_Cmnd *sc, void (*done)(Scsi_Cmnd *))
+{
+	char fname[MAX_ROOT_LEN+16];
+	char *buf;
+#if DEBUG_SIMSCSI
+	register long sp asm ("sp");
+
+	if (DBG)
+		printk("simscsi_queuecommand: target=%d,cmnd=%u,sc=%lu,sp=%lx,done=%p\n",
+		       sc->target, sc->cmnd[0], sc->serial_number, sp, done);
+#endif
+
+	sc->result = DID_BAD_TARGET << 16;
+	sc->scsi_done = done;
+	if (sc->target <= 7 && sc->lun == 0) {
+		switch (sc->cmnd[0]) {
+		      case INQUIRY:
+			if (sc->request_bufflen < 35) {
+				break;
+			}
+			sprintf (fname, "%s%c", simscsi_root, 'a' + sc->target);
+			desc[sc->target] = ia64_ssc (__pa(fname), SSC_READ_ACCESS|SSC_WRITE_ACCESS,
+						     0, 0, SSC_OPEN);
+			if (desc[sc->target] < 0) {
+				/* disk doesn't exist... */
+				break;
+			}
+			buf = sc->request_buffer;
+			buf[0] = 0;	/* magnetic disk */
+			buf[1] = 0;	/* not a removable medium */
+			buf[2] = 2;	/* SCSI-2 compliant device */
+			buf[3] = 2;	/* SCSI-2 response data format */
+			buf[4] = 31;	/* additional length (bytes) */
+			buf[5] = 0;	/* reserved */
+			buf[6] = 0;	/* reserved */
+			buf[7] = 0;	/* various flags */
+			memcpy(buf + 8, "HP      SIMULATED DISK  0.00",  28);
+			sc->result = GOOD;
+			break;
+
+		      case TEST_UNIT_READY:
+			sc->result = GOOD;
+			break;
+
+		      case READ_6:
+			if (desc[sc->target] < 0 )
+				break;
+			simscsi_readwrite6(sc, SSC_READ);
+			break;
+
+		      case READ_10:
+			if (desc[sc->target] < 0 )
+				break;
+			simscsi_readwrite10(sc, SSC_READ);
+			break;
+
+		      case WRITE_6:
+			if (desc[sc->target] < 0)
+				break;
+			simscsi_readwrite6(sc, SSC_WRITE);
+			break;
+
+		      case WRITE_10:
+			if (desc[sc->target] < 0)
+				break;
+			simscsi_readwrite10(sc, SSC_WRITE);
+			break;
+
+
+		      case READ_CAPACITY:
+			if (desc[sc->target] < 0 || sc->request_bufflen < 8) {
+				break;
+			}
+			buf = sc->request_buffer;
+
+			/* pretend to be a 1GB disk (partition table contains real stuff): */
+			buf[0] = 0x00;
+			buf[1] = 0x1f;
+			buf[2] = 0xff;
+			buf[3] = 0xff;
+			/* set block size of 512 bytes: */
+			buf[4] = 0;
+			buf[5] = 0;
+			buf[6] = 2;
+			buf[7] = 0;
+			sc->result = GOOD;
+			break;
+
+		      case MODE_SENSE:
+			printk("MODE_SENSE\n");
+			break;
+
+		      case START_STOP:
+			printk("START_STOP\n");
+			break;
+
+		      default:
+			panic("simscsi: unknown SCSI command %u\n", sc->cmnd[0]);
+		}
+	}
+	if (sc->result == DID_BAD_TARGET) {
+		sc->result |= DRIVER_SENSE << 24;
+		sc->sense_buffer[0] = 0x70;
+		sc->sense_buffer[2] = 0x00;
+	}
+	if (atomic_read(&num_reqs) >= SIMSCSI_REQ_QUEUE_LEN) {
+		panic("Attempt to queue command while command is pending!!");
+	}
+	atomic_inc(&num_reqs);
+	queue[wr].sc = sc;
+	wr = (wr + 1) % SIMSCSI_REQ_QUEUE_LEN;
+
+#if 0
+	if (!timer_pending(&disk_timer)) {
+		disk_timer.expires = jiffies;
+		add_timer(&disk_timer);
+	}
+#else
+	tasklet_schedule(&simscsi_tasklet);
+#endif
+	return 0;
+}
+
+
+static Scsi_Host_Template driver_template = SIMSCSI;
+
+#include "scsi_module.c"
diff -urN linux-2.4.16/drivers/scsi/simscsi.h lia64-2.4/drivers/scsi/simscsi.h
--- linux-2.4.16/drivers/scsi/simscsi.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/drivers/scsi/simscsi.h	Wed Feb 21 16:31:25 2001
@@ -0,0 +1,39 @@
+/*
+ * Simulated SCSI driver.
+ *
+ * Copyright (C) 1999 Hewlett-Packard Co
+ * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef SIMSCSI_H
+#define SIMSCSI_H
+
+#define SIMSCSI_REQ_QUEUE_LEN	64
+
+#define DEFAULT_SIMSCSI_ROOT	"/var/ski-disks/sd"
+
+extern int simscsi_detect (Scsi_Host_Template *);
+extern int simscsi_release (struct Scsi_Host *);
+extern const char *simscsi_info (struct Scsi_Host *);
+extern int simscsi_queuecommand (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
+extern int simscsi_abort (Scsi_Cmnd *);
+extern int simscsi_reset (Scsi_Cmnd *, unsigned int);
+extern int simscsi_biosparam (Disk *, kdev_t, int[]);
+
+#define SIMSCSI {					\
+	detect:			simscsi_detect,		\
+	release:		simscsi_release,	\
+	info:			simscsi_info,		\
+	queuecommand:		simscsi_queuecommand,	\
+	abort:			simscsi_abort,		\
+	reset:			simscsi_reset,		\
+	bios_param:		simscsi_biosparam,	\
+	can_queue:		SIMSCSI_REQ_QUEUE_LEN,	\
+	this_id:		-1,			\
+	sg_tablesize:		SG_ALL,			\
+	cmd_per_lun:		SIMSCSI_REQ_QUEUE_LEN,	\
+	present:		0,			\
+	unchecked_isa_dma:	0,			\
+	use_clustering:		DISABLE_CLUSTERING	\
+}
+
+#endif /* SIMSCSI_H */
diff -urN linux-2.4.16/drivers/usb/usb-ohci.c lia64-2.4/drivers/usb/usb-ohci.c
--- linux-2.4.16/drivers/usb/usb-ohci.c	Mon Nov 26 11:19:04 2001
+++ lia64-2.4/drivers/usb/usb-ohci.c	Mon Nov 26 11:22:02 2001
@@ -2351,21 +2351,22 @@
 {
 	ohci_t * ohci;
 	struct usb_bus * bus;
+	dma_addr_t bus_addr;
 
 	ohci = (ohci_t *) kmalloc (sizeof *ohci, GFP_KERNEL);
 	if (!ohci)
 		return NULL;
-		
+
 	memset (ohci, 0, sizeof (ohci_t));
 
-	ohci->hcca = pci_alloc_consistent (dev, sizeof *ohci->hcca,
-			&ohci->hcca_dma);
+	ohci->hcca = pci_alloc_consistent (dev, sizeof *ohci->hcca, &bus_addr);
         if (!ohci->hcca) {
                 kfree (ohci);
                 return NULL;
         }
         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 
+	ohci->hcca_dma = bus_addr;
 	ohci->disabled = 1;
 	ohci->sleeping = 0;
 	ohci->irq = -1;
diff -urN linux-2.4.16/drivers/video/fbmem.c lia64-2.4/drivers/video/fbmem.c
--- linux-2.4.16/drivers/video/fbmem.c	Mon Nov 26 11:19:06 2001
+++ lia64-2.4/drivers/video/fbmem.c	Mon Nov 26 11:22:05 2001
@@ -611,6 +611,8 @@
 	vma->vm_flags |= VM_IO;
 #elif defined(__sh__)
 	pgprot_val(vma->vm_page_prot) &= ~_PAGE_CACHABLE;
+#elif defined(__ia64__)
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 #else
 #warning What do we have to do here??
 #endif
diff -urN linux-2.4.16/drivers/video/vgacon.c lia64-2.4/drivers/video/vgacon.c
--- linux-2.4.16/drivers/video/vgacon.c	Wed Oct 24 10:17:58 2001
+++ lia64-2.4/drivers/video/vgacon.c	Wed Oct 24 10:24:37 2001
@@ -109,14 +109,7 @@
 static unsigned int    vga_default_font_height;	/* Height of default screen font */
 static unsigned char   vga_video_type;		/* Card type */
 static unsigned char   vga_hardscroll_enabled;
-#ifdef CONFIG_IA64_SOFTSDV_HACKS
-/*
- * SoftSDV doesn't have hardware assist VGA scrolling 
- */
-static unsigned char   vga_hardscroll_user_enable = 0;
-#else
 static unsigned char   vga_hardscroll_user_enable = 1;
-#endif
 static unsigned char   vga_font_is_default = 1;
 static int	       vga_vesa_blanked;
 static int	       vga_palette_blanked;
diff -urN linux-2.4.16/fs/devfs/base.c lia64-2.4/fs/devfs/base.c
--- linux-2.4.16/fs/devfs/base.c	Mon Nov  5 18:29:02 2001
+++ lia64-2.4/fs/devfs/base.c	Mon Nov  5 18:34:16 2001
@@ -1949,6 +1949,27 @@
     return master->slave;
 }   /*  End Function devfs_get_unregister_slave  */
 
+#ifdef CONFIG_DEVFS_GUID
+/**
+ *	devfs_unregister_slave - remove the slave that is unregistered when @master is unregistered.
+ *      Destroys the connection established by devfs_auto_unregister.
+ *
+ *	@master: The master devfs entry.
+ */
+
+void devfs_unregister_slave (devfs_handle_t master)
+{
+	devfs_handle_t slave;
+
+	if (master == NULL) return;
+
+	slave = master->slave;
+	if (slave) {
+		master->slave = NULL;
+		unregister (slave);
+	};
+}
+#endif /* CONFIG_DEVFS_GUID */
 
 /**
  *	devfs_get_name - Get the name for a device entry in its parent directory.
@@ -2126,6 +2147,9 @@
 EXPORT_SYMBOL(devfs_register_blkdev);
 EXPORT_SYMBOL(devfs_unregister_chrdev);
 EXPORT_SYMBOL(devfs_unregister_blkdev);
+#ifdef CONFIG_DEVFS_GUID
+EXPORT_SYMBOL(devfs_unregister_slave);
+#endif
 
 
 /**
diff -urN linux-2.4.16/fs/fcntl.c lia64-2.4/fs/fcntl.c
--- linux-2.4.16/fs/fcntl.c	Mon Sep 24 15:08:13 2001
+++ lia64-2.4/fs/fcntl.c	Mon Sep 24 15:23:46 2001
@@ -289,6 +289,7 @@
 			 * to fix this will be in libc.
 			 */
 			err = filp->f_owner.pid;
+			force_successful_syscall_return();
 			break;
 		case F_SETOWN:
 			lock_kernel();
diff -urN linux-2.4.16/fs/partitions/Config.in lia64-2.4/fs/partitions/Config.in
--- linux-2.4.16/fs/partitions/Config.in	Mon Aug 20 10:19:20 2001
+++ lia64-2.4/fs/partitions/Config.in	Mon Aug 20 12:21:01 2001
@@ -24,6 +24,8 @@
       bool '    Minix subpartition support' CONFIG_MINIX_SUBPARTITION
       bool '    Solaris (x86) partition table support' CONFIG_SOLARIS_X86_PARTITION
       bool '    Unixware slices support' CONFIG_UNIXWARE_DISKLABEL
+      bool '    EFI GUID Partition support' CONFIG_EFI_PARTITION
+      dep_bool '    /dev/guid support (EXPERIMENTAL)' CONFIG_DEVFS_GUID $CONFIG_DEVFS_FS $CONFIG_EFI_PARTITION
    fi
    dep_bool '  Windows Logical Disk Manager (Dynamic Disk) support' CONFIG_LDM_PARTITION $CONFIG_EXPERIMENTAL
    if [ "$CONFIG_LDM_PARTITION" = "y" ]; then
diff -urN linux-2.4.16/fs/partitions/Makefile lia64-2.4/fs/partitions/Makefile
--- linux-2.4.16/fs/partitions/Makefile	Thu Jul 26 16:30:04 2001
+++ lia64-2.4/fs/partitions/Makefile	Mon Aug 13 23:46:06 2001
@@ -24,6 +24,7 @@
 obj-$(CONFIG_SUN_PARTITION) += sun.o
 obj-$(CONFIG_ULTRIX_PARTITION) += ultrix.o
 obj-$(CONFIG_IBM_PARTITION) += ibm.o
+obj-$(CONFIG_EFI_PARTITION) += efi.o
 
 include $(TOPDIR)/Rules.make
 
diff -urN linux-2.4.16/fs/partitions/check.c lia64-2.4/fs/partitions/check.c
--- linux-2.4.16/fs/partitions/check.c	Wed Oct 24 10:17:59 2001
+++ lia64-2.4/fs/partitions/check.c	Wed Oct 24 10:24:48 2001
@@ -33,6 +33,7 @@
 #include "sun.h"
 #include "ibm.h"
 #include "ultrix.h"
+#include "efi.h"
 
 extern int *blk_size[];
 
@@ -42,6 +43,9 @@
 #ifdef CONFIG_ACORN_PARTITION
 	acorn_partition,
 #endif
+#ifdef CONFIG_EFI_PARTITION
+	efi_partition,		/* this must come before msdos */
+#endif
 #ifdef CONFIG_LDM_PARTITION
 	ldm_partition,		/* this must come before msdos */
 #endif
@@ -75,6 +79,20 @@
 	NULL
 };
 
+#ifdef CONFIG_DEVFS_GUID
+static devfs_handle_t guid_top_handle;
+
+#define GUID_UNPARSED_LEN 36
+static void
+uuid_unparse_1(efi_guid_t *guid, char *out)
+{
+	sprintf(out, "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x",
+		guid->data1, guid->data2, guid->data3,
+ 		guid->data4[0], guid->data4[1], guid->data4[2], guid->data4[3],
+		guid->data4[4], guid->data4[5], guid->data4[6], guid->data4[7]);
+}
+#endif
+
 /*
  *	This is ucking fugly but its probably the best thing for 2.4.x
  *	Take it as a clear reminder than we should put the device name
@@ -267,6 +285,103 @@
 	devfs_register_partitions (hd, i, hd->sizes ? 0 : 1);
 }
 
+#ifdef CONFIG_DEVFS_GUID
+/*
+  devfs_register_guid: create a /dev/guid entry for a disk or partition
+                       if it has a GUID.
+
+  The /dev/guid entry will be a symlink to the "real" devfs device.
+  It is marked as "slave" of the real device,
+  to be automatically unregistered by devfs if that device is unregistered.
+
+  If the partition already had a /dev/guid entry, delete (unregister) it.
+  (If the disk was repartitioned, it's likely the old GUID entry will be wrong).
+
+  dev, minor:  Device for which an entry is to be created.
+
+  Prerequisites: dev->part[minor].guid must be either NULL or point
+                 to a valid kmalloc'ed GUID.
+*/
+
+static void devfs_register_guid (struct gendisk *dev, int minor)
+{
+	efi_guid_t *guid = dev->part[minor].guid;
+	devfs_handle_t guid_handle, slave,
+		real_master = dev->part[minor].de;
+	devfs_handle_t master = real_master;
+	char guid_link[GUID_UNPARSED_LEN + 1];
+	char dirname[128];
+	int pos, st;
+
+	if (!guid_top_handle)
+		guid_top_handle = devfs_mk_dir (NULL, "guid", NULL);
+
+	if (!guid || !master) return;
+
+	do {
+		slave = devfs_get_unregister_slave (master);
+		if (slave) {
+			if (slave == master || slave == real_master) {
+				printk (KERN_WARNING
+					"devfs_register_guid: infinite slave loop!\n");
+				return;
+			} else if (devfs_get_parent (slave) == guid_top_handle) {
+				printk (KERN_INFO
+					"devfs_register_guid: unregistering %s\n",
+					devfs_get_name (slave, NULL));
+				devfs_unregister_slave (master);
+				slave = NULL;
+			} else
+				master = slave;
+		};
+	} while (slave);
+
+	uuid_unparse_1 (guid, guid_link);
+	pos = devfs_generate_path (real_master, dirname + 3,
+				   sizeof (dirname) - 3);
+	if (pos < 0) {
+		printk (KERN_WARNING
+			"devfs_register_guid: error generating path: %d\n",
+			pos);
+		return;
+	};
+
+	strncpy (dirname + pos, "../", 3);
+
+	st = devfs_mk_symlink (guid_top_handle, guid_link,
+			       DEVFS_FL_DEFAULT,
+			       dirname + pos, &guid_handle, NULL);
+
+	if (st < 0) {
+		printk ("Error %d creating symlink\n", st);
+	} else {
+		devfs_auto_unregister (master, guid_handle);
+	};
+};
+
+/*
+  free_disk_guids: kfree all guid data structures alloced for
+  the disk device specified by (dev, minor) and all its partitions.
+
+  This function does not remove symlinks in /dev/guid.
+*/
+static void free_disk_guids (struct gendisk *dev, int minor)
+{
+	int i;
+	efi_guid_t *guid;
+
+	for (i = 0; i < dev->max_p; i++) {
+		guid = dev->part[minor + i].guid;
+		if (!guid) continue;
+		kfree (guid);
+		dev->part[minor + i].guid = NULL;
+	};
+}
+#else
+#define devfs_register_guid(dev, minor)
+#define free_disk_guids(dev, minor)
+#endif /* CONFIG_DEVFS_GUID */
+
 #ifdef CONFIG_DEVFS_FS
 static void devfs_register_partition (struct gendisk *dev, int minor, int part)
 {
@@ -275,7 +390,11 @@
 	unsigned int devfs_flags = DEVFS_FL_DEFAULT;
 	char devname[16];
 
-	if (dev->part[minor + part].de) return;
+	/* Even if the devfs handle is still up-to-date,
+	   the GUID entry probably isn't */
+	if (dev->part[minor + part].de)
+		goto do_guid;
+
 	dir = devfs_get_parent (dev->part[minor].de);
 	if (!dir) return;
 	if ( dev->flags && (dev->flags[devnum] & GENHD_FL_REMOVABLE) )
@@ -286,6 +405,9 @@
 			    dev->major, minor + part,
 			    S_IFBLK | S_IRUSR | S_IWUSR,
 			    dev->fops, NULL);
+ do_guid:
+	devfs_register_guid (dev, minor + part);
+	return;
 }
 
 static struct unique_numspace disc_numspace = UNIQUE_NUMBERSPACE_INITIALISER;
@@ -299,7 +421,9 @@
 	char dirname[64], symlink[16];
 	static devfs_handle_t devfs_handle;
 
-	if (dev->part[minor].de) return;
+	if (dev->part[minor].de)
+		goto do_guid;
+
 	if ( dev->flags && (dev->flags[devnum] & GENHD_FL_REMOVABLE) )
 		devfs_flags |= DEVFS_FL_REMOVABLE;
 	if (dev->de_arr) {
@@ -327,6 +451,10 @@
 	devfs_auto_unregister (dev->part[minor].de, slave);
 	if (!dev->de_arr)
 		devfs_auto_unregister (slave, dir);
+
+ do_guid:
+	devfs_register_guid (dev, minor);
+	return;
 }
 #endif  /*  CONFIG_DEVFS_FS  */
 
@@ -350,6 +478,7 @@
 		dev->part[minor].de = NULL;
 		devfs_dealloc_unique_number (&disc_numspace,
 					     dev->part[minor].number);
+		free_disk_guids (dev, minor);
 	}
 #endif  /*  CONFIG_DEVFS_FS  */
 }
@@ -367,8 +496,21 @@
 void register_disk(struct gendisk *gdev, kdev_t dev, unsigned minors,
 	struct block_device_operations *ops, long size)
 {
+	int i;
+
 	if (!gdev)
 		return;
+
+#ifdef CONFIG_DEVFS_GUID
+	/* Initialize all guid fields to NULL (=^ not kmalloc'ed).
+	   It is assumed that drivers call register_disk after
+	   allocating the gen_hd structure, and call grok_partitions
+	   directly for a revalidate event, as those drives I've inspected
+	   (among which hd and sd) do. */
+	for (i = 0; i < gdev->max_p; i++)
+		gdev->part[MINOR(dev) + i].guid = NULL;
+#endif
+
 	grok_partitions(gdev, MINOR(dev)>>gdev->minor_shift, minors, size);
 }
 
@@ -385,6 +527,12 @@
 	/* No such device or no minors to use for partitions */
 	if (!size || minors == 1)
 		return;
+
+	/* In case this is a revalidation, free GUID memory.
+	   On the first call for this device,
+	   register_disk has set all entries to NULL,
+	   and nothing will happen. */
+	free_disk_guids (dev, first_minor);
 
 	if (dev->sizes) {
 		dev->sizes[first_minor] = size >> (BLOCK_SIZE_BITS - 9);
diff -urN linux-2.4.16/fs/partitions/efi.c lia64-2.4/fs/partitions/efi.c
--- linux-2.4.16/fs/partitions/efi.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/fs/partitions/efi.c	Wed Oct 10 16:53:19 2001
@@ -0,0 +1,789 @@
+/************************************************************
+ * EFI GUID Partition Table handling
+ * Per Intel EFI Specification v1.02
+ * http://developer.intel.com/technology/efi/efi.htm
+ * efi.[ch] by Matt Domsch <Matt_Domsch@dell.com>
+ *   Copyright 2000,2001 Dell Computer Corporation
+ *
+ * Note, the EFI Specification, v1.02, has a reference to
+ * Dr. Dobbs Journal, May 1994 (actually it's in May 1992)
+ * but that isn't the CRC function being used by EFI.  Intel's
+ * EFI Sample Implementation shows that they use the same function
+ * as was COPYRIGHT (C) 1986 Gary S. Brown.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *
+ * TODO:
+ *
+ * Changelog:
+ * Mon Oct 08 2001 Matt Domsch <Matt_Domsch@dell.com>
+ * - Change read_lba() to use the page cache per Al Viro's work.
+ * - print u64s properly on all architectures
+ * - fixed debug_printk(), now Dprintk()
+ *
+ * Mon Oct 01 2001 Matt Domsch <Matt_Domsch@dell.com>
+ * - Style cleanups
+ * - made most functions static
+ * - Endianness addition
+ * - remove test for second alternate header, as it's not per spec,
+ *   and is unnecessary.  There's now a method to read/write the last
+ *   sector of an odd-sized disk from user space.  No tools have ever
+ *   been released which used this code, so it's effectively dead.
+ * - Per Asit Mallick of Intel, added a test for a valid PMBR.
+ * - Added kernel command line option 'gpt' to override valid PMBR test.
+ *
+ * Wed Jun  6 2001 Martin Wilck <Martin.Wilck@Fujitsu-Siemens.com>
+ * - added devfs GUID support (/dev/guid) for mounting file systems
+ *   by the partition GUID. 
+ *
+ * Tue Dec  5 2000 Matt Domsch <Matt_Domsch@dell.com>
+ * - Moved crc32() to linux/lib, added efi_crc32().
+ *
+ * Thu Nov 30 2000 Matt Domsch <Matt_Domsch@dell.com>
+ * - Replaced Intel's CRC32 function with an equivalent
+ *   non-license-restricted version.
+ *
+ * Wed Oct 25 2000 Matt Domsch <Matt_Domsch@dell.com>
+ * - Fixed the last_lba() call to return the proper last block
+ *
+ * Thu Oct 12 2000 Matt Domsch <Matt_Domsch@dell.com>
+ * - Thanks to Andries Brouwer for his debugging assistance.
+ * - Code works, detects all the partitions.
+ *
+ ************************************************************/
+#include <linux/config.h>
+#include <linux/fs.h>
+#include <linux/genhd.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/blk.h>
+#include <linux/blkpg.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/crc32.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/byteorder.h>
+#include "check.h"
+#include "efi.h"
+
+#if CONFIG_BLK_DEV_MD
+extern void md_autodetect_dev(kdev_t dev);
+#endif
+
+/* Handle printing of 64-bit values */
+#if BITS_PER_LONG == 64
+#define PU64X "%lx"
+#else
+#define PU64X "%llx"
+#endif
+
+
+#undef EFI_DEBUG
+#ifdef EFI_DEBUG
+#define Dprintk(x...) printk(KERN_DEBUG x)
+#else
+#define Dprintk(x...)
+#endif
+
+/* This allows a kernel command line option 'gpt' to override
+ * the test for invalid PMBR.  Not __initdata because reloading
+ * the partition tables happens after init too.
+ */
+static int forcegpt;
+static int __init force_gpt(char *str)
+{
+	forcegpt = 1;
+	return 1;
+}
+
+__setup("gpt", force_gpt);
+
+
+
+
+/************************************************************
+ * efi_crc32()
+ * Requires:
+ *  - a buffer of length len
+ * Modifies: nothing
+ * Returns:
+ *  EFI-style CRC32 value for buf
+ *
+ * This function uses the crc32 function by Gary S. Brown,
+ * but seeds the function with ~0, and xor's with ~0 at the end.
+ ************************************************************/
+
+static inline u32 efi_crc32(const void *buf, unsigned long len)
+{
+	return (crc32(buf, len, ~0L) ^ ~0L);
+}
+
+
+/************************************************************
+ * le_guid_to_cpus()
+ * Requires: guid
+ * Modifies: guid in situ
+ * Returns: nothing
+ *
+ * This function converts a little endian efi_guid_t to the
+ * native cpu representation.  The EFI Spec. declares that all 
+ * on-disk structures are stored in little endian format.
+ * 
+ ************************************************************/
+
+static void le_guid_to_cpus(efi_guid_t * guid)
+{
+	le32_to_cpus(guid->data1);
+	le16_to_cpus(guid->data2);
+	le16_to_cpus(guid->data3);
+	/* no need to change data4. It's already an array of chars */
+	return;
+}
+
+/************************************************************
+ * le_part_attributes_to_cpus()
+ * Requires: attributes
+ * Modifies: attributes in situ
+ * Returns: nothing
+ *
+ * This function converts a little endian partition attributes
+ * struct to the native cpu representation.
+ * 
+ ************************************************************/
+
+static void le_part_attributes_to_cpus(GuidPartitionEntryAttributes_t * a)
+{
+	u64 *b = (u64 *) a;
+	*b = le64_to_cpu(*b);
+}
+
+/************************************************************
+ * is_pmbr_valid()
+ * Requires:
+ *  - mbr is a pointer to a legacy mbr structure
+ * Modifies: nothing
+ * Returns:
+ *  1 on true
+ *  0 on false
+ ************************************************************/
+static int is_pmbr_valid(LegacyMBR_t * mbr)
+{
+	int i, found = 0, signature = 0;
+	if (!mbr)
+		return 0;
+	signature = (le16_to_cpu(mbr->Signature) == MSDOS_MBR_SIGNATURE);
+	for (i = 0; signature && i < 4; i++) {
+		if (mbr->PartitionRecord[i].OSType ==
+		    EFI_PMBR_OSTYPE_EFI_GPT) {
+			found = 1;
+			break;
+		}
+	}
+	return (signature && found);
+}
+
+
+/************************************************************
+ * last_lba()
+ * Requires:
+ *  - struct gendisk hd
+ *  - struct block_device *bdev
+ * Modifies: nothing
+ * Returns:
+ *  Last LBA value on success.  This is stored (by sd and
+ *  ide-geometry) in
+ *  the part[0] entry for this disk, and is the number of
+ *  physical sectors available on the disk.
+ *  0 on error
+ ************************************************************/
+static u64 last_lba(struct gendisk *hd, struct block_device *bdev)
+{
+	if (!hd || !hd->part || !bdev)
+		return 0;
+	return hd->part[MINOR(to_kdev_t(bdev->bd_dev))].nr_sects - 1;
+}
+
+
+/************************************************************
+ * read_lba()
+ * Requires:
+ *  - hd is our disk device.
+ *  - bdev is our device major number
+ *  - lba is the logical block address desired (disk hardsector number)
+ *  - buffer is a buffer of size size into which data copied
+ *  - size_t count is size of the read (in bytes)
+ * Modifies:
+ *  - buffer
+ * Returns:
+ *  - count of bytes read
+ *  - 0 on error
+ ************************************************************/
+
+static size_t
+read_lba(struct gendisk *hd, struct block_device *bdev, u64 lba,
+	 u8 * buffer, size_t count)
+{
+
+	size_t totalreadcount = 0, bytesread = 0;
+	unsigned long blocksize;
+	int i;
+	Sector sect;
+	unsigned char *data = NULL;
+
+	if (!hd || !bdev || !buffer || !count)
+		return 0;
+
+	blocksize = get_hardsect_size(to_kdev_t(bdev->bd_dev));
+	if (!blocksize)
+		blocksize = 512;
+
+	for (i = 0; count > 0; i++) {
+		data = read_dev_sector(bdev, lba, &sect);
+		if (!data)
+			return totalreadcount;
+
+		bytesread =
+		    PAGE_CACHE_SIZE - (data -
+				       (unsigned char *) page_address(sect.
+								      v));
+		bytesread = min(bytesread, count);
+		memcpy(buffer, data, bytesread);
+		put_dev_sector(sect);
+
+		buffer += bytesread;
+		totalreadcount += bytesread;
+		count -= bytesread;
+		lba += (bytesread / blocksize);
+	}
+	return totalreadcount;
+}
+
+
+
+static void print_gpt_header(GuidPartitionTableHeader_t * gpt)
+{
+	Dprintk("GUID Partition Table Header\n");
+	if (!gpt)
+		return;
+	Dprintk("Signature      : " PU64X "\n", gpt->Signature);
+	Dprintk("Revision       : %x\n", gpt->Revision);
+	Dprintk("HeaderSize     : %x\n", gpt->HeaderSize);
+	Dprintk("HeaderCRC32    : %x\n", gpt->HeaderCRC32);
+	Dprintk("MyLBA          : " PU64X "\n", gpt->MyLBA);
+	Dprintk("AlternateLBA   : " PU64X "\n", gpt->AlternateLBA);
+	Dprintk("FirstUsableLBA : " PU64X "\n", gpt->FirstUsableLBA);
+	Dprintk("LastUsableLBA  : " PU64X "\n", gpt->LastUsableLBA);
+
+	Dprintk("PartitionEntryLBA : " PU64X "\n", gpt->PartitionEntryLBA);
+	Dprintk("NumberOfPartitionEntries : %x\n",
+		gpt->NumberOfPartitionEntries);
+	Dprintk("SizeOfPartitionEntry : %x\n", gpt->SizeOfPartitionEntry);
+	Dprintk("PartitionEntryArrayCRC32 : %x\n",
+		gpt->PartitionEntryArrayCRC32);
+
+	return;
+}
+
+
+
+/************************************************************
+ * alloc_read_gpt_entries()
+ * Requires:
+ *  - hd, bdev, gpt
+ * Modifies:
+ *  - nothing
+ * Returns:
+ *   ptes on success
+ *   NULL on error
+ * Notes: remember to free pte when you're done!
+ ************************************************************/
+static GuidPartitionEntry_t *
+alloc_read_gpt_entries(struct gendisk *hd,
+                       struct block_device *bdev,
+                       GuidPartitionTableHeader_t *gpt)
+{
+	u32 i, j;
+	size_t count;
+	GuidPartitionEntry_t *pte;
+	if (!hd || !bdev || !gpt)
+		return NULL;
+
+	count = gpt->NumberOfPartitionEntries * gpt->SizeOfPartitionEntry;
+	Dprintk("ReadGPTEs() kmallocing %x bytes\n", count);
+	if (!count)
+		return NULL;
+	pte = kmalloc(count, GFP_KERNEL);
+	if (!pte)
+		return NULL;
+	memset(pte, 0, count);
+
+	if (read_lba(hd, bdev, gpt->PartitionEntryLBA, (u8 *) pte,
+		     count) < count) {
+		kfree(pte);
+		return NULL;
+	}
+	/* Fixup endianness */
+	for (i = 0; i < gpt->NumberOfPartitionEntries; i++) {
+		le_guid_to_cpus(&pte[i].PartitionTypeGuid);
+		le_guid_to_cpus(&pte[i].UniquePartitionGuid);
+		le64_to_cpus(pte[i].StartingLBA);
+		le64_to_cpus(pte[i].EndingLBA);
+		le_part_attributes_to_cpus(&pte[i].Attributes);
+		for (j = 0; j < (72 / sizeof(efi_char16_t)); j++) {
+			le16_to_cpus((u16) (pte[i].PartitionName[j]));
+		}
+	}
+
+	return pte;
+}
+
+
+
+/************************************************************
+ * alloc_read_gpt_header()
+ * Requires:
+ *  - hd is our struct gendisk
+ *  - dev is our device major number
+ *  - lba is the Logical Block Address of the partition table
+ *  - gpt is a buffer into which the GPT will be put
+ *  - pte is a buffer into which the PTEs will be put
+ * Modifies:
+ *  - gpt and pte
+ * Returns:
+ *   1 on success
+ *   0 on error
+ ************************************************************/
+
+static GuidPartitionTableHeader_t *alloc_read_gpt_header(struct gendisk
+							 *hd,
+							 struct
+							 block_device
+							 *bdev, u64 lba)
+{
+	GuidPartitionTableHeader_t *gpt;
+	if (!hd || !bdev)
+		return NULL;
+
+	gpt = kmalloc(sizeof(GuidPartitionTableHeader_t), GFP_KERNEL);
+	if (!gpt)
+		return NULL;
+	memset(gpt, 0, sizeof(GuidPartitionTableHeader_t));
+
+	Dprintk("GPTH() calling read_lba().\n");
+	if (read_lba(hd, bdev, lba, (u8 *) gpt,
+		     sizeof(GuidPartitionTableHeader_t)) <
+	    sizeof(GuidPartitionTableHeader_t)) {
+		Dprintk("ReadGPTH(" PU64X ") read failed.\n", lba);
+		kfree(gpt);
+		return NULL;
+	}
+
+	/* Fixup endianness */
+	le64_to_cpus(gpt->Signature);
+	le32_to_cpus(gpt->Revision);
+	le32_to_cpus(gpt->HeaderSize);
+	le32_to_cpus(gpt->HeaderCRC32);
+	le32_to_cpus(gpt->Reserved1);
+	le64_to_cpus(gpt->MyLBA);
+	le64_to_cpus(gpt->AlternateLBA);
+	le64_to_cpus(gpt->FirstUsableLBA);
+	le64_to_cpus(gpt->LastUsableLBA);
+	le_guid_to_cpus(&gpt->DiskGUID);
+	le64_to_cpus(gpt->PartitionEntryLBA);
+	le32_to_cpus(gpt->NumberOfPartitionEntries);
+	le32_to_cpus(gpt->SizeOfPartitionEntry);
+	le32_to_cpus(gpt->PartitionEntryArrayCRC32);
+
+	print_gpt_header(gpt);
+
+	return gpt;
+}
+
+
+
+/************************************************************
+ * is_gpt_valid()
+ * Requires:
+ *  - gd points to our struct gendisk
+ *  - dev is our device major number
+ *  - lba is the logical block address of the GPTH to test
+ *  - gpt is a GPTH if it's valid
+ *  - ptes is a PTEs if it's valid
+ * Modifies:
+ *  - gpt and ptes
+ * Returns:
+ *   1 if valid
+ *   0 on error
+ ************************************************************/
+static int
+is_gpt_valid(struct gendisk *hd, struct block_device *bdev, u64 lba,
+	     GuidPartitionTableHeader_t ** gpt,
+	     GuidPartitionEntry_t ** ptes)
+{
+	u32 crc, origcrc;
+
+	if (!hd || !bdev || !gpt || !ptes)
+		return 0;
+	if (!(*gpt = alloc_read_gpt_header(hd, bdev, lba)))
+		return 0;
+
+	/* Check the GUID Partition Table Signature */
+	if ((*gpt)->Signature != GPT_HEADER_SIGNATURE) {
+		Dprintk("GUID Partition Table Header Signature is wrong: "
+			PU64X " != " PU64X "\n", (*gpt)->Signature,
+			GPT_HEADER_SIGNATURE);
+		kfree(*gpt);
+		*gpt = NULL;
+		return 0;
+	}
+
+	/* Check the GUID Partition Table CRC */
+	origcrc = (*gpt)->HeaderCRC32;
+	(*gpt)->HeaderCRC32 = 0;
+	crc =
+	    efi_crc32((const unsigned char *) (*gpt), (*gpt)->HeaderSize);
+
+
+	if (crc != origcrc) {
+		Dprintk
+		    ("GUID Partition Table Header CRC is wrong: %x != %x\n",
+		     (*gpt)->HeaderCRC32, origcrc);
+		kfree(*gpt);
+		*gpt = NULL;
+		return 0;
+	}
+	(*gpt)->HeaderCRC32 = origcrc;
+
+	/* Check that the MyLBA entry points to the LBA that contains
+	 * the GUID Partition Table */
+	if ((*gpt)->MyLBA != lba) {
+		Dprintk("GPT MyLBA incorrect: " PU64X " != " PU64X "\n",
+			(*gpt)->MyLBA, lba);
+		kfree(*gpt);
+		*gpt = NULL;
+		return 0;
+	}
+
+	if (!(*ptes = alloc_read_gpt_entries(hd, bdev, *gpt))) {
+		Dprintk("read PTEs failed.\n");
+		kfree(*gpt);
+		*gpt = NULL;
+		return 0;
+	}
+
+	/* Check the GUID Partition Entry Array CRC */
+	crc = efi_crc32((const unsigned char *) (*ptes),
+			(*gpt)->NumberOfPartitionEntries *
+			(*gpt)->SizeOfPartitionEntry);
+
+	if (crc != (*gpt)->PartitionEntryArrayCRC32) {
+		Dprintk
+		    ("GUID Partitition Entry Array CRC check failed.\n");
+		kfree(*gpt);
+		*gpt = NULL;
+		kfree(*ptes);
+		*ptes = NULL;
+		return 0;
+	}
+
+
+	/* We're done, all's well */
+	return 1;
+}
+
+
+
+/************************************************************
+ * find_valid_gpt()
+ * Requires:
+ *  - gd points to our struct gendisk
+ *  - dev is our device major number
+ *  - gpt is a GPTH if it's valid
+ *  - ptes is a PTE
+ * Modifies:
+ *  - gpt & ptes
+ * Returns:
+ *   1 if valid
+ *   0 on error
+ ************************************************************/
+static int
+find_valid_gpt(struct gendisk *hd, struct block_device *bdev,
+	       GuidPartitionTableHeader_t ** gpt,
+	       GuidPartitionEntry_t ** ptes)
+{
+	int good_pgpt = 0, good_agpt = 0, good_pmbr = 0;
+	GuidPartitionTableHeader_t *pgpt = NULL, *agpt = NULL;
+	GuidPartitionEntry_t *pptes = NULL, *aptes = NULL;
+	LegacyMBR_t *legacyMbr = NULL;
+	u64 lastlba;
+	if (!hd || !bdev || !gpt || !ptes)
+		return 0;
+
+	lastlba = last_lba(hd, bdev);
+	/* Check the Primary GPT */
+	good_pgpt = is_gpt_valid(hd, bdev, GPT_PRIMARY_PARTITION_TABLE_LBA,
+				 &pgpt, &pptes);
+	if (good_pgpt) {
+		/* Primary GPT is OK, check the alternate and warn if bad */
+		good_agpt = is_gpt_valid(hd, bdev, pgpt->AlternateLBA,
+					 &agpt, &aptes);
+		if (!good_agpt) {
+			printk(KERN_WARNING
+			       "Alternate GPT is invalid, using primary GPT.\n");
+		}
+
+		*gpt = pgpt;
+		*ptes = pptes;
+		if (agpt)
+			kfree(agpt);
+		if (aptes)
+			kfree(aptes);
+	} /* if primary is valid */
+	else {
+		/* Primary GPT is bad, check the Alternate GPT */
+		good_agpt = is_gpt_valid(hd, bdev, lastlba, &agpt, &aptes);
+		if (good_agpt) {
+			/* Primary is bad, alternate is good.
+			   Return values from the alternate and warn.
+			 */
+			printk(KERN_WARNING
+			       "Primary GPT is invalid, using alternate GPT.\n");
+			*gpt = agpt;
+			*ptes = aptes;
+		}
+	}
+
+	/* Now test for valid PMBR */
+	/* This will be added to the EFI Spec. per Intel after v1.02. */
+	if (good_pgpt || good_agpt) {
+		legacyMbr = kmalloc(sizeof(*legacyMbr), GFP_KERNEL);
+		if (legacyMbr) {
+			memset(legacyMbr, 0, sizeof(*legacyMbr));
+			read_lba(hd, bdev, 0, (u8 *) legacyMbr,
+				 sizeof(*legacyMbr));
+			good_pmbr = is_pmbr_valid(legacyMbr);
+			kfree(legacyMbr);
+		}
+		if (good_pmbr)
+			return 1;
+		if (!forcegpt) {
+			printk
+			    (" Warning: Disk has a valid GPT signature but invalid PMBR.\n");
+			printk(KERN_WARNING
+			       "  Assuming this disk is *not* a GPT disk anymore.\n");
+			printk(KERN_WARNING
+			       "  Use gpt kernel option to override.  Use GNU Parted to correct disk.\n");
+		} else {
+			printk(KERN_WARNING
+			       "  Warning: Disk has a valid GPT signature but invalid PMBR.\n");
+			printk(KERN_WARNING
+			       "  Use GNU Parted to correct disk.\n");
+			printk(KERN_WARNING
+			       "  gpt option taken, disk treated as GPT.\n");
+			return 1;
+		}
+	}
+
+	/* Both primary and alternate GPTs are bad, and/or PMBR is invalid.
+	 * This isn't our disk, return 0.
+	 */
+	if (pgpt) {
+		kfree(pgpt);
+		pgpt = NULL;
+	}
+	if (agpt) {
+		kfree(agpt);
+		agpt = NULL;
+	}
+	if (pptes) {
+		kfree(pptes);
+		pptes = NULL;
+	}
+	if (aptes) {
+		kfree(aptes);
+		aptes = NULL;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_DEVFS_GUID
+/* set_partition_guid */
+/* Fill in the GUID field of the partition.
+   It is set to NULL by register_disk before. */
+static void
+set_partition_guid(struct gendisk *hd,
+		   const int minor, const efi_guid_t * guid)
+{
+	efi_guid_t *part_guid = hd->part[minor].guid;
+
+	if (!guid || !hd)
+		return;
+
+	part_guid = kmalloc(sizeof(efi_guid_t), GFP_KERNEL);
+
+	if (part_guid) {
+		memcpy(part_guid, guid, sizeof(efi_guid_t));
+	} else {
+		printk(KERN_WARNING
+		       "add_gpt_partitions: cannot allocate GUID memory!\n");
+	};
+
+	hd->part[minor].guid = part_guid;
+}
+#else
+#define set_partition_guid(hd, minor, guid)
+#endif				/* CONFIG_DEVFS_GUID */
+
+/*
+ * Create devices for each entry in the GUID Partition Table Entries.
+ * The first block of each partition is a Legacy MBR.
+ *
+ * We do not create a Linux partition for GPT, but
+ * only for the actual data partitions.
+ * Returns:
+ * -1 if unable to read the partition table
+ *  0 if this isn't our partition table
+ *  1 if successful
+ *
+ */
+
+static int
+add_gpt_partitions(struct gendisk *hd, struct block_device *bdev,
+		   int nextminor)
+{
+	GuidPartitionTableHeader_t *gpt = NULL;
+	GuidPartitionEntry_t *ptes = NULL;
+	u32 i, nummade = 0;
+
+	efi_guid_t unusedGuid = UNUSED_ENTRY_GUID;
+#if CONFIG_BLK_DEV_MD
+	efi_guid_t raidGuid = PARTITION_LINUX_RAID_GUID;
+#endif
+
+	if (!hd || !bdev)
+		return -1;
+
+	if (!find_valid_gpt(hd, bdev, &gpt, &ptes) || !gpt || !ptes) {
+		if (gpt)
+			kfree(gpt);
+		if (ptes)
+			kfree(ptes);
+		return 0;
+	}
+
+	Dprintk("GUID Partition Table is valid!  Yea!\n");
+
+	set_partition_guid(hd, nextminor - 1, &(gpt->DiskGUID));
+
+	for (i = 0; i < gpt->NumberOfPartitionEntries &&
+	     nummade < (hd->max_p - 1); i++) {
+		if (!efi_guidcmp(unusedGuid, ptes[i].PartitionTypeGuid))
+			continue;
+
+		add_gd_partition(hd, nextminor, ptes[i].StartingLBA,
+				 (ptes[i].EndingLBA - ptes[i].StartingLBA +
+				  1));
+
+		set_partition_guid(hd, nextminor,
+				   &(ptes[i].UniquePartitionGuid));
+
+		/* If there's this is a RAID volume, tell md */
+#if CONFIG_BLK_DEV_MD
+		if (!efi_guidcmp(raidGuid, ptes[i].PartitionTypeGuid)) {
+			md_autodetect_dev(MKDEV
+					  (MAJOR(to_kdev_t(bdev->bd_dev)),
+					   nextminor));
+		}
+#endif
+		nummade++;
+		nextminor++;
+
+	}
+	kfree(ptes);
+	kfree(gpt);
+	printk("\n");
+	return 1;
+
+}
+
+
+/*
+ * efi_partition()
+ *
+ * If the first block on the disk is a legacy MBR,
+ * it will get handled by msdos_partition().
+ * If it's a Protective MBR, we'll handle it here.
+ *
+ * set_blocksize() calls are necessary to be able to read
+ * a disk with an odd number of 512-byte sectors, as the
+ * default BLOCK_SIZE of 1024 bytes won't let that last
+ * sector be read otherwise.
+ *
+ * Returns:
+ * -1 if unable to read the partition table
+ *  0 if this isn't our partitoin table
+ *  1 if successful
+ *
+ */
+
+int
+efi_partition(struct gendisk *hd, struct block_device *bdev,
+	      unsigned long first_sector, int first_part_minor)
+{
+
+	kdev_t dev = to_kdev_t(bdev->bd_dev);
+	int hardblocksize = get_hardsect_size(dev);
+	int orig_blksize_size = BLOCK_SIZE;
+	int rc = 0;
+
+	/* Need to change the block size that the block layer uses */
+	if (blksize_size[MAJOR(dev)]) {
+		orig_blksize_size = blksize_size[MAJOR(dev)][MINOR(dev)];
+	}
+
+	if (orig_blksize_size != hardblocksize)
+		set_blocksize(dev, hardblocksize);
+
+	rc = add_gpt_partitions(hd, bdev, first_part_minor);
+
+	/* change back */
+	if (orig_blksize_size != hardblocksize)
+		set_blocksize(dev, orig_blksize_size);
+
+	return rc;
+}
+
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-indent-level: 4
+ * c-brace-imaginary-offset: 0
+ * c-brace-offset: -4
+ * c-argdecl-indent: 4
+ * c-label-offset: -4
+ * c-continued-statement-offset: 4
+ * c-continued-brace-offset: 0
+ * indent-tabs-mode: nil
+ * tab-width: 8
+ * End:
+ */
diff -urN linux-2.4.16/fs/partitions/efi.h lia64-2.4/fs/partitions/efi.h
--- linux-2.4.16/fs/partitions/efi.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/fs/partitions/efi.h	Mon Nov 26 18:09:13 2001
@@ -0,0 +1,156 @@
+/************************************************************
+ * EFI GUID Partition Table
+ * Per Intel EFI Specification v1.02
+ * http://developer.intel.com/technology/efi/efi.htm
+ *
+ * By Matt Domsch <Matt_Domsch@dell.com>  Fri Sep 22 22:15:56 CDT 2000  
+ *   Copyright 2000,2001 Dell Computer Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ * 
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ ************************************************************/
+
+#ifndef FS_PART_EFI_H_INCLUDED
+#define FS_PART_EFI_H_INCLUDED
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/fs.h>
+#include <linux/genhd.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/blk.h>
+/*
+ * Yes, specifying asm-ia64 is ugly, but this lets it build on
+ * other platforms too, until efi.h moves to include/linux.
+ */
+#include <asm-ia64/efi.h>
+
+
+#define MSDOS_MBR_SIGNATURE 0xaa55
+#define EFI_PMBR_OSTYPE_EFI 0xEF
+#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
+
+#define GPT_BLOCK_SIZE 512
+#define GPT_HEADER_SIGNATURE 0x5452415020494645L
+#define GPT_HEADER_REVISION_V1 0x00010000
+#define GPT_PRIMARY_PARTITION_TABLE_LBA 1
+
+#define UNUSED_ENTRY_GUID    \
+    ((efi_guid_t) { 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }})
+#define PARTITION_SYSTEM_GUID \
+((efi_guid_t) { 0xC12A7328, 0xF81F, 0x11d2, { 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B }})
+#define LEGACY_MBR_PARTITION_GUID \
+    ((efi_guid_t) { 0x024DEE41, 0x33E7, 0x11d3, { 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F }})
+#define PARTITION_MSFT_RESERVED_GUID \
+    ((efi_guid_t) { 0xE3C9E316, 0x0B5C, 0x4DB8, { 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE }})
+#define PARTITION_BASIC_DATA_GUID \
+    ((efi_guid_t) { 0xEBD0A0A2, 0xB9E5, 0x4433, { 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7 }})
+#define PARTITION_LINUX_RAID_GUID \
+    ((efi_guid_t) { 0xa19d880f, 0x05fc, 0x4d3b, { 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e  }})
+#define PARTITION_LINUX_SWAP_GUID \
+    ((efi_guid_t) { 0x0657fd6d, 0xa4ab, 0x43c4, { 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f  }})
+#define PARTITION_LINUX_LVM_GUID \
+    ((efi_guid_t) { 0xe6d6d379, 0xf507, 0x44c2, { 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28 }})
+
+typedef struct _GuidPartitionTableHeader_t {
+	u64 Signature;
+	u32 Revision;
+	u32 HeaderSize;
+	u32 HeaderCRC32;
+	u32 Reserved1;
+	u64 MyLBA;
+	u64 AlternateLBA;
+	u64 FirstUsableLBA;
+	u64 LastUsableLBA;
+	efi_guid_t DiskGUID;
+	u64 PartitionEntryLBA;
+	u32 NumberOfPartitionEntries;
+	u32 SizeOfPartitionEntry;
+	u32 PartitionEntryArrayCRC32;
+	u8 Reserved2[GPT_BLOCK_SIZE - 92];
+} __attribute__ ((packed)) GuidPartitionTableHeader_t;
+
+typedef struct _GuidPartitionEntryAttributes_t {
+	u64 RequiredToFunction:1;
+	u64 Reserved:63;
+} __attribute__ ((packed)) GuidPartitionEntryAttributes_t;
+
+typedef struct _GuidPartitionEntry_t {
+	efi_guid_t PartitionTypeGuid;
+	efi_guid_t UniquePartitionGuid;
+	u64 StartingLBA;
+	u64 EndingLBA;
+	GuidPartitionEntryAttributes_t Attributes;
+	efi_char16_t PartitionName[72 / sizeof(efi_char16_t)];
+} __attribute__ ((packed)) GuidPartitionEntry_t;
+
+typedef struct _PartitionRecord_t {
+	u8 BootIndicator;	/* Not used by EFI firmware. Set to 0x80 to indicate that this
+				   is the bootable legacy partition. */
+	u8 StartHead;		/* Start of partition in CHS address, not used by EFI firmware. */
+	u8 StartSector;		/* Start of partition in CHS address, not used by EFI firmware. */
+	u8 StartTrack;		/* Start of partition in CHS address, not used by EFI firmware. */
+	u8 OSType;		/* OS type. A value of 0xEF defines an EFI system partition.
+				   Other values are reserved for legacy operating systems, and
+				   allocated independently of the EFI specification. */
+	u8 EndHead;		/* End of partition in CHS address, not used by EFI firmware. */
+	u8 EndSector;		/* End of partition in CHS address, not used by EFI firmware. */
+	u8 EndTrack;		/* End of partition in CHS address, not used by EFI firmware. */
+	u32 StartingLBA;	/* Starting LBA address of the partition on the disk. Used by
+				   EFI firmware to define the start of the partition. */
+	u32 SizeInLBA;		/* Size of partition in LBA. Used by EFI firmware to determine
+				   the size of the partition. */
+} PartitionRecord_t;
+
+typedef struct _LegacyMBR_t {
+	u8 BootCode[440];
+	u32 UniqueMBRSignature;
+	u16 Unknown;
+	PartitionRecord_t PartitionRecord[4];
+	u16 Signature;
+} __attribute__ ((packed)) LegacyMBR_t;
+
+
+
+/* Functions */
+extern int
+efi_partition(struct gendisk *hd, struct block_device *bdev,
+	      unsigned long first_sector, int first_part_minor);
+
+
+
+
+#endif
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * --------------------------------------------------------------------------
+ * Local variables:
+ * c-indent-level: 4 
+ * c-brace-imaginary-offset: 0
+ * c-brace-offset: -4
+ * c-argdecl-indent: 4
+ * c-label-offset: -4
+ * c-continued-statement-offset: 4
+ * c-continued-brace-offset: 0
+ * indent-tabs-mode: nil
+ * tab-width: 8
+ * End:
+ */
diff -urN linux-2.4.16/fs/partitions/msdos.c lia64-2.4/fs/partitions/msdos.c
--- linux-2.4.16/fs/partitions/msdos.c	Wed Oct 24 10:17:59 2001
+++ lia64-2.4/fs/partitions/msdos.c	Wed Oct 24 10:24:48 2001
@@ -36,6 +36,10 @@
 #include "check.h"
 #include "msdos.h"
 
+#ifdef CONFIG_EFI_PARTITION
+#include "efi.h"
+#endif
+
 #if CONFIG_BLK_DEV_MD
 extern void md_autodetect_dev(kdev_t dev);
 #endif
@@ -564,6 +568,16 @@
 		return 0;
 	}
 	p = (struct partition *) (data + 0x1be);
+#ifdef CONFIG_EFI_PARTITION
+	for (i=1 ; i<=4 ; i++,p++) {
+		/* If this is an EFI GPT disk, msdos should ignore it. */
+		if (SYS_IND(p) == EFI_PMBR_OSTYPE_EFI_GPT) {
+			put_dev_sector(sect);
+			return 0;
+		}
+	}
+	p = (struct partition *) (data + 0x1be);
+#endif
 
 	/*
 	 * Look for partitions in two passes:
diff -urN linux-2.4.16/fs/proc/base.c lia64-2.4/fs/proc/base.c
--- linux-2.4.16/fs/proc/base.c	Wed Oct 24 10:17:32 2001
+++ lia64-2.4/fs/proc/base.c	Wed Oct 24 10:23:48 2001
@@ -396,7 +396,24 @@
 }
 #endif
 
+static loff_t mem_lseek(struct file * file, loff_t offset, int orig)
+{
+	switch (orig) {
+	      case 0:
+		file->f_pos = offset;
+		break;
+	      case 1:
+		file->f_pos += offset;
+		break;
+	      default:
+		return -EINVAL;
+	}
+	force_successful_syscall_return();
+	return file->f_pos;
+}
+
 static struct file_operations proc_mem_operations = {
+	llseek:		mem_lseek,
 	read:		mem_read,
 	write:		mem_write,
 	open:		mem_open,
diff -urN linux-2.4.16/include/asm-ia64/acpi-ext.h lia64-2.4/include/asm-ia64/acpi-ext.h
--- linux-2.4.16/include/asm-ia64/acpi-ext.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/acpi-ext.h	Mon Nov 26 18:06:04 2001
@@ -13,7 +13,9 @@
  *	ACPI 2.0 specification
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
+#include <linux/mm.h>
 
 #pragma	pack(1)
 #define ACPI_RSDP_SIG "RSD PTR " /* Trailing space required */
@@ -24,7 +26,7 @@
 	char oem_id[6];
 	u8 revision;
 	u32 rsdt;
-	u32 lenth;
+	u32 length;
 	struct acpi_xsdt *xsdt;
 	u8 ext_checksum;
 	u8 reserved[3];
@@ -96,7 +98,7 @@
 	struct acpi_rsdt *rsdt;
 } acpi_rsdp_t;
 
-typedef struct {
+typedef struct acpi_rsdt {
 	acpi_desc_table_hdr_t header;
 	u8 reserved[4];
 	unsigned long entry_ptrs[1];	/* Not really . . . */
@@ -151,15 +153,15 @@
 #define MADT_PCAT_COMPAT	(1<<0)
 
 /* acpi 2.0 MADT structure types */
-#define ACPI20_ENTRY_LOCAL_APIC                 0
-#define ACPI20_ENTRY_IO_APIC                    1
-#define ACPI20_ENTRY_INT_SRC_OVERRIDE           2
-#define ACPI20_ENTRY_NMI_SOURCE                 3
-#define ACPI20_ENTRY_LOCAL_APIC_NMI             4
-#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE   5
-#define ACPI20_ENTRY_IO_SAPIC                   6
-#define ACPI20_ENTRY_LOCAL_SAPIC                7
-#define ACPI20_ENTRY_PLATFORM_INT_SOURCE        8
+#define ACPI20_ENTRY_LOCAL_APIC			0
+#define ACPI20_ENTRY_IO_APIC			1
+#define ACPI20_ENTRY_INT_SRC_OVERRIDE		2
+#define ACPI20_ENTRY_NMI_SOURCE			3
+#define ACPI20_ENTRY_LOCAL_APIC_NMI		4
+#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE	5
+#define ACPI20_ENTRY_IO_SAPIC			6
+#define ACPI20_ENTRY_LOCAL_SAPIC		7
+#define ACPI20_ENTRY_PLATFORM_INT_SOURCE	8
 
 typedef struct acpi20_entry_lsapic {
 	u8 type;
@@ -190,16 +192,132 @@
 } acpi20_entry_platform_src_t;
 
 /* constants for interrupt routing API for device drivers */
-#define	ACPI20_ENTRY_PIS_PMI	1
-#define	ACPI20_ENTRY_PIS_INIT	2
-#define	ACPI20_ENTRY_PIS_CPEI	3
-#define	ACPI_MAX_PLATFORM_IRQS	4
+#define ACPI20_ENTRY_PIS_PMI	1
+#define ACPI20_ENTRY_PIS_INIT	2
+#define ACPI20_ENTRY_PIS_CPEI	3
+#define ACPI_MAX_PLATFORM_IRQS	4
+
+#define ACPI_SPCRT_SIG	"SPCR"
+#define ACPI_SPCRT_SIG_LEN 4
+
+#define ACPI_DBGPT_SIG	"DBGP"
+#define ACPI_DBGPT_SIG_LEN 4
 
 extern int acpi20_parse(acpi20_rsdp_t *);
+extern int acpi20_early_parse(acpi20_rsdp_t *);
 extern int acpi_parse(acpi_rsdp_t *);
 extern const char *acpi_get_sysname (void);
 extern int acpi_request_vector(u32 int_type);
-
 extern void (*acpi_idle) (void);	/* power-management idle function, if any */
+#ifdef CONFIG_NUMA
+extern cnodeid_t paddr_to_nid(unsigned long paddr);
+#endif
+
+/*
+ * ACPI 2.0 SRAT Table
+ * http://www.microsoft.com/HWDEV/design/SRAT.htm
+ */
+
+typedef struct acpi_srat {
+	acpi_desc_table_hdr_t header;
+	u32 table_revision;
+	u64 reserved;
+} acpi_srat_t;
+
+typedef struct srat_cpu_affinity {
+	u8 type;
+	u8 length;
+	u8 proximity_domain;
+	u8 apic_id;
+	u32 flags;
+	u8 local_sapic_eid;
+	u8 reserved[7];
+} srat_cpu_affinity_t;
+
+typedef struct srat_memory_affinity {
+	u8 type;
+	u8 length;
+	u8 proximity_domain;
+	u8 reserved[5];
+	u32 base_addr_lo;
+	u32 base_addr_hi;
+	u32 length_lo;
+	u32 length_hi;
+	u32 memory_type;
+	u32 flags;
+	u64 reserved2;
+} srat_memory_affinity_t;
+
+/* ACPI 2.0 SRAT structure */
+#define ACPI_SRAT_SIG "SRAT"
+#define ACPI_SRAT_SIG_LEN 4
+#define ACPI_SRAT_REVISION 1
+
+#define SRAT_CPU_STRUCTURE		0
+#define SRAT_MEMORY_STRUCTURE		1
+
+/* Only 1 flag for cpu affinity structure! */
+#define SRAT_CPU_FLAGS_ENABLED			0x00000001
+
+#define SRAT_MEMORY_FLAGS_ENABLED		0x00000001
+#define SRAT_MEMORY_FLAGS_HOTREMOVABLE		0x00000002
+
+/* ACPI 2.0 address range types */
+#define ACPI_ADDRESS_RANGE_MEMORY	1
+#define ACPI_ADDRESS_RANGE_RESERVED	2
+#define ACPI_ADDRESS_RANGE_ACPI		3
+#define ACPI_ADDRESS_RANGE_NVS		4
+
+#define NODE_ARRAY_INDEX(x)	((x) / 8)	/* 8 bits/char */
+#define NODE_ARRAY_OFFSET(x)	((x) % 8)	/* 8 bits/char */
+#define MAX_PXM_DOMAINS		(256)
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * List of node memory chunks. Filled when parsing SRAT table to
+ * obtain information about memory nodes.
+*/
+
+struct node_memory_chunk_s {
+	unsigned long start_paddr;
+	unsigned long size;
+	int pxm;			// proximity domain of node
+	int nid;			// which cnode contains this chunk?
+	int bank;			// which mem bank on this node
+};
+
+extern struct node_memory_chunk_s node_memory_chunk[PLAT_MAXCLUMPS];	// temporary?
+
+struct node_cpuid_s {
+	u16	phys_id;		/* id << 8 | eid */
+	int	pxm;			// proximity domain of cpu
+	int	nid;
+};
+extern struct node_cpuid_s node_cpuid[NR_CPUS];
+
+extern int pxm_to_nid_map[MAX_PXM_DOMAINS]; /* _PXM to logical node ID map */
+extern int nid_to_pxm_map[PLAT_MAX_COMPACT_NODES]; /* logical node ID to _PXM map */
+extern int num_compact_nodes;		/* total number of nodes in system */
+extern int num_memory_chunks;		/* total number of memory chunks */
+
+/*
+ * ACPI 2.0 SLIT Table
+ * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf
+ */
+
+typedef struct acpi_slit {
+	acpi_desc_table_hdr_t header;
+	u64 localities;
+	u8 entries[1];			/* dummy, real size = locality^2 */
+} acpi_slit_t;
+
+extern u8 acpi20_slit[PLAT_MAX_COMPACT_NODES * PLAT_MAX_COMPACT_NODES];
+
+#define ACPI_SLIT_SIG "SLIT"
+#define ACPI_SLIT_SIG_LEN 4
+#define ACPI_SLIT_REVISION 1
+#define ACPI_SLIT_LOCAL 10
+#endif /* CONFIG_DISCONTIGMEM */
+
 #pragma	pack()
 #endif /* _ASM_IA64_ACPI_EXT_H */
diff -urN linux-2.4.16/include/asm-ia64/machvec.h lia64-2.4/include/asm-ia64/machvec.h
--- linux-2.4.16/include/asm-ia64/machvec.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/machvec.h	Mon Nov 26 18:05:56 2001
@@ -20,6 +20,7 @@
 struct irq_desc;
 
 typedef void ia64_mv_setup_t (char **);
+typedef void ia64_mv_cpu_init_t(void);
 typedef void ia64_mv_irq_init_t (void);
 typedef void ia64_mv_pci_fixup_t (int);
 typedef unsigned long ia64_mv_map_nr_t (unsigned long);
@@ -77,6 +78,7 @@
 # else
 #  define platform_name		ia64_mv.name
 #  define platform_setup	ia64_mv.setup
+#  define platform_cpu_init	ia64_mv.cpu_init
 #  define platform_irq_init	ia64_mv.irq_init
 #  define platform_map_nr	ia64_mv.map_nr
 #  define platform_mca_init	ia64_mv.mca_init
@@ -110,6 +112,7 @@
 struct ia64_machine_vector {
 	const char *name;
 	ia64_mv_setup_t *setup;
+	ia64_mv_cpu_init_t *cpu_init;
 	ia64_mv_irq_init_t *irq_init;
 	ia64_mv_pci_fixup_t *pci_fixup;
 	ia64_mv_map_nr_t *map_nr;
@@ -200,6 +203,9 @@
  */
 #ifndef platform_setup
 # define platform_setup		((ia64_mv_setup_t *) machvec_noop)
+#endif
+#ifndef platform_cpu_init
+# define platform_cpu_init	((ia64_mv_cpu_init_t *) machvec_noop)
 #endif
 #ifndef platform_irq_init
 # define platform_irq_init	((ia64_mv_irq_init_t *) machvec_noop)
diff -urN linux-2.4.16/include/asm-ia64/machvec_sn1.h lia64-2.4/include/asm-ia64/machvec_sn1.h
--- linux-2.4.16/include/asm-ia64/machvec_sn1.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/machvec_sn1.h	Mon Nov 26 16:34:04 2001
@@ -2,6 +2,7 @@
 #define _ASM_IA64_MACHVEC_SN1_h
 
 extern ia64_mv_setup_t sn1_setup;
+extern ia64_mv_cpu_init_t sn_cpu_init;
 extern ia64_mv_irq_init_t sn1_irq_init;
 extern ia64_mv_map_nr_t sn1_map_nr;
 extern ia64_mv_send_ipi_t sn1_send_IPI;
@@ -32,6 +33,7 @@
  */
 #define platform_name		"sn1"
 #define platform_setup		sn1_setup
+#define platform_cpu_init	sn_cpu_init
 #define platform_irq_init	sn1_irq_init
 #define platform_map_nr		sn1_map_nr
 #define platform_send_ipi	sn1_send_IPI
diff -urN linux-2.4.16/include/asm-ia64/offsets.h lia64-2.4/include/asm-ia64/offsets.h
--- linux-2.4.16/include/asm-ia64/offsets.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/offsets.h	Mon Nov 26 12:08:19 2001
@@ -8,7 +8,7 @@
  */
 #define PT_PTRACED_BIT		0
 #define PT_TRACESYS_BIT		1
-#define IA64_TASK_SIZE			3408	/* 0xd50 */
+#define IA64_TASK_SIZE			3936	/* 0xf60 */
 #define IA64_PT_REGS_SIZE		400	/* 0x190 */
 #define IA64_SWITCH_STACK_SIZE		560	/* 0x230 */
 #define IA64_SIGINFO_SIZE		128	/* 0x80 */
@@ -19,11 +19,11 @@
 #define IA64_TASK_PTRACE_OFFSET		48	/* 0x30 */
 #define IA64_TASK_SIGPENDING_OFFSET	16	/* 0x10 */
 #define IA64_TASK_NEED_RESCHED_OFFSET	40	/* 0x28 */
-#define IA64_TASK_PROCESSOR_OFFSET	100	/* 0x64 */
-#define IA64_TASK_THREAD_OFFSET		976	/* 0x3d0 */
-#define IA64_TASK_THREAD_KSP_OFFSET	976	/* 0x3d0 */
-#define IA64_TASK_PFM_MUST_BLOCK_OFFSET	1600	/* 0x640 */
-#define IA64_TASK_PID_OFFSET		220	/* 0xdc */
+#define IA64_TASK_PROCESSOR_OFFSET	96	/* 0x60 */
+#define IA64_TASK_THREAD_OFFSET		1488	/* 0x5d0 */
+#define IA64_TASK_THREAD_KSP_OFFSET	1488	/* 0x5d0 */
+#define IA64_TASK_PFM_MUST_BLOCK_OFFSET	2112	/* 0x840 */
+#define IA64_TASK_PID_OFFSET		228	/* 0xe4 */
 #define IA64_TASK_MM_OFFSET		88	/* 0x58 */
 #define IA64_PT_REGS_CR_IPSR_OFFSET	0	/* 0x0 */
 #define IA64_PT_REGS_CR_IIP_OFFSET	8	/* 0x8 */
diff -urN linux-2.4.16/include/asm-ia64/pgtable.h lia64-2.4/include/asm-ia64/pgtable.h
--- linux-2.4.16/include/asm-ia64/pgtable.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/pgtable.h	Mon Nov 26 18:05:58 2001
@@ -121,6 +121,7 @@
 #define PAGE_COPY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 #define PAGE_GATE	__pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
 #define PAGE_KERNEL	__pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
+#define PAGE_KERNELRX	__pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
 
 # ifndef __ASSEMBLY__
 
@@ -178,6 +179,7 @@
 	return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
 }
 
+#ifndef CONFIG_DISCONTIGMEM
 /*
  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
  * memory.  For the return value to be meaningful, ADDR must be >=
@@ -193,6 +195,8 @@
  */
 #define kern_addr_valid(addr)	(1)
 
+#endif
+
 /*
  * Now come the defines and routines to manage and access the three-level
  * page table.
@@ -237,8 +241,10 @@
 #define pte_none(pte) 			(!pte_val(pte))
 #define pte_present(pte)		(pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 #define pte_clear(pte)			(pte_val(*(pte)) = 0UL)
+#ifndef CONFIG_DISCONTIGMEM
 /* pte_page() returns the "struct page *" corresponding to the PTE: */
 #define pte_page(pte)			(mem_map + (unsigned long) ((pte_val(pte) & _PFN_MASK) >> PAGE_SHIFT))
+#endif
 
 #define pmd_none(pmd)			(!pmd_val(pmd))
 #define pmd_bad(pmd)			(!ia64_phys_addr_valid(pmd_val(pmd)))
diff -urN linux-2.4.16/include/asm-ia64/processor.h lia64-2.4/include/asm-ia64/processor.h
--- linux-2.4.16/include/asm-ia64/processor.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/processor.h	Mon Nov 26 18:05:56 2001
@@ -282,8 +282,12 @@
 	__u64 ipi_operation;
 #endif
 #ifdef CONFIG_NUMA
+	void *node_directory;
+	int numa_node_id;
 	struct cpuinfo_ia64 *cpu_data[NR_CPUS];
 #endif
+	/* Platform specific word.  MUST BE LAST IN STRUCT */
+	__u64 platform_specific;
 } __attribute__ ((aligned (PAGE_SIZE))) ;
 
 /*
@@ -303,7 +307,8 @@
  * the array.
  */
 #ifdef CONFIG_NUMA
-# define cpu_data(cpu)		local_cpu_data->cpu_data_ptrs[cpu]
+# define cpu_data(cpu)		local_cpu_data->cpu_data[cpu]
+# define numa_node_id()		(local_cpu_data->numa_node_id)
 #else
   extern struct cpuinfo_ia64 _cpu_data[NR_CPUS];
 # define cpu_data(cpu)		(&_cpu_data[cpu])
diff -urN linux-2.4.16/include/asm-ia64/scatterlist.h lia64-2.4/include/asm-ia64/scatterlist.h
--- linux-2.4.16/include/asm-ia64/scatterlist.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/scatterlist.h	Mon Nov 26 11:22:43 2001
@@ -7,14 +7,8 @@
  */
 
 struct scatterlist {
-	/* This will disappear in 2.5.x: */
-	char *address;		/* location data is to be transferred to, NULL for highmem page */
-	char *orig_address;	/* for use by swiotlb */
-
-	/* These two are only valid if ADDRESS member of this struct is NULL.  */
-	struct page *page;
-	unsigned int offset;
-
+	char *address;		/* location data is to be transferred to */
+	void *page;		/* stupid: SCSI code insists on a member of this name... */
 	unsigned int length;	/* buffer length */
 };
 
diff -urN linux-2.4.16/include/asm-ia64/sn/addrs.h lia64-2.4/include/asm-ia64/sn/addrs.h
--- linux-2.4.16/include/asm-ia64/sn/addrs.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/addrs.h	Mon Nov 26 18:05:56 2001
@@ -1,40 +1,42 @@
-/* $Id$
+
+/*
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
+ * Copyright (c) 1992-1999,2001 Silicon Graphics, Inc.  All rights reserved.
  */
-#ifndef _ASM_SN_ADDRS_H
-#define _ASM_SN_ADDRS_H
 
-#include <linux/config.h>
 
-#if _LANGUAGE_C
-#include <linux/types.h>
-#endif /* _LANGUAGE_C */
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#include <asm/addrspace.h>
-#include <asm/reg.h>
-#include <asm/sn/kldir.h>
-#endif	/* CONFIG_IA64_SGI_SN1 */
+#ifndef _ASM_IA64_SN_ADDRS_H
+#define _ASM_IA64_SN_ADDRS_H
+
+#include <linux/config.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined (CONFIG_IA64_SGI_SN1)
 #include <asm/sn/sn1/addrs.h>
-#endif
+#elif defined (CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/addrs.h>
+#else
+#error <<<BOMB! addrs.h defined only for SN1, or SN2 >>>
+#endif /* !SN1 && !SN2 */
 
+#ifndef __ASSEMBLY__
+#include <asm/sn/types.h>
+#endif 
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define PS_UINT_CAST		(__psunsigned_t)
 #define UINT64_CAST		(uint64_t)
-
+#ifdef CONFIG_IA64_SGI_SN2
+#define HUBREG_CAST		(volatile mmr_t *)
+#else
 #define HUBREG_CAST		(volatile hubreg_t *)
+#endif
 
-#elif _LANGUAGE_ASSEMBLY
+#elif __ASSEMBLY__
 
 #define PS_UINT_CAST
 #define UINT64_CAST
@@ -43,18 +45,6 @@
 #endif
 
 
-#define NASID_GET_META(_n)	((_n) >> NASID_LOCAL_BITS)
-#if defined CONFIG_SGI_IP35 || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define NASID_GET_LOCAL(_n)	((_n) & 0x7f)
-#endif
-#define NASID_MAKE(_m, _l)	(((_m) << NASID_LOCAL_BITS) | (_l))
-
-#define NODE_ADDRSPACE_MASK	(NODE_ADDRSPACE_SIZE - 1)
-#define TO_NODE_ADDRSPACE(_pa)	(UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
-
-#define CHANGE_ADDR_NASID(_pa, _nasid)	\
-		((UINT64_CAST (_pa) & ~NASID_MASK) | \
-		 (UINT64_CAST(_nasid) <<  NASID_SHFT))
 
 
 /*
@@ -62,7 +52,11 @@
  * node's address space.
  */
 
+#ifdef CONFIG_IA64_SGI_SN2	/* SN2 has an extra AS field between node offset and node id (nasid) */
+#define NODE_OFFSET(_n)		(UINT64_CAST (_n) << NASID_SHFT)
+#else
 #define NODE_OFFSET(_n)		(UINT64_CAST (_n) << NODE_SIZE_BITS)
+#endif
 
 #define NODE_CAC_BASE(_n)	(CAC_BASE   + NODE_OFFSET(_n))
 #define NODE_HSPEC_BASE(_n)	(HSPEC_BASE + NODE_OFFSET(_n))
@@ -118,11 +112,6 @@
 /*
  * The following define the major position-independent aliases used
  * in SN.
- *	UALIAS -- 256MB in size, reads in the UALIAS result in
- *			uncached references to the memory of the reader's node.
- *	CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
- *			depending on which CPU does the access to provide
- *			all CPUs with unique uncached memory at low addresses.
  *	LBOOT  -- 256MB in size, reads in the LBOOT area result in
  *			uncached references to the local hub's boot prom and
  *			other directory-bus connected devices.
@@ -130,17 +119,7 @@
  *			references to the local hub's registers.
  */
 
-#define UALIAS_BASE		HSPEC_BASE
-#define UALIAS_SIZE		0x10000000	/* 256 Megabytes */
-#define CPU_UALIAS		0x20000		/* 128 Kilobytes */
-#define UALIAS_CPU_SIZE		(CPU_UALIAS / CPUS_PER_NODE)
-#define UALIAS_LIMIT		(UALIAS_BASE + UALIAS_SIZE)
-
-/*
- * The bottom of ualias space is flipped depending on whether you're
- * processor 0 or 1 within a node.
- */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined CONFIG_IA64_SGI_SN1
 #define LREG_BASE		(HSPEC_BASE + 0x10000000)
 #define LREG_SIZE		0x8000000  /* 128 MB */
 #define LREG_LIMIT		(LREG_BASE + LREG_SIZE)
@@ -151,7 +130,11 @@
 #endif
 
 #define	HUB_REGISTER_WIDGET	1
+#ifdef CONFIG_IA64_SGI_SN2
+#define IALIAS_BASE		LOCAL_SWIN_BASE(HUB_REGISTER_WIDGET)
+#else
 #define IALIAS_BASE		NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#endif
 #define IALIAS_SIZE		0x800000	/* 8 Megabytes */
 #define IS_IALIAS(_a)		(((_a) >= IALIAS_BASE) &&		\
 				 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
@@ -160,7 +143,7 @@
  * Macro for referring to Hub's RBOOT space
  */
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined CONFIG_IA64_SGI_SN1
 
 #define NODE_LREG_BASE(_n)	(NODE_HSPEC_BASE(_n) + 0x30000000)
 #define NODE_LREG_LIMIT(_n)	(NODE_LREG_BASE(_n) + LREG_SIZE)
@@ -172,168 +155,6 @@
 
 #endif
 
-/*
- * Macros for referring the Hub's back door space
- *
- *   These macros correctly process addresses in any node's space.
- *   WARNING: They won't work in assembler.
- *
- *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
- *                  entry corresponding to a physical (Cac or Uncac) address.
- *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
- *   BDPRT_ENTRY    returns the address of the double-word protection entry
- *                  corresponding to the page containing the physical address.
- *   BDPRT_ENTRY_S  Stores the value into the protection entry.
- *   BDPRT_ENTRY_L  Load the value from the protection entry.
- *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
- *                  double-word at a specified physical address.
- *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
- *                  quad-word at a specified physical address.
- */
-#define NODE_BDOOR_BASE(_n)	(NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
-
-#define NODE_BDECC_BASE(_n)	(NODE_BDOOR_BASE(_n))
-#define NODE_BDDIR_BASE(_n)	(NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-/*
- * Bedrock's directory entries are a single word:  no low/high
- */
-
-#define BDDIR_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 7 / 8  		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDDIR_UPPER_MASK)
-
-#ifdef BRINGUP
-        /* minimize source changes by mapping *_LO() & *_HI()   */
-#define BDDIR_ENTRY_LO(_pa)     BDDIR_ENTRY(_pa)
-#define BDDIR_ENTRY_HI(_pa)     BDDIR_ENTRY(_pa)
-#endif /* BRINGUP */
-
-#define BDDIR_PAGE_MASK		(BDDIR_UPPER_MASK & 0x7ffff << 11)
-#define BDDIR_PAGE_BASE_MASK	(UINT64_CAST 0xfffffffffffff800)
-
-#ifdef _LANGUAGE_C
-
-#define BDPRT_ENTRY_ADDR(_pa, _rgn)      ((uint64_t *) ( (HSPEC_BASE +       \
-                                 NODE_ADDRSPACE_SIZE * 7 / 8 + 0x408)       | \
-                                (UINT64_CAST (_pa)      & NASID_MASK)        | \
-                                (UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK)   | \
-                                (UINT64_CAST (_pa) >> 3 & 0x3 << 4)          | \
-                                ((_rgn) & 0x1e) << 5))
-
-static __inline uint64_t BDPRT_ENTRY_L(paddr_t pa,uint32_t rgn) {
-	uint64_t word=*BDPRT_ENTRY_ADDR(pa,rgn);
-
-	if(rgn&0x20)			/*If the region is > 32, move it down*/
-		word = word >> 32;
-	if(rgn&0x1)			/*If the region is odd, get that part */
-		word = word >> 16;
-	word = word & 0xffff;		/*Get the 16 bits we are interested in*/
-
-	return word;
-}
-
-static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) {
-        uint64_t *addr=(uint64_t *)BDPRT_ENTRY_ADDR(pa,rgn);
-        uint64_t word,mask;
-
-        word=*addr;
-	mask=0;
-	if(rgn&0x1) {
-		mask|=0x0000ffff0000ffff;
-		val=val<<16;
-	}
-	else
-		mask|=0xffff0000ffff0000;
-	if(rgn&0x20) {
-		mask|=0x00000000ffffffff;
-		val=val<<32;
-	}
-	else
-		mask|=0xffffffff00000000;
-	word &= mask;
-	word |= val;
-
-	*(addr++)=word;
-	addr++;
-        *(addr++)=word;
-        addr++;
-        *(addr++)=word;
-        addr++;
-        *addr=word;
-}
-#endif	/*_LANGUAGE_C*/
-
-#define BDCNT_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 7 / 8 + 0x8    	    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK   | \
-				 UINT64_CAST (_pa) >> 3 & 0x3 << 4)
-
-
-#ifdef    BRINGUP
-  /* little endian packing of ecc bytes requires a swizzle */ 
-  /* this is problemmatic for memory_init_ecc              */
-#endif /* BRINGUP */
-#define BDECC_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 5 / 8 		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x7ULL)
-
-#define BDECC_SCRUB(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE / 2 		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x7ULL)
-
-  /* address for Halfword backdoor ecc access. Note that   */
-  /* ecc bytes are packed in little endian order           */
-#define BDECC_ENTRY_H(_pa)	(HSPEC_BASE +                                 \
-				  NODE_ADDRSPACE_SIZE * 5 / 8		    | \
-				 UINT64_CAST (_pa)	 & NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x6ULL)
-
-/*
- * Macro to convert a back door directory, protection, page counter, or ecc
- * address into the raw physical address of the associated cache line
- * or protection page.
- */
-
-#define BDDIR_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK            | \
-				 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK) << 3)
-
-#ifdef BRINGUP
-/*
- * This can't be done since there are 4 entries per address so you'd end up
- * mapping back to 4 different physical addrs.
- */
-  
-#define BDPRT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
-				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
-#endif
-
-#define BDCNT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
-				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
-
-#define BDECC_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 ((UINT64_CAST (_ba) ^ 0x7ULL)                \
-				                    & BDECC_UPPER_MASK) << 3 )
-
-#define BDECC_H_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 ((UINT64_CAST (_ba) ^ 0x6ULL)                \
-				                    & BDECC_UPPER_MASK) << 3 )
-
-#define BDADDR_IS_DIR(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0)
-#define BDADDR_IS_PRT(_ba)	((UINT64_CAST  (_ba) & 0x408) == 0x408)
-#define BDADDR_IS_CNT(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0x8)
-
-#endif /* CONFIG_SGI_IP35 */
-
 
 /*
  * The following macros produce the correct base virtual address for
@@ -344,6 +165,36 @@
  * for _x.
  */
 
+
+#ifdef CONFIG_IA64_SGI_SN2
+/*
+ * SN2 has II mmr's located inside small window space like SN0 & SN1,
+ * but has all other non-II mmr's located at the top of big window
+ * space, unlike SN0 & SN1.
+ */
+#define LOCAL_HUB_BASE(_x)	(LOCAL_MMR_ADDR(_x) | (((~(_x)) & BWIN_TOP)>>8))
+#define REMOTE_HUB_BASE(_x)						\
+        (UNCACHED | GLOBAL_MMR_SPACE |                                  \
+        (((~(_x)) & BWIN_TOP)>>8)    |                                       \
+        (((~(_x)) & BWIN_TOP)>>9)    | (_x))
+
+#define LOCAL_HUB(_x) (HUBREG_CAST LOCAL_HUB_BASE(_x))
+#define REMOTE_HUB(_n, _x)						\
+	(HUBREG_CAST (REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT))))
+
+#else	/* not CONFIG_IA64_SGI_SN2 */
+
+#define LOCAL_HUB(_x)		(HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
+					      0x800000 + (_x)))
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define LOCAL_HSPEC(_x)		(HUBREG_CAST (LREG_BASE + (_x)))
+#define REMOTE_HSPEC(_n, _x)		(HUBREG_CAST (RREG_BASE(_n) + (_x)))
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
 /*
  * WARNING:
  *	When certain Hub chip workaround are defined, it's not sufficient
@@ -352,17 +203,29 @@
  *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *	They're always safe.
  */
+#ifdef CONFIG_IA64_SGI_SN2
+#define LOCAL_HUB_ADDR(_x)							\
+	(((_x) & BWIN_TOP) ? (HUBREG_CAST (LOCAL_MMR_ADDR(_x)))		\
+	: (HUBREG_CAST (IALIAS_BASE + (_x))))
+#define REMOTE_HUB_ADDR(_n, _x)						\
+	(((_x) & BWIN_TOP) ? (HUBREG_CAST (GLOBAL_MMR_ADDR(_n, _x)))	\
+	: (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x))))
+#else
 #define LOCAL_HUB_ADDR(_x)	(HUBREG_CAST (IALIAS_BASE + (_x)))
 #define REMOTE_HUB_ADDR(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
 					      0x800000 + (_x)))
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#endif
+#if CONFIG_IA64_SGI_SN1
 #define REMOTE_HUB_PI_ADDR(_n, _sn, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
 					      0x800000 + PIREG(_x, _sn)))
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
 #define LOCAL_HSPEC_ADDR(_x)		(HUBREG_CAST (LREG_BASE + (_x)))
 #define REMOTE_HSPEC_ADDR(_n, _x)	(HUBREG_CAST (RREG_BASE(_n) + (_x)))
-#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define HUB_L(_a)			*(_a)
 #define	HUB_S(_a, _d)			*(_a) = (_d)
@@ -374,14 +237,14 @@
 #define REMOTE_HUB_PI_L(_n, _sn, _r)	HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
 #define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#ifdef CONFIG_IA64_SGI_SN1
 #define LOCAL_HSPEC_L(_r)	     HUB_L(LOCAL_HSPEC_ADDR(_r))
 #define LOCAL_HSPEC_S(_r, _d)	     HUB_S(LOCAL_HSPEC_ADDR(_r), (_d))
 #define REMOTE_HSPEC_L(_n, _r)	     HUB_L(REMOTE_HSPEC_ADDR((_n), (_r)))
 #define REMOTE_HSPEC_S(_n, _r, _d)   HUB_S(REMOTE_HSPEC_ADDR((_n), (_r)), (_d))
-#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /*
  * The following macros are used to get to a hub/bridge register, given
@@ -410,13 +273,8 @@
 #define ARCS_SPB_SIZE		0x0400
 
 #define KLDIR_OFFSET		0x2000
-#ifndef __ia64
 #define KLDIR_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
-#else
-#define KLDIR_ADDR(nasid)                                               \
-        TO_NODE_CAC((nasid), KLDIR_OFFSET)
-#endif
+	TO_NODE_CAC((nasid), KLDIR_OFFSET)
 #define KLDIR_SIZE		0x0400
 
 
@@ -439,7 +297,7 @@
 #define	KLI_KERN_XP		8
 #define	KLI_KERN_PARTID		9
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define KLD_BASE(nasid)		((kldir_ent_t *) KLDIR_ADDR(nasid))
 #define KLD_LAUNCH(nasid)	(KLD_BASE(nasid) + KLI_LAUNCH)
@@ -453,85 +311,23 @@
 #define	KLD_KERN_XP(nasid)	(KLD_BASE(nasid) + KLI_KERN_XP)
 #define	KLD_KERN_PARTID(nasid)	(KLD_BASE(nasid) + KLI_KERN_PARTID)
 
-#define LAUNCH_OFFSET(nasid, slice)					\
-	(KLD_LAUNCH(nasid)->offset +					\
-	 KLD_LAUNCH(nasid)->stride * (slice))
-#define LAUNCH_ADDR(nasid, slice)					\
-	TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
-#define LAUNCH_SIZE(nasid)	KLD_LAUNCH(nasid)->size
-
-#define NMI_OFFSET(nasid, slice)					\
-	(KLD_NMI(nasid)->offset +					\
-	 KLD_NMI(nasid)->stride * (slice))
-#define NMI_ADDR(nasid, slice)						\
-	TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
-#define NMI_SIZE(nasid)	KLD_NMI(nasid)->size
-
+#ifndef CONFIG_IA64_SGI_SN2
 #define KLCONFIG_OFFSET(nasid)	KLD_KLCONFIG(nasid)->offset
+#else
+#define KLCONFIG_OFFSET(nasid) \
+	ia64_sn_get_klconfig_addr(nasid)
+#endif /* CONFIG_IA64_SGI_SN2 */
+
 #define KLCONFIG_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+	TO_NODE_CAC((nasid), KLCONFIG_OFFSET(nasid))
 #define KLCONFIG_SIZE(nasid)	KLD_KLCONFIG(nasid)->size
 
 #define GDA_ADDR(nasid)		KLD_GDA(nasid)->pointer
 #define GDA_SIZE(nasid)		KLD_GDA(nasid)->size
 
-#define SYMMON_STK_OFFSET(nasid, slice)					\
-	(KLD_SYMMON_STK(nasid)->offset +				\
-	 KLD_SYMMON_STK(nasid)->stride * (slice))
-#define SYMMON_STK_STRIDE(nasid)	KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_ADDR(nasid, slice)					\
-	TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
-
-#define SYMMON_STK_SIZE(nasid)	KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_END(nasid)	(SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
-
-/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
- * relocatable program
- */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-/* update master.d/sn1_elspec.dbg, SN1/addrs.h/DEBUGUNIX_ADDR, and
- * DBGLOADADDR in symmon's Makefile when changing this */
-#define UNIX_DEBUG_LOADADDR     0x310000
-#elif defined(SN0XXL)
-#define UNIX_DEBUG_LOADADDR     0x360000
-#else
-#define	UNIX_DEBUG_LOADADDR	0x300000
-#endif
-#define	SYMMON_LOADADDR(nasid)						\
-	TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
-
-#define FREEMEM_OFFSET(nasid)	KLD_FREEMEM(nasid)->offset
-#define FREEMEM_ADDR(nasid)	SYMMON_STK_END(nasid)
-/*
- * XXX
- * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
- * Also, it should take into account what prom thinks to be a safe
- * address
-	PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
- */
-#define FREEMEM_SIZE(nasid)	KLD_FREEMEM(nasid)->size
-
-#define PI_ERROR_OFFSET(nasid)	KLD_PI_ERROR(nasid)->offset
-#define PI_ERROR_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
-#define PI_ERROR_SIZE(nasid)	KLD_PI_ERROR(nasid)->size
-
 #define NODE_OFFSET_TO_K0(_nasid, _off)					\
 	(PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off))
-#define K0_TO_NODE_OFFSET(_k0addr)					\
-	((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
-
-#define KERN_VARS_ADDR(nasid)	KLD_KERN_VARS(nasid)->pointer
-#define KERN_VARS_SIZE(nasid)	KLD_KERN_VARS(nasid)->size
-
-#define	KERN_XP_ADDR(nasid)	KLD_KERN_XP(nasid)->pointer
-#define	KERN_XP_SIZE(nasid)	KLD_KERN_XP(nasid)->size
-
-#define GPDA_ADDR(nasid)	TO_NODE_CAC(nasid, GPDA_OFFSET)
-
-#endif /* _LANGUAGE_C */
 
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_ADDRS_H */
+#endif /* _ASM_IA64_SN_ADDRS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/agent.h lia64-2.4/include/asm-ia64/sn/agent.h
--- linux-2.4.16/include/asm-ia64/sn/agent.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/agent.h	Wed Dec 31 16:00:00 1969
@@ -1,47 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * This file has definitions for the hub and snac interfaces.
- *
- * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SGI_SN_AGENT_H
-#define _ASM_SGI_SN_AGENT_H
-
-#include <linux/config.h>
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-//#include <asm/sn/io.h>
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/bedrock.h>
-#endif	/* CONFIG_SGI_IP35 */
-
-/*
- * NIC register macros
- */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define HUB_NIC_ADDR(_cpuid) 						   \
-	REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(_cpuid)),       \
-		LB_MICROLAN_CTL)
-#endif
-
-#define SET_HUB_NIC(_my_cpuid, _val) 				  	   \
-	(HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
-
-#define SET_MY_HUB_NIC(_v) 					           \
-	SET_HUB_NIC(cpuid(), (_v))
-
-#define GET_HUB_NIC(_my_cpuid) 						   \
-	(HUB_L(HUB_NIC_ADDR(_my_cpuid)))
-
-#define GET_MY_HUB_NIC() 						   \
-	GET_HUB_NIC(cpuid())
-
-#endif /* _ASM_SGI_SN_AGENT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/alenlist.h lia64-2.4/include/asm-ia64/sn/alenlist.h
--- linux-2.4.16/include/asm-ia64/sn/alenlist.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/alenlist.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_ALENLIST_H
-#define _ASM_SN_ALENLIST_H
+#ifndef _ASM_IA64_SN_ALENLIST_H
+#define _ASM_IA64_SN_ALENLIST_H
 
 /* Definition of Address/Length List */
 
@@ -201,4 +200,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_ALENLIST_H */
+#endif /* _ASM_IA64_SN_ALENLIST_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/arc/hinv.h lia64-2.4/include/asm-ia64/sn/arc/hinv.h
--- linux-2.4.16/include/asm-ia64/sn/arc/hinv.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/arc/hinv.h	Mon Nov 19 23:22:54 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
diff -urN linux-2.4.16/include/asm-ia64/sn/arc/types.h lia64-2.4/include/asm-ia64/sn/arc/types.h
--- linux-2.4.16/include/asm-ia64/sn/arc/types.h	Thu Apr 12 12:16:36 2001
+++ lia64-2.4/include/asm-ia64/sn/arc/types.h	Mon Nov 19 23:22:54 2001
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright 1999 Ralf Baechle (ralf@gnu.org)
- * Copyright 1999 Silicon Graphics, Inc.
+ * Copyright 1999,2001 Silicon Graphics, Inc.
  */
 #ifndef _ASM_SN_ARC_TYPES_H
 #define _ASM_SN_ARC_TYPES_H
diff -urN linux-2.4.16/include/asm-ia64/sn/arch.h lia64-2.4/include/asm-ia64/sn/arch.h
--- linux-2.4.16/include/asm-ia64/sn/arch.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/arch.h	Mon Nov 19 23:22:54 2001
@@ -6,88 +6,39 @@
  *
  * SGI specific setup.
  *
- * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1995-1997,1999,2001 Silcon Graphics, Inc. All rights reserved.
  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
  */
-#ifndef _ASM_SN_ARCH_H
-#define _ASM_SN_ARCH_H
+#ifndef _ASM_IA64_SN_ARCH_H
+#define _ASM_IA64_SN_ARCH_H
 
-#include <linux/types.h>
 #include <linux/config.h>
-
+#include <linux/threads.h>
 #include <asm/sn/types.h>
-#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_SGI_IP37) || defined(CONFIG_IA64_GENERIC)
+
+#if defined(CONFIG_IA64_SGI_SN1) 
 #include <asm/sn/sn1/arch.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/arch.h>
 #endif
 
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#if defined(CONFIG_IA64_SGI_SN1) 
+typedef u64	bdrkreg_t;
+#elif defined(CONFIG_IA64_SGI_SN2)
+typedef u64	shubreg_t;
+#endif
+
 typedef u64	hubreg_t;
+typedef u64	mmr_t;
 typedef u64	nic_t;
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-typedef u64     bdrkreg_t;
-#endif	/* CONFIG_SGI_xxxxx */
-#endif	/* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define CPUS_PER_NODE		4	/* CPUs on a single hub */
-#define CPUS_PER_NODE_SHFT	2	/* Bits to shift in the node number */
-#define CPUS_PER_SUBNODE	2	/* CPUs on a single hub PI */
-#endif
-#define CNODE_NUM_CPUS(_cnode)		(NODEPDA(_cnode)->node_num_cpus)
 
+#define CNODE_NUM_CPUS(_cnode)		(NODEPDA(_cnode)->node_num_cpus)
 #define CNODE_TO_CPU_BASE(_cnode)	(NODEPDA(_cnode)->node_first_cpu)
 
-#define makespnum(_nasid, _slice)					\
-		(((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-
-/*
- * There are 2 very similar macros for dealing with "slices". Make sure
- * you use the right one. 
- * Unfortunately, on all platforms except IP35 (currently), the 2 macros 
- * are interchangible. 
- *
- * On IP35, there are 4 cpus per node. Each cpu is refered to by it's slice.
- * The slices are numbered 0 thru 3. 
- *
- * There are also 2 PI interfaces per node. Each PI interface supports 2 cpus.
- * The term "local slice" specifies the cpu number relative to the PI.
- *
- * The cpus on the node are numbered:
- *	slice	localslice
- *	  0          0
- *	  1          1
- *	  2          0
- *	  3          1
- *
- *	cputoslice - returns a number 0..3 that is the slice of the specified cpu.
- *	cputolocalslice - returns a number 0..1 that identifies the local slice of
- *			the cpu within it's PI interface.
- */
-#ifdef LATER
-	/* These are dummied up for now ..... */
-#define cputocnode(cpu)				\
-               (pdaindr[(cpu)].p_nodeid)
-#define cputonasid(cpu)				\
-               (pdaindr[(cpu)].p_nasid)
-#define cputoslice(cpu)				\
-               (ASSERT(pdaindr[(cpu)].pda), (pdaindr[(cpu)].pda->p_slice))
-#define cputolocalslice(cpu)			\
-               (ASSERT(pdaindr[(cpu)].pda), (LOCALCPU(pdaindr[(cpu)].pda->p_slice)))
-#define cputosubnode(cpu)			\
-		(ASSERT(pdaindr[(cpu)].pda), (SUBNODE(pdaindr[(cpu)].pda->p_slice)))
-#else
-#define cputocnode(cpu) 0
-#define cputonasid(cpu) 0
-#define cputoslice(cpu) 0
-#define cputolocalslice(cpu) 0
-#define cputosubnode(cpu) 0
-#endif	/* LATER */
-#endif	/* CONFIG_SGI_IP35 */
+#define NASID_TO_COMPACT_NODEID(nasid)  (nasid_to_cnodeid(nasid))
+#define COMPACT_TO_NASID_NODEID(cnode)  (cnodeid_to_nasid(cnode))
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
 
 #define INVALID_NASID		(nasid_t)-1
 #define INVALID_CNODEID		(cnodeid_t)-1
@@ -95,91 +46,12 @@
 #define INVALID_MODULE		(moduleid_t)-1
 #define	INVALID_PARTID		(partid_t)-1
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-extern int     get_slice(void);
-extern cpuid_t get_cnode_cpu(cnodeid_t);
 extern int get_cpu_slice(cpuid_t);
 extern cpuid_t cnodetocpu(cnodeid_t);
-// extern cpuid_t cnode_slice_to_cpuid(cnodeid_t, int);
-
-extern int cnode_exists(cnodeid_t cnode);
-extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
-#endif	/* CONFIG_IP35 */
-
-extern nasid_t get_nasid(void);
-extern cnodeid_t get_cpu_cnode(int);
 extern int get_cpu_slice(cpuid_t);
+void   sn_flush_all_caches(long addr, long bytes);
 
-/*
- * NO ONE should access these arrays directly.  The only reason we refer to
- * them here is to avoid the procedure call that would be required in the
- * macros below.  (Really want private data members here :-)
- */
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+extern int     is_fine_dirmode(void);
 
-/*
- * These macros are used by various parts of the kernel to convert
- * between the three different kinds of node numbering.   At least some
- * of them may change to procedure calls in the future, but the macros
- * will continue to work.  Don't use the arrays above directly.
- */
 
-#define	NASID_TO_REGION(nnode)	      	\
-    ((nnode) >> \
-     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
-
-#ifndef __ia64
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
-extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
-
-#if !defined(DEBUG)
-
-#define NASID_TO_COMPACT_NODEID(nnode)	(nasid_to_compact_node[nnode])
-#define COMPACT_TO_NASID_NODEID(cnode)	(compact_to_nasid_node[cnode])
-#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
-#else
-
-/*
- * These functions can do type checking and fail if they need to return
- * a bad nodeid, but they're not as fast so just use 'em for debug kernels.
- */
-cnodeid_t nasid_to_compact_nodeid(nasid_t nasid);
-nasid_t compact_to_nasid_nodeid(cnodeid_t cnode);
-
-#define NASID_TO_COMPACT_NODEID(nnode)	nasid_to_compact_nodeid(nnode)
-#define COMPACT_TO_NASID_NODEID(cnode)	compact_to_nasid_nodeid(cnode)
-#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
-#endif
-
-#else
-
-/*
- * IA64 specific nasid and cnode ids.
- */
-#define NASID_TO_COMPACT_NODEID(nasid)  (nasid_to_cnodeid(nasid))
-#define COMPACT_TO_NASID_NODEID(cnode)  (cnodeid_to_nasid(cnode))
-#define CPUID_TO_COMPACT_NODEID(cpu)    (cpuid_to_cnodeid(cpu))
-
-#endif /* #ifndef __ia64 */
-
-extern int node_getlastslot(cnodeid_t);
-
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#define SLOT_BITMASK    	(MAX_MEM_SLOTS - 1)
-#define SLOT_SIZE		(1LL<<SLOT_SHIFT)
-
-#define node_getnumslots(node)	(MAX_MEM_SLOTS)
-#define NODE_MAX_MEM_SIZE	SLOT_SIZE * MAX_MEM_SLOTS
-
-/*
- * New stuff in here from Irix sys/pfdat.h.
- */
-#define	SLOT_PFNSHIFT		(SLOT_SHIFT - PAGE_SHIFT)
-#define	PFN_NASIDSHFT		(NASID_SHFT - PAGE_SHIFT)
-#define mkpfn(nasid, off)	(((pfn_t)(nasid) << PFN_NASIDSHFT) | (off))
-#define slot_getbasepfn(node,slot) \
-		(mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT))
-#endif /* _ASM_SN_ARCH_H */
+#endif /* _ASM_IA64_SN_ARCH_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ate_utils.h lia64-2.4/include/asm-ia64/sn/ate_utils.h
--- linux-2.4.16/include/asm-ia64/sn/ate_utils.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/ate_utils.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,47 @@
+#ifndef _ASM_IA64_SN_ATE_UTILS_H
+#define _ASM_IA64_SN_ATE_UTILS_H
+
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ *	struct map	X[]	.m_size		.m_addr
+ *			---	------------	-----------
+ *			[0]	mapsize(X)	unused
+ *				# X[] unused
+ *			[1]	map lock *	mapwant sv_t *
+ *				map access	wait for free map space
+ *
+ *	  mapstart(X)-> [2]	# units		unit number
+ *			 :	    :		  :
+ *			[ ]	    0
+ */
+
+struct map
+{
+	unsigned long m_size;	/* number of units available */
+	unsigned long m_addr;	/* address of first available unit */
+};
+
+#define mapstart(X)		&X[2]		/* start of map array */
+
+#define mapsize(X)		X[0].m_size	/* number of empty slots */
+						/* remaining in map array */
+#define maplock(X)		(((spinlock_t *) X[1].m_size))
+
+#define mapout(X)		((sv_t *) X[1].m_addr)
+
+
+extern ulong_t atealloc(struct map *, size_t);
+extern struct map *atemapalloc(ulong_t);
+extern void atefree(struct map *, size_t, ulong_t);
+extern void atemapfree(struct map *);
+
+#endif /* _ASM_IA64_SN_ATE_UTILS_H  */
+
diff -urN linux-2.4.16/include/asm-ia64/sn/cdl.h lia64-2.4/include/asm-ia64/sn/cdl.h
--- linux-2.4.16/include/asm-ia64/sn/cdl.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/cdl.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_CDL_H
-#define _ASM_SN_CDL_H
+#ifndef _ASM_IA64_SN_CDL_H
+#define _ASM_IA64_SN_CDL_H
 
 #include <asm/sn/sgi.h>
 
@@ -193,4 +192,4 @@
 void		async_attach_signal_done(async_attach_t);
 void		async_attach_waitall(async_attach_t);
 
-#endif	/* _ASM_SN_CDL_H */
+#endif /* _ASM_IA64_SN_CDL_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/clksupport.h lia64-2.4/include/asm-ia64/sn/clksupport.h
--- linux-2.4.16/include/asm-ia64/sn/clksupport.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/clksupport.h	Mon Nov 19 23:22:54 2001
@@ -4,61 +4,52 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-
-#ifndef  _ASM_KSYS_CLKSUPPORT_H
-#define _ASM_KSYS_CLKSUPPORT_H
-
-/* #include <sys/mips_addrspace.h> */
-
-#if SN
-#include <asm/sn/agent.h>
-#include <asm/sn/intr_public.h>
-typedef hubreg_t clkreg_t;
-extern nasid_t master_nasid;
-
-#define GET_LOCAL_RTC		(clkreg_t)LOCAL_HUB_L(PI_RT_COUNT)
-#define DISABLE_TMO_INTR()	if  (cpuid_to_localslice(cpuid())) \
-					REMOTE_HUB_PI_S(get_nasid(),\
-						cputosubnode(cpuid()),\
-						PI_RT_COMPARE_B, 0); \
-				else \
-					REMOTE_HUB_PI_S(get_nasid(),\
-						cputosubnode(cpuid()),\
-						PI_RT_COMPARE_A, 0);
-
-/* This is a hack; we really need to figure these values out dynamically */
-/* 
- * Since 800 ns works very well with various HUB frequencies, such as
- * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time.
- */
-#define NSEC_PER_CYCLE		800
-#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
 /*
- * Number of cycles per profiling intr 
+ * This file contains definitions for accessing a platform supported high resolution
+ * clock. The clock is monitonically increasing and can be accessed from any node
+ * in the system. The clock is synchronized across nodes - all nodes see the
+ * same value.
+ * 
+ *	RTC_COUNTER_ADDR - contains the address of the counter 
+ *
+ *	GET_RTC_COUNTER() - macro to read the value of the clock
+ *
+ *	RTC_CYCLES_PER_SEC - clock frequency in ticks per second	
+ *
  */
-#define CLK_FCLOCK_FAST_FREQ	1250
-#define CLK_FCLOCK_SLOW_FREQ	0
-/* The is the address that the user will use to mmap the cycle counter */
-#define CLK_CYCLE_ADDRESS_FOR_USER LOCAL_HUB_ADDR(PI_RT_COUNT)
-
-#elif IP30
-#include <sys/cpu.h>
-typedef heartreg_t clkreg_t;
-#define NSEC_PER_CYCLE		80
-#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
-#define GET_LOCAL_RTC	*((volatile clkreg_t *)PHYS_TO_COMPATK1(HEART_COUNT))
-#define DISABLE_TMO_INTR()
-#define CLK_CYCLE_ADDRESS_FOR_USER PHYS_TO_K1(HEART_COUNT)
-#define CLK_FCLOCK_SLOW_FREQ (CYCLE_PER_SEC / HZ)
+
+#ifndef _ASM_IA64_SN_CLKSUPPORT_H
+#define _ASM_IA64_SN_CLKSUPPORT_H
+
+#include <linux/config.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+
+typedef long clkreg_t;
+extern long sn_rtc_cycles_per_second;
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/sn1/hubpi_next.h>
+#ifdef BRINGUP
+/* clocks are not synchronized yet on SN1  - used node 0 (problem if no NASID 0) */
+#define RTC_COUNTER_ADDR	((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COUNTER))
+#else
+#define RTC_COUNTER_ADDR	((clkreg_t*)LOCAL_HUB_ADDR(PI_RT_COUNTER))
+#endif
+#else
+#include <asm/sn/sn2/shub_mmr.h>
+#define RTC_COUNTER_ADDR	((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
 #endif
 
-/* Prototypes */
-extern void init_timebase(void);
-extern void fastick_maint(struct eframe_s *);
-extern int audioclock;
-extern int prfclk_enabled_cnt;
-#endif  /* _ASM_KSYS_CLKSUPPORT_H */
+
+#define GET_RTC_COUNTER()	(*RTC_COUNTER_ADDR)
+#define rtc_time()		GET_RTC_COUNTER()
+
+#define RTC_CYCLES_PER_SEC	sn_rtc_cycles_per_second
+
+#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/dmamap.h lia64-2.4/include/asm-ia64/sn/dmamap.h
--- linux-2.4.16/include/asm-ia64/sn/dmamap.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/dmamap.h	Mon Nov 26 18:05:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_DMAMAP_H
-#define _ASM_SN_DMAMAP_H
+#ifndef _ASM_IA64_SN_DMAMAP_H
+#define _ASM_IA64_SN_DMAMAP_H
 
 #include <asm/sn/sv.h>
 
@@ -70,7 +69,6 @@
 extern int a24_mapsize;
 extern int a32_mapsize;
 
-extern lock_t dmamaplock;
 extern sv_t dmamapout;
 
 #ifdef __cplusplus
@@ -87,4 +85,4 @@
 
 #define	DMAMAP_FLAGS	0x7
 
-#endif /* _ASM_SN_DMAMAP_H */
+#endif /* _ASM_IA64_SN_DMAMAP_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/driver.h lia64-2.4/include/asm-ia64/sn/driver.h
--- linux-2.4.16/include/asm-ia64/sn/driver.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/driver.h	Mon Nov 26 18:07:20 2001
@@ -4,11 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_DRIVER_H
-#define _ASM_SN_DRIVER_H
+#ifndef _ASM_IA64_SN_DRIVER_H
+#define _ASM_IA64_SN_DRIVER_H
+
+#include <linux/devfs_fs_kernel.h>
 
 /*
 ** Interface for device driver handle management.
@@ -18,133 +19,91 @@
 */
 
 typedef struct device_driver_s *device_driver_t;
-#define DEVICE_DRIVER_NONE (device_driver_t)NULL
 
 /* == Driver thread priority support == */
 typedef int ilvl_t;
-/* default driver thread priority level */
-#define DRIVER_THREAD_PRI_DEFAULT	(ilvl_t)230
-/* invalid driver thread priority level */
-#define DRIVER_THREAD_PRI_INVALID	(ilvl_t)-1
-
-/* Associate a thread priority with a driver */
-extern int device_driver_thread_pri_set(device_driver_t driver,
-					ilvl_t pri);
-
-/* Get the thread priority associated with the driver */
-extern ilvl_t device_driver_thread_pri_get(device_driver_t driver);
-
-/* Get the thread priority for a driver from the sysgen paramters */
-extern ilvl_t device_driver_sysgen_thread_pri_get(char *driver_prefix);
-
-/* Initialize device driver functions. */
-extern void device_driver_init(void);
-
 
-/* Allocate a driver handle */
-extern device_driver_t device_driver_alloc(char *prefix);
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct eframe_s;
+struct piomap;
+struct dmamap;
 
 
-/* Free a driver handle */
-extern void device_driver_free(device_driver_t driver);
-
-
-/* Given a device driver prefix, return a handle to the driver. */
-extern device_driver_t device_driver_get(char *prefix);
-
-/* Given a device, return a handle to the driver. */
-extern device_driver_t device_driver_getbydev(devfs_handle_t device);
+/* for ilvl_t interrupt level, for use with intr_block_level.  Can't
+ * typedef twice without causing warnings, and some users of this header
+ * file do not already include driver.h, but expect ilvl_t to be defined,
+ * while others include both, leading to the warning ...
+ */
 
-struct cdevsw;
-struct bdevsw;
+#include <asm/types.h>
 
-/* Associate a driver with bdevsw/cdevsw pointers. */
-extern int
-device_driver_devsw_put(device_driver_t driver,
-			struct bdevsw *my_bdevsw,
-			struct cdevsw *my_cdevsw);
+typedef __psunsigned_t iobush_t;
 
+typedef struct device_driver_s *device_driver_t;
+ 
+/* == Driver thread priority support == */
+typedef int ilvl_t;
 
-/* Given a driver, return the corresponding bdevsw and cdevsw pointers. */
-extern void
-device_driver_devsw_get(	device_driver_t driver, 
-				struct bdevsw **bdevswp,
-				struct cdevsw **cdevswp);
+/* interrupt function */
+typedef void	       *intr_arg_t;
+typedef void		intr_func_f(intr_arg_t);
+typedef intr_func_f    *intr_func_t;
+
+#define	INTR_ARG(n)	((intr_arg_t)(__psunsigned_t)(n))
+
+/* system interrupt resource handle -- returned from intr_alloc */
+typedef struct intr_s *intr_t;
+#define INTR_HANDLE_NONE ((intr_t)0)
 
-/* Given a driver, return its name (prefix). */
-extern void device_driver_name_get(device_driver_t driver, char *buffer, int length);
+/*
+ * restore interrupt level value, returned from intr_block_level
+ * for use with intr_unblock_level.
+ */
+typedef void *rlvl_t;
 
 
 /* 
- * A descriptor for every static device driver in the system.
- * lboot creates a table of these and places in in master.c.
- * device_driver_init runs through this table during initialization
- * in order to "register" every static device driver.
+ * A basic, platform-independent description of I/O requirements for
+ * a device. This structure is usually formed by lboot based on information 
+ * in configuration files.  It contains information about PIO, DMA, and
+ * interrupt requirements for a specific instance of a device.
+ *
+ * The pio description is currently unused.
+ *
+ * The dma description describes bandwidth characteristics and bandwidth
+ * allocation requirements. (TBD)
+ *
+ * The Interrupt information describes the priority of interrupt, desired 
+ * destination, policy (TBD), whether this is an error interrupt, etc.  
+ * For now, interrupts are targeted to specific CPUs.
  */
-typedef struct static_device_driver_desc_s {
-	char 		*sdd_prefix;
-	struct bdevsw 	*sdd_bdevsw;
-	struct cdevsw 	*sdd_cdevsw;
-} *static_device_driver_desc_t;
-
-extern struct static_device_driver_desc_s static_device_driver_table[];
-extern int static_devsw_count;
-
 
-/*====== administration support ========== */
-/* structure of each entry in the table created by lboot for
- * device / driver administration
-*/
-typedef struct dev_admin_info_s {
-	char	*dai_name;		/* name of the device or driver
-					 * prefix 
-					 */
-	char	*dai_param_name;	/* device or driver parameter name */
-	char	*dai_param_val;		/* value of the parameter */
-} dev_admin_info_t;
-
-
-/* Update all the administrative hints associated with the device */
-extern void 	device_admin_info_update(devfs_handle_t	dev_vhdl);
-
-/* Update all the administrative hints associated with the device driver */
-extern void	device_driver_admin_info_update(device_driver_t	driver);
-
-/* Get a particular administrative hint associated with a device */
-extern char 	*device_admin_info_get(devfs_handle_t	dev_vhdl,
-				       char		*info_lbl);
-
-/* Associate a particular administrative hint for a device */
-extern int	device_admin_info_set(devfs_handle_t	dev_vhdl,
-				      char		*info_lbl,
-				      char		*info_val);
-
-/* Get a particular administrative hint associated with a device driver*/
-extern char 	*device_driver_admin_info_get(char	*driver_prefix,	
-					      char	*info_name);
-
-/* Associate a particular administrative hint for a device driver*/
-extern int	device_driver_admin_info_set(char	*driver_prefix,
-					     char	*driver_info_lbl,
-					     char	*driver_info_val);
-
-/* Initialize the extended device administrative hint table */
-extern void	device_admin_table_init(void);
+typedef struct device_desc_s {
+	/* pio description (currently none) */
 
-/* Add a hint corresponding to a device to the extended device administrative
- * hint table.
- */
-extern void	device_admin_table_update(char *dev_name,
-					  char *param_name,
-					  char *param_val);
+	/* dma description */
+	/* TBD: allocated badwidth requirements */
 
-/* Initialize the extended device driver administrative hint table */
-extern void	device_driver_admin_table_init(void);
-
-/* Add a hint corresponding to a device to the extended device driver 
- * administrative hint table.
- */
-extern void	device_driver_admin_table_update(char *drv_prefix,
-						 char *param_name,
-						 char *param_val);	
-#endif /* _ASM_SN_DRIVER_H */
+	/* interrupt description */
+	devfs_handle_t	intr_target;	/* Hardware locator string */
+	int 		intr_policy;	/* TBD */
+	ilvl_t		intr_swlevel;	/* software level for blocking intr */
+	char		*intr_name;	/* name of interrupt, if any */
+
+	int		flags;
+} *device_desc_t;
+
+/* flag values */
+#define	D_INTR_ISERR	0x1		/* interrupt is for error handling */
+#define D_IS_ASSOC	0x2		/* descriptor is associated with a dev */
+#define D_INTR_NOTHREAD	0x4		/* Interrupt handler isn't threaded. */
+
+#define INTR_SWLEVEL_NOTHREAD_DEFAULT 	0	/* Default
+						 * Interrupt level in case of
+						 * non-threaded interrupt 
+						 * handlers
+						 */
+#endif /* _ASM_IA64_SN_DRIVER_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/eeprom.h lia64-2.4/include/asm-ia64/sn/eeprom.h
--- linux-2.4.16/include/asm-ia64/sn/eeprom.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/eeprom.h	Mon Nov 19 23:22:54 2001
@@ -6,11 +6,10 @@
  *
  * Public interface for reading Atmel EEPROMs via L1 system controllers
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_EEPROM_H
-#define _ASM_SN_EEPROM_H
+#ifndef _ASM_IA64_SN_EEPROM_H
+#define _ASM_IA64_SN_EEPROM_H
 
 #include <asm/sn/sgi.h>
 #include <asm/sn/vector.h>
@@ -395,4 +394,4 @@
 #define ROUTER_UID_GET(d,p)	rbrick_uid_get(get_nasid(),(d),(p))
 #define XBOW_UID_GET(n,p)	iobrick_uid_get((n),(p))
 
-#endif /* _ASM_SN_EEPROM_H */
+#endif /* _ASM_IA64_SN_EEPROM_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/fetchop.h lia64-2.4/include/asm-ia64/sn/fetchop.h
--- linux-2.4.16/include/asm-ia64/sn/fetchop.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/fetchop.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,33 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_FETCHOP_H
+#define _ASM_IA64_SN_FETCHOP_H
+
+#define FETCHOP_BASENAME	"sgi_fetchop"
+#define FETCHOP_FULLNAME	"/dev/sgi_fetchop"
+
+
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD		0
+#define FETCHOP_INCREMENT	8
+#define FETCHOP_DECREMENT	16
+#define FETCHOP_CLEAR		24
+
+#define FETCHOP_STORE		0
+#define FETCHOP_AND		24
+#define FETCHOP_OR		32
+
+#define FETCHOP_CLEAR_CACHE	56
+
+#endif /* _ASM_IA64_SN_FETCHOP_H */
+
diff -urN linux-2.4.16/include/asm-ia64/sn/gda.h lia64-2.4/include/asm-ia64/sn/gda.h
--- linux-2.4.16/include/asm-ia64/sn/gda.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/gda.h	Mon Nov 19 23:22:54 2001
@@ -6,16 +6,17 @@
  *
  * Derived from IRIX <sys/SN/gda.h>.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  *
  * gda.h -- Contains the data structure for the global data area,
  * 	The GDA contains information communicated between the
  *	PROM, SYMMON, and the kernel. 
  */
-#ifndef _ASM_SN_GDA_H
-#define _ASM_SN_GDA_H
+#ifndef _ASM_IA64_SN_GDA_H
+#define _ASM_IA64_SN_GDA_H
 
 #include <asm/sn/addrs.h>
+#include <asm/sn/sn_cpuid.h>
 
 #define GDA_MAGIC	0x58464552
 
@@ -42,7 +43,7 @@
 #define G_PARTIDOFF	40
 #define G_TABLEOFF	128
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 typedef struct gda {
 	u32	g_magic;	/* GDA magic number */
@@ -68,7 +69,7 @@
 
 #define GDA ((gda_t*) GDA_ADDR(get_nasid()))
 
-#endif /* __LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 /*
  * Define:	PART_GDA_VERSION
  * Purpose:	Define the minimum version of the GDA required, lower 
@@ -105,4 +106,4 @@
 #define PROMOP_BIST1		0x0800		/* keep track of which BIST ran */
 #define PROMOP_BIST2		0x1000		/* keep track of which BIST ran */
 
-#endif /* _ASM_SN_GDA_H */
+#endif /* _ASM_IA64_SN_GDA_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/hack.h lia64-2.4/include/asm-ia64/sn/hack.h
--- linux-2.4.16/include/asm-ia64/sn/hack.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/hack.h	Mon Nov 19 23:22:54 2001
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
-#ifndef _ASM_SN_HACK_H
-#define _ASM_SN_HACK_H
+#ifndef _ASM_IA64_SN_HACK_H
+#define _ASM_IA64_SN_HACK_H
 
 #include <asm/sn/types.h>
 #include <asm/uaccess.h>		/* for copy_??_user */
@@ -32,7 +31,6 @@
 #include <linux/devfs_fs_kernel.h>
 
 #define DELAY(a)
-#define cpuid() 0
 
 /************************************************
  * Routines redefined to use linux equivalents. *
@@ -59,14 +57,14 @@
 #define spl7	splhi()
 #define splx(s)
 
-extern void * kmem_alloc_node(register size_t, register int, cnodeid_t);
-extern void * kmem_zalloc(size_t, int);
-extern void * kmem_zalloc_node(register size_t, register int, cnodeid_t );
-extern void * kmem_zone_alloc(register zone_t *, int);
-extern zone_t * kmem_zone_init(register int , char *);
-extern void kmem_zone_free(register zone_t *, void *);
+extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t);
+extern void * snia_kmem_zalloc(size_t, int);
+extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t );
+extern void * snia_kmem_zone_alloc(register zone_t *, int);
+extern zone_t * snia_kmem_zone_init(register int , char *);
+extern void snia_kmem_zone_free(register zone_t *, void *);
 extern int is_specified(char *);
 extern int cap_able(uint64_t);
 extern int compare_and_swap_ptr(void **, void *, void *);
 
-#endif	/* _ASM_SN_HACK_H */
+#endif /* _ASM_IA64_SN_HACK_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/hcl.h lia64-2.4/include/asm-ia64/sn/hcl.h
--- linux-2.4.16/include/asm-ia64/sn/hcl.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/hcl.h	Mon Nov 19 23:22:54 2001
@@ -4,13 +4,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_HCL_H
-#define _ASM_SN_HCL_H
+#ifndef _ASM_IA64_SN_HCL_H
+#define _ASM_IA64_SN_HCL_H
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/invent.h>
+#include <linux/devfs_fs_kernel.h>
 
-extern spinlock_t hcl_spinlock;
 extern devfs_handle_t hcl_handle; /* HCL driver */
 extern devfs_handle_t hwgraph_root;
 extern devfs_handle_t linux_busnum;
@@ -93,7 +95,6 @@
 extern devfs_handle_t hwgraph_char_device_get(devfs_handle_t);
 extern graph_error_t hwgraph_char_device_add(devfs_handle_t, char *, char *, devfs_handle_t *);
 extern int hwgraph_path_add(devfs_handle_t, char *, devfs_handle_t *);
-extern struct file_operations * hwgraph_bdevsw_get(devfs_handle_t);
 extern int hwgraph_info_add_LBL(devfs_handle_t, char *, arbitrary_info_t);
 extern int hwgraph_info_get_LBL(devfs_handle_t, char *, arbitrary_info_t *);
 extern int hwgraph_info_replace_LBL(devfs_handle_t, char *, arbitrary_info_t,
@@ -111,4 +112,4 @@
 
 
 
-#endif /* _ASM_SN_HCL_H */
+#endif /* _ASM_IA64_SN_HCL_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/hcl_util.h lia64-2.4/include/asm-ia64/sn/hcl_util.h
--- linux-2.4.16/include/asm-ia64/sn/hcl_util.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/hcl_util.h	Mon Nov 19 23:22:54 2001
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_HCL_UTIL_H
-#define _ASM_SN_HCL_UTIL_H
+#ifndef _ASM_IA64_SN_HCL_UTIL_H
+#define _ASM_IA64_SN_HCL_UTIL_H
 
 extern char * dev_to_name(devfs_handle_t, char *, uint);
 extern int device_master_set(devfs_handle_t, devfs_handle_t);
@@ -17,8 +16,5 @@
 extern cnodeid_t master_node_get(devfs_handle_t);
 extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t);
 extern void mark_nodevertex_as_node(devfs_handle_t, cnodeid_t);
-extern void device_info_set(devfs_handle_t, void *);
-extern void *device_info_get(devfs_handle_t);
 
-
-#endif _ASM_SN_HCL_UTIL_H
+#endif /* _ASM_IA64_SN_HCL_UTIL_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/hires_clock.h lia64-2.4/include/asm-ia64/sn/hires_clock.h
--- linux-2.4.16/include/asm-ia64/sn/hires_clock.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/hires_clock.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ *
+ * SGI Hi Resolution Clock
+ *
+ * SGI SN platforms provide a high resolution clock that is
+ * synchronized across all nodes. The clock can be memory mapped
+ * and directly read from user space.
+ *
+ * Access to the clock is thru the following:
+ *       (error checking not shown)
+ *
+ * (Note: should library routines be provided to encapsulate this??)
+ *
+ *	int		fd:
+ *	volatile long	*clk;
+ *
+ *	fd = open (HIRES_FULLNAME, O_RDONLY);
+ *	clk = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, fd, 0);
+ *	clk += ioctl(fd, HIRES_IOCQGETOFFSET, 0);
+ *
+ * At this point, clk is a pointer to the high resolution clock.
+ *
+ * The clock period can be obtained via:
+ *
+ *	long	picosec_per_tick;
+ *	picosec_per_tick = ioctl(fd, HIRES_IOCQGETPICOSEC, 0);
+ */
+
+#ifndef _ASM_IA64_SN_HIRES_CLOCK_H
+#define _ASM_IA64_SN_HIRES_CLOCK_H
+
+
+#define HIRES_BASENAME	"sgi_hires_clock"
+#define HIRES_FULLNAME  "/dev/sgi_hires_clock"
+#define HIRES_IOC_BASE	's'
+
+
+/* Get page offset of hires timer */
+#define HIRES_IOCQGETOFFSET	_IO( HIRES_IOC_BASE, 0 )
+
+/* get clock period in picoseconds per tick */
+#define HIRES_IOCQGETPICOSEC	_IO( HIRES_IOC_BASE, 1 )
+
+/* get number of significant bits in clock counter */
+#define HIRES_IOCQGETCLOCKBITS	_IO( HIRES_IOC_BASE, 2 )
+
+#endif /* _ASM_IA64_SN_HIRES_CLOCK_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/hubspc.h lia64-2.4/include/asm-ia64/sn/hubspc.h
--- linux-2.4.16/include/asm-ia64/sn/hubspc.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/hubspc.h	Wed Dec 31 16:00:00 1969
@@ -1,25 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_HUBSPC_H
-#define _ASM_SN_HUBSPC_H
-
-typedef enum {
-        HUBSPC_REFCOUNTERS,
-	HUBSPC_PROM
-} hubspc_subdevice_t;
-
-
-/*
- * Reference Counters
- */
-
-extern int refcounters_attach(devfs_handle_t hub);
-
-#endif /* _ASM_SN_HUBSPC_H */        
diff -urN linux-2.4.16/include/asm-ia64/sn/hwcntrs.h lia64-2.4/include/asm-ia64/sn/hwcntrs.h
--- linux-2.4.16/include/asm-ia64/sn/hwcntrs.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/hwcntrs.h	Wed Dec 31 16:00:00 1969
@@ -1,97 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_HWCNTRS_H
-#define _ASM_SN_HWCNTRS_H
-
-
-typedef  uint64_t refcnt_t;
-
-#define SN0_REFCNT_MAX_COUNTERS 64
-
-typedef struct sn0_refcnt_set {
-	refcnt_t    refcnt[SN0_REFCNT_MAX_COUNTERS];
-        uint64_t  flags;
-        uint64_t  reserved[4];
-} sn0_refcnt_set_t;
-
-typedef struct sn0_refcnt_buf {
-	sn0_refcnt_set_t   refcnt_set;
-	uint64_t         paddr;
-        uint64_t         page_size;
-        cnodeid_t          cnodeid;         /* cnodeid + pad[3] use 64 bits */
-        uint16_t           pad[3];
-        uint64_t         reserved[4];
-} sn0_refcnt_buf_t;
-
-typedef struct sn0_refcnt_args {
-	uint64_t          vaddr;
-	uint64_t          len;
-	sn0_refcnt_buf_t*   buf;
-        uint64_t          reserved[4];
-} sn0_refcnt_args_t;
-
-/*
- * Info needed by the user level program
- * to mmap the refcnt buffer
- */
-
-#define RCB_INFO_GET  1
-#define RCB_SLOT_GET  2
-
-typedef struct rcb_info {
-        uint64_t  rcb_len;                  /* total refcnt buffer len in bytes */
-
-        int         rcb_sw_sets;              /* number of sw counter sets in buffer */
-        int         rcb_sw_counters_per_set;  /* sw counters per set -- numnodes */
-        int         rcb_sw_counter_size;      /* sizeof(refcnt_t) -- size of sw cntr */
-
-        int         rcb_base_pages;           /* number of base pages in node */
-        int         rcb_base_page_size;       /* sw base page size */        
-        uint64_t  rcb_base_paddr;           /* base physical address for this node */
-
-        int         rcb_cnodeid;              /* cnodeid for this node */
-        int         rcb_granularity;          /* hw page size used for counter sets */
-        uint        rcb_hw_counter_max;       /* max hwcounter count (width mask) */
-        int         rcb_diff_threshold;       /* current node differential threshold */
-        int         rcb_abs_threshold;        /* current node absolute threshold */
-        int         rcb_num_slots;            /* physmem slots */
-        
-        int         rcb_reserved[512];
-        
-} rcb_info_t;
-
-typedef struct rcb_slot {
-        uint64_t  base;
-        uint64_t  size;
-} rcb_slot_t;
-
-#if defined(__KERNEL__)
-typedef struct sn0_refcnt_args_32 {
-	uint64_t    vaddr;
-	uint64_t    len;
-	app32_ptr_t   buf;
-        uint64_t    reserved[4];
-} sn0_refcnt_args_32_t;
-
-/* Defines and Macros  */
-/* A set of reference counts are for 4k bytes of physical memory */
-#define	NBPREFCNTP	0x1000	
-#define	BPREFCNTPSHIFT	12
-#define bytes_to_refcntpages(x)	(((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT)
-#define refcntpage_offset(x)	((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1)))
-#define align_to_refcntpage(x)	((__psunsigned_t)(x)&(~(NBPREFCNTP-1)))
-
-extern void migr_refcnt_read(sn0_refcnt_buf_t*);
-extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*);
-extern int migr_refcnt_enabled(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SN_HWCNTRS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/idle.h lia64-2.4/include/asm-ia64/sn/idle.h
--- linux-2.4.16/include/asm-ia64/sn/idle.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/idle.h	Mon Nov 26 18:07:23 2001
@@ -0,0 +1,54 @@
+#ifndef _ASM_IA64_SN_IDLE_H
+#define _ASM_IA64_SN_IDLE_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/sn/leds.h>
+#include <asm/sn/simulator.h>
+
+static __inline__ void
+snidle() {
+
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+	{
+		extern int	autotest_enabled;
+		if (autotest_enabled) {
+			extern void llsc_main(int, long, long);
+			llsc_main(smp_processor_id(), 0xe000000000000000LL, 0xe000000001000000LL);
+		}
+	}
+#endif
+	
+	if (pda.idle_flag == 0) {
+		/* 
+		 * Turn the activity LED off.
+		 */
+		set_led_bits(0, LED_CPU_ACTIVITY);
+	}
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+	if (IS_RUNNING_ON_SIMULATOR())
+		SIMULATOR_SLEEP();
+#endif
+
+	pda.idle_flag = 1;
+}
+
+static __inline__ void
+snidleoff() {
+	/* 
+	 * Turn the activity LED on.
+	 */
+	set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY);
+
+	pda.idle_flag = 0;
+}
+
+#endif /* _ASM_IA64_SN_IDLE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ifconfig_net.h lia64-2.4/include/asm-ia64/sn/ifconfig_net.h
--- linux-2.4.16/include/asm-ia64/sn/ifconfig_net.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/ifconfig_net.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_IFCONFIG_NET_H
+#define _ASM_IA64_SN_IFCONFIG_NET_H
+
+#define NETCONFIG_FILE "/tmp/ifconfig_net"
+#define POUND_CHAR                   '#'
+#define MAX_LINE_LEN 128
+#define MAXPATHLEN 128
+
+struct ifname_num {
+	long next_eth;
+	long next_fddi;
+	long next_hip;
+	long next_tr;
+	long next_fc;
+	long size;
+};
+
+struct ifname_MAC {
+	char name[16];
+	unsigned char           dev_addr[7];
+	unsigned char           addr_len;       /* hardware address length      */
+};
+
+#endif /* _ASM_IA64_SN_IFCONFIG_NET_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/intr.h lia64-2.4/include/asm-ia64/sn/intr.h
--- linux-2.4.16/include/asm-ia64/sn/intr.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/intr.h	Mon Nov 19 23:22:54 2001
@@ -4,250 +4,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INTR_H
-#define _ASM_SN_INTR_H
-
-/* Subnode wildcard */
-#define SUBNODE_ANY		-1
-
-/* Number of interrupt levels associated with each interrupt register. */
-#define N_INTPEND_BITS		64
-
-#define INT_PEND0_BASELVL	0
-#define INT_PEND1_BASELVL	64
-
-#define	N_INTPENDJUNK_BITS	8
-#define	INTPENDJUNK_CLRBIT	0x80
+#ifndef _ASM_IA64_SN_INTR_H
+#define _ASM_IA64_SN_INTR_H
 
 #include <linux/config.h>
-#include <asm/sn/intr_public.h>
-
-#if LANGUAGE_C
-
-#define II_NAMELEN	24
-
-/*
- * Dispatch table entry - contains information needed to call an interrupt
- * routine.
- */
-typedef struct intr_vector_s {
-	intr_func_t	iv_func;	/* Interrupt handler function */
-	intr_func_t	iv_prefunc;	/* Interrupt handler prologue func */
-	void		*iv_arg;	/* Argument to pass to handler */
-#ifdef LATER
-	thd_int_t		iv_tinfo;	/* Thread info */
-#endif
-	cpuid_t			iv_mustruncpu;	/* Where we must run. */
-} intr_vector_t;
-
-/* Interrupt information table. */
-typedef struct intr_info_s {
-	xtalk_intr_setfunc_t	ii_setfunc;	/* Function to set the interrupt
-						 * destination and level register.
-						 * It returns 0 (success) or an
-						 * error code.
-						 */
-	void			*ii_cookie;	/* arg passed to setfunc */
-	devfs_handle_t		ii_owner_dev;	/* device that owns this intr */
-	char			ii_name[II_NAMELEN];	/* Name of this intr. */
-	int			ii_flags;	/* informational flags */
-} intr_info_t;
-
-#define iv_tflags	iv_tinfo.thd_flags
-#define iv_isync	iv_tinfo.thd_isync
-#define iv_lat		iv_tinfo.thd_latstats
-#define iv_thread	iv_tinfo.thd_ithread
-#define iv_pri		iv_tinfo.thd_pri
-
-#define THD_CREATED	0x00000001	/*
-					 * We've created a thread for this
-					 * interrupt.
-					 */
-
-/*
- * Bits for ii_flags:
- */
-#define II_UNRESERVE	0
-#define II_RESERVE	1		/* Interrupt reserved. 			*/
-#define II_INUSE	2		/* Interrupt connected 			*/
-#define II_ERRORINT	4		/* INterrupt is an error condition 	*/
-#define II_THREADED	8		/* Interrupt handler is threaded.	*/
-
-/*
- * Interrupt level wildcard
- */
-#define INTRCONNECT_ANYBIT	-1
-
-/*
- * This structure holds information needed both to call and to maintain
- * interrupts.  The two are in separate arrays for the locality benefits.
- * Since there's only one set of vectors per hub chip (but more than one
- * CPU, the lock to change the vector tables must be here rather than in
- * the PDA.
- */
-
-typedef struct intr_vecblk_s {
-	intr_vector_t	vectors[N_INTPEND_BITS];  /* information needed to
-						     call an intr routine. */
-	intr_info_t	info[N_INTPEND_BITS];	  /* information needed only
-						     to maintain interrupts. */
-	spinlock_t	vector_lock;		  /* Lock for this and the
-						     masks in the PDA. */
-	splfunc_t	vector_spl;		  /* vector_lock req'd spl */
-	int		vector_state;		  /* Initialized to zero.
-						     Set to INTR_INITED
-						     by hubintr_init.
-						   */
-	int		vector_count;		  /* Number of vectors
-						   * reserved.
-						   */
-	int		cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
-						   * connected to each CPU
-						   */
-	int		ithreads_enabled;	  /* Are interrupt threads
-						   * initialized on this node.
-						   * and block?
-						   */
-} intr_vecblk_t;
-
-/* Possible values for vector_state: */
-#define VECTOR_UNINITED	0
-#define VECTOR_INITED	1
-#define VECTOR_SET	2
-
-#define hub_intrvect0	private.p_intmasks.dispatch0->vectors
-#define hub_intrvect1	private.p_intmasks.dispatch1->vectors
-#define hub_intrinfo0	private.p_intmasks.dispatch0->info
-#define hub_intrinfo1	private.p_intmasks.dispatch1->info
-
-/*
- * Macros to manipulate the interrupt register on the calling hub chip.
- */
-
-#define LOCAL_HUB_SEND_INTR(_level)	LOCAL_HUB_S(PI_INT_PEND_MOD, \
-						    (0x100|(_level)))
-#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
-		REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
-
-#define REMOTE_CPU_SEND_INTR(_cpuid, _level) 					\
-		REMOTE_HUB_PI_S(cputonasid(_cpuid),				\
-			SUBNODE(cputoslice(_cpuid)),				\
-			PI_INT_PEND_MOD, (0x100|(_level)))
-
-/*
- * When clearing the interrupt, make sure this clear does make it 
- * to the hub. Otherwise we could end up losing interrupts.
- * We do an uncached load of the int_pend0 register to ensure this.
- */
-
-#define LOCAL_HUB_CLR_INTR(_level)	  \
-                LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)),	\
-                LOCAL_HUB_L(PI_INT_PEND0)
-#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
-		REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)),	\
-                REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
-
-/* Special support for use by gfx driver only.  Supports special gfx hub interrupt. */
-extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
-
-void setrtvector(intr_func_t func);
-
-/*
- * Interrupt blocking
- */
-extern void intr_block_bit(cpuid_t cpu, int bit);
-extern void intr_unblock_bit(cpuid_t cpu, int bit);
-
-#endif /* LANGUAGE_C */
-
-/*
- * Hard-coded interrupt levels:
- */
-
-/*
- *	L0 = SW1
- *	L1 = SW2
- *	L2 = INT_PEND0
- *	L3 = INT_PEND1
- *	L4 = RTC
- *	L5 = Profiling Timer
- *	L6 = Hub Errors
- *	L7 = Count/Compare (T5 counters)
- */
-
-
-/* INT_PEND0 hard-coded bits. */
-#ifdef DEBUG_INTR_TSTAMP
-/* hard coded interrupt level for interrupt latency test interrupt */
-#define	CPU_INTRLAT_B	62
-#define	CPU_INTRLAT_A	61
-#endif
-
-/* Hardcoded bits required by software. */
-#define MSC_MESG_INTR	9
-#define CPU_ACTION_B	8
-#define CPU_ACTION_A	7
-
-/* These are determined by hardware: */
-#define CC_PEND_B	6
-#define CC_PEND_A	5
-#define UART_INTR	4
-#define PG_MIG_INTR	3
-#define GFX_INTR_B	2
-#define GFX_INTR_A	1
-#define RESERVED_INTR	0
-
-/* INT_PEND1 hard-coded bits: */
-#define MSC_PANIC_INTR	63
-#define NI_ERROR_INTR	62
-#define MD_COR_ERR_INTR	61
-#define COR_ERR_INTR_B	60
-#define COR_ERR_INTR_A	59
-#define CLK_ERR_INTR	58
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-# define NACK_INT_B	57
-# define NACK_INT_A	56
-# define LB_ERROR	55
-# define XB_ERROR	54
-#else
-	<< BOMB! >>  Must define IP27 or IP35 or IP37
-#endif
-
-#define BRIDGE_ERROR_INTR 53	/* Setup by PROM to catch Bridge Errors */
-
-#define IP27_INTR_0	52	/* Reserved for PROM use */
-#define IP27_INTR_1	51	/*   (do not use in Kernel) */
-#define IP27_INTR_2	50
-#define IP27_INTR_3	49
-#define IP27_INTR_4	48
-#define IP27_INTR_5	47
-#define IP27_INTR_6	46
-#define IP27_INTR_7	45
-
-#define	TLB_INTR_B	44	/* used for tlb flush random */
-#define	TLB_INTR_A	43
-
-#define LLP_PFAIL_INTR_B 42	/* see ml/SN/SN0/sysctlr.c */
-#define LLP_PFAIL_INTR_A 41
-
-#define NI_BRDCAST_ERR_B 40
-#define NI_BRDCAST_ERR_A 39
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-# define IO_ERROR_INTR	38	/* set up by prom */
-# define DEBUG_INTR_B	37	/* used by symmon to stop all cpus */
-# define DEBUG_INTR_A	36
-#endif
 
-#ifdef CONFIG_IA64_SGI_SN1
-// These aren't strictly accurate or complete.  See the
-// Synergy Spec. for details.
-#define SGI_UART_IRQ	(65)
-#define SGI_HUB_ERROR_IRQ	(182)
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/intr.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/intr.h>
 #endif
 
-#endif /* _ASM_SN_INTR_H */
+#endif /* _ASM_IA64_SN_INTR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/intr_public.h lia64-2.4/include/asm-ia64/sn/intr_public.h
--- linux-2.4.16/include/asm-ia64/sn/intr_public.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/intr_public.h	Mon Nov 19 23:22:54 2001
@@ -4,56 +4,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INTR_PUBLIC_H__
-#define _ASM_SN_INTR_PUBLIC_H__
+#ifndef _ASM_IA64_SN_INTR_PUBLIC_H
+#define _ASM_IA64_SN_INTR_PUBLIC_H
 
 #include <linux/config.h>
 
-/* REMEMBER: If you change these, the whole world needs to be recompiled.
- * It would also require changing the hubspl.s code and SN0/intr.c
- * Currently, the spl code has no support for multiple INTPEND1 masks.
- */
-
-#define	N_INTPEND0_MASKS	1
-#define	N_INTPEND1_MASKS	1
-
-#define INTPEND0_MAXMASK	(N_INTPEND0_MASKS - 1)
-#define INTPEND1_MAXMASK	(N_INTPEND1_MASKS - 1)
-
-#if _LANGUAGE_C
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/arch.h>
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/intr_public.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
 #endif
-#include <asm/sn/arch.h>
-
-struct intr_vecblk_s;	/* defined in asm/sn/intr.h */
-
-/*
- * The following are necessary to create the illusion of a CEL
- * on the IP27 hub.  We'll add more priority levels soon, but for
- * now, any interrupt in a particular band effectively does an spl.
- * These must be in the PDA since they're different for each processor.
- * Users of this structure must hold the vector_lock in the appropriate vector
- * block before modifying the mask arrays.  There's only one vector block
- * for each Hub so a lock in the PDA wouldn't be adequate.
- */
-typedef struct hub_intmasks_s {
-	/*
-	 * The masks are stored with the lowest-priority (most inclusive)
-	 * in the lowest-numbered masks (i.e., 0, 1, 2...).
-	 */
-	/* INT_PEND0: */
-	hubreg_t		intpend0_masks[N_INTPEND0_MASKS]; 
-	/* INT_PEND1: */
-	hubreg_t		intpend1_masks[N_INTPEND1_MASKS];
-	/* INT_PEND0: */
-	struct intr_vecblk_s	*dispatch0;	
-	/* INT_PEND1: */
-	struct intr_vecblk_s	*dispatch1;
-} hub_intmasks_t;
 
-#endif /* _LANGUAGE_C */
-#endif /* _ASM_SN_INTR_PUBLIC_H__ */
+#endif /* _ASM_IA64_SN_INTR_PUBLIC_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/invent.h lia64-2.4/include/asm-ia64/sn/invent.h
--- linux-2.4.16/include/asm-ia64/sn/invent.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/invent.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INVENT_H
-#define _ASM_SN_INVENT_H
+#ifndef _ASM_IA64_SN_INVENT_H
+#define _ASM_IA64_SN_INVENT_H
 
 /*
  * sys/sn/invent.h --  Kernel Hardware Inventory
@@ -743,4 +742,4 @@
 					int);
 extern int device_controller_num_get(	devfs_handle_t);
 #endif /* __KERNEL__ */
-#endif /* _ASM_SN_INVENT_H */
+#endif /* _ASM_IA64_SN_INVENT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/io.h lia64-2.4/include/asm-ia64/sn/io.h
--- linux-2.4.16/include/asm-ia64/sn/io.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/io.h	Mon Nov 19 23:22:54 2001
@@ -1,21 +1,17 @@
-
-/* $Id: io.h,v 1.2 2000/02/02 16:35:57 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 2000 Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.
  */
-#ifndef _ASM_SN_IO_H
-#define _ASM_SN_IO_H
+#ifndef _ASM_IA64_SN_IO_H
+#define _ASM_IA64_SN_IO_H
 
 #include <linux/config.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/addrs.h>
-#endif
+#include <asm/sn/addrs.h>
 
 /* Because we only have PCI I/O ports.  */
 #define IIO_ITTE_BASE	0x400160	/* base of translation table entries */
@@ -51,17 +47,35 @@
 #define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
 
 /*
- * Macro which takes the widget number, and returns the 
+ * Macro which takes the widget number, and returns the
  * IO PRB address of that widget.
- * value _x is expected to be a widget number in the range 
+ * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
 #define	IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
 			(_x) : \
 			(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/bedrock.h>
 #include <asm/sn/sn1/hubio.h>
+#include <asm/sn/sn1/hubio_next.h>
+#include <asm/sn/sn1/hubmd.h>
+#include <asm/sn/sn1/hubmd_next.h>
+#include <asm/sn/sn1/hubpi.h>
+#include <asm/sn/sn1/hubpi_next.h>
+#include <asm/sn/sn1/hublb.h>
+#include <asm/sn/sn1/hublb_next.h>
+#include <asm/sn/sn1/hubni.h>
+#include <asm/sn/sn1/hubni_next.h>
+#include <asm/sn/sn1/hubxb.h>
+#include <asm/sn/sn1/hubxb_next.h>
+#include <asm/sn/sn1/hubstat.h>
+#include <asm/sn/sn1/hubdev.h>
+#include <asm/sn/sn1/synergy.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/shub.h>
+#include <asm/sn/sn2/shubio.h>
 #endif
 
-#endif /* _ASM_SN_IO_H */
+#endif /* _ASM_IA64_SN_IO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/iobus.h lia64-2.4/include/asm-ia64/sn/iobus.h
--- linux-2.4.16/include/asm-ia64/sn/iobus.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/iobus.h	Wed Dec 31 16:00:00 1969
@@ -1,185 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_IOBUS_H
-#define _ASM_SN_IOBUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct eframe_s;
-struct piomap;
-struct dmamap;
-
-
-/* for ilvl_t interrupt level, for use with intr_block_level.  Can't
- * typedef twice without causing warnings, and some users of this header
- * file do not already include driver.h, but expect ilvl_t to be defined,
- * while others include both, leading to the warning ...
- */
-
-#include <asm/types.h>
-#include <asm/sn/driver.h>
-
-
-typedef __psunsigned_t iobush_t;
-
-#if __KERNEL__
-/* adapter handle */
-typedef devfs_handle_t adap_t;
-#endif
-
-
-/* interrupt function */
-typedef void	       *intr_arg_t;
-typedef void		intr_func_f(intr_arg_t);
-typedef intr_func_f    *intr_func_t;
-
-#define	INTR_ARG(n)	((intr_arg_t)(__psunsigned_t)(n))
-
-/* system interrupt resource handle -- returned from intr_alloc */
-typedef struct intr_s *intr_t;
-#define INTR_HANDLE_NONE ((intr_t)0)
-
-/*
- * restore interrupt level value, returned from intr_block_level
- * for use with intr_unblock_level.
- */
-typedef void *rlvl_t;
-
-
-/* 
- * A basic, platform-independent description of I/O requirements for
- * a device. This structure is usually formed by lboot based on information 
- * in configuration files.  It contains information about PIO, DMA, and
- * interrupt requirements for a specific instance of a device.
- *
- * The pio description is currently unused.
- *
- * The dma description describes bandwidth characteristics and bandwidth
- * allocation requirements. (TBD)
- *
- * The Interrupt information describes the priority of interrupt, desired 
- * destination, policy (TBD), whether this is an error interrupt, etc.  
- * For now, interrupts are targeted to specific CPUs.
- */
-
-typedef struct device_desc_s {
-	/* pio description (currently none) */
-
-	/* dma description */
-	/* TBD: allocated badwidth requirements */
-
-	/* interrupt description */
-	devfs_handle_t	intr_target;	/* Hardware locator string */
-	int 		intr_policy;	/* TBD */
-	ilvl_t		intr_swlevel;	/* software level for blocking intr */
-	char		*intr_name;	/* name of interrupt, if any */
-
-	int		flags;
-} *device_desc_t;
-
-/* flag values */
-#define	D_INTR_ISERR	0x1		/* interrupt is for error handling */
-#define D_IS_ASSOC	0x2		/* descriptor is associated with a dev */
-#define D_INTR_NOTHREAD	0x4		/* Interrupt handler isn't threaded. */
-
-#define INTR_SWLEVEL_NOTHREAD_DEFAULT 	0	/* Default
-						 * Interrupt level in case of
-						 * non-threaded interrupt 
-						 * handlers
-						 */
-/* 
- * Drivers use these interfaces to manage device descriptors.
- *
- * To examine defaults:
- *	desc = device_desc_default_get(dev);
- *	device_desc_*_get(desc);
- *
- * To modify defaults:
- *	desc = device_desc_default_get(dev);
- *	device_desc_*_set(desc);
- *
- * To eliminate defaults:
- *	device_desc_default_set(dev, NULL);
- *
- * To override defaults:
- *	desc = device_desc_dup(dev);
- *	device_desc_*_set(desc,...);
- *	use device_desc in calls
- *	device_desc_free(desc);
- *
- * Software must not set or eliminate default device descriptors for a device while
- * concurrently get'ing, dup'ing or using them.  Default device descriptors can be 
- * changed only for a device that is quiescent.  In general, device drivers have no
- * need to permanently change defaults anyway -- they just override defaults, when
- * necessary.
- */
-extern device_desc_t	device_desc_dup(devfs_handle_t dev);
-extern void		device_desc_free(device_desc_t device_desc);
-extern device_desc_t	device_desc_default_get(devfs_handle_t dev);
-extern void		device_desc_default_set(devfs_handle_t dev, device_desc_t device_desc);
-
-extern devfs_handle_t	device_desc_intr_target_get(device_desc_t device_desc);
-extern int		device_desc_intr_policy_get(device_desc_t device_desc);
-extern ilvl_t		device_desc_intr_swlevel_get(device_desc_t device_desc);
-extern char *		device_desc_intr_name_get(device_desc_t device_desc);
-extern int		device_desc_flags_get(device_desc_t device_desc);
-
-extern void		device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target);
-extern void		device_desc_intr_policy_set(device_desc_t device_desc, int policy);
-extern void		device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel);
-extern void		device_desc_intr_name_set(device_desc_t device_desc, char *name);
-extern void		device_desc_flags_set(device_desc_t device_desc, int flags);
-
-
-/* IO state */
-#ifdef COMMENT
-#define IO_STATE_EMPTY			0x01	/* non-existent */
-#define IO_STATE_INITIALIZING		0x02	/* being initialized */
-#define IO_STATE_ATTACHING   		0x04    /* becoming active */
-#define IO_STATE_ACTIVE      		0x08    /* active */
-#define IO_STATE_DETACHING   		0x10    /* becoming inactive */
-#define IO_STATE_INACTIVE    		0x20    /* not in use */
-#define IO_STATE_ERROR			0x40    /* problems */
-#define IO_STATE_BAD_HARDWARE		0x80	/* broken hardware */
-#endif
-
-struct edt;
-
-
-/* return codes */
-#define RC_OK				0	
-#define RC_ERROR			1
-
-/* bus configuration management op code */
-#define IOBUS_CONFIG_ATTACH		0	/* vary on */
-#define IOBUS_CONFIG_DETACH		1	/* vary off */
-#define IOBUS_CONFIG_RECOVER		2	/* clear error then vary on */
-
-/* get low-level PIO handle */
-extern int pio_geth(struct piomap*, int bus, int bus_id, int subtype, 
-	iopaddr_t addr, int size);	
-
-/* get low-level DMA handle */
-extern int dma_geth(struct dmamap*, int bus_type, int bus_id, int dma_type, 
-	int npages, int page_size, int flags);	
-
-#ifdef __cplusplus
-}
-#endif
-
-/*
- * Macros for page number and page offsets, using ps as page size
- */
-#define x_pnum(addr, ps) ((__psunsigned_t)(addr) / (__psunsigned_t)(ps))
-#define x_poff(addr, ps) ((__psunsigned_t)(addr) & ((__psunsigned_t)(ps) - 1))
-
-#endif /* _ASM_SN_IOBUS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ioc3.h lia64-2.4/include/asm-ia64/sn/ioc3.h
--- linux-2.4.16/include/asm-ia64/sn/ioc3.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/ioc3.h	Mon Nov 19 23:22:54 2001
@@ -3,8 +3,8 @@
  * Copyright (C) 1999 Ralf Baechle
  * This file is part of the Linux driver for the SGI IOC3.
  */
-#ifndef IOC3_H
-#define IOC3_H
+#ifndef _ASM_IA64_SN_IOC3_H
+#define _ASM_IA64_SN_IOC3_H
 
 /* SUPERIO uart register map */
 typedef volatile struct ioc3_uartregs {
@@ -668,4 +668,4 @@
 #define IOC3_VENDOR_ID_NUM	0x10A9
 #define IOC3_DEVICE_ID_NUM	0x0003
 
-#endif /* IOC3_H */
+#endif /* _ASM_IA64_SN_IOC3_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ioerror.h lia64-2.4/include/asm-ia64/sn/ioerror.h
--- linux-2.4.16/include/asm-ia64/sn/ioerror.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/ioerror.h	Mon Nov 19 23:22:54 2001
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOERROR_H
-#define _ASM_SN_IOERROR_H
+#ifndef _ASM_IA64_SN_IOERROR_H
+#define _ASM_IA64_SN_IOERROR_H
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 
 /*
  * Macros defining the various Errors to be handled as part of
@@ -162,7 +161,6 @@
 #define	IOERROR_FIELDVALID(e,f)	(((e)->ie_v.iev_b.ievb_ ## f) != 0)
 #define	IOERROR_GETVALUE(e,f)	(ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f))
 
-#if	IP27 || IP35
 /* hub code likes to call the SysAD address "hubaddr" ... */
 #define	ie_hubaddr	ie_sysioaddr
 #define	ievb_hubaddr	ievb_sysioaddr
@@ -178,7 +176,6 @@
     MODE_DEVREENABLE		/* Reenable pass                */
 } ioerror_mode_t;
 
-#endif				/* C || C++ */
 
 typedef int             error_handler_f(void *, int, ioerror_mode_t, ioerror_t *);
 typedef void           *error_handler_arg_t;
@@ -193,4 +190,4 @@
 #define	IOERR_PRINTF(x)
 #endif				/* ERROR_DEBUG */
 
-#endif				/* _ASM_SN_IOERROR_H */
+#endif /* _ASM_IA64_SN_IOERROR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ioerror_handling.h lia64-2.4/include/asm-ia64/sn/ioerror_handling.h
--- linux-2.4.16/include/asm-ia64/sn/ioerror_handling.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/ioerror_handling.h	Mon Nov 19 23:22:54 2001
@@ -1,14 +1,12 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOERROR_HANDLING_H
-#define _ASM_SN_IOERROR_HANDLING_H
+#ifndef _ASM_IA64_SN_IOERROR_HANDLING_H
+#define _ASM_IA64_SN_IOERROR_HANDLING_H
 
 #include <linux/config.h>
 
@@ -264,7 +262,7 @@
 	 * one.								 
 	 */								 
 	if (v_error_skip_env_get(v, error_env) != GRAPH_SUCCESS) {	 
-		error_env = kmem_zalloc(sizeof(label_t), KM_NOSLEEP);	 
+		error_env = snia_kmem_zalloc(sizeof(label_t), KM_NOSLEEP);	 
 		/* Unable to allocate memory for jum buffer. This should 
 		 * be a very rare occurrence.				 
 		 */							 
@@ -302,4 +300,4 @@
 #endif
 
 #endif /* __KERNEL__ */
-#endif /* _ASM_SN_IOERROR_HANDLING_H */
+#endif /* _ASM_IA64_SN_IOERROR_HANDLING_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/iograph.h lia64-2.4/include/asm-ia64/sn/iograph.h
--- linux-2.4.16/include/asm-ia64/sn/iograph.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/iograph.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOGRAPH_H
-#define _ASM_SN_IOGRAPH_H
+#ifndef _ASM_IA64_SN_IOGRAPH_H
+#define _ASM_IA64_SN_IOGRAPH_H
 
 /*
  * During initialization, platform-dependent kernel code establishes some
@@ -68,6 +67,7 @@
 #define EDGE_LBL_HPC			"hpc"
 #define EDGE_LBL_GFX			"gfx"
 #define EDGE_LBL_HUB			"hub"		/* For SN0 */
+#define EDGE_LBL_SYNERGY		"synergy"	/* For SNIA only */
 #define EDGE_LBL_IBUS			"ibus"		/* For EVEREST */
 #define EDGE_LBL_INTERCONNECT		"link"
 #define EDGE_LBL_IO			"io"
@@ -216,4 +216,4 @@
 };
 
 
-#endif /* _ASM_SN_IOGRAPH_H */
+#endif /* _ASM_IA64_SN_IOGRAPH_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/klclock.h lia64-2.4/include/asm-ia64/sn/klclock.h
--- linux-2.4.16/include/asm-ia64/sn/klclock.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/klclock.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,60 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2001 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2001 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_KLCLOCK_H
+#define _ASM_IA64_SN_KLCLOCK_H
+
+#include <asm/sn/ioc3.h>
+
+#define RTC_BASE_ADDR		(unsigned char *)(nvram_base)
+
+/* Defines for the SGS-Thomson M48T35 clock */
+#define RTC_SGS_WRITE_ENABLE    0x80
+#define RTC_SGS_READ_PROTECT    0x40
+#define RTC_SGS_YEAR_ADDR       (RTC_BASE_ADDR + 0x7fffL)
+#define RTC_SGS_MONTH_ADDR      (RTC_BASE_ADDR + 0x7ffeL)
+#define RTC_SGS_DATE_ADDR       (RTC_BASE_ADDR + 0x7ffdL)
+#define RTC_SGS_DAY_ADDR        (RTC_BASE_ADDR + 0x7ffcL)
+#define RTC_SGS_HOUR_ADDR       (RTC_BASE_ADDR + 0x7ffbL)
+#define RTC_SGS_MIN_ADDR        (RTC_BASE_ADDR + 0x7ffaL)
+#define RTC_SGS_SEC_ADDR        (RTC_BASE_ADDR + 0x7ff9L)
+#define RTC_SGS_CONTROL_ADDR    (RTC_BASE_ADDR + 0x7ff8L)
+
+/* Defines for the Dallas DS1386 */
+#define RTC_DAL_UPDATE_ENABLE   0x80
+#define RTC_DAL_UPDATE_DISABLE  0x00
+#define RTC_DAL_YEAR_ADDR       (RTC_BASE_ADDR + 0xaL)
+#define RTC_DAL_MONTH_ADDR      (RTC_BASE_ADDR + 0x9L)
+#define RTC_DAL_DATE_ADDR       (RTC_BASE_ADDR + 0x8L)
+#define RTC_DAL_DAY_ADDR        (RTC_BASE_ADDR + 0x6L)
+#define RTC_DAL_HOUR_ADDR       (RTC_BASE_ADDR + 0x4L)
+#define RTC_DAL_MIN_ADDR        (RTC_BASE_ADDR + 0x2L)
+#define RTC_DAL_SEC_ADDR        (RTC_BASE_ADDR + 0x1L)
+#define RTC_DAL_CONTROL_ADDR    (RTC_BASE_ADDR + 0xbL)
+#define RTC_DAL_USER_ADDR       (RTC_BASE_ADDR + 0xeL)
+
+/* Defines for the Dallas DS1742 */
+#define RTC_DS1742_WRITE_ENABLE    0x80
+#define RTC_DS1742_READ_ENABLE     0x40
+#define RTC_DS1742_UPDATE_DISABLE  0x00
+#define RTC_DS1742_YEAR_ADDR       (RTC_BASE_ADDR + 0x7ffL)
+#define RTC_DS1742_MONTH_ADDR      (RTC_BASE_ADDR + 0x7feL)
+#define RTC_DS1742_DATE_ADDR       (RTC_BASE_ADDR + 0x7fdL)
+#define RTC_DS1742_DAY_ADDR        (RTC_BASE_ADDR + 0x7fcL)
+#define RTC_DS1742_HOUR_ADDR       (RTC_BASE_ADDR + 0x7fbL)
+#define RTC_DS1742_MIN_ADDR        (RTC_BASE_ADDR + 0x7faL)
+#define RTC_DS1742_SEC_ADDR        (RTC_BASE_ADDR + 0x7f9L)
+#define RTC_DS1742_CONTROL_ADDR    (RTC_BASE_ADDR + 0x7f8L)
+#define RTC_DS1742_USER_ADDR       (RTC_BASE_ADDR + 0x0L)
+
+#define BCD_TO_INT(x) (((x>>4) * 10) + (x & 0xf))
+#define INT_TO_BCD(x) (((x / 10)<<4) + (x % 10))
+
+#define YRREF	1970 
+
+#endif /* _ASM_IA64_SN_KLCLOCK_H  */
diff -urN linux-2.4.16/include/asm-ia64/sn/klconfig.h lia64-2.4/include/asm-ia64/sn/klconfig.h
--- linux-2.4.16/include/asm-ia64/sn/klconfig.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/klconfig.h	Mon Nov 19 23:22:54 2001
@@ -6,11 +6,11 @@
  *
  * Derived from IRIX <sys/SN/klconfig.h>.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 1999,2001 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef	_ASM_SN_KLCONFIG_H
-#define	_ASM_SN_KLCONFIG_H
+#ifndef _ASM_IA64_SN_KLCONFIG_H
+#define _ASM_IA64_SN_KLCONFIG_H
 
 #include <linux/config.h>
 
@@ -38,28 +38,22 @@
 #include <asm/sn/types.h>
 #include <asm/sn/slotnum.h>
 #include <asm/sn/router.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/sgi.h>
-#include <asm/sn/sn1/addrs.h>
+#include <asm/sn/addrs.h>
 #include <asm/sn/vector.h>
-#include <asm/sn/agent.h>
-// #include <sys/graph.h>
-// #include <asm/sn/arc/types.h>
 #include <asm/sn/arc/hinv.h>
 #include <asm/sn/xtalk/xbow.h>
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/kldir.h>
 #include <asm/sn/sn_fru.h>
 
-#endif  /* CONFIG_SGI_IP35 ... */
-
 #define KLCFGINFO_MAGIC	0xbeedbabe
 
 typedef s32 klconf_off_t;
 
 #define	MAX_MODULE_ID		255
 #define SIZE_PAD		4096 /* 4k padding for structures */
-#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP) /* MAX_SLOTS_PER_NODE??? */
+#if defined(BRINGUP) /* MAX_SLOTS_PER_NODE??? */
 /* 
  * 1 NODE brick, 3 Router bricks (1 local, 1 meta, 1 repeater),
  * 6 XIO Widgets, 1 Xbow, 1 gfx
@@ -349,7 +343,7 @@
 #define KLCLASS(_x) ((_x) & KLCLASS_MASK)
 
 /*
- * IP27 board types
+ * board types
  */
 
 #define KLTYPE_MASK	0x0f
@@ -357,11 +351,7 @@
 #define KLTYPE_EMPTY	0x00
 
 #define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
-#define KLTYPE_IP27	(KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define KLTYPE_IP35	KLTYPE_IP27
-#define KLTYPE_IP37	KLTYPE_IP35
-#endif
+#define KLTYPE_SNIA	(KLCLASS_CPU | 0x1)
 
 #define KLTYPE_WEIRDIO	(KLCLASS_IO  | 0x0)
 #define KLTYPE_BASEIO	(KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
@@ -963,4 +953,4 @@
 extern nasid_t	get_actual_nasid(lboard_t *brd) ;
 extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
 
-#endif /* _ASM_SN_KLCONFIG_H */
+#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/kldir.h lia64-2.4/include/asm-ia64/sn/kldir.h
--- linux-2.4.16/include/asm-ia64/sn/kldir.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/kldir.h	Mon Nov 19 23:22:54 2001
@@ -1,18 +1,16 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 1999,2001 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_KLDIR_H
-#define _ASM_SN_KLDIR_H
+#ifndef _ASM_IA64_SN_KLDIR_H
+#define _ASM_IA64_SN_KLDIR_H
 
-#include <linux/config.h>
 #include <asm/sn/sgi.h>
 
 /*
@@ -125,16 +123,16 @@
  * 0x0   (0K)              +-----------------------------------------+
  */
 
-#ifdef LANGUAGE_ASSEMBLY
+#ifdef __ASSEMBLY__
 #define KLDIR_OFF_MAGIC			0x00
 #define KLDIR_OFF_OFFSET		0x08
 #define KLDIR_OFF_POINTER		0x10
 #define KLDIR_OFF_SIZE			0x18
 #define KLDIR_OFF_COUNT			0x20
 #define KLDIR_OFF_STRIDE		0x28
-#endif /* LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef struct kldir_ent_s {
 	u64		magic;		/* Indicates validity of entry      */
 	off_t		offset;		/* Offset from start of node space  */
@@ -146,19 +144,220 @@
 	/* NOTE: These 16 bytes are used in the Partition KLDIR
 	   entry to store partition info. Refer to klpart.h for this. */
 } kldir_ent_t;
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 #define KLDIR_ENT_SIZE			0x40
 #define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
 
+
+
 /*
- * The actual offsets of each memory area are machine-dependent
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.  The minimum memory bank
+ * size on IP35 is 64M, which provides a limit on the amount of space
+ * the PROM can assume it has available.
+ *
+ * Most of the addresses below are defined as macros in this file, or
+ * in SN/addrs.h or SN/SN1/addrs.h.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x4000000 (64M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      IO7 TEXT/DATA/BSS/stack            |
+ * 0x3000000 (48M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x2102000 (>33M)        +-----------------------------------------+
+ *                         |      IP35 Topology (PCFG) + misc data   |
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO7 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1C00000 (28M)         +-----------------------------------------+
+ *                         |      IP35 PROM TEXT/DATA/BSS/stack      |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Routing temp. space                |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      Diagnostics temp. space            |
+ * 0x1500000 (21M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1400000 (20M)         +-----------------------------------------+
+ *                         |      IO7 PROM temporary copy            |
+ * 0x1300000 (19M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |      (UNIX DATA starts above 0x1000000) |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x0310000 (3.1M)        +-----------------------------------------+
+ *                         |      SYMMON, loaded just below UNIX     |
+ *                         |      (For UNIX Debug only)              |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x006C000 (432K)        +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x004C000 (304K)        +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x0040000 (256K)        +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP35PROM, IO7PROM and IRIX.
+ *
+ * 0x40000 (256K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      KLCONFIG (64K)                     |
+ *                         |                                         |
+ * 0x30000 (192K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (64K)              |
+ *                         |                                         |
+ * 0x20000 (128K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 3)|
+ * 0x18800 (98K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 3)	     |
+ * 0x18400 (97K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 3)         |
+ * 0x18000 (96K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x13c00 (79K)           +-----------------------------------------+
+ *                         |      GPDA (8k)                          |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 2)|
+ * 0x10800 (66k)	   +-----------------------------------------+
+ *			   |      cache error eframe (CPU 2)	     |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 2)         |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x0b400 (45K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x0b000 (44K)           +-----------------------------------------+
+ *                         |      NMI Eframe areas (4)       	     |
+ * 0x0a000 (40K)           +-----------------------------------------+
+ *                         |      NMI Register save areas (4)        |
+ * 0x09000 (36K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 1)|
+ * 0x08800 (34K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 1)	     |
+ * 0x08400 (33K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 1)         |
+ * 0x08000 (32K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x04000 (16K)           +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x03000 (12K)           +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x02c00 (11K)           +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x02800 (10K)           +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x02400 (9K)            +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x02000 (8K)            +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x01000 (4K)            +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 0)|
+ * 0x00800 (2k)	           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 0)	     |
+ * 0x00400 (1K)            +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 0)         |
+ * 0x00000 (0K)            +-----------------------------------------+
+ */
+
+/*
+ * NOTE:  To change the kernel load address, you must update:
+ *  - the appropriate elspec files in irix/kern/master.d
+ *  - NODEBUGUNIX_ADDR in SN/SN1/addrs.h
+ *  - IP27_FREEMEM_OFFSET below
+ *  - KERNEL_START_OFFSET below (if supporting cells)
  */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/kldir.h>
-#else
-#error "kldir.h is currently defined for IP27 and IP35 platforms only"
-#endif
 
-#endif /* _ASM_SN_KLDIR_H */
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE		0x8000
+
+#if defined (PROM) || defined (SABLE)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP35
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET		0x2400
+#define IP27_LAUNCH_SIZE		0x400
+#define IP27_LAUNCH_COUNT		4
+#define IP27_LAUNCH_STRIDE		0x100 /* could be as small as 0x80 */
+
+#define IP27_KLCONFIG_OFFSET		0x30000
+#define IP27_KLCONFIG_SIZE		0x10000
+#define IP27_KLCONFIG_COUNT		1
+#define IP27_KLCONFIG_STRIDE		0
+
+#define IP27_NMI_OFFSET			0x3000
+#define IP27_NMI_SIZE			0x100
+#define IP27_NMI_COUNT			4
+#define IP27_NMI_STRIDE			0x40
+
+#define IP27_PI_ERROR_OFFSET		0x20000
+#define IP27_PI_ERROR_SIZE		0x10000
+#define IP27_PI_ERROR_COUNT		1
+#define IP27_PI_ERROR_STRIDE		0
+
+#define IP27_SYMMON_STK_OFFSET		0x4c000
+#define IP27_SYMMON_STK_SIZE		0x20000
+#define IP27_SYMMON_STK_COUNT		4
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE		0x8000
+
+#define IP27_FREEMEM_OFFSET		0x40000
+#define IP27_FREEMEM_SIZE		-1
+#define IP27_FREEMEM_COUNT		1
+#define IP27_FREEMEM_STRIDE		0
+
+#endif /* PROM || SABLE*/
+/*
+ * There will be only one of these in a partition so the IO7 must set it up.
+ */
+#define IO6_GDA_OFFSET			0xb000
+#define IO6_GDA_SIZE			0x400
+#define IO6_GDA_COUNT			1
+#define IO6_GDA_STRIDE			0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET		0x9000
+#define IP27_NMI_KREGS_CPU_SIZE		0x400
+/*
+ * save area of kernel nmi regs in eframe format 
+ */
+#define IP27_NMI_EFRAME_OFFSET		0xa000
+#define IP27_NMI_EFRAME_SIZE		0x400
+
+#define GPDA_OFFSET			0x11c00
+
+#endif /* _ASM_IA64_SN_KLDIR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ksys/elsc.h lia64-2.4/include/asm-ia64/sn/ksys/elsc.h
--- linux-2.4.16/include/asm-ia64/sn/ksys/elsc.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/ksys/elsc.h	Mon Nov 19 23:22:54 2001
@@ -4,36 +4,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */
 #ifndef _ASM_SN_KSYS_ELSC_H
 #define _ASM_SN_KSYS_ELSC_H
 
-#include <linux/config.h>
-
-#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/ksys/l1.h>
-#endif
-
-// #include <asm/sn/ksys/i2c.h>
 
-#define ELSC_I2C_ADDR		0x08
-#define ELSC_I2C_HUB0		0x09
-#define ELSC_I2C_HUB1		0x0a
-#define ELSC_I2C_HUB2		0x0b
-#define ELSC_I2C_HUB3		0x0c
-
-#define ELSC_PACKET_MAX		96
 #define ELSC_ACP_MAX		86		/* 84+cr+lf */
 #define ELSC_LINE_MAX		(ELSC_ACP_MAX - 2)
 
-/*
- * ELSC character queue type for I/O
- */
-
-#define ELSC_QSIZE	128		/* Power of 2 is more efficient */
-
 typedef sc_cq_t elsc_cq_t;
 
 /*
@@ -49,14 +30,11 @@
 int	elsc_msg_callback(elsc_t *e,
 			  void (*callback)(void *callback_data, char *msg),
 			  void *callback_data);
-#ifdef LATER
 char   *elsc_errmsg(int code);
 
 int	elsc_nvram_write(elsc_t *e, int addr, char *buf, int len);
 int	elsc_nvram_read(elsc_t *e, int addr, char *buf, int len);
 int	elsc_nvram_magic(elsc_t *e);
-#endif
-
 int	elsc_command(elsc_t *e, int only_if_message);
 int	elsc_parse(elsc_t *e, char *p1, char *p2, char *p3);
 int	elsc_ust_write(elsc_t *e, uchar_t c);
@@ -69,10 +47,8 @@
  */
 
 int	elsc_version(elsc_t *e, char *result);
-#ifdef LATER
 int	elsc_debug_set(elsc_t *e, u_char byte1, u_char byte2);
 int	elsc_debug_get(elsc_t *e, u_char *byte1, u_char *byte2);
-#endif
 int	elsc_module_set(elsc_t *e, int module);
 int	elsc_module_get(elsc_t *e);
 int	elsc_partition_set(elsc_t *e, int partition);
@@ -85,13 +61,10 @@
 int	elsc_cell_get(elsc_t *e);
 int	elsc_bist_set(elsc_t *e, char bist_status);
 char	elsc_bist_get(elsc_t *e);
-int	elsc_lock(elsc_t *e,
-		  int retry_interval_usec,
-		  int timeout_usec, u_char lock_val);
+int	elsc_lock(elsc_t *e, int retry_interval_usec, int timeout_usec, u_char lock_val);
 int	elsc_unlock(elsc_t *e);
 int	elsc_display_char(elsc_t *e, int led, int chr);
 int	elsc_display_digit(elsc_t *e, int led, int num, int l_case);
-#ifdef LATER
 int	elsc_display_mesg(elsc_t *e, char *chr);	/* 8-char input */
 int	elsc_password_set(elsc_t *e, char *password);	/* 4-char input */
 int	elsc_password_get(elsc_t *e, char *password);	/* 4-char output */
@@ -102,7 +75,6 @@
 int	elsc_system_reset(elsc_t *e);
 int	elsc_dip_switches(elsc_t *e);
 int	elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose);
-#endif
 
 int	_elsc_hbt(elsc_t *e, int ival, int rdly);
 
@@ -110,28 +82,7 @@
 #define	elsc_hbt_disable(e)		_elsc_hbt(e, 0, 0)
 #define	elsc_hbt_send(e)		_elsc_hbt(e, 0, 1)
 
-/*
- * Routines for using the ELSC as a UART.  There's a version of each
- * routine that takes a pointer to an elsc_t, and another version that
- * gets the pointer by calling a user-supplied global routine "get_elsc".
- * The latter version is useful when the elsc is employed for stdio.
- */
-
-#define ELSCUART_FLASH		0x3c			/* LED pattern */
-
 elsc_t	       *get_elsc(void);
-
-int	elscuart_probe(void);
-void	elscuart_init(void *);
-int	elscuart_poll(void);
-int	elscuart_readc(void);
-int	elscuart_getc(void);
-int	elscuart_putc(int);
-int	elscuart_puts(char *);
-char   *elscuart_gets(char *, int);
-int	elscuart_flush(void);
-
-
 
 /*
  * Error codes
diff -urN linux-2.4.16/include/asm-ia64/sn/ksys/i2c.h lia64-2.4/include/asm-ia64/sn/ksys/i2c.h
--- linux-2.4.16/include/asm-ia64/sn/ksys/i2c.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/ksys/i2c.h	Wed Dec 31 16:00:00 1969
@@ -1,77 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_KSYS_I2C_H
-#define _ASM_SN_KSYS_I2C_H
-
-#if _STANDALONE
-# include "rtc.h"
-#else
-# define rtc_time()	(GET_LOCAL_RTC * NSEC_PER_CYCLE / 1000)
-# define rtc_sleep	us_delay
-# define rtc_time_t	uint64_t
-#endif
-
-typedef u_char			i2c_addr_t;	/* 7-bit address            */
-
-int		i2c_init(nasid_t);
-
-int		i2c_probe(nasid_t nasid, rtc_time_t timeout);
-
-int		i2c_arb(nasid_t, rtc_time_t timeout, rtc_time_t *token_start);
-
-int		i2c_master_xmit(nasid_t,
-				i2c_addr_t addr,
-				u_char *buf,
-				int len_max,
-				int *len_ptr,
-				rtc_time_t timeout,
-				int only_if_message);
-
-int		i2c_master_recv(nasid_t,
-				i2c_addr_t addr,
-				u_char *buf,
-				int len_max,
-				int *len_ptr,
-				int emblen,
-				rtc_time_t timeout,
-				int only_if_message);
-
-int		i2c_master_xmit_recv(nasid_t,
-				     i2c_addr_t addr,
-				     u_char *xbuf,
-				     int xlen_max,
-				     int *xlen_ptr,
-				     u_char *rbuf,
-				     int rlen_max,
-				     int *rlen_ptr,
-				     int emblen,
-				     rtc_time_t timeout,
-				     int only_if_message);
-
-char	       *i2c_errmsg(int code);
-
-/*
- * Error codes
- */
-
-#define I2C_ERROR_NONE		 0
-#define I2C_ERROR_INIT		-1	/* Initialization error             */
-#define I2C_ERROR_STATE		-2	/* Unexpected chip state	    */
-#define I2C_ERROR_NAK		-3	/* Addressed slave not responding   */
-#define I2C_ERROR_TO_ARB	-4	/* Timeout waiting for sysctlr arb  */
-#define I2C_ERROR_TO_BUSY	-5	/* Timeout waiting for busy bus     */
-#define I2C_ERROR_TO_SENDA	-6	/* Timeout sending address byte     */
-#define I2C_ERROR_TO_SENDD	-7	/* Timeout sending data byte        */
-#define I2C_ERROR_TO_RECVA	-8	/* Timeout receiving address byte   */
-#define I2C_ERROR_TO_RECVD	-9	/* Timeout receiving data byte      */
-#define I2C_ERROR_NO_MESSAGE	-10	/* No message was waiting	    */
-#define I2C_ERROR_NO_ELSC	-11	/* ELSC is disabled for access 	    */ 	
-
-#endif /* _ASM_SN_KSYS_I2C_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/ksys/l1.h lia64-2.4/include/asm-ia64/sn/ksys/l1.h
--- linux-2.4.16/include/asm-ia64/sn/ksys/l1.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/ksys/l1.h	Mon Nov 19 23:22:54 2001
@@ -4,8 +4,8 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */
 
 #ifndef _ASM_SN_KSYS_L1_H
@@ -13,7 +13,6 @@
 
 #include <asm/sn/vector.h>
 #include <asm/sn/addrs.h>
-#include <asm/sn/sn1/bedrock.h>
 
 #define BRL1_QSIZE	128	/* power of 2 is more efficient */
 #define BRL1_BUFSZ	264	/* needs to be large enough
@@ -39,7 +38,7 @@
  * This value can't be confused with a network vector because the least-
  * significant nibble of a network vector cannot be greater than 8.
  */
-#define BRL1_LOCALUART	((net_vec_t)0xf)
+#define BRL1_LOCALHUB_UART	((net_vec_t)0xf)
 
 /* L1<->Bedrock reserved subchannels */
 
@@ -71,7 +70,14 @@
 
 
 struct l1sc_s;     
-typedef void (*brl1_notif_t)(struct l1sc_s *, int);
+/* Saved off interrupt frame */
+typedef struct brl1_intr_frame {
+	int bf_irq;		/* irq received */
+	void *bf_dev_id;	/* device information */
+	struct pt_regs *bf_regs; /* register frame */
+} brl1_intr_frame_t;
+
+typedef void (*brl1_notif_t)(int, void *, struct pt_regs *, struct l1sc_s *, int);
 typedef int  (*brl1_uartf_t)(struct l1sc_s *);
 
 /* structure for controlling a subchannel */
@@ -90,6 +96,7 @@
 				 * continue */
     brl1_notif_t rx_notify;	/* notify higher layer that a packet has been
 				 * received */
+    brl1_intr_frame_t irq_frame; /* saved off irq information */
 } brl1_sch_t;
 
 /* br<->l1 protocol states */
@@ -101,7 +108,7 @@
 #define BRL1_RESET	7
 
 
-#ifndef _LANGUAGE_ASSEMBLY
+#ifndef __ASSEMBLY__
 
 /*
  * l1sc_t structure-- tracks protocol state, open subchannels, etc.
@@ -118,6 +125,8 @@
     brl1_uartf_t putc_f;	/* pointer to UART putc function */
     brl1_uartf_t getc_f;	/* pointer to UART getc function */
 
+    spinlock_t   send_lock;     /* arbitrates send synchronization */
+    spinlock_t   recv_lock;     /* arbitrates uart receive access */
     spinlock_t	 subch_lock;	/* arbitrates subchannel allocation */
     cpuid_t	 intr_cpu;	/* cpu that receives L1 interrupts */
 
@@ -327,15 +336,6 @@
 void	sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart );
 void	sc_intr_enable( l1sc_t *sc );
 
-int	_elscuart_putc( l1sc_t *sc, int c );
-int	_elscuart_getc( l1sc_t *sc );
-int	_elscuart_poll( l1sc_t *sc );
-int	_elscuart_readc( l1sc_t *sc );
-int	_elscuart_flush( l1sc_t *sc );
-int	_elscuart_probe( l1sc_t *sc );
-void	_elscuart_init( l1sc_t *sc );
-void	elscuart_syscon_listen( l1sc_t *sc );
-
 int	elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay);
 int	elsc_rack_bay_type_get(l1sc_t *e, uint *rack, 
 			       uint *bay, uint *brick_type);
@@ -357,5 +357,5 @@
 int	iobrick_sc_version( l1sc_t *sc, char *result );
 
 
-#endif /* !_LANGUAGE_ASSEMBLY */
+#endif /* !__ASSEMBLY__ */
 #endif /* _ASM_SN_KSYS_L1_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/labelcl.h lia64-2.4/include/asm-ia64/sn/labelcl.h
--- linux-2.4.16/include/asm-ia64/sn/labelcl.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/labelcl.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_LABELCL_H
-#define _ASM_SN_LABELCL_H
+#ifndef _ASM_IA64_SN_LABELCL_H
+#define _ASM_IA64_SN_LABELCL_H
 
 #define LABELCL_MAGIC 0x4857434c	/* 'HWLC' */
 #define LABEL_LENGTH_MAX 256		/* Includes NULL char */
@@ -90,4 +89,4 @@
 extern int labelcl_info_get_IDX(struct devfs_entry *, int, arbitrary_info_t *);
 extern struct devfs_entry *device_info_connectpt_get(struct devfs_entry *);
 
-#endif /* _ASM_SN_LABELCL_H */
+#endif /* _ASM_IA64_SN_LABELCL_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/leds.h lia64-2.4/include/asm-ia64/sn/leds.h
--- linux-2.4.16/include/asm-ia64/sn/leds.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/leds.h	Mon Nov 26 18:07:23 2001
@@ -0,0 +1,42 @@
+#ifndef _ASM_IA64_SN_LEDS_H
+#define _ASM_IA64_SN_LEDS_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/smp.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pda.h>
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define LED0		0xc0000b00100000c0LL	/* ZZZ fixme */
+#define LED_CPU_SHIFT	3
+#else
+#include <asm/sn/sn2/shub.h>
+#define LED0		(LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
+#define LED_CPU_SHIFT	16
+#endif
+
+#define LED_CPU_HEARTBEAT	0x01
+#define LED_CPU_ACTIVITY	0x02
+#define LED_MASK_AUTOTEST	0xfe
+
+/*
+ * Basic macros for flashing the LEDS on an SGI, SN1.
+ */
+
+static __inline__ void
+set_led_bits(u8 value, u8 mask)
+{
+	pda.led_state = (pda.led_state & ~mask) | (value & mask);
+	*pda.led_address = (long) pda.led_state;
+}
+
+#endif /* _ASM_IA64_SN_LEDS_H */
+
diff -urN linux-2.4.16/include/asm-ia64/sn/mca.h lia64-2.4/include/asm-ia64/sn/mca.h
--- linux-2.4.16/include/asm-ia64/sn/mca.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/mca.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,98 @@
+/*
+ * File:	mca.h
+ * Purpose:	Machine check handling specific to the SN platform defines
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) Alan Mayer (ajm@sgi.com)
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN
+
+typedef u64 __uint64_t;
+
+typedef struct {
+	__uint64_t sh_event_occurred;
+	__uint64_t sh_first_error;
+	__uint64_t sh_event_overflow;
+	__uint64_t sh_pi_first_error;
+	__uint64_t sh_pi_error_summary;
+	__uint64_t sh_pi_error_overflow;
+	__uint64_t sh_pi_error_detail_1;
+	__uint64_t sh_pi_error_detail_2;
+	__uint64_t sh_pi_hw_time_stamp;
+	__uint64_t sh_pi_uncorrected_detail_1;
+	__uint64_t sh_pi_uncorrected_detail_2;
+	__uint64_t sh_pi_uncorrected_detail_3;
+	__uint64_t sh_pi_uncorrected_detail_4;
+	__uint64_t sh_pi_uncor_time_stamp;
+	__uint64_t sh_pi_corrected_detail_1;
+	__uint64_t sh_pi_corrected_detail_2;
+	__uint64_t sh_pi_corrected_detail_3;
+	__uint64_t sh_pi_corrected_detail_4;
+	__uint64_t sh_pi_cor_time_stamp;
+	__uint64_t sh_mem_error_summary;
+	__uint64_t sh_mem_error_overflow;
+	__uint64_t sh_misc_err_hdr_lower;
+	__uint64_t sh_misc_err_hdr_upper;
+	__uint64_t sh_dir_uc_err_hdr_lower;
+	__uint64_t sh_dir_uc_err_hdr_upper;
+	__uint64_t sh_dir_cor_err_hdr_lower;
+	__uint64_t sh_dir_cor_err_hdr_upper;
+	__uint64_t sh_mem_error_mask;
+	__uint64_t sh_md_uncor_time_stamp;
+	__uint64_t sh_md_cor_time_stamp;
+	__uint64_t sh_md_hw_time_stamp;
+	__uint64_t sh_xn_error_summary;
+	__uint64_t sh_xn_first_error;
+	__uint64_t sh_xn_error_overflow;
+	__uint64_t sh_xniilb_error_summary;
+	__uint64_t sh_xniilb_first_error;
+	__uint64_t sh_xniilb_error_overflow;
+	__uint64_t sh_xniilb_error_detail_1;
+	__uint64_t sh_xniilb_error_detail_2;
+	__uint64_t sh_xniilb_error_detail_3;
+	__uint64_t sh_xnpi_error_summary;
+	__uint64_t sh_xnpi_first_error;
+	__uint64_t sh_xnpi_error_overflow;
+	__uint64_t sh_xnpi_error_detail_1;
+	__uint64_t sh_xnmd_error_summary;
+	__uint64_t sh_xnmd_first_error;
+	__uint64_t sh_xnmd_error_overflow;
+	__uint64_t sh_xnmd_ecc_err_report;
+	__uint64_t sh_xnmd_error_detail_1;
+	__uint64_t sh_lb_error_summary;
+	__uint64_t sh_lb_first_error;
+	__uint64_t sh_lb_error_overflow;
+	__uint64_t sh_lb_error_detail_1;
+	__uint64_t sh_lb_error_detail_2;
+	__uint64_t sh_lb_error_detail_3;
+	__uint64_t sh_lb_error_detail_4;
+	__uint64_t sh_lb_error_detail_5;
+} sal_log_shub_state_t;
+
+typedef struct {
+sal_log_section_hdr_t header;
+	struct
+	{
+		__uint64_t    err_status      : 1,
+		guid            : 1,
+		oem_data        : 1,
+		reserved        : 61;
+	} valid;
+	__uint64_t             err_status;
+	efi_guid_t      guid;
+	__uint64_t shub_nic;
+	sal_log_shub_state_t    shub_state;
+} sal_log_plat_info_t;
+
+
+extern void sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc);
+
+#ifdef platform_plat_specific_err_print
+#undef platform_plat_specific_err_print
+#endif
+#define platform_plat_specific_err_print sal_log_plat_print
+
+#endif /* CONFIG_IA64_SGI_SN */
diff -urN linux-2.4.16/include/asm-ia64/sn/mem_refcnt.h lia64-2.4/include/asm-ia64/sn/mem_refcnt.h
--- linux-2.4.16/include/asm-ia64/sn/mem_refcnt.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/mem_refcnt.h	Wed Dec 31 16:00:00 1969
@@ -1,26 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_MEM_REFCNT_H
-#define _ASM_SN_MEM_REFCNT_H
-
-extern int mem_refcnt_attach(devfs_handle_t hub);
-extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp);
-extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp);
-extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot);
-extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt);
-extern int mem_refcnt_ioctl(devfs_handle_t dev,
-                 int cmd,
-                 void *arg,
-                 int mode,
-                 cred_t *cred_p,
-                 int *rvalp);
-        
-
-#endif /* _ASM_SN_MEM_REFCNT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/mmzone.h lia64-2.4/include/asm-ia64/sn/mmzone.h
--- linux-2.4.16/include/asm-ia64/sn/mmzone.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/mmzone.h	Wed Dec 31 16:00:00 1969
@@ -1,113 +0,0 @@
-/*
- * Written by Kanoj Sarcar (kanoj@sgi.com) Jan 2000
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-#ifndef _LINUX_ASM_SN_MMZONE_H
-#define _LINUX_ASM_SN_MMZONE_H
-
-#include <linux/config.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/sn/sn_cpuid.h>
-
-/*
- * Memory is conceptually divided into chunks. A chunk is either
- * completely present, or else the kernel assumes it is completely
- * absent. Each node consists of a number of contiguous chunks.
- */
-
-#define CHUNKMASK       	(~(CHUNKSZ - 1))
-#define CHUNKNUM(vaddr)        	(__pa(vaddr) >> CHUNKSHIFT)
-#define PCHUNKNUM(paddr)        ((paddr) >> CHUNKSHIFT)
-
-#define MAXCHUNKS      		(MAXNODES * MAX_CHUNKS_PER_NODE)
-
-extern int chunktonid[];
-#define CHUNKTONID(cnum)       (chunktonid[cnum])
-
-typedef struct plat_pglist_data {
-       pg_data_t       gendata;		/* try to keep this first. */
-       unsigned long   virtstart;
-       unsigned long   size;
-} plat_pg_data_t;
-
-extern plat_pg_data_t plat_node_data[];
-
-extern int numa_debug(void);
-
-/*
- * The foll two will move into linux/mmzone.h RSN.
- */
-#define NODE_START(n)  plat_node_data[(n)].virtstart
-#define NODE_SIZE(n)   plat_node_data[(n)].size
-
-#define KVADDR_TO_NID(kaddr) \
-       ((CHUNKTONID(CHUNKNUM((kaddr))) != -1) ? (CHUNKTONID(CHUNKNUM((kaddr)))) : \
-       (printk("DISCONTIGBUG: %s line %d addr 0x%lx", __FILE__, __LINE__, \
-       (unsigned long)(kaddr)), numa_debug()))
-#if 0
-#define KVADDR_TO_NID(kaddr) CHUNKTONID(CHUNKNUM((kaddr)))
-#endif
-
-/* These 2 macros should never be used if KVADDR_TO_NID(kaddr) is -1 */
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-                       NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-
-/*
- * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory
- * and returns the kaddr corresponding to first physical page in the
- * node's mem_map.
- */
-#define LOCAL_BASE_ADDR(kaddr) NODE_START(KVADDR_TO_NID(kaddr))
-
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Return a pointer to the node data for node n.
- * Assume that n is the compact node id.
- */
-#define NODE_DATA(n)   (&((plat_node_data + (n))->gendata))
-
-/*
- * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
- */
-#define NODE_MEM_MAP(nid)      (NODE_DATA((nid))->node_mem_map)
-
-/* This macro should never be used if KVADDR_TO_NID(kaddr) is -1 */
-#define LOCAL_MAP_NR(kvaddr) \
-        (((unsigned long)(kvaddr)-LOCAL_BASE_ADDR((kvaddr))) >> PAGE_SHIFT)
-#define MAP_NR_SN1(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
-                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
-                sizeof(mem_map_t)))
-#if 0
-#define MAP_NR_VALID(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
-                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
-                sizeof(mem_map_t)))
-#define MAP_NR_SN1(kaddr)	((KVADDR_TO_NID(kaddr) == -1) ? (max_mapnr + 1) :\
-				MAP_NR_VALID(kaddr))
-#endif
-
-/* FIXME */
-#define sn1_pte_pagenr(x)		MAP_NR_SN1(PAGE_OFFSET + (unsigned long)((pte_val(x)&_PFN_MASK) & PAGE_MASK))
-#define pte_page(pte)			(mem_map + sn1_pte_pagenr(pte))
-/* FIXME */
-
-#define kern_addr_valid(addr)   ((KVADDR_TO_NID((unsigned long)addr) >= \
-        numnodes) ? 0 : (test_bit(LOCAL_MAP_NR((addr)), \
-        NODE_DATA(KVADDR_TO_NID((unsigned long)addr))->valid_addr_bitmap)))
-
-#define virt_to_page(kaddr)	(mem_map + MAP_NR_SN1(kaddr))
-
-#else /* CONFIG_DISCONTIGMEM */
-
-#define MAP_NR_SN1(addr)	(((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#define numa_node_id()		cpuid_to_cnodeid(smp_processor_id())
-
-#endif /* !_LINUX_ASM_SN_MMZONE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/mmzone_default.h lia64-2.4/include/asm-ia64/sn/mmzone_default.h
--- linux-2.4.16/include/asm-ia64/sn/mmzone_default.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/mmzone_default.h	Wed Dec 31 16:00:00 1969
@@ -1,15 +0,0 @@
-/*
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-
-#define MAXNODES                16
-#define MAXNASIDS               16
-
-#define CHUNKSZ                (8*1024*1024)
-#define CHUNKSHIFT              23      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
-
-#define CNODEID_TO_NASID(n)	n
-#define NASID_TO_CNODEID(n)     n
-
-#define MAX_CHUNKS_PER_NODE     8
-
diff -urN linux-2.4.16/include/asm-ia64/sn/mmzone_sn1.h lia64-2.4/include/asm-ia64/sn/mmzone_sn1.h
--- linux-2.4.16/include/asm-ia64/sn/mmzone_sn1.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/mmzone_sn1.h	Wed Dec 31 16:00:00 1969
@@ -1,105 +0,0 @@
-#ifndef _ASM_IA64_MMZONE_SN1_H
-#define _ASM_IA64_MMZONE_SN1_H
-
-#include <linux/config.h>
-
-/*
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-/* Maximum configuration supported by SNIA hardware. There are other
- * restrictions that may limit us to a smaller max configuration.
- */
-#define MAXNODES                128
-#define MAXNASIDS		128
-
-#define CHUNKSZ                (64*1024*1024)
-#define CHUNKSHIFT              26      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
-
-extern int 	cnodeid_map[] ;
-extern int	nasid_map[] ;
-
-#define CNODEID_TO_NASID(n)	(cnodeid_map[(n)])
-#define NASID_TO_CNODEID(n)     (nasid_map[(n)])
-
-#define MAX_CHUNKS_PER_NODE     128
-
-
-/*
- * These are a bunch of sn1 hw specific defines. For now, keep it 
- * in this file. If it gets too diverse we may want to create a 
- * mmhwdefs_sn1.h
- */
-
-/*
- * Structure of the mem config of the node as a SN1 MI reg
- * Medusa supports this reg config.
- */
-
-typedef struct node_memmap_s
-{
-        unsigned int    b0      :1,     /* 0 bank 0 present */
-                        b1      :1,     /* 1 bank 1 present */
-                        r01     :2,     /* 2-3 reserved */
-                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
-                        b2      :1,     /* 8 bank 2 present */
-                        b3      :1,     /* 9 bank 3 present */
-                        r23     :2,     /* 10-11 reserved */
-                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
-                        b4      :1,     /* 16 bank 4 present */
-                        b5      :1,     /* 17 bank 5 present */
-                        r45     :2,     /* 18-19 reserved */
-                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
-                        b6      :1,     /* 24 bank 6 present */
-                        b7      :1,     /* 25 bank 7 present */
-                        r67     :2,     /* 26-27 reserved */
-                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
-} node_memmap_t ;
-
-#define GBSHIFT                 30
-#define MBSHIFT                 20
-
-/*
- * SN1 Arch defined values
- */
-#define SN1_MAX_BANK_PER_NODE   8
-#define SN1_BANK_PER_NODE_SHIFT 3       /* derived from SN1_MAX_BANK_PER_NODE */
-#define SN1_NODE_ADDR_SHIFT     (GBSHIFT+3)             /* 8GB */
-#define SN1_BANK_ADDR_SHIFT     (SN1_NODE_ADDR_SHIFT-SN1_BANK_PER_NODE_SHIFT)
-
-#define SN1_BANK_SIZE_SHIFT     (MBSHIFT+6)     /* 64 MB */
-#define SN1_MIN_BANK_SIZE_SHIFT SN1_BANK_SIZE_SHIFT
-
-/*
- * BankSize nibble to bank size mapping
- *
- *      1 - 64 MB
- *      2 - 128 MB
- *      3 - 256 MB
- *      4 - 512 MB
- *      5 - 1024 MB (1GB)
- */
-
-/* fixme - this macro breaks for bsize 6-8 and 0 */
-
-#ifdef CONFIG_IA64_SGI_SN1_SIM
-/* Support the medusa hack for 8M/16M/32M nodes */
-#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
-					 (1<<((bsize-9)+MBSHIFT)))
-#else
-#define BankSizeBytes(bsize)            (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT))
-#endif
-
-#define BankSizeToEFIPages(bsize)       ((BankSizeBytes(bsize)) >> 12)
-
-#define GetPhysAddr(n,b)                (((u64)n<<SN1_NODE_ADDR_SHIFT) | \
-                                                ((u64)b<<SN1_BANK_ADDR_SHIFT))
-
-#define GetNasId(paddr)			((u64)(paddr) >> SN1_NODE_ADDR_SHIFT)
-
-#define GetBankId(paddr)						\
-				(((u64)(paddr) >> SN1_BANK_ADDR_SHIFT) & 7)
-
-#define SN1_MAX_BANK_SIZE		((u64)BankSizeBytes(5))
-#define SN1_BANK_SIZE_MASK		(~(SN1_MAX_BANK_SIZE-1))
-
-#endif /* _ASM_IA64_MMZONE_SN1_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/mmzone_temp.h lia64-2.4/include/asm-ia64/sn/mmzone_temp.h
--- linux-2.4.16/include/asm-ia64/sn/mmzone_temp.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/mmzone_temp.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,276 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_MMZONE_TEMP_H
+#define _ASM_IA64_SN_MMZONE_TEMP_H
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/mmzone_sn1.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/mmzone_sn2.h>
+#elif defined(CONFIG_IA64_DIG)
+#include <asm/mmzone_dig_numa.h>
+#else
+#error "Unknown architecture"
+#endif
+
+
+/*
+ * General Concepts:
+ *
+ *	- Nodes are numbered several ways:
+ *
+ *		compact node numbers - compact node numbers are a dense numbering of 
+ *			all the nodes in the system. An N node system will have compact
+ *			nodes numbered 0 .. N-1. There is no significance to the node
+ *			numbers. The compact node number assigned to a specific physical
+ *			node may vary from boot to boot. The boot node is not necessarily
+ *			node 0.
+ *
+ *		physical node numbers - Physical node numbers may not be dense
+ *			nor do they necessarily start with 0. The exact significance of 
+ *			a physical node number is platform specific.
+ *
+ *		proximity domain numbers - these numbers are assigned by ACPI. 
+ *			Each platform must provide a platform specific function
+ *			for mapping proximity node numbers to physical node numbers.
+ *
+ *	  Most of the code in the kernel uses compact node numbers to identify nodes.
+ *
+ *
+ *	- Memory is conceptually divided into chunks. A chunk is either
+ *	  completely present, or else the kernel assumes it is completely
+ *	  absent. Each node consists of a number of possibly discontiguous chunks.
+ * 
+ *	- A contiguous group of memory chunks that reside on the same node
+ *	  are referred to as a clump. Note that a clump may be partially present.
+ *	  (Note, on some hardware implementations, a clump is the same as a memory
+ *	  bank or a DIMM).
+ *
+ *      - a node consists of multiple clumps of memory. From a NUMA perspective,
+ *        accesses to all clumps on the node have the same latency. Except for zone issues,
+ *        the clumps are treated as equivalent for allocation/performance purposes.
+ *
+ *      - each node has a single contiguous mem_map array. The array contains page struct
+ *        entries for every page on the node. There are no "holes" in the mem_map array.
+ *	  The node directory (see below) has pointers to the start of the mem_map entries
+ *	  for each clump on the node.
+ *
+ *      - associated with each node is a pg_data_t structure. This structure contains the
+ *	  information used by the linux memory allocator for managing the memory on the
+ *	  node. The pg_data_t structure for a node is located on the node.
+ *
+ *	- to minimize offnode memory references, a "node directory" is maintained on each
+ *	  node. This directory replicates frequently used read-only data structures that
+ *	  are used in macro evaluation. Examples include the addresses of the
+ *	  pernode pg_data structures for each node.
+ *
+ *      - the MAP_NR function has been modified to be "clump aware" & uses the clump_mem_map_base
+ *        array in the node directory for generating MAP_NR numbers.
+ * 
+ *	- the node directory contains array of pointers to the mem_map entries for each clump
+ *	  of memory. The array is indexed by a platform specific function.
+ *
+ *	- each cpu has a pointer the node directory contained in it's cpu_data structure.
+ *
+ *	- each platform is responsible for defining the following constants & functions:
+ *
+ *		PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) - Calculate a "goal" value to be passed 
+ *			to __alloc_bootmem_node for allocating structures on nodes so that 
+ *			they dont alias to the same line in the cache as the previous 
+ *			allocated structure. You can return 0 if your platform doesnt have
+ *			this problem.
+ *				(Note: need better solution but works for now ZZZ).
+ *			
+ *		PLAT_CHUNKNUM(kaddr) - takes a kaddr & returns its chunk number
+ *
+ *		PLAT_CLUMP_MEM_MAP_INDEX(kaddr) - Given a kaddr, find the index into the 
+ *			clump_mem_map_base array of the page struct entry for the first page 
+ *			of the clump.
+ *
+ *		PLAT_CLUMP_OFFSET(kaddr) - find the byte offset of a kaddr within the clump that
+ *			contains it.
+ *
+ *		PLAT_CLUMPSIZE - defines the size in bytes of the smallest clump supported on the platform.
+ *
+ *		PLAT_CLUMPS_PER_NODE - maximum number of clumps per node
+ *
+ *		PLAT_MAXCLUMPS - maximum number of clumps on all node combined
+ *
+ *		PLAT_MAX_COMPACT_NODES - maximum number of nodes in a system. (do not confuse this
+ *			with the maximum node number. Nodes can be sparsely numbered).
+ *
+ *		PLAT_MAX_NODE_NUMBER - maximum physical node number plus 1
+ *
+ *		PLAT_MAX_PHYS_MEMORY - maximum physical memory address
+ *
+ *		PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm) - convert a proximity_domain number (from ACPI)
+ *			into a physical node number
+ *
+ *		PLAT_VALID_MEM_KADDR(kaddr) - tests a kaddr to see if it potentially represents a
+ *			valid physical memory address.  Return 1 if potentially valid, 0 otherwise.
+ *			(This function generally tests to see if any invalid bits are set in
+ *			the address).
+ *
+ *
+ *	- each platform is responsible for defining the following typedefs::
+ *	
+ *		cnodeid_t	- compact node number
+ *	
+ */
+
+
+#if 0	/* need new discontig.c for this */
+extern struct page 	*invalid_mem_map;	/* value returned by virt_to_page for bad addresses */
+#endif
+
+
+/*
+ * Node Directory. 
+ * 
+ * The  node directory is a read-only (after boot) structure
+ * containing pointers to VM structures located on all nodes. The directory is
+ * replicated on each node in order to reduce off-node references.
+ */
+
+typedef struct ia64_node_directory_s {
+        pg_data_t	*pg_data_ptrs[PLAT_MAX_COMPACT_NODES];
+	cnodeid_t	physical_node_map[PLAT_MAX_NODE_NUMBER];
+	struct page	*clump_mem_map_base[PLAT_MAXCLUMPS];
+} ia64_node_directory_t;
+
+
+#define NODEDIR			((ia64_node_directory_t*)(local_cpu_data->node_directory))
+
+
+
+/*
+ * Given a compact node id, return a pointer to the pg_data_t for the node.
+ * The following 2 macros are similar. 
+ *
+ *	NODE_DATA 	- should be used in all code not related to system
+ *			  initialization. It uses pernode data structures to minimize
+ *			  offnode memory references. However, these structure are not 
+ *			  present during boot. This macro can be used once cpu_init
+ *			  completes.
+ *
+ *	BOOT_NODE_DATA	- should be used during system initialization 
+ *			  prior to freeing __initdata. It does not depend on the percpu
+ *			  area being present.
+ *
+ */
+#define NODE_DATA(nid)			(NODEDIR->pg_data_ptrs[nid])
+#define BOOT_NODE_DATA(nid)		boot_get_pg_data_ptr((long)(nid))
+extern pg_data_t* __init boot_get_pg_data_ptr(long);
+
+
+
+/*
+ * Chunk related macros
+ *	Note: It is not clear if VALIDCHUNK is really needed. It is currently used
+ *		ONLY in kern_address_valid. The non-NUMA variant of this always
+ *		returns 1.
+ *	ZZZ Fixme????
+ */
+#define VALIDCHUNK(cnum)		1
+
+
+
+/*
+ * Given a kaddr, find the base mem_map address for the start of the mem_map
+ * entries for the clump containing the kaddr.
+ */
+#define CLUMP_MEM_MAP_BASE(kaddr)	NODEDIR->clump_mem_map_base[PLAT_CLUMP_MEM_MAP_INDEX(kaddr)]
+
+
+
+/*
+ * Given a kaddr, this macro return the relative map number 
+ * within the clump.
+ */
+#define CLUMP_MAP_NR(kaddr) 		(PLAT_CLUMP_OFFSET(kaddr) >> PAGE_SHIFT)
+
+
+
+/*
+ * Finally.... This is the MAP_NR function for the platform.
+ */
+#define MAP_NR_DISCONTIG(kaddr)		({long _kmns=(long)(kaddr);				\
+						CLUMP_MAP_NR(_kmns) +				\
+						CLUMP_MEM_MAP_BASE(_kmns) - mem_map;})
+
+/*
+ * Given a pte, this macro returns a pointer to the page struct for the pte.
+ */
+#define pte_page(pte)			virt_to_page(PAGE_OFFSET | (pte_val(pte)&_PFN_MASK))
+
+
+
+/*
+ * Determine if a kaddr is a valid memory address of memory that
+ * actually exists. 
+ *
+ * The check consists of 2 parts:
+ *	- verify that the address is a region 7 address & does not 
+ *	  contain any bits that preclude it from being a valid platform
+ *	  memory address
+ *	- verify that the chunk actually exists.
+ *
+ * Note that IO addresses are NOT considered valid addresses.
+ *
+ * Note, many platforms can simply check if kaddr exceeds a specific size.  
+ *	(However, this wont work on SGI platforms since IO space is embedded 
+ * 	within the range of valid memory addresses & nodes have holes in the 
+ *	address range between clumps). 
+ */
+#define kern_addr_valid(kaddr)		({long _kav=(long)(kaddr);						\
+					PLAT_VALID_MEM_KADDR(_kav) && VALIDCHUNK(PLAT_CHUNKNUM(_kav));})
+
+
+/*
+ * Given a kaddr, return a pointer to the page struct for the page.
+ * If the kaddr does not represent RAM memory that potentially exists, return
+ * a pointer the page struct for max_mapnr. IO addresses will
+ * return the page for max_nr. Addresses in unpopulated RAM banks may
+ * return undefined results OR may panic the system.
+ *
+ */
+#if 0	/* need new discontig.c for invalid_mem_map */
+#define virt_to_page(kaddr)		({long _kvtp=(long)(kaddr);					\
+					(PLAT_VALID_MEM_KADDR(_kvtp))					\
+						? CLUMP_MEM_MAP_BASE(_kvtp) + CLUMP_MAP_NR(_kvtp)	\
+						: invalid_mem_map;})
+#else
+#define virt_to_page(kaddr)	({long _kvtp=(long)(kaddr);		\
+				(PLAT_VALID_MEM_KADDR(_kvtp))		\
+					? CLUMP_MEM_MAP_BASE(_kvtp) + CLUMP_MAP_NR(_kvtp)	\
+					: (void*)0;})
+#endif
+
+/*
+ * Given a page struct entry, return the physical address that the page struct represents.
+ * Since IA64 has all memory in the DMA zone, the following works:
+ */
+#define page_to_phys(page)		__pa(page_address(page))
+
+
+/*
+ * phys_node_to_cnodeid - convert a physical node number  to a cnodeid
+ */
+#define phys_node_to_cnodeid(pnode)	(NODEDIR->physical_node_map[pnode])
+
+
+/*
+ * phys_node_present(pnode) - test a physical node number to see if it is present
+ */
+#define phys_node_present(pnode)	(NODEDIR->physical_node_map[pnode] != (cnodeid_t) -1)
+
+#endif /* _ASM_IA64_SN_MMZONE_TEMP_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/module.h lia64-2.4/include/asm-ia64/sn/module.h
--- linux-2.4.16/include/asm-ia64/sn/module.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/module.h	Mon Nov 19 23:22:54 2001
@@ -1,31 +1,26 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_MODULE_H
-#define _ASM_SN_MODULE_H
+#ifndef _ASM_IA64_SN_MODULE_H
+#define _ASM_IA64_SN_MODULE_H
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-#include <linux/config.h>
 
 #include <asm/sn/systeminfo.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/ksys/elsc.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #ifdef BRINGUP /* max. number of modules?  Should be about 300.*/
 #define MODULE_MAX			56
 #endif /* BRINGUP */
 #define MODULE_MAX_NODES		1
-#endif /* CONFIG_SGI_IP35 */
 #define MODULE_HIST_CNT			16
 #define MAX_MODULE_LEN			16
 
@@ -39,8 +34,6 @@
 #define MODULE_FORMAT_LONG	2
 
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-
 /*
  *	Module id format
  *
@@ -134,17 +127,6 @@
 				 ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)))
 #define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
 
-#else
-
-/*
- * Some code that uses this macro will not be conditionally compiled.
- */
-#define MODULE_GET_BTCHAR(_m)	('?')
-#define MODULE_CMP(_m1, _m2)	((_m1) - (_m2))
-#define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
-
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
 typedef struct module_s module_t;
 
 struct module_s {
@@ -205,4 +187,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_MODULE_H */
+#endif /* _ASM_IA64_SN_MODULE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/nag.h lia64-2.4/include/asm-ia64/sn/nag.h
--- linux-2.4.16/include/asm-ia64/sn/nag.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/nag.h	Mon Nov 19 23:22:54 2001
@@ -0,0 +1,32 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+*/
+
+
+#ifndef _ASM_IA64_SN_NAG_H
+#define _ASM_IA64_SN_NAG_H
+
+
+#define NAG(mesg...) \
+do {										\
+	static unsigned int how_broken = 1;					\
+	static unsigned int threshold = 1;					\
+	if (how_broken == threshold) {						\
+		if (threshold < 10000)						\
+			threshold *= 10;					\
+		if (how_broken > 1)						\
+			printk(KERN_WARNING "%u times: ", how_broken);		\
+		else								\
+			printk(KERN_WARNING);					\
+		printk(mesg);							\
+	}									\
+	how_broken++;								\
+} while (0)
+
+
+#endif /* _ASM_IA64_SN_NAG_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/nic.h lia64-2.4/include/asm-ia64/sn/nic.h
--- linux-2.4.16/include/asm-ia64/sn/nic.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/nic.h	Mon Nov 19 23:22:54 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_NIC_H
-#define _ASM_SN_NIC_H
+#ifndef _ASM_IA64_SN_NIC_H
+#define _ASM_IA64_SN_NIC_H
 
 #include <asm/types.h>
 
@@ -125,4 +124,4 @@
 extern nic_vmce_t	nic_vmc_add(char *, nic_vmc_func *);
 extern void		nic_vmc_del(nic_vmce_t);
 
-#endif /* _ASM_SN_NIC_H */
+#endif /* _ASM_IA64_SN_NIC_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/nodemask.h lia64-2.4/include/asm-ia64/sn/nodemask.h
--- linux-2.4.16/include/asm-ia64/sn/nodemask.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/nodemask.h	Wed Dec 31 16:00:00 1969
@@ -1,330 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_NODEMASK_H
-#define _ASM_SN_NODEMASK_H
-
-#if defined(__KERNEL__) || defined(_KMEMUSER)
-
-#include <linux/config.h>
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#include <asm/sn/sn1/arch.h>    /* needed for MAX_COMPACT_NODES */
-#endif
-
-#define CNODEMASK_BOOTED_MASK		boot_cnodemask
-#define CNODEMASK_BIPW    64
-
-#if !defined(SN0XXL) && !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-			/* MAXCPUS 128p (64 nodes) or less */
-
-#define CNODEMASK_SIZE    1
-typedef uint64_t cnodemask_t;
-
-#define CNODEMASK_WORD(p,w)     (p)
-#define CNODEMASK_SET_WORD(p,w,val)     (p) = val
-#define CNODEMASK_CLRALL(p)     (p) = 0
-#define CNODEMASK_SETALL(p)     (p) = ~((cnodemask_t)0)
-#define CNODEMASK_IS_ZERO(p)	((p) == 0)
-#define CNODEMASK_IS_NONZERO(p)	((p) != 0)
-#define CNODEMASK_NOTEQ(p, q)	((p) != (q))
-#define CNODEMASK_EQ(p, q)      ((p) == (q))
-#define CNODEMASK_LSB_ISONE(p)  ((p) & 0x1ULL)
-
-#define CNODEMASK_ZERO()        ((cnodemask_t)0)
-#define CNODEMASK_CVTB(bit)     (1ULL << (bit))
-#define CNODEMASK_SETB(p, bit)	((p) |= 1ULL << (bit))
-#define CNODEMASK_CLRB(p, bit)	((p) &= ~(1ULL << (bit)))
-#define CNODEMASK_TSTB(p, bit)	((p) & (1ULL << (bit)))
-
-#define CNODEMASK_SETM(p, q)	((p) |= (q))
-#define CNODEMASK_CLRM(p, q)	((p) &= ~(q))
-#define CNODEMASK_ANDM(p, q)	((p) &= (q))
-#define CNODEMASK_TSTM(p, q)	((p) & (q))
-
-#define CNODEMASK_CPYNOTM(p, q)	((p) = ~(q))
-#define CNODEMASK_CPY(p, q)     ((p) = (q))
-#define CNODEMASK_ORNOTM(p, q)	((p) |= ~(q))
-#define CNODEMASK_SHIFTL(p)     ((p) <<= 1)
-#define CNODEMASK_SHIFTR(p)     ((p) >>= 1)
-#define CNODEMASK_SHIFTL_PTR(p)     (*(p) <<= 1)
-#define CNODEMASK_SHIFTR_PTR(p)     (*(p) >>= 1)
-
-/* Atomically set or clear a particular bit */
-#define CNODEMASK_ATOMSET_BIT(p, bit) atomicSetUlong((cnodemask_t *)&(p), (1ULL<<(bit))) 
-#define CNODEMASK_ATOMCLR_BIT(p, bit) atomicClearUlong((cnodemask_t *)&(p), (1ULL<<(bit)))
-
-/* Atomically set or clear a collection of bits */
-#define CNODEMASK_ATOMSET(p, q)  atomicSetUlong((cnodemask_t *)&(p), q)
-#define CNODEMASK_ATOMCLR(p, q)  atomicClearUlong((cnodemask_t *)&(p), q)
-
-/* Atomically set or clear a collection of bits, returning the old value */
-#define CNODEMASK_ATOMSET_MASK(__old, p, q)	{ \
-		(__old) = atomicSetUlong((cnodemask_t *)&(p), q); \
-}
-#define CNODEMASK_ATOMCLR_MASK(__old, p, q)	{ \
-		(__old) = atomicClearUlong((cnodemask_t *)&(p),q); \
-}
-
-#define CNODEMASK_FROM_NUMNODES(n)	((~(cnodemask_t)0)>>(CNODEMASK_BIPW-(n)))
-
-#else  /* SN0XXL || SN1 - MAXCPUS > 128 */
-
-#define CNODEMASK_SIZE    (MAX_COMPACT_NODES / CNODEMASK_BIPW)
-
-typedef struct {
-        uint64_t _bits[CNODEMASK_SIZE];
-} cnodemask_t;
-
-#define CNODEMASK_WORD(p,w)  \
-	((w >= 0 && w < CNODEMASK_SIZE) ? (p)._bits[(w)] : 0)
-#define CNODEMASK_SET_WORD(p,w,val)  { 				\
-	if (w >= 0 && w < CNODEMASK_SIZE) 			\
-		(p)._bits[(w)] = val;				\
-}
-
-#define CNODEMASK_CLRALL(p)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = 0;                               \
-}
-
-#define CNODEMASK_SETALL(p)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = ~(0);                            \
-}
-
-#define CNODEMASK_LSB_ISONE(p)  ((p)._bits[0] & 0x1ULL)
-
-
-#define CNODEMASK_SETM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] |= ((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_CLRM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] &= ~((q)._bits[i]);                \
-}
-
-#define CNODEMASK_ANDM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] &= ((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_CPY(p, q)  {					\
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = (q)._bits[i];	                \
-}
-
-#define CNODEMASK_CPYNOTM(p,q)    {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = ~((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_ORNOTM(p,q)     {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] |= ~((q)._bits[i]);                \
-}
-
-#define CNODEMASK_INDEX(bit)      ((bit) >> 6)
-#define CNODEMASK_SHFT(bit)       ((bit) & 0x3f)
-
-
-#define CNODEMASK_SETB(p, bit)	 				\
-	(p)._bits[CNODEMASK_INDEX(bit)] |= (1ULL << CNODEMASK_SHFT(bit))
-
-
-#define CNODEMASK_CLRB(p, bit)					\
-	(p)._bits[CNODEMASK_INDEX(bit)] &= ~(1ULL << CNODEMASK_SHFT(bit)) 
-
-
-#define CNODEMASK_TSTB(p, bit)		\
-	((p)._bits[CNODEMASK_INDEX(bit)] & (1ULL << CNODEMASK_SHFT(bit))) 
-
-/** Probably should add atomic update for entire cnodemask_t struct **/
-
-/* Atomically set or clear a particular bit */
-#define CNODEMASK_ATOMSET_BIT(p, bit) \
-        (atomicSetUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
-#define CNODEMASK_ATOMCLR_BIT(__old, p, bit) \
-        (atomicClearUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
-
-/* Atomically set or clear a collection of bits */
-#define CNODEMASK_ATOMSET(p, q) { \
-        int i;				\
-					\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
-	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
-        }				\
-}
-#define CNODEMASK_ATOMCLR(p, q) { \
-        int i;				\
-                        		\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
-	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
-        }				\
-}
-
-/* Atomically set or clear a collection of bits, returning the old value */
-#define CNODEMASK_ATOMSET_MASK(__old, p, q)  { \
-        int i;				\
-					\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
-           (__old)._bits[i] =	 \
-	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
-        }				\
-}
-#define CNODEMASK_ATOMCLR_MASK(__old, p, q) {					\
-        int i;				\
-                        		\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
-           (__old)._bits[i] =				\
-	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
-        }				\
-}
-
-__inline static cnodemask_t CNODEMASK_CVTB(int bit) 
-{
-	cnodemask_t __tmp;
-	CNODEMASK_CLRALL(__tmp);
-	CNODEMASK_SETB(__tmp,bit);
-	return(__tmp);
-}
-
-
-__inline static cnodemask_t CNODEMASK_ZERO(void)
-{
-	cnodemask_t __tmp;
-	CNODEMASK_CLRALL(__tmp);
-	return(__tmp);
-}
-
-__inline static int CNODEMASK_IS_ZERO (cnodemask_t p)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != 0)
-                        return 0;
-        return 1;
-}
-
-__inline static int CNODEMASK_IS_NONZERO (cnodemask_t p)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != 0)
-                        return 1;
-        return 0;
-}
-
-__inline static int CNODEMASK_NOTEQ (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != q._bits[i])
-                        return 1;
-        return 0;
-}
-
-__inline static int CNODEMASK_EQ (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != q._bits[i])
-                        return 0;
-        return 1;
-}
-
-
-__inline static int CNODEMASK_TSTM (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] & q._bits[i])
-                        return 1;
-        return 0;
-}
-
-__inline static void CNODEMASK_SHIFTL_PTR (cnodemask_t *p)
-{
-        int i;
-        uint64_t upper;
-
-        /*
-         * shift words starting with the last word
-         * of the vector and work backward to the first
-         * word updating the low order bits with the
-         * high order bit of the prev word.
-         */
-        for (i=(CNODEMASK_SIZE-1); i > 0; --i) {
-	   upper = (p->_bits[i-1] & (1ULL<<(CNODEMASK_BIPW-1))) ? 1 : 0;
-           p->_bits[i] <<= 1;
-           p->_bits[i] |= upper;
-        }
-        p->_bits[i] <<= 1;
-}
-
-__inline static void CNODEMASK_SHIFTR_PTR (cnodemask_t *p)
-{
-        int i;
-        uint64_t lower;
-
-        /*
-         * shift words starting with the first word
-         * of the vector and work forward to the last
-         * word updating the high order bit with the
-         * low order bit of the next word.
-         */
-        for (i=0; i < (CNODEMASK_SIZE-2); ++i) {
-	   lower = (p->_bits[i+1] & (0x1)) ? 1 : 0;
-           p->_bits[i] >>= 1;
-           p->_bits[i] |= (lower<<((CNODEMASK_BIPW-1)));
-        }
-        p->_bits[i] >>= 1;
-}
-
-__inline static cnodemask_t CNODEMASK_FROM_NUMNODES(int n)
-{
-	cnodemask_t __tmp;
-	int i;
-	CNODEMASK_CLRALL(__tmp);
-	for (i=0; i<n; i++) {
-		CNODEMASK_SETB(__tmp, i);
-	}
-	return(__tmp);
-}
-
-#endif /* SN0XXL || SN1 */
-
-extern cnodemask_t boot_cnodemask;
-
-#endif /* __KERNEL__ || _KMEMUSER */
-
-#endif /* _ASM_SN_NODEMASK_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/nodepda.h lia64-2.4/include/asm-ia64/sn/nodepda.h
--- linux-2.4.16/include/asm-ia64/sn/nodepda.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/nodepda.h	Mon Nov 19 23:22:54 2001
@@ -1,32 +1,27 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_NODEPDA_H
-#define _ASM_SN_NODEPDA_H
+#ifndef _ASM_IA64_SN_NODEPDA_H
+#define _ASM_IA64_SN_NODEPDA_H
 
-#ifdef	__cplusplus
-extern "C" {
-#endif
 
 #include <linux/config.h>
-
-#include <asm/sn/agent.h>
+#include <asm/irq.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/router.h>
-#include <asm/sn/synergy.h>
-/* #include <SN/klkernvars.h> */
-#ifdef LATER
-typedef struct module_s module_t;       /* Avoids sys/SN/module.h */
-#else
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/synergy.h>
+#endif
+#include <asm/sn/pda.h>
 #include <asm/sn/module.h>
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/hubstat.h>
 #endif
-/* #include <SN/slotnum.h> */
 
 /*
  * NUMA Node-Specific Data structures are defined in this file.
@@ -37,26 +32,16 @@
 /*
  * Subnode PDA structures. Each node needs a few data structures that 
  * correspond to the PIs on the HUB chip that supports the node.
- *
- * WARNING!!!! 6.5.x compatibility requirements prevent us from
- * changing or reordering fields in the following structure for IP27.
- * It is essential that the data mappings not change for IP27 platforms.
- * It is OK to add fields that are IP35 specific if they are under #ifdef IP35.
  */
+#if defined(CONFIG_IA64_SGI_SN1)
 struct subnodepda_s {
 	intr_vecblk_t	intr_dispatch0;
 	intr_vecblk_t	intr_dispatch1;
-	uint64_t	next_prof_timeout;
-	int		prof_count;
 };
 
-
 typedef struct subnodepda_s subnode_pda_t;
 
 
-struct ptpool_s;
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
 struct synergy_perf_s;
 #endif
 
@@ -65,8 +50,6 @@
  * Node-specific data structure.
  *
  * One of these structures is allocated on each node of a NUMA system.
- * Non-NUMA systems are considered to be systems with one node, and
- * hence there will be one of this structure for the entire system.
  *
  * This structure provides a convenient way of keeping together 
  * all per-node data structures. 
@@ -74,119 +57,14 @@
 
 
 
-#ifdef LATER
-/*
- * The following structure is contained in the nodepda & contains
- * a lock & queue-head for sanon pages that belong to the node.
- * See the anon manager for more details.
- */
-typedef struct {
-	lock_t  sal_lock;
-	plist_t sal_listhead;
-} sanon_list_head_t;
-#endif
 struct nodepda_s {
 
-#ifdef	NUMA_BASE
-
-	/* 
-	 * Pointer to this node's copy of Nodepdaindr 
-	 */
-	struct nodepda_s	**pernode_pdaindr; 
-
-	/*
-         * Data used for migration control
-         */
-	struct migr_control_data_s *mcd; 
-
-	/*
-         * Data used for replication control
-         */
-	struct repl_control_data_s *rcd;
-
-        /*
-         * Numa statistics
-         */
-	struct numa_stats_s *numa_stats;
-
-        /*
-         * Load distribution
-         */
-        uint memfit_assign;
-
-        /*
-         * New extended memory reference counters
-         */
-        void *migr_refcnt_counterbase;
-        void *migr_refcnt_counterbuffer;
-        size_t migr_refcnt_cbsize;
-        int  migr_refcnt_numsets;
-
-        /*
-         * mem_tick quiescing lock
-         */
-        uint mem_tick_lock;
-
-        /*
-         * Migration candidate set
-         * by migration prologue intr handler
-         */
-        uint64_t migr_candidate;
-
-	/*
-	 * Each node gets its own syswait counter to remove contention
-	 * on the global one.
-	 */
-#ifdef	LATER
-	struct syswait syswait;
-#endif
-
-#endif	/* NUMA_BASE */
-	/*
-	 * Node-specific Zone structures.
-	 */
-#ifdef LATER
-	zoneset_element_t	node_zones;
-	pg_data_t	node_pg_data;	/* VM page data structures */ 
-	plist_t	error_discard_plist;
-#endif
-	uint		error_discard_count;
-	uint		error_page_count;
-	uint		error_cleaned_count;
-	spinlock_t	error_discard_lock;
 
-	/* Information needed for SN Hub chip interrupt handling. */
-	subnode_pda_t	snpda[NUM_SUBNODES];
-	/* Distributed kernel support */
-#ifdef	LATER
-	kern_vars_t	kern_vars;
-#endif
-	/* Vector operation support */
-	/* Change this to a sleep lock? */
-	spinlock_t	vector_lock;
-	/* State of the vector unit for this node */
-	char		vector_unit_busy;
 	cpuid_t         node_first_cpu; /* Starting cpu number for node */
 	ushort          node_num_cpus;  /* Number of cpus present       */
-
-	/* node utlbmiss info */
-  	spinlock_t		node_utlbswitchlock;
-	volatile cpumask_t	node_utlbmiss_flush;
-	volatile signed char	node_need_utlbmiss_patch;
-	volatile char		node_utlbmiss_patched;
-	nodepda_router_info_t	*npda_rip_first;
-	nodepda_router_info_t	**npda_rip_last;
-	int		dependent_routers;
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-	int			synergy_perf_enabled;
-        int       		synergy_perf_freq;
-	spinlock_t		synergy_perf_lock;
-        uint64_t       		synergy_inactive_intervals;
-        uint64_t       		synergy_active_intervals;
-        struct synergy_perf_s	*synergy_perf_data;
-        struct synergy_perf_s	*synergy_perf_first; /* reporting consistency .. */
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
+					/* WARNING: no guarantee that   */
+					/*  the second cpu on a node is */
+					/*  node_first_cpu+1.           */
 
 	devfs_handle_t 	xbow_vhdl;
 	nasid_t		xbow_peer;	/* NASID of our peer hub on xbow */
@@ -194,84 +72,67 @@
 	slotid_t	slotdesc;
 	moduleid_t	module_id;	/* Module ID (redundant local copy) */
 	module_t	*module;	/* Pointer to containing module */
-	int		hub_chip_rev;	/* Rev of my Hub chip */
-	char		nasid_mask[NASID_MASK_BYTES];
-					/* Need a copy of the nasid mask
-					 * on every node */
 	xwidgetnum_t 	basew_id;
 	devfs_handle_t 	basew_xc;
-	spinlock_t	fprom_lock;
-	char		ni_error_print; /* For printing ni error state
-					 * only once during system panic
-					 */
-#ifdef	LATER
-	md_perf_monitor_t node_md_perfmon;
-	hubstat_t	hubstats;
 	int		hubticks;
-	sbe_info_t	*sbe_info;	/* ECC single-bit error statistics */
-#endif	/* LATER */
-	int		huberror_ticks;
-
-	router_queue_t  *visited_router_q;
-	router_queue_t	*bfs_router_q; 
-					/* Used for router traversal */
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-	router_map_ent_t router_map[MAX_RTR_BREADTH];
-#endif
-	int		num_routers;	/* Total routers in the system */
+	int		num_routers;	/* XXX not setup! Total routers in the system */
 
-        char		membank_flavor;
-	                                /* Indicates what sort of memory 
-					 * banks are present on this node
-					 */
 	
 	char		*hwg_node_name;	/* hwgraph node name */
-
-	struct widget_info_t *widget_info;	/* Node as xtalk widget */
 	devfs_handle_t	node_vertex;	/* Hwgraph vertex for this node */
 
 	void 		*pdinfo;	/* Platform-dependent per-node info */
-	uint64_t	*dump_stack;	/* Dump stack during nmi handling */
-	int		dump_count;	/* To allow only one cpu-per-node */
-#ifdef	LATER
-	io_perf_monitor_t node_io_perfmon;
-#endif
 
-	/*
-	 * Each node gets its own pdcount counter to remove contention
-	 * on the global one.
-	 */
-
-	int pdcount;			/* count of pdinserted pages */
 
-#ifdef	NUMA_BASE
-	void		*cached_global_pool;	/* pointer to cached vmpool */
-#endif /* NUMA_BASE */
+	nodepda_router_info_t	*npda_rip_first;
+	nodepda_router_info_t	**npda_rip_last;
 
-#ifdef	LATER
-	sanon_list_head_t sanon_list_head;	/* head for sanon pages */	
-#endif
-#ifdef	NUMA_BASE
-	struct ptpool_s	*ptpool;	/* ptpool for this node */
-#endif /* NUMA_BASE */
 
 	/*
 	 * The BTEs on this node are shared by the local cpus
 	 */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#ifdef	LATER
-	bteinfo_t	*node_bte_info[BTES_PER_NODE];
-#endif
-#endif
+	//bteinfo_t	node_bte_info[BTES_PER_NODE];
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	subnode_pda_t	snpda[NUM_SUBNODES];
+	/*
+	 * New extended memory reference counters
+ 	 */
+	void			*migr_refcnt_counterbase;
+	void			*migr_refcnt_counterbuffer;
+	size_t			migr_refcnt_cbsize;
+	int			migr_refcnt_numsets;
+	hubstat_t		hubstats;
+	int			synergy_perf_enabled;
+        int       		synergy_perf_freq;
+	spinlock_t		synergy_perf_lock;
+        uint64_t       		synergy_inactive_intervals;
+        uint64_t       		synergy_active_intervals;
+        struct synergy_perf_s	*synergy_perf_data;
+        struct synergy_perf_s	*synergy_perf_first; /* reporting consistency .. */
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+	/* 
+	 * Array of pointers to the nodepdas for each node.
+	 */
+	struct nodepda_s	*pernode_pdaindr[MAX_COMPACT_NODES]; 
+
 };
 
 typedef struct nodepda_s nodepda_t;
 
+#ifdef CONFIG_IA64_SGI_SN2
+struct irqpda_s {
+	int num_irq_used;
+	char irq_flags[NR_IRQS];
+};
+
+typedef struct irqpda_s irqpda_t;
+
+#endif /* CONFIG_IA64_SGI_SN2 */
+
 
-#define NODE_MODULEID(_node)	(NODEPDA(_node)->module_id)
-#define NODE_SLOTID(_node)	(NODEPDA(_node)->slotdesc)
 
-#ifdef	NUMA_BASE
 /*
  * Access Functions for node PDA.
  * Since there is one nodepda for each node, we need a convenient mechanism
@@ -279,180 +140,49 @@
  * The next set of definitions provides this.
  * Routines are expected to use 
  *
- *	nodepda		-> to access PDA for the node on which code is running
- *	subnodepda	-> to access subnode PDA for the node on which code is running
+ *	nodepda			-> to access node PDA for the node on which code is running
+ *	subnodepda		-> to access subnode PDA for the subnode on which code is running
  *
- *	NODEPDA(x)	-> to access node PDA for cnodeid 'x'
- *	SUBNODEPDA(x,s)	-> to access subnode PDA for cnodeid/slice 'x'
- */
-
-#ifdef	LATER
-#define	nodepda		private.p_nodepda	/* Ptr to this node's PDA */
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#define subnodepda	private.p_subnodepda	/* Ptr to this node's subnode PDA */
-#endif
-
-#else
-/*
- * Until we have a shared node local area defined, do it this way ..
- * like in Caliase space.  See above.
- */
-extern nodepda_t        *nodepda;
-extern subnode_pda_t	*subnodepda;
-#endif
-
-/* 
- * Nodepdaindr[]
- * This is a private data structure for use only in early initialization.
- * All users of nodepda should use the macro NODEPDA(nodenum) to get
- * the suitable nodepda structure.
- * This macro has the advantage of not requiring #ifdefs for NUMA and
- * non-NUMA code.
- */
-extern nodepda_t	*Nodepdaindr[]; 
-/*
- * NODEPDA_GLOBAL(x) macro should ONLY be used during early initialization.
- * Once meminit is complete, NODEPDA(x) is ready to use.
- * During early init, the system fills up Nodepdaindr.  By the time we
- * are in meminit(), all nodepdas are initialized, and hence
- * we can fill up the node_pdaindr array in each nodepda structure.
+ *	NODEPDA(cnode)		-> to access node PDA for cnodeid 
+ *	SUBNODEPDA(cnode,sn)	-> to access subnode PDA for cnodeid/subnode
  */
-#define	NODEPDA_GLOBAL(x)	Nodepdaindr[x]
 
-/*
- * Returns a pointer to a given node's nodepda.
- */
-#define	NODEPDA(x)		(nodepda->pernode_pdaindr[x])
+#define	nodepda		pda.p_nodepda		/* Ptr to this node's PDA */
+#define	NODEPDA(cnode)		(nodepda->pernode_pdaindr[cnode])
 
-/*
- * Returns a pointer to a given node/slice's subnodepda.
- *	SUBNODEPDA(cnode, subnode) - uses cnode as first arg
- *	SNPDA(npda, subnode)	   - uses pointer to nodepda as first arg
- */
-#define	SUBNODEPDA(x,sn)	(&nodepda->pernode_pdaindr[x]->snpda[sn])
+#if defined(CONFIG_IA64_SGI_SN1)
+#define subnodepda	pda.p_subnodepda	/* Ptr to this node's subnode PDA */
+#define	SUBNODEPDA(cnode,sn)	(&(NODEPDA(cnode)->snpda[sn]))
 #define	SNPDA(npda,sn)		(&(npda)->snpda[sn])
+#endif
 
-#define NODEPDA_ERROR_FOOTPRINT(node, cpu) \
-                   (&(NODEPDA(node)->error_stamp[cpu]))
-#define NODEPDA_MDP_MON(node)	(&(NODEPDA(node)->node_md_perfmon))
-#define NODEPDA_IOP_MON(node)	(&(NODEPDA(node)->node_io_perfmon))
 
 /*
  * Macros to access data structures inside nodepda 
  */
-#if NUMA_MIGR_CONTROL
-#define NODEPDA_MCD(node) (NODEPDA(node)->mcd)
-#endif /* NUMA_MIGR_CONTROL */
-
-#if NUMA_REPL_CONTROL
-#define NODEPDA_RCD(node) (NODEPDA(node)->rcd)
-#endif /* NUMA_REPL_CONTROL */
-
-#if (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL)
-#define NODEPDA_LRS(node) (NODEPDA(node)->lrs)
-#endif /* (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL) */
+#define NODE_MODULEID(cnode)	(NODEPDA(cnode)->module_id)
+#define NODE_SLOTID(cnode)	(NODEPDA(cnode)->slotdesc)
 
-/* 
- * Exported functions
- */
-extern nodepda_t *nodepda_alloc(void);
 
-#else	/* !NUMA_BASE */
 /*
- * For a single-node system we will just have one global nodepda pointer
- * allocated at startup.  The global nodepda will point to this nodepda 
- * structure.
+ * Quickly convert a compact node ID into a hwgraph vertex
  */
-extern nodepda_t	*Nodepdaindr; 
+#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex)
 
-/*
- * On non-NUMA systems, NODEPDA_GLOBAL and NODEPDA macros collapse to
- * be the same.
- */
-#define	NODEPDA_GLOBAL(x)	Nodepdaindr
 
 /*
- * Returns a pointer to a given node's nodepda.
+ * Check if given a compact node id the corresponding node has all the
+ * cpus disabled. 
  */
-#define	NODEPDA(x)	Nodepdaindr
+#define is_headless_node(cnode)		((cnode == CNODEID_NONE) || \
+					 (CNODE_NUM_CPUS(cnode) == 0))
 
 /*
- * nodepda can also be defined as private.p_nodepda.
- * But on non-NUMA systems, there is only one nodepda, and there is
- * no reason to go through the PDA to access this pointer.
- * Hence nodepda aliases to the global nodepda directly.
- *
- * Routines should use nodepda to access the local node's PDA.
- */
-#define	nodepda		(Nodepdaindr)
-
-#endif	/* NUMA_BASE */
-
-/* Quickly convert a compact node ID into a hwgraph vertex */
-#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex)
-
-
-/* Check if given a compact node id the corresponding node has all the
- * cpus disabled. 
- */
-#define is_headless_node(_cnode)	((_cnode == CNODEID_NONE) || \
-					 (CNODE_NUM_CPUS(_cnode) == 0))
-/* Check if given a node vertex handle the corresponding node has all the
+ * Check if given a node vertex handle the corresponding node has all the
  * cpus disabled. 
  */
 #define is_headless_node_vertex(_nodevhdl) \
 			is_headless_node(nodevertex_to_cnodeid(_nodevhdl))
 
-#ifdef	__cplusplus
-}
-#endif
-
-#ifdef NUMA_BASE
-/*
- * To remove contention on the global syswait counter each node will have
- * its own.  Each clock tick the clock cpu will re-calculate the global
- * syswait counter by summing from each of the nodes.  The other cpus will
- * continue to read the global one during their clock ticks.   This does 
- * present a problem when a thread increments the count on one node and wakes
- * up on a different node and decrements it there.  Eventually the count could
- * overflow if this happens continually for a long period.  To prevent this
- * second_thread() periodically preserves the current syswait state and
- * resets the counters.
- */
-#define ADD_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, 1)
-#define SUB_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, -1)
-#else
-#define ADD_SYSWAIT(_field)				\
-{							\
-	ASSERT(syswait._field >= 0);			\
-	atomicAddInt(&syswait._field, 1);		\
-}
-#define SUB_SYSWAIT(_field)				\
-{							\
-	ASSERT(syswait._field > 0);			\
-	atomicAddInt(&syswait._field, -1);		\
-}
-#endif /* NUMA_BASE */
-
-#ifdef NUMA_BASE
-/*
- * Another global variable to remove contention from: pdcount.
- * See above comments for SYSWAIT.
- */
-#define ADD_PDCOUNT(_n)					\
-{							\
-	atomicAddInt(&nodepda->pdcount, _n);		\
-	if (_n > 0 && !pdflag)				\
-		pdflag = 1;				\
-}
-#else
-#define ADD_PDCOUNT(_n)					\
-{							\
-	ASSERT(&pdcount >= 0);				\
-	atomicAddInt(&pdcount, _n);			\
-	if (_n > 0 && !pdflag)				\
-		pdflag = 1;				\
-}
-#endif /* NUMA_BASE */
 
-#endif /* _ASM_SN_NODEPDA_H */
+#endif /* _ASM_IA64_SN_NODEPDA_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/bridge.h lia64-2.4/include/asm-ia64/sn/pci/bridge.h
--- linux-2.4.16/include/asm-ia64/sn/pci/bridge.h	Tue Mar  6 19:44:34 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/bridge.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_BRIDGE_H
 #define _ASM_SN_PCI_BRIDGE_H
@@ -53,7 +52,7 @@
  *    Bridge address map
  */
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 
 #ifdef __cplusplus
 extern "C" {
@@ -373,7 +372,7 @@
 				    ds:2,	/* Data size	  */
 				    gbr:1,	/* GBR enable	  */
 				    vbpm:1,	/* VBPM message	  */
-				    error:1,	/* Error occurred  */
+				    error:1,	/* Error occurred */
 				    barr:1,	/* Barrier op	  */
 				    rsvd:8;
 	} berr_st;
@@ -638,7 +637,7 @@
 
 
 #define berr_field	berr_un.berr_st
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /*
  * The values of these macros can and should be crosschecked
@@ -903,10 +902,10 @@
 #define BRIDGE_DEVIO_2MB	0x00200000	/* Device IO Offset (0..1) */
 #define BRIDGE_DEVIO_1MB	0x00100000	/* Device IO Offset (2..7) */
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS */
 
@@ -971,6 +970,10 @@
 #define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)
 #define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)
 #define BRIDGE_CTRL_SYS_END		(0x1 << 9)
+#define BRIDGE_CTRL_BUS_SPEED(n)        ((n) << 4)
+#define BRIDGE_CTRL_BUS_SPEED_MASK      (BRIDGE_CTRL_BUS_SPEED(0x3))
+#define BRIDGE_CTRL_BUS_SPEED_33        0x00
+#define BRIDGE_CTRL_BUS_SPEED_66        0x10
 #define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)
 #define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))
 #define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)
@@ -1296,14 +1299,14 @@
 #define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
 #define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define IS_PCI32_LOCAL(x)	((uint64_t)(x) < PCI32_MAPPED_BASE)
 #define IS_PCI32_MAPPED(x)	((uint64_t)(x) < PCI32_DIRECT_BASE && \
 					(uint64_t)(x) >= PCI32_MAPPED_BASE)
 #define IS_PCI32_DIRECT(x)	((uint64_t)(x) >= PCI32_MAPPED_BASE)
 #define IS_PCI64(x)		((uint64_t)(x) >= PCI64_BASE)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /*
  * The GIO address space.
@@ -1318,13 +1321,13 @@
 #define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
 #define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define IS_GIO_LOCAL(x)		((uint64_t)(x) < GIO_MAPPED_BASE)
 #define IS_GIO_MAPPED(x)	((uint64_t)(x) < GIO_DIRECT_BASE && \
 					(uint64_t)(x) >= GIO_MAPPED_BASE)
 #define IS_GIO_DIRECT(x)	((uint64_t)(x) >= GIO_MAPPED_BASE)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /* PCI to xtalk mapping */
 
@@ -1347,7 +1350,7 @@
 #define PCI64_ATTR_RMF_MASK	0x00ff000000000000
 #define PCI64_ATTR_RMF_SHFT	48
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* Address translation entry for mapped pci32 accesses */
 typedef union ate_u {
     uint64_t		    ent;
@@ -1375,7 +1378,7 @@
 	uint64_t		valid:1;
     } field;
 } ate_t;
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define ATE_V		(1 << 0)
 #define ATE_CO		(1 << 1)
@@ -1401,7 +1404,7 @@
 #define is_xbridge(bridge) \
         (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM)
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* ========================================================================
  */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pci_bus_cvlink.h lia64-2.4/include/asm-ia64/sn/pci/pci_bus_cvlink.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pci_bus_cvlink.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pci_bus_cvlink.h	Mon Nov 19 23:22:55 2001
@@ -4,18 +4,45 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_CVLINK_H
 #define _ASM_SN_PCI_CVLINK_H
 
+#include <asm/sn/types.h>
+#include <asm/sn/hack.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/io.h>
+
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+
 #define SET_PCIA64(dev) \
 	(((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1
 #define IS_PCIA64(dev)	(((dev)->dma_mask == 0xffffffffffffffffUL) || \
 		(((struct sn1_device_sysdata *)((dev)->sysdata))->isa64))
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
+
+#define PCIDEV_VERTEX(pci_dev) \
+	(((struct sn1_device_sysdata *)((pci_dev)->sysdata))->vhdl)
+
+#define PCIBUS_VERTEX(pci_bus) \
+	(((struct sn1_widget_sysdata *)((pci_bus)->sysdata))->vhdl)
 
 struct sn1_widget_sysdata {
         devfs_handle_t  vhdl;
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pci_defs.h lia64-2.4/include/asm-ia64/sn/pci/pci_defs.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pci_defs.h	Thu Jan  4 15:25:55 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pci_defs.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCI_DEFS_H
 #define _ASM_SN_PCI_PCI_DEFS_H
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pciba.h lia64-2.4/include/asm-ia64/sn/pci/pciba.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pciba.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pciba.h	Mon Nov 19 23:22:55 2001
@@ -1,24 +1,33 @@
-/* $Id$
+/* 
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Copyright (C) 1997, 2001 Silicon Graphics, Inc. All rights reserved.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
  */
+
 #ifndef _ASM_SN_PCI_PCIBA_H
 #define _ASM_SN_PCI_PCIBA_H
 
-/*
- * These are all the HACKS from ioccom.h ..
- */
-#define IOCPARM_MASK    0xff            /* parameters must be < 256 bytes */
-#define IOC_VOID        0x20000000      /* no parameters */
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+/* for application compatibility with IRIX (why do I bother?) */
+
+#ifndef __KERNEL__
+typedef u_int8_t uint8_t;
+typedef u_int16_t uint16_t;
+typedef u_int32_t uint32_t;
+#endif
+
+#define PCI_CFG_VENDOR_ID	PCI_VENDOR_ID
+#define PCI_CFG_COMMAND		PCI_COMMAND
+#define PCI_CFG_REV_ID		PCI_REVISION_ID
+#define PCI_CFG_HEADER_TYPE	PCI_HEADER_TYPE
+#define PCI_CFG_BASE_ADDR(n)	PCI_BASE_ADDRESS_##n
 
-/*
- * The above needs to be modified and follow LINUX ...
- */
 
 /* /hw/.../pci/[slot]/config accepts ioctls to read
  * and write specific registers as follows:
@@ -69,18 +78,11 @@
 /* PCIIOCGETBASE(n): arg is ptr to a 32-bit int,
  * which will get the value of the BASE<n> register.
  */
+
+/* FIXME chadt: this doesn't tell me whether or not this will work
+   with non-constant 'n.'  */
 #define	PCIIOCGETBASE(n)	PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n))
 
-/* /hw/.../pci/[slot]/intr accepts an ioctl to
- * set up user level interrupt handling as follows:
- *
- * "n" is a bitmap of which of the four PCI interrupt
- * lines are of interest, using PCIIO_INTR_LINE_[ABCD].
- */
-#define	PCIIOCSETULI(n)		_IOWR(1,n,struct uliargs)
-#if _KERNEL
-#define PCIIOCSETULI32(n)	_IOWR(1,n,struct uliargs32)
-#endif
 
 /* /hw/.../pci/[slot]/dma accepts ioctls to allocate
  * and free physical memory for use in user-triggered
@@ -93,11 +95,20 @@
  * both the size of the request and the flag values
  * to be used in setting up the DMA.
  *
+
+FIXME chadt: gonna have to revisit this: what flags would an IRIXer like to
+ have available?
+
  * Any flags normally useful in pciio_dmamap
- * or pciio_dmatrans function calls can6 be used here.
- */
+ * or pciio_dmatrans function calls can6 be used here.  */
 #define	PCIIOCDMAALLOC_REQUEST_PACK(flags,size)		\
 	((((uint64_t)(flags))<<32)|			\
 	 (((uint64_t)(size))&0xFFFFFFFF))
+
+
+#ifdef __KERNEL__
+extern int pciba_init(void);
+#endif
+
 
 #endif	/* _ASM_SN_PCI_PCIBA_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pcibr.h lia64-2.4/include/asm-ia64/sn/pci/pcibr.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pcibr.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pcibr.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIBR_H
 #define _ASM_SN_PCI_PCIBR_H
@@ -13,7 +12,7 @@
 #if defined(__KERNEL__)
 
 #include <asm/sn/dmamap.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/pio.h>
 
 #include <asm/sn/pci/pciio.h>
@@ -31,7 +30,7 @@
 #define PCIBR_INTR_BLOCKED		0x40000000
 #define PCIBR_INTR_BUSY			0x80000000
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* =====================================================================
  *    opaque types used by pcibr's xtalk bus provider
@@ -183,10 +182,7 @@
 
 extern void		pcibr_intr_free(pcibr_intr_t intr);
 
-extern int		pcibr_intr_connect(pcibr_intr_t intr,
-					   intr_func_t intr_func,
-					   intr_arg_t intr_arg,
-					   void *thread);
+extern int		pcibr_intr_connect(pcibr_intr_t intr);
 
 extern void		pcibr_intr_disconnect(pcibr_intr_t intr);
 
@@ -349,7 +345,7 @@
 
 extern int		pcibr_asic_rev(devfs_handle_t);
 
-#endif 	/* _LANGUAGE_C */
+#endif 	/* __ASSEMBLY__ */
 #endif	/* #if defined(__KERNEL__) */
 /* 
  * Some useful ioctls into the pcibr driver
@@ -390,10 +386,34 @@
 /*
  * Structures for requesting PCI bridge information and receiving a response
  */
-typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t;
+typedef struct pcibr_slot_req_s *pcibr_slot_req_t;
+typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t;
+typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t;
 typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
 typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
 
+#define L1_QSIZE                128      /* our L1 message buffer size */
+struct pcibr_slot_req_s {
+    int                      req_slot;
+    union {
+        pcibr_slot_up_resp_t     up;
+        pcibr_slot_down_resp_t   down;
+        pcibr_slot_info_resp_t   query;
+        void                    *any;
+    }                       req_respp;
+    int                     req_size;
+};
+
+struct pcibr_slot_up_resp_s {
+    int                     resp_sub_errno;
+    char                    resp_l1_msg[L1_QSIZE + 1];
+};
+
+struct pcibr_slot_down_resp_s {
+    int                     resp_sub_errno;
+    char                    resp_l1_msg[L1_QSIZE + 1];
+};
+
 struct pcibr_slot_info_req_s {
    int                      req_slot;
    pcibr_slot_info_resp_t   req_respp;
@@ -454,7 +474,40 @@
         int                     resp_f_att_det_error;
 
     } resp_func[8];
-
 };
+
+
+/*
+ * PCI specific errors, interpreted by pciconfig command
+ */
+
+/* EPERM                          1    */
+#define PCI_SLOT_ALREADY_UP       2     /* slot already up */
+#define PCI_SLOT_ALREADY_DOWN     3     /* slot already down */
+#define PCI_IS_SYS_CRITICAL       4     /* slot is system critical */
+/* EIO                            5    */
+/* ENXIO                          6    */
+#define PCI_L1_ERR                7     /* L1 console command error */
+#define PCI_NOT_A_BRIDGE          8     /* device is not a bridge */
+#define PCI_SLOT_IN_SHOEHORN      9     /* slot is in a shorhorn */
+#define PCI_NOT_A_SLOT           10     /* slot is invalid */
+#define PCI_RESP_AREA_TOO_SMALL  11     /* slot is invalid */
+/* ENOMEM                        12    */
+#define PCI_NO_DRIVER            13     /* no driver for device */
+/* EFAULT                        14    */
+#define PCI_EMPTY_33MHZ          15     /* empty 33 MHz bus */
+/* EBUSY                         16    */
+#define PCI_SLOT_RESET_ERR       17     /* slot reset error */
+#define PCI_SLOT_INFO_INIT_ERR   18     /* slot info init error */
+/* ENODEV                        19    */
+#define PCI_SLOT_ADDR_INIT_ERR   20     /* slot addr space init error */
+#define PCI_SLOT_DEV_INIT_ERR    21     /* slot device init error */
+/* EINVAL                        22    */
+#define PCI_SLOT_GUEST_INIT_ERR  23     /* slot guest info init error */
+#define PCI_SLOT_RRB_ALLOC_ERR   24     /* slot initial rrb alloc error */
+#define PCI_SLOT_DRV_ATTACH_ERR  25     /* driver attach error */
+#define PCI_SLOT_DRV_DETACH_ERR  26     /* driver detach error */
+/* ERANGE                        34    */
+/* EUNATCH                       42    */
 
 #endif				/* _ASM_SN_PCI_PCIBR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pcibr_private.h lia64-2.4/include/asm-ia64/sn/pci/pcibr_private.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pcibr_private.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pcibr_private.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H
 #define _ASM_SN_PCI_PCIBR_PRIVATE_H
@@ -16,6 +15,7 @@
  * should ever peek into this file.
  */
 
+#include <linux/config.h>
 #include <asm/sn/pci/pciio_private.h>
 #include <asm/sn/ksys/l1.h>
 
@@ -100,9 +100,6 @@
 #define	bi_flags	bi_pi.pi_flags	/* PCIBR_INTR flags */
 #define	bi_dev		bi_pi.pi_dev	/* associated pci card */
 #define	bi_lines	bi_pi.pi_lines	/* which PCI interrupt line(s) */
-#define	bi_func		bi_pi.pi_func	/* handler function (when connected) */
-#define	bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
-#define bi_tinfo	bi_pi.pi_tinfo	/* Thread info (when connected) */
 #define bi_mustruncpu	bi_pi.pi_mustruncpu /* Where we must run. */
 #define bi_irq		bi_pi.pi_irq	/* IRQ assigned. */
 #define bi_cpu		bi_pi.pi_cpu	/* cpu assigned. */
@@ -173,14 +170,17 @@
  */
 
 struct pcibr_soft_s {
-    devfs_handle_t            bs_conn;	/* xtalk connection point */
-    devfs_handle_t            bs_vhdl;	/* vertex owned by pcibr */
+    devfs_handle_t          bs_conn;		/* xtalk connection point */
+    devfs_handle_t          bs_vhdl;		/* vertex owned by pcibr */
     int                     bs_int_enable;	/* Mask of enabled intrs */
-    bridge_t               *bs_base;	/* PIO pointer to Bridge chip */
-    char                   *bs_name;	/* hw graph name */
-    xwidgetnum_t            bs_xid;	/* Bridge's xtalk ID number */
-    devfs_handle_t            bs_master;	/* xtalk master vertex */
-    xwidgetnum_t            bs_mxid;	/* master's xtalk ID number */
+    bridge_t               *bs_base;		/* PIO pointer to Bridge chip */
+    char                   *bs_name;		/* hw graph name */
+    xwidgetnum_t            bs_xid;		/* Bridge's xtalk ID number */
+    devfs_handle_t          bs_master;		/* xtalk master vertex */
+    xwidgetnum_t            bs_mxid;		/* master's xtalk ID number */
+    pciio_slot_t            bs_first_slot;      /* first existing slot */
+    pciio_slot_t            bs_last_slot;       /* last existing slot */
+
 
     iopaddr_t               bs_dir_xbase;	/* xtalk address for 32-bit PCI direct map */
     xwidgetnum_t	    bs_dir_xport;	/* xtalk port for 32-bit PCI direct map */
@@ -190,7 +190,7 @@
     short		    bs_int_ate_size;	/* number of internal ates */
     short		    bs_xbridge;		/* if 1 then xbridge */
 
-    int                     bs_rev_num;	/* revision number of Bridge */
+    int                     bs_rev_num;		/* revision number of Bridge */
 
     unsigned                bs_dma_flags;	/* revision-implied DMA flags */
 
@@ -253,6 +253,7 @@
 	struct {
 	    pciio_space_t           bssd_space;
 	    iopaddr_t               bssd_base;
+            int                     bssd_ref_cnt;
 	} bss_devio;
 
 	/* Shadow value for Device(x) register,
@@ -312,7 +313,9 @@
     int                     bs_rrb_fixed;
     int			    bs_rrb_avail[2];
     int			    bs_rrb_res[8];
-    int			    bs_rrb_valid[16];
+    int                     bs_rrb_res_dflt[8];
+    int                     bs_rrb_valid[16];
+    int                     bs_rrb_valid_dflt[16];
 
     struct {
 	/* Each Bridge interrupt bit has a single XIO
@@ -433,5 +436,42 @@
 
 #define pcibr_soft_get(v)       ((pcibr_soft_t)hwgraph_fastinfo_get((v)))
 #define pcibr_soft_set(v,i)     (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i)))
+
+/* Use io spin locks. This ensures that all the PIO writes from a particular
+ * CPU to a particular IO device are synched before the start of the next
+ * set of PIO operations to the same device.
+ */
+#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)
+#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)
+
+/*
+ * mem alloc/free macros
+ */
+#define NEWAf(ptr,n,f)	(ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))
+#define NEWA(ptr,n)	(ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))
+#define DELA(ptr,n)	(kfree(ptr))
+
+#define NEWf(ptr,f)	NEWAf(ptr,1,f)
+#define NEW(ptr)	NEWA(ptr,1)
+#define DEL(ptr)	DELA(ptr,1)
+
+typedef volatile unsigned *cfg_p;
+typedef volatile bridgereg_t *reg_p;
+
+#define PCIBR_RRB_SLOT_VIRTUAL  8
+#define PCIBR_VALID_SLOT(s)     (s < 8)
+#define PCIBR_D64_BASE_UNSET    (0xFFFFFFFFFFFFFFFF)
+#define PCIBR_D32_BASE_UNSET    (0xFFFFFFFF)
+#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev"
+
+#define PCIBR_SOFT_LIST 1
+#if PCIBR_SOFT_LIST
+typedef struct pcibr_list_s *pcibr_list_p;
+struct pcibr_list_s {
+	pcibr_list_p            bl_next;
+	pcibr_soft_t            bl_soft;
+	devfs_handle_t          bl_vhdl;
+};
+#endif /* PCIBR_SOFT_LIST */
 
 #endif				/* _ASM_SN_PCI_PCIBR_PRIVATE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pciio.h lia64-2.4/include/asm-ia64/sn/pci/pciio.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pciio.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pciio.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIIO_H
 #define _ASM_SN_PCI_PCIIO_H
@@ -15,18 +14,14 @@
  */
 
 #include <asm/sn/ioerror.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 
 #include <asm/sn/dmamap.h>
 #include <asm/sn/alenlist.h>
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 typedef int pciio_vendor_id_t;
 
 #define PCIIO_VENDOR_ID_NONE	-1
@@ -387,10 +382,7 @@
 pciio_intr_free_f       (pciio_intr_t intr_hdl);
 
 typedef int
-pciio_intr_connect_f    (pciio_intr_t intr_hdl,		/* pciio intr resource handle */
-			 intr_func_t intr_func,		/* pciio intr handler */
-			 intr_arg_t intr_arg,	/* arg to intr handler */
-			 void *thread);	/* intr thread to use */
+pciio_intr_connect_f    (pciio_intr_t intr_hdl);	/* pciio intr resource handle */
 
 typedef void
 pciio_intr_disconnect_f (pciio_intr_t intr_hdl);
@@ -729,8 +721,5 @@
 extern int              pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
 extern int		pciio_dma_enabled(devfs_handle_t);
 
-#ifdef __cplusplus
-};
-#endif
 #endif				/* C or C++ */
 #endif				/* _ASM_SN_PCI_PCIIO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pci/pciio_private.h lia64-2.4/include/asm-ia64/sn/pci/pciio_private.h
--- linux-2.4.16/include/asm-ia64/sn/pci/pciio_private.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pci/pciio_private.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
 #define _ASM_SN_PCI_PCIIO_PRIVATE_H
@@ -48,11 +47,6 @@
     devfs_handle_t            pi_dev;	/* associated pci card */
     device_desc_t	    pi_dev_desc;	/* override device descriptor */
     pciio_intr_line_t       pi_lines;	/* which interrupt line(s) */
-    intr_func_t             pi_func;	/* handler function (when connected) */
-    intr_arg_t              pi_arg;	/* handler parameter (when connected) */
-#ifdef LATER
-    thd_int_t               pi_tinfo;	/* Thread info (when connected) */
-#endif
     cpuid_t                 pi_mustruncpu; /* Where we must run. */
     int                     pi_irq;     /* IRQ assigned */
     int                     pi_cpu;     /* cpu assigned */
@@ -84,6 +78,8 @@
 	pciio_space_t		w_space;
 	iopaddr_t		w_base;
 	size_t			w_size;
+        int                     w_devio_index;  /* DevIO[] register used to
+                                                   access this window */
     }			    c_window[6];
 
     unsigned		    c_rbase;	/* EXPANSION ROM base addr */
diff -urN linux-2.4.16/include/asm-ia64/sn/pda.h lia64-2.4/include/asm-ia64/sn/pda.h
--- linux-2.4.16/include/asm-ia64/sn/pda.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/pda.h	Mon Nov 26 18:05:56 2001
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PDA_H
+#define _ASM_IA64_SN_PDA_H
+
+#include <linux/config.h>
+#include <linux/cache.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+
+/*
+ * CPU-specific data structure.
+ *
+ * One of these structures is allocated for each cpu of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all SN per-cpu data structures. 
+ */
+
+
+
+typedef struct pda_s {
+
+	/* Having a pointer in the begining of PDA tends to increase
+	 * the chance of having this pointer in cache. (Yes something
+	 * else gets pushed out). Doing this reduces the number of memory
+	 * access to all nodepda variables to be one
+	 */
+	struct nodepda_s *p_nodepda;		/* Pointer to Per node PDA */
+	struct subnodepda_s *p_subnodepda;	/* Pointer to CPU  subnode PDA */
+
+	/*
+	 * Support for blinking SN LEDs
+	 */
+	long		*led_address;
+	u8		led_state;
+	char		hb_state;	/* supports blinking heartbeat leds */
+	unsigned int	hb_count;
+
+	unsigned int	idle_flag;
+	
+#ifdef CONFIG_IA64_SGI_SN2
+	struct irqpda_s *p_irqpda;			/* Pointer to CPU irq data */
+#endif
+
+} pda_t;
+
+
+#define CACHE_ALIGN(x)	(((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+/*
+ * PDA
+ * Per-cpu private data area for each cpu. The PDA is located immediately after
+ * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
+ * cpu but only a small amout of the page is actually used. We put the SNIA PDA
+ * in the same page as the cpu_data area. Note that there is a check in the setup
+ * code to verify that we dont overflow the page.
+ *
+ * Seems like we should should cache-line align the pda so that any changes in the
+ * size of the cpu_data area dont change cache layout. Should we align to 32, 64, 128
+ * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
+ */
+#define CPU_DATA_END	CACHE_ALIGN((long)&(((struct cpuinfo_ia64*)0)->platform_specific))
+#define PDAADDR		(PERCPU_ADDR+CPU_DATA_END)
+
+#define pda		(*((pda_t *) PDAADDR))
+
+
+#endif /* _ASM_IA64_SN_PDA_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/pio.h lia64-2.4/include/asm-ia64/sn/pio.h
--- linux-2.4.16/include/asm-ia64/sn/pio.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/pio.h	Mon Nov 19 23:22:55 2001
@@ -4,15 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PIO_H
-#define _ASM_SN_PIO_H
+#ifndef _ASM_IA64_SN_PIO_H
+#define _ASM_IA64_SN_PIO_H
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 
 /*
  * pioaddr_t	- The kernel virtual address that a PIO can be done upon.
@@ -156,4 +155,4 @@
 
 #define	PIOMAP_FLAGS	0x7
 
-#endif	/* _ASM_SN_PIO_H */
+#endif	/* _ASM_IA64_SN_PIO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/prio.h lia64-2.4/include/asm-ia64/sn/prio.h
--- linux-2.4.16/include/asm-ia64/sn/prio.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/prio.h	Mon Nov 19 23:22:55 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PRIO_H
-#define _ASM_SN_PRIO_H
+#ifndef _ASM_IA64_SN_PRIO_H
+#define _ASM_IA64_SN_PRIO_H
 
 /*
  * Priority I/O function prototypes and macro definitions
@@ -35,4 +34,4 @@
 #define PRIO_SUCCESS     0
 #define PRIO_FAIL       -1 
 
-#endif /* _ASM_SN_PRIO_H */
+#endif /* _ASM_IA64_SN_PRIO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/router.h lia64-2.4/include/asm-ia64/sn/router.h
--- linux-2.4.16/include/asm-ia64/sn/router.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/router.h	Mon Nov 19 23:22:55 2001
@@ -1,19 +1,664 @@
+
 /* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ROUTER_H
+#define _ASM_IA64_SN_ROUTER_H
+
+/*
+ * Router Register definitions
+ *
+ * Macro argument _L always stands for a link number (1 to 8, inclusive).
+ */
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sn/vector.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/arch.h>
+
+typedef uint64_t	router_reg_t;
+
+#define MAX_ROUTERS	64
+
+#define MAX_ROUTER_PATH	80
+
+#define ROUTER_REG_CAST		(volatile router_reg_t *)
+#define PS_UINT_CAST		(__psunsigned_t)
+#define UINT64_CAST		(uint64_t)
+typedef signed char port_no_t;	 /* Type for router port number      */
+
+#else 
+
+#define ROUTERREG_CAST
+#define PS_UINT_CAST
+#define UINT64_CAST
+
+#endif /* __ASSEMBLY__ */
+
+#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */
+
+#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */
+
+#define PORT_INVALID (-1)	 /* Invalid port number              */
+
+#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)
+
+#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
+
+/*
+ * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
+ * port to generate an output port.
+ *
+ * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
+ * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
+ *
+ * These are written to work on unsigned data.
  */
-#ifndef _ASM_SN_ROUTER_H
-#define _ASM_SN_ROUTER_H
 
-#include <linux/config.h>
+#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
+				 (_L) + (count) - MAX_ROUTER_PORTS :	\
+				 (_L) + (count))
+
+#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
+				 (_LD) - (_LS) :			\
+				 (_LD) + MAX_ROUTER_PORTS - (_LS))
+
+/* Router register addresses */
+
+#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
+#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
+#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
+#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
+#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
+#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
+#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
+#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
+#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
+#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
+#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */
+
+#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */
+
+#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
+#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */
+
+#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */
+
+#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
+/* Port-specific registers (_L is the link number from 1 to 8) */
+
+#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
+#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
+#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
+#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
+#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
+#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
+#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
+#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
+#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
+#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
+#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
+#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
+#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
+
+#define RR_META_ENTRIES		16
+
+#define RR_LOCAL_ENTRIES	128
+
+/*
+ * RR_STATUS_REV_ID mask and shift definitions
+ */
+
+#define RSRI_INPORT_SHFT	52
+#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
+#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
+#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
+#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
+#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
+#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
+#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
+#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
+#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
+#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
+#define RSRI_LOCAL_SHFT 	32
+#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
+#define RSRI_CHIPREV_SHFT	28
+#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
+#define RSRI_CHIPID_SHFT	12
+#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
+#define RSRI_MFGID_SHFT		1
+#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)
+
+#define RSRI_LSTAT_WENTDOWN	0
+#define RSRI_LSTAT_RESETFAIL	1
+#define RSRI_LSTAT_LINKUP	2
+#define RSRI_LSTAT_NOTUSED	3
+
+/*
+ * RR_PORT_RESET mask definitions
+ */
+
+#define RPRESET_WARM		(UINT64_CAST 1 << 9)
+#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
+#define RPRESET_LOCAL		(UINT64_CAST 1)
+
+/*
+ * RR_PROT_CONF mask and shift definitions
+ */
+
+#define RPCONF_DIRCMPDIS_SHFT	13
+#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
+#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
+#define RPCONF_FLOCAL_SHFT	12
+#define RPCONF_METAID_SHFT	8
+#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
+#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))
+
+/*
+ * RR_GLOBAL_PORT_DEF mask and shift definitions
+ */
+
+#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
+#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
+#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
+#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
+#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
+#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
+#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
+#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
+#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
+#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
+#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)
+
+#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */
+
+/*
+ * RR_GLOBAL_PARMS0 mask and shift definitions
+ */
+
+#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
+#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
+#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
+#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
+#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
+#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
+#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
+#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
+#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
+#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
+#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
+#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
+#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
+#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
+#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
+#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
+#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
+#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
+#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
+#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
+#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
+#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
+#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
+#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
+#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
+#define RGPARM0_BYPEN_SHFT	0
+#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */
+
+/*
+ * RR_GLOBAL_PARMS1 shift and mask definitions
+ */
+
+#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
+#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
+#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
+#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
+#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
+#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)
+
+/*
+ * RR_DIAG_PARMS mask and shift definitions
+ */
+
+#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
+#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
+#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
+#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))
+
+/*
+ * RR_DEBUG_ADDR mask and shift definitions
+ */
+
+#define RDA_DATA_SHFT		10	/* Observed debug data */
+#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
+#define RDA_ADDR_SHFT		0	/* debug address for data */
+#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)
+
+/*
+ * RR_LB_TO_L2 mask and shift definitions
+ */
+
+#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
+#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
+#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
+#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_L2_TO_LB mask and shift definitions
+ */
+
+#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
+#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
+#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
+#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
+#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
+#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_JBUS_CONTROL mask and shift definitions
+ */
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#include <asm/sn/sn1/router.h>
+#define RJC_POS_BITS_SHFT	20	/* Router position bits */
+#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
+#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
+#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
+#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
+#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
+#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
+#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)
+
+/*
+ * RR_SCRATCH_REGx mask and shift definitions
+ *  note: these fields represent a software convention, and are not
+ *        understood/interpreted by the hardware. 
+ */
+
+#define	RSCR0_BOOTED_SHFT	63
+#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
+#define RSCR0_LOCALID_SHFT	56
+#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
+#define	RSCR0_UNUSED_SHFT	48
+#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
+#define RSCR0_NIC_SHFT		0
+#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)
+
+#define RSCR1_MODID_SHFT	0
+#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)
+
+/*
+ * RR_VECTOR_HW_BAR mask and shift definitions
+ */
+
+#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
+#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
+#define BAR_VLD_SHFT		26	/* Valid Configuration */
+#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
+#define BAR_SEQ_SHFT		24	/* Sequence number */
+#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
+#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
+#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
+#define BAR_PARENT_SHFT		14	/* Parent Port */
+#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
+#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
+#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
+#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
+#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)
+
+/*
+ * RR_PORT_PARMS(_L) mask and shift definitions
+ */
+
+#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
+#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
+#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
+#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
+#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
+#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)
+#define RPPARM_PORTMATE_SHFT	21	/* Port Mate for the port */
+#define RPPARM_PORTMATE_MASK	(UINT64_CAST 0x7 << 21)
+#define RPPARM_HISTEN_SHFT	20	/* Histogram counter enable */
+#define RPPARM_HISTEN_MASK	(UINT64_CAST 0x1 << 20)
+#define RPPARM_HISTSEL_SHFT	18
+#define RPPARM_HISTSEL_MASK	(UINT64_CAST 0x3 << 18)
+#define RPPARM_DAMQHS_SHFT	16
+#define RPPARM_DAMQHS_MASK	(UINT64_CAST 0x3 << 16)
+#define RPPARM_NULLTO_SHFT	10
+#define RPPARM_NULLTO_MASK	(UINT64_CAST 0x3f << 10)
+#define RPPARM_MAXBURST_SHFT	0
+#define RPPARM_MAXBURST_MASK	(UINT64_CAST 0x3ff)
+
+/*
+ * NOTE: Normally the kernel tracks only UTILIZATION statistics.
+ * The other 2 should not be used, except during any experimentation
+ * with the router.
+ */
+#define RPPARM_HISTSEL_AGE	0	/* Histogram age characterization.  */
+#define RPPARM_HISTSEL_UTIL	1	/* Histogram link utilization 	    */
+#define RPPARM_HISTSEL_DAMQ	2	/* Histogram DAMQ characterization. */
+
+/*
+ * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
+ */
+#define RSERR_POWERNOK		(UINT64_CAST 1 << 38)
+#define RSERR_PORT_DEADLOCK     (UINT64_CAST 1 << 37)
+#define RSERR_WARMRESET         (UINT64_CAST 1 << 36)
+#define RSERR_LINKRESET         (UINT64_CAST 1 << 35)
+#define RSERR_RETRYTIMEOUT      (UINT64_CAST 1 << 34)
+#define RSERR_FIFOOVERFLOW	(UINT64_CAST 1 << 33)
+#define RSERR_ILLEGALPORT	(UINT64_CAST 1 << 32)
+#define RSERR_DEADLOCKTO_SHFT	28
+#define RSERR_DEADLOCKTO_MASK	(UINT64_CAST 0xf << 28)
+#define RSERR_RECVTAILTO_SHFT	24
+#define RSERR_RECVTAILTO_MASK	(UINT64_CAST 0xf << 24)
+#define RSERR_RETRYCNT_SHFT	16
+#define RSERR_RETRYCNT_MASK	(UINT64_CAST 0xff << 16)
+#define RSERR_CBERRCNT_SHFT	8
+#define RSERR_CBERRCNT_MASK	(UINT64_CAST 0xff << 8)
+#define RSERR_SNERRCNT_SHFT	0
+#define RSERR_SNERRCNT_MASK	(UINT64_CAST 0xff << 0)
+
+
+#define PORT_STATUS_UP		(1 << 0)	/* Router link up */
+#define PORT_STATUS_FENCE	(1 << 1)	/* Router link fenced */
+#define PORT_STATUS_RESETFAIL	(1 << 2)	/* Router link didnot 
+						 * come out of reset */
+#define PORT_STATUS_DISCFAIL	(1 << 3)	/* Router link failed after 
+						 * out of reset but before
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_KERNFAIL	(1 << 4)	/* Router link failed
+						 * after reset and the 
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_UNDEF	(1 << 5)	/* Unable to pinpoint
+						 * why the router link
+						 * went down
+						 */	
+#define PROBE_RESULT_BAD	(-1)		/* Set if any of the router
+						 * links failed after reset
+						 */
+#define PROBE_RESULT_GOOD	(0)		/* Set if all the router links
+						 * which came out of reset 
+						 * are up
+						 */
+
+/* Should be enough for 256 CPUs */
+#define MAX_RTR_BREADTH		64		/* Max # of routers possible */
+
+/* Get the require set of bits in a var. corr to a sequence of bits  */
+#define GET_FIELD(var, fname) \
+        ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
+/* Set the require set of bits in a var. corr to a sequence of bits  */
+#define SET_FIELD(var, fname, fval) \
+        ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct router_map_ent_s {
+	uint64_t	nic;
+	moduleid_t	module;
+	slotid_t	slot;
+} router_map_ent_t;
+
+struct rr_status_error_fmt {
+	uint64_t	rserr_unused		: 30,
+			rserr_fifooverflow	: 1,
+			rserr_illegalport	: 1,
+			rserr_deadlockto	: 4,
+			rserr_recvtailto	: 4,
+			rserr_retrycnt		: 8,
+			rserr_cberrcnt		: 8,
+			rserr_snerrcnt		: 8;
+};
+
+/*
+ * This type is used to store "absolute" counts of router events
+ */
+typedef int	router_count_t;
+
+/* All utilizations are on a scale from 0 - 1023. */
+#define RP_BYPASS_UTIL	0
+#define RP_RCV_UTIL	1
+#define RP_SEND_UTIL	2
+#define RP_TOTAL_PKTS	3	/* Free running clock/packet counter */
+
+#define RP_NUM_UTILS	3
+
+#define RP_HIST_REGS	2
+#define RP_NUM_BUCKETS  4
+#define RP_HIST_TYPES	3
+
+#define RP_AGE0		0
+#define RP_AGE1		1
+#define RP_AGE2		2
+#define RP_AGE3		3
+
+
+#define RR_UTIL_SCALE	1024
+
+/*
+ * Router port-oriented information
+ */
+typedef struct router_port_info_s {
+	router_reg_t	rp_histograms[RP_HIST_REGS];/* Port usage info */
+	router_reg_t	rp_port_error;		/* Port error info */
+	router_count_t	rp_retry_errors;	/* Total retry errors */
+	router_count_t	rp_sn_errors;		/* Total sn errors */
+	router_count_t	rp_cb_errors;		/* Total cb errors */
+	int		rp_overflows;		/* Total count overflows */
+	int		rp_excess_err;		/* Port has excessive errors */
+	ushort		rp_util[RP_NUM_BUCKETS];/* Port utilization */
+} router_port_info_t;
+
+#define ROUTER_INFO_VERSION	7
+
+struct lboard_s;
+
+/*
+ * Router information
+ */
+typedef struct router_info_s {
+	char		ri_version;	/* structure version		    */
+	cnodeid_t	ri_cnode;	/* cnode of its legal guardian hub  */
+	nasid_t		ri_nasid;	/* Nasid of same 		    */
+	char		ri_ledcache;	/* Last LED bitmap		    */
+	char		ri_leds;	/* Current LED bitmap		    */
+	char		ri_portmask;	/* Active port bitmap		    */
+	router_reg_t	ri_stat_rev_id;	/* Status rev ID value		    */
+	net_vec_t	ri_vector;	/* vector from guardian to router   */
+	int		ri_writeid;	/* router's vector write ID	    */
+	int64_t	ri_timebase;	/* Time of first sample		    */
+	int64_t	ri_timestamp;	/* Time of last sample		    */
+	router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info      */
+	moduleid_t	ri_module;	/* Which module are we in?	    */
+	slotid_t	ri_slotnum;	/* Which slot are we in?	    */
+	router_reg_t	ri_glbl_parms[GLBL_PARMS_REGS];
+					/* Global parms0&1 register contents*/
+	devfs_handle_t	ri_vertex;	/* hardware graph vertex            */
+	router_reg_t	ri_prot_conf;	/* protection config. register	    */
+	int64_t	ri_per_minute;	/* Ticks per minute		    */
+
+	/*
+	 * Everything below here is for kernel use only and may change at	
+	 * at any time with or without a change in teh revision number
+	 *
+	 * Any pointers or things that come and go with DEBUG must go at
+ 	 * the bottom of the structure, below the user stuff.
+	 */
+	char		ri_hist_type;   /* histogram type		    */
+	devfs_handle_t	ri_guardian;	/* guardian node for the router	    */
+	int64_t	ri_last_print;	/* When did we last print	    */
+	char		ri_print;	/* Should we print 		    */
+	char 		ri_just_blink;	/* Should we blink the LEDs         */
+	
+#ifdef DEBUG
+	int64_t	ri_deltatime;	/* Time it took to sample	    */
 #endif
+	spinlock_t	ri_lock;	/* Lock for access to router info   */
+	net_vec_t	*ri_vecarray;	/* Pointer to array of vectors	    */
+	struct lboard_s	*ri_brd;	/* Pointer to board structure	    */
+	char *		ri_name;	/* This board's hwg path 	    */
+        unsigned char	ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a 
+					message to availmon */
+} router_info_t;
+
+
+/* Router info location specifiers */
+
+#define RIP_PROMLOG			2	/* Router info in promlog */
+#define RIP_CONSOLE			4	/* Router info on console */
+
+#define ROUTER_INFO_PRINT(_rip,_where)	(_rip->ri_print |= _where)	
+					/* Set the field used to check if a 
+					 * router info can be printed
+					 */
+#define IS_ROUTER_INFO_PRINTED(_rip,_where)	\
+					(_rip->ri_print & _where)	
+					/* Was the router info printed to
+					 * the given location (_where) ?
+					 * Mainly used to prevent duplicate
+					 * router error states.
+					 */
+#define ROUTER_INFO_LOCK(_rip,_s)	_s = mutex_spinlock(&(_rip->ri_lock))
+					/* Take the lock on router info
+					 * to gain exclusive access
+					 */
+#define ROUTER_INFO_UNLOCK(_rip,_s)	mutex_spinunlock(&(_rip->ri_lock),_s)
+					/* Release the lock on router info */
+/* 
+ * Router info hanging in the nodepda 
+ */
+typedef struct nodepda_router_info_s {
+	devfs_handle_t 	router_vhdl;	/* vertex handle of the router 	    */
+	short		router_port;	/* port thru which we entered       */
+	short		router_portmask;
+	moduleid_t	router_module;	/* module in which router is there  */
+	slotid_t	router_slot;	/* router slot			    */
+	unsigned char	router_type;	/* kind of router 		    */
+	net_vec_t	router_vector;	/* vector from the guardian node    */
+
+	router_info_t	*router_infop;	/* info hanging off the hwg vertex  */
+	struct nodepda_router_info_s *router_next;
+	                                /* pointer to next element 	    */
+} nodepda_router_info_t;
+
+#define ROUTER_NAME_SIZE	20	/* Max size of a router name */
+
+#define NORMAL_ROUTER_NAME	"normal_router"
+#define NULL_ROUTER_NAME	"null_router"
+#define META_ROUTER_NAME	"meta_router"
+#define REPEATER_ROUTER_NAME	"repeater_router"
+#define UNKNOWN_ROUTER_NAME	"unknown_router" 
+
+/* The following definitions are needed by the router traversing
+ * code either using the hardware graph or using vector operations.
+ */
+/* Structure of the router queue element */
+typedef struct router_elt_s {
+	union {
+		/* queue element structure during router probing */
+		struct {
+			/* number-in-a-can (unique) for the router */
+			nic_t		nic;	
+			/* vector route from the master hub to 
+			 * this router.
+			 */
+			net_vec_t	vec;	
+			/* port status */
+			uint64_t	status;	
+			char		port_status[MAX_ROUTER_PORTS + 1];
+		} r_elt;
+		/* queue element structure during router guardian 
+		 * assignment
+		 */
+		struct {
+			/* vertex handle for the router */
+			devfs_handle_t	vhdl;
+			/* guardian for this router */
+			devfs_handle_t	guard;	
+			/* vector router from the guardian to the router */
+			net_vec_t	vec;
+		} k_elt;
+	} u;
+	                        /* easy to use port status interpretation */
+} router_elt_t;
+
+/* structure of the router queue */
+
+typedef struct router_queue_s {
+	char		head;	/* Point where a queue element is inserted */
+	char		tail;	/* Point where a queue element is removed */
+	int		type;
+	router_elt_t	array[MAX_RTR_BREADTH];
+	                        /* Entries for queue elements */
+} router_queue_t;
+
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * RR_HISTOGRAM(_L) mask and shift definitions
+ * There are two 64 bit histogram registers, so the following macros take
+ * into account dealing with an array of 4 32 bit values indexed by _x
+ */
+
+#define RHIST_BUCKET_SHFT(_x)	(32 * ((_x) & 0x1))
+#define RHIST_BUCKET_MASK(_x)	(UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1))
+#define RHIST_GET_BUCKET(_x, _reg)	\
+	((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
+
+/*
+ * RR_RESET_MASK(_L) mask and shift definitions
+ */
+
+#define RRM_RESETOK(_L)		(UINT64_CAST 1 << ((_L) - 1))
+#define RRM_RESETOK_ALL		ALL_PORTS
+
+/*
+ * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
+ */
+
+#define RTABLE_SHFT(_L)		(4 * ((_L) - 1))
+#define RTABLE_MASK(_L)		(UINT64_CAST 0x7 << RTABLE_SHFT(_L))
+
+
+#define	ROUTERINFO_STKSZ	4096
+
+#ifndef __ASSEMBLY__
+
+int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
+int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
+int router_get_info(devfs_handle_t routerv, router_info_t *, int);
+int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip);
+int router_set_leds(router_info_t *rip);
+void router_print_state(router_info_t *rip, int level,
+		   void (*pf)(int, char *, ...),int print_where);
+void capture_router_stats(router_info_t *rip);
+
+
+int 	probe_routers(void);
+void 	get_routername(unsigned char brd_type,char *rtrname);
+void 	router_guardians_set(devfs_handle_t hwgraph_root);
+int 	router_hist_reselect(router_info_t *, int64_t);
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_ROUTER_H */
+#endif /* _ASM_IA64_SN_ROUTER_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sgi.h lia64-2.4/include/asm-ia64/sn/sgi.h
--- linux-2.4.16/include/asm-ia64/sn/sgi.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sgi.h	Mon Nov 19 23:22:55 2001
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
-#ifndef _ASM_SN_SGI_H
-#define _ASM_SN_SGI_H
+#ifndef _ASM_IA64_SN_SGI_H
+#define _ASM_IA64_SN_SGI_H
 
 #include <linux/config.h>
 
@@ -95,9 +94,6 @@
 				 bigger. This is NULL-terminated  */
 };
 
-#define MIN(_a,_b)		((_a)<(_b)?(_a):(_b))
-
-typedef uint32_t app32_ptr_t;	/* needed by edt.h */
 typedef int64_t  __psint_t;	/* needed by klgraph.c */
 
 typedef enum { B_FALSE, B_TRUE } boolean_t;
@@ -129,10 +125,6 @@
 					 * calls */
 #define XG_WIDGET_PART_NUM      0xC102          /* KONA/xt_regs.h     XG_XT_PART_NUM_VALUE */
 
-#ifndef TO_PHYS_MASK
-#define TO_PHYS_MASK 0x0000000fffffffff
-#endif
-
 typedef uint64_t vhandl_t;
 
 
@@ -225,9 +217,6 @@
         } } while(0)
 #endif	/* DISABLE_ASSERT */
 
-#define PRINT_WARNING(x...)	do { printk("WARNING : "); printk(x); } while(0)
-#define PRINT_NOTICE(x...)	do { printk("NOTICE : "); printk(x); } while(0)
-#define PRINT_ALERT(x...)	do { printk("ALERT : "); printk(x); } while(0)
 #define PRINT_PANIC		panic
 
 #ifdef CONFIG_SMP
@@ -238,4 +227,4 @@
 
 #include <asm/sn/hack.h>	/* for now */
 
-#endif	/* _ASM_SN_SGI_H */
+#endif /* _ASM_IA64_SN_SGI_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/simulator.h lia64-2.4/include/asm-ia64/sn/simulator.h
--- linux-2.4.16/include/asm-ia64/sn/simulator.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/simulator.h	Mon Nov 19 23:22:55 2001
@@ -0,0 +1,27 @@
+#ifndef _ASM_IA64_SN_SIMULATOR_H
+#define _ASM_IA64_SN_SIMULATOR_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+
+#define SNMAGIC 0xaeeeeeee8badbeefL
+#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
+
+#define SIMULATOR_SLEEP()	asm("nop.i 0x8beef")
+
+#else
+
+#define IS_RUNNING_ON_SIMULATOR()	(0)
+#define SIMULATOR_SLEEP()
+
+#endif
+
+#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/slotnum.h lia64-2.4/include/asm-ia64/sn/slotnum.h
--- linux-2.4.16/include/asm-ia64/sn/slotnum.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/slotnum.h	Mon Nov 19 23:22:55 2001
@@ -4,22 +4,23 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SLOTNUM_H
-#define _ASM_SN_SLOTNUM_H
+#ifndef _ASM_IA64_SN_SLOTNUM_H
+#define _ASM_IA64_SN_SLOTNUM_H
 
 #include <linux/config.h>
 
 typedef	unsigned char slotid_t;
 
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined (CONFIG_IA64_SGI_SN1)
 #include <asm/sn/sn1/slotnum.h>
+#elif defined (CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/slotnum.h>
 #else
 
 #error <<BOMB! slotnum defined only for SN0 and SN1 >>
 
-#endif /* !CONFIG_SGI_IP35 && !CONFIG_IA64_SGI_SN1 */
+#endif /* !CONFIG_IA64_SGI_SN1 */
 
-#endif /* _ASM_SN_SLOTNUM_H */
+#endif /* _ASM_IA64_SN_SLOTNUM_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/addrs.h lia64-2.4/include/asm-ia64/sn/sn1/addrs.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/addrs.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/addrs.h	Mon Nov 26 18:05:56 2001
@@ -4,19 +4,21 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_ADDRS_H
-#define _ASM_SN_SN1_ADDRS_H
+#ifndef _ASM_IA64_SN_SN1_ADDRS_H
+#define _ASM_IA64_SN_SN1_ADDRS_H
 
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN1
 /*
- * IP35 (on a TRex) Address map
+ * SN1 (on a TRex) Address map
  *
  * This file contains a set of definitions and macros which are used
  * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
- * and UNCAC) used by the IP35 architecture.  It also contains addresses
+ * and UNCAC) used by the SN1 architecture.  It also contains addresses
  * for "major" statically locatable PROM/Kernel data structures, such as
  * the partition table, the configuration data structure, etc.
  * We make an implicit assumption that the processor using this file
@@ -40,22 +42,14 @@
  * use some new ANSI preprocessor stuff to paste these on where needed.
  */
 
-#if defined(_RUN_UNCACHED)
-#define CAC_BASE		0x9600000000000000
-#else
-#ifndef __ia64
-#define CAC_BASE		0xa800000000000000
-#else
 #define CAC_BASE                0xe000000000000000
-#endif
-#endif
-
 #define HSPEC_BASE              0xc0000b0000000000
 #define HSPEC_SWIZ_BASE         0xc000030000000000
 #define IO_BASE                 0xc0000a0000000000
 #define IO_SWIZ_BASE            0xc000020000000000
-#define MSPEC_BASE              0xc000000000000000
+#define MSPEC_BASE              0xc000090000000000
 #define UNCAC_BASE              0xc000000000000000
+#define TO_PHYS_MASK		0x000000ffffffffff
 
 #define TO_PHYS(x)		(	      ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
@@ -109,18 +103,14 @@
 #define NASID_GET(_pa)		(int) ((UINT64_CAST (_pa) >>		\
 					NASID_SHFT) & NASID_BITMASK)
 
-#if _LANGUAGE_C && !defined(_STANDALONE)
-#ifndef REAL_HARDWARE
-#define NODE_SWIN_BASE(nasid, widget) RAW_NODE_SWIN_BASE(nasid, widget)
-#else
+#ifndef __ASSEMBLY__
 #define NODE_SWIN_BASE(nasid, widget)					\
 	((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)		\
 	: RAW_NODE_SWIN_BASE(nasid, widget))
-#endif
 #else
 #define NODE_SWIN_BASE(nasid, widget) \
      (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /*
  * The following definitions pertain to the IO special address
@@ -155,7 +145,7 @@
 
 /*
  * The following define the major position-independent aliases used
- * in IP27.
+ * in SN1.
  *	CALIAS -- Varies in size, points to the first n bytes of memory
  *		  	on the reader's node.
  */
@@ -169,11 +159,6 @@
 
 #define SN0_WIDGET_BASE(_nasid, _wid)	(NODE_SWIN_BASE((_nasid), (_wid)))
 
-#if _LANGUAGE_C
-#define KERN_NMI_ADDR(nasid, slice)					\
-                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + 	\
-				  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
-#endif /* _LANGUAGE_C */
 
 
 /*
@@ -197,7 +182,7 @@
 #define KL_UART_CMD	LOCAL_HSPEC(HSPEC_UART_0)	/* UART command reg */
 #define KL_UART_DATA	LOCAL_HSPEC(HSPEC_UART_1)	/* UART data reg */
 
-#if !_LANGUAGE_ASSEMBLY
+#if !__ASSEMBLY__
 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
  * CACHE_ERR_SP_PTR could either contain an address to the stack, or
  * the stack could start at CACHE_ERR_SP_PTR
@@ -210,28 +195,9 @@
 #define CACHE_ERR_SP		(CACHE_ERR_SP_PTR - 16)
 #define CACHE_ERR_AREA_SIZE	(ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
 
-#endif	/* !_LANGUAGE_ASSEMBLY */
+#endif	/* !__ASSEMBLY__ */
+
 
-/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries
- * This determines the locations of the exception vectors
- */
-#define UALIAS_FLIP_BASE	UALIAS_BASE
-#define UALIAS_FLIP_SHIFT	15
-#define UALIAS_FLIP_ADDR(_x)	((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT))
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT)
-#endif
-#define EX_HANDLER_ADDR(nasid, slice)					\
-	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
-#define EX_HANDLER_SIZE		0x0400
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#define EX_FRAME_OFFSET(slice)	((slice) << UALIAS_FLIP_SHIFT | 0x400)
-#endif
-#define EX_FRAME_ADDR(nasid, slice)					\
-	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
-#define EX_FRAME_SIZE		0x0c00
 
 #define _ARCSPROM
 
@@ -241,7 +207,7 @@
  * The PROM needs to pass the device base address and the
  * device pci cfg space address to the device drivers during
  * install. The COMPONENT->Key field is used for this purpose.
- * Macros needed by IP27 device drivers to convert the
+ * Macros needed by SN1 device drivers to convert the
  * COMPONENT->Key field to the respective base address.
  * Key field looks as follows:
  *
@@ -256,7 +222,7 @@
  * is in place.
  */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define uchar unsigned char
 
@@ -301,8 +267,9 @@
 #define PUT_INSTALL_STATUS(c,s)		c->Revision = s
 #define GET_INSTALL_STATUS(c)		c->Revision
 
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 #endif /* _STANDALONE */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#endif /* _ASM_SN_SN1_ADDRS_H */
+#endif /* _ASM_IA64_SN_SN1_ADDRS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/arch.h lia64-2.4/include/asm-ia64/sn/sn1/arch.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/arch.h	Thu Jan  4 15:25:55 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/arch.h	Mon Nov 19 23:22:55 2001
@@ -4,29 +4,29 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_ARCH_H
-#define _ASM_SN_SN1_ARCH_H
+#ifndef _ASM_IA64_SN_SN1_ARCH_H
+#define _ASM_IA64_SN_SN1_ARCH_H
 
 #if defined(N_MODE)
 #error "ERROR constants defined only for M-mode"
 #endif
 
+#include <linux/threads.h>
+#include <asm/types.h>
+
+#define CPUS_PER_NODE           4       /* CPUs on a single hub */
+#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
+
 /*
  * This is the maximum number of NASIDS that can be present in a system.
+ * This include ALL nodes in ALL partitions connected via NUMALINK.
  * (Highest NASID plus one.)
  */
 #define MAX_NASIDS              128
 
 /*
- * MAXCPUS refers to the maximum number of CPUs in a single kernel.
- * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
- */
-#define MAXCPUS                 512
-
-/*
  * This is the maximum number of nodes that can be part of a kernel.
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  * This is not necessarily the same as MAX_NASIDS.
@@ -40,6 +40,19 @@
 #define MAX_NONPREMIUM_REGIONS  16
 #define MAX_PREMIUM_REGIONS     MAX_REGIONS
 
+/*
+ * Slot constants for IP35
+ */
+
+#define MAX_MEM_SLOTS    8                     /* max slots per node */
+
+#if defined(N_MODE)
+#error "N-mode not supported"
+#endif
+
+#define SLOT_SHIFT              (30)
+#define SLOT_MIN_MEM_SIZE       (64*1024*1024)
+
 
 /*
  * MAX_PARITIONS refers to the maximum number of logically defined 
@@ -51,17 +64,14 @@
 #define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
 
 /*
- * Slot constants for IP35
+ * New stuff in here from Irix sys/pfdat.h.
  */
+#define SLOT_PFNSHIFT           (SLOT_SHIFT - PAGE_SHIFT)
+#define PFN_NASIDSHFT           (NASID_SHFT - PAGE_SHIFT)
+#define slot_getbasepfn(node,slot)  (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT))
+#define mkpfn(nasid, off)       (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off))
 
-#define MAX_MEM_SLOTS    8                     /* max slots per node */
-
-#if defined(N_MODE)
-#error "N-mode not supported"
-#endif
 
-#define SLOT_SHIFT      	(30)
-#define SLOT_MIN_MEM_SIZE	(64*1024*1024)
 
 /*
  * two PIs per bedrock, two CPUs per PI
@@ -76,4 +86,4 @@
 #define TO_SLICE(subn, local)	(((subn) << SUBNODE_SHFT) | \
 				 ((local) << LOCALCPU_SHFT))
 
-#endif /* _ASM_SN_SN1_ARCH_H */
+#endif /* _ASM_IA64_SN_SN1_ARCH_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/bedrock.h lia64-2.4/include/asm-ia64/sn/sn1/bedrock.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/bedrock.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/bedrock.h	Mon Nov 19 23:22:55 2001
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_BEDROCK_H
-#define _ASM_SN_SN1_BEDROCK_H
+#ifndef _ASM_IA64_SN_SN1_BEDROCK_H
+#define _ASM_IA64_SN_SN1_BEDROCK_H
 
 #include <linux/config.h>
 
@@ -24,7 +23,6 @@
 
 #define MAX_HUB_PATH		80
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/arch.h>
 #include <asm/sn/sn1/addrs.h>
 #include <asm/sn/sn1/hubpi.h>
@@ -40,19 +38,13 @@
 #include <asm/sn/sn1/hublb_next.h>
 #include <asm/sn/sn1/hubxb_next.h>
 
-#else /* ! CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
-<< BOMB! CONFIG_SGI_IP35 is only defined for IP35 >>
-
-#endif /* defined(CONFIG_SGI_IP35) */
-
 /* Translation of uncached attributes */
 #define	UATTR_HSPEC	0
 #define	UATTR_IO	1
 #define	UATTR_MSPEC	2
 #define	UATTR_UNCAC	3
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 
 /*
  * Get nasid into register, r (uses at)
@@ -63,9 +55,9 @@
 	and	r, LRI_NODEID_MASK;			\
 	dsrl	r, LRI_NODEID_SHFT
 
-#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #include <asm/sn/xtalk/xwidget.h>
 
@@ -78,6 +70,6 @@
 void capture_hub_stats(cnodeid_t, struct nodepda_s *);
 void init_hub_stats(cnodeid_t, struct nodepda_s *);
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_SN1_BEDROCK_H */
+#endif /* _ASM_IA64_SN_SN1_BEDROCK_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubdev.h lia64-2.4/include/asm-ia64/sn/sn1/hubdev.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubdev.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubdev.h	Mon Nov 19 23:22:55 2001
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_HUBDEV_H
-#define _ASM_SN_SN1_HUBDEV_H
+#ifndef _ASM_IA64_SN_SN1_HUBDEV_H
+#define _ASM_IA64_SN_SN1_HUBDEV_H
 
 extern void hubdev_init(void);
 extern void hubdev_register(int (*attach_method)(devfs_handle_t));
@@ -19,4 +18,4 @@
 extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
 extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
 
-#endif /* _ASM_SN_SN1_HUBDEV_H */
+#endif /* _ASM_IA64_SN_SN1_HUBDEV_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubio.h lia64-2.4/include/asm-ia64/sn/sn1/hubio.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubio.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubio.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /************************************************************************
@@ -20,8 +19,8 @@
  ************************************************************************/
 
 
-#ifndef _ASM_SN_SN1_HUBIO_H
-#define _ASM_SN_SN1_HUBIO_H
+#ifndef _ASM_IA64_SN_SN1_HUBIO_H
+#define _ASM_IA64_SN_SN1_HUBIO_H
 
 
 #define    IIO_WID                   0x00400000    /*
@@ -762,7 +761,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -2942,15 +2941,15 @@
 typedef union ii_ilct_u {
 	bdrkreg_t	ii_ilct_regval;
 	struct  {
-		bdrkreg_t	i_rsvd                    :	 9;
-		bdrkreg_t	i_test_err_capture        :	 1;
-		bdrkreg_t	i_test_clear              :	 1;
-		bdrkreg_t	i_test_flit               :	 3;
-		bdrkreg_t	i_test_cberr              :	 1;
-		bdrkreg_t	i_test_valid              :	 1;
-		bdrkreg_t	i_test_data               :	20;
-		bdrkreg_t	i_test_mask               :	 8;
-		bdrkreg_t	i_test_seed               :	20;
+		bdrkreg_t	i_test_seed		  :	20;
+		bdrkreg_t	i_test_mask		  :	 8;
+		bdrkreg_t	i_test_data		  :	20;
+		bdrkreg_t	i_test_valid		  :	 1;
+		bdrkreg_t	i_test_cberr		  :	 1;
+		bdrkreg_t	i_test_flit		  :	 3;
+		bdrkreg_t	i_test_clear		  :	 1;
+		bdrkreg_t	i_test_err_capture	  :	 1;
+		bdrkreg_t	i_rsvd			  :	 9;
 	} ii_ilct_fld_s;
 } ii_ilct_u_t;
 
@@ -4935,7 +4934,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -5014,4 +5013,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBIO_H */
+#endif /* _ASM_IA64_SN_SN1_HUBIO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubio_next.h lia64-2.4/include/asm-ia64/sn/sn1/hubio_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubio_next.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubio_next.h	Mon Nov 19 23:22:55 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBIO_NEXT_H
-#define _ASM_SN_SN1_HUBIO_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBIO_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBIO_NEXT_H
 
 /*
  * Slightly friendlier names for some common registers.
@@ -78,11 +77,16 @@
 /* names used in hub_diags.c; carried over from SN0 */
 #define IIO_BASE_BTE0   IIO_IBLS_0		
 #define IIO_BASE_BTE1   IIO_IBLS_1		
-#if 0
-#define IIO_BASE        IIO_WID
-#define IIO_BASE_PERF   IIO_IPCR   /* IO Performance Control */
-#define IIO_PERF_CNT    IIO_IPPR   /* IO Performance Profiling */
-#endif
+
+/*
+ * Macro which takes the widget number, and returns the 
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range 
+ * 0, 8 - 0xF
+ */
+#define	IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+			(_x) : \
+			(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
 
 /* GFX Flow Control Node/Widget Register */
@@ -343,7 +347,7 @@
  * CRBs.
  */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /*
  * Easy access macros for CRBs, all 4 registers (A-D)
@@ -389,7 +393,7 @@
 #define icrbd_context   ii_icrb0_d_fld_s.id_context
 #define d_regvalue	ii_icrb0_d_regval
 
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /* Number of widgets supported by hub */
 #define HUB_NUM_WIDGET          9
@@ -399,7 +403,7 @@
 #define HUB_WIDGET_PART_NUM     0xc110
 #define MAX_HUBS_PER_XBOW       2
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* A few more #defines for backwards compatibility */
 #define iprb_t          ii_iprb0_u_t
 #define iprb_regval     ii_iprb0_regval
@@ -430,11 +434,11 @@
 #define IO_PERF_SETS	32
 
 #if __KERNEL__
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */
 #include <asm/sn/alenlist.h>
 #include <asm/sn/dmamap.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/xtalk/xtalk.h>
 
 /* Bit for the widget in inbound access register */
@@ -699,12 +703,9 @@
 
 extern int
 hub_intr_connect(       hub_intr_t intr_hdl,    /* xtalk intr resource hndl */
-                        intr_func_t intr_func,  /* xtalk intr handler */
-                        void *intr_arg,         /* arg to intr handler */
                         xtalk_intr_setfunc_t setfunc,
                                                 /* func to set intr hw */
-                        void *setfunc_arg,      /* arg to setfunc */
-                        void *thread);          /* intr thread to use */
+                        void *setfunc_arg);     /* arg to setfunc */
 
 extern void
 hub_intr_disconnect(hub_intr_t intr_hdl);
@@ -756,6 +757,6 @@
 extern void hub_widgetdev_shutdown(devfs_handle_t, int);
 extern int  hub_dma_enabled(devfs_handle_t);
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 #endif /* _KERNEL */
-#endif  /* _ASM_SN_SN1_HUBIO_NEXT_H */
+#endif  /* _ASM_IA64_SN_SN1_HUBIO_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hublb.h lia64-2.4/include/asm-ia64/sn/sn1/hublb.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hublb.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hublb.h	Mon Nov 19 23:22:55 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /************************************************************************
@@ -20,8 +19,8 @@
  ************************************************************************/
 
 
-#ifndef _ASM_SN_SN1_HUBLB_H
-#define _ASM_SN_SN1_HUBLB_H
+#ifndef _ASM_IA64_SN_SN1_HUBLB_H
+#define _ASM_IA64_SN_SN1_HUBLB_H
 
 
 #define    LB_REV_ID                 0x00600000    /*
@@ -251,7 +250,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1593,7 +1592,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1605,4 +1604,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBLB_H */
+#endif /* _ASM_IA64_SN_SN1_HUBLB_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hublb_next.h lia64-2.4/include/asm-ia64/sn/sn1/hublb_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hublb_next.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hublb_next.h	Mon Nov 19 23:22:55 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBLB_NEXT_H
-#define _ASM_SN_SN1_HUBLB_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBLB_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBLB_NEXT_H
 
 /**********************************************************************
 
@@ -107,4 +106,4 @@
 #define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
 #define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
 
-#endif	/* _ASM_SN_SN1_HUBLB_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBLB_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubmd.h lia64-2.4/include/asm-ia64/sn/sn1/hubmd.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubmd.h	Tue Mar  6 19:44:34 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubmd.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBMD_H
-#define _ASM_SN_SN1_HUBMD_H
+#ifndef _ASM_IA64_SN_SN1_HUBMD_H
+#define _ASM_IA64_SN_SN1_HUBMD_H
 
 
 /************************************************************************
@@ -315,7 +314,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -2140,7 +2139,7 @@
  * corresponds to the valid bit, and bit 1 of each two-bit field        *
  * corresponds to the overrun bit.                                      *
  * The rule for the valid bit is that it gets set whenever that error   *
- * occurs, regardless of whether a higher priority error has occurred.   *
+ * occurs, regardless of whether a higher priority error has occurred.  *
  * The rule for the overrun bit is that it gets set whenever we are     *
  * unable to record the address information for this particular         *
  * error, due to a previous error of the same or higher priority.       *
@@ -2463,7 +2462,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -2474,4 +2473,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBMD_H */
+#endif /* _ASM_IA64_SN_SN1_HUBMD_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubmd_next.h lia64-2.4/include/asm-ia64/sn/sn1/hubmd_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubmd_next.h	Tue Mar  6 19:44:34 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubmd_next.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBMD_NEXT_H
-#define _ASM_SN_SN1_HUBMD_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H
 
 #ifdef BRINGUP
 /* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */
@@ -147,7 +146,7 @@
 #define MD_SPROT_REFCNT_GET(value) ( \
         ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 #ifdef LITTLE_ENDIAN
 
 typedef union md_perf_sel {
@@ -171,7 +170,7 @@
 } md_perf_sel_t;
 
 #endif
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 #endif /* BRINGUP */
 
@@ -300,7 +299,7 @@
 
 ***********************************************************************/
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* Standard Directory Entries */
 
@@ -533,7 +532,7 @@
 	struct	md_pdir_sparse_fmt	pds_fmt;
 } md_pdir_t;
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 /**********************************************************************
@@ -568,7 +567,7 @@
 #define MD_DIR_WAIT		(UINT64_CAST 0x6)	/* ptr format, hw-defined */
 #define MD_DIR_POISONED		(UINT64_CAST 0x7)	/* ptr format, hw-defined */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* Convert format and state fields into a single "cacheline state" value, defined above */
 
@@ -578,7 +577,7 @@
    MD_DIR_SHARED)
 #define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x))
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 
@@ -812,4 +811,4 @@
 
 #define MFC_ADDR_SHFT		6
 
-#endif  /* _ASM_SN_SN1_HUBMD_NEXT_H */
+#endif  /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubni.h lia64-2.4/include/asm-ia64/sn/sn1/hubni.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubni.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubni.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBNI_H
-#define _ASM_SN_SN1_HUBNI_H
+#ifndef _ASM_IA64_SN_SN1_HUBNI_H
+#define _ASM_IA64_SN_SN1_HUBNI_H
 
 
 /************************************************************************
@@ -1000,7 +999,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1615,7 +1614,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1779,4 +1778,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBNI_H */
+#endif /* _ASM_IA64_SN_SN1_HUBNI_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubni_next.h lia64-2.4/include/asm-ia64/sn/sn1/hubni_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubni_next.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubni_next.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBNI_NEXT_H
-#define _ASM_SN_SN1_HUBNI_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBNI_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBNI_NEXT_H
 
 #define NI_LOCAL_ENTRIES        128
 #define NI_META_ENTRIES        1
@@ -67,7 +66,7 @@
 				 NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\
 				 NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK)
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* NI_PORT_HEADER[AB] registers (not automatically generated) */
 
 #ifdef LITTLE_ENDIAN
@@ -172,4 +171,4 @@
 				 0x6 << NPP_NULL_TIMEOUT_SHFT | \
 				 0x3f0 << NPP_MAX_BURST_SHFT)
 
-#endif  /* _ASM_SN_SN1_HUBNI_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBNI_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubpi.h lia64-2.4/include/asm-ia64/sn/sn1/hubpi.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubpi.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubpi.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBPI_H
-#define _ASM_SN_SN1_HUBPI_H
+#ifndef _ASM_IA64_SN_SN1_HUBPI_H
+#define _ASM_IA64_SN_SN1_HUBPI_H
 
 /************************************************************************
  *                                                                      *
@@ -551,7 +550,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -4248,7 +4247,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -4261,4 +4260,4 @@
 #define PI_GFX_PAGE_ENABLE	0x0000010000000000LL
 
 
-#endif /* _ASM_SN_SN1_HUBPI_H */
+#endif /* _ASM_IA64_SN_SN1_HUBPI_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubpi_next.h lia64-2.4/include/asm-ia64/sn/sn1/hubpi_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubpi_next.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubpi_next.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBPI_NEXT_H
-#define _ASM_SN_SN1_HUBPI_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBPI_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBPI_NEXT_H
 
 
 /* define for remote PI_1 space. It is always half of a node_addressspace
@@ -54,7 +53,7 @@
     ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \
      ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1)
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /*
  * format of error stack and error status registers.
  */
@@ -329,4 +328,4 @@
 /* Error stack address shift, for use with pi_stk_fmt.sk_addr */
 #define ERR_STK_ADDR_SHFT	3
 
-#endif /* _ASM_SN_SN1_HUBPI_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBPI_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubspc.h lia64-2.4/include/asm-ia64/sn/sn1/hubspc.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubspc.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubspc.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,24 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_HUBSPC_H
+#define _ASM_IA64_SN_SN1_HUBSPC_H
+
+typedef enum {
+        HUBSPC_REFCOUNTERS,
+	HUBSPC_PROM
+} hubspc_subdevice_t;
+
+
+/*
+ * Reference Counters
+ */
+
+extern int refcounters_attach(devfs_handle_t hub);
+
+#endif /* _ASM_IA64_SN_SN1_HUBSPC_H */        
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubstat.h lia64-2.4/include/asm-ia64/sn/sn1/hubstat.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubstat.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubstat.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 - 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN1_HUBSTAT_H
+#define _ASM_IA64_SN_SN1_HUBSTAT_H
+
+typedef int64_t 	hub_count_t;
+
+#define HUBSTAT_VERSION	1
+
+typedef struct hubstat_s {
+        char            hs_version;		/* structure version    */
+        cnodeid_t       hs_cnode;       	/* cnode of this hub    */
+        nasid_t         hs_nasid;       	/* Nasid of same        */	
+	int64_t		hs_timebase;		/* Time of first sample */
+	int64_t		hs_timestamp;		/* Time of last sample	*/
+	int64_t		hs_per_minute;		/* Ticks per minute 	*/
+
+	union {
+		hubreg_t	hs_niu_stat_rev_id; /* SN0: Status rev ID */
+		hubreg_t	hs_niu_port_status; /* SN1: Port status */
+	} hs_niu;
+
+        hub_count_t	hs_ni_retry_errors;	/* Total retry errors   */
+        hub_count_t	hs_ni_sn_errors;	/* Total sn errors      */
+        hub_count_t	hs_ni_cb_errors;	/* Total cb errors      */
+        int		hs_ni_overflows;	/* NI count overflows   */
+        hub_count_t	hs_ii_sn_errors;	/* Total sn errors      */
+        hub_count_t	hs_ii_cb_errors;	/* Total cb errors      */
+        int		hs_ii_overflows;	/* II count overflows   */
+
+	/*
+	 * Anything below this comment is intended for kernel internal-use
+	 * only and may be changed at any time.
+	 *
+	 * Any members that contain pointers or are conditionally compiled
+	 * need to be below here also.
+	 */
+        int64_t		hs_last_print;		/* When we last printed */
+        char		hs_print;		/* Should we print      */
+
+	char	       *hs_name;		/* This hub's name */
+	unsigned char	hs_maint;		/* Should we print to availmon */
+} hubstat_t;
+
+#define       hs_ni_stat_rev_id       hs_niu.hs_niu_stat_rev_id
+#define       hs_ni_port_status       hs_niu.hs_niu_port_status
+
+extern struct file_operations hub_mon_fops;
+
+#endif /* _ASM_IA64_SN_SN1_HUBSTAT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubxb.h lia64-2.4/include/asm-ia64/sn/sn1/hubxb.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubxb.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubxb.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBXB_H
-#define _ASM_SN_SN1_HUBXB_H
+#ifndef _ASM_IA64_SN_SN1_HUBXB_H
+#define _ASM_IA64_SN_SN1_HUBXB_H
 
 /************************************************************************
  *                                                                      *
@@ -273,7 +272,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1247,7 +1246,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1286,4 +1285,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBXB_H */
+#endif /* _ASM_IA64_SN_SN1_HUBXB_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hubxb_next.h lia64-2.4/include/asm-ia64/sn/sn1/hubxb_next.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hubxb_next.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/hubxb_next.h	Mon Nov 19 23:22:56 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBXB_NEXT_H
-#define _ASM_SN_SN1_HUBXB_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBXB_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBXB_NEXT_H
 
 /* XB_FIRST_ERROR fe_source field encoding */
 #define XVE_SOURCE_POQ0 0xf	/* 1111 */
@@ -30,4 +29,4 @@
 #define XBP_RESET_DEFAULTS	0x0008000080000021LL
 #define XBP_ACTIVE_DEFAULTS	0x00080000fffff021LL
 
-#endif	/* _ASM_SN_SN1_HUBXB_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBXB_NEXT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/hwcntrs.h lia64-2.4/include/asm-ia64/sn/sn1/hwcntrs.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/hwcntrs.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/hwcntrs.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,96 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_HWCNTRS_H
+#define _ASM_IA64_SN_SN1_HWCNTRS_H
+
+
+typedef  uint64_t refcnt_t;
+
+#define SN0_REFCNT_MAX_COUNTERS 64
+
+typedef struct sn0_refcnt_set {
+	refcnt_t    refcnt[SN0_REFCNT_MAX_COUNTERS];
+        uint64_t  flags;
+        uint64_t  reserved[4];
+} sn0_refcnt_set_t;
+
+typedef struct sn0_refcnt_buf {
+	sn0_refcnt_set_t   refcnt_set;
+	uint64_t         paddr;
+        uint64_t         page_size;
+        cnodeid_t          cnodeid;         /* cnodeid + pad[3] use 64 bits */
+        uint16_t           pad[3];
+        uint64_t         reserved[4];
+} sn0_refcnt_buf_t;
+
+typedef struct sn0_refcnt_args {
+	uint64_t          vaddr;
+	uint64_t          len;
+	sn0_refcnt_buf_t*   buf;
+        uint64_t          reserved[4];
+} sn0_refcnt_args_t;
+
+/*
+ * Info needed by the user level program
+ * to mmap the refcnt buffer
+ */
+
+#define RCB_INFO_GET  1
+#define RCB_SLOT_GET  2
+
+typedef struct rcb_info {
+        uint64_t  rcb_len;                  /* total refcnt buffer len in bytes */
+
+        int         rcb_sw_sets;              /* number of sw counter sets in buffer */
+        int         rcb_sw_counters_per_set;  /* sw counters per set -- num_compact_nodes */
+        int         rcb_sw_counter_size;      /* sizeof(refcnt_t) -- size of sw cntr */
+
+        int         rcb_base_pages;           /* number of base pages in node */
+        int         rcb_base_page_size;       /* sw base page size */        
+        uint64_t  rcb_base_paddr;           /* base physical address for this node */
+
+        int         rcb_cnodeid;              /* cnodeid for this node */
+        int         rcb_granularity;          /* hw page size used for counter sets */
+        uint        rcb_hw_counter_max;       /* max hwcounter count (width mask) */
+        int         rcb_diff_threshold;       /* current node differential threshold */
+        int         rcb_abs_threshold;        /* current node absolute threshold */
+        int         rcb_num_slots;            /* physmem slots */
+        
+        int         rcb_reserved[512];
+        
+} rcb_info_t;
+
+typedef struct rcb_slot {
+        uint64_t  base;
+        uint64_t  size;
+} rcb_slot_t;
+
+#if defined(__KERNEL__)
+typedef struct sn0_refcnt_args_32 {
+	uint64_t    vaddr;
+	uint64_t    len;
+	app32_ptr_t   buf;
+        uint64_t    reserved[4];
+} sn0_refcnt_args_32_t;
+
+/* Defines and Macros  */
+/* A set of reference counts are for 4k bytes of physical memory */
+#define	NBPREFCNTP	0x1000	
+#define	BPREFCNTPSHIFT	12
+#define bytes_to_refcntpages(x)	(((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT)
+#define refcntpage_offset(x)	((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1)))
+#define align_to_refcntpage(x)	((__psunsigned_t)(x)&(~(NBPREFCNTP-1)))
+
+extern void migr_refcnt_read(sn0_refcnt_buf_t*);
+extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*);
+extern int migr_refcnt_enabled(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_SN1_HWCNTRS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/intr.h lia64-2.4/include/asm-ia64/sn/sn1/intr.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/intr.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/intr.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,238 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_INTR_H
+#define _ASM_IA64_SN_SN1_INTR_H
+
+/* Subnode wildcard */
+#define SUBNODE_ANY		-1
+
+/* Number of interrupt levels associated with each interrupt register. */
+#define N_INTPEND_BITS		64
+
+#define INT_PEND0_BASELVL	0
+#define INT_PEND1_BASELVL	64
+
+#define	N_INTPENDJUNK_BITS	8
+#define	INTPENDJUNK_CLRBIT	0x80
+
+#include <linux/config.h>
+#include <asm/sn/intr_public.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/hack.h>
+
+#ifndef __ASSEMBLY__
+#define II_NAMELEN	24
+
+/*
+ * Dispatch table entry - contains information needed to call an interrupt
+ * routine.
+ */
+typedef struct intr_vector_s {
+	intr_func_t	iv_func;	/* Interrupt handler function */
+	intr_func_t	iv_prefunc;	/* Interrupt handler prologue func */
+	void		*iv_arg;	/* Argument to pass to handler */
+	cpuid_t			iv_mustruncpu;	/* Where we must run. */
+} intr_vector_t;
+
+/* Interrupt information table. */
+typedef struct intr_info_s {
+	xtalk_intr_setfunc_t	ii_setfunc;	/* Function to set the interrupt
+						 * destination and level register.
+						 * It returns 0 (success) or an
+						 * error code.
+						 */
+	void			*ii_cookie;	/* arg passed to setfunc */
+	devfs_handle_t		ii_owner_dev;	/* device that owns this intr */
+	char			ii_name[II_NAMELEN];	/* Name of this intr. */
+	int			ii_flags;	/* informational flags */
+} intr_info_t;
+
+
+#define THD_CREATED	0x00000001	/*
+					 * We've created a thread for this
+					 * interrupt.
+					 */
+
+/*
+ * Bits for ii_flags:
+ */
+#define II_UNRESERVE	0
+#define II_RESERVE	1		/* Interrupt reserved. 			*/
+#define II_INUSE	2		/* Interrupt connected 			*/
+#define II_ERRORINT	4		/* INterrupt is an error condition 	*/
+#define II_THREADED	8		/* Interrupt handler is threaded.	*/
+
+/*
+ * Interrupt level wildcard
+ */
+#define INTRCONNECT_ANYBIT	-1
+
+/*
+ * This structure holds information needed both to call and to maintain
+ * interrupts.  The two are in separate arrays for the locality benefits.
+ * Since there's only one set of vectors per hub chip (but more than one
+ * CPU, the lock to change the vector tables must be here rather than in
+ * the PDA.
+ */
+
+typedef struct intr_vecblk_s {
+	intr_vector_t	vectors[N_INTPEND_BITS];  /* information needed to
+						     call an intr routine. */
+	intr_info_t	info[N_INTPEND_BITS];	  /* information needed only
+						     to maintain interrupts. */
+	spinlock_t	vector_lock;		  /* Lock for this and the
+						     masks in the PDA. */
+	splfunc_t	vector_spl;		  /* vector_lock req'd spl */
+	int		vector_state;		  /* Initialized to zero.
+						     Set to INTR_INITED
+						     by hubintr_init.
+						   */
+	int		vector_count;		  /* Number of vectors
+						   * reserved.
+						   */
+	int		cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
+						   * connected to each CPU
+						   */
+	int		ithreads_enabled;	  /* Are interrupt threads
+						   * initialized on this node.
+						   * and block?
+						   */
+} intr_vecblk_t;
+
+/* Possible values for vector_state: */
+#define VECTOR_UNINITED	0
+#define VECTOR_INITED	1
+#define VECTOR_SET	2
+
+#define hub_intrvect0	private.p_intmasks.dispatch0->vectors
+#define hub_intrvect1	private.p_intmasks.dispatch1->vectors
+#define hub_intrinfo0	private.p_intmasks.dispatch0->info
+#define hub_intrinfo1	private.p_intmasks.dispatch1->info
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(_level)	LOCAL_HUB_S(PI_INT_PEND_MOD, \
+						    (0x100|(_level)))
+#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
+
+#define REMOTE_CPU_SEND_INTR(_cpuid, _level) 					\
+		REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid),				\
+			SUBNODE(cpuid_to_slice(_cpuid)),				\
+			PI_INT_PEND_MOD, (0x100|(_level)))
+
+/*
+ * When clearing the interrupt, make sure this clear does make it 
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(_level)	  \
+                LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)),	\
+                LOCAL_HUB_L(PI_INT_PEND0)
+#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)),	\
+                REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
+
+/* Special support for use by gfx driver only.  Supports special gfx hub interrupt. */
+extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
+
+void setrtvector(intr_func_t func);
+
+/*
+ * Interrupt blocking
+ */
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *	L0 = SW1
+ *	L1 = SW2
+ *	L2 = INT_PEND0
+ *	L3 = INT_PEND1
+ *	L4 = RTC
+ *	L5 = Profiling Timer
+ *	L6 = Hub Errors
+ *	L7 = Count/Compare (T5 counters)
+ */
+
+
+/* INT_PEND0 hard-coded bits. */
+#ifdef DEBUG_INTR_TSTAMP
+/* hard coded interrupt level for interrupt latency test interrupt */
+#define	CPU_INTRLAT_B	62
+#define	CPU_INTRLAT_A	61
+#endif
+
+/* Hardcoded bits required by software. */
+#define MSC_MESG_INTR	9
+#define CPU_ACTION_B	8
+#define CPU_ACTION_A	7
+
+/* These are determined by hardware: */
+#define CC_PEND_B	6
+#define CC_PEND_A	5
+#define UART_INTR	4
+#define PG_MIG_INTR	3
+#define GFX_INTR_B	2
+#define GFX_INTR_A	1
+#define RESERVED_INTR	0
+
+/* INT_PEND1 hard-coded bits: */
+#define MSC_PANIC_INTR	63
+#define NI_ERROR_INTR	62
+#define MD_COR_ERR_INTR	61
+#define COR_ERR_INTR_B	60
+#define COR_ERR_INTR_A	59
+#define CLK_ERR_INTR	58
+
+# define NACK_INT_B	57
+# define NACK_INT_A	56
+# define LB_ERROR	55
+# define XB_ERROR	54
+
+#define BRIDGE_ERROR_INTR 53	/* Setup by PROM to catch Bridge Errors */
+
+#define IP27_INTR_0	52	/* Reserved for PROM use */
+#define IP27_INTR_1	51	/*   (do not use in Kernel) */
+#define IP27_INTR_2	50
+#define IP27_INTR_3	49
+#define IP27_INTR_4	48
+#define IP27_INTR_5	47
+#define IP27_INTR_6	46
+#define IP27_INTR_7	45
+
+#define	TLB_INTR_B	44	/* used for tlb flush random */
+#define	TLB_INTR_A	43
+
+#define LLP_PFAIL_INTR_B 42	/* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_A 41
+
+#define NI_BRDCAST_ERR_B 40
+#define NI_BRDCAST_ERR_A 39
+
+# define IO_ERROR_INTR	38	/* set up by prom */
+# define DEBUG_INTR_B	37	/* used by symmon to stop all cpus */
+# define DEBUG_INTR_A	36
+
+// These aren't strictly accurate or complete.  See the
+// Synergy Spec. for details.
+#define SGI_UART_IRQ	(65)
+#define SGI_HUB_ERROR_IRQ	(182)
+
+#endif /* _ASM_IA64_SN_SN1_INTR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/intr_public.h lia64-2.4/include/asm-ia64/sn/sn1/intr_public.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/intr_public.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/intr_public.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,53 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_INTR_PUBLIC_H
+#define _ASM_IA64_SN_SN1_INTR_PUBLIC_H
+
+/* REMEMBER: If you change these, the whole world needs to be recompiled.
+ * It would also require changing the hubspl.s code and SN0/intr.c
+ * Currently, the spl code has no support for multiple INTPEND1 masks.
+ */
+
+#define	N_INTPEND0_MASKS	1
+#define	N_INTPEND1_MASKS	1
+
+#define INTPEND0_MAXMASK	(N_INTPEND0_MASKS - 1)
+#define INTPEND1_MAXMASK	(N_INTPEND1_MASKS - 1)
+
+#ifndef __ASSEMBLY__
+#include <asm/sn/arch.h>
+
+struct intr_vecblk_s;	/* defined in asm/sn/intr.h */
+
+/*
+ * The following are necessary to create the illusion of a CEL
+ * on the IP27 hub.  We'll add more priority levels soon, but for
+ * now, any interrupt in a particular band effectively does an spl.
+ * These must be in the PDA since they're different for each processor.
+ * Users of this structure must hold the vector_lock in the appropriate vector
+ * block before modifying the mask arrays.  There's only one vector block
+ * for each Hub so a lock in the PDA wouldn't be adequate.
+ */
+typedef struct hub_intmasks_s {
+	/*
+	 * The masks are stored with the lowest-priority (most inclusive)
+	 * in the lowest-numbered masks (i.e., 0, 1, 2...).
+	 */
+	/* INT_PEND0: */
+	hubreg_t		intpend0_masks[N_INTPEND0_MASKS]; 
+	/* INT_PEND1: */
+	hubreg_t		intpend1_masks[N_INTPEND1_MASKS];
+	/* INT_PEND0: */
+	struct intr_vecblk_s	*dispatch0;	
+	/* INT_PEND1: */
+	struct intr_vecblk_s	*dispatch1;
+} hub_intmasks_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_IA64_SN_SN1_INTR_PUBLIC_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/ip27config.h lia64-2.4/include/asm-ia64/sn/sn1/ip27config.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/ip27config.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/ip27config.h	Mon Nov 19 23:22:56 2001
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_IP27CONFIG_H
-#define _ASM_SN_SN1_IP27CONFIG_H
+#ifndef _ASM_IA64_SN_SN1_IP27CONFIG_H
+#define _ASM_IA64_SN_SN1_IP27CONFIG_H
 
 
 /*
@@ -50,7 +49,7 @@
  */
 #define IP27_RTC_FREQ			1250	/* 800ns cycle time */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 typedef	struct ip27config_s {		/* KEEP IN SYNC w/ start.s & below  */
     uint		time_const;	/* Time constant 		    */
@@ -110,9 +109,9 @@
  */
 #define CONFIG_12P4I_NODE(n)	(0)
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 	.struct		0		/* KEEP IN SYNC WITH C structure */
 
 ip27c_time_const:	.word	0
@@ -137,7 +136,7 @@
 ip27c_pvers_rev:	.word	0
 
 ip27c_config_type:	.word 	0	/* To recognize special configs */
-#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
 /*
  * R10000 Configuration Cycle - These define the SYSAD values used
@@ -245,7 +244,7 @@
 
 #define CONFIG_FREQ_RTC	IP27C_KHZ(IP27_RTC_FREQ)
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* we are going to define all the known configs is a table
  * for building hex images we will pull out the particular
@@ -500,9 +499,9 @@
 #define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr
 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 
 /* these need to be in here since we need assembly definitions
  * for building hex images (as required by start.s)
@@ -653,6 +652,6 @@
 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_SN1_IP27CONFIG_H */
+#endif /* _ASM_IA64_SN_SN1_IP27CONFIG_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/kldir.h lia64-2.4/include/asm-ia64/sn/sn1/kldir.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/kldir.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/kldir.h	Wed Dec 31 16:00:00 1969
@@ -1,222 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef _ASM_SN_SN1_KLDIR_H
-#define _ASM_SN_SN1_KLDIR_H
-
-/*
- * The upper portion of the memory map applies during boot
- * only and is overwritten by IRIX/SYMMON.  The minimum memory bank
- * size on IP35 is 64M, which provides a limit on the amount of space
- * the PROM can assume it has available.
- *
- * Most of the addresses below are defined as macros in this file, or
- * in SN/addrs.h or SN/SN1/addrs.h.
- *
- *                                    MEMORY MAP PER NODE
- *
- * 0x4000000 (64M)         +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      IO7 TEXT/DATA/BSS/stack            |
- * 0x3000000 (48M)         +-----------------------------------------+
- *                         |      Free                               |
- * 0x2102000 (>33M)        +-----------------------------------------+
- *                         |      IP35 Topology (PCFG) + misc data   |
- * 0x2000000 (32M)         +-----------------------------------------+
- *                         |      IO7 BUFFERS FOR FLASH ENET IOC3    |
- * 0x1F80000 (31.5M)       +-----------------------------------------+
- *                         |      Free                               |
- * 0x1C00000 (28M)         +-----------------------------------------+
- *                         |      IP35 PROM TEXT/DATA/BSS/stack      |
- * 0x1A00000 (26M)         +-----------------------------------------+
- *                         |      Routing temp. space                |
- * 0x1800000 (24M)         +-----------------------------------------+
- *                         |      Diagnostics temp. space            |
- * 0x1500000 (21M)         +-----------------------------------------+
- *                         |      Free                               |
- * 0x1400000 (20M)         +-----------------------------------------+
- *                         |      IO7 PROM temporary copy            |
- * 0x1300000 (19M)         +-----------------------------------------+
- *                         |                                         |
- *                         |      Free                               |
- *                         |      (UNIX DATA starts above 0x1000000) |
- *                         |                                         |
- *                         +-----------------------------------------+
- *                         |      UNIX DEBUG Version                 |
- * 0x0310000 (3.1M)        +-----------------------------------------+
- *                         |      SYMMON, loaded just below UNIX     |
- *                         |      (For UNIX Debug only)              |
- *                         |                                         |
- *                         |                                         |
- * 0x006C000 (432K)        +-----------------------------------------+
- *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
- *                         |      (For UNIX Debug only)              |
- * 0x004C000 (304K)        +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      UNIX NON-DEBUG Version             |
- * 0x0040000 (256K)        +-----------------------------------------+
- *
- *
- * The lower portion of the memory map contains information that is
- * permanent and is used by the IP35PROM, IO7PROM and IRIX.
- *
- * 0x40000 (256K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      KLCONFIG (64K)                     |
- *                         |                                         |
- * 0x30000 (192K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      PI Error Spools (64K)              |
- *                         |                                         |
- * 0x20000 (128K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x19000 (100K)          +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 3)|
- * 0x18800 (98K)           +-----------------------------------------+
- *			   |      cache error eframe (CPU 3)	     |
- * 0x18400 (97K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 3)         |
- * 0x18000 (96K)           +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x13c00 (79K)           +-----------------------------------------+
- *                         |      GPDA (8k)                          |
- * 0x11c00 (71K)           +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 2)|
- * 0x10800 (66k)	   +-----------------------------------------+
- *			   |      cache error eframe (CPU 2)	     |
- * 0x10400 (65K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 2)         |
- * 0x10000 (64K)           +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x0b400 (45K)           +-----------------------------------------+
- *                         |      GDA (1k)                           |
- * 0x0b000 (44K)           +-----------------------------------------+
- *                         |      NMI Eframe areas (4)       	     |
- * 0x0a000 (40K)           +-----------------------------------------+
- *                         |      NMI Register save areas (4)        |
- * 0x09000 (36K)           +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 1)|
- * 0x08800 (34K)           +-----------------------------------------+
- *			   |      cache error eframe (CPU 1)	     |
- * 0x08400 (33K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 1)         |
- * 0x08000 (32K)           +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- *                         |                                         |
- * 0x04000 (16K)           +-----------------------------------------+
- *                         |      NMI Handler (Protected Page)       |
- * 0x03000 (12K)           +-----------------------------------------+
- *                         |      ARCS PVECTORS (master node only)   |
- * 0x02c00 (11K)           +-----------------------------------------+
- *                         |      ARCS TVECTORS (master node only)   |
- * 0x02800 (10K)           +-----------------------------------------+
- *                         |      LAUNCH [NUM_CPU]                   |
- * 0x02400 (9K)            +-----------------------------------------+
- *                         |      Low memory directory (KLDIR)       |
- * 0x02000 (8K)            +-----------------------------------------+
- *                         |      ARCS SPB (1K)                      |
- * 0x01000 (4K)            +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 0)|
- * 0x00800 (2k)	           +-----------------------------------------+
- *			   |      cache error eframe (CPU 0)	     |
- * 0x00400 (1K)            +-----------------------------------------+
- *                         |      Exception Handlers (CPU 0)         |
- * 0x00000 (0K)            +-----------------------------------------+
- */
-
-/*
- * NOTE:  To change the kernel load address, you must update:
- *  - the appropriate elspec files in irix/kern/master.d
- *  - NODEBUGUNIX_ADDR in SN/SN1/addrs.h
- *  - IP27_FREEMEM_OFFSET below
- *  - KERNEL_START_OFFSET below (if supporting cells)
- */
-
-
-/*
- * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
- * we define here.  Since it's set up in the prom.  We can't redefine it later
- * and expect more space to be allocated.  The way to find out the true size
- * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
- * for a particular node.
- */
-#define SYMMON_STACK_SIZE		0x8000
-
-#if defined (PROM) || defined (SABLE)
-
-/*
- * These defines are prom version dependent.  No code other than the IP35
- * prom should attempt to use these values.
- */
-#define IP27_LAUNCH_OFFSET		0x2400
-#define IP27_LAUNCH_SIZE		0x400
-#define IP27_LAUNCH_COUNT		4
-#define IP27_LAUNCH_STRIDE		0x100 /* could be as small as 0x80 */
-
-#define IP27_KLCONFIG_OFFSET		0x30000
-#define IP27_KLCONFIG_SIZE		0x10000
-#define IP27_KLCONFIG_COUNT		1
-#define IP27_KLCONFIG_STRIDE		0
-
-#define IP27_NMI_OFFSET			0x3000
-#define IP27_NMI_SIZE			0x100
-#define IP27_NMI_COUNT			4
-#define IP27_NMI_STRIDE			0x40
-
-#define IP27_PI_ERROR_OFFSET		0x20000
-#define IP27_PI_ERROR_SIZE		0x10000
-#define IP27_PI_ERROR_COUNT		1
-#define IP27_PI_ERROR_STRIDE		0
-
-#define IP27_SYMMON_STK_OFFSET		0x4c000
-#define IP27_SYMMON_STK_SIZE		0x20000
-#define IP27_SYMMON_STK_COUNT		4
-/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
-#define IP27_SYMMON_STK_STRIDE		0x8000
-
-#define IP27_FREEMEM_OFFSET		0x40000
-#define IP27_FREEMEM_SIZE		-1
-#define IP27_FREEMEM_COUNT		1
-#define IP27_FREEMEM_STRIDE		0
-
-#endif /* PROM || SABLE*/
-/*
- * There will be only one of these in a partition so the IO7 must set it up.
- */
-#define IO6_GDA_OFFSET			0xb000
-#define IO6_GDA_SIZE			0x400
-#define IO6_GDA_COUNT			1
-#define IO6_GDA_STRIDE			0
-
-/*
- * save area of kernel nmi regs in the prom format
- */
-#define IP27_NMI_KREGS_OFFSET		0x9000
-#define IP27_NMI_KREGS_CPU_SIZE		0x400
-/*
- * save area of kernel nmi regs in eframe format 
- */
-#define IP27_NMI_EFRAME_OFFSET		0xa000
-#define IP27_NMI_EFRAME_SIZE		0x400
-
-#define GPDA_OFFSET			0x11c00
-
-#endif /* _ASM_SN_SN1_KLDIR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/leds.h lia64-2.4/include/asm-ia64/sn/sn1/leds.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/leds.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/leds.h	Wed Dec 31 16:00:00 1969
@@ -1,35 +0,0 @@
-#ifndef _ASM_SN_SN1_LED_H
-#define _ASM_SN_SN1_LED_H
-
-/*
- * Copyright (C) 2000 Silicon Graphics, Inc
- * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
- */
-
-#include <asm/smp.h>
-
-#define LED0		0xc0000b00100000c0LL	/* ZZZ fixme */
-
-
-
-#define LED_AP_START	0x01		/* AP processor started */
-#define LED_AP_IDLE	0x01
-
-/*
- * Basic macros for flashing the LEDS on an SGI, SN1.
- */
-
-extern __inline__ void
-HUB_SET_LED(int val)
-{
-	long	*ledp;
-	int	eid;
-
-	eid = hard_smp_processor_id() & 3;
-	ledp = (long*) (LED0 + (eid<<3));
-	*ledp = val;
-}
-
-
-#endif /* _ASM_SN_SN1_LED_H */
-
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/mem_refcnt.h lia64-2.4/include/asm-ia64/sn/sn1/mem_refcnt.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/mem_refcnt.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/mem_refcnt.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,25 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_MEM_REFCNT_H
+#define _ASM_IA64_SN_SN1_MEM_REFCNT_H
+
+extern int mem_refcnt_attach(devfs_handle_t hub);
+extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot);
+extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt);
+extern int mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp);
+        
+
+#endif /* _ASM_IA64_SN_SN1_MEM_REFCNT_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/mmzone_sn1.h lia64-2.4/include/asm-ia64/sn/sn1/mmzone_sn1.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/mmzone_sn1.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/mmzone_sn1.h	Mon Nov 19 23:22:56 2001
@@ -0,0 +1,150 @@
+#ifndef _ASM_IA64_SN_MMZONE_SN1_H
+#define _ASM_IA64_SN_MMZONE_SN1_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/sn/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+
+
+/*
+ * SGI SN1 Arch defined values
+ *
+ * 	An SN1 physical address is broken down as follows:
+ *
+ *             +-----------------------------------------+
+ *             |         |    |      |   node offset     |
+ *             | unused  | AS | node |-------------------|
+ *             |         |    |      | cn | clump offset |
+ *             +-----------------------------------------+
+ *              6       4 4  4 3    3 3  3 2            0
+ *              3       4 3  0 9    3 2  0 9            0
+ *
+ *		bits 63-44	Unused - must be zero
+ *		bits 43-40	Address space ID. Cached memory has a value of 0.
+ *				Chipset & IO addresses have non-zero values.
+ *		bits 39-33	Node number. Note that some configurations do NOT
+ *				have a node zero.
+ *		bits 32-0	Node offset.
+ *
+ *	The node offset can be further broken down as:
+ *		bits 32-30	Clump (bank) number.
+ *		bits 29-0	Clump (bank) offset.
+ *
+ *	A node consists of up to 8 clumps (banks) of memory. A clump may be empty, or may be
+ *	populated with a single contiguous block of memory starting at clump
+ *	offset 0. The size of the block is (2**n) * 64MB, where 0<n<5.
+ *
+ *
+ * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with
+ *	 "SN_" are intended for internal use only and should not be used in
+ *	 any platform independent code. 
+ *
+ *	 This file is also responsible for exporting the following definitions:
+ *		cnodeid_t	Define a compact node id. 
+ */
+
+#define SN1_BANKS_PER_NODE		8
+#define SN1_NODE_SIZE			(8UL*1024*1024*1024)	/* 8 GB per node */
+#define SN1_BANK_SIZE			(SN1_NODE_SIZE/SN1_BANKS_PER_NODE)
+#define SN1_NODE_SHIFT			33
+#define SN1_NODE_MASK			0x7fUL
+#define SN1_NODE_OFFSET_MASK		(SN1_NODE_SIZE-1)
+#define SN1_NODE_NUMBER(addr)		(((unsigned long)(addr) >> SN1_NODE_SHIFT) & SN1_NODE_MASK)
+#define SN1_NODE_CLUMP_NUMBER(addr)	(((unsigned long)(addr) >>30) & 7)
+#define SN1_NODE_OFFSET(addr)		(((unsigned long)(addr)) & SN1_NODE_OFFSET_MASK)
+#define SN1_KADDR(nasid, offset)	(((unsigned long)(nasid)<<SN1_NODE_SHIFT) | (offset) | PAGE_OFFSET)
+
+
+#define PLAT_MAX_NODE_NUMBER		MAX_NASIDS			/* Maximum node number +1 */
+#define PLAT_MAX_COMPACT_NODES		MAX_COMPACT_NODES		/* Maximum number of nodes in SSI */
+
+#define PLAT_MAX_PHYS_MEMORY		(1UL << 40)
+
+
+
+/*
+ * On the SN platforms, a clump is the same as a memory bank.
+ */
+#define PLAT_CLUMPS_PER_NODE		SN1_BANKS_PER_NODE
+#define PLAT_CLUMP_OFFSET(addr)		((unsigned long)(addr) & 0x3fffffffUL)
+#define PLAT_CLUMPSIZE                  (SN1_NODE_SIZE/PLAT_CLUMPS_PER_NODE)
+#define PLAT_MAXCLUMPS			(PLAT_CLUMPS_PER_NODE*PLAT_MAX_COMPACT_NODES)
+
+
+
+
+/*
+ * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a
+ * valid cacheable identity mapped RAM memory address.
+ * Note that the RAM may or may not actually be present!!
+ */
+#define SN1_VALID_KERN_ADDR_MASK	0xffffff0000000000UL
+#define SN1_VALID_KERN_ADDR_VALUE	0xe000000000000000UL
+#define PLAT_VALID_MEM_KADDR(kaddr)	(((unsigned long)(kaddr) & SN1_VALID_KERN_ADDR_MASK) == SN1_VALID_KERN_ADDR_VALUE)
+
+
+
+/*
+ * Memory is conceptually divided into chunks. A chunk is either
+ * completely present, or else the kernel assumes it is completely
+ * absent. Each node consists of a number of possibly discontiguous chunks.
+ */
+#define SN1_CHUNKSHIFT			26			/* 64 MB */
+#define SN1_CHUNKSIZE			(1UL << SN1_CHUNKSHIFT)
+#define PLAT_CHUNKNUM(addr)		(((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT)
+
+
+/*
+ * Given a kaddr, find the nid (compact nodeid)
+ */
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+#define DISCONBUG(kaddr)		panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx",	 	\
+						__LINE__, __FILE__, (long)(kaddr))
+
+#define KVADDR_TO_NID(kaddr)		({long _ktn=(long)(kaddr);					\
+						kern_addr_valid(_ktn) ? 				\
+						NODEDIR->physical_node_map[SN1_NODE_NUMBER(_ktn)] :	\
+						(DISCONBUG(_ktn), 0UL);})
+#else
+#define KVADDR_TO_NID(kaddr)		(NODEDIR->physical_node_map[SN1_NODE_NUMBER(kaddr)])
+#endif
+
+
+
+/*
+ * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry
+ * for the first page of the clump.
+ */
+#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr)		({long _kmmi=(long)(kaddr);				\
+							KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE +	\
+							SN1_NODE_CLUMP_NUMBER(_kmmi);})
+
+
+/*
+ * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on
+ * nodes so that they dont alias to the same line in the cache as the previous allocated structure.
+ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & 
+ * changes the node number.
+ */
+#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr)	SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]),	\
+						  (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)
+
+
+
+
+/*
+ * Convert a proximity domain number (from the ACPI tables) into a physical node number.
+ */
+
+#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm)	(pxm)
+
+#endif /* _ASM_IA64_SN_MMZONE_SN1_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/promlog.h lia64-2.4/include/asm-ia64/sn/sn1/promlog.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/promlog.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/promlog.h	Wed Dec 31 16:00:00 1969
@@ -1,85 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef	_ASM_SN_SN1_PROMLOG_H
-#define	_ASM_SN_SN1_PROMLOG_H
-
-#include <asm/sn/fprom.h>
-
-#define PROMLOG_MAGIC			0x504c4f49
-#define PROMLOG_VERSION			1
-
-#define PROMLOG_OFFSET_MAGIC		0x10
-#define PROMLOG_OFFSET_VERSION		0x14
-#define PROMLOG_OFFSET_SEQUENCE		0x18
-#define PROMLOG_OFFSET_ENTRY0		0x100
-
-#define PROMLOG_ERROR_NONE		0
-#define PROMLOG_ERROR_PROM	       -1
-#define PROMLOG_ERROR_MAGIC	       -2
-#define PROMLOG_ERROR_CORRUPT	       -3
-#define PROMLOG_ERROR_BOL	       -4
-#define PROMLOG_ERROR_EOL	       -5
-#define PROMLOG_ERROR_POS	       -6
-#define PROMLOG_ERROR_REPLACE	       -7
-#define PROMLOG_ERROR_COMPACT	       -8
-#define PROMLOG_ERROR_FULL	       -9
-#define PROMLOG_ERROR_ARG	       -10
-#define PROMLOG_ERROR_UNUSED	       -11	  	
-
-#define PROMLOG_TYPE_UNUSED		0xf
-#define PROMLOG_TYPE_LOG		3
-#define PROMLOG_TYPE_LIST		2
-#define PROMLOG_TYPE_VAR		1
-#define PROMLOG_TYPE_DELETED		0
-
-#define PROMLOG_TYPE_ANY		98
-#define PROMLOG_TYPE_INVALID		99
-
-#define PROMLOG_KEY_MAX			14
-#define PROMLOG_VALUE_MAX		47
-#define PROMLOG_CPU_MAX			4
-
-typedef struct promlog_header_s {
-    unsigned int	unused[4];
-    unsigned int	magic;
-    unsigned int	version;
-    unsigned int	sequence;
-} promlog_header_t;
-
-typedef unsigned int promlog_pos_t;
-
-typedef struct promlog_ent_s {		/* PROM individual entry */
-    uint		type		: 4;
-    uint		cpu_num		: 4;
-    char		key[PROMLOG_KEY_MAX + 1];
-
-    char		value[PROMLOG_VALUE_MAX + 1];
-
-} promlog_ent_t;
-
-typedef struct promlog_s {		/* Activation handle */
-    fprom_t		f;
-    int			sector_base;
-    int			cpu_num;
-
-    int			active;		/* Active sector, 0 or 1 */
-
-    promlog_pos_t	log_start;
-    promlog_pos_t	log_end;
-
-    promlog_pos_t	alt_start;
-    promlog_pos_t	alt_end;
-
-    promlog_pos_t	pos;
-    promlog_ent_t	ent;
-} promlog_t;
-
-#endif /* _ASM_SN_SN1_PROMLOG_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/router.h lia64-2.4/include/asm-ia64/sn/sn1/router.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/router.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/router.h	Wed Dec 31 16:00:00 1969
@@ -1,670 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef	_ASM_SN_SN1_ROUTER_H
-#define	_ASM_SN_SN1_ROUTER_H
-
-/*
- * Router Register definitions
- *
- * Macro argument _L always stands for a link number (1 to 8, inclusive).
- */
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
-#include <asm/sn/vector.h>
-#include <asm/sn/slotnum.h>
-#include <asm/sn/arch.h>
-
-typedef uint64_t	router_reg_t;
-
-#define MAX_ROUTERS	64
-
-#define MAX_ROUTER_PATH	80
-
-#define ROUTER_REG_CAST		(volatile router_reg_t *)
-#define PS_UINT_CAST		(__psunsigned_t)
-#define UINT64_CAST		(uint64_t)
-typedef signed char port_no_t;	 /* Type for router port number      */
-
-#elif _LANGUAGE_ASSEMBLY
-
-#define ROUTERREG_CAST
-#define PS_UINT_CAST
-#define UINT64_CAST
-
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */
-
-#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */
-
-#define PORT_INVALID (-1)	 /* Invalid port number              */
-
-#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)
-
-#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
-
-/*
- * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
- * port to generate an output port.
- *
- * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
- * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
- *
- * These are written to work on unsigned data.
- */
-
-#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
-				 (_L) + (count) - MAX_ROUTER_PORTS :	\
-				 (_L) + (count))
-
-#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
-				 (_LD) - (_LS) :			\
-				 (_LD) + MAX_ROUTER_PORTS - (_LS))
-
-/* Router register addresses */
-
-#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
-#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
-#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
-#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
-#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
-#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
-#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
-#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
-#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
-#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
-#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */
-
-#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
-#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
-#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
-#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
-#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */
-
-#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
-#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */
-
-#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
-#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
-#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
-#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
-#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */
-
-#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
-/* Port-specific registers (_L is the link number from 1 to 8) */
-
-#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
-#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
-#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
-#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
-#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
-#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
-#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
-#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
-#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
-#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
-#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
-#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
-#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
-
-#define RR_META_ENTRIES		16
-
-#define RR_LOCAL_ENTRIES	128
-
-/*
- * RR_STATUS_REV_ID mask and shift definitions
- */
-
-#define RSRI_INPORT_SHFT	52
-#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
-#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
-#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
-#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
-#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
-#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
-#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
-#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
-#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
-#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
-#define RSRI_LOCAL_SHFT 	32
-#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
-#define RSRI_CHIPREV_SHFT	28
-#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
-#define RSRI_CHIPID_SHFT	12
-#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
-#define RSRI_MFGID_SHFT		1
-#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)
-
-#define RSRI_LSTAT_WENTDOWN	0
-#define RSRI_LSTAT_RESETFAIL	1
-#define RSRI_LSTAT_LINKUP	2
-#define RSRI_LSTAT_NOTUSED	3
-
-/*
- * RR_PORT_RESET mask definitions
- */
-
-#define RPRESET_WARM		(UINT64_CAST 1 << 9)
-#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
-#define RPRESET_LOCAL		(UINT64_CAST 1)
-
-/*
- * RR_PROT_CONF mask and shift definitions
- */
-
-#define RPCONF_DIRCMPDIS_SHFT	13
-#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
-#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
-#define RPCONF_FLOCAL_SHFT	12
-#define RPCONF_METAID_SHFT	8
-#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
-#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))
-
-/*
- * RR_GLOBAL_PORT_DEF mask and shift definitions
- */
-
-#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
-#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
-#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
-#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
-#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
-#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
-#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
-#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
-#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
-#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
-#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
-#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)
-
-#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */
-
-/*
- * RR_GLOBAL_PARMS0 mask and shift definitions
- */
-
-#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
-#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
-#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
-#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
-#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
-#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
-#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
-#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
-#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
-#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
-#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
-#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
-#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
-#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
-#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
-#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
-#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
-#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
-#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
-#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
-#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
-#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
-#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
-#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
-#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
-#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
-#define RGPARM0_BYPEN_SHFT	0
-#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */
-
-/*
- * RR_GLOBAL_PARMS1 shift and mask definitions
- */
-
-#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
-#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
-#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
-#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
-#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
-#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)
-
-/*
- * RR_DIAG_PARMS mask and shift definitions
- */
-
-#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
-#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
-#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
-#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))
-
-/*
- * RR_DEBUG_ADDR mask and shift definitions
- */
-
-#define RDA_DATA_SHFT		10	/* Observed debug data */
-#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
-#define RDA_ADDR_SHFT		0	/* debug address for data */
-#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)
-
-/*
- * RR_LB_TO_L2 mask and shift definitions
- */
-
-#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
-#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
-#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
-#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)
-
-/*
- * RR_L2_TO_LB mask and shift definitions
- */
-
-#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
-#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
-#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
-#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
-#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
-#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)
-
-/*
- * RR_JBUS_CONTROL mask and shift definitions
- */
-
-#define RJC_POS_BITS_SHFT	20	/* Router position bits */
-#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
-#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
-#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
-#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
-#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
-#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
-#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)
-
-/*
- * RR_SCRATCH_REGx mask and shift definitions
- *  note: these fields represent a software convention, and are not
- *        understood/interpreted by the hardware. 
- */
-
-#define	RSCR0_BOOTED_SHFT	63
-#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
-#define RSCR0_LOCALID_SHFT	56
-#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
-#define	RSCR0_UNUSED_SHFT	48
-#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
-#define RSCR0_NIC_SHFT		0
-#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)
-
-#define RSCR1_MODID_SHFT	0
-#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)
-
-/*
- * RR_VECTOR_HW_BAR mask and shift definitions
- */
-
-#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
-#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
-#define BAR_VLD_SHFT		26	/* Valid Configuration */
-#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
-#define BAR_SEQ_SHFT		24	/* Sequence number */
-#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
-#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
-#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
-#define BAR_PARENT_SHFT		14	/* Parent Port */
-#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
-#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
-#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
-#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
-#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)
-
-/*
- * RR_PORT_PARMS(_L) mask and shift definitions
- */
-
-#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
-#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
-#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
-#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
-#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
-#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)
-#define RPPARM_PORTMATE_SHFT	21	/* Port Mate for the port */
-#define RPPARM_PORTMATE_MASK	(UINT64_CAST 0x7 << 21)
-#define RPPARM_HISTEN_SHFT	20	/* Histogram counter enable */
-#define RPPARM_HISTEN_MASK	(UINT64_CAST 0x1 << 20)
-#define RPPARM_HISTSEL_SHFT	18
-#define RPPARM_HISTSEL_MASK	(UINT64_CAST 0x3 << 18)
-#define RPPARM_DAMQHS_SHFT	16
-#define RPPARM_DAMQHS_MASK	(UINT64_CAST 0x3 << 16)
-#define RPPARM_NULLTO_SHFT	10
-#define RPPARM_NULLTO_MASK	(UINT64_CAST 0x3f << 10)
-#define RPPARM_MAXBURST_SHFT	0
-#define RPPARM_MAXBURST_MASK	(UINT64_CAST 0x3ff)
-
-/*
- * NOTE: Normally the kernel tracks only UTILIZATION statistics.
- * The other 2 should not be used, except during any experimentation
- * with the router.
- */
-#define RPPARM_HISTSEL_AGE	0	/* Histogram age characterization.  */
-#define RPPARM_HISTSEL_UTIL	1	/* Histogram link utilization 	    */
-#define RPPARM_HISTSEL_DAMQ	2	/* Histogram DAMQ characterization. */
-
-/*
- * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
- */
-#define RSERR_POWERNOK		(UINT64_CAST 1 << 38)
-#define RSERR_PORT_DEADLOCK     (UINT64_CAST 1 << 37)
-#define RSERR_WARMRESET         (UINT64_CAST 1 << 36)
-#define RSERR_LINKRESET         (UINT64_CAST 1 << 35)
-#define RSERR_RETRYTIMEOUT      (UINT64_CAST 1 << 34)
-#define RSERR_FIFOOVERFLOW	(UINT64_CAST 1 << 33)
-#define RSERR_ILLEGALPORT	(UINT64_CAST 1 << 32)
-#define RSERR_DEADLOCKTO_SHFT	28
-#define RSERR_DEADLOCKTO_MASK	(UINT64_CAST 0xf << 28)
-#define RSERR_RECVTAILTO_SHFT	24
-#define RSERR_RECVTAILTO_MASK	(UINT64_CAST 0xf << 24)
-#define RSERR_RETRYCNT_SHFT	16
-#define RSERR_RETRYCNT_MASK	(UINT64_CAST 0xff << 16)
-#define RSERR_CBERRCNT_SHFT	8
-#define RSERR_CBERRCNT_MASK	(UINT64_CAST 0xff << 8)
-#define RSERR_SNERRCNT_SHFT	0
-#define RSERR_SNERRCNT_MASK	(UINT64_CAST 0xff << 0)
-
-
-#define PORT_STATUS_UP		(1 << 0)	/* Router link up */
-#define PORT_STATUS_FENCE	(1 << 1)	/* Router link fenced */
-#define PORT_STATUS_RESETFAIL	(1 << 2)	/* Router link didnot 
-						 * come out of reset */
-#define PORT_STATUS_DISCFAIL	(1 << 3)	/* Router link failed after 
-						 * out of reset but before
-						 * router tables were
-						 * programmed
-						 */
-#define PORT_STATUS_KERNFAIL	(1 << 4)	/* Router link failed
-						 * after reset and the 
-						 * router tables were
-						 * programmed
-						 */
-#define PORT_STATUS_UNDEF	(1 << 5)	/* Unable to pinpoint
-						 * why the router link
-						 * went down
-						 */	
-#define PROBE_RESULT_BAD	(-1)		/* Set if any of the router
-						 * links failed after reset
-						 */
-#define PROBE_RESULT_GOOD	(0)		/* Set if all the router links
-						 * which came out of reset 
-						 * are up
-						 */
-
-/* Should be enough for 256 CPUs */
-#define MAX_RTR_BREADTH		64		/* Max # of routers possible */
-
-/* Get the require set of bits in a var. corr to a sequence of bits  */
-#define GET_FIELD(var, fname) \
-        ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
-/* Set the require set of bits in a var. corr to a sequence of bits  */
-#define SET_FIELD(var, fname, fval) \
-        ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
-
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
-typedef struct router_map_ent_s {
-	uint64_t	nic;
-	moduleid_t	module;
-	slotid_t	slot;
-} router_map_ent_t;
-
-struct rr_status_error_fmt {
-	uint64_t	rserr_unused		: 30,
-			rserr_fifooverflow	: 1,
-			rserr_illegalport	: 1,
-			rserr_deadlockto	: 4,
-			rserr_recvtailto	: 4,
-			rserr_retrycnt		: 8,
-			rserr_cberrcnt		: 8,
-			rserr_snerrcnt		: 8;
-};
-
-/*
- * This type is used to store "absolute" counts of router events
- */
-typedef int	router_count_t;
-
-/* All utilizations are on a scale from 0 - 1023. */
-#define RP_BYPASS_UTIL	0
-#define RP_RCV_UTIL	1
-#define RP_SEND_UTIL	2
-#define RP_TOTAL_PKTS	3	/* Free running clock/packet counter */
-
-#define RP_NUM_UTILS	3
-
-#define RP_HIST_REGS	2
-#define RP_NUM_BUCKETS  4
-#define RP_HIST_TYPES	3
-
-#define RP_AGE0		0
-#define RP_AGE1		1
-#define RP_AGE2		2
-#define RP_AGE3		3
-
-
-#define RR_UTIL_SCALE	1024
-
-/*
- * Router port-oriented information
- */
-typedef struct router_port_info_s {
-	router_reg_t	rp_histograms[RP_HIST_REGS];/* Port usage info */
-	router_reg_t	rp_port_error;		/* Port error info */
-	router_count_t	rp_retry_errors;	/* Total retry errors */
-	router_count_t	rp_sn_errors;		/* Total sn errors */
-	router_count_t	rp_cb_errors;		/* Total cb errors */
-	int		rp_overflows;		/* Total count overflows */
-	int		rp_excess_err;		/* Port has excessive errors */
-	ushort		rp_util[RP_NUM_BUCKETS];/* Port utilization */
-} router_port_info_t;
-
-#define ROUTER_INFO_VERSION	7
-
-struct lboard_s;
-
-/*
- * Router information
- */
-typedef struct router_info_s {
-	char		ri_version;	/* structure version		    */
-	cnodeid_t	ri_cnode;	/* cnode of its legal guardian hub  */
-	nasid_t		ri_nasid;	/* Nasid of same 		    */
-	char		ri_ledcache;	/* Last LED bitmap		    */
-	char		ri_leds;	/* Current LED bitmap		    */
-	char		ri_portmask;	/* Active port bitmap		    */
-	router_reg_t	ri_stat_rev_id;	/* Status rev ID value		    */
-	net_vec_t	ri_vector;	/* vector from guardian to router   */
-	int		ri_writeid;	/* router's vector write ID	    */
-	int64_t	ri_timebase;	/* Time of first sample		    */
-	int64_t	ri_timestamp;	/* Time of last sample		    */
-	router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info      */
-	moduleid_t	ri_module;	/* Which module are we in?	    */
-	slotid_t	ri_slotnum;	/* Which slot are we in?	    */
-	router_reg_t	ri_glbl_parms[GLBL_PARMS_REGS];
-					/* Global parms0&1 register contents*/
-	devfs_handle_t	ri_vertex;	/* hardware graph vertex            */
-	router_reg_t	ri_prot_conf;	/* protection config. register	    */
-	int64_t	ri_per_minute;	/* Ticks per minute		    */
-
-	/*
-	 * Everything below here is for kernel use only and may change at	
-	 * at any time with or without a change in teh revision number
-	 *
-	 * Any pointers or things that come and go with DEBUG must go at
- 	 * the bottom of the structure, below the user stuff.
-	 */
-	char		ri_hist_type;   /* histogram type		    */
-	devfs_handle_t	ri_guardian;	/* guardian node for the router	    */
-	int64_t	ri_last_print;	/* When did we last print	    */
-	char		ri_print;	/* Should we print 		    */
-	char 		ri_just_blink;	/* Should we blink the LEDs         */
-	
-#ifdef DEBUG
-	int64_t	ri_deltatime;	/* Time it took to sample	    */
-#endif
-	spinlock_t	ri_lock;	/* Lock for access to router info   */
-	net_vec_t	*ri_vecarray;	/* Pointer to array of vectors	    */
-	struct lboard_s	*ri_brd;	/* Pointer to board structure	    */
-	char *		ri_name;	/* This board's hwg path 	    */
-        unsigned char	ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a 
-					message to availmon */
-} router_info_t;
-
-
-/* Router info location specifiers */
-
-#define RIP_PROMLOG			2	/* Router info in promlog */
-#define RIP_CONSOLE			4	/* Router info on console */
-
-#define ROUTER_INFO_PRINT(_rip,_where)	(_rip->ri_print |= _where)	
-					/* Set the field used to check if a 
-					 * router info can be printed
-					 */
-#define IS_ROUTER_INFO_PRINTED(_rip,_where)	\
-					(_rip->ri_print & _where)	
-					/* Was the router info printed to
-					 * the given location (_where) ?
-					 * Mainly used to prevent duplicate
-					 * router error states.
-					 */
-#define ROUTER_INFO_LOCK(_rip,_s)	_s = mutex_spinlock(&(_rip->ri_lock))
-					/* Take the lock on router info
-					 * to gain exclusive access
-					 */
-#define ROUTER_INFO_UNLOCK(_rip,_s)	mutex_spinunlock(&(_rip->ri_lock),_s)
-					/* Release the lock on router info */
-/* 
- * Router info hanging in the nodepda 
- */
-typedef struct nodepda_router_info_s {
-	devfs_handle_t 	router_vhdl;	/* vertex handle of the router 	    */
-	short		router_port;	/* port thru which we entered       */
-	short		router_portmask;
-	moduleid_t	router_module;	/* module in which router is there  */
-	slotid_t	router_slot;	/* router slot			    */
-	unsigned char	router_type;	/* kind of router 		    */
-	net_vec_t	router_vector;	/* vector from the guardian node    */
-
-	router_info_t	*router_infop;	/* info hanging off the hwg vertex  */
-	struct nodepda_router_info_s *router_next;
-	                                /* pointer to next element 	    */
-} nodepda_router_info_t;
-
-#define ROUTER_NAME_SIZE	20	/* Max size of a router name */
-
-#define NORMAL_ROUTER_NAME	"normal_router"
-#define NULL_ROUTER_NAME	"null_router"
-#define META_ROUTER_NAME	"meta_router"
-#define REPEATER_ROUTER_NAME	"repeater_router"
-#define UNKNOWN_ROUTER_NAME	"unknown_router" 
-
-/* The following definitions are needed by the router traversing
- * code either using the hardware graph or using vector operations.
- */
-/* Structure of the router queue element */
-typedef struct router_elt_s {
-	union {
-		/* queue element structure during router probing */
-		struct {
-			/* number-in-a-can (unique) for the router */
-			nic_t		nic;	
-			/* vector route from the master hub to 
-			 * this router.
-			 */
-			net_vec_t	vec;	
-			/* port status */
-			uint64_t	status;	
-			char		port_status[MAX_ROUTER_PORTS + 1];
-		} r_elt;
-		/* queue element structure during router guardian 
-		 * assignment
-		 */
-		struct {
-			/* vertex handle for the router */
-			devfs_handle_t	vhdl;
-			/* guardian for this router */
-			devfs_handle_t	guard;	
-			/* vector router from the guardian to the router */
-			net_vec_t	vec;
-		} k_elt;
-	} u;
-	                        /* easy to use port status interpretation */
-} router_elt_t;
-
-/* structure of the router queue */
-
-typedef struct router_queue_s {
-	char		head;	/* Point where a queue element is inserted */
-	char		tail;	/* Point where a queue element is removed */
-	int		type;
-	router_elt_t	array[MAX_RTR_BREADTH];
-	                        /* Entries for queue elements */
-} router_queue_t;
-
-
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-/*
- * RR_HISTOGRAM(_L) mask and shift definitions
- * There are two 64 bit histogram registers, so the following macros take
- * into account dealing with an array of 4 32 bit values indexed by _x
- */
-
-#define RHIST_BUCKET_SHFT(_x)	(32 * ((_x) & 0x1))
-#define RHIST_BUCKET_MASK(_x)	(UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1))
-#define RHIST_GET_BUCKET(_x, _reg)	\
-	((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
-
-/*
- * RR_RESET_MASK(_L) mask and shift definitions
- */
-
-#define RRM_RESETOK(_L)		(UINT64_CAST 1 << ((_L) - 1))
-#define RRM_RESETOK_ALL		ALL_PORTS
-
-/*
- * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
- */
-
-#define RTABLE_SHFT(_L)		(4 * ((_L) - 1))
-#define RTABLE_MASK(_L)		(UINT64_CAST 0x7 << RTABLE_SHFT(_L))
-
-
-#define	ROUTERINFO_STKSZ	4096
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-#if defined(_LANGUAGE_C_PLUS_PLUS)
-extern "C" {
-#endif
-
-int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
-int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
-int router_get_info(devfs_handle_t routerv, router_info_t *, int);
-int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip);
-int router_set_leds(router_info_t *rip);
-void router_print_state(router_info_t *rip, int level,
-		   void (*pf)(int, char *, ...),int print_where);
-void capture_router_stats(router_info_t *rip);
-
-
-int 	probe_routers(void);
-void 	get_routername(unsigned char brd_type,char *rtrname);
-void 	router_guardians_set(devfs_handle_t hwgraph_root);
-int 	router_hist_reselect(router_info_t *, int64_t);
-#if defined(_LANGUAGE_C_PLUS_PLUS)
-}
-#endif
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#endif /* _ASM_SN_SN1_ROUTER_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/slotnum.h lia64-2.4/include/asm-ia64/sn/sn1/slotnum.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/slotnum.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/slotnum.h	Mon Nov 19 23:22:56 2001
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_SLOTNUM_H
-#define _ASM_SN_SN1_SLOTNUM_H
+#ifndef _ASM_IA64_SN_SN1_SLOTNUM_H
+#define _ASM_IA64_SN_SN1_SLOTNUM_H
 
 #define SLOTNUM_MAXLENGTH	16
 
@@ -85,4 +84,4 @@
 
 #endif /* __KERNEL__ */
 
-#endif /* _ASM_SN_SN1_SLOTNUM_H */
+#endif /* _ASM_IA64_SN_SN1_SLOTNUM_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/sn1.h lia64-2.4/include/asm-ia64/sn/sn1/sn1.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/sn1.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/sn1.h	Wed Dec 31 16:00:00 1969
@@ -1,34 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-/*
- * sn1.h -- hardware specific defines for sn1 boards
- * The defines used here are used to limit the size of 
- * various datastructures in the PROM. eg. KLCFGINFO, MPCONF etc.
- */
-
-#ifndef _ASM_SN_SN1_SN1_H
-#define _ASM_SN_SN1_SN1_H
-
-extern xwidgetnum_t hub_widget_id(nasid_t);
-extern nasid_t get_nasid(void);
-extern int	get_slice(void);
-extern int     is_fine_dirmode(void);
-extern hubreg_t get_hub_chiprev(nasid_t nasid);
-extern hubreg_t get_region(cnodeid_t);
-extern hubreg_t nasid_to_region(nasid_t);
-extern int      verify_snchip_rev(void);
-extern void 	ni_reset_port(void);
-
-#ifdef SN1_USE_POISON_BITS
-extern int hub_bte_poison_ok(void);
-#endif /* SN1_USE_POISON_BITS */
-
-#endif /* _ASM_SN_SN1_SN1_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/sn_private.h lia64-2.4/include/asm-ia64/sn/sn1/sn_private.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/sn_private.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/sn_private.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,292 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN1_SN_PRIVATE_H
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk_private.h>
+
+extern nasid_t master_nasid;
+
+/* promif.c */
+#ifdef	LATER
+extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes);
+#endif
+extern void he_arcs_set_vectors(void);
+extern void mem_init(void);
+#ifdef	LATER
+extern int cpu_enabled(cpuid_t);
+#endif
+extern void cpu_unenable(cpuid_t);
+extern nasid_t get_lowest_nasid(void);
+extern __psunsigned_t get_master_bridge_base(void);
+extern void set_master_bridge_base(void);
+extern int check_nasid_equiv(nasid_t, nasid_t);
+extern nasid_t get_console_nasid(void);
+extern char get_console_pcislot(void);
+#ifdef	LATER
+extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
+#endif
+
+extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
+
+/* memsupport.c */
+extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
+extern int memory_present(paddr_t);
+extern int memory_read_accessible(paddr_t);
+extern int memory_write_accessible(paddr_t);
+extern void memory_set_access(paddr_t, int, int);
+extern void show_dir_state(paddr_t, void (*)(char *, ...));
+extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
+extern void set_dir_owner(paddr_t, int);
+extern void set_dir_state(paddr_t, int);
+extern void set_dir_state_POISONED(paddr_t);
+extern void set_dir_state_UNOWNED(paddr_t);
+extern int is_POISONED_dir_state(paddr_t);
+extern int is_UNOWNED_dir_state(paddr_t);
+extern void get_dir_ent(paddr_t paddr, int *state,
+			uint64_t *vec_ptr, hubreg_t *elo);
+
+/* intr.c */
+extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
+extern void intr_unreserve_level(cpuid_t cpu, int level);
+extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
+			intr_func_t intr_prefunc);
+extern int intr_disconnect_level(cpuid_t cpu, int bit);
+extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
+			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
+			      char *intr_name,int *resp_bit);
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+extern void setrtvector(intr_func_t);
+extern void install_cpuintr(cpuid_t cpu);
+extern void install_dbgintr(cpuid_t cpu);
+extern void install_tlbintr(cpuid_t cpu);
+extern void hub_migrintr_init(cnodeid_t /*cnode*/);
+extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
+extern int cause_intr_disconnect(int level);
+extern void intr_reserve_hardwired(cnodeid_t);
+extern void intr_clear_all(nasid_t);
+extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
+
+/* error_dump.c */
+extern char *hub_rrb_err_type[];
+extern char *hub_wrb_err_type[];
+
+void nmi_dump(void);
+void install_cpu_nmi_handler(int slice);
+
+/* klclock.c */
+extern void hub_rtc_init(cnodeid_t);
+
+/* bte.c */
+void bte_lateinit(void);
+void bte_wait_for_xfer_completion(void *);
+
+/* klgraph.c */
+void klhwg_add_all_nodes(devfs_handle_t);
+void klhwg_add_all_modules(devfs_handle_t);
+
+/* klidbg.c */
+void install_klidbg_functions(void);
+
+/* klnuma.c */
+extern void replicate_kernel_text(int numnodes);
+extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
+extern void setup_replication_mask(int maxnodes);
+
+/* init.c */
+extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
+extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
+extern void init_platform_pda(cpuid_t cpu);
+extern void per_cpu_init(void);
+#ifdef	LATER
+extern cpumask_t boot_cpumask;
+#endif
+extern int is_fine_dirmode(void);
+extern void update_node_information(cnodeid_t);
+ 
+#ifdef	LATER
+/* clksupport.c */
+extern void early_counter_intr(eframe_t *);
+#endif
+
+/* hubio.c */
+extern void hubio_init(void);
+extern void hub_merge_clean(nasid_t nasid);
+extern void hub_set_piomode(nasid_t nasid, int conveyor);
+
+/* huberror.c */
+extern void hub_error_init(cnodeid_t);
+extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
+extern void hubni_error_handler(char *, int);
+extern int check_ni_errors(void);
+
+/* Used for debugger to signal upper software a breakpoint has taken place */
+
+extern void		*debugger_update;
+extern __psunsigned_t	debugger_stopped;
+
+/* 
+ * IP27 piomap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_piomap_s by generic xtalk routines.
+ */
+struct hub_piomap_s {
+	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
+	devfs_handle_t		hpio_hub;	/* which hub's mapping registers are set up */
+	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
+	char			hpio_bigwin_num;/* if big window map, which one */
+	int 			hpio_flags;	/* defined below */
+};
+/* hub_piomap flags */
+#define HUB_PIOMAP_IS_VALID		0x1
+#define HUB_PIOMAP_IS_BIGWINDOW		0x2
+#define HUB_PIOMAP_IS_FIXED		0x4
+
+#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
+#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
+#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
+
+#if TBD
+ /* Ensure that hpio_xtalk_info is first */
+ #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0)
+#endif
+
+
+/* 
+ * IP27 dmamap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_dmamap_s by generic xtalk routines.
+ */
+struct hub_dmamap_s {
+	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
+	devfs_handle_t		hdma_hub;	/* which hub we go through */
+	int			hdma_flags;	/* defined below */
+};
+/* hub_dmamap flags */
+#define HUB_DMAMAP_IS_VALID		0x1
+#define HUB_DMAMAP_USED			0x2
+#define	HUB_DMAMAP_IS_FIXED		0x4
+
+#if TBD
+ /* Ensure that hdma_xtalk_info is first */
+ #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0)
+#endif
+
+/* 
+ * IP27 interrupt handle, created by hub_intr_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_intr_s by generic xtalk routines.
+ */
+struct hub_intr_s {
+	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
+	ilvl_t			i_swlevel;	/* software level for blocking intr */
+	cpuid_t			i_cpuid;	/* which cpu */
+	int			i_bit;		/* which bit */
+	int			i_flags;
+};
+/* flag values */
+#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
+#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
+
+#if TBD
+ /* Ensure that i_xtalk_info is first */
+ #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0)
+#endif
+
+
+/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */
+/* TBD: IP27-dependent stuff currently in nodepda.h should be here */
+typedef struct hubinfo_s {
+	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
+	cnodeid_t			h_cnodeid;	/* compact nodeid */
+	nasid_t				h_nasid;	/* nasid */
+
+	/* structures for PIO management */
+	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
+	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
+	sv_t				h_bwwait;	/* wait for big window to free */
+	spinlock_t			h_bwlock;	/* guard big window piomap's */
+	spinlock_t			h_crblock;      /* gaurd CRB error handling */
+	int				h_num_big_window_fixed;	/* count number of FIXED maps */
+	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
+	hub_intr_t			hub_ii_errintr;
+} *hubinfo_t;
+
+#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
+
+#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
+
+#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
+
+/*
+ * Hub info PIO map access functions.
+ */
+#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
+			(&hinfo->h_big_window_piomap[win])
+#define	hubinfo_swin_piomap_get(hinfo, win)	\
+			(&hinfo->h_small_window_piomap[win])
+	
+/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */
+/* TBD: IP27-dependent stuff currently in pda.h should be here */
+typedef struct cpuinfo_s {
+#ifdef	LATER
+	pda_t		*ci_cpupda;	/* pointer to CPU's private data area */
+#endif
+	cpuid_t		ci_cpuid;	/* CPU ID */
+} *cpuinfo_t;
+
+#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
+
+#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
+
+/* Special initialization function for xswitch vertices created during startup. */
+extern void xswitch_vertex_init(devfs_handle_t xswitch);
+
+extern xtalk_provider_t hub_provider;
+
+/* du.c */
+int ducons_write(char *buf, int len);
+
+/* memerror.c */
+
+extern void install_eccintr(cpuid_t cpu);
+extern void memerror_get_stats(cnodeid_t cnode,
+			       int *bank_stats, int *bank_stats_max);
+extern void probe_md_errors(nasid_t);
+/* sysctlr.c */
+extern void sysctlr_init(void);
+extern void sysctlr_power_off(int sdonly);
+extern void sysctlr_keepalive(void);
+
+#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
+
+/* Useful definitions to get the memory dimm given a physical
+ * address.
+ */
+#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
+extern void membank_pathname_get(paddr_t,char *);
+
+/* To redirect the output into the error buffer */
+#define errbuf_print(_s)	printf("#%s",_s)
+
+extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
+void bootstrap(void);
+
+/* sndrv.c */
+extern int sndrv_attach(devfs_handle_t vertex);
+
+#endif /* _ASM_IA64_SN_SN1_SN_PRIVATE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/synergy.h lia64-2.4/include/asm-ia64/sn/sn1/synergy.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/synergy.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn1/synergy.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,185 @@
+#ifndef _ASM_IA64_SN_SN1_SYNERGY_H
+#define _ASM_IA64_SN_SN1_SYNERGY_H
+
+#include <linux/config.h>
+#include <asm/io.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/intr_public.h>
+
+
+/*
+ * Definitions for the synergy asic driver
+ * 
+ * These are for SGI platforms only.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#define SYNERGY_L4_BYTES		(64UL*1024*1024)
+#define SYNERGY_L4_WAYS			8
+#define SYNERGY_L4_BYTES_PER_WAY	(SYNERGY_L4_BYTES/SYNERGY_L4_WAYS)
+#define SYNERGY_BLOCK_SIZE		512UL
+
+
+#define SSPEC_BASE	(0xe0000000000UL)
+#define LB_REG_BASE	(SSPEC_BASE + 0x0)
+
+#define VEC_MASK3A_ADDR	(0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3B_ADDR	(0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3A	(0x2a0)
+#define VEC_MASK3B	(0x2a8)
+
+#define VEC_MASK2A_ADDR	(0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2B_ADDR	(0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2A	(0x2b0)
+#define VEC_MASK2B	(0x2b8)
+
+#define VEC_MASK1A_ADDR	(0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1B_ADDR	(0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1A	(0x2c0)
+#define VEC_MASK1B	(0x2c8)
+
+#define VEC_MASK0A_ADDR	(0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0B_ADDR	(0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0A	(0x2d0)
+#define VEC_MASK0B	(0x2d8)
+
+#define WRITE_LOCAL_SYNERGY_REG(addr, value)	__synergy_out(addr, value)
+
+#define HUB_L(_a)               *(_a)
+#define HUB_S(_a, _d)           *(_a) = (_d)
+
+#define HSPEC_SYNERGY0_0        0x04000000    /* Synergy0 Registers     */
+#define HSPEC_SYNERGY1_0        0x05000000    /* Synergy1 Registers     */
+#define HS_SYNERGY_STRIDE       (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
+#define REMOTE_HSPEC(_n, _x)    (HUBREG_CAST (RREG_BASE(_n) + (_x)))
+
+#define RREG_BASE(_n)           (NODE_LREG_BASE(_n))
+#define NODE_LREG_BASE(_n)      (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#ifndef HSPEC_BASE
+#define HSPEC_BASE              (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN)
+#endif
+#define SYN_UNCACHED_SPACE      0xc000000000000000
+#define HSPEC_BASE_SYN          0x00000b0000000000
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+#define NODE_SIZE_BITS		33
+
+#define SYN_TAG_DISABLE_WAY	(SSPEC_BASE+0xae0)
+
+
+#define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg))
+
+#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg)  __remote_synergy_in(nasid, fsb, reg)
+#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
+
+static inline uint64_t
+__remote_synergy_in(int nasid, int fsb, uint64_t reg) {
+	volatile uint64_t *addr;
+
+	addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg));
+	return (*addr);
+}
+
+static inline void
+__remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) {
+	volatile uint64_t *addr;
+
+        addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2)));
+        *(addr+0) = value >> 48;
+        *(addr+1) = value >> 32;
+        *(addr+2) = value >> 16;
+        *(addr+3) = value;
+        __ia64_mf_a();
+}
+
+/* XX this doesn't make a lot of sense. Which fsb?  */
+static inline void
+__synergy_out(unsigned long addr, unsigned long value)
+{
+	volatile unsigned long *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	*adr = value;
+	__ia64_mf_a();
+}
+
+#define READ_LOCAL_SYNERGY_REG(addr)	__synergy_in(addr)
+
+/* XX this doesn't make a lot of sense. Which fsb? */
+static inline unsigned long
+__synergy_in(unsigned long addr)
+{
+	unsigned long ret, *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	ret = *adr;
+	__ia64_mf_a();
+	return ret;
+}
+
+struct sn1_intr_action {
+	void (*handler)(int, void *, struct pt_regs *);
+	void *intr_arg;
+	unsigned long flags;
+	struct sn1_intr_action * next;
+};
+
+typedef struct synergy_da_s {
+	hub_intmasks_t	s_intmasks;
+}synergy_da_t;
+
+struct sn1_cnode_action_list {
+	spinlock_t action_list_lock;
+	struct sn1_intr_action *action_list;
+};
+
+/*
+ * ioctl cmds for node/hub/synergy/[01]/mon for synergy
+ * perf monitoring are defined in sndrv.h
+ */
+
+/* multiplex the counters every 10 timer interrupts */ 
+#define SYNERGY_PERF_FREQ_DEFAULT 10
+
+/* macros for synergy "mon" device ioctl handler */
+#define SYNERGY_PERF_INFO(_s, _f)	(arbitrary_info_t)(((_s) << 16)|(_f))
+#define SYNERGY_PERF_INFO_CNODE(_x)	(cnodeid_t)(((uint64_t)_x) >> 16)
+#define SYNERGY_PERF_INFO_FSB(_x)	(((uint64_t)_x) & 1)
+
+/* synergy perf control registers */
+#define PERF_CNTL0_A            0xab0UL /* control A on FSB0 */
+#define PERF_CNTL0_B            0xab8UL /* control B on FSB0 */
+#define PERF_CNTL1_A            0xac0UL /* control A on FSB1 */
+#define PERF_CNTL1_B            0xac8UL /* control B on FSB1 */
+
+/* synergy perf counters */
+#define PERF_CNTR0_A            0xad0UL /* counter A on FSB0 */
+#define PERF_CNTR0_B            0xad8UL /* counter B on FSB0 */
+#define PERF_CNTR1_A            0xaf0UL /* counter A on FSB1 */
+#define PERF_CNTR1_B            0xaf8UL /* counter B on FSB1 */
+
+/* Synergy perf data. Each nodepda keeps a list of these */
+struct synergy_perf_s {
+        uint64_t        intervals;      /* count of active intervals for this event */
+        uint64_t        total_intervals;/* snapshot of total intervals */
+        uint64_t        modesel;        /* mode and sel bits, both A and B registers */
+        struct synergy_perf_s *next;	/* next in circular linked list */
+        uint64_t        counts[2];      /* [0] is synergy-A counter, [1] synergy-B counter */
+};
+
+typedef struct synergy_perf_s synergy_perf_t;
+
+typedef struct synergy_info_s synergy_info_t;
+
+extern void synergy_perf_init(void);
+extern void synergy_perf_update(int);
+extern struct file_operations synergy_mon_fops;
+
+#endif /* _ASM_IA64_SN_SN1_SYNERGY_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn1/uart16550.h lia64-2.4/include/asm-ia64/sn/sn1/uart16550.h
--- linux-2.4.16/include/asm-ia64/sn/sn1/uart16550.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn1/uart16550.h	Wed Dec 31 16:00:00 1969
@@ -1,228 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef _ASM_SN_SN1_UART16550_H
-#define _ASM_SN_SN1_UART16550_H
-
-
-/*
- * Definitions for 16550  chip
- */
-
-	/* defined as offsets from the data register */
-#define REG_DAT     0   /* receive/transmit data */
-#define REG_ICR     1   /* interrupt control register */
-#define REG_ISR     2   /* interrupt status register */
-#define REG_FCR     2   /* fifo control register */
-#define REG_LCR     3   /* line control register */
-#define REG_MCR     4   /* modem control register */
-#define REG_LSR     5   /* line status register */
-#define REG_MSR     6   /* modem status register */
-#define REG_SCR     7   /* Scratch register      */
-#define REG_DLL     0   /* divisor latch (lsb) */
-#define REG_DLH     1   /* divisor latch (msb) */
-#define REG_EFR		2	/* 16650 enhanced feature register */
-
-/*
- * 16450/16550 Registers Structure.
- */
-
-/* Line Control Register */
-#define		LCR_WLS0	0x01	/*word length select bit 0 */	
-#define		LCR_WLS1	0x02	/*word length select bit 2 */	
-#define		LCR_STB	0x04		/* number of stop bits */
-#define		LCR_PEN	0x08		/* parity enable */
-#define		LCR_EPS	0x10		/* even parity select */
-#define		LCR_SETBREAK 0x40	/* break key */
-#define		LCR_DLAB	0x80	/* divisor latch access bit */
-#define 	LCR_RXLEN   0x03    /* # of data bits per received/xmitted char */
-#define 	LCR_STOP1   0x00
-#define 	LCR_STOP2   0x04
-#define 	LCR_PAREN   0x08
-#define 	LCR_PAREVN  0x10
-#define 	LCR_PARMARK 0x20
-#define 	LCR_SNDBRK  0x40
-#define 	LCR_DLAB    0x80
-
-
-#define		LCR_BITS5	0x00	/* 5 bits per char */
-#define		LCR_BITS6	0x01	/* 6 bits per char */
-#define		LCR_BITS7	0x02	/* 7 bits per char */
-#define		LCR_BITS8	0x03	/* 8 bits per char */
-
-#define		LCR_MASK_BITS_CHAR 		0x03
-#define 	LCR_MASK_STOP_BITS		0x04
-#define		LCR_MASK_PARITY_BITS	0x18
-
-
-/* Line Status Register */
-#define		LSR_RCA	0x01		/* data ready */
-#define		LSR_OVRRUN	0x02	/* overrun error */
-#define		LSR_PARERR	0x04	/* parity error */
-#define		LSR_FRMERR	0x08	/* framing error */
-#define		LSR_BRKDET 	0x10	/* a break has arrived */
-#define		LSR_XHRE	0x20	/* tx hold reg is now empty */
-#define		LSR_XSRE	0x40	/* tx shift reg is now empty */
-#define		LSR_RFBE	0x80	/* rx FIFO Buffer error */
-
-/* Interrupt Status Regisger */
-#define		ISR_MSTATUS	0x00
-#define		ISR_TxRDY	0x02
-#define		ISR_RxRDY	0x04
-#define		ISR_ERROR_INTR	0x08
-#define		ISR_FFTMOUT 0x0c	/* FIFO Timeout */
-#define		ISR_RSTATUS 0x06	/* Receiver Line status */
-
-/* Interrupt Enable Register */
-#define		ICR_RIEN	0x01	/* Received Data Ready */
-#define		ICR_TIEN	0x02	/* Tx Hold Register Empty */
-#define		ICR_SIEN	0x04	/* Receiver Line Status */
-#define		ICR_MIEN	0x08	/* Modem Status */
-
-/* Modem Control Register */
-#define		MCR_DTR		0x01	/* Data Terminal Ready */
-#define		MCR_RTS		0x02	/* Request To Send */
-#define		MCR_OUT1	0x04	/* Aux output - not used */
-#define		MCR_OUT2	0x08	/* turns intr to 386 on/off */	
-#define		MCR_LOOP	0x10	/* loopback for diagnostics */
-#define		MCR_AFE 	0x20	/* Auto flow control enable */
-
-/* Modem Status Register */
-#define		MSR_DCTS	0x01	/* Delta Clear To Send */
-#define		MSR_DDSR	0x02	/* Delta Data Set Ready */
-#define		MSR_DRI		0x04	/* Trail Edge Ring Indicator */
-#define		MSR_DDCD	0x08	/* Delta Data Carrier Detect */
-#define		MSR_CTS		0x10	/* Clear To Send */
-#define		MSR_DSR		0x20	/* Data Set Ready */
-#define		MSR_RI		0x40	/* Ring Indicator */
-#define		MSR_DCD		0x80	/* Data Carrier Detect */
-
-#define 	DELTAS(x) 	((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD))
-#define 	STATES(x) 	((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD))
-
-
-#define		FCR_FIFOEN	0x01	/* enable receive/transmit fifo */
-#define		FCR_RxFIFO	0x02	/* enable receive fifo */
-#define		FCR_TxFIFO	0x04	/* enable transmit fifo */
-#define 	FCR_MODE1	0x08	/* change to mode 1 */
-#define		RxLVL0		0x00	/* Rx fifo level at 1	*/
-#define		RxLVL1		0x40	/* Rx fifo level at 4 */
-#define		RxLVL2		0x80	/* Rx fifo level at 8 */
-#define		RxLVL3		0xc0	/* Rx fifo level at 14 */
-
-#define 	FIFOEN		(FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 
-
-#define		FCT_TxMASK	0x30	/* mask for Tx trigger */
-#define		FCT_RxMASK	0xc0	/* mask for Rx trigger */
-
-/* enhanced festures register */
-#define		EFR_SFLOW	0x0f	/* various S/w Flow Controls */
-#define 	EFR_EIC		0x10	/* Enhanced Interrupt Control bit */
-#define 	EFR_SCD		0x20	/* Special Character Detect */
-#define 	EFR_RTS		0x40	/* RTS flow control */
-#define 	EFR_CTS		0x80	/* CTS flow control */
-
-/* Rx Tx software flow controls in 16650 enhanced mode */
-#define		SFLOW_Tx0	0x00	/* no Xmit flow control */
-#define		SFLOW_Tx1	0x08	/* Transmit Xon1, Xoff1 */
-#define		SFLOW_Tx2	0x04	/* Transmit Xon2, Xoff2 */
-#define		SFLOW_Tx3	0x0c	/* Transmit Xon1,Xon2, Xoff1,Xoff2 */
-#define		SFLOW_Rx0	0x00	/* no Rcv flow control */
-#define		SFLOW_Rx1	0x02	/* Receiver compares Xon1, Xoff1 */
-#define		SFLOW_Rx2	0x01	/* Receiver compares Xon2, Xoff2 */
-
-#define	ASSERT_DTR(x)		(x |= MCR_DTR)
-#define	ASSERT_RTS(x)		(x |= MCR_RTS)
-#define DU_RTS_ASSERTED(x)  (((x) & MCR_RTS) != 0)
-#define DU_RTS_ASSERT(x)    ((x) |= MCR_RTS)
-#define DU_RTS_DEASSERT(x)  ((x) &= ~MCR_RTS)
-
-
-/*
- * ioctl(fd, I_STR, arg)
- * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI
- */
-#define SIOC        ('z' << 8)  /* z for z85130 */
-#define SIOC_EXTCLK (SIOC | 1)  /* select/de-select external clock */
-#define SIOC_RS422  (SIOC | 2)  /* select/de-select RS422 protocol */
-#define SIOC_ITIMER (SIOC | 3)  /* upstream timer adjustment */
-#define SIOC_LOOPBACK   (SIOC | 4)  /* diagnostic loopback test mode */
-
-
-/* channel control register */
-#define	DMA_INT_MASK		0xe0	/* ring intr mask */
-#define DMA_INT_TH25		0x20	/* 25% threshold */
-#define DMA_INT_TH50		0x40	/* 50% threshold */
-#define DMA_INT_TH75		0x60	/* 75% threshold */
-#define DMA_INT_EMPTY		0x80	/* ring buffer empty */
-#define DMA_INT_NEMPTY		0xa0	/* ring buffer not empty */
-#define DMA_INT_FULL		0xc0	/* ring buffer full */
-#define DMA_INT_NFULL		0xe0	/* ring buffer not full */
-
-#define DMA_CHANNEL_RESET	0x400	/* reset dma channel */
-#define DMA_ENABLE			0x200	/* enable DMA */
-
-/* peripheral controller intr status bits applicable to serial ports */
-#define ISA_SERIAL0_MASK 		0x03f00000	/* mask for port #1 intrs */
-#define ISA_SERIAL0_DIR			0x00100000	/* device intr request */
-#define ISA_SERIAL0_Tx_THIR		0x00200000	/* Transmit DMA threshold */
-#define ISA_SERIAL0_Tx_PREQ		0x00400000	/* Transmit DMA pair req */
-#define ISA_SERIAL0_Tx_MEMERR	0x00800000	/* Transmit DMA memory err */
-#define ISA_SERIAL0_Rx_THIR		0x01000000	/* Receive DMA threshold  */
-#define ISA_SERIAL0_Rx_OVERRUN	0x02000000	/* Receive DMA over-run  */
-
-#define ISA_SERIAL1_MASK 		0xfc000000	/* mask for port #1 intrs */
-#define ISA_SERIAL1_DIR			0x04000000	/* device intr request */
-#define ISA_SERIAL1_Tx_THIR		0x08000000	/* Transmit DMA threshold */
-#define ISA_SERIAL1_Tx_PREQ		0x10000000	/* Transmit DMA pair req */
-#define ISA_SERIAL1_Tx_MEMERR	0x20000000	/* Transmit DMA memory err */
-#define ISA_SERIAL1_Rx_THIR		0x40000000	/* Receive DMA threshold  */
-#define ISA_SERIAL1_Rx_OVERRUN	0x80000000	/* Receive DMA over-run  */
-
-#define MAX_RING_BLOCKS		128			/* 4096/32 */
-#define MAX_RING_SIZE		4096
-
-/* DMA Input Control Byte */
-#define	DMA_IC_OVRRUN	0x01	/* overrun error */
-#define	DMA_IC_PARERR	0x02	/* parity error */
-#define	DMA_IC_FRMERR	0x04	/* framing error */
-#define	DMA_IC_BRKDET 	0x08	/* a break has arrived */
-#define DMA_IC_VALID	0x80	/* pair is valid */
-
-/* DMA Output Control Byte */
-#define DMA_OC_TxINTR	0x20	/* set Tx intr after processing byte */
-#define DMA_OC_INVALID	0x00	/* invalid pair */
-#define DMA_OC_WTHR		0x40	/* Write byte to THR */
-#define DMA_OC_WMCR		0x80	/* Write byte to MCR */
-#define DMA_OC_DELAY	0xc0	/* time delay before next xmit */
-
-/* ring id's */
-#define RID_SERIAL0_TX	0x4		/* serial port 0, transmit ring buffer */
-#define RID_SERIAL0_RX	0x5		/* serial port 0, receive ring buffer */
-#define RID_SERIAL1_TX	0x6		/* serial port 1, transmit ring buffer */
-#define RID_SERIAL1_RX	0x7		/* serial port 1, receive ring buffer */
-
-#define CLOCK_XIN			22
-#define PRESCALER_DIVISOR	3
-#define CLOCK_ACE			7333333
-
-/*
- * increment the ring offset. One way to do this would be to add b'100000.
- * this would let the offset value roll over automatically when it reaches
- * its maximum value (127). However when we use the offset, we must use
- * the appropriate bits only by masking with 0xfe0.
- * The other option is to shift the offset right by 5 bits and look at its
- * value. Then increment if required and shift back
- * note: 127 * 2^5 = 4064
- */
-#define INC_RING_POINTER(x) \
-	( ((x & 0xffe0) < 4064) ? (x += 32) : 0 )
-
-#endif /* _ASM_SN_SN1_UART16550_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/addrs.h lia64-2.4/include/asm-ia64/sn/sn2/addrs.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/addrs.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/addrs.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,153 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_ADDRS_H
+#define _ASM_IA64_SN_SN2_ADDRS_H
+
+/* McKinley Address Format:
+ *
+ *   4 4       3 3  3 3
+ *   9 8       8 7  6 5             0
+ *  +-+---------+----+--------------+
+ *  |0| Node ID | AS | Node Offset  |
+ *  +-+---------+----+--------------+
+ *
+ *   Node ID: If bit 38 = 1, is ICE, else is SHUB
+ *   AS: Address Space Identifier. Used only if bit 38 = 0.
+ *     b'00: Local Resources and MMR space
+ *           bit 35
+ *               0: Local resources space
+ *                  node id:
+ *                        0: IA64/NT compatibility space
+ *                        2: Local MMR Space
+ *                        4: Local memory, regardless of local node id
+ *               1: Global MMR space
+ *     b'01: GET space.
+ *     b'10: AMO space.
+ *     b'11: Cacheable memory space.
+ *
+ *   NodeOffset: byte offset
+ */
+
+#ifndef __ASSEMBLY__
+typedef union ia64_sn2_pa {
+	struct {
+		unsigned long off  : 36;
+		unsigned long as   : 2;
+		unsigned long nasid: 11;
+		unsigned long fill : 15;
+	} f;
+	unsigned long l;
+	void *p;
+} ia64_sn2_pa_t;
+#endif
+
+#define TO_PHYS_MASK		0x0001ffcfffffffff	/* Note - clear AS bits */
+
+
+/* Regions determined by AS */
+#define LOCAL_MMR_SPACE		0xc000008000000000	/* Local MMR space */
+#define LOCAL_MEM_SPACE		0xc000010000000000	/* Local Memory space */
+#define GLOBAL_MMR_SPACE	0xc000000800000000	/* Global MMR space */
+#define GET_SPACE		0xc000001000000000	/* GET space */
+#define AMO_SPACE		0xc000002000000000	/* AMO space */
+#define CACHEABLE_MEM_SPACE	0xe000003000000000	/* Cacheable memory space */
+#define UNCACHED                0xc000000000000000      /* UnCacheable memory space */
+
+/* SN2 address macros */
+#define NID_SHFT		38
+#define LOCAL_MMR_ADDR(a)	(UNCACHED | LOCAL_MMR_SPACE | (a))
+#define LOCAL_MEM_ADDR(a)	(LOCAL_MEM_SPACE | (a))
+#define REMOTE_ADDR(n,a)	((((unsigned long)(n))<<NID_SHFT) | (a))
+#define GLOBAL_MMR_ADDR(n,a)	(UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GET_ADDR(n,a)		(GET_SPACE | REMOTE_ADDR(n,a))
+#define AMO_ADDR(n,a)		(UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_MEM_ADDR(n,a)	(CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a))
+
+/* non-II mmr's start at top of big window space (4G) */
+#define BWIN_TOP		0x0000000100000000
+
+/*
+ * general address defines - for code common to SN0/SN1/SN2
+ */
+#define CAC_BASE		CACHEABLE_MEM_SPACE			/* cacheable memory space */
+#define IO_BASE			(UNCACHED | GLOBAL_MMR_SPACE)		/* lower 4G maps II's XIO space */
+#define AMO_BASE		(UNCACHED | AMO_SPACE)			/* fetch & op space */
+#define MSPEC_BASE		AMO_BASE				/* fetch & op space */
+#define UNCAC_BASE		(UNCACHED | CACHEABLE_MEM_SPACE)	/* uncached global memory */
+#define GET_BASE		GET_SPACE				/* momentarily coherent remote mem. */
+#define CALIAS_BASE             LOCAL_CACHEABLE_BASE			/* cached node-local memory */
+#define UALIAS_BASE             (UNCACHED | LOCAL_CACHEABLE_BASE)	/* uncached node-local memory */
+
+#define TO_PHYS(x)              (              ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE    | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE  | ((x) & TO_PHYS_MASK))
+#define TO_MSPEC(x)             (MSPEC_BASE  | ((x) & TO_PHYS_MASK))
+#define TO_GET(x)		(GET_BASE    | ((x) & TO_PHYS_MASK))
+#define TO_CALIAS(x)            (CALIAS_BASE | TO_NODE_ADDRSPACE(x))
+#define TO_UALIAS(x)            (UALIAS_BASE | TO_NODE_ADDRSPACE(x))
+#define NODE_SIZE_BITS		36	/* node offset : bits <35:0> */
+#define BWIN_SIZE_BITS		29	/* big window size: 512M */
+#define NASID_BITS		11	/* bits <48:38> */
+#define NASID_BITMASK		(0x7ffULL)
+#define NASID_SHFT		NID_SHFT
+#define NASID_META_BITS		0	/* ???? */
+#define NASID_LOCAL_BITS	7	/* same router as SN1 */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#define CHANGE_NASID(n,x)	({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;})
+
+#ifndef __ASSEMBLY__
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+#define LOCAL_SWIN_BASE(widget) \
+	(UNCACHED | LOCAL_MMR_SPACE | ((UINT64_CAST (widget) << SWIN_SIZE_BITS)))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+#endif	/* _ASM_IA64_SN_SN2_ADDRS_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/arch.h lia64-2.4/include/asm-ia64/sn/sn2/arch.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/arch.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/arch.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,67 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_ARCH_H
+#define _ASM_IA64_SN_SN2_ARCH_H
+
+#include <linux/config.h>
+#include <asm/types.h>
+
+
+#define CPUS_PER_NODE           4       /* CPUs on a single hub */
+#define CPUS_PER_SUBNODE        4       /* CPUs on a single hub PI */
+
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              2048
+
+
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ * This is not necessarily the same as MAX_NASIDS.
+ */
+#define MAX_COMPACT_NODES       128
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define	MAX_REGIONS		64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined 
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS		MAX_REGIONS
+
+
+#define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
+
+
+/*
+ * 1 FSB per SHUB, with up to 4 cpus per FSB.
+ */
+#define NUM_SUBNODES	1
+#define SUBNODE_SHFT	0
+#define SUBNODE_MASK	(0x0 << SUBNODE_SHFT)
+#define LOCALCPU_SHFT	0
+#define LOCALCPU_MASK	(0x3 << LOCALCPU_SHFT)
+#define SUBNODE(slice)	(((slice) & SUBNODE_MASK) >> SUBNODE_SHFT)
+#define LOCALCPU(slice)	(((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT)
+#define TO_SLICE(subn, local)	(((subn) << SUBNODE_SHFT) | \
+				 ((local) << LOCALCPU_SHFT))
+
+typedef u64 mmr_t;
+
+#endif /* _ASM_IA64_SN_SN2_ARCH_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/intr.h lia64-2.4/include/asm-ia64/sn/sn2/intr.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/intr.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/intr.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,16 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_INTR_H
+#define _ASM_IA64_SN_SN2_INTR_H
+#define SGI_UART_VECTOR (0xe9)
+#define SGI_SHUB_ERROR_VECTOR   (0xea)
+#define SN2_IRQ_RESERVED        (0x1)
+#define SN2_IRQ_CONNECTED       (0x2)
+
+#endif /* _ASM_IA64_SN_SN2_INTR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/mmzone_sn2.h lia64-2.4/include/asm-ia64/sn/sn2/mmzone_sn2.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/mmzone_sn2.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/mmzone_sn2.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,166 @@
+#ifndef _ASM_IA64_SN_MMZONE_SN2_H
+#define _ASM_IA64_SN_MMZONE_SN2_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/sn/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+
+
+/*
+ * SGI SN2 Arch defined values
+ *
+ * 	An SN2 physical address is broken down as follows:
+ *
+ *             +-----------------------------------------+
+ *             |         |      |    |   node offset     |
+ *             | unused  | node | AS |-------------------|
+ *             |         |      |    | cn | clump offset |
+ *             +-----------------------------------------+
+ *              6       4 4    3 3  3 3  3 3            0
+ *              3       9 8    8 7  6 5  4 3            0
+ *
+ *		bits 63-49	Unused - must be zero
+ *		bits 48-38	Node number. Note that some configurations do NOT
+ *				have a node zero.
+ *		bits 37-36	Address space ID. Cached memory has a value of 3 (!!!).
+ *				Chipset & IO addresses have other values.
+ *				  (Yikes!! The hardware folks hate us...)
+ *		bits 35-0	Node offset.
+ *
+ *	The node offset can be further broken down as:
+ *		bits 35-34	Clump (bank) number.
+ *		bits 33-0	Clump (bank) offset.
+ *
+ *	A node consists of up to 4 clumps (banks) of memory. A clump may be empty, or may be
+ *	populated with a single contiguous block of memory starting at clump
+ *	offset 0. The size of the block is (2**n) * 64MB, where 0<n<9.
+ *
+ *	Important notes:
+ *		- IO space addresses are embedded with the range of valid memory addresses.
+ *		- All cached memory addresses have bits 36 & 37 set to 1's.
+ *		- There is no physical address 0.
+ *
+ * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with
+ *	 "SN_" are intended for internal use only and should not be used in
+ *	 any platform independent code. 
+ *
+ *	 This file is also responsible for exporting the following definitions:
+ *		cnodeid_t	Define a compact node id. 
+ */
+
+#define SN2_BANKS_PER_NODE		4
+#define SN2_NODE_SIZE			(64UL*1024*1024*1024)	/* 64GB per node */
+#define SN2_BANK_SIZE			(SN2_NODE_SIZE/SN2_BANKS_PER_NODE)
+#define SN2_NODE_SHIFT			38
+#define SN2_NODE_MASK			0x7ffUL
+#define SN2_NODE_OFFSET_MASK		(SN2_NODE_SIZE-1)
+#define SN2_NODE_NUMBER(addr)		(((unsigned long)(addr) >> SN2_NODE_SHIFT) & SN2_NODE_MASK)
+#define SN2_NODE_CLUMP_NUMBER(kaddr)	(((unsigned long)(kaddr) >>34) & 3)
+#define SN2_NODE_OFFSET(addr)		(((unsigned long)(addr)) & SN2_NODE_OFFSET_MASK)
+#define SN2_KADDR(nasid, offset)	(((unsigned long)(nasid)<<SN2_NODE_SHIFT) | (offset) | SN2_PAGE_OFFSET)
+#define SN2_PAGE_OFFSET			0xe000003000000000UL      /* Cacheable memory space */
+
+
+#define PLAT_MAX_NODE_NUMBER		MAX_NASIDS			/* Maximum node number + 1 */
+#define PLAT_MAX_COMPACT_NODES		MAX_COMPACT_NODES		/* Maximum number of nodes in SSI system */
+
+#define PLAT_MAX_PHYS_MEMORY		(1UL << 49)
+
+
+
+/*
+ * On the SN platforms, a clump is the same as a memory bank.
+ */
+#define PLAT_CLUMPS_PER_NODE		SN2_BANKS_PER_NODE
+#define PLAT_CLUMP_OFFSET(addr)		((unsigned long)(addr) & 0x3ffffffffUL)
+#define PLAT_CLUMPSIZE			(SN2_NODE_SIZE/PLAT_CLUMPS_PER_NODE)
+#define PLAT_MAXCLUMPS			(PLAT_CLUMPS_PER_NODE * PLAT_MAX_COMPACT_NODES)
+
+
+
+/*
+ * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a
+ * valid cacheable identity mapped RAM memory address.
+ * Note that the RAM may or may not actually be present!!
+ */
+#define SN2_VALID_KERN_ADDR_MASK	0xffff003000000000UL
+#define SN2_VALID_KERN_ADDR_VALUE	0xe000003000000000UL
+#define PLAT_VALID_MEM_KADDR(kaddr)	(((unsigned long)(kaddr) & SN2_VALID_KERN_ADDR_MASK) == SN2_VALID_KERN_ADDR_VALUE)
+
+
+
+/*
+ * Memory is conceptually divided into chunks. A chunk is either
+ * completely present, or else the kernel assumes it is completely
+ * absent. Each node consists of a number of possibly contiguous chunks.
+ */
+#define SN2_CHUNKSHIFT			25			/* 32 MB */
+#define SN2_CHUNKSIZE			(1UL << SN2_CHUNKSHIFT)
+#define PLAT_CHUNKNUM(addr)		({unsigned long _p=(unsigned long)(addr);		\
+						(((_p&SN2_NODE_MASK)>>2) | 			\
+						(_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;})
+
+/*
+ * Given a kaddr, find the nid (compact nodeid)
+ */
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+#define DISCONBUG(kaddr)		panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx",	 	\
+						__LINE__, __FILE__, (long)(kaddr))
+
+#define KVADDR_TO_NID(kaddr)		({long _ktn=(long)(kaddr);					\
+						kern_addr_valid(_ktn) ? 				\
+						NODEDIR->physical_node_map[SN2_NODE_NUMBER(_ktn)] :	\
+						(DISCONBUG(_ktn), 0UL);})
+#else
+#define KVADDR_TO_NID(kaddr)		(NODEDIR->physical_node_map[SN2_NODE_NUMBER(kaddr)])
+#endif
+
+
+
+/*
+ * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry 
+ * for the first page of the clump.
+ */
+#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr)		({long _kmmi=(long)(kaddr);				\
+							KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE +	\
+							SN2_NODE_CLUMP_NUMBER(_kmmi);})
+
+
+
+/*
+ * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on
+ * nodes so that they dont alias to the same line in the cache as the previous allocated structure.
+ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & 
+ * changes the node number.
+ */
+#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr)	SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]),       \
+						 (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)
+
+
+
+
+/*
+ * Convert a proximity domain number (from the ACPI tables) into a physical node number.
+ *	Note: on SN2, the promity domain number is the same as bits [8:1] of the NASID. The following
+ *	algorithm relies on:
+ *		- bit 0 of the NASID for cpu nodes is always 0
+ *		- bits [10:9] of all NASIDs in a partition are always the same
+ *		- hard_smp_processor_id return the SAPIC of the current cpu &
+ *			bits 0..11 contain the NASID.
+ *
+ *	All of this complexity is because MS architectually limited proximity domain numbers to
+ *	8 bits. 
+ */
+
+#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm)	(((pxm)<<1) | (hard_smp_processor_id() & 0x300))
+
+#endif /* _ASM_IA64_SN_MMZONE_SN2_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/shub.h lia64-2.4/include/asm-ia64/sn/sn2/shub.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/shub.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/shub.h	Mon Nov 26 18:07:20 2001
@@ -0,0 +1,44 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_H
+#define _ASM_IA64_SN_SN2_SHUB_H
+
+#include <asm/sn/sn2/shub_mmr.h>		/* shub mmr addresses and formats */
+#include <asm/sn/sn2/shub_md.h>	
+#include <asm/sn/sn2/shubio.h>	
+#ifndef __ASSEMBLY__
+#include <asm/sn/sn2/shub_mmr_t.h>		/* shub mmr struct defines */
+#endif
+
+/*
+ * Junk Bus Address Space
+ *   The junk bus is used to access the PROM, LED's, and UART. It's 
+ *   accessed through the local block MMR space. The data path is
+ *   16 bits wide. This space requires address bits 31-27 to be set, and
+ *   is further divided by address bits 26:15.
+ *   The LED addresses are write-only. To read the LEDs, you need to use
+ *   SH_JUNK_BUS_LED0-3, defined in shub_mmr.h
+ *		
+ */
+#define SH_REAL_JUNK_BUS_LED0           0x7fed00000
+#define SH_REAL_JUNK_BUS_LED1           0x7fed10000
+#define SH_REAL_JUNK_BUS_LED2           0x7fed20000
+#define SH_REAL_JUNK_BUS_LED3           0x7fed30000
+#define SH_JUNK_BUS_UART0               0x7fed40000
+#define SH_JUNK_BUS_UART1               0x7fed40008
+#define SH_JUNK_BUS_UART2               0x7fed40010
+#define SH_JUNK_BUS_UART3               0x7fed40018
+#define SH_JUNK_BUS_UART4               0x7fed40020
+#define SH_JUNK_BUS_UART5               0x7fed40028
+#define SH_JUNK_BUS_UART6               0x7fed40030
+#define SH_JUNK_BUS_UART7               0x7fed40038
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/shub_md.h lia64-2.4/include/asm-ia64/sn/sn2/shub_md.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/shub_md.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/shub_md.h	Mon Nov 19 23:22:57 2001
@@ -0,0 +1,278 @@
+/**************************************************************************
+ *                                                                        *
+ *  Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.        *
+ *                                                                        *
+ *  These coded instructions, statements, and computer programs  contain  *
+ *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
+ *  are protected by Federal copyright law.  They  may  not be disclosed  *
+ *  to  third  parties  or copied or duplicated in any form, in whole or  *
+ *  in part, without the prior written consent of Silicon Graphics, Inc.  *
+ *                                                                        *
+ **************************************************************************/
+
+#ifndef _SHUB_MD_H
+#define _SHUB_MD_H
+
+/* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced, 
+   contiguous regions, or "software banks".  On SN2, software bank n begins at 
+   addresses n * 16GB, 0 <= n < 4.  Each bank has a 16GB address space.  If 
+   the 4 dimms do not use up this space there will be holes between the 
+   banks.  Even with these holes the whole memory space within a bank is
+   not addressable address space.  The top 1/32 of each bank is directory
+   memory space and is accessible through bist only.
+
+   Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets
+   each.  A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms 
+   each.  The data is stripped across the 4 memory busses so all dimms within 
+   a dimm bank must have identical capacity dimms.  Memory is increased or 
+   decreased in sets of 4.  Each dimm bank has 2 dimms on each side.
+
+             Physical Dimm Bank layout.
+                  DTR Card0
+                 ------------
+   Dimm Bank 3   |  MemYL3  |   CS 3
+                 |  MemXL3  |
+                 |----------|
+   Dimm Bank 2   |  MemYL2  |   CS 2
+                 |  MemXL2  |
+                 |----------|
+   Dimm Bank 1   |  MemYL1  |   CS 1
+                 |  MemXL1  |
+                 |----------|
+   Dimm Bank 0   |  MemYL0  |   CS 0 
+                 |  MemXL0  |
+                 ------------
+                  |       |
+                  BUS     BUS
+                  XL      YL
+                  |       |
+                 ------------
+                 |   SHUB   |
+                 |    MD    |
+                 ------------
+                  |       |
+                  BUS     BUS
+                  XR      YR
+                  |       |
+                 ------------
+   Dimm Bank 0   |  MemXR0  |   CS 0
+                 |  MemYR0  |
+                 |----------|
+   Dimm Bank 1   |  MemXR1  |   CS 1
+                 |  MemYR1  |
+                 |----------|
+   Dimm Bank 2   |  MemXR2  |   CS 2
+                 |  MemYR2  |
+                 |----------|
+   Dimm Bank 3   |  MemXR3  |   CS 3
+                 |  MemYR3  |
+                 ------------
+                  DTR Card1
+
+   The dimms can be 1 or 2 sided dimms.  The size and bankness is defined  
+   separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register.
+
+   Normally software bank 0 would map directly to physical dimm bank 0.  The 
+   software banks can map to the different physical dimm banks via the 
+   DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot.   
+
+   All the PROM's data structures (promlog variables, klconfig, etc.)
+   track memory by the physical dimm bank number.  The kernel usually
+   tracks memory by the software bank number.
+
+ */
+
+
+/* Preprocessor macros */
+#define MD_MEM_BANKS		4
+#define MD_PHYS_BANKS_PER_DIMM  2                  /* dimms may be 2 sided. */
+#define MD_NUM_PHYS_BANKS       (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM)
+#define MD_DIMMS_IN_SLOT	4  /* 4 dimms in each dimm bank.  aka slot */
+
+/* Address bits 35,34 control dimm bank access. */
+#define MD_BANK_SHFT       	34     
+#define MD_BANK_MASK       	(UINT64_CAST 0x3 << MD_BANK_SHFT )
+#define MD_BANK_GET(addr)  	(((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define MD_BANK_SIZE       	(UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */
+#define MD_BANK_OFFSET(_b) 	(UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*Address bit 12 selects side of dimm if 2bnk dimms present. */
+#define MD_PHYS_BANK_SEL_SHFT   12
+#define MD_PHYS_BANK_SEL_MASK   (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT)
+
+/* Address bit 7 determines if data resides on X or Y memory system. 
+ * If addr Bit 7 is set the data resides on Y memory system and
+ * the corresponing directory entry reside on the X. 
+ */
+#define MD_X_OR_Y_SEL_SHFT	7	
+#define MD_X_OR_Y_SEL_MASK	(1 << MD_X_OR_Y_SEL_SHFT)	
+
+/* Address bit 8 determines which directory entry of the pair the address
+ * corresponds to.  If addr Bit 8 is set DirB corresponds to the memory address.
+ */
+#define MD_DIRA_OR_DIRB_SEL_SHFT	8
+#define MD_DIRA_OR_DIRB_SEL_MASK  	(1 << MD_DIRA_OR_DIRB_SEL_SHFT)	
+
+/* Address bit 11 determines if corresponding directory entry resides 
+ * on Left or Right memory bus.  If addr Bit 11 is set the corresponding 
+ * directory entry resides on Right memory bus.
+ */
+#define MD_L_OR_R_SEL_SHFT	11
+#define MD_L_OR_R_SEL_MASK	(1 << MD_L_OR_R_SEL_SHFT)	
+
+/* DRAM sizes. */
+#define MD_SZ_64_Mb		0x0
+#define MD_SZ_128_Mb		0x1
+#define MD_SZ_256_Mb		0x2
+#define MD_SZ_512_Mb		0x3
+#define MD_SZ_1024_Mb		0x4
+#define MD_SZ_2048_Mb	 	0x5
+#define MD_SZ_UNUSED		0x7
+
+#define MD_DIMM_SIZE_BYTES(_size, _2bk) (				 \
+		( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\
+
+#define MD_DIMM_SIZE_MBYTES(_size, _2bk) (				 \
+	 	( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk)))  	 \
+
+/* The top 1/32 of each bank is directory memory, and not accessable
+ * via normal reads and writes */
+#define MD_DIMM_USER_SIZE(_size)	((_size) * 31 / 32)
+
+/* Minimum size of a populated bank is 64M (62M usable) */
+#define MIN_BANK_SIZE		MD_DIMM_USER_SIZE((64 * 0x100000))
+#define MIN_BANK_STRING		"62"
+
+
+/*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */
+#define MD_DIMM_100_CL2_0 	0x0
+#define MD_DIMM_133_CL2_0 	0x1
+#define MD_DIMM_133_CL2_5 	0x2
+#define MD_DIMM_160_CL2_0 	0x3
+#define MD_DIMM_160_CL2_5 	0x4
+#define MD_DIMM_160_CL3_0 	0x5
+#define MD_DIMM_200_CL2_0 	0x6
+#define MD_DIMM_200_CL2_5 	0x7
+#define MD_DIMM_200_CL3_0 	0x8
+
+/* DIMM_CFG fields */
+#define MD_DIMM_SHFT(_dimm)	((_dimm) << 3)
+#define MD_DIMM_SIZE_MASK(_dimm)					\
+		(SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << 			\
+		(MD_DIMM_SHFT(_dimm)))
+
+#define MD_DIMM_2BK_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_REV_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_REV_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_CS_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_CS_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_SIZE(_dimm, _cfg)					\
+		(((_cfg) & MD_DIMM_SIZE_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT))
+
+#define MD_DIMM_TWO_SIDED(_dimm,_cfg)					\
+		( ((_cfg) & MD_DIMM_2BK_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT))
+
+#define MD_DIMM_REVERSED(_dimm,_cfg) 					\
+		(((_cfg) & MD_DIMM_REV_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT))
+
+#define MD_DIMM_CS(_dimm,_cfg)						\
+		(((_cfg) & MD_DIMM_CS_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT))
+
+
+
+/* Macros to set MMRs that must be set identically to others. */
+#define MD_SET_DIMM_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value);			\
+                REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value);		\
+                REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);}
+
+#define MD_SET_DQCT_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value);			\
+		REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); }
+
+#define MD_SET_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_CFG,_value);			\
+		REMOTE_HUB_S(_n, SH_Y_CFG,_value);} 
+
+#define MD_SET_REFRESH_CONTROL(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value);		\
+		REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);}
+
+#define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value);	\
+                REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);}
+
+#define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);}
+
+/* 
+ * There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the
+ * LB.  The data in the left and right DQ MMRs and the LB must match.
+ */
+#define MD_SET_PRESENT_VEC(_n, _vec, _value) {				   \
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
+			 _value);					   \
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
+			 _value);					   \
+		REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);}
+/*
+ * There are 16 Privilege Vector MMRs, 8 in each primary DQ.  The data
+ * in the corresponding left and right DQ MMRs must match.  Each MMR
+ * pair is used for a single partition.
+ */
+#define MD_SET_PRI_VEC(_n, _vec, _value) {				  \
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
+			 _value);					  \
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
+			 _value);}
+/*
+ * There are 16 Local/Remote MMRs, 8 in each primary DQ.  The data in
+ * the corresponding left and right DQ MMRs must match.  Each MMR pair
+ * is used for a single partition.
+ */
+#define MD_SET_LOC_VEC(_n, _vec, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
+			 _value);					\
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
+			 _value);}
+
+/* Memory BIST CMDS */
+#define MD_DIMM_INIT_MODE_SET	0x0
+#define MD_DIMM_INIT_REFRESH	0x1
+#define MD_DIMM_INIT_PRECHARGE	0x2
+#define MD_DIMM_INIT_BURST_TERM	0x6
+#define MD_DIMM_INIT_NOP	0x7
+#define MD_DIMM_BIST_READ	0x10
+#define MD_FILL_DIR		0x20
+#define MD_FILL_DATA		0x30
+#define MD_FILL_DIR_ACCESS	0X40
+#define MD_READ_DIR_PAIR	0x50
+#define MD_READ_DIR_TAG		0x60
+
+/* SH_MMRBIST_CTL macros */
+#define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) &		\
+                SH_MMRBIST_CTL_FAIL_MASK)
+
+#define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & 	\
+                SH_MMRBIST_CTL_IN_PROGRESS_MASK)
+
+#define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & 	\
+                SH_MMRBIST_CTL_MEM_IDLE_MASK)
+
+/* SH_MMRBIST_ERR macros */
+#define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) &	\
+		SH_MMRBIST_ERR_DETECTED_MASK)
+
+#endif	/* _SHUB_MD_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/shub_mmr.h lia64-2.4/include/asm-ia64/sn/sn2/shub_mmr.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/shub_mmr.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/shub_mmr.h	Mon Nov 19 23:22:59 2001
@@ -0,0 +1,31597 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H
+#define _ASM_IA64_SN_SN2_SHUB_MMR_H
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_BINIT_CONTROL"                    */
+/*                          FSB BINIT# Control                          */
+/* ==================================================================== */
+
+#define SH_FSB_BINIT_CONTROL                     0x0000000120010000
+#define SH_FSB_BINIT_CONTROL_MASK                0x0000000000000001
+#define SH_FSB_BINIT_CONTROL_INIT                0x0000000000000000
+
+/*   SH_FSB_BINIT_CONTROL_BINIT                                         */
+/*   Description:  Assert the FSB's BINIT# Signal                       */
+#define SH_FSB_BINIT_CONTROL_BINIT_SHFT          0
+#define SH_FSB_BINIT_CONTROL_BINIT_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_RESET_CONTROL"                    */
+/*                          FSB Reset Control                           */
+/* ==================================================================== */
+
+#define SH_FSB_RESET_CONTROL                     0x0000000120010080
+#define SH_FSB_RESET_CONTROL_MASK                0x0000000000000001
+#define SH_FSB_RESET_CONTROL_INIT                0x0000000000000000
+
+/*   SH_FSB_RESET_CONTROL_RESET                                         */
+/*   Description:  Assert the FSB's RESET# Signal                       */
+#define SH_FSB_RESET_CONTROL_RESET_SHFT          0
+#define SH_FSB_RESET_CONTROL_RESET_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
+/*                    FSB System Agent Configuration                    */
+/* ==================================================================== */
+
+#define SH_FSB_SYSTEM_AGENT_CONFIG               0x0000000120010100
+#define SH_FSB_SYSTEM_AGENT_CONFIG_MASK          0x00003fff0187fff9
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INIT          0x0000000000000000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN                            */
+/*   Description:  RCNT/SCNT Assertion Enabled                          */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0
+#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN                          */
+/*   Description:  BERR Assertion Enabled for Bus Errors                */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN                        */
+/*   Description:  BERR Sampling Enabled                                */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN                         */
+/*   Description:  BINIT Assertion Enabled                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN                       */
+/*   Description:  stutter FSB request assertion                        */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN                           */
+/*   Description:  use short duration hang timeout                      */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA                           */
+/*   Description:  Interrupt Acknowledge Response Data                  */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP                            */
+/*   Description:  IO Transaction Response                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16
+#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP                          */
+/*   Description:  External Task Priority Register (xTPR) Transaction   */
+/*  Response                                                            */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17
+#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP                          */
+/*   Description:  Interrupt Acknowledge Transaction Response           */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_TDOT                                    */
+/*   Description:  Throttle Data-bus Ownership Transitions              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT     23
+#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK     0x0000000000800000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN                        */
+/*   Description:  serialize processor transactions                     */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES                     */
+/*   Description:  FSB error binit enables                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000
+
+/* ==================================================================== */
+/*                     Register "SH_FSB_VGA_REMAP"                      */
+/*                     FSB VGA Address Space Remap                      */
+/* ==================================================================== */
+
+#define SH_FSB_VGA_REMAP                         0x0000000120010180
+#define SH_FSB_VGA_REMAP_MASK                    0x4001fffffffe0000
+#define SH_FSB_VGA_REMAP_INIT                    0x0000000000000000
+
+/*   SH_FSB_VGA_REMAP_OFFSET                                            */
+/*   Description:  VGA Remap Node Offset                                */
+#define SH_FSB_VGA_REMAP_OFFSET_SHFT             17
+#define SH_FSB_VGA_REMAP_OFFSET_MASK             0x0000000ffffe0000
+
+/*   SH_FSB_VGA_REMAP_ASID                                              */
+/*   Description:  VGA Remap Address Space ID                           */
+#define SH_FSB_VGA_REMAP_ASID_SHFT               36
+#define SH_FSB_VGA_REMAP_ASID_MASK               0x0000003000000000
+
+/*   SH_FSB_VGA_REMAP_NID                                               */
+/*   Description:  VGA Remap Node ID                                    */
+#define SH_FSB_VGA_REMAP_NID_SHFT                38
+#define SH_FSB_VGA_REMAP_NID_MASK                0x0001ffc000000000
+
+/*   SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED                             */
+/*   Description:  VGA Remapping Enabled                                */
+#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62
+#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_FSB_RESET_STATUS"                    */
+/*                           FSB Reset Status                           */
+/* ==================================================================== */
+
+#define SH_FSB_RESET_STATUS                      0x0000000120020000
+#define SH_FSB_RESET_STATUS_MASK                 0x0000000000000001
+#define SH_FSB_RESET_STATUS_INIT                 0x0000000000000000
+
+/*   SH_FSB_RESET_STATUS_RESET_IN_PROGRESS                              */
+/*   Description:  Reset in Progress                                    */
+#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0
+#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
+/*                      FSB Symmetric Agent Status                      */
+/* ==================================================================== */
+
+#define SH_FSB_SYMMETRIC_AGENT_STATUS            0x0000000120020080
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK       0x0000000000000007
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT       0x0000000000000000
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE                         */
+/*   Description:  CPU 0 Active.                                        */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE                         */
+/*   Description:  CPU 1 Active.                                        */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY                           */
+/*   Description:  The Processors are Ready                             */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
+/*                Graphics-write Credit Count for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_CREDIT_COUNT_0                    0x0000000120030000
+#define SH_GFX_CREDIT_COUNT_0_MASK               0x80000000000fffff
+#define SH_GFX_CREDIT_COUNT_0_INIT               0x000000000000003f
+
+/*   SH_GFX_CREDIT_COUNT_0_COUNT                                        */
+/*   Description:  Credit Count                                         */
+#define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT         0
+#define SH_GFX_CREDIT_COUNT_0_COUNT_MASK         0x00000000000fffff
+
+/*   SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE                              */
+/*   Description:  Reset GFX state                                      */
+#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63
+#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
+/*                Graphics-write Credit Count for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_CREDIT_COUNT_1                    0x0000000120030080
+#define SH_GFX_CREDIT_COUNT_1_MASK               0x80000000000fffff
+#define SH_GFX_CREDIT_COUNT_1_INIT               0x000000000000003f
+
+/*   SH_GFX_CREDIT_COUNT_1_COUNT                                        */
+/*   Description:  Credit Count                                         */
+#define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT         0
+#define SH_GFX_CREDIT_COUNT_1_COUNT_MASK         0x00000000000fffff
+
+/*   SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE                              */
+/*   Description:  Reset GFX state                                      */
+#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63
+#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_0"                    */
+/*         Graphics credit mode amd message ordering for CPU 0          */
+/* ==================================================================== */
+
+#define SH_GFX_MODE_CNTRL_0                      0x0000000120030100
+#define SH_GFX_MODE_CNTRL_0_MASK                 0x0000000000000007
+#define SH_GFX_MODE_CNTRL_0_INIT                 0x0000000000000003
+
+/*   SH_GFX_MODE_CNTRL_0_DWORD_CREDITS                                  */
+/*   Description:  GFX credits are tracked by D-words                   */
+#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT   0
+#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK   0x0000000000000001
+
+/*   SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS                             */
+/*   Description:  GFX credits are tracked by D-words and messages      */
+#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1
+#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002
+
+/*   SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING                               */
+/*   Description:  GFX message routing order                            */
+#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2
+#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_1"                    */
+/*         Graphics credit mode amd message ordering for CPU 1          */
+/* ==================================================================== */
+
+#define SH_GFX_MODE_CNTRL_1                      0x0000000120030180
+#define SH_GFX_MODE_CNTRL_1_MASK                 0x0000000000000007
+#define SH_GFX_MODE_CNTRL_1_INIT                 0x0000000000000003
+
+/*   SH_GFX_MODE_CNTRL_1_DWORD_CREDITS                                  */
+/*   Description:  GFX credits are tracked by D-words                   */
+#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT   0
+#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK   0x0000000000000001
+
+/*   SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS                             */
+/*   Description:  GFX credits are tracked by D-words and messages      */
+#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1
+#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002
+
+/*   SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING                               */
+/*   Description:  GFX message routing order                            */
+#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2
+#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
+/*              Graphics-write Skid Credit Count for CPU 0              */
+/* ==================================================================== */
+
+#define SH_GFX_SKID_CREDIT_COUNT_0               0x0000000120030200
+#define SH_GFX_SKID_CREDIT_COUNT_0_MASK          0x00000000000fffff
+#define SH_GFX_SKID_CREDIT_COUNT_0_INIT          0x0000000000000030
+
+/*   SH_GFX_SKID_CREDIT_COUNT_0_SKID                                    */
+/*   Description:  Skid Credit Count                                    */
+#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT     0
+#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK     0x00000000000fffff
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
+/*              Graphics-write Skid Credit Count for CPU 1              */
+/* ==================================================================== */
+
+#define SH_GFX_SKID_CREDIT_COUNT_1               0x0000000120030280
+#define SH_GFX_SKID_CREDIT_COUNT_1_MASK          0x00000000000fffff
+#define SH_GFX_SKID_CREDIT_COUNT_1_INIT          0x0000000000000030
+
+/*   SH_GFX_SKID_CREDIT_COUNT_1_SKID                                    */
+/*   Description:  Skid Credit Count                                    */
+#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT     0
+#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK     0x00000000000fffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_0"                    */
+/*                 Graphics-write Stall Limit for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_LIMIT_0                     0x0000000120030300
+#define SH_GFX_STALL_LIMIT_0_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_LIMIT_0_INIT                0x0000000000010000
+
+/*   SH_GFX_STALL_LIMIT_0_LIMIT                                         */
+/*   Description:  Graphics Stall Limit for CPU 0                       */
+#define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT          0
+#define SH_GFX_STALL_LIMIT_0_LIMIT_MASK          0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_1"                    */
+/*                 Graphics-write Stall Limit for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_LIMIT_1                     0x0000000120030380
+#define SH_GFX_STALL_LIMIT_1_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_LIMIT_1_INIT                0x0000000000010000
+
+/*   SH_GFX_STALL_LIMIT_1_LIMIT                                         */
+/*   Description:  Graphics Stall Limit for CPU 1                       */
+#define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT          0
+#define SH_GFX_STALL_LIMIT_1_LIMIT_MASK          0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_0"                    */
+/*                 Graphics-write Stall Timer for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_TIMER_0                     0x0000000120030400
+#define SH_GFX_STALL_TIMER_0_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_TIMER_0_INIT                0x0000000000000000
+
+/*   SH_GFX_STALL_TIMER_0_TIMER_VALUE                                   */
+/*   Description:  Timer Value                                          */
+#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT    0
+#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK    0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_1"                    */
+/*                 Graphics-write Stall Timer for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_TIMER_1                     0x0000000120030480
+#define SH_GFX_STALL_TIMER_1_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_TIMER_1_INIT                0x0000000000000000
+
+/*   SH_GFX_STALL_TIMER_1_TIMER_VALUE                                   */
+/*   Description:  Timer Value                                          */
+#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT    0
+#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK    0x0000000003ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_0"                      */
+/*                   Graphics-write Window for CPU 0                    */
+/* ==================================================================== */
+
+#define SH_GFX_WINDOW_0                          0x0000000120030500
+#define SH_GFX_WINDOW_0_MASK                     0x8000000fff000000
+#define SH_GFX_WINDOW_0_INIT                     0x0000000000000000
+
+/*   SH_GFX_WINDOW_0_BASE_ADDR                                          */
+/*   Description:  Base Address for CPU 0's 16 MB Graphics Window       */
+#define SH_GFX_WINDOW_0_BASE_ADDR_SHFT           24
+#define SH_GFX_WINDOW_0_BASE_ADDR_MASK           0x0000000fff000000
+
+/*   SH_GFX_WINDOW_0_GFX_WINDOW_EN                                      */
+/*   Description:  Graphics Window Enabled                              */
+#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT       63
+#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_1"                      */
+/*                   Graphics-write Window for CPU 1                    */
+/* ==================================================================== */
+
+#define SH_GFX_WINDOW_1                          0x0000000120030580
+#define SH_GFX_WINDOW_1_MASK                     0x8000000fff000000
+#define SH_GFX_WINDOW_1_INIT                     0x0000000000000000
+
+/*   SH_GFX_WINDOW_1_BASE_ADDR                                          */
+/*   Description:  Base Address for CPU 1's 16 MB Graphics Window       */
+#define SH_GFX_WINDOW_1_BASE_ADDR_SHFT           24
+#define SH_GFX_WINDOW_1_BASE_ADDR_MASK           0x0000000fff000000
+
+/*   SH_GFX_WINDOW_1_GFX_WINDOW_EN                                      */
+/*   Description:  Graphics Window Enabled                              */
+#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT       63
+#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
+/*               Graphics-write Interrupt Limit for CPU 0               */
+/* ==================================================================== */
+
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0           0x0000000120030600
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK      0x00000000000000ff
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT      0x0000000000000040
+
+/*   SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT               */
+/*   Description:  GFX Interrupt Timer Limit                            */
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
+/*               Graphics-write Interrupt Limit for CPU 1               */
+/* ==================================================================== */
+
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1           0x0000000120030680
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK      0x00000000000000ff
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT      0x0000000000000040
+
+/*   SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT               */
+/*   Description:  GFX Interrupt Timer Limit                            */
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
+/*                   Graphics Write Status for CPU 0                    */
+/* ==================================================================== */
+
+#define SH_GFX_WRITE_STATUS_0                    0x0000000120040000
+#define SH_GFX_WRITE_STATUS_0_MASK               0x8000000000000001
+#define SH_GFX_WRITE_STATUS_0_INIT               0x0000000000000000
+
+/*   SH_GFX_WRITE_STATUS_0_BUSY                                         */
+/*   Description:  Busy                                                 */
+#define SH_GFX_WRITE_STATUS_0_BUSY_SHFT          0
+#define SH_GFX_WRITE_STATUS_0_BUSY_MASK          0x0000000000000001
+
+/*   SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL                          */
+/*   Description:  Re-enable GFX stall logic for this processor         */
+#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63
+#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
+/*                   Graphics Write Status for CPU 1                    */
+/* ==================================================================== */
+
+#define SH_GFX_WRITE_STATUS_1                    0x0000000120040080
+#define SH_GFX_WRITE_STATUS_1_MASK               0x8000000000000001
+#define SH_GFX_WRITE_STATUS_1_INIT               0x0000000000000000
+
+/*   SH_GFX_WRITE_STATUS_1_BUSY                                         */
+/*   Description:  Busy                                                 */
+#define SH_GFX_WRITE_STATUS_1_BUSY_SHFT          0
+#define SH_GFX_WRITE_STATUS_1_BUSY_MASK          0x0000000000000001
+
+/*   SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL                          */
+/*   Description:  Re-enable GFX stall logic for this processor         */
+#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63
+#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT0"                         */
+/*                    SHub II Interrupt 0 Registers                     */
+/* ==================================================================== */
+
+#define SH_II_INT0                               0x0000000110000000
+#define SH_II_INT0_MASK                          0x00000000000001ff
+#define SH_II_INT0_INIT                          0x0000000000000000
+
+/*   SH_II_INT0_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_II_INT0_IDX_SHFT                      0
+#define SH_II_INT0_IDX_MASK                      0x00000000000000ff
+
+/*   SH_II_INT0_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_II_INT0_SEND_SHFT                     8
+#define SH_II_INT0_SEND_MASK                     0x0000000000000100
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_CONFIG"                     */
+/*                 SHub II Interrupt 0 Config Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT0_CONFIG                        0x0000000110000080
+#define SH_II_INT0_CONFIG_MASK                   0x0003ffffffefffff
+#define SH_II_INT0_CONFIG_INIT                   0x0000000000000000
+
+/*   SH_II_INT0_CONFIG_TYPE                                             */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_II_INT0_CONFIG_TYPE_SHFT              0
+#define SH_II_INT0_CONFIG_TYPE_MASK              0x0000000000000007
+
+/*   SH_II_INT0_CONFIG_AGT                                              */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_II_INT0_CONFIG_AGT_SHFT               3
+#define SH_II_INT0_CONFIG_AGT_MASK               0x0000000000000008
+
+/*   SH_II_INT0_CONFIG_PID                                              */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_II_INT0_CONFIG_PID_SHFT               4
+#define SH_II_INT0_CONFIG_PID_MASK               0x00000000000ffff0
+
+/*   SH_II_INT0_CONFIG_BASE                                             */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_II_INT0_CONFIG_BASE_SHFT              21
+#define SH_II_INT0_CONFIG_BASE_MASK              0x0003ffffffe00000
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_ENABLE"                     */
+/*                 SHub II Interrupt 0 Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT0_ENABLE                        0x0000000110000200
+#define SH_II_INT0_ENABLE_MASK                   0x0000000000000001
+#define SH_II_INT0_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_II_INT0_ENABLE_II_ENABLE                                        */
+/*   Description:  Enable II Interrupt                                  */
+#define SH_II_INT0_ENABLE_II_ENABLE_SHFT         0
+#define SH_II_INT0_ENABLE_II_ENABLE_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT1"                         */
+/*                    SHub II Interrupt 1 Registers                     */
+/* ==================================================================== */
+
+#define SH_II_INT1                               0x0000000110000100
+#define SH_II_INT1_MASK                          0x00000000000001ff
+#define SH_II_INT1_INIT                          0x0000000000000000
+
+/*   SH_II_INT1_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_II_INT1_IDX_SHFT                      0
+#define SH_II_INT1_IDX_MASK                      0x00000000000000ff
+
+/*   SH_II_INT1_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_II_INT1_SEND_SHFT                     8
+#define SH_II_INT1_SEND_MASK                     0x0000000000000100
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_CONFIG"                     */
+/*                 SHub II Interrupt 1 Config Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT1_CONFIG                        0x0000000110000180
+#define SH_II_INT1_CONFIG_MASK                   0x0003ffffffefffff
+#define SH_II_INT1_CONFIG_INIT                   0x0000000000000000
+
+/*   SH_II_INT1_CONFIG_TYPE                                             */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_II_INT1_CONFIG_TYPE_SHFT              0
+#define SH_II_INT1_CONFIG_TYPE_MASK              0x0000000000000007
+
+/*   SH_II_INT1_CONFIG_AGT                                              */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_II_INT1_CONFIG_AGT_SHFT               3
+#define SH_II_INT1_CONFIG_AGT_MASK               0x0000000000000008
+
+/*   SH_II_INT1_CONFIG_PID                                              */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_II_INT1_CONFIG_PID_SHFT               4
+#define SH_II_INT1_CONFIG_PID_MASK               0x00000000000ffff0
+
+/*   SH_II_INT1_CONFIG_BASE                                             */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_II_INT1_CONFIG_BASE_SHFT              21
+#define SH_II_INT1_CONFIG_BASE_MASK              0x0003ffffffe00000
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_ENABLE"                     */
+/*                 SHub II Interrupt 1 Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT1_ENABLE                        0x0000000110000280
+#define SH_II_INT1_ENABLE_MASK                   0x0000000000000001
+#define SH_II_INT1_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_II_INT1_ENABLE_II_ENABLE                                        */
+/*   Description:  Enable II 1 Interrupt                                */
+#define SH_II_INT1_ENABLE_II_ENABLE_SHFT         0
+#define SH_II_INT1_ENABLE_II_ENABLE_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_INT_NODE_ID_CONFIG"                   */
+/*                 SHub Interrupt Node ID Configuration                 */
+/* ==================================================================== */
+
+#define SH_INT_NODE_ID_CONFIG                    0x0000000110000300
+#define SH_INT_NODE_ID_CONFIG_MASK               0x0000000000000fff
+#define SH_INT_NODE_ID_CONFIG_INIT               0x0000000000000000
+
+/*   SH_INT_NODE_ID_CONFIG_NODE_ID                                      */
+/*   Description:  Node ID for interrupt messages                       */
+#define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT       0
+#define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK       0x00000000000007ff
+
+/*   SH_INT_NODE_ID_CONFIG_ID_SEL                                       */
+/*   Description:  Select node id for interrupt messages                */
+#define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT        11
+#define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK        0x0000000000000800
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+
+#define SH_IPI_INT                               0x0000000110000380
+#define SH_IPI_INT_MASK                          0x8ff3ffffffefffff
+#define SH_IPI_INT_INIT                          0x0000000000000000
+
+/*   SH_IPI_INT_TYPE                                                    */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_IPI_INT_TYPE_SHFT                     0
+#define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
+
+/*   SH_IPI_INT_AGT                                                     */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_IPI_INT_AGT_SHFT                      3
+#define SH_IPI_INT_AGT_MASK                      0x0000000000000008
+
+/*   SH_IPI_INT_PID                                                     */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_IPI_INT_PID_SHFT                      4
+#define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
+
+/*   SH_IPI_INT_BASE                                                    */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_IPI_INT_BASE_SHFT                     21
+#define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
+
+/*   SH_IPI_INT_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_IPI_INT_IDX_SHFT                      52
+#define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
+
+/*   SH_IPI_INT_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_IPI_INT_SEND_SHFT                     63
+#define SH_IPI_INT_SEND_MASK                     0x8000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_IPI_INT_ENABLE"                     */
+/*           SHub Inter-Processor Interrupt Enable Registers            */
+/* ==================================================================== */
+
+#define SH_IPI_INT_ENABLE                        0x0000000110000400
+#define SH_IPI_INT_ENABLE_MASK                   0x0000000000000001
+#define SH_IPI_INT_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_IPI_INT_ENABLE_PIO_ENABLE                                       */
+/*   Description:  Enable PIO Interrupt                                 */
+#define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT        0
+#define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK        0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_CONFIG"                    */
+/*                   SHub Local Interrupt 0 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT0_CONFIG                     0x0000000110000480
+#define SH_LOCAL_INT0_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT0_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT0_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT0_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT0_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT0_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT0_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT0_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT0_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT0_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT0_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT0_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT0_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT0_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT0_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT0_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT0_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_ENABLE"                    */
+/*                    SHub Local Interrupt 0 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT0_ENABLE                     0x0000000110000500
+#define SH_LOCAL_INT0_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT0_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT0_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT0_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT0_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT0_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT0_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT0_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT0_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT0_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT0_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT0_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT0_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT0_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT0_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT0_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT0_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_CONFIG"                    */
+/*                   SHub Local Interrupt 1 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT1_CONFIG                     0x0000000110000580
+#define SH_LOCAL_INT1_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT1_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT1_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT1_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT1_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT1_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT1_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT1_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT1_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT1_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT1_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT1_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT1_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT1_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT1_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT1_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT1_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_ENABLE"                    */
+/*                    SHub Local Interrupt 1 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT1_ENABLE                     0x0000000110000600
+#define SH_LOCAL_INT1_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT1_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT1_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT1_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT1_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT1_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT1_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT1_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT1_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT1_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT1_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT1_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT1_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT1_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT1_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT1_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT1_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_CONFIG"                    */
+/*                   SHub Local Interrupt 2 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT2_CONFIG                     0x0000000110000680
+#define SH_LOCAL_INT2_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT2_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT2_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT2_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT2_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT2_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT2_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT2_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT2_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT2_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT2_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT2_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT2_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT2_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT2_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT2_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT2_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_ENABLE"                    */
+/*                    SHub Local Interrupt 2 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT2_ENABLE                     0x0000000110000700
+#define SH_LOCAL_INT2_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT2_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT2_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT2_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT2_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT2_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT2_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT2_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT2_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT2_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT2_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT2_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT2_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT2_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT2_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT2_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT2_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_CONFIG"                    */
+/*                   SHub Local Interrupt 3 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT3_CONFIG                     0x0000000110000780
+#define SH_LOCAL_INT3_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT3_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT3_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT3_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT3_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT3_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT3_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT3_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT3_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT3_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT3_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT3_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT3_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT3_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT3_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT3_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT3_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_ENABLE"                    */
+/*                    SHub Local Interrupt 3 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT3_ENABLE                     0x0000000110000800
+#define SH_LOCAL_INT3_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT3_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT3_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT3_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT3_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT3_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT3_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT3_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT3_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT3_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT3_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT3_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT3_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT3_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT3_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT3_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT3_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_CONFIG"                    */
+/*                   SHub Local Interrupt 4 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT4_CONFIG                     0x0000000110000880
+#define SH_LOCAL_INT4_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT4_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT4_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT4_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT4_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT4_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT4_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT4_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT4_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT4_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT4_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT4_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT4_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT4_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT4_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT4_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT4_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_ENABLE"                    */
+/*                    SHub Local Interrupt 4 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT4_ENABLE                     0x0000000110000900
+#define SH_LOCAL_INT4_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT4_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT4_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT4_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT4_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT4_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT4_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT4_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT4_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT4_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT4_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT4_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT4_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT4_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT4_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT4_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT4_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_CONFIG"                    */
+/*                   SHub Local Interrupt 5 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT5_CONFIG                     0x0000000110000980
+#define SH_LOCAL_INT5_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT5_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT5_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT5_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT5_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT5_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT5_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT5_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT5_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT5_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT5_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT5_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT5_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT5_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT5_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT5_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT5_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_ENABLE"                    */
+/*                    SHub Local Interrupt 5 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT5_ENABLE                     0x0000000110000a00
+#define SH_LOCAL_INT5_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT5_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT5_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT5_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT5_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT5_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT5_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT5_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT5_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT5_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT5_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT5_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT5_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT5_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT5_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT5_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT5_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
+/*              SHub Processor 0 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_INT_CONFIG                  0x0000000110000a80
+#define SH_PROC0_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC0_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC0_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC0_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC0_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC0_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC0_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC0_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC0_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC0_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC0_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
+/*              SHub Processor 1 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_INT_CONFIG                  0x0000000110000b00
+#define SH_PROC1_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC1_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC1_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC1_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC1_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC1_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC1_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC1_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC1_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC1_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC1_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
+/*              SHub Processor 2 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_INT_CONFIG                  0x0000000110000b80
+#define SH_PROC2_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC2_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC2_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC2_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC2_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC2_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC2_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC2_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC2_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC2_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC2_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
+/*              SHub Processor 3 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_INT_CONFIG                  0x0000000110000c00
+#define SH_PROC3_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC3_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC3_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC3_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC3_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC3_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC3_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC3_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC3_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC3_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC3_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
+/*            SHub Processor 0 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_INT_CONFIG                  0x0000000110000c80
+#define SH_PROC0_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC0_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC0_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC0_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC0_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC0_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC0_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC0_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC0_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC0_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC0_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
+/*            SHub Processor 1 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_INT_CONFIG                  0x0000000110000d00
+#define SH_PROC1_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC1_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC1_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC1_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC1_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC1_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC1_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC1_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC1_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC1_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC1_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
+/*            SHub Processor 2 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_INT_CONFIG                  0x0000000110000d80
+#define SH_PROC2_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC2_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC2_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC2_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC2_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC2_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC2_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC2_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC2_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC2_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC2_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
+/*            SHub Processor 3 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_INT_CONFIG                  0x0000000110000e00
+#define SH_PROC3_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC3_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC3_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC3_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC3_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC3_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC3_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC3_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC3_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC3_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC3_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
+/*          SHub Processor 0 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_INT_ENABLE                  0x0000000110000e80
+#define SH_PROC0_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC0_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE                           */
+/*   Description:  Enable Processor 0 Error Interrupt                   */
+#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0
+#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
+/*          SHub Processor 1 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_INT_ENABLE                  0x0000000110000f00
+#define SH_PROC1_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC1_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE                           */
+/*   Description:  Enable Processor 1 Error Interrupt                   */
+#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0
+#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
+/*          SHub Processor 2 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_INT_ENABLE                  0x0000000110000f80
+#define SH_PROC2_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC2_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE                           */
+/*   Description:  Enable Processor 2 Error Interrupt                   */
+#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0
+#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
+/*          SHub Processor 3 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_INT_ENABLE                  0x0000000110001000
+#define SH_PROC3_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC3_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE                           */
+/*   Description:  Enable Processor 3 Error Interrupt                   */
+#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0
+#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
+/*         SHub Processor 0 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_INT_ENABLE                  0x0000000110001080
+#define SH_PROC0_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC0_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE                           */
+/*   Description:  Enable Processor 0 Advisory Interrupt                */
+#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0
+#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
+/*         SHub Processor 1 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_INT_ENABLE                  0x0000000110001100
+#define SH_PROC1_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC1_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE                           */
+/*   Description:  Enable Processor 1 Advisory Interrupt                */
+#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0
+#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
+/*         SHub Processor 2 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_INT_ENABLE                  0x0000000110001180
+#define SH_PROC2_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC2_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE                           */
+/*   Description:  Enable Processor 2 Advisory Interrupt                */
+#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0
+#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
+/*         SHub Processor 3 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_INT_ENABLE                  0x0000000110001200
+#define SH_PROC3_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC3_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE                           */
+/*   Description:  Enable Processor 3 Advisory Interrupt                */
+#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0
+#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_CONFIG"                   */
+/*            SHub Profile Interrupt Configuration Registers            */
+/* ==================================================================== */
+
+#define SH_PROFILE_INT_CONFIG                    0x0000000110001280
+#define SH_PROFILE_INT_CONFIG_MASK               0x0ff3ffffffefffff
+#define SH_PROFILE_INT_CONFIG_INIT               0x0000000000000000
+
+/*   SH_PROFILE_INT_CONFIG_TYPE                                         */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROFILE_INT_CONFIG_TYPE_SHFT          0
+#define SH_PROFILE_INT_CONFIG_TYPE_MASK          0x0000000000000007
+
+/*   SH_PROFILE_INT_CONFIG_AGT                                          */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROFILE_INT_CONFIG_AGT_SHFT           3
+#define SH_PROFILE_INT_CONFIG_AGT_MASK           0x0000000000000008
+
+/*   SH_PROFILE_INT_CONFIG_PID                                          */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROFILE_INT_CONFIG_PID_SHFT           4
+#define SH_PROFILE_INT_CONFIG_PID_MASK           0x00000000000ffff0
+
+/*   SH_PROFILE_INT_CONFIG_BASE                                         */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROFILE_INT_CONFIG_BASE_SHFT          21
+#define SH_PROFILE_INT_CONFIG_BASE_MASK          0x0003ffffffe00000
+
+/*   SH_PROFILE_INT_CONFIG_IDX                                          */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROFILE_INT_CONFIG_IDX_SHFT           52
+#define SH_PROFILE_INT_CONFIG_IDX_MASK           0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_ENABLE"                   */
+/*               SHub Profile Interrupt Enable Registers                */
+/* ==================================================================== */
+
+#define SH_PROFILE_INT_ENABLE                    0x0000000110001300
+#define SH_PROFILE_INT_ENABLE_MASK               0x0000000000000001
+#define SH_PROFILE_INT_ENABLE_INIT               0x0000000000000000
+
+/*   SH_PROFILE_INT_ENABLE_PROFILE_ENABLE                               */
+/*   Description:  Enable Profile Interrupt                             */
+#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0
+#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_CONFIG"                     */
+/*                SHub RTC 0 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC0_INT_CONFIG                       0x0000000110001380
+#define SH_RTC0_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC0_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC0_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC0_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC0_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC0_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC0_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC0_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC0_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC0_INT_CONFIG_PID_SHFT              4
+#define SH_RTC0_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC0_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC0_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC0_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC0_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC0_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC0_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_ENABLE"                     */
+/*                SHub RTC 0 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC0_INT_ENABLE                       0x0000000110001400
+#define SH_RTC0_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC0_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC0_INT_ENABLE_RTC0_ENABLE                                     */
+/*   Description:  Enable RTC 0 Interrupt                               */
+#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT      0
+#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_CONFIG                       0x0000000110001480
+#define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC1_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC1_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC1_INT_CONFIG_PID_SHFT              4
+#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC1_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC1_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_ENABLE                       0x0000000110001500
+#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
+/*   Description:  Enable RTC 1 Interrupt                               */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_CONFIG                       0x0000000110001580
+#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC2_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC2_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC2_INT_CONFIG_PID_SHFT              4
+#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC2_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC2_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_ENABLE                       0x0000000110001600
+#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
+/*   Description:  Enable RTC 2 Interrupt                               */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_CONFIG                       0x0000000110001680
+#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC3_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC3_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC3_INT_CONFIG_PID_SHFT              4
+#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC3_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC3_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_ENABLE                       0x0000000110001700
+#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
+/*   Description:  Enable RTC 3 Interrupt                               */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+
+#define SH_EVENT_OCCURRED                        0x0000000110010000
+#define SH_EVENT_OCCURRED_MASK                   0x000000007fffffff
+#define SH_EVENT_OCCURRED_INIT                   0x0000000000000000
+
+/*   SH_EVENT_OCCURRED_PI_HW_INT                                        */
+/*   Description:  Pending PI Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_PI_HW_INT_SHFT         0
+#define SH_EVENT_OCCURRED_PI_HW_INT_MASK         0x0000000000000001
+
+/*   SH_EVENT_OCCURRED_MD_HW_INT                                        */
+/*   Description:  Pending MD Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_MD_HW_INT_SHFT         1
+#define SH_EVENT_OCCURRED_MD_HW_INT_MASK         0x0000000000000002
+
+/*   SH_EVENT_OCCURRED_XN_HW_INT                                        */
+/*   Description:  Pending XN Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_XN_HW_INT_SHFT         2
+#define SH_EVENT_OCCURRED_XN_HW_INT_MASK         0x0000000000000004
+
+/*   SH_EVENT_OCCURRED_LB_HW_INT                                        */
+/*   Description:  Pending LB Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_LB_HW_INT_SHFT         3
+#define SH_EVENT_OCCURRED_LB_HW_INT_MASK         0x0000000000000008
+
+/*   SH_EVENT_OCCURRED_II_HW_INT                                        */
+/*   Description:  Pending II wrapper Hardware interrupt                */
+#define SH_EVENT_OCCURRED_II_HW_INT_SHFT         4
+#define SH_EVENT_OCCURRED_II_HW_INT_MASK         0x0000000000000010
+
+/*   SH_EVENT_OCCURRED_PI_CE_INT                                        */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_PI_CE_INT_SHFT         5
+#define SH_EVENT_OCCURRED_PI_CE_INT_MASK         0x0000000000000020
+
+/*   SH_EVENT_OCCURRED_MD_CE_INT                                        */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_MD_CE_INT_SHFT         6
+#define SH_EVENT_OCCURRED_MD_CE_INT_MASK         0x0000000000000040
+
+/*   SH_EVENT_OCCURRED_XN_CE_INT                                        */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_XN_CE_INT_SHFT         7
+#define SH_EVENT_OCCURRED_XN_CE_INT_MASK         0x0000000000000080
+
+/*   SH_EVENT_OCCURRED_PI_UCE_INT                                       */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT        8
+#define SH_EVENT_OCCURRED_PI_UCE_INT_MASK        0x0000000000000100
+
+/*   SH_EVENT_OCCURRED_MD_UCE_INT                                       */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT        9
+#define SH_EVENT_OCCURRED_MD_UCE_INT_MASK        0x0000000000000200
+
+/*   SH_EVENT_OCCURRED_XN_UCE_INT                                       */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT        10
+#define SH_EVENT_OCCURRED_XN_UCE_INT_MASK        0x0000000000000400
+
+/*   SH_EVENT_OCCURRED_PROC0_ADV_INT                                    */
+/*   Description:  Pending Processor 0 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT     11
+#define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK     0x0000000000000800
+
+/*   SH_EVENT_OCCURRED_PROC1_ADV_INT                                    */
+/*   Description:  Pending Processor 1 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT     12
+#define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK     0x0000000000001000
+
+/*   SH_EVENT_OCCURRED_PROC2_ADV_INT                                    */
+/*   Description:  Pending Processor 2 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT     13
+#define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK     0x0000000000002000
+
+/*   SH_EVENT_OCCURRED_PROC3_ADV_INT                                    */
+/*   Description:  Pending Processor 3 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT     14
+#define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK     0x0000000000004000
+
+/*   SH_EVENT_OCCURRED_PROC0_ERR_INT                                    */
+/*   Description:  Pending Processor 0 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT     15
+#define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK     0x0000000000008000
+
+/*   SH_EVENT_OCCURRED_PROC1_ERR_INT                                    */
+/*   Description:  Pending Processor 1 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT     16
+#define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK     0x0000000000010000
+
+/*   SH_EVENT_OCCURRED_PROC2_ERR_INT                                    */
+/*   Description:  Pending Processor 2 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT     17
+#define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK     0x0000000000020000
+
+/*   SH_EVENT_OCCURRED_PROC3_ERR_INT                                    */
+/*   Description:  Pending Processor 3 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT     18
+#define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK     0x0000000000040000
+
+/*   SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT                              */
+/*   Description:  Pending System Shutdown Interrupt                    */
+#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19
+#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
+
+/*   SH_EVENT_OCCURRED_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OCCURRED_UART_INT_SHFT          20
+#define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
+
+/*   SH_EVENT_OCCURRED_L1_NMI_INT                                       */
+/*   Description:  Pending L1 Controller NMI Interrupt                  */
+#define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT        21
+#define SH_EVENT_OCCURRED_L1_NMI_INT_MASK        0x0000000000200000
+
+/*   SH_EVENT_OCCURRED_STOP_CLOCK                                       */
+/*   Description:  Pending Stop Clock Interrupt                         */
+#define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT        22
+#define SH_EVENT_OCCURRED_STOP_CLOCK_MASK        0x0000000000400000
+
+/*   SH_EVENT_OCCURRED_RTC0_INT                                         */
+/*   Description:  Pending RTC 0 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC0_INT_SHFT          23
+#define SH_EVENT_OCCURRED_RTC0_INT_MASK          0x0000000000800000
+
+/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
+
+/*   SH_EVENT_OCCURRED_PROFILE_INT                                      */
+/*   Description:  Pending Profile Interrupt                            */
+#define SH_EVENT_OCCURRED_PROFILE_INT_SHFT       27
+#define SH_EVENT_OCCURRED_PROFILE_INT_MASK       0x0000000008000000
+
+/*   SH_EVENT_OCCURRED_IPI_INT                                          */
+/*   Description:  Pending IPI Interrupt                                */
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
+
+/*   SH_EVENT_OCCURRED_II_INT0                                          */
+/*   Description:  Pending II 0 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT0_SHFT           29
+#define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
+
+/*   SH_EVENT_OCCURRED_II_INT1                                          */
+/*   Description:  Pending II 1 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT1_SHFT           30
+#define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
+
+/* ==================================================================== */
+/*                  Register "SH_EVENT_OCCURRED_ALIAS"                  */
+/*                 SHub Interrupt Event Occurred Alias                  */
+/* ==================================================================== */
+
+#define SH_EVENT_OCCURRED_ALIAS                  0x0000000110010008
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OVERFLOW"                     */
+/*                SHub Interrupt Event Occurred Overflow                */
+/* ==================================================================== */
+
+#define SH_EVENT_OVERFLOW                        0x0000000110010080
+#define SH_EVENT_OVERFLOW_MASK                   0x000000000fffffff
+#define SH_EVENT_OVERFLOW_INIT                   0x0000000000000000
+
+/*   SH_EVENT_OVERFLOW_PI_HW_INT                                        */
+/*   Description:  Pending PI Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT         0
+#define SH_EVENT_OVERFLOW_PI_HW_INT_MASK         0x0000000000000001
+
+/*   SH_EVENT_OVERFLOW_MD_HW_INT                                        */
+/*   Description:  Pending MD Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT         1
+#define SH_EVENT_OVERFLOW_MD_HW_INT_MASK         0x0000000000000002
+
+/*   SH_EVENT_OVERFLOW_XN_HW_INT                                        */
+/*   Description:  Pending XN Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT         2
+#define SH_EVENT_OVERFLOW_XN_HW_INT_MASK         0x0000000000000004
+
+/*   SH_EVENT_OVERFLOW_LB_HW_INT                                        */
+/*   Description:  Pending LB Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT         3
+#define SH_EVENT_OVERFLOW_LB_HW_INT_MASK         0x0000000000000008
+
+/*   SH_EVENT_OVERFLOW_II_HW_INT                                        */
+/*   Description:  Pending II wrapper Hardware interrupt                */
+#define SH_EVENT_OVERFLOW_II_HW_INT_SHFT         4
+#define SH_EVENT_OVERFLOW_II_HW_INT_MASK         0x0000000000000010
+
+/*   SH_EVENT_OVERFLOW_PI_CE_INT                                        */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT         5
+#define SH_EVENT_OVERFLOW_PI_CE_INT_MASK         0x0000000000000020
+
+/*   SH_EVENT_OVERFLOW_MD_CE_INT                                        */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT         6
+#define SH_EVENT_OVERFLOW_MD_CE_INT_MASK         0x0000000000000040
+
+/*   SH_EVENT_OVERFLOW_XN_CE_INT                                        */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT         7
+#define SH_EVENT_OVERFLOW_XN_CE_INT_MASK         0x0000000000000080
+
+/*   SH_EVENT_OVERFLOW_PI_UCE_INT                                       */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT        8
+#define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK        0x0000000000000100
+
+/*   SH_EVENT_OVERFLOW_MD_UCE_INT                                       */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT        9
+#define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK        0x0000000000000200
+
+/*   SH_EVENT_OVERFLOW_XN_UCE_INT                                       */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT        10
+#define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK        0x0000000000000400
+
+/*   SH_EVENT_OVERFLOW_PROC0_ADV_INT                                    */
+/*   Description:  Pending Processor 0 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT     11
+#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK     0x0000000000000800
+
+/*   SH_EVENT_OVERFLOW_PROC1_ADV_INT                                    */
+/*   Description:  Pending Processor 1 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT     12
+#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK     0x0000000000001000
+
+/*   SH_EVENT_OVERFLOW_PROC2_ADV_INT                                    */
+/*   Description:  Pending Processor 2 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT     13
+#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK     0x0000000000002000
+
+/*   SH_EVENT_OVERFLOW_PROC3_ADV_INT                                    */
+/*   Description:  Pending Processor 3 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT     14
+#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK     0x0000000000004000
+
+/*   SH_EVENT_OVERFLOW_PROC0_ERR_INT                                    */
+/*   Description:  Pending Processor 0 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT     15
+#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK     0x0000000000008000
+
+/*   SH_EVENT_OVERFLOW_PROC1_ERR_INT                                    */
+/*   Description:  Pending Processor 1 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT     16
+#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK     0x0000000000010000
+
+/*   SH_EVENT_OVERFLOW_PROC2_ERR_INT                                    */
+/*   Description:  Pending Processor 2 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT     17
+#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK     0x0000000000020000
+
+/*   SH_EVENT_OVERFLOW_PROC3_ERR_INT                                    */
+/*   Description:  Pending Processor 3 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT     18
+#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK     0x0000000000040000
+
+/*   SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT                              */
+/*   Description:  Pending System Shutdown Interrupt                    */
+#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19
+#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
+
+/*   SH_EVENT_OVERFLOW_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OVERFLOW_UART_INT_SHFT          20
+#define SH_EVENT_OVERFLOW_UART_INT_MASK          0x0000000000100000
+
+/*   SH_EVENT_OVERFLOW_L1_NMI_INT                                       */
+/*   Description:  Pending L1 Controller NMI Interrupt                  */
+#define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT        21
+#define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK        0x0000000000200000
+
+/*   SH_EVENT_OVERFLOW_STOP_CLOCK                                       */
+/*   Description:  Pending Stop Clock Interrupt                         */
+#define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT        22
+#define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK        0x0000000000400000
+
+/*   SH_EVENT_OVERFLOW_RTC0_INT                                         */
+/*   Description:  Pending RTC 0 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC0_INT_SHFT          23
+#define SH_EVENT_OVERFLOW_RTC0_INT_MASK          0x0000000000800000
+
+/*   SH_EVENT_OVERFLOW_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC1_INT_SHFT          24
+#define SH_EVENT_OVERFLOW_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OVERFLOW_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC2_INT_SHFT          25
+#define SH_EVENT_OVERFLOW_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OVERFLOW_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC3_INT_SHFT          26
+#define SH_EVENT_OVERFLOW_RTC3_INT_MASK          0x0000000004000000
+
+/*   SH_EVENT_OVERFLOW_PROFILE_INT                                      */
+/*   Description:  Pending Profile Interrupt                            */
+#define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT       27
+#define SH_EVENT_OVERFLOW_PROFILE_INT_MASK       0x0000000008000000
+
+/* ==================================================================== */
+/*                  Register "SH_EVENT_OVERFLOW_ALIAS"                  */
+/*             SHub Interrupt Event Occurred Overflow Alias             */
+/* ==================================================================== */
+
+#define SH_EVENT_OVERFLOW_ALIAS                  0x0000000110010088
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_TIME"                      */
+/*                           Junk Bus Timing                            */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_TIME                         0x0000000110020000
+#define SH_JUNK_BUS_TIME_MASK                    0x00000000ffffffff
+#define SH_JUNK_BUS_TIME_INIT                    0x0000000040404040
+
+/*   SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD                                  */
+/*   Description:  Fprom_Setup_Hold                                     */
+#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT   0
+#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK   0x00000000000000ff
+
+/*   SH_JUNK_BUS_TIME_FPROM_ENABLE                                      */
+/*   Description:  Fprom_Enable                                         */
+#define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT       8
+#define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK       0x000000000000ff00
+
+/*   SH_JUNK_BUS_TIME_UART_SETUP_HOLD                                   */
+/*   Description:  Uart_Setup_Hold                                      */
+#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT    16
+#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK    0x0000000000ff0000
+
+/*   SH_JUNK_BUS_TIME_UART_ENABLE                                       */
+/*   Description:  Uart_Enable                                          */
+#define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT        24
+#define SH_JUNK_BUS_TIME_UART_ENABLE_MASK        0x00000000ff000000
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_LATCH_TIME"                     */
+/*                        Junk Bus Latch Timing                         */
+/* ==================================================================== */
+
+#define SH_JUNK_LATCH_TIME                       0x0000000110020080
+#define SH_JUNK_LATCH_TIME_MASK                  0x0000000000000007
+#define SH_JUNK_LATCH_TIME_INIT                  0x0000000000000002
+
+/*   SH_JUNK_LATCH_TIME_SETUP_HOLD                                      */
+/*   Description:  Setup and Hold Time                                  */
+#define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT       0
+#define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK       0x0000000000000007
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_NACK_RESET"                     */
+/*                     Junk Bus Nack Counter Reset                      */
+/* ==================================================================== */
+
+#define SH_JUNK_NACK_RESET                       0x0000000110020100
+#define SH_JUNK_NACK_RESET_MASK                  0x0000000000000001
+#define SH_JUNK_NACK_RESET_INIT                  0x0000000000000000
+
+/*   SH_JUNK_NACK_RESET_PULSE                                           */
+/*   Description:  Junk bus nack counter reset                          */
+#define SH_JUNK_NACK_RESET_PULSE_SHFT            0
+#define SH_JUNK_NACK_RESET_PULSE_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED0"                      */
+/*                            Junk Bus LED0                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED0                         0x0000000110030000
+#define SH_JUNK_BUS_LED0_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED0_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED0_LED0_DATA                                         */
+/*   Description:  LED0_data                                            */
+#define SH_JUNK_BUS_LED0_LED0_DATA_SHFT          0
+#define SH_JUNK_BUS_LED0_LED0_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED1"                      */
+/*                            Junk Bus LED1                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED1                         0x0000000110030080
+#define SH_JUNK_BUS_LED1_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED1_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED1_LED1_DATA                                         */
+/*   Description:  LED1_data                                            */
+#define SH_JUNK_BUS_LED1_LED1_DATA_SHFT          0
+#define SH_JUNK_BUS_LED1_LED1_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED2"                      */
+/*                            Junk Bus LED2                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED2                         0x0000000110030100
+#define SH_JUNK_BUS_LED2_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED2_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED2_LED2_DATA                                         */
+/*   Description:  LED2_data                                            */
+#define SH_JUNK_BUS_LED2_LED2_DATA_SHFT          0
+#define SH_JUNK_BUS_LED2_LED2_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED3"                      */
+/*                            Junk Bus LED3                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED3                         0x0000000110030180
+#define SH_JUNK_BUS_LED3_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED3_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED3_LED3_DATA                                         */
+/*   Description:  LED3_data                                            */
+#define SH_JUNK_BUS_LED3_LED3_DATA_SHFT          0
+#define SH_JUNK_BUS_LED3_LED3_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_JUNK_ERROR_STATUS"                    */
+/*                        Junk Bus Error Status                         */
+/* ==================================================================== */
+
+#define SH_JUNK_ERROR_STATUS                     0x0000000110030200
+#define SH_JUNK_ERROR_STATUS_MASK                0x1fff7fffffffffff
+#define SH_JUNK_ERROR_STATUS_INIT                0x0000000000000000
+
+/*   SH_JUNK_ERROR_STATUS_ADDRESS                                       */
+/*   Description:  Failing junk bus address                             */
+#define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT        0
+#define SH_JUNK_ERROR_STATUS_ADDRESS_MASK        0x00007fffffffffff
+
+/*   SH_JUNK_ERROR_STATUS_CMD                                           */
+/*   Description:  Junk bus command                                     */
+#define SH_JUNK_ERROR_STATUS_CMD_SHFT            48
+#define SH_JUNK_ERROR_STATUS_CMD_MASK            0x00ff000000000000
+
+/*   SH_JUNK_ERROR_STATUS_MODE                                          */
+/*   Description:  Mode                                                 */
+#define SH_JUNK_ERROR_STATUS_MODE_SHFT           56
+#define SH_JUNK_ERROR_STATUS_MODE_MASK           0x0100000000000000
+
+/*   SH_JUNK_ERROR_STATUS_STATUS                                        */
+/*   Description:  Status                                               */
+#define SH_JUNK_ERROR_STATUS_STATUS_SHFT         57
+#define SH_JUNK_ERROR_STATUS_STATUS_MASK         0x1e00000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_STAT                          0x0000000150000000
+#define SH_NI0_LLP_STAT_MASK                     0x000000000000000f
+#define SH_NI0_LLP_STAT_INIT                     0x0000000000000000
+
+/*   SH_NI0_LLP_STAT_LINK_RESET_STATE                                   */
+/*   Description:  Status of LLP link.                                  */
+#define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT    0
+#define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK    0x000000000000000f
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_RESET                         0x0000000150000008
+#define SH_NI0_LLP_RESET_MASK                    0x0000000000000003
+#define SH_NI0_LLP_RESET_INIT                    0x0000000000000000
+
+/*   SH_NI0_LLP_RESET_LINK                                              */
+/*   Description:  Send Link Reset. Generates a pulse.                  */
+#define SH_NI0_LLP_RESET_LINK_SHFT               0
+#define SH_NI0_LLP_RESET_LINK_MASK               0x0000000000000001
+
+/*   SH_NI0_LLP_RESET_WARM                                              */
+/*   Description:  Send Warm Reset. Generates a pulse.                  */
+#define SH_NI0_LLP_RESET_WARM_SHFT               1
+#define SH_NI0_LLP_RESET_WARM_MASK               0x0000000000000002
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_RESET_EN                      0x0000000150000010
+#define SH_NI0_LLP_RESET_EN_MASK                 0x0000000000000001
+#define SH_NI0_LLP_RESET_EN_INIT                 0x0000000000000001
+
+/*   SH_NI0_LLP_RESET_EN_OK                                             */
+/*   Description:  Allow LLP warm reset to reset SHUB                   */
+#define SH_NI0_LLP_RESET_EN_OK_SHFT              0
+#define SH_NI0_LLP_RESET_EN_OK_MASK              0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CHAN_MODE                     0x0000000150000018
+#define SH_NI0_LLP_CHAN_MODE_MASK                0x000000000000001f
+#define SH_NI0_LLP_CHAN_MODE_INIT                0x0000000000000000
+
+/*   SH_NI0_LLP_CHAN_MODE_BITMODE32                                     */
+/*   Description:  Enables 32-bit (plus sideband) channel phits         */
+#define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT      0
+#define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK      0x0000000000000001
+
+/*   SH_NI0_LLP_CHAN_MODE_AC_ENCODE                                     */
+/*   Description:  Enables nearly dc-free encoding for AC-coupling      */
+#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT      1
+#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK      0x0000000000000002
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING                                 */
+/*   Description:  Enables automatic tuning of channel skew.            */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT  2
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK  0x0000000000000004
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD                             */
+/*   Description:  Enables remote fine tune updates                     */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD                                */
+/*   Description:  Enables quadrature clock in the pfssd                */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CONFIG                        0x0000000150000020
+#define SH_NI0_LLP_CONFIG_MASK                   0x0000003fffffffff
+#define SH_NI0_LLP_CONFIG_INIT                   0x00000007fc6ffd00
+
+/*   SH_NI0_LLP_CONFIG_MAXBURST                                         */
+#define SH_NI0_LLP_CONFIG_MAXBURST_SHFT          0
+#define SH_NI0_LLP_CONFIG_MAXBURST_MASK          0x00000000000003ff
+
+/*   SH_NI0_LLP_CONFIG_MAXRETRY                                         */
+#define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT          10
+#define SH_NI0_LLP_CONFIG_MAXRETRY_MASK          0x00000000000ffc00
+
+/*   SH_NI0_LLP_CONFIG_NULLTIMEOUT                                      */
+#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT       20
+#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK       0x0000000003f00000
+
+/*   SH_NI0_LLP_CONFIG_FTU_TIME                                         */
+#define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT          26
+#define SH_NI0_LLP_CONFIG_FTU_TIME_MASK          0x0000003ffc000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_TEST_CTL                      0x0000000150000028
+#define SH_NI0_LLP_TEST_CTL_MASK                 0x7ff3f3ffffffffff
+#define SH_NI0_LLP_TEST_CTL_INIT                 0x000000000a5fffff
+
+/*   SH_NI0_LLP_TEST_CTL_PATTERN                                        */
+/*   Description:  Send channel data pattern                            */
+#define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT         0
+#define SH_NI0_LLP_TEST_CTL_PATTERN_MASK         0x000000ffffffffff
+
+/*   SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE                                 */
+/*   Description:  Enables continuous send of data                      */
+#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT  40
+#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK  0x0000030000000000
+
+/*   SH_NI0_LLP_TEST_CTL_WIRE_SEL                                       */
+#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT        44
+#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK        0x0003f00000000000
+
+/*   SH_NI0_LLP_TEST_CTL_LFSR_MODE                                      */
+#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT       52
+#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK       0x0030000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_NOISE_MODE                                     */
+#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT      54
+#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK      0x00c0000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_ARMCAPTURE                                     */
+/*   Description:  Enable Capture of Next MicroPacket                   */
+#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT      56
+#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK      0x0100000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CAPTURECBONLY                                  */
+/*   Description:  Only capture a micropacket with a Check Byte error  */
+#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT   57
+#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK   0x0200000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_SENDCBERROR                                    */
+/*   Description:  Sends a single error                                 */
+#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT     58
+#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK     0x0400000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_SENDSNERROR                                    */
+/*   Description:  Sends a single sequence number error                 */
+#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT     59
+#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK     0x0800000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_FAKESNERROR                                    */
+/*   Description:  Causes receiver to pretend it saw a sn error         */
+#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT     60
+#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK     0x1000000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CAPTURED                                       */
+/*   Description:  Indicates a Valid Micropacket was captured           */
+#define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT        61
+#define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK        0x2000000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CBERROR                                        */
+/*   Description:  Indicates a Micropacket with a CB error was capture  */
+#define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT         62
+#define SH_NI0_LLP_TEST_CTL_CBERROR_MASK         0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_WD1                      0x0000000150000030
+#define SH_NI0_LLP_CAPT_WD1_MASK                 0xffffffffffffffff
+#define SH_NI0_LLP_CAPT_WD1_INIT                 0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_WD1_DATA                                           */
+/*   Description:  low order 64-bit captured word                       */
+#define SH_NI0_LLP_CAPT_WD1_DATA_SHFT            0
+#define SH_NI0_LLP_CAPT_WD1_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_WD2                      0x0000000150000038
+#define SH_NI0_LLP_CAPT_WD2_MASK                 0xffffffffffffffff
+#define SH_NI0_LLP_CAPT_WD2_INIT                 0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_WD2_DATA                                           */
+/*   Description:  high order 64-bit captured word                      */
+#define SH_NI0_LLP_CAPT_WD2_DATA_SHFT            0
+#define SH_NI0_LLP_CAPT_WD2_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_SBCB                     0x0000000150000040
+#define SH_NI0_LLP_CAPT_SBCB_MASK                0x0000001fffffffff
+#define SH_NI0_LLP_CAPT_SBCB_INIT                0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN                               */
+/*   Description:  sideband and sequence                                */
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
+
+/*   SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC                                */
+/*   Description:  CRC                                                  */
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
+
+/*   SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS                               */
+/*   Description:  All CB errors have been sent                         */
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS                               */
+/*   Description:  All SN errors have been sent                         */
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS                              */
+/*   Description:  All faked SN errors have been sent                   */
+#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
+#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW                                */
+/*   Description:  wire charge counter overflowed, valid if llp_mode e  */
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW                               */
+/*   Description:  wire charge counter underflowed, valid if llp_mode   */
+/*  enabled                                                             */
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_ERR"                       */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_ERR                           0x0000000150000048
+#define SH_NI0_LLP_ERR_MASK                      0x001fffffffffffff
+#define SH_NI0_LLP_ERR_INIT                      0x0000000000000000
+
+/*   SH_NI0_LLP_ERR_RX_SN_ERR_COUNT                                     */
+/*   Description:  Counts the sequence number errors received           */
+#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT      0
+#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK      0x00000000000000ff
+
+/*   SH_NI0_LLP_ERR_RX_CB_ERR_COUNT                                     */
+/*   Description:  Counts the check byte errors received                */
+#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT      8
+#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK      0x000000000000ff00
+
+/*   SH_NI0_LLP_ERR_RETRY_COUNT                                         */
+/*   Description:  Counts the retries                                   */
+#define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT          16
+#define SH_NI0_LLP_ERR_RETRY_COUNT_MASK          0x0000000000ff0000
+
+/*   SH_NI0_LLP_ERR_RETRY_TIMEOUT                                       */
+/*   Description:  Indicates a retry timeout has occured                */
+#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT        24
+#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK        0x0000000001000000
+
+/*   SH_NI0_LLP_ERR_RCV_LINK_RESET                                      */
+/*   Description:  Indicates a link reset has been received             */
+#define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT       25
+#define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK       0x0000000002000000
+
+/*   SH_NI0_LLP_ERR_SQUASH                                              */
+/*   Description:  Indicates a micropacket was squashed                 */
+#define SH_NI0_LLP_ERR_SQUASH_SHFT               26
+#define SH_NI0_LLP_ERR_SQUASH_MASK               0x0000000004000000
+
+/*   SH_NI0_LLP_ERR_POWER_NOT_OK                                        */
+/*   Description:  Detects and traps a loss of power_OK                 */
+#define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT         27
+#define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK         0x0000000008000000
+
+/*   SH_NI0_LLP_ERR_WIRE_CNT                                            */
+/*   Description:  counts the errors detected on a single wire test     */
+#define SH_NI0_LLP_ERR_WIRE_CNT_SHFT             28
+#define SH_NI0_LLP_ERR_WIRE_CNT_MASK             0x000ffffff0000000
+
+/*   SH_NI0_LLP_ERR_WIRE_OVERFLOW                                       */
+/*   Description:  wire_error_cnt has overflowed                        */
+#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT        52
+#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK        0x0010000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_STAT                          0x0000000150002000
+#define SH_NI1_LLP_STAT_MASK                     0x000000000000000f
+#define SH_NI1_LLP_STAT_INIT                     0x0000000000000000
+
+/*   SH_NI1_LLP_STAT_LINK_RESET_STATE                                   */
+/*   Description:  Status of LLP link.                                  */
+#define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT    0
+#define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK    0x000000000000000f
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_RESET                         0x0000000150002008
+#define SH_NI1_LLP_RESET_MASK                    0x0000000000000003
+#define SH_NI1_LLP_RESET_INIT                    0x0000000000000000
+
+/*   SH_NI1_LLP_RESET_LINK                                              */
+/*   Description:  Send Link Reset. Generates a pulse.                  */
+#define SH_NI1_LLP_RESET_LINK_SHFT               0
+#define SH_NI1_LLP_RESET_LINK_MASK               0x0000000000000001
+
+/*   SH_NI1_LLP_RESET_WARM                                              */
+/*   Description:  Send Warm Reset. Generates a pulse.                  */
+#define SH_NI1_LLP_RESET_WARM_SHFT               1
+#define SH_NI1_LLP_RESET_WARM_MASK               0x0000000000000002
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_RESET_EN                      0x0000000150002010
+#define SH_NI1_LLP_RESET_EN_MASK                 0x0000000000000001
+#define SH_NI1_LLP_RESET_EN_INIT                 0x0000000000000001
+
+/*   SH_NI1_LLP_RESET_EN_OK                                             */
+/*   Description:  Allow LLP warm reset to reset SHUB                   */
+#define SH_NI1_LLP_RESET_EN_OK_SHFT              0
+#define SH_NI1_LLP_RESET_EN_OK_MASK              0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CHAN_MODE                     0x0000000150002018
+#define SH_NI1_LLP_CHAN_MODE_MASK                0x000000000000001f
+#define SH_NI1_LLP_CHAN_MODE_INIT                0x0000000000000000
+
+/*   SH_NI1_LLP_CHAN_MODE_BITMODE32                                     */
+/*   Description:  Enables 32-bit (plus sideband) channel phits         */
+#define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT      0
+#define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK      0x0000000000000001
+
+/*   SH_NI1_LLP_CHAN_MODE_AC_ENCODE                                     */
+/*   Description:  Enables nearly dc-free encoding for AC-coupling      */
+#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT      1
+#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK      0x0000000000000002
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING                                 */
+/*   Description:  Enables automatic tuning of channel skew.            */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT  2
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK  0x0000000000000004
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD                             */
+/*   Description:  Enables remote fine tune updates                     */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD                                */
+/*   Description:  Enables quadrature clock in the pfssd                */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CONFIG                        0x0000000150002020
+#define SH_NI1_LLP_CONFIG_MASK                   0x0000003fffffffff
+#define SH_NI1_LLP_CONFIG_INIT                   0x00000007fc6ffd00
+
+/*   SH_NI1_LLP_CONFIG_MAXBURST                                         */
+#define SH_NI1_LLP_CONFIG_MAXBURST_SHFT          0
+#define SH_NI1_LLP_CONFIG_MAXBURST_MASK          0x00000000000003ff
+
+/*   SH_NI1_LLP_CONFIG_MAXRETRY                                         */
+#define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT          10
+#define SH_NI1_LLP_CONFIG_MAXRETRY_MASK          0x00000000000ffc00
+
+/*   SH_NI1_LLP_CONFIG_NULLTIMEOUT                                      */
+#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT       20
+#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK       0x0000000003f00000
+
+/*   SH_NI1_LLP_CONFIG_FTU_TIME                                         */
+#define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT          26
+#define SH_NI1_LLP_CONFIG_FTU_TIME_MASK          0x0000003ffc000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_TEST_CTL                      0x0000000150002028
+#define SH_NI1_LLP_TEST_CTL_MASK                 0x7ff3f3ffffffffff
+#define SH_NI1_LLP_TEST_CTL_INIT                 0x000000000a5fffff
+
+/*   SH_NI1_LLP_TEST_CTL_PATTERN                                        */
+/*   Description:  Send channel data pattern                            */
+#define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT         0
+#define SH_NI1_LLP_TEST_CTL_PATTERN_MASK         0x000000ffffffffff
+
+/*   SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE                                 */
+/*   Description:  Enables continuous send of data                      */
+#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT  40
+#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK  0x0000030000000000
+
+/*   SH_NI1_LLP_TEST_CTL_WIRE_SEL                                       */
+#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT        44
+#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK        0x0003f00000000000
+
+/*   SH_NI1_LLP_TEST_CTL_LFSR_MODE                                      */
+#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT       52
+#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK       0x0030000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_NOISE_MODE                                     */
+#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT      54
+#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK      0x00c0000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_ARMCAPTURE                                     */
+/*   Description:  Enable Capture of Next MicroPacket                   */
+#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT      56
+#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK      0x0100000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CAPTURECBONLY                                  */
+/*   Description:  Only capture a micropacket with a Check Byte error  */
+#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT   57
+#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK   0x0200000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_SENDCBERROR                                    */
+/*   Description:  Sends a single error                                 */
+#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT     58
+#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK     0x0400000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_SENDSNERROR                                    */
+/*   Description:  Sends a single sequence number error                 */
+#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT     59
+#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK     0x0800000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_FAKESNERROR                                    */
+/*   Description:  Causes receiver to pretend it saw a sn error         */
+#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT     60
+#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK     0x1000000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CAPTURED                                       */
+/*   Description:  Indicates a Valid Micropacket was captured           */
+#define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT        61
+#define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK        0x2000000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CBERROR                                        */
+/*   Description:  Indicates a Micropacket with a CB error was capture  */
+#define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT         62
+#define SH_NI1_LLP_TEST_CTL_CBERROR_MASK         0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_WD1                      0x0000000150002030
+#define SH_NI1_LLP_CAPT_WD1_MASK                 0xffffffffffffffff
+#define SH_NI1_LLP_CAPT_WD1_INIT                 0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_WD1_DATA                                           */
+/*   Description:  low order 64-bit captured word                       */
+#define SH_NI1_LLP_CAPT_WD1_DATA_SHFT            0
+#define SH_NI1_LLP_CAPT_WD1_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_WD2                      0x0000000150002038
+#define SH_NI1_LLP_CAPT_WD2_MASK                 0xffffffffffffffff
+#define SH_NI1_LLP_CAPT_WD2_INIT                 0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_WD2_DATA                                           */
+/*   Description:  high order 64-bit captured word                      */
+#define SH_NI1_LLP_CAPT_WD2_DATA_SHFT            0
+#define SH_NI1_LLP_CAPT_WD2_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_SBCB                     0x0000000150002040
+#define SH_NI1_LLP_CAPT_SBCB_MASK                0x0000001fffffffff
+#define SH_NI1_LLP_CAPT_SBCB_INIT                0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN                               */
+/*   Description:  sideband and sequence                                */
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
+
+/*   SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC                                */
+/*   Description:  CRC                                                  */
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
+
+/*   SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS                               */
+/*   Description:  All CB errors have been sent                         */
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS                               */
+/*   Description:  All SN errors have been sent                         */
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS                              */
+/*   Description:  All faked SN errors have been sent                   */
+#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
+#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW                                */
+/*   Description:  wire charge counter overflowed, valid if llp_mode e  */
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW                               */
+/*   Description:  wire charge counter underflowed, valid if llp_mode   */
+/*  enabled                                                             */
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_ERR"                       */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_ERR                           0x0000000150002048
+#define SH_NI1_LLP_ERR_MASK                      0x001fffffffffffff
+#define SH_NI1_LLP_ERR_INIT                      0x0000000000000000
+
+/*   SH_NI1_LLP_ERR_RX_SN_ERR_COUNT                                     */
+/*   Description:  Counts the sequence number errors received           */
+#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT      0
+#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK      0x00000000000000ff
+
+/*   SH_NI1_LLP_ERR_RX_CB_ERR_COUNT                                     */
+/*   Description:  Counts the check byte errors received                */
+#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT      8
+#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK      0x000000000000ff00
+
+/*   SH_NI1_LLP_ERR_RETRY_COUNT                                         */
+/*   Description:  Counts the retries                                   */
+#define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT          16
+#define SH_NI1_LLP_ERR_RETRY_COUNT_MASK          0x0000000000ff0000
+
+/*   SH_NI1_LLP_ERR_RETRY_TIMEOUT                                       */
+/*   Description:  Indicates a retry timeout has occured                */
+#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT        24
+#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK        0x0000000001000000
+
+/*   SH_NI1_LLP_ERR_RCV_LINK_RESET                                      */
+/*   Description:  Indicates a link reset has been received             */
+#define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT       25
+#define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK       0x0000000002000000
+
+/*   SH_NI1_LLP_ERR_SQUASH                                              */
+/*   Description:  Indicates a micropacket was squashed                 */
+#define SH_NI1_LLP_ERR_SQUASH_SHFT               26
+#define SH_NI1_LLP_ERR_SQUASH_MASK               0x0000000004000000
+
+/*   SH_NI1_LLP_ERR_POWER_NOT_OK                                        */
+/*   Description:  Detects and traps a loss of power_OK                 */
+#define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT         27
+#define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK         0x0000000008000000
+
+/*   SH_NI1_LLP_ERR_WIRE_CNT                                            */
+/*   Description:  counts the errors detected on a single wire test     */
+#define SH_NI1_LLP_ERR_WIRE_CNT_SHFT             28
+#define SH_NI1_LLP_ERR_WIRE_CNT_MASK             0x000ffffff0000000
+
+/*   SH_NI1_LLP_ERR_WIRE_OVERFLOW                                       */
+/*   Description:  wire_error_cnt has overflowed                        */
+#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT        52
+#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK        0x0010000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW              0x0000000150001010
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW              0x0000000150001020
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_DEBIT_FLOW                  0x0000000150001030
+#define SH_XNNI0_LLP_DEBIT_FLOW_MASK             0x1f1f1f1f1f1f1f1f
+#define SH_XNNI0_LLP_DEBIT_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN                              */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP                              */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN                              */
+/*   Description:  vc1 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP                              */
+/*   Description:  vc1 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN                              */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP                              */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN                              */
+/*   Description:  vc3 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP                              */
+/*   Description:  vc3 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_0_FLOW                     0x0000000150001040
+#define SH_XNNI0_LINK_0_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_0_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD                            */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED                          */
+/*   Description:  Force Credit on vc0 from debit cntr                  */
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST                               */
+/*   Description:  vc0 Limit Test                                       */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN                                */
+/*   Description:  Dynamic vc0 credit value                             */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP                                */
+/*   Description:  Captured vc0 credit                                  */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_1_FLOW                     0x0000000150001050
+#define SH_XNNI0_LINK_1_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_1_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD                            */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED                          */
+/*   Description:  Force Credit on vc1 from debit cntr                  */
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST                               */
+/*   Description:  vc1 Limit Test                                       */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN                                */
+/*   Description:  Dynamic vc1 credit value                             */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP                                */
+/*   Description:  Captured vc1 credit                                  */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_2_FLOW                     0x0000000150001060
+#define SH_XNNI0_LINK_2_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_2_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD                            */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED                          */
+/*   Description:  Force Credit on vc2 from debit cntr                  */
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST                               */
+/*   Description:  vc2 Limit Test                                       */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN                                */
+/*   Description:  Dynamic vc2 credit value                             */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP                                */
+/*   Description:  Captured vc2 credit                                  */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_3_FLOW                     0x0000000150001070
+#define SH_XNNI0_LINK_3_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_3_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD                            */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED                          */
+/*   Description:  Force Credit on vc3 from debit cntr                  */
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST                               */
+/*   Description:  vc3 Limit Test                                       */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN                                */
+/*   Description:  Dynamic vc3 credit value                             */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP                                */
+/*   Description:  Captured vc3 credit                                  */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW              0x0000000150003010
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW              0x0000000150003020
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_DEBIT_FLOW                  0x0000000150003030
+#define SH_XNNI1_LLP_DEBIT_FLOW_MASK             0x1f1f1f1f1f1f1f1f
+#define SH_XNNI1_LLP_DEBIT_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN                              */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP                              */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN                              */
+/*   Description:  vc1 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP                              */
+/*   Description:  vc1 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN                              */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP                              */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN                              */
+/*   Description:  vc3 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP                              */
+/*   Description:  vc3 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_0_FLOW                     0x0000000150003040
+#define SH_XNNI1_LINK_0_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_0_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD                            */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED                          */
+/*   Description:  Force Credit on vc0 from debit cntr                  */
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST                               */
+/*   Description:  vc0 Limit Test                                       */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN                                */
+/*   Description:  Dynamic vc0 credit value                             */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP                                */
+/*   Description:  Captured vc0 credit                                  */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_1_FLOW                     0x0000000150003050
+#define SH_XNNI1_LINK_1_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_1_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD                            */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED                          */
+/*   Description:  Force Credit on vc1 from debit cntr                  */
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST                               */
+/*   Description:  vc1 Limit Test                                       */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN                                */
+/*   Description:  Dynamic vc1 credit value                             */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP                                */
+/*   Description:  Captured vc1 credit                                  */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_2_FLOW                     0x0000000150003060
+#define SH_XNNI1_LINK_2_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_2_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD                            */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED                          */
+/*   Description:  Force Credit on vc2 from debit cntr                  */
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST                               */
+/*   Description:  vc2 Limit Test                                       */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN                                */
+/*   Description:  Dynamic vc2 credit value                             */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP                                */
+/*   Description:  Captured vc2 credit                                  */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_3_FLOW                     0x0000000150003070
+#define SH_XNNI1_LINK_3_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_3_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD                            */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED                          */
+/*   Description:  Force Credit on vc3 from debit cntr                  */
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST                               */
+/*   Description:  vc3 Limit Test                                       */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN                                */
+/*   Description:  Dynamic vc3 credit value                             */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP                                */
+/*   Description:  Captured vc3 credit                                  */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                    Register "SH_IILB_LOCAL_TABLE"                    */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_IILB_LOCAL_TABLE                      0x0000000150020000
+#define SH_IILB_LOCAL_TABLE_MASK                 0x800000000000003f
+#define SH_IILB_LOCAL_TABLE_MEMDEPTH             128
+#define SH_IILB_LOCAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_IILB_LOCAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_LOCAL_TABLE_DIR0_SHFT            0
+#define SH_IILB_LOCAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_IILB_LOCAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_LOCAL_TABLE_V0_SHFT              4
+#define SH_IILB_LOCAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_IILB_LOCAL_TABLE_NI_SEL0                                        */
+/*   Description:  ni select for requests                               */
+#define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT         5
+#define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK         0x0000000000000020
+
+/*   SH_IILB_LOCAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_IILB_LOCAL_TABLE_VALID_SHFT           63
+#define SH_IILB_LOCAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_IILB_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_IILB_GLOBAL_TABLE                     0x0000000150020400
+#define SH_IILB_GLOBAL_TABLE_MASK                0x800000000000003f
+#define SH_IILB_GLOBAL_TABLE_MEMDEPTH            16
+#define SH_IILB_GLOBAL_TABLE_INIT                0x0000000000000000
+
+/*   SH_IILB_GLOBAL_TABLE_DIR0                                          */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_GLOBAL_TABLE_DIR0_SHFT           0
+#define SH_IILB_GLOBAL_TABLE_DIR0_MASK           0x000000000000000f
+
+/*   SH_IILB_GLOBAL_TABLE_V0                                            */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_GLOBAL_TABLE_V0_SHFT             4
+#define SH_IILB_GLOBAL_TABLE_V0_MASK             0x0000000000000010
+
+/*   SH_IILB_GLOBAL_TABLE_NI_SEL0                                       */
+/*   Description:  ni select for requests                               */
+#define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT        5
+#define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK        0x0000000000000020
+
+/*   SH_IILB_GLOBAL_TABLE_VALID                                         */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_IILB_GLOBAL_TABLE_VALID_SHFT          63
+#define SH_IILB_GLOBAL_TABLE_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_OVER_RIDE_TABLE"                  */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_IILB_OVER_RIDE_TABLE                  0x0000000150020480
+#define SH_IILB_OVER_RIDE_TABLE_MASK             0x800000000000003f
+#define SH_IILB_OVER_RIDE_TABLE_INIT             0x8000000000000000
+
+/*   SH_IILB_OVER_RIDE_TABLE_DIR0                                       */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT        0
+#define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK        0x000000000000000f
+
+/*   SH_IILB_OVER_RIDE_TABLE_V0                                         */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_OVER_RIDE_TABLE_V0_SHFT          4
+#define SH_IILB_OVER_RIDE_TABLE_V0_MASK          0x0000000000000010
+
+/*   SH_IILB_OVER_RIDE_TABLE_NI_SEL0                                    */
+/*   Description:  ni select                                            */
+#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT     5
+#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK     0x0000000000000020
+
+/*   SH_IILB_OVER_RIDE_TABLE_ENABLE                                     */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT      63
+#define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_IILB_RSP_PLANE_HINT                   0x0000000150020488
+#define SH_IILB_RSP_PLANE_HINT_MASK              0x0000000000000000
+#define SH_IILB_RSP_PLANE_HINT_INIT              0x0000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_PI_LOCAL_TABLE                        0x0000000150021000
+#define SH_PI_LOCAL_TABLE_MASK                   0x8000000000003f3f
+#define SH_PI_LOCAL_TABLE_MEMDEPTH               128
+#define SH_PI_LOCAL_TABLE_INIT                   0x0000000000000000
+
+/*   SH_PI_LOCAL_TABLE_DIR0                                             */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_LOCAL_TABLE_DIR0_SHFT              0
+#define SH_PI_LOCAL_TABLE_DIR0_MASK              0x000000000000000f
+
+/*   SH_PI_LOCAL_TABLE_V0                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_LOCAL_TABLE_V0_SHFT                4
+#define SH_PI_LOCAL_TABLE_V0_MASK                0x0000000000000010
+
+/*   SH_PI_LOCAL_TABLE_NI_SEL0                                          */
+/*   Description:  ni select for requests                               */
+#define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT           5
+#define SH_PI_LOCAL_TABLE_NI_SEL0_MASK           0x0000000000000020
+
+/*   SH_PI_LOCAL_TABLE_DIR1                                             */
+#define SH_PI_LOCAL_TABLE_DIR1_SHFT              8
+#define SH_PI_LOCAL_TABLE_DIR1_MASK              0x0000000000000f00
+
+/*   SH_PI_LOCAL_TABLE_V1                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_LOCAL_TABLE_V1_SHFT                12
+#define SH_PI_LOCAL_TABLE_V1_MASK                0x0000000000001000
+
+/*   SH_PI_LOCAL_TABLE_NI_SEL1                                          */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT           13
+#define SH_PI_LOCAL_TABLE_NI_SEL1_MASK           0x0000000000002000
+
+/*   SH_PI_LOCAL_TABLE_VALID                                            */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_PI_LOCAL_TABLE_VALID_SHFT             63
+#define SH_PI_LOCAL_TABLE_VALID_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_PI_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_PI_GLOBAL_TABLE                       0x0000000150021400
+#define SH_PI_GLOBAL_TABLE_MASK                  0x8000000000003f3f
+#define SH_PI_GLOBAL_TABLE_MEMDEPTH              16
+#define SH_PI_GLOBAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_PI_GLOBAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_GLOBAL_TABLE_DIR0_SHFT             0
+#define SH_PI_GLOBAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_PI_GLOBAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_GLOBAL_TABLE_V0_SHFT               4
+#define SH_PI_GLOBAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_PI_GLOBAL_TABLE_NI_SEL0                                         */
+/*   Description:  ni select for requests                               */
+#define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT          5
+#define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK          0x0000000000000020
+
+/*   SH_PI_GLOBAL_TABLE_DIR1                                            */
+#define SH_PI_GLOBAL_TABLE_DIR1_SHFT             8
+#define SH_PI_GLOBAL_TABLE_DIR1_MASK             0x0000000000000f00
+
+/*   SH_PI_GLOBAL_TABLE_V1                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_GLOBAL_TABLE_V1_SHFT               12
+#define SH_PI_GLOBAL_TABLE_V1_MASK               0x0000000000001000
+
+/*   SH_PI_GLOBAL_TABLE_NI_SEL1                                         */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT          13
+#define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK          0x0000000000002000
+
+/*   SH_PI_GLOBAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_PI_GLOBAL_TABLE_VALID_SHFT            63
+#define SH_PI_GLOBAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_PI_OVER_RIDE_TABLE                    0x0000000150021480
+#define SH_PI_OVER_RIDE_TABLE_MASK               0x8000000000003f3f
+#define SH_PI_OVER_RIDE_TABLE_INIT               0x8000000000002000
+
+/*   SH_PI_OVER_RIDE_TABLE_DIR0                                         */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT          0
+#define SH_PI_OVER_RIDE_TABLE_DIR0_MASK          0x000000000000000f
+
+/*   SH_PI_OVER_RIDE_TABLE_V0                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_OVER_RIDE_TABLE_V0_SHFT            4
+#define SH_PI_OVER_RIDE_TABLE_V0_MASK            0x0000000000000010
+
+/*   SH_PI_OVER_RIDE_TABLE_NI_SEL0                                      */
+/*   Description:  ni select                                            */
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT       5
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK       0x0000000000000020
+
+/*   SH_PI_OVER_RIDE_TABLE_DIR1                                         */
+#define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT          8
+#define SH_PI_OVER_RIDE_TABLE_DIR1_MASK          0x0000000000000f00
+
+/*   SH_PI_OVER_RIDE_TABLE_V1                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_OVER_RIDE_TABLE_V1_SHFT            12
+#define SH_PI_OVER_RIDE_TABLE_V1_MASK            0x0000000000001000
+
+/*   SH_PI_OVER_RIDE_TABLE_NI_SEL1                                      */
+/*   Description:  ni select                                            */
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT       13
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK       0x0000000000002000
+
+/*   SH_PI_OVER_RIDE_TABLE_ENABLE                                       */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT        63
+#define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_PI_RSP_PLANE_HINT                     0x0000000150021488
+#define SH_PI_RSP_PLANE_HINT_MASK                0x0000000000000001
+#define SH_PI_RSP_PLANE_HINT_INIT                0x0000000000000000
+
+/*   SH_PI_RSP_PLANE_HINT_INVERT                                        */
+/*   Description:  Invert Response Plane Hint                           */
+#define SH_PI_RSP_PLANE_HINT_INVERT_SHFT         0
+#define SH_PI_RSP_PLANE_HINT_INVERT_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI0_LOCAL_TABLE                       0x0000000150022000
+#define SH_NI0_LOCAL_TABLE_MASK                  0x800000000000001f
+#define SH_NI0_LOCAL_TABLE_MEMDEPTH              128
+#define SH_NI0_LOCAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_NI0_LOCAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_LOCAL_TABLE_DIR0_SHFT             0
+#define SH_NI0_LOCAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_NI0_LOCAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_LOCAL_TABLE_V0_SHFT               4
+#define SH_NI0_LOCAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_NI0_LOCAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI0_LOCAL_TABLE_VALID_SHFT            63
+#define SH_NI0_LOCAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI0_GLOBAL_TABLE                      0x0000000150022400
+#define SH_NI0_GLOBAL_TABLE_MASK                 0x800000000000001f
+#define SH_NI0_GLOBAL_TABLE_MEMDEPTH             16
+#define SH_NI0_GLOBAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_NI0_GLOBAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_GLOBAL_TABLE_DIR0_SHFT            0
+#define SH_NI0_GLOBAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_NI0_GLOBAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_GLOBAL_TABLE_V0_SHFT              4
+#define SH_NI0_GLOBAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_NI0_GLOBAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI0_GLOBAL_TABLE_VALID_SHFT           63
+#define SH_NI0_GLOBAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_NI0_OVER_RIDE_TABLE                   0x0000000150022480
+#define SH_NI0_OVER_RIDE_TABLE_MASK              0x800000000000001f
+#define SH_NI0_OVER_RIDE_TABLE_INIT              0x8000000000000000
+
+/*   SH_NI0_OVER_RIDE_TABLE_DIR0                                        */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT         0
+#define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK         0x000000000000000f
+
+/*   SH_NI0_OVER_RIDE_TABLE_V0                                          */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_OVER_RIDE_TABLE_V0_SHFT           4
+#define SH_NI0_OVER_RIDE_TABLE_V0_MASK           0x0000000000000010
+
+/*   SH_NI0_OVER_RIDE_TABLE_ENABLE                                      */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT       63
+#define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_NI0_RSP_PLANE_HINT                    0x0000000150022488
+#define SH_NI0_RSP_PLANE_HINT_MASK               0x0000000000000000
+#define SH_NI0_RSP_PLANE_HINT_INIT               0x0000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI1_LOCAL_TABLE                       0x0000000150023000
+#define SH_NI1_LOCAL_TABLE_MASK                  0x800000000000001f
+#define SH_NI1_LOCAL_TABLE_MEMDEPTH              128
+#define SH_NI1_LOCAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_NI1_LOCAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_LOCAL_TABLE_DIR0_SHFT             0
+#define SH_NI1_LOCAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_NI1_LOCAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_LOCAL_TABLE_V0_SHFT               4
+#define SH_NI1_LOCAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_NI1_LOCAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI1_LOCAL_TABLE_VALID_SHFT            63
+#define SH_NI1_LOCAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI1_GLOBAL_TABLE                      0x0000000150023400
+#define SH_NI1_GLOBAL_TABLE_MASK                 0x800000000000001f
+#define SH_NI1_GLOBAL_TABLE_MEMDEPTH             16
+#define SH_NI1_GLOBAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_NI1_GLOBAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_GLOBAL_TABLE_DIR0_SHFT            0
+#define SH_NI1_GLOBAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_NI1_GLOBAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_GLOBAL_TABLE_V0_SHFT              4
+#define SH_NI1_GLOBAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_NI1_GLOBAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI1_GLOBAL_TABLE_VALID_SHFT           63
+#define SH_NI1_GLOBAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_NI1_OVER_RIDE_TABLE                   0x0000000150023480
+#define SH_NI1_OVER_RIDE_TABLE_MASK              0x800000000000001f
+#define SH_NI1_OVER_RIDE_TABLE_INIT              0x8000000000000000
+
+/*   SH_NI1_OVER_RIDE_TABLE_DIR0                                        */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT         0
+#define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK         0x000000000000000f
+
+/*   SH_NI1_OVER_RIDE_TABLE_V0                                          */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_OVER_RIDE_TABLE_V0_SHFT           4
+#define SH_NI1_OVER_RIDE_TABLE_V0_MASK           0x0000000000000010
+
+/*   SH_NI1_OVER_RIDE_TABLE_ENABLE                                      */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT       63
+#define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_NI1_RSP_PLANE_HINT                    0x0000000150023488
+#define SH_NI1_RSP_PLANE_HINT_MASK               0x0000000000000000
+#define SH_NI1_RSP_PLANE_HINT_INIT               0x0000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_MD_LOCAL_TABLE                        0x0000000150024000
+#define SH_MD_LOCAL_TABLE_MASK                   0x8000000000003f3f
+#define SH_MD_LOCAL_TABLE_MEMDEPTH               128
+#define SH_MD_LOCAL_TABLE_INIT                   0x0000000000000000
+
+/*   SH_MD_LOCAL_TABLE_DIR0                                             */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_LOCAL_TABLE_DIR0_SHFT              0
+#define SH_MD_LOCAL_TABLE_DIR0_MASK              0x000000000000000f
+
+/*   SH_MD_LOCAL_TABLE_V0                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_LOCAL_TABLE_V0_SHFT                4
+#define SH_MD_LOCAL_TABLE_V0_MASK                0x0000000000000010
+
+/*   SH_MD_LOCAL_TABLE_NI_SEL0                                          */
+/*   Description:  ni select for requests                               */
+#define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT           5
+#define SH_MD_LOCAL_TABLE_NI_SEL0_MASK           0x0000000000000020
+
+/*   SH_MD_LOCAL_TABLE_DIR1                                             */
+#define SH_MD_LOCAL_TABLE_DIR1_SHFT              8
+#define SH_MD_LOCAL_TABLE_DIR1_MASK              0x0000000000000f00
+
+/*   SH_MD_LOCAL_TABLE_V1                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_LOCAL_TABLE_V1_SHFT                12
+#define SH_MD_LOCAL_TABLE_V1_MASK                0x0000000000001000
+
+/*   SH_MD_LOCAL_TABLE_NI_SEL1                                          */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT           13
+#define SH_MD_LOCAL_TABLE_NI_SEL1_MASK           0x0000000000002000
+
+/*   SH_MD_LOCAL_TABLE_VALID                                            */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_MD_LOCAL_TABLE_VALID_SHFT             63
+#define SH_MD_LOCAL_TABLE_VALID_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_MD_GLOBAL_TABLE                       0x0000000150024400
+#define SH_MD_GLOBAL_TABLE_MASK                  0x8000000000003f3f
+#define SH_MD_GLOBAL_TABLE_MEMDEPTH              16
+#define SH_MD_GLOBAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_MD_GLOBAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_GLOBAL_TABLE_DIR0_SHFT             0
+#define SH_MD_GLOBAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_MD_GLOBAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_GLOBAL_TABLE_V0_SHFT               4
+#define SH_MD_GLOBAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_MD_GLOBAL_TABLE_NI_SEL0                                         */
+/*   Description:  ni select for requests                               */
+#define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT          5
+#define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK          0x0000000000000020
+
+/*   SH_MD_GLOBAL_TABLE_DIR1                                            */
+#define SH_MD_GLOBAL_TABLE_DIR1_SHFT             8
+#define SH_MD_GLOBAL_TABLE_DIR1_MASK             0x0000000000000f00
+
+/*   SH_MD_GLOBAL_TABLE_V1                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_GLOBAL_TABLE_V1_SHFT               12
+#define SH_MD_GLOBAL_TABLE_V1_MASK               0x0000000000001000
+
+/*   SH_MD_GLOBAL_TABLE_NI_SEL1                                         */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT          13
+#define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK          0x0000000000002000
+
+/*   SH_MD_GLOBAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_MD_GLOBAL_TABLE_VALID_SHFT            63
+#define SH_MD_GLOBAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_MD_OVER_RIDE_TABLE                    0x0000000150024480
+#define SH_MD_OVER_RIDE_TABLE_MASK               0x8000000000003f3f
+#define SH_MD_OVER_RIDE_TABLE_INIT               0x8000000000002000
+
+/*   SH_MD_OVER_RIDE_TABLE_DIR0                                         */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT          0
+#define SH_MD_OVER_RIDE_TABLE_DIR0_MASK          0x000000000000000f
+
+/*   SH_MD_OVER_RIDE_TABLE_V0                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_OVER_RIDE_TABLE_V0_SHFT            4
+#define SH_MD_OVER_RIDE_TABLE_V0_MASK            0x0000000000000010
+
+/*   SH_MD_OVER_RIDE_TABLE_NI_SEL0                                      */
+/*   Description:  ni select                                            */
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT       5
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK       0x0000000000000020
+
+/*   SH_MD_OVER_RIDE_TABLE_DIR1                                         */
+#define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT          8
+#define SH_MD_OVER_RIDE_TABLE_DIR1_MASK          0x0000000000000f00
+
+/*   SH_MD_OVER_RIDE_TABLE_V1                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_OVER_RIDE_TABLE_V1_SHFT            12
+#define SH_MD_OVER_RIDE_TABLE_V1_MASK            0x0000000000001000
+
+/*   SH_MD_OVER_RIDE_TABLE_NI_SEL1                                      */
+/*   Description:  ni select                                            */
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT       13
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK       0x0000000000002000
+
+/*   SH_MD_OVER_RIDE_TABLE_ENABLE                                       */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT        63
+#define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_MD_RSP_PLANE_HINT                     0x0000000150024488
+#define SH_MD_RSP_PLANE_HINT_MASK                0x0000000000000001
+#define SH_MD_RSP_PLANE_HINT_INIT                0x0000000000000000
+
+/*   SH_MD_RSP_PLANE_HINT_INVERT                                        */
+/*   Description:  Invert Response Plane Hint                           */
+#define SH_MD_RSP_PLANE_HINT_INVERT_SHFT         0
+#define SH_MD_RSP_PLANE_HINT_INVERT_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LIQ_CTL"                       */
+/*                       Local Block LIQ Control                        */
+/* ==================================================================== */
+
+#define SH_LB_LIQ_CTL                            0x0000000110040000
+#define SH_LB_LIQ_CTL_MASK                       0x0000000000070f1f
+#define SH_LB_LIQ_CTL_INIT                       0x0000000000000000
+
+/*   SH_LB_LIQ_CTL_LIQ_REQ_CTL                                          */
+/*   Description:  LIQ Request Control                                  */
+#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT           0
+#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK           0x000000000000001f
+
+/*   SH_LB_LIQ_CTL_LIQ_RPL_CTL                                          */
+/*   Description:  LIQ Reply Control                                    */
+#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT           8
+#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK           0x0000000000000f00
+
+/*   SH_LB_LIQ_CTL_FORCE_RQ_CREDIT                                      */
+/*   Description:  Force request credit                                 */
+#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT       16
+#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK       0x0000000000010000
+
+/*   SH_LB_LIQ_CTL_FORCE_RP_CREDIT                                      */
+/*   Description:  Force reply credit                                   */
+#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT       17
+#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK       0x0000000000020000
+
+/*   SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT                                   */
+/*   Description:  Force linvv credit                                   */
+#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT    18
+#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK    0x0000000000040000
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LOQ_CTL"                       */
+/*                       Local Block LOQ Control                        */
+/* ==================================================================== */
+
+#define SH_LB_LOQ_CTL                            0x0000000110040080
+#define SH_LB_LOQ_CTL_MASK                       0x0000000000000003
+#define SH_LB_LOQ_CTL_INIT                       0x0000000000000000
+
+/*   SH_LB_LOQ_CTL_LOQ_REQ_CTL                                          */
+/*   Description:  LOQ Request Control                                  */
+#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT           0
+#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK           0x0000000000000001
+
+/*   SH_LB_LOQ_CTL_LOQ_RPL_CTL                                          */
+/*   Description:  LOQ Reply Control                                    */
+#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT           1
+#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK           0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REP_CREDIT_CNT"                  */
+/*               Maximum number of reply credits from XN                */
+/* ==================================================================== */
+
+#define SH_LB_MAX_REP_CREDIT_CNT                 0x0000000110040100
+#define SH_LB_MAX_REP_CREDIT_CNT_MASK            0x000000000000001f
+#define SH_LB_MAX_REP_CREDIT_CNT_INIT            0x000000000000001f
+
+/*   SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT                                   */
+/*   Description:  Max reply credits                                    */
+#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT    0
+#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK    0x000000000000001f
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REQ_CREDIT_CNT"                  */
+/*              Maximum number of request credits from XN               */
+/* ==================================================================== */
+
+#define SH_LB_MAX_REQ_CREDIT_CNT                 0x0000000110040180
+#define SH_LB_MAX_REQ_CREDIT_CNT_MASK            0x000000000000001f
+#define SH_LB_MAX_REQ_CREDIT_CNT_INIT            0x000000000000001f
+
+/*   SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT                                   */
+/*   Description:  Max request credits                                  */
+#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT    0
+#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK    0x000000000000001f
+
+/* ==================================================================== */
+/*                      Register "SH_PIO_TIME_OUT"                      */
+/*                    Local Block PIO time out value                    */
+/* ==================================================================== */
+
+#define SH_PIO_TIME_OUT                          0x0000000110040200
+#define SH_PIO_TIME_OUT_MASK                     0x000000000000ffff
+#define SH_PIO_TIME_OUT_INIT                     0x0000000000000400
+
+/*   SH_PIO_TIME_OUT_VALUE                                              */
+/*   Description:  PIO time out value                                   */
+#define SH_PIO_TIME_OUT_VALUE_SHFT               0
+#define SH_PIO_TIME_OUT_VALUE_MASK               0x000000000000ffff
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_NACK_RESET"                     */
+/*               Local Block PIO Reset for nack counters                */
+/* ==================================================================== */
+
+#define SH_PIO_NACK_RESET                        0x0000000110040280
+#define SH_PIO_NACK_RESET_MASK                   0x0000000000000001
+#define SH_PIO_NACK_RESET_INIT                   0x0000000000000000
+
+/*   SH_PIO_NACK_RESET_PULSE                                            */
+/*   Description:  PIO nack counter reset                               */
+#define SH_PIO_NACK_RESET_PULSE_SHFT             0
+#define SH_PIO_NACK_RESET_PULSE_MASK             0x0000000000000001
+
+/* ==================================================================== */
+/*                 Register "SH_CONVEYOR_BELT_TIME_OUT"                 */
+/*               Local Block conveyor belt time out value               */
+/* ==================================================================== */
+
+#define SH_CONVEYOR_BELT_TIME_OUT                0x0000000110040300
+#define SH_CONVEYOR_BELT_TIME_OUT_MASK           0x0000000000000fff
+#define SH_CONVEYOR_BELT_TIME_OUT_INIT           0x0000000000000000
+
+/*   SH_CONVEYOR_BELT_TIME_OUT_VALUE                                    */
+/*   Description:  Conveyor belt time out value                         */
+#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT     0
+#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK     0x0000000000000fff
+
+/* ==================================================================== */
+/*                    Register "SH_LB_CREDIT_STATUS"                    */
+/*                    Credit Counter Status Register                    */
+/* ==================================================================== */
+
+#define SH_LB_CREDIT_STATUS                      0x0000000110050000
+#define SH_LB_CREDIT_STATUS_MASK                 0x000000000ffff3df
+#define SH_LB_CREDIT_STATUS_INIT                 0x0000000000000000
+
+/*   SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT                                  */
+/*   Description:  LIQ request queue credit counter                     */
+#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT   0
+#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK   0x000000000000001f
+
+/*   SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT                                  */
+/*   Description:  LIQ reply queue credit counter                       */
+#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT   6
+#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK   0x00000000000003c0
+
+/*   SH_LB_CREDIT_STATUS_LINVV_CREDIT                                   */
+/*   Description:  LINVV credit counter                                 */
+#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT    12
+#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK    0x000000000003f000
+
+/*   SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT                                  */
+/*   Description:  LOQ request queue credit counter                     */
+#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT   18
+#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK   0x00000000007c0000
+
+/*   SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT                                  */
+/*   Description:  LOQ reply queue credit counter                       */
+#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT   23
+#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK   0x000000000f800000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_LOCAL_SEL"                   */
+/*                         LB Debug Port Select                         */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_LOCAL_SEL                    0x0000000110050080
+#define SH_LB_DEBUG_LOCAL_SEL_MASK               0xf777777777777777
+#define SH_LB_DEBUG_LOCAL_SEL_INIT               0x0000000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL                          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL                          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL                          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL                          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL                          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL                          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL                          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL                          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE                               */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63
+#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_PERF_SEL"                    */
+/*                   LB Debug Port Performance Select                   */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_PERF_SEL                     0x0000000110050100
+#define SH_LB_DEBUG_PERF_SEL_MASK                0x7777777777777777
+#define SH_LB_DEBUG_PERF_SEL_INIT                0x0000000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL                           */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL                            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL                           */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL                            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL                           */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL                            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL                           */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL                            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL                           */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL                            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL                           */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL                            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL                           */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL                            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL                           */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL                            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_TRIG_SEL"                    */
+/*                       LB Debug Trigger Select                        */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_TRIG_SEL                     0x0000000110050180
+#define SH_LB_DEBUG_TRIG_SEL_MASK                0x7777777777777777
+#define SH_LB_DEBUG_TRIG_SEL_INIT                0x0000000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL                          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL                          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL                          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL                          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL                          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL                          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL                          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL                          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_1"                    */
+/*                  LB Error capture information: HDR1                  */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_1                     0x0000000110050200
+#define SH_LB_ERROR_DETAIL_1_MASK                0x8003073fff3fffff
+#define SH_LB_ERROR_DETAIL_1_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_COMMAND                                       */
+/*   Description:  COMMAND                                              */
+#define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT        0
+#define SH_LB_ERROR_DETAIL_1_COMMAND_MASK        0x00000000000000ff
+
+/*   SH_LB_ERROR_DETAIL_1_SUPPL                                         */
+/*   Description:  SUPPLMENTAL                                          */
+#define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT          8
+#define SH_LB_ERROR_DETAIL_1_SUPPL_MASK          0x00000000003fff00
+
+/*   SH_LB_ERROR_DETAIL_1_SOURCE                                        */
+/*   Description:  SOURCE                                               */
+#define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT         24
+#define SH_LB_ERROR_DETAIL_1_SOURCE_MASK         0x0000003fff000000
+
+/*   SH_LB_ERROR_DETAIL_1_DEST                                          */
+/*   Description:  DEST                                                 */
+#define SH_LB_ERROR_DETAIL_1_DEST_SHFT           40
+#define SH_LB_ERROR_DETAIL_1_DEST_MASK           0x0000070000000000
+
+/*   SH_LB_ERROR_DETAIL_1_HDR_ERR                                       */
+/*   Description:  HDR_ERR                                              */
+#define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT        48
+#define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK        0x0001000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_DATA_ERR                                      */
+/*   Description:  DATA_ERR                                             */
+#define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT       49
+#define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK       0x0002000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_VALID                                         */
+/*   Description:  VALID                                                */
+#define SH_LB_ERROR_DETAIL_1_VALID_SHFT          63
+#define SH_LB_ERROR_DETAIL_1_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_2"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_2                     0x0000000110050280
+#define SH_LB_ERROR_DETAIL_2_MASK                0x00007fffffffffff
+#define SH_LB_ERROR_DETAIL_2_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_2_ADDRESS                                       */
+/*   Description:  ADDRESS                                              */
+#define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT        0
+#define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK        0x00007fffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_3"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_3                     0x0000000110050300
+#define SH_LB_ERROR_DETAIL_3_MASK                0xffffffffffffffff
+#define SH_LB_ERROR_DETAIL_3_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_3_DATA                                          */
+/*   Description:  DATA                                                 */
+#define SH_LB_ERROR_DETAIL_3_DATA_SHFT           0
+#define SH_LB_ERROR_DETAIL_3_DATA_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_4"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_4                     0x0000000110050380
+#define SH_LB_ERROR_DETAIL_4_MASK                0xffffffffffffffff
+#define SH_LB_ERROR_DETAIL_4_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_4_ROUTE                                         */
+/*   Description:  ROUTE                                                */
+#define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT          0
+#define SH_LB_ERROR_DETAIL_4_ROUTE_MASK          0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_5"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_5                     0x0000000110050400
+#define SH_LB_ERROR_DETAIL_5_MASK                0x000000000000007f
+#define SH_LB_ERROR_DETAIL_5_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_5_READ_RETRY                                    */
+/*   Description:  Read retry error                                     */
+#define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT     0
+#define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK     0x0000000000000001
+
+/*   SH_LB_ERROR_DETAIL_5_PTC1_WRITE                                    */
+/*   Description:  PTC1 write error                                     */
+#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT     1
+#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK     0x0000000000000002
+
+/*   SH_LB_ERROR_DETAIL_5_WRITE_RETRY                                   */
+/*   Description:  Write retry error                                    */
+#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT    2
+#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK    0x0000000000000004
+
+/*   SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW                              */
+/*   Description:  Nack A counter overflow error                        */
+#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3
+#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW                              */
+/*   Description:  Nack B counter overflow error                        */
+#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4
+#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010
+
+/*   SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT                                */
+/*   Description:  Nack A counter timeout error                         */
+#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5
+#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020
+
+/*   SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT                                */
+/*   Description:  Nack B counter timeout error                         */
+#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6
+#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040
+
+/* ==================================================================== */
+/*                     Register "SH_LB_ERROR_MASK"                      */
+/*                            LB Error Mask                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_MASK                         0x0000000110050480
+#define SH_LB_ERROR_MASK_MASK                    0x00000000007fffff
+#define SH_LB_ERROR_MASK_INIT                    0x00000000007fffff
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_CMD                                        */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT         0
+#define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK         0x0000000000000001
+
+/*   SH_LB_ERROR_MASK_RP_BAD_CMD                                        */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT         1
+#define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK         0x0000000000000002
+
+/*   SH_LB_ERROR_MASK_RQ_SHORT                                          */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_ERROR_MASK_RQ_SHORT_SHFT           2
+#define SH_LB_ERROR_MASK_RQ_SHORT_MASK           0x0000000000000004
+
+/*   SH_LB_ERROR_MASK_RP_SHORT                                          */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_ERROR_MASK_RP_SHORT_SHFT           3
+#define SH_LB_ERROR_MASK_RP_SHORT_MASK           0x0000000000000008
+
+/*   SH_LB_ERROR_MASK_RQ_LONG                                           */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_ERROR_MASK_RQ_LONG_SHFT            4
+#define SH_LB_ERROR_MASK_RQ_LONG_MASK            0x0000000000000010
+
+/*   SH_LB_ERROR_MASK_RP_LONG                                           */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_ERROR_MASK_RP_LONG_SHFT            5
+#define SH_LB_ERROR_MASK_RP_LONG_MASK            0x0000000000000020
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_DATA                                       */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT        6
+#define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK        0x0000000000000040
+
+/*   SH_LB_ERROR_MASK_RP_BAD_DATA                                       */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT        7
+#define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK        0x0000000000000080
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_ADDR                                       */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT        8
+#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK        0x0000000000000100
+
+/*   SH_LB_ERROR_MASK_RQ_TIME_OUT                                       */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT        9
+#define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK        0x0000000000000200
+
+/*   SH_LB_ERROR_MASK_LINVV_OVERFLOW                                    */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT     10
+#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK     0x0000000000000400
+
+/*   SH_LB_ERROR_MASK_UNEXPECTED_LINV                                   */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT    11
+#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK    0x0000000000000800
+
+/*   SH_LB_ERROR_MASK_PTC_1_TIMEOUT                                     */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT      12
+#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK      0x0000000000001000
+
+/*   SH_LB_ERROR_MASK_JUNK_BUS_ERR                                      */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT       13
+#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK       0x0000000000002000
+
+/*   SH_LB_ERROR_MASK_PIO_CB_ERR                                        */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT         14
+#define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK         0x0000000000004000
+
+/*   SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR                             */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR                             */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_MASK_GCLK_DROP                                         */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_ERROR_MASK_GCLK_DROP_SHFT          17
+#define SH_LB_ERROR_MASK_GCLK_DROP_MASK          0x0000000000020000
+
+/*   SH_LB_ERROR_MASK_RQ_FIFO_ERROR                                     */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT      18
+#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK      0x0000000000040000
+
+/*   SH_LB_ERROR_MASK_RP_FIFO_ERROR                                     */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT      19
+#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK      0x0000000000080000
+
+/*   SH_LB_ERROR_MASK_UNEXP_VALID                                       */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT        20
+#define SH_LB_ERROR_MASK_UNEXP_VALID_MASK        0x0000000000100000
+
+/*   SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW                                */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW                                */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_OVERFLOW"                    */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_OVERFLOW                     0x0000000110050500
+#define SH_LB_ERROR_OVERFLOW_MASK                0x00000000007fffff
+#define SH_LB_ERROR_OVERFLOW_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL                              */
+/*   Description:  RQ_BAD_CMD_OVRFL                                     */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001
+
+/*   SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL                              */
+/*   Description:  RP_BAD_CMD_OVRFL                                     */
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL                                */
+/*   Description:  RQ_SHORT_OVRFL                                       */
+#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2
+#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004
+
+/*   SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL                                */
+/*   Description:  RP_SHORT_OVRFL                                       */
+#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3
+#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL                                 */
+/*   Description:  RQ_LONG_OVRFL                                        */
+#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT  4
+#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK  0x0000000000000010
+
+/*   SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL                                 */
+/*   Description:  RP_LONG_OVRFL                                        */
+#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT  5
+#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK  0x0000000000000020
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL                             */
+/*   Description:  RQ_BAD_DATA_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040
+
+/*   SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL                             */
+/*   Description:  RP_BAD_DATA_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL                             */
+/*   Description:  RQ_BAD_ADDR_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL                             */
+/*   Description:  RQ_TIME_OUT_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9
+#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200
+
+/*   SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL                          */
+/*   Description:  LINVV_OVERFLOW_OVRFL                                 */
+#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10
+#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400
+
+/*   SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL                         */
+/*   Description:  UNEXPECTED_LINV_OVRFL                                */
+#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11
+#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800
+
+/*   SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL                           */
+/*   Description:  PTC_1 Time out overflow                              */
+#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12
+#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000
+
+/*   SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL                            */
+/*   Description:  Junk Bus error overflow                              */
+#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13
+#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000
+
+/*   SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL                              */
+/*   Description:  PIO Conveyor Belt operation error overflow           */
+#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14
+#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000
+
+/*   SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL                   */
+/*   Description:  Vector request Route data was invalid overflow       */
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL                   */
+/*   Description:  Vector reply Route data was invalid overflow         */
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL                               */
+/*   Description:  Gclk drop error overflow                             */
+#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17
+#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL                           */
+/*   Description:  Request queue FIFO error overflow                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18
+#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000
+
+/*   SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL                           */
+/*   Description:  Reply queue FIFO error overflow                      */
+#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19
+#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000
+
+/*   SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL                             */
+/*   Description:  Unexpected valid error overflow                      */
+#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20
+#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL                      */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21
+#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL                      */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22
+#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                Register "SH_LB_ERROR_OVERFLOW_ALIAS"                 */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_OVERFLOW_ALIAS               0x0000000110050508
+
+/* ==================================================================== */
+/*                    Register "SH_LB_ERROR_SUMMARY"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_SUMMARY                      0x0000000110050580
+#define SH_LB_ERROR_SUMMARY_MASK                 0x00000000007fffff
+#define SH_LB_ERROR_SUMMARY_INIT                 0x0000000000000000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_CMD                                     */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT      0
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK      0x0000000000000001
+
+/*   SH_LB_ERROR_SUMMARY_RP_BAD_CMD                                     */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT      1
+#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK      0x0000000000000002
+
+/*   SH_LB_ERROR_SUMMARY_RQ_SHORT                                       */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT        2
+#define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK        0x0000000000000004
+
+/*   SH_LB_ERROR_SUMMARY_RP_SHORT                                       */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT        3
+#define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK        0x0000000000000008
+
+/*   SH_LB_ERROR_SUMMARY_RQ_LONG                                        */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT         4
+#define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK         0x0000000000000010
+
+/*   SH_LB_ERROR_SUMMARY_RP_LONG                                        */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT         5
+#define SH_LB_ERROR_SUMMARY_RP_LONG_MASK         0x0000000000000020
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_DATA                                    */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT     6
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK     0x0000000000000040
+
+/*   SH_LB_ERROR_SUMMARY_RP_BAD_DATA                                    */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT     7
+#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK     0x0000000000000080
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR                                    */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT     8
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK     0x0000000000000100
+
+/*   SH_LB_ERROR_SUMMARY_RQ_TIME_OUT                                    */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT     9
+#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK     0x0000000000000200
+
+/*   SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW                                 */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT  10
+#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK  0x0000000000000400
+
+/*   SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV                                */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11
+#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800
+
+/*   SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT                                  */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT   12
+#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK   0x0000000000001000
+
+/*   SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR                                   */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT    13
+#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK    0x0000000000002000
+
+/*   SH_LB_ERROR_SUMMARY_PIO_CB_ERR                                     */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT      14
+#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK      0x0000000000004000
+
+/*   SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR                          */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR                          */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_SUMMARY_GCLK_DROP                                      */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT       17
+#define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK       0x0000000000020000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR                                  */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT   18
+#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK   0x0000000000040000
+
+/*   SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR                                  */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT   19
+#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK   0x0000000000080000
+
+/*   SH_LB_ERROR_SUMMARY_UNEXP_VALID                                    */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT     20
+#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK     0x0000000000100000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW                             */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW                             */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                 Register "SH_LB_ERROR_SUMMARY_ALIAS"                 */
+/*                         LB Error Bits Alias                          */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_SUMMARY_ALIAS                0x0000000110050588
+
+/* ==================================================================== */
+/*                     Register "SH_LB_FIRST_ERROR"                     */
+/*                            LB First Error                            */
+/* ==================================================================== */
+
+#define SH_LB_FIRST_ERROR                        0x0000000110050600
+#define SH_LB_FIRST_ERROR_MASK                   0x00000000007fffff
+#define SH_LB_FIRST_ERROR_INIT                   0x0000000000000000
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_CMD                                       */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT        0
+#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK        0x0000000000000001
+
+/*   SH_LB_FIRST_ERROR_RP_BAD_CMD                                       */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT        1
+#define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK        0x0000000000000002
+
+/*   SH_LB_FIRST_ERROR_RQ_SHORT                                         */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT          2
+#define SH_LB_FIRST_ERROR_RQ_SHORT_MASK          0x0000000000000004
+
+/*   SH_LB_FIRST_ERROR_RP_SHORT                                         */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_FIRST_ERROR_RP_SHORT_SHFT          3
+#define SH_LB_FIRST_ERROR_RP_SHORT_MASK          0x0000000000000008
+
+/*   SH_LB_FIRST_ERROR_RQ_LONG                                          */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_FIRST_ERROR_RQ_LONG_SHFT           4
+#define SH_LB_FIRST_ERROR_RQ_LONG_MASK           0x0000000000000010
+
+/*   SH_LB_FIRST_ERROR_RP_LONG                                          */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_FIRST_ERROR_RP_LONG_SHFT           5
+#define SH_LB_FIRST_ERROR_RP_LONG_MASK           0x0000000000000020
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_DATA                                      */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT       6
+#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK       0x0000000000000040
+
+/*   SH_LB_FIRST_ERROR_RP_BAD_DATA                                      */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT       7
+#define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK       0x0000000000000080
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_ADDR                                      */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT       8
+#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK       0x0000000000000100
+
+/*   SH_LB_FIRST_ERROR_RQ_TIME_OUT                                      */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT       9
+#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK       0x0000000000000200
+
+/*   SH_LB_FIRST_ERROR_LINVV_OVERFLOW                                   */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT    10
+#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK    0x0000000000000400
+
+/*   SH_LB_FIRST_ERROR_UNEXPECTED_LINV                                  */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT   11
+#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK   0x0000000000000800
+
+/*   SH_LB_FIRST_ERROR_PTC_1_TIMEOUT                                    */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT     12
+#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK     0x0000000000001000
+
+/*   SH_LB_FIRST_ERROR_JUNK_BUS_ERR                                     */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT      13
+#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK      0x0000000000002000
+
+/*   SH_LB_FIRST_ERROR_PIO_CB_ERR                                       */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT        14
+#define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK        0x0000000000004000
+
+/*   SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR                            */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR                            */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_FIRST_ERROR_GCLK_DROP                                        */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT         17
+#define SH_LB_FIRST_ERROR_GCLK_DROP_MASK         0x0000000000020000
+
+/*   SH_LB_FIRST_ERROR_RQ_FIFO_ERROR                                    */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT     18
+#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK     0x0000000000040000
+
+/*   SH_LB_FIRST_ERROR_RP_FIFO_ERROR                                    */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT     19
+#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK     0x0000000000080000
+
+/*   SH_LB_FIRST_ERROR_UNEXP_VALID                                      */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT       20
+#define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK       0x0000000000100000
+
+/*   SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW                               */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW                               */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                     Register "SH_LB_LAST_CREDIT"                     */
+/*                    Credit counter status register                    */
+/* ==================================================================== */
+
+#define SH_LB_LAST_CREDIT                        0x0000000110050680
+#define SH_LB_LAST_CREDIT_MASK                   0x000000000ffff3df
+#define SH_LB_LAST_CREDIT_INIT                   0x0000000000000000
+
+/*   SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT                                    */
+/*   Description:  LIQ request queue credit counter                     */
+#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT     0
+#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK     0x000000000000001f
+
+/*   SH_LB_LAST_CREDIT_LIQ_RP_CREDIT                                    */
+/*   Description:  LIQ reply queue credit counter                       */
+#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT     6
+#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK     0x00000000000003c0
+
+/*   SH_LB_LAST_CREDIT_LINVV_CREDIT                                     */
+/*   Description:  LINVV credit counter                                 */
+#define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT      12
+#define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK      0x000000000003f000
+
+/*   SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT                                    */
+/*   Description:  LOQ request queue credit counter                     */
+#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT     18
+#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK     0x00000000007c0000
+
+/*   SH_LB_LAST_CREDIT_LOQ_RP_CREDIT                                    */
+/*   Description:  LOQ reply queue credit counter                       */
+#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT     23
+#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK     0x000000000f800000
+
+/* ==================================================================== */
+/*                     Register "SH_LB_NACK_STATUS"                     */
+/*                     Nack Counter Status Register                     */
+/* ==================================================================== */
+
+#define SH_LB_NACK_STATUS                        0x0000000110050700
+#define SH_LB_NACK_STATUS_MASK                   0x3fffffff0fff0fff
+#define SH_LB_NACK_STATUS_INIT                   0x0000000000000000
+
+/*   SH_LB_NACK_STATUS_PIO_NACK_A                                       */
+/*   Description:  PIO nackA counter                                    */
+#define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT        0
+#define SH_LB_NACK_STATUS_PIO_NACK_A_MASK        0x0000000000000fff
+
+/*   SH_LB_NACK_STATUS_PIO_NACK_B                                       */
+/*   Description:  PIO nackA counter                                    */
+#define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT        16
+#define SH_LB_NACK_STATUS_PIO_NACK_B_MASK        0x000000000fff0000
+
+/*   SH_LB_NACK_STATUS_JUNK_NACK                                        */
+/*   Description:  Junk bus nack counter                                */
+#define SH_LB_NACK_STATUS_JUNK_NACK_SHFT         32
+#define SH_LB_NACK_STATUS_JUNK_NACK_MASK         0x0000ffff00000000
+
+/*   SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT                                 */
+/*   Description:  Conveyor belt time out counter                       */
+#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT  48
+#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK  0x0fff000000000000
+
+/*   SH_LB_NACK_STATUS_CB_STATE                                         */
+/*   Description:  Conveyor belt state                                  */
+#define SH_LB_NACK_STATUS_CB_STATE_SHFT          60
+#define SH_LB_NACK_STATUS_CB_STATE_MASK          0x3000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_TRIGGER_COMPARE"                   */
+/*                    LB Test-point Trigger Compare                     */
+/* ==================================================================== */
+
+#define SH_LB_TRIGGER_COMPARE                    0x0000000110050780
+#define SH_LB_TRIGGER_COMPARE_MASK               0x00000000ffffffff
+#define SH_LB_TRIGGER_COMPARE_INIT               0x0000000000000000
+
+/*   SH_LB_TRIGGER_COMPARE_MASK                                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_LB_TRIGGER_COMPARE_MASK_SHFT          0
+#define SH_LB_TRIGGER_COMPARE_MASK_MASK          0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_LB_TRIGGER_DATA"                     */
+/*                  LB Test-point Trigger Compare Data                  */
+/* ==================================================================== */
+
+#define SH_LB_TRIGGER_DATA                       0x0000000110050800
+#define SH_LB_TRIGGER_DATA_MASK                  0x00000000ffffffff
+#define SH_LB_TRIGGER_DATA_INIT                  0x00000000ffffffff
+
+/*   SH_LB_TRIGGER_DATA_COMPARE_PATTERN                                 */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT  0
+#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_CONFIG"                      */
+/*              PI Adaptive Error Correction Configuration              */
+/* ==================================================================== */
+
+#define SH_PI_AEC_CONFIG                         0x0000000120050000
+#define SH_PI_AEC_CONFIG_MASK                    0x0000000000000007
+#define SH_PI_AEC_CONFIG_INIT                    0x0000000000000000
+
+/*   SH_PI_AEC_CONFIG_MODE                                              */
+/*   Description:  AEC Operation Mode                                   */
+#define SH_PI_AEC_CONFIG_MODE_SHFT               0
+#define SH_PI_AEC_CONFIG_MODE_MASK               0x0000000000000007
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_ERROR_MASK"                    */
+/*                          PI AFI Error Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_AFI_ERROR_MASK                     0x0000000120050080
+#define SH_PI_AFI_ERROR_MASK_MASK                0x00000007ffe00000
+#define SH_PI_AFI_ERROR_MASK_INIT                0x00000007ffe00000
+
+/*   SH_PI_AFI_ERROR_MASK_HUNG_BUS                                      */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT       21
+#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK       0x0000000000200000
+
+/*   SH_PI_AFI_ERROR_MASK_RSP_PARITY                                    */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT     22
+#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK     0x0000000000400000
+
+/*   SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN                                   */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT    23
+#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK    0x0000000000800000
+
+/*   SH_PI_AFI_ERROR_MASK_REQ_FORMAT                                    */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT     24
+#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK     0x0000000001000000
+
+/*   SH_PI_AFI_ERROR_MASK_ADDR_ACCESS                                   */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT    25
+#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK    0x0000000002000000
+
+/*   SH_PI_AFI_ERROR_MASK_REQ_PARITY                                    */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT     26
+#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK     0x0000000004000000
+
+/*   SH_PI_AFI_ERROR_MASK_ADDR_PARITY                                   */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT    27
+#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK    0x0000000008000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE                                  */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT   28
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK   0x0000000010000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT   29
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK   0x0000000020000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT    30
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK    0x0000000040000000
+
+/*   SH_PI_AFI_ERROR_MASK_LIVELOCK                                      */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT       31
+#define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK       0x0000000080000000
+
+/*   SH_PI_AFI_ERROR_MASK_BAD_SNOOP                                     */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT      32
+#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK      0x0000000100000000
+
+/*   SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS                                  */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT   33
+#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK   0x0000000200000000
+
+/*   SH_PI_AFI_ERROR_MASK_MSG_LEN                                       */
+/*   Description:  Runt or Obese message received from SIC              */
+#define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT        34
+#define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK        0x0000000400000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_AFI_TEST_POINT_COMPARE"                */
+/*                      PI AFI Test Point Compare                       */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_COMPARE             0x0000000120050100
+#define SH_PI_AFI_TEST_POINT_COMPARE_MASK        0xffffffffffffffff
+#define SH_PI_AFI_TEST_POINT_COMPARE_INIT        0xffffffff00000000
+
+/*   SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK                          */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN                       */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_AFI_TEST_POINT_SELECT"                */
+/*                       PI AFI Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_SELECT              0x0000000120050180
+#define SH_PI_AFI_TEST_POINT_SELECT_MASK         0xff7f7f7f7f7f7f7f
+#define SH_PI_AFI_TEST_POINT_SELECT_INIT         0x0000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                    */
+/*   Description:  Nibble 0: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                     */
+/*   Description:  Nibble 0: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                    */
+/*   Description:  Nibble 1: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                     */
+/*   Description:  Nibble 1: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                    */
+/*   Description:  Nibble 2: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                     */
+/*   Description:  Nibble 2: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                    */
+/*   Description:  Nibble 3: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                     */
+/*   Description:  Nibble 3: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                    */
+/*   Description:  Nibble 4: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                     */
+/*   Description:  Nibble 4: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                    */
+/*   Description:  Nibble 5: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                     */
+/*   Description:  Nibble 5: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                    */
+/*   Description:  Nibble 6: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                     */
+/*   Description:  Nibble 6: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                    */
+/*   Description:  Nibble 7: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                     */
+/*   Description:  Nibble 7: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE                         */
+/*   Description:  Trigger Enabled                                      */
+#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*            Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT      0x0000000120050200
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL           */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL           */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL           */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL           */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL           */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL           */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL           */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL           */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_AUTO_REPLY_ENABLE"                  */
+/*                         PI Auto Reply Enable                         */
+/* ==================================================================== */
+
+#define SH_PI_AUTO_REPLY_ENABLE                  0x0000000120050280
+#define SH_PI_AUTO_REPLY_ENABLE_MASK             0x0000000000000001
+#define SH_PI_AUTO_REPLY_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE                          */
+/*   Description:  Auto Reply Enabled                                   */
+#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0
+#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_CONTROL                        0x0000000120050300
+#define SH_PI_CAM_CONTROL_MASK                   0x800000000000037f
+#define SH_PI_CAM_CONTROL_INIT                   0x0000000000000000
+
+/*   SH_PI_CAM_CONTROL_CAM_INDX                                         */
+/*   Description:  CRB CAM Index to perform read/write on.              */
+#define SH_PI_CAM_CONTROL_CAM_INDX_SHFT          0
+#define SH_PI_CAM_CONTROL_CAM_INDX_MASK          0x000000000000007f
+
+/*   SH_PI_CAM_CONTROL_CAM_WRITE                                        */
+/*   Description:  Is CRB CAM MMR function a write.                     */
+#define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT         8
+#define SH_PI_CAM_CONTROL_CAM_WRITE_MASK         0x0000000000000100
+
+/*   SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR                                */
+/*   Description:  Clear RRB read tranfer pending.                      */
+#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9
+#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200
+
+/*   SH_PI_CAM_CONTROL_START                                            */
+/*   Description:  Start CRB CAM read/write operation                   */
+#define SH_PI_CAM_CONTROL_START_SHFT             63
+#define SH_PI_CAM_CONTROL_START_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_COMPARE"               */
+/*                      PI CRBC Test Point Compare                      */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_COMPARE            0x0000000120050380
+#define SH_PI_CRBC_TEST_POINT_COMPARE_MASK       0xffffffffffffffff
+#define SH_PI_CRBC_TEST_POINT_COMPARE_INIT       0xffffffff00000000
+
+/*   SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN                      */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_SELECT"                */
+/*                      PI CRBC Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_SELECT             0x0000000120050400
+#define SH_PI_CRBC_TEST_POINT_SELECT_MASK        0xf777777777777777
+#define SH_PI_CRBC_TEST_POINT_SELECT_INIT        0x0000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                   */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                    */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                   */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                    */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                   */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                    */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                   */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                    */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                   */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                    */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                   */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                    */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                   */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                    */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                   */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                    */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE                        */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT     0x0000000120050480
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_CRBP_ERROR_MASK"                   */
+/*                          PI CRBP Error Mask                          */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_ERROR_MASK                    0x0000000120050500
+#define SH_PI_CRBP_ERROR_MASK_MASK               0x00000000001fffff
+#define SH_PI_CRBP_ERROR_MASK_INIT               0x00000000001fffff
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR                                */
+/*   Description:  Mask detection internal protocol table misses        */
+#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0
+#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR                                   */
+/*   Description:  Mask graphic reply error detection                   */
+#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT    1
+#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK    0x0000000000000002
+
+/*   SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR                                 */
+/*   Description:  Mask detection of external protocol table misses     */
+#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT  2
+#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK  0x0000000000000004
+
+/*   SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR                                   */
+/*   Description:  Mask memory error reply message detection            */
+#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT    3
+#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK    0x0000000000000008
+
+/*   SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR                                   */
+/*   Description:  Mask PIO reply error message detection               */
+#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT    4
+#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK    0x0000000000000010
+
+/*   SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR                                   */
+/*   Description:  Mask memory time-out detection                       */
+#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT    5
+#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK    0x0000000000000020
+
+/*   SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR                                   */
+/*   Description:  Mask PIO time-out detection                          */
+#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT    6
+#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK    0x0000000000000040
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE                                 */
+/*   Description:  Mask un-correctable ECC error detection              */
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT  7
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK  0x0000000000000080
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE                                  */
+/*   Description:  Mask correctable ECC error detection                 */
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT   8
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK   0x0000000000000100
+
+/*   SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR                                */
+/*   Description:  Mask detection of color errors                       */
+#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9
+#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW                                */
+/*   Description:  Mask MD Request input buffer over flow error         */
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW                                */
+/*   Description:  Mask MD Reply input buffer over flow error           */
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW                                */
+/*   Description:  Mask XN Request input buffer over flow error         */
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW                                */
+/*   Description:  Mask XN Reply input buffer over flow error           */
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000
+
+/*   SH_PI_CRBP_ERROR_MASK_NACK_OFLOW                                   */
+/*   Description:  Mask NACK over flow error                            */
+#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT    14
+#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK    0x0000000000004000
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_INT_0                                    */
+/*   Description:  Mask GFX transfer interrupt for CPU 0                */
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT     15
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK     0x0000000000008000
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_INT_1                                    */
+/*   Description:  Mask GFX transfer interrupt for CPU 1                */
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT     16
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK     0x0000000000010000
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW                              */
+/*   Description:  Mask MD Request Credit Overflow Error                */
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW                              */
+/*   Description:  Mask MD Reply Credit Overflow Error                  */
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW                              */
+/*   Description:  Mask XN Request Credit Overflow Error                */
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW                              */
+/*   Description:  Mask XN Reply Credit Overflow Error                  */
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/* ==================================================================== */
+/*                Register "SH_PI_CRBP_FSB_PIPE_COMPARE"                */
+/*                        CRBP FSB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FSB_PIPE_COMPARE              0x0000000120050580
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK         0x001fffffffffffff
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT         0x0000000000000000
+
+/*   SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS                        */
+/*   Description:  Address A or B to compare against                    */
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ                            */
+/*   Description:  REQa or REQb value to compare against                */
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_FSB_PIPE_MASK"                  */
+/*                          CRBP Compare Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FSB_PIPE_MASK                 0x0000000120050600
+#define SH_PI_CRBP_FSB_PIPE_MASK_MASK            0x001fffffffffffff
+#define SH_PI_CRBP_FSB_PIPE_MASK_INIT            0x0000000000000000
+
+/*   SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK                      */
+/*   Description:  Address A or B mask values                           */
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK                          */
+/*   Description:  REQa or REQb mask values                             */
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_COMPARE"               */
+/*                      PI CRBP Test Point Compare                      */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_COMPARE            0x0000000120050680
+#define SH_PI_CRBP_TEST_POINT_COMPARE_MASK       0xffffffffffffffff
+#define SH_PI_CRBP_TEST_POINT_COMPARE_INIT       0xffffffff00000000
+
+/*   SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN                      */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_SELECT"                */
+/*                      PI CRBP Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_SELECT             0x0000000120050700
+#define SH_PI_CRBP_TEST_POINT_SELECT_MASK        0xf777777777777777
+#define SH_PI_CRBP_TEST_POINT_SELECT_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                   */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                    */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                   */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                    */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                   */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                    */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                   */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                    */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                   */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                    */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                   */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                    */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                   */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                    */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                   */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                    */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE                        */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBP Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT     0x0000000120050780
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_0"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0             0x0000000120050800
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK        0x007fffffffffffff
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS                       */
+/*   Description:  Address to compare against                           */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND                       */
+/*   Description:  SN2NET Command to compare against                    */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_1"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1             0x0000000120050880
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK        0x000001ff3fff3fff
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE                        */
+/*   Description:  Source to compare against                            */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL                  */
+/*   Description:  Supplemental to compare against                      */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO                          */
+/*   Description:  Echo to compare against                              */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_0"                 */
+/*                     CRBP Compare Mask Register 1                     */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_MASK_0                0x0000000120050900
+#define SH_PI_CRBP_XB_PIPE_MASK_0_MASK           0x007fffffffffffff
+#define SH_PI_CRBP_XB_PIPE_MASK_0_INIT           0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK                     */
+/*   Description:  Address to compare against                           */
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK                     */
+/*   Description:  SN2NET Command to compare against                    */
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_1"                 */
+/*                 CRBP XB Pipe Compare Mask Register 1                 */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_MASK_1                0x0000000120050980
+#define SH_PI_CRBP_XB_PIPE_MASK_1_MASK           0x000001ff3fff3fff
+#define SH_PI_CRBP_XB_PIPE_MASK_1_INIT           0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK                      */
+/*   Description:  Source to compare against                            */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK                */
+/*   Description:  Supplemental to compare against                      */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK                        */
+/*   Description:  Echo to compare against                              */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_DPC_QUEUE_CONFIG"                   */
+/*                       DPC Queue Configuration                        */
+/* ==================================================================== */
+
+#define SH_PI_DPC_QUEUE_CONFIG                   0x0000000120050a00
+#define SH_PI_DPC_QUEUE_CONFIG_MASK              0x000000001f1f1f1f
+#define SH_PI_DPC_QUEUE_CONFIG_INIT              0x000000000c010c01
+
+/*   SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL                               */
+/*   Description:  DXB WTL Command Queue Almost Empty Level             */
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f
+
+/*   SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH                              */
+/*   Description:  DXB WTL Command Queue Almost Full Threshold          */
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00
+
+/*   SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL                               */
+/*   Description:  FSB WTL Command Queue Almost Empty Level             */
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000
+
+/*   SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH                              */
+/*   Description:  FSB WTL Command Queue Almost Full Threshold          */
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_ERROR_MASK"                      */
+/*                            PI Error Mask                             */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_MASK                         0x0000000120050a80
+#define SH_PI_ERROR_MASK_MASK                    0x00000007ffffffff
+#define SH_PI_ERROR_MASK_INIT                    0x00000007ffffffff
+
+/*   SH_PI_ERROR_MASK_FSB_PROTO_ERR                                     */
+/*   Description:  Mask detection of internal protocol table misses     */
+#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT      0
+#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK      0x0000000000000001
+
+/*   SH_PI_ERROR_MASK_GFX_RP_ERR                                        */
+/*   Description:  Mask graphic reply error message error detection     */
+#define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT         1
+#define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK         0x0000000000000002
+
+/*   SH_PI_ERROR_MASK_XB_PROTO_ERR                                      */
+/*   Description:  Mask detection of external protocol table misses     */
+#define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT       2
+#define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK       0x0000000000000004
+
+/*   SH_PI_ERROR_MASK_MEM_RP_ERR                                        */
+/*   Description:  Mask memory reply error detection                    */
+#define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT         3
+#define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK         0x0000000000000008
+
+/*   SH_PI_ERROR_MASK_PIO_RP_ERR                                        */
+/*   Description:  Mask PIO reply error detection                       */
+#define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT         4
+#define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK         0x0000000000000010
+
+/*   SH_PI_ERROR_MASK_MEM_TO_ERR                                        */
+/*   Description:  Mask CRB time-out errors                             */
+#define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT         5
+#define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK         0x0000000000000020
+
+/*   SH_PI_ERROR_MASK_PIO_TO_ERR                                        */
+/*   Description:  Mask PIO time-out errors                             */
+#define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT         6
+#define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK         0x0000000000000040
+
+/*   SH_PI_ERROR_MASK_FSB_SHUB_UCE                                      */
+/*   Description:  Mask un-correctable ECC error detection              */
+#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT       7
+#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK       0x0000000000000080
+
+/*   SH_PI_ERROR_MASK_FSB_SHUB_CE                                       */
+/*   Description:  Mask correctable ECC error detection                 */
+#define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT        8
+#define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK        0x0000000000000100
+
+/*   SH_PI_ERROR_MASK_MSG_COLOR_ERR                                     */
+/*   Description:  Mask message color error detection                   */
+#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT      9
+#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK      0x0000000000000200
+
+/*   SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW                                     */
+/*   Description:  Mask MD Request input buffer over flow error         */
+#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT      10
+#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK      0x0000000000000400
+
+/*   SH_PI_ERROR_MASK_MD_RP_Q_OFLOW                                     */
+/*   Description:  Mask MD Reply input buffer over flow error           */
+#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT      11
+#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK      0x0000000000000800
+
+/*   SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW                                     */
+/*   Description:  Mask XN Request input buffer over flow error         */
+#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT      12
+#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK      0x0000000000001000
+
+/*   SH_PI_ERROR_MASK_XN_RP_Q_OFLOW                                     */
+/*   Description:  Mask XN Reply input buffer over flow error           */
+#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT      13
+#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK      0x0000000000002000
+
+/*   SH_PI_ERROR_MASK_NACK_OFLOW                                        */
+/*   Description:  Mask NACK over flow error                            */
+#define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT         14
+#define SH_PI_ERROR_MASK_NACK_OFLOW_MASK         0x0000000000004000
+
+/*   SH_PI_ERROR_MASK_GFX_INT_0                                         */
+/*   Description:  Mask GFX transfer interrupt for CPU 0                */
+#define SH_PI_ERROR_MASK_GFX_INT_0_SHFT          15
+#define SH_PI_ERROR_MASK_GFX_INT_0_MASK          0x0000000000008000
+
+/*   SH_PI_ERROR_MASK_GFX_INT_1                                         */
+/*   Description:  Mask GFX transfer interrupt for CPU 1                */
+#define SH_PI_ERROR_MASK_GFX_INT_1_SHFT          16
+#define SH_PI_ERROR_MASK_GFX_INT_1_MASK          0x0000000000010000
+
+/*   SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW                                   */
+/*   Description:  Mask MD Request Credit Overflow Error                */
+#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT    17
+#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK    0x0000000000020000
+
+/*   SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW                                   */
+/*   Description:  Mask MD Reply Credit Overflow Error                  */
+#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT    18
+#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK    0x0000000000040000
+
+/*   SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW                                   */
+/*   Description:  Mask XN Request Credit Overflow Error                */
+#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT    19
+#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK    0x0000000000080000
+
+/*   SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW                                   */
+/*   Description:  Mask XN Reply Credit Overflow Error                  */
+#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT    20
+#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK    0x0000000000100000
+
+/*   SH_PI_ERROR_MASK_HUNG_BUS                                          */
+/*   Description:  Mask FSB hung error                                  */
+#define SH_PI_ERROR_MASK_HUNG_BUS_SHFT           21
+#define SH_PI_ERROR_MASK_HUNG_BUS_MASK           0x0000000000200000
+
+/*   SH_PI_ERROR_MASK_RSP_PARITY                                        */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_MASK_RSP_PARITY_SHFT         22
+#define SH_PI_ERROR_MASK_RSP_PARITY_MASK         0x0000000000400000
+
+/*   SH_PI_ERROR_MASK_IOQ_OVERRUN                                       */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT        23
+#define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK        0x0000000000800000
+
+/*   SH_PI_ERROR_MASK_REQ_FORMAT                                        */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT         24
+#define SH_PI_ERROR_MASK_REQ_FORMAT_MASK         0x0000000001000000
+
+/*   SH_PI_ERROR_MASK_ADDR_ACCESS                                       */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT        25
+#define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK        0x0000000002000000
+
+/*   SH_PI_ERROR_MASK_REQ_PARITY                                        */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_MASK_REQ_PARITY_SHFT         26
+#define SH_PI_ERROR_MASK_REQ_PARITY_MASK         0x0000000004000000
+
+/*   SH_PI_ERROR_MASK_ADDR_PARITY                                       */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT        27
+#define SH_PI_ERROR_MASK_ADDR_PARITY_MASK        0x0000000008000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_DQE                                      */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT       28
+#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK       0x0000000010000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_UCE                                      */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT       29
+#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK       0x0000000020000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_CE                                       */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT        30
+#define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK        0x0000000040000000
+
+/*   SH_PI_ERROR_MASK_LIVELOCK                                          */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_MASK_LIVELOCK_SHFT           31
+#define SH_PI_ERROR_MASK_LIVELOCK_MASK           0x0000000080000000
+
+/*   SH_PI_ERROR_MASK_BAD_SNOOP                                         */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT          32
+#define SH_PI_ERROR_MASK_BAD_SNOOP_MASK          0x0000000100000000
+
+/*   SH_PI_ERROR_MASK_FSB_TBL_MISS                                      */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT       33
+#define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK       0x0000000200000000
+
+/*   SH_PI_ERROR_MASK_MSG_LENGTH                                        */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT         34
+#define SH_PI_ERROR_MASK_MSG_LENGTH_MASK         0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_CONFIG"                 */
+/*                    PI Express Reply Configuration                    */
+/* ==================================================================== */
+
+#define SH_PI_EXPRESS_REPLY_CONFIG               0x0000000120050b00
+#define SH_PI_EXPRESS_REPLY_CONFIG_MASK          0x0000000000000007
+#define SH_PI_EXPRESS_REPLY_CONFIG_INIT          0x0000000000000001
+
+/*   SH_PI_EXPRESS_REPLY_CONFIG_MODE                                    */
+/*   Description:  Express Reply Mode                                   */
+#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT     0
+#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK     0x0000000000000007
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_VALUE"                  */
+/*                          FSB Compare Value                           */
+/* ==================================================================== */
+
+#define SH_PI_FSB_COMPARE_VALUE                  0x0000000120050c00
+#define SH_PI_FSB_COMPARE_VALUE_MASK             0xffffffffffffffff
+#define SH_PI_FSB_COMPARE_VALUE_INIT             0x0000000000000000
+
+/*   SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE                              */
+/*   Description:  Compare value                                        */
+#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0
+#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_MASK"                   */
+/*                           FSB Compare Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_FSB_COMPARE_MASK                   0x0000000120050b80
+#define SH_PI_FSB_COMPARE_MASK_MASK              0xffffffffffffffff
+#define SH_PI_FSB_COMPARE_MASK_INIT              0x0000000000000000
+
+/*   SH_PI_FSB_COMPARE_MASK_MASK_VALUE                                  */
+/*   Description:  Mask value                                           */
+#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT   0
+#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_FSB_ERROR_INJECTION"                 */
+/*                     Inject an Error onto the FSB                     */
+/* ==================================================================== */
+
+#define SH_PI_FSB_ERROR_INJECTION                0x0000000120050c80
+#define SH_PI_FSB_ERROR_INJECTION_MASK           0x000000070fff03ff
+#define SH_PI_FSB_ERROR_INJECTION_INIT           0x0000000000000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB                             */
+/*   Description:  Inject a RP# Parity Error onto the FSB               */
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB                            */
+/*   Description:  Inject an AP[0]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB                            */
+/*   Description:  Inject an AP[1]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004
+
+/*   SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB                            */
+/*   Description:  Inject a RSP# Parity Error onto the FSB              */
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB                            */
+/*   Description:  Inject a Correctable Error in Doubleword 0 onto the  */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB                           */
+/*   Description:  Inject an Uncorrectable Error in Doubleword 0 onto   */
+/*  the FSB                                                             */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB                            */
+/*   Description:  Inject a Correctable Error in Doubleword 1 onto the  */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB                           */
+/*   Description:  Inject an Uncorrectable Error in Doubleword 1 onto   */
+/*  the FSB                                                             */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080
+
+/*   SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB                            */
+/*   Description:  Inject an IP[0]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8
+#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100
+
+/*   SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB                            */
+/*   Description:  Inject an IP[1]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9
+#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200
+
+/*   SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB                           */
+/*   Description:  Inject a RP# Parity Error When Sampling the FSB      */
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB                          */
+/*   Description:  Inject an AP[0]# Parity Error When Sampling the FSB  */
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB                          */
+/*   Description:  Inject an AP[1]# Parity Error When Sampling the FSB  */
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000
+
+/*   SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB                          */
+/*   Description:  Inject a RSP# Parity Error When Sampling the FSB     */
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24
+#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25
+#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26
+#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27
+#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN                              */
+/*   Description:  Inject an ioq overrun Error on the FSB               */
+#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32
+#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_LIVELOCK                                 */
+/*   Description:  Inject a livelock Error on the FSB                   */
+#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT  33
+#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK  0x0000000200000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_BUS_HANG                                 */
+/*   Description:  Inject an bus hang on the FSB                        */
+#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT  34
+#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK  0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_CONFIG"                */
+/*             MD-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REPLY_VC_CONFIG              0x0000000120050d00
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK         0xc000000000003fff
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT         0x000000000000088c
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH                              */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH                             */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS                            */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT                           */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS                  */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_CONFIG"               */
+/*            MD-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG            0x0000000120050d80
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK       0xc000000000003fff
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT       0x000000000000088c
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH                            */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH                           */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS                          */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT                         */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS                */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_QUEUE_ERROR_INJECTION"                */
+/*                       PI Queue Error Injection                       */
+/* ==================================================================== */
+
+#define SH_PI_QUEUE_ERROR_INJECTION              0x0000000120050e00
+#define SH_PI_QUEUE_ERROR_INJECTION_MASK         0x00000000000000ff
+#define SH_PI_QUEUE_ERROR_INJECTION_INIT         0x0000000000000000
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q                              */
+#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0
+#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q                         */
+#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1
+#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q                         */
+#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2
+#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR                           */
+#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3
+#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR                               */
+#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4
+#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q                             */
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q                              */
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR                           */
+#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7
+#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                 Register "SH_PI_TEST_POINT_COMPARE"                  */
+/*                        PI Test Point Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_COMPARE                 0x0000000120050e80
+#define SH_PI_TEST_POINT_COMPARE_MASK            0xffffffffffffffff
+#define SH_PI_TEST_POINT_COMPARE_INIT            0xffffffff00000000
+
+/*   SH_PI_TEST_POINT_COMPARE_COMPARE_MASK                              */
+/*   Description:  Mask to select test point data for trigger generati  */
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN                           */
+/*   Description:  Pattern of test point data to cause trigger          */
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_TEST_POINT_SELECT"                  */
+/*                         PI Test Point Select                         */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_SELECT                  0x0000000120050f00
+#define SH_PI_TEST_POINT_SELECT_MASK             0xf777777777777777
+#define SH_PI_TEST_POINT_SELECT_INIT             0x0000000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                        */
+/*   Description:  Nibble 0 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 0                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                        */
+/*   Description:  Nibble 1 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 1                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                        */
+/*   Description:  Nibble 2 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 2                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                        */
+/*   Description:  Nibble 3 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 3                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                        */
+/*   Description:  Nibble 4 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 4                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                        */
+/*   Description:  Nibble 5 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 5                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                        */
+/*   Description:  Nibble 6 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 6                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                        */
+/*   Description:  Nibble 7 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 7                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE                             */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_PI_TEST_POINT_TRIGGER_SELECT"              */
+/*                     PI Test Point Trigger Select                     */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_TRIGGER_SELECT          0x0000000120050f80
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK     0x7777777777777777
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT     0x0000000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL               */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL                */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL               */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL                */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL               */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL                */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL               */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL                */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL               */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL                */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL               */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL                */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL               */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL                */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL               */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL                */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_CONFIG"                */
+/*             XN-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REPLY_VC_CONFIG              0x0000000120051000
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK         0xc000000000003fff
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT         0x000000000000068c
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH                              */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH                             */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS                            */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT                           */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS                  */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_CONFIG"               */
+/*            XN-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG            0x0000000120051080
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK       0xc000000000003fff
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT       0x000000000000068c
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH                            */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH                           */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS                          */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT                         */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS                */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_STATUS"                      */
+/*                 PI Adaptive Error Correction Status                  */
+/* ==================================================================== */
+
+#define SH_PI_AEC_STATUS                         0x0000000120060000
+#define SH_PI_AEC_STATUS_MASK                    0x0000000000000007
+#define SH_PI_AEC_STATUS_INIT                    0x0000000000000000
+
+/*   SH_PI_AEC_STATUS_STATE                                             */
+/*   Description:  AEC State                                            */
+#define SH_PI_AEC_STATUS_STATE_SHFT              0
+#define SH_PI_AEC_STATUS_STATE_MASK              0x0000000000000007
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_FIRST_ERROR"                   */
+/*                          PI AFI First Error                          */
+/* ==================================================================== */
+
+#define SH_PI_AFI_FIRST_ERROR                    0x0000000120060080
+#define SH_PI_AFI_FIRST_ERROR_MASK               0x00000007ffe00180
+#define SH_PI_AFI_FIRST_ERROR_INIT               0x0000000000000000
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE                                 */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT  7
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK  0x0000000000000080
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE                                  */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT   8
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK   0x0000000000000100
+
+/*   SH_PI_AFI_FIRST_ERROR_HUNG_BUS                                     */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT      21
+#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK      0x0000000000200000
+
+/*   SH_PI_AFI_FIRST_ERROR_RSP_PARITY                                   */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT    22
+#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK    0x0000000000400000
+
+/*   SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN                                  */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT   23
+#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK   0x0000000000800000
+
+/*   SH_PI_AFI_FIRST_ERROR_REQ_FORMAT                                   */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT    24
+#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK    0x0000000001000000
+
+/*   SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS                                  */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT   25
+#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK   0x0000000002000000
+
+/*   SH_PI_AFI_FIRST_ERROR_REQ_PARITY                                   */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT    26
+#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK    0x0000000004000000
+
+/*   SH_PI_AFI_FIRST_ERROR_ADDR_PARITY                                  */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT   27
+#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK   0x0000000008000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE                                 */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT  28
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK  0x0000000010000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE                                 */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT  29
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK  0x0000000020000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE                                  */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT   30
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK   0x0000000040000000
+
+/*   SH_PI_AFI_FIRST_ERROR_LIVELOCK                                     */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT      31
+#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK      0x0000000080000000
+
+/*   SH_PI_AFI_FIRST_ERROR_BAD_SNOOP                                    */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT     32
+#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK     0x0000000100000000
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS                                 */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT  33
+#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK  0x0000000200000000
+
+/*   SH_PI_AFI_FIRST_ERROR_MSG_LEN                                      */
+/*   Description:  Runt or Obese message received from SIC              */
+#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT       34
+#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK       0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_CAM_ADDRESS_READ_DATA"                */
+/*                    CRB CAM MMR Address Read Data                     */
+/* ==================================================================== */
+
+#define SH_PI_CAM_ADDRESS_READ_DATA              0x0000000120060100
+#define SH_PI_CAM_ADDRESS_READ_DATA_MASK         0x8000ffffffffffff
+#define SH_PI_CAM_ADDRESS_READ_DATA_INIT         0x0000000000000000
+
+/*   SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR                               */
+/*   Description:  CRB CAM Address Read Data.                           */
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff
+
+/*   SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL                           */
+/*   Description:  CRB CAM Address Read Data Valid.                     */
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_LPRA_READ_DATA"                  */
+/*                      CRB CAM MMR LPRA Read Data                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_LPRA_READ_DATA                 0x0000000120060180
+#define SH_PI_CAM_LPRA_READ_DATA_MASK            0xffffffffffffffff
+#define SH_PI_CAM_LPRA_READ_DATA_INIT            0x0000000000000000
+
+/*   SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA                                  */
+/*   Description:  CRB CAM LPRA read data.                              */
+#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT   0
+#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_STATE_READ_DATA"                 */
+/*                     CRB CAM MMR State Read Data                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_STATE_READ_DATA                0x0000000120060200
+#define SH_PI_CAM_STATE_READ_DATA_MASK           0x8003ffff0000003f
+#define SH_PI_CAM_STATE_READ_DATA_INIT           0x0000000000000000
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_STATE                                */
+/*   Description:  CRB CAM State read data.                             */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_TO                                   */
+/*   Description:  CRB CAM Time-out Status.                             */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT    4
+#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK    0x0000000000000010
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND                        */
+/*   Description:  CRB CAM State Read Pending.                          */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_LPRA                                 */
+/*   Description:  CRB LPRA Overflow Data.                              */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT  32
+#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK  0x0003ffff00000000
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL                          */
+/*   Description:  CRB CAM MMR read data is valid.                      */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63
+#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_1"                  */
+/*                      PI Corrected Error Detail                       */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_1                 0x0000000120060280
+#define SH_PI_CORRECTED_DETAIL_1_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_1_ADDRESS                                   */
+/*   Description:  Address of Message that logged Correctable Error     */
+#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT    0
+#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK    0x0000ffffffffffff
+
+/*   SH_PI_CORRECTED_DETAIL_1_SYNDROME                                  */
+/*   Description:  Syndrome for double word data with Correctable Erro  */
+#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT   48
+#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK   0x00ff000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_1_DEP                                       */
+/*   Description:  DEP code for Double word in error                    */
+#define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT        56
+#define SH_PI_CORRECTED_DETAIL_1_DEP_MASK        0xff00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_2"                  */
+/*                     PI Corrected Error Detail 2                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_2                 0x0000000120060300
+#define SH_PI_CORRECTED_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_2_DATA                                      */
+/*   Description:  Double word data in error                            */
+#define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT       0
+#define SH_PI_CORRECTED_DETAIL_2_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_3"                  */
+/*                     PI Corrected Error Detail 3                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_3                 0x0000000120060380
+#define SH_PI_CORRECTED_DETAIL_3_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_3_ADDRESS                                   */
+/*   Description:  Address of Message that logged Correctable Error     */
+#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT    0
+#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK    0x0000ffffffffffff
+
+/*   SH_PI_CORRECTED_DETAIL_3_SYNDROME                                  */
+/*   Description:  Syndrome for double word data with Correctable Erro  */
+#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT   48
+#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK   0x00ff000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_3_DEP                                       */
+/*   Description:  DEP code for Double word in error                    */
+#define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT        56
+#define SH_PI_CORRECTED_DETAIL_3_DEP_MASK        0xff00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_4"                  */
+/*                     PI Corrected Error Detail 4                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_4                 0x0000000120060400
+#define SH_PI_CORRECTED_DETAIL_4_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_4_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_4_DATA                                      */
+/*   Description:  Double word data in error                            */
+#define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT       0
+#define SH_PI_CORRECTED_DETAIL_4_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PI_CRBP_FIRST_ERROR"                   */
+/*                         PI CRBP First Error                          */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FIRST_ERROR                   0x0000000120060480
+#define SH_PI_CRBP_FIRST_ERROR_MASK              0x00000000001fffff
+#define SH_PI_CRBP_FIRST_ERROR_INIT              0x0000000000000000
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR                               */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0
+#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a GFX error reply             */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT   1
+#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK   0x0000000000000002
+
+/*   SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR                                */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2
+#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004
+
+/*   SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a memory error reply message  */
+#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT   3
+#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK   0x0000000000000008
+
+/*   SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a PIO error reply message     */
+#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT   4
+#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK   0x0000000000000010
+
+/*   SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR                                  */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT   5
+#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK   0x0000000000000020
+
+/*   SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR                                  */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT   6
+#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK   0x0000000000000040
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE                                */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE                                 */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT  8
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK  0x0000000000000100
+
+/*   SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR                               */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9
+#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW                               */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW                               */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW                               */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW                               */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000
+
+/*   SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW                                  */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT   14
+#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK   0x0000000000004000
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_INT_0                                   */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT    15
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK    0x0000000000008000
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_INT_1                                   */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT    16
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK    0x0000000000010000
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW                             */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW                             */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW                             */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW                             */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_1"                    */
+/*                          PI Error Detail 1                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_DETAIL_1                     0x0000000120060500
+#define SH_PI_ERROR_DETAIL_1_MASK                0xffffffffffffffff
+#define SH_PI_ERROR_DETAIL_1_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_DETAIL_1_STATUS                                        */
+/*   Description:  Error Detail 1                                       */
+#define SH_PI_ERROR_DETAIL_1_STATUS_SHFT         0
+#define SH_PI_ERROR_DETAIL_1_STATUS_MASK         0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_2"                    */
+/*                          PI Error Detail 2                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_DETAIL_2                     0x0000000120060580
+#define SH_PI_ERROR_DETAIL_2_MASK                0xffffffffffffffff
+#define SH_PI_ERROR_DETAIL_2_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_DETAIL_2_STATUS                                        */
+/*   Description:  Error Status                                         */
+#define SH_PI_ERROR_DETAIL_2_STATUS_SHFT         0
+#define SH_PI_ERROR_DETAIL_2_STATUS_MASK         0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_OVERFLOW"                    */
+/*                          PI Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_OVERFLOW                     0x0000000120060600
+#define SH_PI_ERROR_OVERFLOW_MASK                0x00000007ffffffff
+#define SH_PI_ERROR_OVERFLOW_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR                                 */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT  0
+#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK  0x0000000000000001
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another GFX reply error mess  */
+#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT     1
+#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK     0x0000000000000002
+
+/*   SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR                                  */
+/*   Description:  CRB's XB pipe detected another protocol table miss  */
+#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT   2
+#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK   0x0000000000000004
+
+/*   SH_PI_ERROR_OVERFLOW_MEM_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another memory reply error m  */
+#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT     3
+#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK     0x0000000000000008
+
+/*   SH_PI_ERROR_OVERFLOW_PIO_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another PIO reply error mess  */
+#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT     4
+#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK     0x0000000000000010
+
+/*   SH_PI_ERROR_OVERFLOW_MEM_TO_ERR                                    */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT     5
+#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK     0x0000000000000020
+
+/*   SH_PI_ERROR_OVERFLOW_PIO_TO_ERR                                    */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT     6
+#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK     0x0000000000000040
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT   7
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK   0x0000000000000080
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT    8
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK    0x0000000000000100
+
+/*   SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR                                 */
+/*   Description:  Message color was not correct                        */
+#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT  9
+#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK  0x0000000000000200
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW                                 */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT  10
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK  0x0000000000000400
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW                                 */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT  11
+#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK  0x0000000000000800
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW                                 */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT  12
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK  0x0000000000001000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW                                 */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT  13
+#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK  0x0000000000002000
+
+/*   SH_PI_ERROR_OVERFLOW_NACK_OFLOW                                    */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT     14
+#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK     0x0000000000004000
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_INT_0                                     */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT      15
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK      0x0000000000008000
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_INT_1                                     */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT      16
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK      0x0000000000010000
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW                               */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW                               */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW                               */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW                               */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/*   SH_PI_ERROR_OVERFLOW_HUNG_BUS                                      */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT       21
+#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK       0x0000000000200000
+
+/*   SH_PI_ERROR_OVERFLOW_RSP_PARITY                                    */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT     22
+#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK     0x0000000000400000
+
+/*   SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN                                   */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT    23
+#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK    0x0000000000800000
+
+/*   SH_PI_ERROR_OVERFLOW_REQ_FORMAT                                    */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT     24
+#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK     0x0000000001000000
+
+/*   SH_PI_ERROR_OVERFLOW_ADDR_ACCESS                                   */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT    25
+#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK    0x0000000002000000
+
+/*   SH_PI_ERROR_OVERFLOW_REQ_PARITY                                    */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT     26
+#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK     0x0000000004000000
+
+/*   SH_PI_ERROR_OVERFLOW_ADDR_PARITY                                   */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT    27
+#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK    0x0000000008000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE                                  */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT   28
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK   0x0000000010000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT   29
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK   0x0000000020000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT    30
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK    0x0000000040000000
+
+/*   SH_PI_ERROR_OVERFLOW_LIVELOCK                                      */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT       31
+#define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK       0x0000000080000000
+
+/*   SH_PI_ERROR_OVERFLOW_BAD_SNOOP                                     */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT      32
+#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK      0x0000000100000000
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS                                  */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT   33
+#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK   0x0000000200000000
+
+/*   SH_PI_ERROR_OVERFLOW_MSG_LENGTH                                    */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT     34
+#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK     0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_ERROR_OVERFLOW_ALIAS"                 */
+/*                       PI Error Overflow Alias                        */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_OVERFLOW_ALIAS               0x0000000120060608
+
+/* ==================================================================== */
+/*                    Register "SH_PI_ERROR_SUMMARY"                    */
+/*                           PI Error Summary                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_SUMMARY                      0x0000000120060680
+#define SH_PI_ERROR_SUMMARY_MASK                 0x00000007ffffffff
+#define SH_PI_ERROR_SUMMARY_INIT                 0x0000000000000000
+
+/*   SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR                                  */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT   0
+#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK   0x0000000000000001
+
+/*   SH_PI_ERROR_SUMMARY_GFX_RP_ERR                                     */
+/*   Description:  Graphic reply error message received                 */
+#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT      1
+#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK      0x0000000000000002
+
+/*   SH_PI_ERROR_SUMMARY_XB_PROTO_ERR                                   */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT    2
+#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK    0x0000000000000004
+
+/*   SH_PI_ERROR_SUMMARY_MEM_RP_ERR                                     */
+/*   Description:  Memory reply error message received                  */
+#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT      3
+#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK      0x0000000000000008
+
+/*   SH_PI_ERROR_SUMMARY_PIO_RP_ERR                                     */
+/*   Description:  PIO error reply message received                     */
+#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT      4
+#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK      0x0000000000000010
+
+/*   SH_PI_ERROR_SUMMARY_MEM_TO_ERR                                     */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT      5
+#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK      0x0000000000000020
+
+/*   SH_PI_ERROR_SUMMARY_PIO_TO_ERR                                     */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT      6
+#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK      0x0000000000000040
+
+/*   SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE                                   */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT    7
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK    0x0000000000000080
+
+/*   SH_PI_ERROR_SUMMARY_FSB_SHUB_CE                                    */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT     8
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK     0x0000000000000100
+
+/*   SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR                                  */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT   9
+#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK   0x0000000000000200
+
+/*   SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW                                  */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT   10
+#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK   0x0000000000000400
+
+/*   SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW                                  */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT   11
+#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK   0x0000000000000800
+
+/*   SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW                                  */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT   12
+#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK   0x0000000000001000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW                                  */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT   13
+#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK   0x0000000000002000
+
+/*   SH_PI_ERROR_SUMMARY_NACK_OFLOW                                     */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT      14
+#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK      0x0000000000004000
+
+/*   SH_PI_ERROR_SUMMARY_GFX_INT_0                                      */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT       15
+#define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK       0x0000000000008000
+
+/*   SH_PI_ERROR_SUMMARY_GFX_INT_1                                      */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT       16
+#define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK       0x0000000000010000
+
+/*   SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW                                */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW                                */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW                                */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW                                */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/*   SH_PI_ERROR_SUMMARY_HUNG_BUS                                       */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT        21
+#define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK        0x0000000000200000
+
+/*   SH_PI_ERROR_SUMMARY_RSP_PARITY                                     */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT      22
+#define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK      0x0000000000400000
+
+/*   SH_PI_ERROR_SUMMARY_IOQ_OVERRUN                                    */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT     23
+#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK     0x0000000000800000
+
+/*   SH_PI_ERROR_SUMMARY_REQ_FORMAT                                     */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT      24
+#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK      0x0000000001000000
+
+/*   SH_PI_ERROR_SUMMARY_ADDR_ACCESS                                    */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT     25
+#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK     0x0000000002000000
+
+/*   SH_PI_ERROR_SUMMARY_REQ_PARITY                                     */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT      26
+#define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK      0x0000000004000000
+
+/*   SH_PI_ERROR_SUMMARY_ADDR_PARITY                                    */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT     27
+#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK     0x0000000008000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE                                   */
+/*   Description:  SHUB_FSB_DQE error                                   */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT    28
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK    0x0000000010000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE                                   */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT    29
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK    0x0000000020000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_CE                                    */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT     30
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK     0x0000000040000000
+
+/*   SH_PI_ERROR_SUMMARY_LIVELOCK                                       */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT        31
+#define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK        0x0000000080000000
+
+/*   SH_PI_ERROR_SUMMARY_BAD_SNOOP                                      */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT       32
+#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK       0x0000000100000000
+
+/*   SH_PI_ERROR_SUMMARY_FSB_TBL_MISS                                   */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT    33
+#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK    0x0000000200000000
+
+/*   SH_PI_ERROR_SUMMARY_MSG_LENGTH                                     */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT      34
+#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK      0x0000000400000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_ERROR_SUMMARY_ALIAS"                 */
+/*                        PI Error Summary Alias                        */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_SUMMARY_ALIAS                0x0000000120060688
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_STATUS"                 */
+/*                       PI Express Reply Status                        */
+/* ==================================================================== */
+
+#define SH_PI_EXPRESS_REPLY_STATUS               0x0000000120060700
+#define SH_PI_EXPRESS_REPLY_STATUS_MASK          0x0000000000000007
+#define SH_PI_EXPRESS_REPLY_STATUS_INIT          0x0000000000000000
+
+/*   SH_PI_EXPRESS_REPLY_STATUS_STATE                                   */
+/*   Description:  Express Reply State                                  */
+#define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT    0
+#define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK    0x0000000000000007
+
+/* ==================================================================== */
+/*                     Register "SH_PI_FIRST_ERROR"                     */
+/*                            PI First Error                            */
+/* ==================================================================== */
+
+#define SH_PI_FIRST_ERROR                        0x0000000120060780
+#define SH_PI_FIRST_ERROR_MASK                   0x00000007ffffffff
+#define SH_PI_FIRST_ERROR_INIT                   0x0000000000000000
+
+/*   SH_PI_FIRST_ERROR_FSB_PROTO_ERR                                    */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT     0
+#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK     0x0000000000000001
+
+/*   SH_PI_FIRST_ERROR_GFX_RP_ERR                                       */
+/*   Description:  Graphics error reply message received                */
+#define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT        1
+#define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK        0x0000000000000002
+
+/*   SH_PI_FIRST_ERROR_XB_PROTO_ERR                                     */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT      2
+#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK      0x0000000000000004
+
+/*   SH_PI_FIRST_ERROR_MEM_RP_ERR                                       */
+/*   Description:  Memory reply error message received                  */
+#define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT        3
+#define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK        0x0000000000000008
+
+/*   SH_PI_FIRST_ERROR_PIO_RP_ERR                                       */
+/*   Description:  PIO reply error message received                     */
+#define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT        4
+#define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK        0x0000000000000010
+
+/*   SH_PI_FIRST_ERROR_MEM_TO_ERR                                       */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT        5
+#define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK        0x0000000000000020
+
+/*   SH_PI_FIRST_ERROR_PIO_TO_ERR                                       */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT        6
+#define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK        0x0000000000000040
+
+/*   SH_PI_FIRST_ERROR_FSB_SHUB_UCE                                     */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT      7
+#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK      0x0000000000000080
+
+/*   SH_PI_FIRST_ERROR_FSB_SHUB_CE                                      */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT       8
+#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK       0x0000000000000100
+
+/*   SH_PI_FIRST_ERROR_MSG_COLOR_ERR                                    */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT     9
+#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK     0x0000000000000200
+
+/*   SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW                                    */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT     10
+#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK     0x0000000000000400
+
+/*   SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW                                    */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT     11
+#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK     0x0000000000000800
+
+/*   SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW                                    */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT     12
+#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK     0x0000000000001000
+
+/*   SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW                                    */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT     13
+#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK     0x0000000000002000
+
+/*   SH_PI_FIRST_ERROR_NACK_OFLOW                                       */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT        14
+#define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK        0x0000000000004000
+
+/*   SH_PI_FIRST_ERROR_GFX_INT_0                                        */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT         15
+#define SH_PI_FIRST_ERROR_GFX_INT_0_MASK         0x0000000000008000
+
+/*   SH_PI_FIRST_ERROR_GFX_INT_1                                        */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT         16
+#define SH_PI_FIRST_ERROR_GFX_INT_1_MASK         0x0000000000010000
+
+/*   SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW                                  */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT   17
+#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK   0x0000000000020000
+
+/*   SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW                                  */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT   18
+#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK   0x0000000000040000
+
+/*   SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW                                  */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT   19
+#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK   0x0000000000080000
+
+/*   SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW                                  */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT   20
+#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK   0x0000000000100000
+
+/*   SH_PI_FIRST_ERROR_HUNG_BUS                                         */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT          21
+#define SH_PI_FIRST_ERROR_HUNG_BUS_MASK          0x0000000000200000
+
+/*   SH_PI_FIRST_ERROR_RSP_PARITY                                       */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT        22
+#define SH_PI_FIRST_ERROR_RSP_PARITY_MASK        0x0000000000400000
+
+/*   SH_PI_FIRST_ERROR_IOQ_OVERRUN                                      */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT       23
+#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK       0x0000000000800000
+
+/*   SH_PI_FIRST_ERROR_REQ_FORMAT                                       */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT        24
+#define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK        0x0000000001000000
+
+/*   SH_PI_FIRST_ERROR_ADDR_ACCESS                                      */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT       25
+#define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK       0x0000000002000000
+
+/*   SH_PI_FIRST_ERROR_REQ_PARITY                                       */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT        26
+#define SH_PI_FIRST_ERROR_REQ_PARITY_MASK        0x0000000004000000
+
+/*   SH_PI_FIRST_ERROR_ADDR_PARITY                                      */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT       27
+#define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK       0x0000000008000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_DQE                                     */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT      28
+#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK      0x0000000010000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_UCE                                     */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT      29
+#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK      0x0000000020000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_CE                                      */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT       30
+#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK       0x0000000040000000
+
+/*   SH_PI_FIRST_ERROR_LIVELOCK                                         */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_FIRST_ERROR_LIVELOCK_SHFT          31
+#define SH_PI_FIRST_ERROR_LIVELOCK_MASK          0x0000000080000000
+
+/*   SH_PI_FIRST_ERROR_BAD_SNOOP                                        */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT         32
+#define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK         0x0000000100000000
+
+/*   SH_PI_FIRST_ERROR_FSB_TBL_MISS                                     */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT      33
+#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK      0x0000000200000000
+
+/*   SH_PI_FIRST_ERROR_MSG_LENGTH                                       */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT        34
+#define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK        0x0000000400000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FIRST_ERROR_ALIAS"                  */
+/*                         PI First Error Alias                         */
+/* ==================================================================== */
+
+#define SH_PI_FIRST_ERROR_ALIAS                  0x0000000120060788
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2MD_REPLY_VC_STATUS"                */
+/*                PI-to-MD Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_PI2MD_REPLY_VC_STATUS              0x0000000120060900
+#define SH_PI_PI2MD_REPLY_VC_STATUS_MASK         0x000000000000003f
+#define SH_PI_PI2MD_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT                        */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2MD_REQUEST_VC_STATUS"               */
+/*               PI-to-MD Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_PI2MD_REQUEST_VC_STATUS            0x0000000120060980
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK       0x000000000000003f
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT                      */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2XN_REPLY_VC_STATUS"                */
+/*                PI-to-XN Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_PI2XN_REPLY_VC_STATUS              0x0000000120060a00
+#define SH_PI_PI2XN_REPLY_VC_STATUS_MASK         0x000000000000003f
+#define SH_PI_PI2XN_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT                        */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2XN_REQUEST_VC_STATUS"               */
+/*               PI-to-XN Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_PI2XN_REQUEST_VC_STATUS            0x0000000120060a80
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK       0x000000000000003f
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT                      */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_1"                 */
+/*                    PI Uncorrected Error Detail 1                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_1               0x0000000120060b00
+#define SH_PI_UNCORRECTED_DETAIL_1_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_1_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_ADDRESS                                 */
+/*   Description:  Address of Message that logged Uncorrectable Error  */
+#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT  0
+#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK  0x0000ffffffffffff
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_SYNDROME                                */
+/*   Description:  Syndrome for double word data with Uncorrectable Er  */
+#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48
+#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_DEP                                     */
+/*   Description:  DEP for Double word in error                         */
+#define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT      56
+#define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK      0xff00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_2"                 */
+/*                    PI Uncorrected Error Detail 2                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_2               0x0000000120060b80
+#define SH_PI_UNCORRECTED_DETAIL_2_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_2_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_2_DATA                                    */
+/*   Description:  Double word data in error                            */
+#define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT     0
+#define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_3"                 */
+/*                    PI Uncorrected Error Detail 3                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_3               0x0000000120060c00
+#define SH_PI_UNCORRECTED_DETAIL_3_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_3_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_ADDRESS                                 */
+/*   Description:  Address of Message that logged Uncorrectable Error  */
+#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT  0
+#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK  0x0000ffffffffffff
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_SYNDROME                                */
+/*   Description:  Syndrome for double word data with Uncorrectable Er  */
+#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48
+#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_DEP                                     */
+/*   Description:  DCP for Double word in error                         */
+#define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT      56
+#define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK      0xff00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_4"                 */
+/*                    PI Uncorrected Error Detail 4                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_4               0x0000000120060c80
+#define SH_PI_UNCORRECTED_DETAIL_4_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_4_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_4_DATA                                    */
+/*   Description:  Double word data in error                            */
+#define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT     0
+#define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_STATUS"                */
+/*                MD-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REPLY_VC_STATUS              0x0000000120060800
+#define SH_PI_MD2PI_REPLY_VC_STATUS_MASK         0x0000000000000fff
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT                     */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT                     */
+/*   Description:  Status of data credits                               */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT                       */
+/*   Description:  Status of MD Reply Input Queue                       */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_STATUS"               */
+/*               MD-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REQUEST_VC_STATUS            0x0000000120060880
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK       0x0000000000000fff
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT                   */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT                   */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT                     */
+/*   Description:  Status of MD Request Input Queue                     */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_STATUS"                */
+/*                XN-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REPLY_VC_STATUS              0x0000000120060d00
+#define SH_PI_XN2PI_REPLY_VC_STATUS_MASK         0x0000000000000fff
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT                     */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT                     */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT                       */
+/*   Description:  Status of XN Reply Input Queue                       */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_STATUS"               */
+/*               XN-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REQUEST_VC_STATUS            0x0000000120060d80
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK       0x0000000000000fff
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT                   */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT                   */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT                     */
+/*   Description:  Status of XN Request Input Queue                     */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*                     Register "SH_XNPI_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNPI_SIC_FLOW                         0x0000000150030000
+#define SH_XNPI_SIC_FLOW_MASK                    0x9f1f1f1f1f1f9f9f
+#define SH_XNPI_SIC_FLOW_INIT                    0x0000080000080000
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD                                */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED                              */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD                                */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED                              */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST                                   */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT    16
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK    0x00000000001f0000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN                                    */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT     24
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK     0x000000001f000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP                                    */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT     32
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK     0x0000001f00000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST                                   */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT    40
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK    0x00001f0000000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN                                    */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT     48
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK     0x001f000000000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP                                    */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT     56
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK     0x1f00000000000000
+
+/*   SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT                                */
+#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
+#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_NI0_PORT_FLOW                 0x0000000150030010
+#define SH_XNPI_TO_NI0_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_NI0_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_NI1_PORT_FLOW                 0x0000000150030020
+#define SH_XNPI_TO_NI1_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_NI1_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_IILB_PORT_FLOW                0x0000000150030030
+#define SH_XNPI_TO_IILB_PORT_FLOW_MASK           0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_IILB_PORT_FLOW_INIT           0x0000000000000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO            0x0000000150030040
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO            0x0000000150030050
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO           0x0000000150030060
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK      0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT      0x00000c0c00000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN                       */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP                       */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN                       */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP                       */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST                      */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST                      */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNMD_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNMD_SIC_FLOW                         0x0000000150030100
+#define SH_XNMD_SIC_FLOW_MASK                    0x9f1f1f1f1f1f9f9f
+#define SH_XNMD_SIC_FLOW_INIT                    0x0000090000090000
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD                                */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED                              */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD                                */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED                              */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST                                   */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT    16
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK    0x00000000001f0000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN                                    */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT     24
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK     0x000000001f000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP                                    */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT     32
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK     0x0000001f00000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST                                   */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT    40
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK    0x00001f0000000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN                                    */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT     48
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK     0x001f000000000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP                                    */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT     56
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK     0x1f00000000000000
+
+/*   SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT                                */
+#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
+#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_NI0_PORT_FLOW                 0x0000000150030110
+#define SH_XNMD_TO_NI0_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_NI0_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_NI1_PORT_FLOW                 0x0000000150030120
+#define SH_XNMD_TO_NI1_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_NI1_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_IILB_PORT_FLOW                0x0000000150030130
+#define SH_XNMD_TO_IILB_PORT_FLOW_MASK           0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_IILB_PORT_FLOW_INIT           0x0000000000000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO            0x0000000150030140
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO            0x0000000150030150
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO           0x0000000150030160
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK      0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT      0x00000c0c00000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN                       */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP                       */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN                       */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP                       */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST                      */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST                      */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNII_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNII_INTRA_FLOW                       0x0000000150030200
+#define SH_XNII_INTRA_FLOW_MASK                  0x7f7f7f7f7f7fbfbf
+#define SH_XNII_INTRA_FLOW_INIT                  0x00003f00003f0000
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD                              */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                            */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD                              */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                            */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST                                 */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT  16
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK  0x00000000007f0000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN                                  */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT   24
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK   0x000000007f000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP                                  */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT   32
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK   0x0000007f00000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST                                 */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT  40
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK  0x00007f0000000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN                                  */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT   48
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK   0x007f000000000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP                                  */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT   56
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK   0x7f00000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNLB_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNLB_INTRA_FLOW                       0x0000000150030210
+#define SH_XNLB_INTRA_FLOW_MASK                  0xff7f7f7f7f7fbfbf
+#define SH_XNLB_INTRA_FLOW_INIT                  0x0000080000100000
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                              */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                            */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                              */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                            */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST                                 */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT  16
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK  0x00000000007f0000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN                                  */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT   24
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK   0x000000007f000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP                                  */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT   32
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK   0x0000007f00000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST                                 */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT  40
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK  0x00007f0000000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN                                  */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT   48
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK   0x007f000000000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP                                  */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT   56
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK   0x7f00000000000000
+
+/*   SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN                               */
+#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63
+#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT        0x0000000150030220
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT        0x0000000150030230
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT         0x0000000150030240
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK    0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT    0x0000000000000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                      */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                    */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                      */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                    */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                           */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                           */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                           */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                           */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT       0x0000000150030250
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK  0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT  0x0000000000000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                    */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                  */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                    */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                  */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                         */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                         */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                         */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                         */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT         0x0000000150030260
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK    0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT    0x0000000000000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                      */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                    */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                      */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                    */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                           */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                           */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                           */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                           */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT       0x0000000150030270
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT       0x0000000150030280
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT        0x0000000150030290
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK   0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT   0x000000000c00000c
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                         */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                          */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                          */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                         */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                          */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                          */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT"            */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT      0x00000001500302a0
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                       */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                        */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                        */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                       */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                        */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                        */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT        0x00000001500302b0
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK   0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT   0x000000000c00000c
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                         */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                          */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                          */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                         */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                          */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                          */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT          0x0000000150030300
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT          0x0000000150030310
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT        0x0000000150030320
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT         0x0000000150030330
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT         0x0000000150030340
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT       0x0000000150030350
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_0_INTRANI_FLOW                  0x0000000150030360
+#define SH_XNNI0_0_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_0_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD                         */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED                       */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_1_INTRANI_FLOW                  0x0000000150030370
+#define SH_XNNI0_1_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_1_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD                         */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED                       */
+/*   Description:  Force Credit on VC1 from debit cntr                  */
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_2_INTRANI_FLOW                  0x0000000150030380
+#define SH_XNNI0_2_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_2_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD                         */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED                       */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_3_INTRANI_FLOW                  0x0000000150030390
+#define SH_XNNI0_3_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_3_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD                         */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED                       */
+/*   Description:  Force Credit on VC3 from debit cntr                  */
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNNI0_VCSWITCH_FLOW                   0x00000001500303a0
+#define SH_XNNI0_VCSWITCH_FLOW_MASK              0x0000000701010101
+#define SH_XNNI0_VCSWITCH_FLOW_INIT              0x0000000000000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH                   */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
+#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
+
+/*   SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
+#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
+
+/*   SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
+#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH                          */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
+#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN                      */
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT                     */
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES                                */
+#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
+#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_TIMER_REG"                     */
+/* ==================================================================== */
+
+#define SH_XNNI0_TIMER_REG                       0x00000001500303b0
+#define SH_XNNI0_TIMER_REG_MASK                  0x0000000100ffffff
+#define SH_XNNI0_TIMER_REG_INIT                  0x0000000000ffffff
+
+/*   SH_XNNI0_TIMER_REG_TIMEOUT_REG                                     */
+/*   Description:  Master Timeout Counter                               */
+#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT      0
+#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK      0x0000000000ffffff
+
+/*   SH_XNNI0_TIMER_REG_LINKCLEANUP_REG                                 */
+/*   Description:  Link Clean Up                                        */
+#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT  32
+#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK  0x0000000100000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_FIFO02_FLOW                     0x00000001500303c0
+#define SH_XNNI0_FIFO02_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI0_FIFO02_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT  8
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT  16
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT  32
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT  40
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_FIFO13_FLOW                     0x00000001500303d0
+#define SH_XNNI0_FIFO13_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI0_FIFO13_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT  8
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT  16
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT  32
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT  40
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI0_NI_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNNI0_NI_FLOW                         0x00000001500303e0
+#define SH_XNNI0_NI_FLOW_MASK                    0xff0fff0fff0fff0f
+#define SH_XNNI0_NI_FLOW_INIT                    0x0000000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC0_LIMIT                                         */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT          0
+#define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK          0x000000000000000f
+
+/*   SH_XNNI0_NI_FLOW_VC0_DYN                                           */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT            8
+#define SH_XNNI0_NI_FLOW_VC0_DYN_MASK            0x0000000000000f00
+
+/*   SH_XNNI0_NI_FLOW_VC0_CAP                                           */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT            12
+#define SH_XNNI0_NI_FLOW_VC0_CAP_MASK            0x000000000000f000
+
+/*   SH_XNNI0_NI_FLOW_VC1_LIMIT                                         */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT          16
+#define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK          0x00000000000f0000
+
+/*   SH_XNNI0_NI_FLOW_VC1_DYN                                           */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT            24
+#define SH_XNNI0_NI_FLOW_VC1_DYN_MASK            0x000000000f000000
+
+/*   SH_XNNI0_NI_FLOW_VC1_CAP                                           */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT            28
+#define SH_XNNI0_NI_FLOW_VC1_CAP_MASK            0x00000000f0000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_LIMIT                                         */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT          32
+#define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK          0x0000000f00000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_DYN                                           */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT            40
+#define SH_XNNI0_NI_FLOW_VC2_DYN_MASK            0x00000f0000000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_CAP                                           */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT            44
+#define SH_XNNI0_NI_FLOW_VC2_CAP_MASK            0x0000f00000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_LIMIT                                         */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT          48
+#define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK          0x000f000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_DYN                                           */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT            56
+#define SH_XNNI0_NI_FLOW_VC3_DYN_MASK            0x0f00000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_CAP                                           */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT            60
+#define SH_XNNI0_NI_FLOW_VC3_CAP_MASK            0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNNI0_DEAD_FLOW                       0x00000001500303f0
+#define SH_XNNI0_DEAD_FLOW_MASK                  0xff0fff0fff0fff0f
+#define SH_XNNI0_DEAD_FLOW_INIT                  0x0000000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_LIMIT                                       */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT        0
+#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK        0x000000000000000f
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_DYN                                         */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT          8
+#define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK          0x0000000000000f00
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_CAP                                         */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT          12
+#define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK          0x000000000000f000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_LIMIT                                       */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT        16
+#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK        0x00000000000f0000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_DYN                                         */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT          24
+#define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK          0x000000000f000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_CAP                                         */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT          28
+#define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK          0x00000000f0000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_LIMIT                                       */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT        32
+#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK        0x0000000f00000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_DYN                                         */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT          40
+#define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK          0x00000f0000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_CAP                                         */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT          44
+#define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK          0x0000f00000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_LIMIT                                       */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT        48
+#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK        0x000f000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_DYN                                         */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT          56
+#define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK          0x0f00000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_CAP                                         */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT          60
+#define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK          0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_INJECT_AGE                      0x0000000150030400
+#define SH_XNNI0_INJECT_AGE_MASK                 0x000000000000ffff
+#define SH_XNNI0_INJECT_AGE_INIT                 0x0000000000000000
+
+/*   SH_XNNI0_INJECT_AGE_REQUEST_INJECT                                 */
+/*   Description:  Value of AGE field for outgoing requests             */
+#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT  0
+#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK  0x00000000000000ff
+
+/*   SH_XNNI0_INJECT_AGE_REPLY_INJECT                                   */
+/*   Description:  Value of AGE field for outgoing replies              */
+#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT    8
+#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK    0x000000000000ff00
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT          0x0000000150030500
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT          0x0000000150030510
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT        0x0000000150030520
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT         0x0000000150030530
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT         0x0000000150030540
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT       0x0000000150030550
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_0_INTRANI_FLOW                  0x0000000150030560
+#define SH_XNNI1_0_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_0_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD                         */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED                       */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_1_INTRANI_FLOW                  0x0000000150030570
+#define SH_XNNI1_1_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_1_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD                         */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED                       */
+/*   Description:  Force Credit on VC1 from debit cntr                  */
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_2_INTRANI_FLOW                  0x0000000150030580
+#define SH_XNNI1_2_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_2_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD                         */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED                       */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_3_INTRANI_FLOW                  0x0000000150030590
+#define SH_XNNI1_3_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_3_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD                         */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED                       */
+/*   Description:  Force Credit on VC3 from debit cntr                  */
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNNI1_VCSWITCH_FLOW                   0x00000001500305a0
+#define SH_XNNI1_VCSWITCH_FLOW_MASK              0x0000000701010101
+#define SH_XNNI1_VCSWITCH_FLOW_INIT              0x0000000000000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH                   */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
+#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
+
+/*   SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
+#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
+
+/*   SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
+#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH                          */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
+#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN                      */
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT                     */
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES                                */
+#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
+#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_TIMER_REG"                     */
+/* ==================================================================== */
+
+#define SH_XNNI1_TIMER_REG                       0x00000001500305b0
+#define SH_XNNI1_TIMER_REG_MASK                  0x0000000100ffffff
+#define SH_XNNI1_TIMER_REG_INIT                  0x0000000000ffffff
+
+/*   SH_XNNI1_TIMER_REG_TIMEOUT_REG                                     */
+/*   Description:  Master Timeout Counter                               */
+#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT      0
+#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK      0x0000000000ffffff
+
+/*   SH_XNNI1_TIMER_REG_LINKCLEANUP_REG                                 */
+/*   Description:  Link Clean Up                                        */
+#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT  32
+#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK  0x0000000100000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_FIFO02_FLOW                     0x00000001500305c0
+#define SH_XNNI1_FIFO02_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI1_FIFO02_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT  8
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT  16
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT  32
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT  40
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_FIFO13_FLOW                     0x00000001500305d0
+#define SH_XNNI1_FIFO13_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI1_FIFO13_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT  8
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT  16
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT  32
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT  40
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI1_NI_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNNI1_NI_FLOW                         0x00000001500305e0
+#define SH_XNNI1_NI_FLOW_MASK                    0xff0fff0fff0fff0f
+#define SH_XNNI1_NI_FLOW_INIT                    0x0000000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC0_LIMIT                                         */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT          0
+#define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK          0x000000000000000f
+
+/*   SH_XNNI1_NI_FLOW_VC0_DYN                                           */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT            8
+#define SH_XNNI1_NI_FLOW_VC0_DYN_MASK            0x0000000000000f00
+
+/*   SH_XNNI1_NI_FLOW_VC0_CAP                                           */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT            12
+#define SH_XNNI1_NI_FLOW_VC0_CAP_MASK            0x000000000000f000
+
+/*   SH_XNNI1_NI_FLOW_VC1_LIMIT                                         */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT          16
+#define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK          0x00000000000f0000
+
+/*   SH_XNNI1_NI_FLOW_VC1_DYN                                           */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT            24
+#define SH_XNNI1_NI_FLOW_VC1_DYN_MASK            0x000000000f000000
+
+/*   SH_XNNI1_NI_FLOW_VC1_CAP                                           */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT            28
+#define SH_XNNI1_NI_FLOW_VC1_CAP_MASK            0x00000000f0000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_LIMIT                                         */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT          32
+#define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK          0x0000000f00000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_DYN                                           */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT            40
+#define SH_XNNI1_NI_FLOW_VC2_DYN_MASK            0x00000f0000000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_CAP                                           */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT            44
+#define SH_XNNI1_NI_FLOW_VC2_CAP_MASK            0x0000f00000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_LIMIT                                         */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT          48
+#define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK          0x000f000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_DYN                                           */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT            56
+#define SH_XNNI1_NI_FLOW_VC3_DYN_MASK            0x0f00000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_CAP                                           */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT            60
+#define SH_XNNI1_NI_FLOW_VC3_CAP_MASK            0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNNI1_DEAD_FLOW                       0x00000001500305f0
+#define SH_XNNI1_DEAD_FLOW_MASK                  0xff0fff0fff0fff0f
+#define SH_XNNI1_DEAD_FLOW_INIT                  0x0000000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_LIMIT                                       */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT        0
+#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK        0x000000000000000f
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_DYN                                         */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT          8
+#define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK          0x0000000000000f00
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_CAP                                         */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT          12
+#define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK          0x000000000000f000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_LIMIT                                       */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT        16
+#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK        0x00000000000f0000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_DYN                                         */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT          24
+#define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK          0x000000000f000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_CAP                                         */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT          28
+#define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK          0x00000000f0000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_LIMIT                                       */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT        32
+#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK        0x0000000f00000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_DYN                                         */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT          40
+#define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK          0x00000f0000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_CAP                                         */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT          44
+#define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK          0x0000f00000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_LIMIT                                       */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT        48
+#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK        0x000f000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_DYN                                         */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT          56
+#define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK          0x0f00000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_CAP                                         */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT          60
+#define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK          0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_INJECT_AGE                      0x0000000150030600
+#define SH_XNNI1_INJECT_AGE_MASK                 0x000000000000ffff
+#define SH_XNNI1_INJECT_AGE_INIT                 0x0000000000000000
+
+/*   SH_XNNI1_INJECT_AGE_REQUEST_INJECT                                 */
+/*   Description:  Value of AGE field for outgoing requests             */
+#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT  0
+#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK  0x00000000000000ff
+
+/*   SH_XNNI1_INJECT_AGE_REPLY_INJECT                                   */
+/*   Description:  Value of AGE field for outgoing replies              */
+#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT    8
+#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK    0x000000000000ff00
+
+/* ==================================================================== */
+/*                      Register "SH_XN_DEBUG_SEL"                      */
+/*                         XN Debug Port Select                         */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_SEL                          0x0000000150031000
+#define SH_XN_DEBUG_SEL_MASK                     0xf777777777777777
+#define SH_XN_DEBUG_SEL_INIT                     0x0000000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL                                    */
+/*   Description:  Nibble 0 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT     0
+#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK     0x0000000000000007
+
+/*   SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                                 */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT  4
+#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK  0x0000000000000070
+
+/*   SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL                                    */
+/*   Description:  Nibble 1 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT     8
+#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK     0x0000000000000700
+
+/*   SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                                 */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT  12
+#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK  0x0000000000007000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL                                    */
+/*   Description:  Nibble 2 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT     16
+#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK     0x0000000000070000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                                 */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT  20
+#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK  0x0000000000700000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL                                    */
+/*   Description:  Nibble 3 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT     24
+#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK     0x0000000007000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                                 */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT  28
+#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK  0x0000000070000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL                                    */
+/*   Description:  Nibble 4 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT     32
+#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK     0x0000000700000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                                 */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT  36
+#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK  0x0000007000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL                                    */
+/*   Description:  Nibble 5 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT     40
+#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK     0x0000070000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                                 */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT  44
+#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK  0x0000700000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL                                    */
+/*   Description:  Nibble 6 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT     48
+#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK     0x0007000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                                 */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT  52
+#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK  0x0070000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL                                    */
+/*   Description:  Nibble 7 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT     56
+#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK     0x0700000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                                 */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT  60
+#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK  0x7000000000000000
+
+/*   SH_XN_DEBUG_SEL_TRIGGER_ENABLE                                     */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT      63
+#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_DEBUG_TRIG_SEL"                    */
+/*                       XN Debug trigger Select                        */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_TRIG_SEL                     0x0000000150031020
+#define SH_XN_DEBUG_TRIG_SEL_MASK                0x7777777777777777
+#define SH_XN_DEBUG_TRIG_SEL_INIT                0x0000000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL                              */
+/*   Description:  Nibble 0 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL                              */
+/*   Description:  Nibble 1 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL                              */
+/*   Description:  Nibble 2 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL                              */
+/*   Description:  Nibble 3 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL                              */
+/*   Description:  Nibble 4 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL                              */
+/*   Description:  Nibble 5 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL                              */
+/*   Description:  Nibble 6 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL                              */
+/*   Description:  Nibble 7 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_TRIGGER_COMPARE"                   */
+/*                           XN Debug Compare                           */
+/* ==================================================================== */
+
+#define SH_XN_TRIGGER_COMPARE                    0x0000000150031040
+#define SH_XN_TRIGGER_COMPARE_MASK               0x00000000ffffffff
+#define SH_XN_TRIGGER_COMPARE_INIT               0x0000000000000000
+
+/*   SH_XN_TRIGGER_COMPARE_MASK                                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_XN_TRIGGER_COMPARE_MASK_SHFT          0
+#define SH_XN_TRIGGER_COMPARE_MASK_MASK          0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XN_TRIGGER_DATA"                     */
+/*                        XN Debug Compare Data                         */
+/* ==================================================================== */
+
+#define SH_XN_TRIGGER_DATA                       0x0000000150031050
+#define SH_XN_TRIGGER_DATA_MASK                  0x00000000ffffffff
+#define SH_XN_TRIGGER_DATA_INIT                  0x00000000ffffffff
+
+/*   SH_XN_TRIGGER_DATA_COMPARE_PATTERN                                 */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT  0
+#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_XN_IILB_DEBUG_SEL"                    */
+/*                      XN IILB Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_IILB_DEBUG_SEL                     0x0000000150031060
+#define SH_XN_IILB_DEBUG_SEL_MASK                0x7777777777777777
+#define SH_XN_IILB_DEBUG_SEL_INIT                0x0000000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL                             */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL                             */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL                             */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL                             */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL                             */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL                             */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL                             */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL                             */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_PI_DEBUG_SEL"                     */
+/*                       XN PI Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_XN_PI_DEBUG_SEL                       0x00000001500310a0
+#define SH_XN_PI_DEBUG_SEL_MASK                  0x7777777777777777
+#define SH_XN_PI_DEBUG_SEL_INIT                  0x0000000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL                               */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                              */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL                               */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                              */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL                               */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                              */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL                               */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                              */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL                               */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                              */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL                               */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                              */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL                               */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                              */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL                               */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                              */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_DEBUG_SEL"                     */
+/*                       XN MD Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_XN_MD_DEBUG_SEL                       0x0000000150031080
+#define SH_XN_MD_DEBUG_SEL_MASK                  0x7777777777777777
+#define SH_XN_MD_DEBUG_SEL_INIT                  0x0000000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL                               */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                              */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL                               */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                              */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL                               */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                              */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL                               */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                              */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL                               */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                              */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL                               */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                              */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL                               */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                              */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL                               */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                              */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI0_DEBUG_SEL"                    */
+/*                       XN NI0 Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_NI0_DEBUG_SEL                      0x00000001500310c0
+#define SH_XN_NI0_DEBUG_SEL_MASK                 0x7777777777777777
+#define SH_XN_NI0_DEBUG_SEL_INIT                 0x0000000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL                              */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                             */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL                              */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                             */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL                              */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                             */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL                              */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                             */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL                              */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                             */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL                              */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                             */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL                              */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                             */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL                              */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                             */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI1_DEBUG_SEL"                    */
+/*                       XN NI1 Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_NI1_DEBUG_SEL                      0x00000001500310e0
+#define SH_XN_NI1_DEBUG_SEL_MASK                 0x7777777777777777
+#define SH_XN_NI1_DEBUG_SEL_INIT                 0x0000000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL                              */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                             */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL                              */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                             */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL                              */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                             */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL                              */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                             */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL                              */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                             */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL                              */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                             */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL                              */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                             */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL                              */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                             */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA0"                */
+/*                 IILB compare LB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_EXP_DATA0              0x0000000150031100
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA1"                */
+/*                 IILB compare LB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_EXP_DATA1              0x0000000150031110
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE0"                 */
+/*                    IILB compare LB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_ENABLE0                0x0000000150031120
+#define SH_XN_IILB_LB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE1"                 */
+/*                    IILB compare LB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_ENABLE1                0x0000000150031130
+#define SH_XN_IILB_LB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA0"                */
+/*                 IILB compare II input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_EXP_DATA0              0x0000000150031140
+#define SH_XN_IILB_II_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA1"                */
+/*                 IILB compare II input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_EXP_DATA1              0x0000000150031150
+#define SH_XN_IILB_II_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE0"                 */
+/*                    IILB compare II input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_ENABLE0                0x0000000150031160
+#define SH_XN_IILB_II_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE1"                 */
+/*                    IILB compare II input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_ENABLE1                0x0000000150031170
+#define SH_XN_IILB_II_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA0"                */
+/*                 IILB compare MD input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_EXP_DATA0              0x0000000150031180
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA1"                */
+/*                 IILB compare MD input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_EXP_DATA1              0x0000000150031190
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE0"                 */
+/*                    IILB compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_ENABLE0                0x00000001500311a0
+#define SH_XN_IILB_MD_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE1"                 */
+/*                    IILB compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_ENABLE1                0x00000001500311b0
+#define SH_XN_IILB_MD_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA0"                */
+/*                 IILB compare PI input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_EXP_DATA0              0x00000001500311c0
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA1"                */
+/*                 IILB compare PI input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_EXP_DATA1              0x00000001500311d0
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE0"                 */
+/*                    IILB compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_ENABLE0                0x00000001500311e0
+#define SH_XN_IILB_PI_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE1"                 */
+/*                    IILB compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_ENABLE1                0x00000001500311f0
+#define SH_XN_IILB_PI_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA0"                */
+/*                IILB compare NI0 input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0             0x0000000150031200
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA1"                */
+/*                IILB compare NI0 input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1             0x0000000150031210
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE0"                 */
+/*                    IILB compare NI0 input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_ENABLE0               0x0000000150031220
+#define SH_XN_IILB_NI0_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE1"                 */
+/*                    IILB compare NI0 input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_ENABLE1               0x0000000150031230
+#define SH_XN_IILB_NI0_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA0"                */
+/*                IILB compare NI1 input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0             0x0000000150031240
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA1"                */
+/*                IILB compare NI1 input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1             0x0000000150031250
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE0"                 */
+/*                    IILB compare NI1 input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_ENABLE0               0x0000000150031260
+#define SH_XN_IILB_NI1_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE1"                 */
+/*                    IILB compare NI1 input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_ENABLE1               0x0000000150031270
+#define SH_XN_IILB_NI1_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA0"                */
+/*                 MD compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_EXP_DATA0              0x0000000150031500
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA1"                */
+/*                 MD compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_EXP_DATA1              0x0000000150031510
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE0"                 */
+/*                    MD compare IILB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_ENABLE0                0x0000000150031520
+#define SH_XN_MD_IILB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE1"                 */
+/*                    MD compare IILB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_ENABLE1                0x0000000150031530
+#define SH_XN_MD_IILB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA0"                 */
+/*                 MD compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_EXP_DATA0               0x0000000150031540
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA1"                 */
+/*                 MD compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_EXP_DATA1               0x0000000150031550
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE0"                  */
+/*                     MD compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_ENABLE0                 0x0000000150031560
+#define SH_XN_MD_NI0_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE1"                  */
+/*                     MD compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_ENABLE1                 0x0000000150031570
+#define SH_XN_MD_NI0_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA0"                 */
+/*                 MD compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_EXP_DATA0               0x0000000150031580
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA1"                 */
+/*                 MD compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_EXP_DATA1               0x0000000150031590
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE0"                  */
+/*                     MD compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_ENABLE0                 0x00000001500315a0
+#define SH_XN_MD_NI1_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE1"                  */
+/*                     MD compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_ENABLE1                 0x00000001500315b0
+#define SH_XN_MD_NI1_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR0"                 */
+/*                MD compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_EXP_HDR0                0x00000001500315c0
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK           0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT           0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_EXP_HDR0_DATA                                     */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT      0
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR1"                 */
+/*                MD compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_EXP_HDR1                0x00000001500315d0
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK           0x000003ffffffffff
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT           0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_EXP_HDR1_DATA                                     */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT      0
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK      0x000003ffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0"                */
+/*                    MD compare SIC header enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0             0x00000001500315e0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK        0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT        0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE                                */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1"                */
+/*                    MD compare SIC header enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1             0x00000001500315f0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK        0x000003ffffffffff
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT        0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE                                */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA0"                   */
+/*                         MD compare SIC data0                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA0                   0x0000000150031600
+#define SH_XN_MD_SIC_CMP_DATA0_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA0_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA0_DATA0                                       */
+/*   Description:  Data0                                                */
+#define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA1"                   */
+/*                         MD compare SIC data1                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA1                   0x0000000150031610
+#define SH_XN_MD_SIC_CMP_DATA1_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA1_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA1_DATA1                                       */
+/*   Description:  Data1                                                */
+#define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA2"                   */
+/*                         MD compare SIC data2                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA2                   0x0000000150031620
+#define SH_XN_MD_SIC_CMP_DATA2_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA2_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA2_DATA2                                       */
+/*   Description:  Data2                                                */
+#define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA3"                   */
+/*                         MD compare SIC data3                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA3                   0x0000000150031630
+#define SH_XN_MD_SIC_CMP_DATA3_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA3_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA3_DATA3                                       */
+/*   Description:  Data3                                                */
+#define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0"               */
+/*                     MD enable compare SIC data0                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0            0x0000000150031640
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0                         */
+/*   Description:  Data0                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1"               */
+/*                     MD enable compare SIC data1                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1            0x0000000150031650
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1                         */
+/*   Description:  Data1                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2"               */
+/*                     MD enable compare SIC data2                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2            0x0000000150031660
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2                         */
+/*   Description:  Data2                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3"               */
+/*                     MD enable compare SIC data3                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3            0x0000000150031670
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3                         */
+/*   Description:  Data3                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA0"                */
+/*                 PI compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_EXP_DATA0              0x0000000150031300
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA1"                */
+/*                 PI compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_EXP_DATA1              0x0000000150031310
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE0"                 */
+/*                    PI compare IILB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_ENABLE0                0x0000000150031320
+#define SH_XN_PI_IILB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE1"                 */
+/*                    PI compare IILB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_ENABLE1                0x0000000150031330
+#define SH_XN_PI_IILB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA0"                 */
+/*                 PI compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_EXP_DATA0               0x0000000150031340
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA1"                 */
+/*                 PI compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_EXP_DATA1               0x0000000150031350
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE0"                  */
+/*                     PI compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_ENABLE0                 0x0000000150031360
+#define SH_XN_PI_NI0_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE1"                  */
+/*                     PI compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_ENABLE1                 0x0000000150031370
+#define SH_XN_PI_NI0_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA0"                 */
+/*                 PI compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_EXP_DATA0               0x0000000150031380
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA1"                 */
+/*                 PI compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_EXP_DATA1               0x0000000150031390
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE0"                  */
+/*                     PI compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_ENABLE0                 0x00000001500313a0
+#define SH_XN_PI_NI1_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE1"                  */
+/*                     PI compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_ENABLE1                 0x00000001500313b0
+#define SH_XN_PI_NI1_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR0"                 */
+/*                PI compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_EXP_HDR0                0x00000001500313c0
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK           0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT           0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_EXP_HDR0_DATA                                     */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT      0
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR1"                 */
+/*                PI compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_EXP_HDR1                0x00000001500313d0
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK           0x000003ffffffffff
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT           0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_EXP_HDR1_DATA                                     */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT      0
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK      0x000003ffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0"                */
+/*                    PI compare SIC header enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0             0x00000001500313e0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK        0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT        0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE                                */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1"                */
+/*                    PI compare SIC header enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1             0x00000001500313f0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK        0x000003ffffffffff
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT        0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE                                */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA0"                   */
+/*                         PI compare SIC data0                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA0                   0x0000000150031400
+#define SH_XN_PI_SIC_CMP_DATA0_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA0_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA0_DATA0                                       */
+/*   Description:  Data0                                                */
+#define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA1"                   */
+/*                         PI compare SIC data1                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA1                   0x0000000150031410
+#define SH_XN_PI_SIC_CMP_DATA1_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA1_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA1_DATA1                                       */
+/*   Description:  Data1                                                */
+#define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA2"                   */
+/*                         PI compare SIC data2                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA2                   0x0000000150031420
+#define SH_XN_PI_SIC_CMP_DATA2_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA2_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA2_DATA2                                       */
+/*   Description:  Data2                                                */
+#define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA3"                   */
+/*                         PI compare SIC data3                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA3                   0x0000000150031430
+#define SH_XN_PI_SIC_CMP_DATA3_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA3_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA3_DATA3                                       */
+/*   Description:  Data3                                                */
+#define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0"               */
+/*                     PI enable compare SIC data0                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0            0x0000000150031440
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0                         */
+/*   Description:  Data0                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1"               */
+/*                     PI enable compare SIC data1                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1            0x0000000150031450
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1                         */
+/*   Description:  Data1                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2"               */
+/*                     PI enable compare SIC data2                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2            0x0000000150031460
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2                         */
+/*   Description:  Data2                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3"               */
+/*                     PI enable compare SIC data3                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3            0x0000000150031470
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3                         */
+/*   Description:  Data3                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA0"                */
+/*                NI0 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0             0x0000000150031700
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA1"                */
+/*                NI0 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1             0x0000000150031710
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE0"                 */
+/*                    NI0 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_ENABLE0               0x0000000150031720
+#define SH_XN_NI0_IILB_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE1"                 */
+/*                    NI0 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_ENABLE1               0x0000000150031730
+#define SH_XN_NI0_IILB_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_EXP_DATA0               0x0000000150031740
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_EXP_DATA1               0x0000000150031750
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE0"                  */
+/*                     NI0 compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_ENABLE0                 0x0000000150031760
+#define SH_XN_NI0_PI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE1"                  */
+/*                     NI0 compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_ENABLE1                 0x0000000150031770
+#define SH_XN_NI0_PI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA0"                 */
+/*                 NI0 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_EXP_DATA0               0x0000000150031780
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA1"                 */
+/*                 NI0 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_EXP_DATA1               0x0000000150031790
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE0"                  */
+/*                     NI0 compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_ENABLE0                 0x00000001500317a0
+#define SH_XN_NI0_MD_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE1"                  */
+/*                     NI0 compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_ENABLE1                 0x00000001500317b0
+#define SH_XN_NI0_MD_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_EXP_DATA0               0x00000001500317c0
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_EXP_DATA1               0x00000001500317d0
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE0"                  */
+/*                     NI0 compare NI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_ENABLE0                 0x00000001500317e0
+#define SH_XN_NI0_NI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE1"                  */
+/*                     NI0 compare NI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_ENABLE1                 0x00000001500317f0
+#define SH_XN_NI0_NI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA0"                */
+/*                 NI0 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0              0x0000000150031800
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA1"                */
+/*                 NI0 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1              0x0000000150031810
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE0"                 */
+/*                    NI0 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_ENABLE0                0x0000000150031820
+#define SH_XN_NI0_LLP_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE1"                 */
+/*                    NI0 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_ENABLE1                0x0000000150031830
+#define SH_XN_NI0_LLP_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA0"                */
+/*                NI1 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0             0x0000000150031900
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA1"                */
+/*                NI1 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1             0x0000000150031910
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE0"                 */
+/*                    NI1 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_ENABLE0               0x0000000150031920
+#define SH_XN_NI1_IILB_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE1"                 */
+/*                    NI1 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_ENABLE1               0x0000000150031930
+#define SH_XN_NI1_IILB_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_EXP_DATA0               0x0000000150031940
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_EXP_DATA1               0x0000000150031950
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE0"                  */
+/*                     NI1 compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_ENABLE0                 0x0000000150031960
+#define SH_XN_NI1_PI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE1"                  */
+/*                     NI1 compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_ENABLE1                 0x0000000150031970
+#define SH_XN_NI1_PI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA0"                 */
+/*                 NI1 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_EXP_DATA0               0x0000000150031980
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA1"                 */
+/*                 NI1 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_EXP_DATA1               0x0000000150031990
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE0"                  */
+/*                     NI1 compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_ENABLE0                 0x00000001500319a0
+#define SH_XN_NI1_MD_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE1"                  */
+/*                     NI1 compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_ENABLE1                 0x00000001500319b0
+#define SH_XN_NI1_MD_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_EXP_DATA0               0x00000001500319c0
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_EXP_DATA1               0x00000001500319d0
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE0"                  */
+/*                     NI1 compare NI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_ENABLE0                 0x00000001500319e0
+#define SH_XN_NI1_NI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE1"                  */
+/*                     NI1 compare NI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_ENABLE1                 0x00000001500319f0
+#define SH_XN_NI1_NI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA0"                */
+/*                 NI1 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0              0x0000000150031a00
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA1"                */
+/*                 NI1 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1              0x0000000150031a10
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE0"                 */
+/*                    NI1 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_ENABLE0                0x0000000150031a20
+#define SH_XN_NI1_LLP_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE1"                 */
+/*                    NI1 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_ENABLE1                0x0000000150031a30
+#define SH_XN_NI1_LLP_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC_INJ_REG                      0x0000000150032000
+#define SH_XNPI_ECC_INJ_REG_MASK                 0xf0fff0fff0fff0ff
+#define SH_XNPI_ECC_INJ_REG_INIT                 0x0000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE0                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT           0
+#define SH_XNPI_ECC_INJ_REG_BYTE0_MASK           0x00000000000000ff
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT0                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT     12
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK     0x0000000000001000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT0                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT      13
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK      0x0000000000002000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT  14
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK  0x0000000000004000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0                                  */
+/*   Description:  Replace Checkbyte Continuous                         */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT   15
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK   0x0000000000008000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE1                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT           16
+#define SH_XNPI_ECC_INJ_REG_BYTE1_MASK           0x0000000000ff0000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT1                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT     28
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK     0x0000000010000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT1                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT      29
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK      0x0000000020000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT  30
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK  0x0000000040000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT   31
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK   0x0000000080000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE2                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT           32
+#define SH_XNPI_ECC_INJ_REG_BYTE2_MASK           0x000000ff00000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT2                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT     44
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK     0x0000100000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT2                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT      45
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK      0x0000200000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2                                 */
+/*   Description:  Replace Checkbyte OneShot                            */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT  46
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK  0x0000400000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT   47
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK   0x0000800000000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE3                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT           48
+#define SH_XNPI_ECC_INJ_REG_BYTE3_MASK           0x00ff000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT3                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT     60
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK     0x1000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT3                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT      61
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK      0x2000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3                                 */
+/*   Description:  Replace Checkbyte One-Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT  62
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK  0x4000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT   63
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK   0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC0_INJ_MASK_REG                0x0000000150032008
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC0_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC1_INJ_MASK_REG                0x0000000150032010
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC1_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC2_INJ_MASK_REG                0x0000000150032018
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC2_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC3_INJ_MASK_REG                0x0000000150032020
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC3_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC_INJ_REG                      0x0000000150032030
+#define SH_XNMD_ECC_INJ_REG_MASK                 0xf0fff0fff0fff0ff
+#define SH_XNMD_ECC_INJ_REG_INIT                 0x0000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE0                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT           0
+#define SH_XNMD_ECC_INJ_REG_BYTE0_MASK           0x00000000000000ff
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT0                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT     12
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK     0x0000000000001000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT0                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT      13
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK      0x0000000000002000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT  14
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK  0x0000000000004000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0                                  */
+/*   Description:  Replace Checkbyte Continuous                         */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT   15
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK   0x0000000000008000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE1                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT           16
+#define SH_XNMD_ECC_INJ_REG_BYTE1_MASK           0x0000000000ff0000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT1                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT     28
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK     0x0000000010000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT1                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT      29
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK      0x0000000020000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT  30
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK  0x0000000040000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT   31
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK   0x0000000080000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE2                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT           32
+#define SH_XNMD_ECC_INJ_REG_BYTE2_MASK           0x000000ff00000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT2                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT     44
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK     0x0000100000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT2                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT      45
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK      0x0000200000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2                                 */
+/*   Description:  Replace Checkbyte OneShot                            */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT  46
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK  0x0000400000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT   47
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK   0x0000800000000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE3                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT           48
+#define SH_XNMD_ECC_INJ_REG_BYTE3_MASK           0x00ff000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT3                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT     60
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK     0x1000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT3                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT      61
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK      0x2000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3                                 */
+/*   Description:  Replace Checkbyte One-Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT  62
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK  0x4000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT   63
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK   0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC0_INJ_MASK_REG                0x0000000150032038
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC0_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC1_INJ_MASK_REG                0x0000000150032040
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC1_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC2_INJ_MASK_REG                0x0000000150032048
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC2_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC3_INJ_MASK_REG                0x0000000150032050
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC3_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ECC_ERR_REPORT"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC_ERR_REPORT                   0x0000000150032058
+#define SH_XNMD_ECC_ERR_REPORT_MASK              0x0001000100010001
+#define SH_XNMD_ECC_ERR_REPORT_INIT              0x0000000000000000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_1"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_1                   0x0000000150040500
+#define SH_NI0_ERROR_SUMMARY_1_MASK              0xffffffffffffffff
+#define SH_NI0_ERROR_SUMMARY_1_INIT              0xffffffffffffffff
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0                      */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2                      */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0                      */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2                      */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP                     */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP                     */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP                     */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP                     */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH                    */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH                    */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH                    */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH                    */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT                  */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT                  */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT                  */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT                  */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0                     */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2                     */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0                   */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2                   */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0                     */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2                     */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0                     */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1                     */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2                     */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3                     */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP                    */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP                    */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP                  */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP                  */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP                    */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP                    */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP                    */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP                    */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH                   */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH                   */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH                 */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH                 */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH                   */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH                   */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT                 */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT                 */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT               */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT               */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT                 */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT                 */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT                 */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT                 */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT                 */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT                 */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0                     */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2                     */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1                     */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3                     */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0                         */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1                         */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2                         */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3                         */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_SUMMARY_1_ALIAS"                */
+/*                     ni0 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_1_ALIAS             0x0000000150040508
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_2"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_2                   0x0000000150040510
+#define SH_NI0_ERROR_SUMMARY_2_MASK              0x7fffffff003fffff
+#define SH_NI0_ERROR_SUMMARY_2_INIT              0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI                                */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI                                */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD                                */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB                              */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0                            */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1                            */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2                            */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3                            */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH                             */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR                         */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_SUMMARY_2_ALIAS"                */
+/*                     ni0 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_2_ALIAS             0x0000000150040518
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_1"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_1                  0x0000000150040520
+#define SH_NI0_ERROR_OVERFLOW_1_MASK             0xffffffffffffffff
+#define SH_NI0_ERROR_OVERFLOW_1_INIT             0xffffffffffffffff
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0                     */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2                     */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0                     */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2                     */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0                    */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2                    */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0                  */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2                  */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0                    */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2                    */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0                    */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1                    */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2                    */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3                    */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0                    */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2                    */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1                    */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3                    */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0                        */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1                        */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2                        */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3                        */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS"               */
+/*                    ni0 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_1_ALIAS            0x0000000150040528
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_2"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_2                  0x0000000150040530
+#define SH_NI0_ERROR_OVERFLOW_2_MASK             0x7fffffff003fffff
+#define SH_NI0_ERROR_OVERFLOW_2_INIT             0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI                               */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI                               */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD                               */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB                             */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP                   */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP                   */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP                   */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP                   */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH                  */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH                  */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH                  */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH                  */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT                */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT                */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT                */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT                */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP                  */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP                  */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP                */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP                */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP                  */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP                  */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP                  */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP                  */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH                 */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH                 */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH               */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH               */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH                 */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH                 */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT               */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT               */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT             */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT             */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT               */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT               */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT               */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT               */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT               */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT               */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0                           */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1                           */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2                           */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3                           */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR                        */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS"               */
+/*                    ni0 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_2_ALIAS            0x0000000150040538
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_1"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_MASK_1                      0x0000000150040540
+#define SH_NI0_ERROR_MASK_1_MASK                 0xffffffffffffffff
+#define SH_NI0_ERROR_MASK_1_INIT                 0xffffffffffffffff
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0                         */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2                         */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0                         */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2                         */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP                        */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP                        */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP                        */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP                        */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH                       */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH                       */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH                       */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH                       */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT                     */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT                     */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT                     */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT                     */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0                        */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2                        */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0                      */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2                      */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0                        */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2                        */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0                        */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1                        */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2                        */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3                        */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP                       */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP                       */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP                     */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP                     */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP                       */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP                       */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP                       */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP                       */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH                      */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH                      */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH                    */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH                    */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH                      */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH                      */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT                    */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT                    */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                  */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                  */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT                    */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT                    */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT                    */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT                    */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT                    */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT                    */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0                        */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2                        */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1                        */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3                        */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0                            */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1                            */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2                            */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3                            */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_2"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_MASK_2                      0x0000000150040550
+#define SH_NI0_ERROR_MASK_2_MASK                 0x7fffffff003fffff
+#define SH_NI0_ERROR_MASK_2_INIT                 0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI                                   */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT    0
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK    0x0000000000000001
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI                                   */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT    1
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK    0x0000000000000002
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD                                   */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT    2
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK    0x0000000000000004
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB                                 */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT  3
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK  0x0000000000000008
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0                               */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1                               */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2                               */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3                               */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH                                */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT  61
+#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK  0x2000000000000000
+
+/*   SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR                            */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_1"                    */
+/*                        ni0  First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_FIRST_ERROR_1                     0x0000000150040560
+#define SH_NI0_FIRST_ERROR_1_MASK                0xffffffffffffffff
+#define SH_NI0_FIRST_ERROR_1_INIT                0xffffffffffffffff
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0                        */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2                        */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0                        */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2                        */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0                       */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2                       */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0                     */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2                     */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0                       */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2                       */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0                       */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1                       */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2                       */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3                       */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0                       */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2                       */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1                       */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3                       */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0                           */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1                           */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2                           */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3                           */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_2"                    */
+/*                         ni0 First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_FIRST_ERROR_2                     0x0000000150040570
+#define SH_NI0_FIRST_ERROR_2_MASK                0x7fffffff003fffff
+#define SH_NI0_FIRST_ERROR_2_INIT                0x7fffffff003fffff
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI                                  */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT   0
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK   0x0000000000000001
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI                                  */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT   1
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK   0x0000000000000002
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD                                  */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT   2
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK   0x0000000000000004
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB                                */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP                      */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP                      */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP                      */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP                      */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH                     */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH                     */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH                     */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH                     */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT                   */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT                   */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT                   */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT                   */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP                     */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP                     */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP                   */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP                   */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP                     */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP                     */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP                     */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP                     */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH                    */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH                    */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                  */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                  */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH                    */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH                    */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                  */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                  */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                  */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                  */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                  */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                  */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                  */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                  */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0                              */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1                              */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2                              */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3                              */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR                           */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_1"                   */
+/*                ni0 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_1                    0x0000000150040580
+#define SH_NI0_ERROR_DETAIL_1_MASK               0xffffffffffffffff
+#define SH_NI0_ERROR_DETAIL_1_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_1_HEADER                                       */
+/*   Description:  Header bits 63:0                                     */
+#define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT        0
+#define SH_NI0_ERROR_DETAIL_1_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_2"                   */
+/*               ni0 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_2                    0x0000000150040590
+#define SH_NI0_ERROR_DETAIL_2_MASK               0xffffffffffffffff
+#define SH_NI0_ERROR_DETAIL_2_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_2_HEADER                                       */
+/*   Description:  Header bits 127:64                                   */
+#define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT        0
+#define SH_NI0_ERROR_DETAIL_2_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_1"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_1                   0x0000000150040600
+#define SH_NI1_ERROR_SUMMARY_1_MASK              0xffffffffffffffff
+#define SH_NI1_ERROR_SUMMARY_1_INIT              0xffffffffffffffff
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0                      */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2                      */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0                      */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2                      */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP                     */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP                     */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP                     */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP                     */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH                    */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH                    */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH                    */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH                    */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT                  */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT                  */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT                  */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT                  */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0                     */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2                     */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0                   */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2                   */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0                     */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2                     */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0                     */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1                     */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2                     */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3                     */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP                    */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP                    */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP                  */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP                  */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP                    */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP                    */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP                    */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP                    */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH                   */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH                   */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH                 */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH                 */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH                   */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH                   */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT                 */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT                 */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT               */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT               */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT                 */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT                 */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT                 */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT                 */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT                 */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT                 */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0                     */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2                     */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1                     */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3                     */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0                         */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1                         */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2                         */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3                         */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_SUMMARY_1_ALIAS"                */
+/*                     ni1 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_1_ALIAS             0x0000000150040608
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_2"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_2                   0x0000000150040610
+#define SH_NI1_ERROR_SUMMARY_2_MASK              0x7fffffff003fffff
+#define SH_NI1_ERROR_SUMMARY_2_INIT              0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI                                */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI                                */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD                                */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB                              */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0                            */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1                            */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2                            */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3                            */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH                             */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR                         */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_SUMMARY_2_ALIAS"                */
+/*                     ni1 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_2_ALIAS             0x0000000150040618
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_1"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_1                  0x0000000150040620
+#define SH_NI1_ERROR_OVERFLOW_1_MASK             0xffffffffffffffff
+#define SH_NI1_ERROR_OVERFLOW_1_INIT             0xffffffffffffffff
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0                     */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2                     */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0                     */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2                     */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0                    */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2                    */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0                  */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2                  */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0                    */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2                    */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0                    */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1                    */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2                    */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3                    */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0                    */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2                    */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1                    */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3                    */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0                        */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1                        */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2                        */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3                        */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS"               */
+/*                    ni1 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_1_ALIAS            0x0000000150040628
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_2"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_2                  0x0000000150040630
+#define SH_NI1_ERROR_OVERFLOW_2_MASK             0x7fffffff003fffff
+#define SH_NI1_ERROR_OVERFLOW_2_INIT             0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI                               */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI                               */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD                               */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB                             */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP                   */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP                   */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP                   */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP                   */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH                  */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH                  */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH                  */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH                  */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT                */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT                */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT                */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT                */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP                  */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP                  */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP                */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP                */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP                  */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP                  */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP                  */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP                  */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH                 */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH                 */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH               */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH               */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH                 */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH                 */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT               */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT               */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT             */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT             */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT               */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT               */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT               */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT               */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT               */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT               */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0                           */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1                           */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2                           */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3                           */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR                        */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS"               */
+/*                    ni1 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_2_ALIAS            0x0000000150040638
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_1"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_MASK_1                      0x0000000150040640
+#define SH_NI1_ERROR_MASK_1_MASK                 0xffffffffffffffff
+#define SH_NI1_ERROR_MASK_1_INIT                 0xffffffffffffffff
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0                         */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2                         */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0                         */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2                         */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP                        */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP                        */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP                        */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP                        */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH                       */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH                       */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH                       */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH                       */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT                     */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT                     */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT                     */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT                     */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0                        */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2                        */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0                      */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2                      */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0                        */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2                        */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0                        */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1                        */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2                        */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3                        */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP                       */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP                       */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP                     */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP                     */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP                       */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP                       */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP                       */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP                       */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH                      */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH                      */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH                    */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH                    */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH                      */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH                      */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT                    */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT                    */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                  */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                  */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT                    */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT                    */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT                    */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT                    */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT                    */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT                    */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0                        */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2                        */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1                        */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3                        */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0                            */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1                            */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2                            */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3                            */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_2"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_MASK_2                      0x0000000150040650
+#define SH_NI1_ERROR_MASK_2_MASK                 0x7fffffff003fffff
+#define SH_NI1_ERROR_MASK_2_INIT                 0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI                                   */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT    0
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK    0x0000000000000001
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI                                   */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT    1
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK    0x0000000000000002
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD                                   */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT    2
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK    0x0000000000000004
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB                                 */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT  3
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK  0x0000000000000008
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0                               */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1                               */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2                               */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3                               */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH                                */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT  61
+#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK  0x2000000000000000
+
+/*   SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR                            */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_1"                    */
+/*                        ni1  First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_FIRST_ERROR_1                     0x0000000150040660
+#define SH_NI1_FIRST_ERROR_1_MASK                0xffffffffffffffff
+#define SH_NI1_FIRST_ERROR_1_INIT                0xffffffffffffffff
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0                        */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2                        */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0                        */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2                        */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0                       */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2                       */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0                     */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2                     */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0                       */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2                       */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0                       */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1                       */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2                       */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3                       */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0                       */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2                       */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1                       */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3                       */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0                           */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1                           */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2                           */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3                           */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_2"                    */
+/*                         ni1 First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_FIRST_ERROR_2                     0x0000000150040670
+#define SH_NI1_FIRST_ERROR_2_MASK                0x7fffffff003fffff
+#define SH_NI1_FIRST_ERROR_2_INIT                0x7fffffff003fffff
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI                                  */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT   0
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK   0x0000000000000001
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI                                  */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT   1
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK   0x0000000000000002
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD                                  */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT   2
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK   0x0000000000000004
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB                                */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP                      */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP                      */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP                      */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP                      */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH                     */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH                     */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH                     */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH                     */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT                   */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT                   */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT                   */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT                   */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP                     */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP                     */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP                   */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP                   */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP                     */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP                     */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP                     */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP                     */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH                    */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH                    */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                  */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                  */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH                    */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH                    */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                  */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                  */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                  */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                  */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                  */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                  */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                  */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                  */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0                              */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1                              */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2                              */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3                              */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR                           */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_1"                   */
+/*                ni1 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_1                    0x0000000150040680
+#define SH_NI1_ERROR_DETAIL_1_MASK               0xffffffffffffffff
+#define SH_NI1_ERROR_DETAIL_1_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_1_HEADER                                       */
+/*   Description:  Header bits 63:0                                     */
+#define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT        0
+#define SH_NI1_ERROR_DETAIL_1_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_2"                   */
+/*               ni1 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_2                    0x0000000150040690
+#define SH_NI1_ERROR_DETAIL_2_MASK               0xffffffffffffffff
+#define SH_NI1_ERROR_DETAIL_2_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_2_HEADER                                       */
+/*   Description:  Header bits 127:64                                   */
+#define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT        0
+#define SH_NI1_ERROR_DETAIL_2_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_1"                  */
+/*                       Corrected error details                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_1                 0x0000000150040070
+#define SH_XN_CORRECTED_DETAIL_1_MASK            0x0fff0fff0fff0fff
+#define SH_XN_CORRECTED_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME                             */
+/*   Description:  ECC0 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_WC                                   */
+/*   Description:  ECC0 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT    8
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK    0x0000000000000300
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_VC                                   */
+/*   Description:  ECC0 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT    10
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK    0x0000000000000c00
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME                             */
+/*   Description:  ECC1 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_WC                                   */
+/*   Description:  ECC1 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT    24
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK    0x0000000003000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_VC                                   */
+/*   Description:  ECC1 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT    26
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK    0x000000000c000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME                             */
+/*   Description:  ECC2 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_WC                                   */
+/*   Description:  ECC2 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT    40
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK    0x0000030000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_VC                                   */
+/*   Description:  ECC2 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT    42
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK    0x00000c0000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME                             */
+/*   Description:  ECC3 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_WC                                   */
+/*   Description:  ECC3 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT    56
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK    0x0300000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_VC                                   */
+/*   Description:  ECC3 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT    58
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK    0x0c00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_2"                  */
+/*                         Corrected error data                         */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_2                 0x0000000150040080
+#define SH_XN_CORRECTED_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_XN_CORRECTED_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_2_DATA                                      */
+/*   Description:  ECC data                                             */
+#define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT       0
+#define SH_XN_CORRECTED_DETAIL_2_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_3"                  */
+/*                       Corrected error header0                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_3                 0x0000000150040090
+#define SH_XN_CORRECTED_DETAIL_3_MASK            0xffffffffffffffff
+#define SH_XN_CORRECTED_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_3_HEADER0                                   */
+/*   Description:  ECC header0 (bits 63 - 0)                            */
+#define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT    0
+#define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_4"                  */
+/*                       Corrected error header1                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_4                 0x00000001500400a0
+#define SH_XN_CORRECTED_DETAIL_4_MASK            0xc00003ffffffffff
+#define SH_XN_CORRECTED_DETAIL_4_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_4_HEADER1                                   */
+/*   Description:  ECC header1 (bits 104 - 64)                          */
+#define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT    0
+#define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK    0x000003ffffffffff
+
+/*   SH_XN_CORRECTED_DETAIL_4_ERR_GROUP                                 */
+/*   Description:  Error group                                          */
+#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT  62
+#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK  0xc000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_1"                 */
+/*                      Uncorrected error details                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_1               0x00000001500400b0
+#define SH_XN_UNCORRECTED_DETAIL_1_MASK          0x0fff0fff0fff0fff
+#define SH_XN_UNCORRECTED_DETAIL_1_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME                           */
+/*   Description:  ECC0 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC                                 */
+/*   Description:  ECC0 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT  8
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK  0x0000000000000300
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC                                 */
+/*   Description:  ECC0 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT  10
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK  0x0000000000000c00
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME                           */
+/*   Description:  ECC1 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC                                 */
+/*   Description:  ECC1 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT  24
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK  0x0000000003000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC                                 */
+/*   Description:  ECC1 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT  26
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK  0x000000000c000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME                           */
+/*   Description:  ECC2 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC                                 */
+/*   Description:  ECC2 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT  40
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK  0x0000030000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC                                 */
+/*   Description:  ECC2 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT  42
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK  0x00000c0000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME                           */
+/*   Description:  ECC3 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC                                 */
+/*   Description:  ECC3 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT  56
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK  0x0300000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC                                 */
+/*   Description:  ECC3 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT  58
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK  0x0c00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_2"                 */
+/*                        Uncorrected error data                        */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_2               0x00000001500400c0
+#define SH_XN_UNCORRECTED_DETAIL_2_MASK          0xffffffffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_2_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_2_DATA                                    */
+/*   Description:  ECC data                                             */
+#define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT     0
+#define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_3"                 */
+/*                      Uncorrected error header0                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_3               0x00000001500400d0
+#define SH_XN_UNCORRECTED_DETAIL_3_MASK          0xffffffffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_3_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_3_HEADER0                                 */
+/*   Description:  ECC header0 (bits 63 - 0)                            */
+#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT  0
+#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_4"                 */
+/*                      Uncorrected error header1                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_4               0x00000001500400e0
+#define SH_XN_UNCORRECTED_DETAIL_4_MASK          0xc00003ffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_4_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_4_HEADER1                                 */
+/*   Description:  ECC header1 (bits 104 - 64)                          */
+#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT  0
+#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK  0x000003ffffffffff
+
+/*   SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP                               */
+/*   Description:  Error group                                          */
+#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62
+#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (md)                      */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_DETAIL_1                   0x00000001500400f0
+#define SH_XNMD_ERROR_DETAIL_1_MASK              0x00000000000007ff
+#define SH_XNMD_ERROR_DETAIL_1_INIT              0x0000000000000000
+
+/*   SH_XNMD_ERROR_DETAIL_1_LUT_ADDR                                    */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT     0
+#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK     0x00000000000007ff
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (pi)                      */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_DETAIL_1                   0x0000000150040100
+#define SH_XNPI_ERROR_DETAIL_1_MASK              0x00000000000007ff
+#define SH_XNPI_ERROR_DETAIL_1_INIT              0x0000000000000000
+
+/*   SH_XNPI_ERROR_DETAIL_1_LUT_ADDR                                    */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT     0
+#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK     0x00000000000007ff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_1"                  */
+/*                    Chiplet NoMatch header [63:0]                     */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_1                 0x0000000150040110
+#define SH_XNIILB_ERROR_DETAIL_1_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_1_HEADER                                    */
+/*   Description:  header bits [63:0]                                   */
+#define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT     0
+#define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_2"                  */
+/*                   Chiplet NoMatch header [127:64]                    */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_2                 0x0000000150040120
+#define SH_XNIILB_ERROR_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_2_HEADER                                    */
+/*   Description:  header bits [127:64]                                 */
+#define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT     0
+#define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_3"                  */
+/*                     Look Up Table Address (iilb)                     */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_3                 0x0000000150040130
+#define SH_XNIILB_ERROR_DETAIL_3_MASK            0x00000000000007ff
+#define SH_XNIILB_ERROR_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR                                  */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT   0
+#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK   0x00000000000007ff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni0)                      */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_3                    0x0000000150040140
+#define SH_NI0_ERROR_DETAIL_3_MASK               0x00000000000007ff
+#define SH_NI0_ERROR_DETAIL_3_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_3_LUT_ADDR                                     */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT      0
+#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK      0x00000000000007ff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni1)                      */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_3                    0x0000000150040150
+#define SH_NI1_ERROR_DETAIL_3_MASK               0x00000000000007ff
+#define SH_NI1_ERROR_DETAIL_3_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_3_LUT_ADDR                                     */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT      0
+#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK      0x00000000000007ff
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERROR_SUMMARY"                    */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_SUMMARY                      0x0000000150040000
+#define SH_XN_ERROR_SUMMARY_MASK                 0x0000003fffffffff
+#define SH_XN_ERROR_SUMMARY_INIT                 0x0000003fffffffff
+
+/*   SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW                               */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0
+#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW                              */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW                            */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW                             */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW                              */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW                             */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW                           */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR                                  */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT   7
+#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK   0x0000000000000080
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR                                 */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT  8
+#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK  0x0000000000000100
+
+/*   SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW                               */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9
+#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW                              */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW                            */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW                             */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW                              */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW                             */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW                           */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR                                  */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT   16
+#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK   0x0000000000010000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR                                 */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT  17
+#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK  0x0000000000020000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW                           */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW                            */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW                        */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW                          */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR                                 */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT  22
+#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK  0x0000000000400000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR                                 */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT  23
+#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK  0x0000000000800000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR                                 */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT  24
+#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK  0x0000000001000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW                           */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW                            */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW                        */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW                          */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR                                 */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT  29
+#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK  0x0000000020000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR                                 */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT  30
+#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK  0x0000000040000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR                                 */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT  31
+#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK  0x0000000080000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW                            */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW                           */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW                             */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW                          */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW                            */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT                            */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERRORS_ALIAS"                     */
+/* ==================================================================== */
+
+#define SH_XN_ERRORS_ALIAS                       0x0000000150040008
+
+/* ==================================================================== */
+/*                   Register "SH_XN_ERROR_OVERFLOW"                    */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_OVERFLOW                     0x0000000150040020
+#define SH_XN_ERROR_OVERFLOW_MASK                0x0000003fffffffff
+#define SH_XN_ERROR_OVERFLOW_INIT                0x0000003fffffffff
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW                              */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW                             */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW                           */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW                            */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW                             */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW                            */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW                          */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR                                 */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT  7
+#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK  0x0000000000000080
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR                                */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8
+#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW                              */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW                             */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW                           */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW                            */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW                             */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW                            */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW                          */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR                                 */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT  16
+#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK  0x0000000000010000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR                                */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17
+#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW                          */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW                           */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW                       */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW                         */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR                                */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22
+#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR                                */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23
+#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR                                */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24
+#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW                          */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW                           */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW                       */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW                         */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR                                */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29
+#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR                                */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30
+#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR                                */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31
+#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW                           */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW                          */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW                            */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW                         */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW                           */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT                           */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_ERROR_OVERFLOW_ALIAS"                 */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_OVERFLOW_ALIAS               0x0000000150040028
+
+/* ==================================================================== */
+/*                     Register "SH_XN_ERROR_MASK"                      */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_MASK                         0x0000000150040040
+#define SH_XN_ERROR_MASK_MASK                    0x0000003fffffffff
+#define SH_XN_ERROR_MASK_INIT                    0x0000003fffffffff
+
+/*   SH_XN_ERROR_MASK_NI0_POP_OVERFLOW                                  */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT   0
+#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK   0x0000000000000001
+
+/*   SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW                                 */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT  1
+#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK  0x0000000000000002
+
+/*   SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW                               */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW                                */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW                                 */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT  4
+#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK  0x0000000000000010
+
+/*   SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW                                */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW                              */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_MASK_NI0_LLP_ERROR                                     */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT      7
+#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK      0x0000000000000080
+
+/*   SH_XN_ERROR_MASK_NI0_PIPE_ERROR                                    */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT     8
+#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK     0x0000000000000100
+
+/*   SH_XN_ERROR_MASK_NI1_POP_OVERFLOW                                  */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT   9
+#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK   0x0000000000000200
+
+/*   SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW                                 */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT  10
+#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK  0x0000000000000400
+
+/*   SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW                               */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW                                */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW                                 */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT  13
+#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK  0x0000000000002000
+
+/*   SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW                                */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW                              */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_MASK_NI1_LLP_ERROR                                     */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT      16
+#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK      0x0000000000010000
+
+/*   SH_XN_ERROR_MASK_NI1_PIPE_ERROR                                    */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT     17
+#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK     0x0000000000020000
+
+/*   SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW                              */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW                               */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW                           */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW                             */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_MASK_XNMD_SBE_ERROR                                    */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT     22
+#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK     0x0000000000400000
+
+/*   SH_XN_ERROR_MASK_XNMD_UCE_ERROR                                    */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT     23
+#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK     0x0000000000800000
+
+/*   SH_XN_ERROR_MASK_XNMD_LUT_ERROR                                    */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT     24
+#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK     0x0000000001000000
+
+/*   SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW                              */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW                               */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW                           */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW                             */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_MASK_XNPI_SBE_ERROR                                    */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT     29
+#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK     0x0000000020000000
+
+/*   SH_XN_ERROR_MASK_XNPI_UCE_ERROR                                    */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT     30
+#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK     0x0000000040000000
+
+/*   SH_XN_ERROR_MASK_XNPI_LUT_ERROR                                    */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT     31
+#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK     0x0000000080000000
+
+/*   SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW                               */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW                              */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW                                */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW                             */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW                               */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT                               */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XN_FIRST_ERROR"                     */
+/* ==================================================================== */
+
+#define SH_XN_FIRST_ERROR                        0x0000000150040060
+#define SH_XN_FIRST_ERROR_MASK                   0x0000003fffffffff
+#define SH_XN_FIRST_ERROR_INIT                   0x0000003fffffffff
+
+/*   SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW                                 */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT  0
+#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK  0x0000000000000001
+
+/*   SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW                                */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW                              */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW                               */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW                                */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW                               */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW                             */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_FIRST_ERROR_NI0_LLP_ERROR                                    */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT     7
+#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK     0x0000000000000080
+
+/*   SH_XN_FIRST_ERROR_NI0_PIPE_ERROR                                   */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT    8
+#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK    0x0000000000000100
+
+/*   SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW                                 */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT  9
+#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK  0x0000000000000200
+
+/*   SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW                                */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW                              */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW                               */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW                                */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW                               */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW                             */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_FIRST_ERROR_NI1_LLP_ERROR                                    */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT     16
+#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK     0x0000000000010000
+
+/*   SH_XN_FIRST_ERROR_NI1_PIPE_ERROR                                   */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT    17
+#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK    0x0000000000020000
+
+/*   SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW                             */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW                              */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW                          */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW                            */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_FIRST_ERROR_XNMD_SBE_ERROR                                   */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT    22
+#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK    0x0000000000400000
+
+/*   SH_XN_FIRST_ERROR_XNMD_UCE_ERROR                                   */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT    23
+#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK    0x0000000000800000
+
+/*   SH_XN_FIRST_ERROR_XNMD_LUT_ERROR                                   */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT    24
+#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK    0x0000000001000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW                             */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW                              */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW                          */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW                            */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_SBE_ERROR                                   */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT    29
+#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK    0x0000000020000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_UCE_ERROR                                   */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT    30
+#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK    0x0000000040000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_LUT_ERROR                                   */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT    31
+#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK    0x0000000080000000
+
+/*   SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW                              */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW                             */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW                               */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW                            */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW                              */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT                              */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERROR_SUMMARY"                  */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_SUMMARY                  0x0000000150040200
+#define SH_XNIILB_ERROR_SUMMARY_MASK             0xffffffffffffffff
+#define SH_XNIILB_ERROR_SUMMARY_INIT             0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0                         */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2                         */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0                         */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2                         */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0                            */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2                            */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0                           */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2                           */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0                            */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2                            */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0                           */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2                           */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN                  */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN                */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN                  */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN                 */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN                 */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN                  */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN                */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN                  */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN                 */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN                 */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN                 */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN               */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN                 */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN                */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN                */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN                 */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN               */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN                 */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN                */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN                */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0                         */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2                         */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                       */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                       */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0                         */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2                         */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                        */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                        */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                        */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                        */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT                 */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT                 */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT                 */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT                 */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT               */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT               */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT                */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT                */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT                */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT                */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERRORS_ALIAS"                   */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERRORS_ALIAS                   0x0000000150040208
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_OVERFLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_OVERFLOW                 0x0000000150040220
+#define SH_XNIILB_ERROR_OVERFLOW_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_OVERFLOW_INIT            0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0                        */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2                        */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0                        */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2                        */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0                           */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2                           */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0                          */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2                          */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0                           */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2                           */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0                          */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2                          */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN                 */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN               */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN                 */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN                */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN                */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN                 */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN               */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN                 */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN                */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN                */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN                */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN              */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN                */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN               */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN               */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN                */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN              */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN                */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN               */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN               */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0                        */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2                        */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                      */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                      */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0                        */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2                        */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                       */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                       */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                       */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                       */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT               */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT               */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT               */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT               */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT             */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT             */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT              */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT              */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT              */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT              */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH                           */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR                            */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS"               */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_OVERFLOW_ALIAS           0x0000000150040228
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_ERROR_MASK"                    */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_MASK                     0x0000000150040240
+#define SH_XNIILB_ERROR_MASK_MASK                0xffffffffffffffff
+#define SH_XNIILB_ERROR_MASK_INIT                0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0                            */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2                            */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0                            */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2                            */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0                               */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2                               */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0                              */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2                              */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0                               */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2                               */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0                              */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2                              */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN                     */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN                   */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN                     */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN                    */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN                    */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN                     */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN                   */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN                     */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN                    */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN                    */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN                    */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN                  */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN                    */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN                   */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN                   */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN                    */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN                  */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN                    */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN                   */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN                   */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0                            */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2                            */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0                          */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2                          */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0                            */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2                            */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0                           */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2                           */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0                           */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2                           */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT                    */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT                    */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT                    */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT                    */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT                  */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT                  */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT                   */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT                   */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT                   */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT                   */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_FIRST_ERROR"                   */
+/* ==================================================================== */
+
+#define SH_XNIILB_FIRST_ERROR                    0x0000000150040260
+#define SH_XNIILB_FIRST_ERROR_MASK               0xffffffffffffffff
+#define SH_XNIILB_FIRST_ERROR_INIT               0xffffffffffffffff
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0                           */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2                           */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0                           */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2                           */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0                              */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2                              */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0                             */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2                             */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0                              */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2                              */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0                             */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2                             */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN                    */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN                  */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN                    */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN                   */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN                   */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN                    */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN                  */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN                    */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN                   */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN                   */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN                   */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN                 */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN                   */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN                  */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN                  */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN                   */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN                 */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN                   */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN                  */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN                  */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0                           */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2                           */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0                           */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2                           */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT                  */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT                  */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT                  */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT                  */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT                */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT                */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT                 */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT                 */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT                 */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT                 */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH                              */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_SUMMARY                    0x0000000150040300
+#define SH_XNPI_ERROR_SUMMARY_MASK               0x0003ffffffffffff
+#define SH_XNPI_ERROR_SUMMARY_INIT               0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0                             */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2                             */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0                             */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2                             */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0                            */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2                            */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT                          */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT                          */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0                        */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2                        */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
+#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0                            */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1                            */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2                            */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3                            */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0                                 */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT  23
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK  0x0000000000800000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1                                 */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT  24
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK  0x0000000001000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2                                 */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT  25
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK  0x0000000002000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3                                 */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT  26
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK  0x0000000004000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0                           */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2                           */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT                      */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT                      */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT                      */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT                      */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT                     */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT                     */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO                  */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERRORS_ALIAS"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_ERRORS_ALIAS                     0x0000000150040308
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_OVERFLOW                   0x0000000150040320
+#define SH_XNPI_ERROR_OVERFLOW_MASK              0x0003ffffffffffff
+#define SH_XNPI_ERROR_OVERFLOW_INIT              0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0                           */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2                           */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0                           */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2                           */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0                          */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2                          */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT                        */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT                        */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0                       */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2                       */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
+#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0                           */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1                           */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2                           */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3                           */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0                                */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1                                */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2                                */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3                                */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0                         */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2                         */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                         */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                         */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                         */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                         */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                        */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                        */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT                    */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT                    */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT                    */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT                    */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT                   */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT                   */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO                 */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_ERROR_OVERFLOW_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_OVERFLOW_ALIAS             0x0000000150040328
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_MASK                       0x0000000150040340
+#define SH_XNPI_ERROR_MASK_MASK                  0x0003ffffffffffff
+#define SH_XNPI_ERROR_MASK_INIT                  0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0                                */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2                                */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0                                */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2                                */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0                               */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2                               */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT                             */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT                             */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0                           */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2                           */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_MASK_LUT_READ_ERROR                                  */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT   18
+#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK   0x0000000000040000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0                               */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1                               */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2                               */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3                               */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR0                                    */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT     23
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK     0x0000000000800000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR1                                    */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT     24
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK     0x0000000001000000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR2                                    */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT     25
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK     0x0000000002000000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR3                                    */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT     26
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK     0x0000000004000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0                              */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2                              */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0                             */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2                             */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0                             */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2                             */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0                            */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2                            */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT                         */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT                         */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT                         */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT                         */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT                        */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT                        */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO                     */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_FIRST_ERROR                      0x0000000150040360
+#define SH_XNPI_FIRST_ERROR_MASK                 0x0003ffffffffffff
+#define SH_XNPI_FIRST_ERROR_INIT                 0x0003ffffffffffff
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0                              */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2                              */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0                              */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2                              */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0                             */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2                             */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT                           */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT                           */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0                          */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2                          */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_FIRST_ERROR_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT  18
+#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK  0x0000000000040000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0                              */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1                              */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2                              */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3                              */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR0                                   */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT    23
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK    0x0000000000800000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR1                                   */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT    24
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK    0x0000000001000000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR2                                   */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT    25
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK    0x0000000002000000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR3                                   */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT    26
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK    0x0000000004000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0                            */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2                            */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                            */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                            */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                            */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                            */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                           */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                           */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT                       */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT                       */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT                       */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT                       */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT                      */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT                      */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO                    */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_SUMMARY                    0x0000000150040400
+#define SH_XNMD_ERROR_SUMMARY_MASK               0x0003ffffffffffff
+#define SH_XNMD_ERROR_SUMMARY_INIT               0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0                             */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2                             */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0                             */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2                             */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0                            */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2                            */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT                          */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT                          */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0                        */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2                        */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
+#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0                            */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1                            */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2                            */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3                            */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0                                 */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT  23
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK  0x0000000000800000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1                                 */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT  24
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK  0x0000000001000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2                                 */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT  25
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK  0x0000000002000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3                                 */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT  26
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK  0x0000000004000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0                           */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2                           */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT                      */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT                      */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT                      */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT                      */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT                     */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT                     */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO                  */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERRORS_ALIAS"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_ERRORS_ALIAS                     0x0000000150040408
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_OVERFLOW                   0x0000000150040420
+#define SH_XNMD_ERROR_OVERFLOW_MASK              0x0003ffffffffffff
+#define SH_XNMD_ERROR_OVERFLOW_INIT              0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0                           */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2                           */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0                           */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2                           */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0                          */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2                          */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT                        */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT                        */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0                       */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2                       */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
+#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0                           */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1                           */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2                           */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3                           */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0                                */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1                                */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2                                */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3                                */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0                         */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2                         */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                         */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                         */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                         */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                         */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                        */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                        */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT                    */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT                    */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT                    */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT                    */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT                   */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT                   */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO                 */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_ERROR_OVERFLOW_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_OVERFLOW_ALIAS             0x0000000150040428
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_MASK                       0x0000000150040440
+#define SH_XNMD_ERROR_MASK_MASK                  0x0003ffffffffffff
+#define SH_XNMD_ERROR_MASK_INIT                  0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0                                */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2                                */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0                                */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2                                */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0                               */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2                               */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT                             */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT                             */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0                           */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2                           */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_MASK_LUT_READ_ERROR                                  */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT   18
+#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK   0x0000000000040000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0                               */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1                               */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2                               */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3                               */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR0                                    */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT     23
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK     0x0000000000800000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR1                                    */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT     24
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK     0x0000000001000000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR2                                    */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT     25
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK     0x0000000002000000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR3                                    */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT     26
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK     0x0000000004000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0                              */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2                              */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0                             */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2                             */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0                             */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2                             */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0                            */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2                            */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT                         */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT                         */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT                         */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT                         */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT                        */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT                        */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO                     */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_FIRST_ERROR                      0x0000000150040460
+#define SH_XNMD_FIRST_ERROR_MASK                 0x0003ffffffffffff
+#define SH_XNMD_FIRST_ERROR_INIT                 0x0003ffffffffffff
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0                              */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2                              */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0                              */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2                              */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0                             */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2                             */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT                           */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT                           */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0                          */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2                          */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_FIRST_ERROR_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT  18
+#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK  0x0000000000040000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0                              */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1                              */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2                              */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3                              */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR0                                   */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT    23
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK    0x0000000000800000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR1                                   */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT    24
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK    0x0000000001000000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR2                                   */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT    25
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK    0x0000000002000000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR3                                   */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT    26
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK    0x0000000004000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0                            */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2                            */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                            */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                            */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                            */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                            */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                           */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                           */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT                       */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT                       */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT                       */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT                       */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT                      */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT                      */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO                    */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE0"                   */
+/*                 Automatic Maintenance Reply Enable 0                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_ENABLE0                    0x0000000110061000
+#define SH_AUTO_REPLY_ENABLE0_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_ENABLE0_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_ENABLE0_ENABLE0                                      */
+/*   Description:  Enable 0                                             */
+#define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT       0
+#define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE1"                   */
+/*                 Automatic Maintenance Reply Enable 1                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_ENABLE1                    0x0000000110061080
+#define SH_AUTO_REPLY_ENABLE1_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_ENABLE1_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_ENABLE1_ENABLE1                                      */
+/*   Description:  Enable 1                                             */
+#define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT       0
+#define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER0"                   */
+/*                 Automatic Maintenance Reply Header 0                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_HEADER0                    0x0000000110061100
+#define SH_AUTO_REPLY_HEADER0_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_HEADER0_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_HEADER0_HEADER0                                      */
+/*   Description:  Header 0                                             */
+#define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT       0
+#define SH_AUTO_REPLY_HEADER0_HEADER0_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER1"                   */
+/*                 Automatic Maintenance Reply Header 1                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_HEADER1                    0x0000000110061180
+#define SH_AUTO_REPLY_HEADER1_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_HEADER1_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_HEADER1_HEADER1                                      */
+/*   Description:  Header 1                                             */
+#define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT       0
+#define SH_AUTO_REPLY_HEADER1_HEADER1_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RP_AUTO_REPLY"                  */
+/*         Enable Automatic Maintenance Reply From Reply Queue          */
+/* ==================================================================== */
+
+#define SH_ENABLE_RP_AUTO_REPLY                  0x0000000110061200
+#define SH_ENABLE_RP_AUTO_REPLY_MASK             0x0000000000000001
+#define SH_ENABLE_RP_AUTO_REPLY_INIT             0x0000000000000000
+
+/*   SH_ENABLE_RP_AUTO_REPLY_ENABLE                                     */
+/*   Description:  Enable Reply Auto Reply                              */
+#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT      0
+#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RQ_AUTO_REPLY"                  */
+/*        Enable Automatic Maintenance Reply From Request Queue         */
+/* ==================================================================== */
+
+#define SH_ENABLE_RQ_AUTO_REPLY                  0x0000000110061280
+#define SH_ENABLE_RQ_AUTO_REPLY_MASK             0x0000000000000001
+#define SH_ENABLE_RQ_AUTO_REPLY_INIT             0x0000000000000000
+
+/*   SH_ENABLE_RQ_AUTO_REPLY_ENABLE                                     */
+/*   Description:  Enable Request Auto Reply                            */
+#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT      0
+#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_REDIRECT_INVAL"                     */
+/*               Redirect invalidate to LB instead of PI                */
+/* ==================================================================== */
+
+#define SH_REDIRECT_INVAL                        0x0000000110061300
+#define SH_REDIRECT_INVAL_MASK                   0x0000000000000001
+#define SH_REDIRECT_INVAL_INIT                   0x0000000000000000
+
+/*   SH_REDIRECT_INVAL_REDIRECT                                         */
+/*   Description:  Redirect invalidates to LB instead of PI             */
+#define SH_REDIRECT_INVAL_REDIRECT_SHFT          0
+#define SH_REDIRECT_INVAL_REDIRECT_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_CNTRL"                     */
+/*                 Diagnostic Message Control Register                  */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_CNTRL                        0x0000000110062000
+#define SH_DIAG_MSG_CNTRL_MASK                   0xc000000000003fff
+#define SH_DIAG_MSG_CNTRL_INIT                   0x0000000000000000
+
+/*   SH_DIAG_MSG_CNTRL_MSG_LENGTH                                       */
+/*   Description:  Message data payload length, 0 - 63                  */
+#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT        0
+#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK        0x000000000000003f
+
+/*   SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT                               */
+/*   Description:  Point message that the error bit would be activated  */
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0
+
+/*   SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE                              */
+/*   Description:  Enable ERROR_INJECT_POINT field                      */
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000
+
+/*   SH_DIAG_MSG_CNTRL_PORT                                             */
+/*   Description:  0 = request port, 1 = reply port                     */
+#define SH_DIAG_MSG_CNTRL_PORT_SHFT              13
+#define SH_DIAG_MSG_CNTRL_PORT_MASK              0x0000000000002000
+
+/*   SH_DIAG_MSG_CNTRL_START                                            */
+/*   Description:  Start                                                */
+#define SH_DIAG_MSG_CNTRL_START_SHFT             62
+#define SH_DIAG_MSG_CNTRL_START_MASK             0x4000000000000000
+
+/*   SH_DIAG_MSG_CNTRL_BUSY                                             */
+/*   Description:  Busy                                                 */
+#define SH_DIAG_MSG_CNTRL_BUSY_SHFT              63
+#define SH_DIAG_MSG_CNTRL_BUSY_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA0L                       0x0000000110062080
+#define SH_DIAG_MSG_DATA0L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA0L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA0L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA0U                       0x0000000110062100
+#define SH_DIAG_MSG_DATA0U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA0U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA0U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA1L                       0x0000000110062180
+#define SH_DIAG_MSG_DATA1L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA1L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA1L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA1U                       0x0000000110062200
+#define SH_DIAG_MSG_DATA1U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA1U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA1U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA2L                       0x0000000110062280
+#define SH_DIAG_MSG_DATA2L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA2L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA2L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA2U                       0x0000000110062300
+#define SH_DIAG_MSG_DATA2U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA2U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA2U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA3L                       0x0000000110062380
+#define SH_DIAG_MSG_DATA3L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA3L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA3L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA3U                       0x0000000110062400
+#define SH_DIAG_MSG_DATA3U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA3U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA3U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA4L                       0x0000000110062480
+#define SH_DIAG_MSG_DATA4L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA4L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA4L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA4U                       0x0000000110062500
+#define SH_DIAG_MSG_DATA4U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA4U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA4U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA5L                       0x0000000110062580
+#define SH_DIAG_MSG_DATA5L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA5L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA5L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA5U                       0x0000000110062600
+#define SH_DIAG_MSG_DATA5U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA5U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA5U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA6L                       0x0000000110062680
+#define SH_DIAG_MSG_DATA6L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA6L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA6L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA6U                       0x0000000110062700
+#define SH_DIAG_MSG_DATA6U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA6U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA6U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA7L                       0x0000000110062780
+#define SH_DIAG_MSG_DATA7L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA7L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA7L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA7U                       0x0000000110062800
+#define SH_DIAG_MSG_DATA7U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA7U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA7U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA8L                       0x0000000110062880
+#define SH_DIAG_MSG_DATA8L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA8L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA8L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA8U                       0x0000000110062900
+#define SH_DIAG_MSG_DATA8U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA8U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA8U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR0"                      */
+/*              Diagnostice Data, lower 64 bits of header               */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_HDR0                         0x0000000110062980
+#define SH_DIAG_MSG_HDR0_MASK                    0xffffffffffffffff
+#define SH_DIAG_MSG_HDR0_INIT                    0x0000000000000000
+
+/*   SH_DIAG_MSG_HDR0_HEADER0                                           */
+/*   Description:  Lower 64 bits of Diagnositic Message Header          */
+#define SH_DIAG_MSG_HDR0_HEADER0_SHFT            0
+#define SH_DIAG_MSG_HDR0_HEADER0_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR1"                      */
+/*              Diagnostice Data, upper 64 bits of header               */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_HDR1                         0x0000000110062a00
+#define SH_DIAG_MSG_HDR1_MASK                    0xffffffffffffffff
+#define SH_DIAG_MSG_HDR1_INIT                    0x0000000000000000
+
+/*   SH_DIAG_MSG_HDR1_HEADER1                                           */
+/*   Description:  Upper 64 bits of Diagnositic Message Header          */
+#define SH_DIAG_MSG_HDR1_HEADER1_SHFT            0
+#define SH_DIAG_MSG_HDR1_HEADER1_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_DEBUG_SELECT"                      */
+/*                        SHub Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_DEBUG_SELECT                          0x0000000110063000
+#define SH_DEBUG_SELECT_MASK                     0x8fffffffffffffff
+#define SH_DEBUG_SELECT_INIT                     0x0000e38e38e38e38
+
+/*   SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL                                 */
+/*   Description:  Nibble0_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT  0
+#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK  0x0000000000000007
+
+/*   SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL                                */
+/*   Description:  Nibble0_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3
+#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038
+
+/*   SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL                                 */
+/*   Description:  Nibble1_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT  6
+#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK  0x00000000000001c0
+
+/*   SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL                                */
+/*   Description:  Nibble1_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9
+#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00
+
+/*   SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL                                 */
+/*   Description:  Nibble2_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT  12
+#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK  0x0000000000007000
+
+/*   SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL                                */
+/*   Description:  Nibble2_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15
+#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000
+
+/*   SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL                                 */
+/*   Description:  Nibble3_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT  18
+#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK  0x00000000001c0000
+
+/*   SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL                                */
+/*   Description:  Nibble3_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21
+#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000
+
+/*   SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL                                 */
+/*   Description:  Nibble4_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT  24
+#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK  0x0000000007000000
+
+/*   SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL                                */
+/*   Description:  Nibble4_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27
+#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000
+
+/*   SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL                                 */
+/*   Description:  Nibble5_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT  30
+#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK  0x00000001c0000000
+
+/*   SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL                                */
+/*   Description:  Nibble5_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33
+#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000
+
+/*   SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL                                 */
+/*   Description:  Nibble6_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT  36
+#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK  0x0000007000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL                                */
+/*   Description:  Nibble6_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39
+#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL                                 */
+/*   Description:  Nibble7_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT  42
+#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK  0x00001c0000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL                                */
+/*   Description:  Nibble7_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45
+#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000
+
+/*   SH_DEBUG_SELECT_DEBUG_II_SEL                                       */
+/*   Description:  Select bits to II port                               */
+#define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT        48
+#define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK        0x0007000000000000
+
+/*   SH_DEBUG_SELECT_SEL_II                                             */
+/*   Description:  Select II to debug port                              */
+#define SH_DEBUG_SELECT_SEL_II_SHFT              51
+#define SH_DEBUG_SELECT_SEL_II_MASK              0x0ff8000000000000
+
+/*   SH_DEBUG_SELECT_TRIGGER_ENABLE                                     */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT      63
+#define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_TRIGGER_COMPARE_MASK"                  */
+/*                      SHub Trigger Compare Mask                       */
+/* ==================================================================== */
+
+#define SH_TRIGGER_COMPARE_MASK                  0x0000000110063080
+#define SH_TRIGGER_COMPARE_MASK_MASK             0x00000000ffffffff
+#define SH_TRIGGER_COMPARE_MASK_INIT             0x0000000000000000
+
+/*   SH_TRIGGER_COMPARE_MASK_MASK                                       */
+/*   Description:  SHub Trigger Compare Mask                            */
+#define SH_TRIGGER_COMPARE_MASK_MASK_SHFT        0
+#define SH_TRIGGER_COMPARE_MASK_MASK_MASK        0x00000000ffffffff
+
+/* ==================================================================== */
+/*                Register "SH_TRIGGER_COMPARE_PATTERN"                 */
+/*                     SHub Trigger Compare Pattern                     */
+/* ==================================================================== */
+
+#define SH_TRIGGER_COMPARE_PATTERN               0x0000000110063100
+#define SH_TRIGGER_COMPARE_PATTERN_MASK          0x00000000ffffffff
+#define SH_TRIGGER_COMPARE_PATTERN_INIT          0x0000000000000000
+
+/*   SH_TRIGGER_COMPARE_PATTERN_DATA                                    */
+/*   Description:  SHub Trigger Compare Pattern                         */
+#define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT     0
+#define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK     0x00000000ffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_TRIGGER_SEL"                       */
+/*                  Trigger select for SHUB debug port                  */
+/* ==================================================================== */
+
+#define SH_TRIGGER_SEL                           0x0000000110063180
+#define SH_TRIGGER_SEL_MASK                      0x7777777777777777
+#define SH_TRIGGER_SEL_INIT                      0x0000000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL                                   */
+/*   Description:  Nibble 0 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT    0
+#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK    0x0000000000000007
+
+/*   SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL                                  */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT   4
+#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK   0x0000000000000070
+
+/*   SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL                                   */
+/*   Description:  Nibble 1 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT    8
+#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK    0x0000000000000700
+
+/*   SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL                                  */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT   12
+#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK   0x0000000000007000
+
+/*   SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL                                   */
+/*   Description:  Nibble 2 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT    16
+#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK    0x0000000000070000
+
+/*   SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL                                  */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT   20
+#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK   0x0000000000700000
+
+/*   SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL                                   */
+/*   Description:  Nibble 3 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT    24
+#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK    0x0000000007000000
+
+/*   SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL                                  */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT   28
+#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK   0x0000000070000000
+
+/*   SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL                                   */
+/*   Description:  Nibble 4 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT    32
+#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK    0x0000000700000000
+
+/*   SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL                                  */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT   36
+#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK   0x0000007000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL                                   */
+/*   Description:  Nibble 5 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT    40
+#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK    0x0000070000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL                                  */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT   44
+#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK   0x0000700000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL                                   */
+/*   Description:  Nibble 6 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT    48
+#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK    0x0007000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL                                  */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT   52
+#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK   0x0070000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL                                   */
+/*   Description:  Nibble 7 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT    56
+#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK    0x0700000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL                                  */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT   60
+#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK   0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_STOP_CLK_CONTROL"                    */
+/*                          Stop Clock Control                          */
+/* ==================================================================== */
+
+#define SH_STOP_CLK_CONTROL                      0x0000000110064000
+#define SH_STOP_CLK_CONTROL_MASK                 0x00000000000000ff
+#define SH_STOP_CLK_CONTROL_INIT                 0x00000000000000e0
+
+/*   SH_STOP_CLK_CONTROL_STIMULUS                                       */
+/*   Description:  Counter stimulus                                     */
+#define SH_STOP_CLK_CONTROL_STIMULUS_SHFT        0
+#define SH_STOP_CLK_CONTROL_STIMULUS_MASK        0x000000000000001f
+
+/*   SH_STOP_CLK_CONTROL_EVENT                                          */
+/*   Description:  Counter event select (0-greater than, 1-equal)       */
+#define SH_STOP_CLK_CONTROL_EVENT_SHFT           5
+#define SH_STOP_CLK_CONTROL_EVENT_MASK           0x0000000000000020
+
+/*   SH_STOP_CLK_CONTROL_POLARITY                                       */
+/*   Description:  Counter polarity select (0-negative edge, 1-positiv  */
+/*  e edge)                                                             */
+#define SH_STOP_CLK_CONTROL_POLARITY_SHFT        6
+#define SH_STOP_CLK_CONTROL_POLARITY_MASK        0x0000000000000040
+
+/*   SH_STOP_CLK_CONTROL_MODE                                           */
+/*   Description:  Counter mode select (0-internal, 1-external)         */
+#define SH_STOP_CLK_CONTROL_MODE_SHFT            7
+#define SH_STOP_CLK_CONTROL_MODE_MASK            0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_STOP_CLK_DELAY_PHASE"                  */
+/*                        Stop Clock Delay Phase                        */
+/* ==================================================================== */
+
+#define SH_STOP_CLK_DELAY_PHASE                  0x0000000110064080
+#define SH_STOP_CLK_DELAY_PHASE_MASK             0x00000000000000ff
+#define SH_STOP_CLK_DELAY_PHASE_INIT             0x0000000000000000
+
+/*   SH_STOP_CLK_DELAY_PHASE_DELAY                                      */
+/*   Description:  Delay phase                                          */
+#define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT       0
+#define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK       0x00000000000000ff
+
+/* ==================================================================== */
+/*                      Register "SH_TSF_ARM_MASK"                      */
+/*                 Trigger sequencing facility arm mask                 */
+/* ==================================================================== */
+
+#define SH_TSF_ARM_MASK                          0x0000000110065000
+#define SH_TSF_ARM_MASK_MASK                     0xffffffffffffffff
+#define SH_TSF_ARM_MASK_INIT                     0x0000000000000000
+
+/*   SH_TSF_ARM_MASK_MASK                                               */
+/*   Description:  Trigger sequencing facility arm mask                 */
+#define SH_TSF_ARM_MASK_MASK_SHFT                0
+#define SH_TSF_ARM_MASK_MASK_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_COUNTER_PRESETS"                   */
+/*             Trigger sequencing facility counter presets              */
+/* ==================================================================== */
+
+#define SH_TSF_COUNTER_PRESETS                   0x0000000110065080
+#define SH_TSF_COUNTER_PRESETS_MASK              0xffffffffffffffff
+#define SH_TSF_COUNTER_PRESETS_INIT              0x0000000000000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_32                                    */
+/*   Description:  Trigger sequencing facility counter 32               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT     0
+#define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK     0x00000000ffffffff
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_16                                    */
+/*   Description:  Trigger sequencing facility counter 16               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT     32
+#define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK     0x0000ffff00000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_8B                                    */
+/*   Description:  Trigger sequencing facility counter 8b               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT     48
+#define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK     0x00ff000000000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_8A                                    */
+/*   Description:  Trigger sequencing facility counter 8a               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT     56
+#define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK     0xff00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_DECREMENT_CTL"                    */
+/*        Trigger sequencing facility counter decrement control         */
+/* ==================================================================== */
+
+#define SH_TSF_DECREMENT_CTL                     0x0000000110065100
+#define SH_TSF_DECREMENT_CTL_MASK                0x000000000000ffff
+#define SH_TSF_DECREMENT_CTL_INIT                0x0000000000000000
+
+/*   SH_TSF_DECREMENT_CTL_CTL                                           */
+/*   Description:  Trigger sequencing facility counter decrement contr  */
+#define SH_TSF_DECREMENT_CTL_CTL_SHFT            0
+#define SH_TSF_DECREMENT_CTL_CTL_MASK            0x000000000000ffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DIAG_MSG_CTL"                    */
+/*        Trigger sequencing facility diagnostic message control        */
+/* ==================================================================== */
+
+#define SH_TSF_DIAG_MSG_CTL                      0x0000000110065180
+#define SH_TSF_DIAG_MSG_CTL_MASK                 0x00000000000000ff
+#define SH_TSF_DIAG_MSG_CTL_INIT                 0x0000000000000000
+
+/*   SH_TSF_DIAG_MSG_CTL_ENABLE                                         */
+/*   Description:  Trigger sequencing facility diagnostic message cont  */
+#define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT          0
+#define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DISARM_MASK"                     */
+/*               Trigger sequencing facility disarm mask                */
+/* ==================================================================== */
+
+#define SH_TSF_DISARM_MASK                       0x0000000110065200
+#define SH_TSF_DISARM_MASK_MASK                  0xffffffffffffffff
+#define SH_TSF_DISARM_MASK_INIT                  0x0000000000000000
+
+/*   SH_TSF_DISARM_MASK_MASK                                            */
+/*   Description:  Trigger sequencing facility disarm mask              */
+#define SH_TSF_DISARM_MASK_MASK_SHFT             0
+#define SH_TSF_DISARM_MASK_MASK_MASK             0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_TSF_ENABLE_CTL"                     */
+/*          Trigger sequencing facility counter enable control          */
+/* ==================================================================== */
+
+#define SH_TSF_ENABLE_CTL                        0x0000000110065280
+#define SH_TSF_ENABLE_CTL_MASK                   0x000000000000ffff
+#define SH_TSF_ENABLE_CTL_INIT                   0x0000000000000000
+
+/*   SH_TSF_ENABLE_CTL_CTL                                              */
+/*   Description:  Trigger sequencing facility counter enable control  */
+#define SH_TSF_ENABLE_CTL_CTL_SHFT               0
+#define SH_TSF_ENABLE_CTL_CTL_MASK               0x000000000000ffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_SOFTWARE_ARM"                    */
+/*               Trigger sequencing facility software arm               */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_ARM                      0x0000000110065300
+#define SH_TSF_SOFTWARE_ARM_MASK                 0x00000000000000ff
+#define SH_TSF_SOFTWARE_ARM_INIT                 0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_ARM_BIT0                                           */
+/*   Description:  Trigger sequencing facility software arm bit 0       */
+#define SH_TSF_SOFTWARE_ARM_BIT0_SHFT            0
+#define SH_TSF_SOFTWARE_ARM_BIT0_MASK            0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_ARM_BIT1                                           */
+/*   Description:  Trigger sequencing facility software arm bit 1       */
+#define SH_TSF_SOFTWARE_ARM_BIT1_SHFT            1
+#define SH_TSF_SOFTWARE_ARM_BIT1_MASK            0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_ARM_BIT2                                           */
+/*   Description:  Trigger sequencing facility software arm bit 2       */
+#define SH_TSF_SOFTWARE_ARM_BIT2_SHFT            2
+#define SH_TSF_SOFTWARE_ARM_BIT2_MASK            0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_ARM_BIT3                                           */
+/*   Description:  Trigger sequencing facility software arm bit 3       */
+#define SH_TSF_SOFTWARE_ARM_BIT3_SHFT            3
+#define SH_TSF_SOFTWARE_ARM_BIT3_MASK            0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_ARM_BIT4                                           */
+/*   Description:  Trigger sequencing facility software arm bit 4       */
+#define SH_TSF_SOFTWARE_ARM_BIT4_SHFT            4
+#define SH_TSF_SOFTWARE_ARM_BIT4_MASK            0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_ARM_BIT5                                           */
+/*   Description:  Trigger sequencing facility software arm bit 5       */
+#define SH_TSF_SOFTWARE_ARM_BIT5_SHFT            5
+#define SH_TSF_SOFTWARE_ARM_BIT5_MASK            0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_ARM_BIT6                                           */
+/*   Description:  Trigger sequencing facility software arm bit 6       */
+#define SH_TSF_SOFTWARE_ARM_BIT6_SHFT            6
+#define SH_TSF_SOFTWARE_ARM_BIT6_MASK            0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_ARM_BIT7                                           */
+/*   Description:  Trigger sequencing facility software arm bit 7       */
+#define SH_TSF_SOFTWARE_ARM_BIT7_SHFT            7
+#define SH_TSF_SOFTWARE_ARM_BIT7_MASK            0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_SOFTWARE_DISARM"                   */
+/*             Trigger sequencing facility software disarm              */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_DISARM                   0x0000000110065380
+#define SH_TSF_SOFTWARE_DISARM_MASK              0x00000000000000ff
+#define SH_TSF_SOFTWARE_DISARM_INIT              0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT0                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 0    */
+#define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT         0
+#define SH_TSF_SOFTWARE_DISARM_BIT0_MASK         0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT1                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 1    */
+#define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT         1
+#define SH_TSF_SOFTWARE_DISARM_BIT1_MASK         0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT2                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 2    */
+#define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT         2
+#define SH_TSF_SOFTWARE_DISARM_BIT2_MASK         0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT3                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 3    */
+#define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT         3
+#define SH_TSF_SOFTWARE_DISARM_BIT3_MASK         0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT4                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 4    */
+#define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT         4
+#define SH_TSF_SOFTWARE_DISARM_BIT4_MASK         0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT5                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 5    */
+#define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT         5
+#define SH_TSF_SOFTWARE_DISARM_BIT5_MASK         0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT6                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 6    */
+#define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT         6
+#define SH_TSF_SOFTWARE_DISARM_BIT6_MASK         0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT7                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 7    */
+#define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT         7
+#define SH_TSF_SOFTWARE_DISARM_BIT7_MASK         0x0000000000000080
+
+/* ==================================================================== */
+/*                 Register "SH_TSF_SOFTWARE_TRIGGERED"                 */
+/*            Trigger sequencing facility software triggered            */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_TRIGGERED                0x0000000110065400
+#define SH_TSF_SOFTWARE_TRIGGERED_MASK           0x00000000000000ff
+#define SH_TSF_SOFTWARE_TRIGGERED_INIT           0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT0                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT      0
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK      0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT1                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT      1
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK      0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT2                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT      2
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK      0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT3                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT      3
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK      0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT4                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT      4
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK      0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT5                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT      5
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK      0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT6                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT      6
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK      0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT7                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT      7
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK      0x0000000000000080
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_TRIGGER_MASK"                    */
+/*               Trigger sequencing facility trigger mask               */
+/* ==================================================================== */
+
+#define SH_TSF_TRIGGER_MASK                      0x0000000110065480
+#define SH_TSF_TRIGGER_MASK_MASK                 0xffffffffffffffff
+#define SH_TSF_TRIGGER_MASK_INIT                 0x0000000000000000
+
+/*   SH_TSF_TRIGGER_MASK_MASK                                           */
+/*   Description:  Trigger sequencing facility trigger mask             */
+#define SH_TSF_TRIGGER_MASK_MASK_SHFT            0
+#define SH_TSF_TRIGGER_MASK_MASK_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_VEC_DATA"                        */
+/*                  Vector Write Request Message Data                   */
+/* ==================================================================== */
+
+#define SH_VEC_DATA                              0x0000000110066000
+#define SH_VEC_DATA_MASK                         0xffffffffffffffff
+#define SH_VEC_DATA_INIT                         0x0000000000000000
+
+/*   SH_VEC_DATA_DATA                                                   */
+/*   Description:  Data                                                 */
+#define SH_VEC_DATA_DATA_SHFT                    0
+#define SH_VEC_DATA_DATA_MASK                    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_PARMS"                        */
+/*                  Vector Message Parameters Register                  */
+/* ==================================================================== */
+
+#define SH_VEC_PARMS                             0x0000000110066080
+#define SH_VEC_PARMS_MASK                        0xc0003ffffffffffb
+#define SH_VEC_PARMS_INIT                        0x0000000000000000
+
+/*   SH_VEC_PARMS_TYPE                                                  */
+/*   Description:  Vector Request Message Type                          */
+#define SH_VEC_PARMS_TYPE_SHFT                   0
+#define SH_VEC_PARMS_TYPE_MASK                   0x0000000000000001
+
+/*   SH_VEC_PARMS_NI_PORT                                               */
+/*   Description:  Network Interface Port Select                        */
+#define SH_VEC_PARMS_NI_PORT_SHFT                1
+#define SH_VEC_PARMS_NI_PORT_MASK                0x0000000000000002
+
+/*   SH_VEC_PARMS_ADDRESS                                               */
+/*   Description:  Address[37:6]                                        */
+#define SH_VEC_PARMS_ADDRESS_SHFT                3
+#define SH_VEC_PARMS_ADDRESS_MASK                0x00000007fffffff8
+
+/*   SH_VEC_PARMS_PIO_ID                                                */
+/*   Description:  PIO ID                                               */
+#define SH_VEC_PARMS_PIO_ID_SHFT                 35
+#define SH_VEC_PARMS_PIO_ID_MASK                 0x00003ff800000000
+
+/*   SH_VEC_PARMS_START                                                 */
+/*   Description:  Start                                                */
+#define SH_VEC_PARMS_START_SHFT                  62
+#define SH_VEC_PARMS_START_MASK                  0x4000000000000000
+
+/*   SH_VEC_PARMS_BUSY                                                  */
+/*   Description:  Busy                                                 */
+#define SH_VEC_PARMS_BUSY_SHFT                   63
+#define SH_VEC_PARMS_BUSY_MASK                   0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_ROUTE"                        */
+/*                     Vector Request Message Route                     */
+/* ==================================================================== */
+
+#define SH_VEC_ROUTE                             0x0000000110066100
+#define SH_VEC_ROUTE_MASK                        0xffffffffffffffff
+#define SH_VEC_ROUTE_INIT                        0x0000000000000000
+
+/*   SH_VEC_ROUTE_ROUTE                                                 */
+/*   Description:  Route                                                */
+#define SH_VEC_ROUTE_ROUTE_SHFT                  0
+#define SH_VEC_ROUTE_ROUTE_MASK                  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_CPU_PERM"                        */
+/*                    CPU MMR Access Permission Bits                    */
+/* ==================================================================== */
+
+#define SH_CPU_PERM                              0x0000000110060000
+#define SH_CPU_PERM_MASK                         0xffffffffffffffff
+#define SH_CPU_PERM_INIT                         0xffffffffffffffff
+
+/*   SH_CPU_PERM_ACCESS_BITS                                            */
+/*   Description:  Access Bits                                          */
+#define SH_CPU_PERM_ACCESS_BITS_SHFT             0
+#define SH_CPU_PERM_ACCESS_BITS_MASK             0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_CPU_PERM_OVR"                      */
+/*                  CPU MMR Access Permission Override                  */
+/* ==================================================================== */
+
+#define SH_CPU_PERM_OVR                          0x0000000110060080
+#define SH_CPU_PERM_OVR_MASK                     0xffffffffffffffff
+#define SH_CPU_PERM_OVR_INIT                     0x0000000000000000
+
+/*   SH_CPU_PERM_OVR_OVERRIDE                                           */
+/*   Description:  Override                                             */
+#define SH_CPU_PERM_OVR_OVERRIDE_SHFT            0
+#define SH_CPU_PERM_OVR_OVERRIDE_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_EXT_IO_PERM"                       */
+/*                External IO MMR Access Permission Bits                */
+/* ==================================================================== */
+
+#define SH_EXT_IO_PERM                           0x0000000110060100
+#define SH_EXT_IO_PERM_MASK                      0xffffffffffffffff
+#define SH_EXT_IO_PERM_INIT                      0x0000000000000000
+
+/*   SH_EXT_IO_PERM_ACCESS_BITS                                         */
+/*   Description:  Access Bits                                          */
+#define SH_EXT_IO_PERM_ACCESS_BITS_SHFT          0
+#define SH_EXT_IO_PERM_ACCESS_BITS_MASK          0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_EXT_IOI_ACCESS"                     */
+/*             External IO Interrupt Access Permission Bits             */
+/* ==================================================================== */
+
+#define SH_EXT_IOI_ACCESS                        0x0000000110060180
+#define SH_EXT_IOI_ACCESS_MASK                   0xffffffffffffffff
+#define SH_EXT_IOI_ACCESS_INIT                   0xffffffffffffffff
+
+/*   SH_EXT_IOI_ACCESS_ACCESS_BITS                                      */
+/*   Description:  Access Bits                                          */
+#define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT       0
+#define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_GC_FIL_CTRL"                       */
+/*                   SHub Global Clock Filter Control                   */
+/* ==================================================================== */
+
+#define SH_GC_FIL_CTRL                           0x0000000110060200
+#define SH_GC_FIL_CTRL_MASK                      0x03ff3ff3ff1fff1f
+#define SH_GC_FIL_CTRL_INIT                      0x0000000000000000
+
+/*   SH_GC_FIL_CTRL_OFFSET                                              */
+/*   Description:  Offset                                               */
+#define SH_GC_FIL_CTRL_OFFSET_SHFT               0
+#define SH_GC_FIL_CTRL_OFFSET_MASK               0x000000000000001f
+
+/*   SH_GC_FIL_CTRL_MASK_COUNTER                                        */
+/*   Description:  Mask Counter                                         */
+#define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT         8
+#define SH_GC_FIL_CTRL_MASK_COUNTER_MASK         0x00000000000fff00
+
+/*   SH_GC_FIL_CTRL_MASK_ENABLE                                         */
+/*   Description:  Mask Enable                                          */
+#define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT          20
+#define SH_GC_FIL_CTRL_MASK_ENABLE_MASK          0x0000000000100000
+
+/*   SH_GC_FIL_CTRL_DROPOUT_COUNTER                                     */
+/*   Description:  Dropout Counter                                      */
+#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT      24
+#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK      0x00000003ff000000
+
+/*   SH_GC_FIL_CTRL_DROPOUT_THRESH                                      */
+/*   Description:  Dropout threshold                                    */
+#define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT       36
+#define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK       0x00003ff000000000
+
+/*   SH_GC_FIL_CTRL_ERROR_COUNTER                                       */
+/*   Description:  Error counter                                        */
+#define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT        48
+#define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK        0x03ff000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_GC_SRC_CTRL"                       */
+/*                      SHub Global Clock Control                       */
+/* ==================================================================== */
+
+#define SH_GC_SRC_CTRL                           0x0000000110060280
+#define SH_GC_SRC_CTRL_MASK                      0x0000000313ff3ff1
+#define SH_GC_SRC_CTRL_INIT                      0x0000000100000000
+
+/*   SH_GC_SRC_CTRL_ENABLE_COUNTER                                      */
+/*   Description:  Enable Counter                                       */
+#define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT       0
+#define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK       0x0000000000000001
+
+/*   SH_GC_SRC_CTRL_MAX_COUNT                                           */
+/*   Description:  Max Count                                            */
+#define SH_GC_SRC_CTRL_MAX_COUNT_SHFT            4
+#define SH_GC_SRC_CTRL_MAX_COUNT_MASK            0x0000000000003ff0
+
+/*   SH_GC_SRC_CTRL_COUNTER                                             */
+/*   Description:  Counter                                              */
+#define SH_GC_SRC_CTRL_COUNTER_SHFT              16
+#define SH_GC_SRC_CTRL_COUNTER_MASK              0x0000000003ff0000
+
+/*   SH_GC_SRC_CTRL_TOGGLE_BIT                                          */
+/*   Description:  Toggle bit                                           */
+#define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT           28
+#define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK           0x0000000010000000
+
+/*   SH_GC_SRC_CTRL_SOURCE_SEL                                          */
+/*   Description:  Source select (0=ext., 1=Int., 2=SHUB)               */
+#define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT           32
+#define SH_GC_SRC_CTRL_SOURCE_SEL_MASK           0x0000000300000000
+
+/* ==================================================================== */
+/*                       Register "SH_HARD_RESET"                       */
+/*                           SHub Hard Reset                            */
+/* ==================================================================== */
+
+#define SH_HARD_RESET                            0x0000000110060300
+#define SH_HARD_RESET_MASK                       0x0000000000000001
+#define SH_HARD_RESET_INIT                       0x0000000000000000
+
+/*   SH_HARD_RESET_HARD_RESET                                           */
+/*   Description:  Hard Reset                                           */
+#define SH_HARD_RESET_HARD_RESET_SHFT            0
+#define SH_HARD_RESET_HARD_RESET_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                        Register "SH_IO_PERM"                         */
+/*                    II MMR Access Permission Bits                     */
+/* ==================================================================== */
+
+#define SH_IO_PERM                               0x0000000110060380
+#define SH_IO_PERM_MASK                          0xffffffffffffffff
+#define SH_IO_PERM_INIT                          0x0000000000000000
+
+/*   SH_IO_PERM_ACCESS_BITS                                             */
+/*   Description:  Access Bits                                          */
+#define SH_IO_PERM_ACCESS_BITS_SHFT              0
+#define SH_IO_PERM_ACCESS_BITS_MASK              0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_IOI_ACCESS"                       */
+/*                 II Interrupt Access Permission Bits                  */
+/* ==================================================================== */
+
+#define SH_IOI_ACCESS                            0x0000000110060400
+#define SH_IOI_ACCESS_MASK                       0xffffffffffffffff
+#define SH_IOI_ACCESS_INIT                       0xffffffffffffffff
+
+/*   SH_IOI_ACCESS_ACCESS_BITS                                          */
+/*   Description:  Access Bits                                          */
+#define SH_IOI_ACCESS_ACCESS_BITS_SHFT           0
+#define SH_IOI_ACCESS_ACCESS_BITS_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH_IPI_ACCESS                            0x0000000110060480
+#define SH_IPI_ACCESS_MASK                       0xffffffffffffffff
+#define SH_IPI_ACCESS_INIT                       0xffffffffffffffff
+
+/*   SH_IPI_ACCESS_ACCESS_BITS                                          */
+/*   Description:  Access Bits                                          */
+#define SH_IPI_ACCESS_ACCESS_BITS_SHFT           0
+#define SH_IPI_ACCESS_ACCESS_BITS_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_JTAG_CONFIG"                       */
+/*                       SHub JTAG configuration                        */
+/* ==================================================================== */
+
+#define SH_JTAG_CONFIG                           0x0000000110060500
+#define SH_JTAG_CONFIG_MASK                      0x00ffffffffffffff
+#define SH_JTAG_CONFIG_INIT                      0x0000000000000000
+
+/*   SH_JTAG_CONFIG_MD_CLK_SEL                                          */
+/*   Description:  Select divide freq of DRAMCLK                        */
+#define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT           0
+#define SH_JTAG_CONFIG_MD_CLK_SEL_MASK           0x0000000000000003
+
+/*   SH_JTAG_CONFIG_NI_CLK_SEL                                          */
+/*   Description:  Selects clock source for NICLK domain                */
+#define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT           2
+#define SH_JTAG_CONFIG_NI_CLK_SEL_MASK           0x0000000000000004
+
+/*   SH_JTAG_CONFIG_II_CLK_SEL                                          */
+/*   Description:  Selects clock source for IOCLK domain                */
+#define SH_JTAG_CONFIG_II_CLK_SEL_SHFT           3
+#define SH_JTAG_CONFIG_II_CLK_SEL_MASK           0x0000000000000018
+
+/*   SH_JTAG_CONFIG_WRT90_TARGET                                        */
+/*   Description:  wrt90_target                                         */
+#define SH_JTAG_CONFIG_WRT90_TARGET_SHFT         5
+#define SH_JTAG_CONFIG_WRT90_TARGET_MASK         0x000000000007ffe0
+
+/*   SH_JTAG_CONFIG_WRT90_OVERRIDER                                     */
+/*   Description:  wrt90_overrideR                                      */
+#define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT      19
+#define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK      0x0000000000080000
+
+/*   SH_JTAG_CONFIG_WRT90_OVERRIDE                                      */
+/*   Description:  wrt90_override                                       */
+#define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT       20
+#define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK       0x0000000000100000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY                                */
+/*   Description:  jtag_mci_reset_delay                                 */
+#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21
+#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_TARGET                                     */
+/*   Description:  jtag_mci_target                                      */
+#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT      25
+#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK      0x0000007ffe000000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE                                   */
+/*   Description:  jtag_mci_override                                    */
+#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT    39
+#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK    0x0000008000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH                                */
+/*   Description:  0=depth 8, 1=depth1                                  */
+#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40
+#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT                             */
+/*   Description:  Enable sampling of BINIT                             */
+#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41
+#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING                       */
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO                              */
+#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43
+#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE                          */
+/*   Description:  Output tristate control                              */
+#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48
+#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST                              */
+/*   Description:  Enables BIST                                         */
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_AUX                                      */
+/*   Description:  Enables BIST                                         */
+#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT       53
+#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK       0x0060000000000000
+
+/*   SH_JTAG_CONFIG_GTL_CONFIG_RE                                       */
+/*   Description:  Reference Enable selection for GTL io                */
+#define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT        55
+#define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK        0x0080000000000000
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+
+#define SH_SHUB_ID                               0x0000000110060580
+#define SH_SHUB_ID_MASK                          0x011f37ffffffffff
+#define SH_SHUB_ID_INIT                          0x0010300000000000
+
+/*   SH_SHUB_ID_FORCE1                                                  */
+/*   Description:  Must be 1                                            */
+#define SH_SHUB_ID_FORCE1_SHFT                   0
+#define SH_SHUB_ID_FORCE1_MASK                   0x0000000000000001
+
+/*   SH_SHUB_ID_MANUFACTURER                                            */
+/*   Description:  Manufacturer                                         */
+#define SH_SHUB_ID_MANUFACTURER_SHFT             1
+#define SH_SHUB_ID_MANUFACTURER_MASK             0x0000000000000ffe
+
+/*   SH_SHUB_ID_PART_NUMBER                                             */
+/*   Description:  Part Number                                          */
+#define SH_SHUB_ID_PART_NUMBER_SHFT              12
+#define SH_SHUB_ID_PART_NUMBER_MASK              0x000000000ffff000
+
+/*   SH_SHUB_ID_REVISION                                                */
+/*   Description:  Revision                                             */
+#define SH_SHUB_ID_REVISION_SHFT                 28
+#define SH_SHUB_ID_REVISION_MASK                 0x00000000f0000000
+
+/*   SH_SHUB_ID_NODE_ID                                                 */
+/*   Description:  Node Identification                                  */
+#define SH_SHUB_ID_NODE_ID_SHFT                  32
+#define SH_SHUB_ID_NODE_ID_MASK                  0x000007ff00000000
+
+/*   SH_SHUB_ID_SHARING_MODE                                            */
+/*   Description:  Sharing mode (Coherency Domain Size)                 */
+#define SH_SHUB_ID_SHARING_MODE_SHFT             44
+#define SH_SHUB_ID_SHARING_MODE_MASK             0x0000300000000000
+
+/*   SH_SHUB_ID_NODES_PER_BIT                                           */
+/*   Description:  Nodes per bit definition for MMR access              */
+#define SH_SHUB_ID_NODES_PER_BIT_SHFT            48
+#define SH_SHUB_ID_NODES_PER_BIT_MASK            0x001f000000000000
+
+/*   SH_SHUB_ID_NI_PORT                                                 */
+/*   Description:  NI port of vector reference, 0 = NI0, 1 = NI1        */
+#define SH_SHUB_ID_NI_PORT_SHFT                  56
+#define SH_SHUB_ID_NI_PORT_MASK                  0x0100000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT0"                     */
+/*         Shubs 0 - 63 Present. Used for invalidate generation         */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT0                        0x0000000110060600
+#define SH_SHUBS_PRESENT0_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT0_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT0_SHUBS_PRESENT0                                   */
+/*   Description:  Shubs 0 - 63 Present configuration                   */
+#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT    0
+#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT1"                     */
+/*        Shubs 64 - 127 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT1                        0x0000000110060680
+#define SH_SHUBS_PRESENT1_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT1_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT1_SHUBS_PRESENT1                                   */
+/*   Description:  Shubs 64 - 127 Present configuration                 */
+#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT    0
+#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT2"                     */
+/*       Shubs 128 - 191 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT2                        0x0000000110060700
+#define SH_SHUBS_PRESENT2_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT2_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT2_SHUBS_PRESENT2                                   */
+/*   Description:  Shubs 128 - 191 Present configuration                */
+#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT    0
+#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT3"                     */
+/*       Shubs 192 - 255 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT3                        0x0000000110060780
+#define SH_SHUBS_PRESENT3_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT3_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT3_SHUBS_PRESENT3                                   */
+/*   Description:  Shubs 192 - 255 Present configuration                */
+#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT    0
+#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_SOFT_RESET"                       */
+/*                           SHub Soft Reset                            */
+/* ==================================================================== */
+
+#define SH_SOFT_RESET                            0x0000000110060800
+#define SH_SOFT_RESET_MASK                       0x0000000000000001
+#define SH_SOFT_RESET_INIT                       0x0000000000000000
+
+/*   SH_SOFT_RESET_SOFT_RESET                                           */
+/*   Description:  Soft Reset                                           */
+#define SH_SOFT_RESET_SOFT_RESET_SHFT            0
+#define SH_SOFT_RESET_SOFT_RESET_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                      Register "SH_FIRST_ERROR"                       */
+/*                    Shub Global First Error Flags                     */
+/* ==================================================================== */
+
+#define SH_FIRST_ERROR                           0x0000000110071000
+#define SH_FIRST_ERROR_MASK                      0x000000000007ffff
+#define SH_FIRST_ERROR_INIT                      0x0000000000000000
+
+/*   SH_FIRST_ERROR_FIRST_ERROR                                         */
+/*   Description:  Chiplet with first error                             */
+#define SH_FIRST_ERROR_FIRST_ERROR_SHFT          0
+#define SH_FIRST_ERROR_FIRST_ERROR_MASK          0x000000000007ffff
+
+/* ==================================================================== */
+/*                    Register "SH_II_HW_TIME_STAMP"                    */
+/*                     II hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_II_HW_TIME_STAMP                      0x0000000110071080
+#define SH_II_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_II_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_II_HW_TIME_STAMP_TIME                                           */
+/*   Description:  II hardware error time stamp                         */
+#define SH_II_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_II_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_II_HW_TIME_STAMP_VALID                                          */
+/*   Description:  II hardware error time stamp valid                   */
+#define SH_II_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_II_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_LB_HW_TIME_STAMP"                    */
+/*                     LB hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_LB_HW_TIME_STAMP                      0x0000000110071100
+#define SH_LB_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_LB_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_LB_HW_TIME_STAMP_TIME                                           */
+/*   Description:  LB hardware error time stamp                         */
+#define SH_LB_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_LB_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_LB_HW_TIME_STAMP_VALID                                          */
+/*   Description:  LB hardware error time stamp valid                   */
+#define SH_LB_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_LB_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_COR_TIME_STAMP"                    */
+/*                   MD correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_MD_COR_TIME_STAMP                     0x0000000110071180
+#define SH_MD_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_MD_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_MD_COR_TIME_STAMP_TIME                                          */
+/*   Description:  MD correctable error time stamp                      */
+#define SH_MD_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_MD_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_MD_COR_TIME_STAMP_VALID                                         */
+/*   Description:  MD correctable error time stamp valid                */
+#define SH_MD_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_MD_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_HW_TIME_STAMP"                    */
+/*                     MD hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_MD_HW_TIME_STAMP                      0x0000000110071200
+#define SH_MD_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_MD_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_MD_HW_TIME_STAMP_TIME                                           */
+/*   Description:  MD hardware error time stamp                         */
+#define SH_MD_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_MD_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_MD_HW_TIME_STAMP_VALID                                          */
+/*   Description:  MD hardware error time stamp valid                   */
+#define SH_MD_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_MD_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_UNCOR_TIME_STAMP"                   */
+/*                  MD uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_MD_UNCOR_TIME_STAMP                   0x0000000110071280
+#define SH_MD_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_MD_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_MD_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  MD uncorrectable error time stamp                    */
+#define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_MD_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_MD_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  MD uncorrectable error time stamp valid              */
+#define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_MD_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_COR_TIME_STAMP"                    */
+/*                   PI correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_PI_COR_TIME_STAMP                     0x0000000110071300
+#define SH_PI_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_PI_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_PI_COR_TIME_STAMP_TIME                                          */
+/*   Description:  PI correctable error time stamp                      */
+#define SH_PI_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_PI_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_PI_COR_TIME_STAMP_VALID                                         */
+/*   Description:  PI correctable error time stamp valid                */
+#define SH_PI_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_PI_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_PI_HW_TIME_STAMP"                    */
+/*                     PI hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_PI_HW_TIME_STAMP                      0x0000000110071380
+#define SH_PI_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_PI_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_PI_HW_TIME_STAMP_TIME                                           */
+/*   Description:  PI hardware error time stamp                         */
+#define SH_PI_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_PI_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_PI_HW_TIME_STAMP_VALID                                          */
+/*   Description:  PI hardware error time stamp valid                   */
+#define SH_PI_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_PI_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_UNCOR_TIME_STAMP"                   */
+/*                  PI uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_PI_UNCOR_TIME_STAMP                   0x0000000110071400
+#define SH_PI_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_PI_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_PI_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  PI uncorrectable error time stamp                    */
+#define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_PI_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_PI_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  PI uncorrectable error time stamp valid              */
+#define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_PI_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_TIME_STAMP"                  */
+/*                      Proc 0 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_TIME_STAMP                  0x0000000110071480
+#define SH_PROC0_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC0_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 0 advisory time stamp                      */
+#define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC0_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC0_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 0 advisory time stamp valid                */
+#define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC0_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_TIME_STAMP"                  */
+/*                       Proc 0 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_TIME_STAMP                  0x0000000110071500
+#define SH_PROC0_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC0_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 0 error time stamp                         */
+#define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC0_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC0_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 0 error time stamp valid                   */
+#define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC0_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_TIME_STAMP"                  */
+/*                      Proc 1 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_TIME_STAMP                  0x0000000110071580
+#define SH_PROC1_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC1_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 1 advisory time stamp                      */
+#define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC1_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC1_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 1 advisory time stamp valid                */
+#define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC1_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_TIME_STAMP"                  */
+/*                       Proc 1 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_TIME_STAMP                  0x0000000110071600
+#define SH_PROC1_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC1_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 1 error time stamp                         */
+#define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC1_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC1_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 1 error time stamp valid                   */
+#define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC1_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_TIME_STAMP"                  */
+/*                      Proc 2 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_TIME_STAMP                  0x0000000110071680
+#define SH_PROC2_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC2_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 2 advisory time stamp                      */
+#define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC2_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC2_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 2 advisory time stamp valid                */
+#define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC2_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_TIME_STAMP"                  */
+/*                       Proc 2 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_TIME_STAMP                  0x0000000110071700
+#define SH_PROC2_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC2_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 2 error time stamp                         */
+#define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC2_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC2_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 2 error time stamp valid                   */
+#define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC2_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_TIME_STAMP"                  */
+/*                      Proc 3 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_TIME_STAMP                  0x0000000110071780
+#define SH_PROC3_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC3_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 3 advisory time stamp                      */
+#define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC3_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC3_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 3 advisory time stamp valid                */
+#define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC3_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_TIME_STAMP"                  */
+/*                       Proc 3 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_TIME_STAMP                  0x0000000110071800
+#define SH_PROC3_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC3_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 3 error time stamp                         */
+#define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC3_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC3_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 3 error time stamp valid                   */
+#define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC3_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_COR_TIME_STAMP"                    */
+/*                   XN correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_XN_COR_TIME_STAMP                     0x0000000110071880
+#define SH_XN_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_XN_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_XN_COR_TIME_STAMP_TIME                                          */
+/*   Description:  XN correctable error time stamp                      */
+#define SH_XN_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_XN_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_XN_COR_TIME_STAMP_VALID                                         */
+/*   Description:  XN correctable error time stamp valid                */
+#define SH_XN_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_XN_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_HW_TIME_STAMP"                    */
+/*                     XN hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_XN_HW_TIME_STAMP                      0x0000000110071900
+#define SH_XN_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_XN_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_XN_HW_TIME_STAMP_TIME                                           */
+/*   Description:  XN hardware error time stamp                         */
+#define SH_XN_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_XN_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_XN_HW_TIME_STAMP_VALID                                          */
+/*   Description:  XN hardware error time stamp valid                   */
+#define SH_XN_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_XN_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XN_UNCOR_TIME_STAMP"                   */
+/*                  XN uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_XN_UNCOR_TIME_STAMP                   0x0000000110071980
+#define SH_XN_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_XN_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_XN_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  XN uncorrectable error time stamp                    */
+#define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_XN_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_XN_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  XN uncorrectable error time stamp valid              */
+#define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_XN_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_DEBUG_PORT"                       */
+/*                           SHub Debug Port                            */
+/* ==================================================================== */
+
+#define SH_DEBUG_PORT                            0x0000000110072000
+#define SH_DEBUG_PORT_MASK                       0x00000000ffffffff
+#define SH_DEBUG_PORT_INIT                       0x0000000000000000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE0                                        */
+/*   Description:  Debug port nibble 0                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT         0
+#define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK         0x000000000000000f
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE1                                        */
+/*   Description:  Debug port nibble 1                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT         4
+#define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK         0x00000000000000f0
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE2                                        */
+/*   Description:  Debug port nibble 2                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT         8
+#define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK         0x0000000000000f00
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE3                                        */
+/*   Description:  Debug port nibble 3                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT         12
+#define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK         0x000000000000f000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE4                                        */
+/*   Description:  Debug port nibble 4                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT         16
+#define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK         0x00000000000f0000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE5                                        */
+/*   Description:  Debug port nibble 5                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT         20
+#define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK         0x0000000000f00000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE6                                        */
+/*   Description:  Debug port nibble 6                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT         24
+#define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK         0x000000000f000000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE7                                        */
+/*   Description:  Debug port nibble 7                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT         28
+#define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK         0x00000000f0000000
+
+/* ==================================================================== */
+/*                     Register "SH_II_DEBUG_DATA"                      */
+/*                            II Debug Data                             */
+/* ==================================================================== */
+
+#define SH_II_DEBUG_DATA                         0x0000000110072080
+#define SH_II_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_II_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_II_DEBUG_DATA_II_DATA                                           */
+/*   Description:  II debug data                                        */
+#define SH_II_DEBUG_DATA_II_DATA_SHFT            0
+#define SH_II_DEBUG_DATA_II_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_II_WRAP_DEBUG_DATA"                   */
+/*                      SHub II Wrapper Debug Data                      */
+/* ==================================================================== */
+
+#define SH_II_WRAP_DEBUG_DATA                    0x0000000110072100
+#define SH_II_WRAP_DEBUG_DATA_MASK               0x00000000ffffffff
+#define SH_II_WRAP_DEBUG_DATA_INIT               0x0000000000000000
+
+/*   SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA                                 */
+/*   Description:  II wrapper debug data                                */
+#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT  0
+#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_LB_DEBUG_DATA"                      */
+/*                          SHub LB Debug Data                          */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_DATA                         0x0000000110072180
+#define SH_LB_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_LB_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_LB_DEBUG_DATA_LB_DATA                                           */
+/*   Description:  LB debug data                                        */
+#define SH_LB_DEBUG_DATA_LB_DATA_SHFT            0
+#define SH_LB_DEBUG_DATA_LB_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_MD_DEBUG_DATA"                      */
+/*                          SHub MD Debug Data                          */
+/* ==================================================================== */
+
+#define SH_MD_DEBUG_DATA                         0x0000000110072200
+#define SH_MD_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_MD_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_MD_DEBUG_DATA_MD_DATA                                           */
+/*   Description:  MD debug data                                        */
+#define SH_MD_DEBUG_DATA_MD_DATA_SHFT            0
+#define SH_MD_DEBUG_DATA_MD_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_PI_DEBUG_DATA"                      */
+/*                          SHub PI Debug Data                          */
+/* ==================================================================== */
+
+#define SH_PI_DEBUG_DATA                         0x0000000110072280
+#define SH_PI_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_PI_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_PI_DEBUG_DATA_PI_DATA                                           */
+/*   Description:  PI Debug Data                                        */
+#define SH_PI_DEBUG_DATA_PI_DATA_SHFT            0
+#define SH_PI_DEBUG_DATA_PI_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_XN_DEBUG_DATA"                      */
+/*                          SHub XN Debug Data                          */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_DATA                         0x0000000110072300
+#define SH_XN_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_XN_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_XN_DEBUG_DATA_XN_DATA                                           */
+/*   Description:  XN debug data                                        */
+#define SH_XN_DEBUG_DATA_XN_DATA_SHFT            0
+#define SH_XN_DEBUG_DATA_XN_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_ARMED_STATE"                     */
+/*                Trigger sequencing facility arm state                 */
+/* ==================================================================== */
+
+#define SH_TSF_ARMED_STATE                       0x0000000110073000
+#define SH_TSF_ARMED_STATE_MASK                  0x00000000000000ff
+#define SH_TSF_ARMED_STATE_INIT                  0x0000000000000000
+
+/*   SH_TSF_ARMED_STATE_STATE                                           */
+/*   Description:  Trigger sequencing facility armed state              */
+#define SH_TSF_ARMED_STATE_STATE_SHFT            0
+#define SH_TSF_ARMED_STATE_STATE_MASK            0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_COUNTER_VALUE"                    */
+/*              Trigger sequencing facility counter value               */
+/* ==================================================================== */
+
+#define SH_TSF_COUNTER_VALUE                     0x0000000110073080
+#define SH_TSF_COUNTER_VALUE_MASK                0xffffffffffffffff
+#define SH_TSF_COUNTER_VALUE_INIT                0x0000000000000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_32                                      */
+/*   Description:  Trigger sequencing facility counter 32               */
+#define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT       0
+#define SH_TSF_COUNTER_VALUE_COUNT_32_MASK       0x00000000ffffffff
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_16                                      */
+/*   Description:  Trigger sequencing facility counter 16               */
+#define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT       32
+#define SH_TSF_COUNTER_VALUE_COUNT_16_MASK       0x0000ffff00000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_8B                                      */
+/*   Description:  Trigger sequencing facility counter 8b               */
+#define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT       48
+#define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK       0x00ff000000000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_8A                                      */
+/*   Description:  Trigger sequencing facility counter 8a               */
+#define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT       56
+#define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK       0xff00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_TRIGGERED_STATE"                   */
+/*             Trigger sequencing facility triggered state              */
+/* ==================================================================== */
+
+#define SH_TSF_TRIGGERED_STATE                   0x0000000110073100
+#define SH_TSF_TRIGGERED_STATE_MASK              0x00000000000000ff
+#define SH_TSF_TRIGGERED_STATE_INIT              0x0000000000000000
+
+/*   SH_TSF_TRIGGERED_STATE_STATE                                       */
+/*   Description:  Trigger sequencing facility triggered state          */
+#define SH_TSF_TRIGGERED_STATE_STATE_SHFT        0
+#define SH_TSF_TRIGGERED_STATE_STATE_MASK        0x00000000000000ff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RDDATA"                       */
+/*                      Vector Reply Message Data                       */
+/* ==================================================================== */
+
+#define SH_VEC_RDDATA                            0x0000000110074000
+#define SH_VEC_RDDATA_MASK                       0xffffffffffffffff
+#define SH_VEC_RDDATA_INIT                       0x0000000000000000
+
+/*   SH_VEC_RDDATA_DATA                                                 */
+/*   Description:  Data                                                 */
+#define SH_VEC_RDDATA_DATA_SHFT                  0
+#define SH_VEC_RDDATA_DATA_MASK                  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RETURN"                       */
+/*                  Vector Reply Message Return Route                   */
+/* ==================================================================== */
+
+#define SH_VEC_RETURN                            0x0000000110074080
+#define SH_VEC_RETURN_MASK                       0xffffffffffffffff
+#define SH_VEC_RETURN_INIT                       0x0000000000000000
+
+/*   SH_VEC_RETURN_ROUTE                                                */
+/*   Description:  Route                                                */
+#define SH_VEC_RETURN_ROUTE_SHFT                 0
+#define SH_VEC_RETURN_ROUTE_MASK                 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_STATUS"                       */
+/*                     Vector Reply Message Status                      */
+/* ==================================================================== */
+
+#define SH_VEC_STATUS                            0x0000000110074100
+#define SH_VEC_STATUS_MASK                       0xcfffffffffffffff
+#define SH_VEC_STATUS_INIT                       0x0000000000000000
+
+/*   SH_VEC_STATUS_TYPE                                                 */
+/*   Description:  Type                                                 */
+#define SH_VEC_STATUS_TYPE_SHFT                  0
+#define SH_VEC_STATUS_TYPE_MASK                  0x0000000000000007
+
+/*   SH_VEC_STATUS_ADDRESS                                              */
+/*   Description:  Address                                              */
+#define SH_VEC_STATUS_ADDRESS_SHFT               3
+#define SH_VEC_STATUS_ADDRESS_MASK               0x00000007fffffff8
+
+/*   SH_VEC_STATUS_PIO_ID                                               */
+/*   Description:  PIO ID                                               */
+#define SH_VEC_STATUS_PIO_ID_SHFT                35
+#define SH_VEC_STATUS_PIO_ID_MASK                0x00003ff800000000
+
+/*   SH_VEC_STATUS_SOURCE                                               */
+/*   Description:  Source                                               */
+#define SH_VEC_STATUS_SOURCE_SHFT                46
+#define SH_VEC_STATUS_SOURCE_MASK                0x0fffc00000000000
+
+/*   SH_VEC_STATUS_OVERRUN                                              */
+/*   Description:  Overrun                                              */
+#define SH_VEC_STATUS_OVERRUN_SHFT               62
+#define SH_VEC_STATUS_OVERRUN_MASK               0x4000000000000000
+
+/*   SH_VEC_STATUS_STATUS_VALID                                         */
+/*   Description:  Status_Valid                                         */
+#define SH_VEC_STATUS_STATUS_VALID_SHFT          63
+#define SH_VEC_STATUS_STATUS_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_VEC_STATUS_ALIAS"                    */
+/*                  Vector Reply Message Status Alias                   */
+/* ==================================================================== */
+
+#define SH_VEC_STATUS_ALIAS                      0x0000000110074108
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT0_CONTROL"               */
+/*                    Performance Counter 0 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT0_CONTROL            0x0000000110080000
+#define SH_PERFORMANCE_COUNT0_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT0_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 0 up stimulus                                */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 0 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 0 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE                              */
+/*   Description:  Counter 0 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 0 down stimulus                              */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 0 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 0 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE                              */
+/*   Description:  Counter 0 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 0 enable increment                           */
+#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 0 enable decrement                           */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 0 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT1_CONTROL"               */
+/*                    Performance Counter 1 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT1_CONTROL            0x0000000110090000
+#define SH_PERFORMANCE_COUNT1_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT1_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 1 up stimulus                                */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 1 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 1 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE                              */
+/*   Description:  Counter 1 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 1 down stimulus                              */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 1 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 1 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE                              */
+/*   Description:  Counter 1 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 1 enable increment                           */
+#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 1 enable decrement                           */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 1 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT2_CONTROL"               */
+/*                    Performance Counter 2 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT2_CONTROL            0x00000001100a0000
+#define SH_PERFORMANCE_COUNT2_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT2_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 2 up stimulus                                */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 2 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 2 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE                              */
+/*   Description:  Counter 2 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 2 down stimulus                              */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 2 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 2 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE                              */
+/*   Description:  Counter 2 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 2 enable increment                           */
+#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 2 enable decrement                           */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 2 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT3_CONTROL"               */
+/*                    Performance Counter 3 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT3_CONTROL            0x00000001100b0000
+#define SH_PERFORMANCE_COUNT3_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT3_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 3 up stimulus                                */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 3 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 3 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE                              */
+/*   Description:  Counter 3 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 3 down stimulus                              */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 3 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 3 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE                              */
+/*   Description:  Counter 3 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 3 enable increment                           */
+#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 3 enable decrement                           */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 3 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT4_CONTROL"               */
+/*                    Performance Counter 4 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT4_CONTROL            0x00000001100c0000
+#define SH_PERFORMANCE_COUNT4_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT4_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 4 up stimulus                                */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 4 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 4 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE                              */
+/*   Description:  Counter 4 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 4 down stimulus                              */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 4 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 4 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE                              */
+/*   Description:  Counter 4 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 4 enable increment                           */
+#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 4 enable decrement                           */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 4 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT5_CONTROL"               */
+/*                    Performance Counter 5 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT5_CONTROL            0x00000001100d0000
+#define SH_PERFORMANCE_COUNT5_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT5_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 5 up stimulus                                */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 5 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 5 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE                              */
+/*   Description:  Counter 5 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 5 down stimulus                              */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 5 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 5 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE                              */
+/*   Description:  Counter 5 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 5 enable increment                           */
+#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 5 enable decrement                           */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 5 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT6_CONTROL"               */
+/*                    Performance Counter 6 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT6_CONTROL            0x00000001100e0000
+#define SH_PERFORMANCE_COUNT6_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT6_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 6 up stimulus                                */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 6 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 6 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE                              */
+/*   Description:  Counter 6 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 6 down stimulus                              */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 6 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 6 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE                              */
+/*   Description:  Counter 6 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 6 enable increment                           */
+#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 6 enable decrement                           */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 6 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT7_CONTROL"               */
+/*                    Performance Counter 7 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT7_CONTROL            0x00000001100f0000
+#define SH_PERFORMANCE_COUNT7_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT7_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 7 up stimulus                                */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 7 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 7 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE                              */
+/*   Description:  Counter 7 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 7 down stimulus                              */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 7 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 7 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE                              */
+/*   Description:  Counter 7 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 7 enable increment                           */
+#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 7 enable decrement                           */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 7 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_DN_CONTROL"                   */
+/*                     Profile Counter Down Control                     */
+/* ==================================================================== */
+
+#define SH_PROFILE_DN_CONTROL                    0x0000000110100000
+#define SH_PROFILE_DN_CONTROL_MASK               0x00000000000000ff
+#define SH_PROFILE_DN_CONTROL_INIT               0x00000000000000b8
+
+/*   SH_PROFILE_DN_CONTROL_STIMULUS                                     */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT      0
+#define SH_PROFILE_DN_CONTROL_STIMULUS_MASK      0x000000000000001f
+
+/*   SH_PROFILE_DN_CONTROL_EVENT                                        */
+/*   Description:  Counter event select (1-greater than, 0-equal)       */
+#define SH_PROFILE_DN_CONTROL_EVENT_SHFT         5
+#define SH_PROFILE_DN_CONTROL_EVENT_MASK         0x0000000000000020
+
+/*   SH_PROFILE_DN_CONTROL_POLARITY                                     */
+/*   Description:  Counter polarity select (1-negative edge, 0-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_DN_CONTROL_POLARITY_SHFT      6
+#define SH_PROFILE_DN_CONTROL_POLARITY_MASK      0x0000000000000040
+
+/*   SH_PROFILE_DN_CONTROL_MODE                                         */
+/*   Description:  Counter mode select (1-internal, 0-external)         */
+#define SH_PROFILE_DN_CONTROL_MODE_SHFT          7
+#define SH_PROFILE_DN_CONTROL_MODE_MASK          0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_PROFILE_PEAK_CONTROL"                  */
+/*                     Profile Counter Peak Control                     */
+/* ==================================================================== */
+
+#define SH_PROFILE_PEAK_CONTROL                  0x0000000110100080
+#define SH_PROFILE_PEAK_CONTROL_MASK             0x0000000000000068
+#define SH_PROFILE_PEAK_CONTROL_INIT             0x0000000000000060
+
+/*   SH_PROFILE_PEAK_CONTROL_STIMULUS                                   */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT    3
+#define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK    0x0000000000000008
+
+/*   SH_PROFILE_PEAK_CONTROL_EVENT                                      */
+/*   Description:  Counter event select (0-greater than, 1-equal)       */
+#define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT       5
+#define SH_PROFILE_PEAK_CONTROL_EVENT_MASK       0x0000000000000020
+
+/*   SH_PROFILE_PEAK_CONTROL_POLARITY                                   */
+/*   Description:  Counter polarity select (0-negative edge, 1-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT    6
+#define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK    0x0000000000000040
+
+/* ==================================================================== */
+/*                     Register "SH_PROFILE_RANGE"                      */
+/*                        Profile Counter Range                         */
+/* ==================================================================== */
+
+#define SH_PROFILE_RANGE                         0x0000000110100100
+#define SH_PROFILE_RANGE_MASK                    0xffffffffffffffff
+#define SH_PROFILE_RANGE_INIT                    0x0000000000000000
+
+/*   SH_PROFILE_RANGE_RANGE0                                            */
+/*   Description:  Profiling range 0                                    */
+#define SH_PROFILE_RANGE_RANGE0_SHFT             0
+#define SH_PROFILE_RANGE_RANGE0_MASK             0x00000000000000ff
+
+/*   SH_PROFILE_RANGE_RANGE1                                            */
+/*   Description:  Profiling range 1                                    */
+#define SH_PROFILE_RANGE_RANGE1_SHFT             8
+#define SH_PROFILE_RANGE_RANGE1_MASK             0x000000000000ff00
+
+/*   SH_PROFILE_RANGE_RANGE2                                            */
+/*   Description:  Profiling range 2                                    */
+#define SH_PROFILE_RANGE_RANGE2_SHFT             16
+#define SH_PROFILE_RANGE_RANGE2_MASK             0x0000000000ff0000
+
+/*   SH_PROFILE_RANGE_RANGE3                                            */
+/*   Description:  Profiling range 3                                    */
+#define SH_PROFILE_RANGE_RANGE3_SHFT             24
+#define SH_PROFILE_RANGE_RANGE3_MASK             0x00000000ff000000
+
+/*   SH_PROFILE_RANGE_RANGE4                                            */
+/*   Description:  Profiling range 4                                    */
+#define SH_PROFILE_RANGE_RANGE4_SHFT             32
+#define SH_PROFILE_RANGE_RANGE4_MASK             0x000000ff00000000
+
+/*   SH_PROFILE_RANGE_RANGE5                                            */
+/*   Description:  Profiling range 5                                    */
+#define SH_PROFILE_RANGE_RANGE5_SHFT             40
+#define SH_PROFILE_RANGE_RANGE5_MASK             0x0000ff0000000000
+
+/*   SH_PROFILE_RANGE_RANGE6                                            */
+/*   Description:  Profiling range 6                                    */
+#define SH_PROFILE_RANGE_RANGE6_SHFT             48
+#define SH_PROFILE_RANGE_RANGE6_MASK             0x00ff000000000000
+
+/*   SH_PROFILE_RANGE_RANGE7                                            */
+/*   Description:  Profiling range 7                                    */
+#define SH_PROFILE_RANGE_RANGE7_SHFT             56
+#define SH_PROFILE_RANGE_RANGE7_MASK             0xff00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_UP_CONTROL"                   */
+/*                      Profile Counter Up Control                      */
+/* ==================================================================== */
+
+#define SH_PROFILE_UP_CONTROL                    0x0000000110100180
+#define SH_PROFILE_UP_CONTROL_MASK               0x00000000000000ff
+#define SH_PROFILE_UP_CONTROL_INIT               0x00000000000000b8
+
+/*   SH_PROFILE_UP_CONTROL_STIMULUS                                     */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT      0
+#define SH_PROFILE_UP_CONTROL_STIMULUS_MASK      0x000000000000001f
+
+/*   SH_PROFILE_UP_CONTROL_EVENT                                        */
+/*   Description:  Counter event select (1-greater than, 0-equal)       */
+#define SH_PROFILE_UP_CONTROL_EVENT_SHFT         5
+#define SH_PROFILE_UP_CONTROL_EVENT_MASK         0x0000000000000020
+
+/*   SH_PROFILE_UP_CONTROL_POLARITY                                     */
+/*   Description:  Counter polarity select (1-negative edge, 0-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_UP_CONTROL_POLARITY_SHFT      6
+#define SH_PROFILE_UP_CONTROL_POLARITY_MASK      0x0000000000000040
+
+/*   SH_PROFILE_UP_CONTROL_MODE                                         */
+/*   Description:  Counter mode select (1-internal, 0-external)         */
+#define SH_PROFILE_UP_CONTROL_MODE_SHFT          7
+#define SH_PROFILE_UP_CONTROL_MODE_MASK          0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER0"                  */
+/*                        Performance Counter 0                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER0                  0x0000000110110000
+#define SH_PERFORMANCE_COUNTER0_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER0_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER0_COUNT                                      */
+/*   Description:  Counter 0                                            */
+#define SH_PERFORMANCE_COUNTER0_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER0_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER1"                  */
+/*                        Performance Counter 1                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER1                  0x0000000110120000
+#define SH_PERFORMANCE_COUNTER1_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER1_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER1_COUNT                                      */
+/*   Description:  Counter 1                                            */
+#define SH_PERFORMANCE_COUNTER1_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER1_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER2"                  */
+/*                        Performance Counter 2                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER2                  0x0000000110130000
+#define SH_PERFORMANCE_COUNTER2_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER2_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER2_COUNT                                      */
+/*   Description:  Counter 2                                            */
+#define SH_PERFORMANCE_COUNTER2_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER2_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER3"                  */
+/*                        Performance Counter 3                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER3                  0x0000000110140000
+#define SH_PERFORMANCE_COUNTER3_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER3_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER3_COUNT                                      */
+/*   Description:  Counter 3                                            */
+#define SH_PERFORMANCE_COUNTER3_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER3_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER4"                  */
+/*                        Performance Counter 4                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER4                  0x0000000110150000
+#define SH_PERFORMANCE_COUNTER4_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER4_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER4_COUNT                                      */
+/*   Description:  Counter 4                                            */
+#define SH_PERFORMANCE_COUNTER4_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER4_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER5"                  */
+/*                        Performance Counter 5                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER5                  0x0000000110160000
+#define SH_PERFORMANCE_COUNTER5_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER5_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER5_COUNT                                      */
+/*   Description:  Counter 5                                            */
+#define SH_PERFORMANCE_COUNTER5_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER5_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER6"                  */
+/*                        Performance Counter 6                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER6                  0x0000000110170000
+#define SH_PERFORMANCE_COUNTER6_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER6_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER6_COUNT                                      */
+/*   Description:  Counter 6                                            */
+#define SH_PERFORMANCE_COUNTER6_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER6_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER7"                  */
+/*                        Performance Counter 7                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER7                  0x0000000110180000
+#define SH_PERFORMANCE_COUNTER7_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER7_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER7_COUNT                                      */
+/*   Description:  Counter 7                                            */
+#define SH_PERFORMANCE_COUNTER7_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER7_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_PROFILE_COUNTER"                     */
+/*                           Profile Counter                            */
+/* ==================================================================== */
+
+#define SH_PROFILE_COUNTER                       0x0000000110190000
+#define SH_PROFILE_COUNTER_MASK                  0x00000000000000ff
+#define SH_PROFILE_COUNTER_INIT                  0x0000000000000000
+
+/*   SH_PROFILE_COUNTER_COUNTER                                         */
+/*   Description:  Counter Value                                        */
+#define SH_PROFILE_COUNTER_COUNTER_SHFT          0
+#define SH_PROFILE_COUNTER_COUNTER_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                      Register "SH_PROFILE_PEAK"                      */
+/*                         Profile Peak Counter                         */
+/* ==================================================================== */
+
+#define SH_PROFILE_PEAK                          0x0000000110190080
+#define SH_PROFILE_PEAK_MASK                     0x00000000000000ff
+#define SH_PROFILE_PEAK_INIT                     0x0000000000000000
+
+/*   SH_PROFILE_PEAK_COUNTER                                            */
+/*   Description:  Counter Value                                        */
+#define SH_PROFILE_PEAK_COUNTER_SHFT             0
+#define SH_PROFILE_PEAK_COUNTER_MASK             0x00000000000000ff
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_0"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#define SH_PTC_0                                 0x00000001101a0000
+#define SH_PTC_0_MASK                            0x80000000fffffffd
+#define SH_PTC_0_INIT                            0x0000000000000000
+
+/*   SH_PTC_0_A                                                         */
+/*   Description:  Type                                                 */
+#define SH_PTC_0_A_SHFT                          0
+#define SH_PTC_0_A_MASK                          0x0000000000000001
+
+/*   SH_PTC_0_PS                                                        */
+/*   Description:  Page Size                                            */
+#define SH_PTC_0_PS_SHFT                         2
+#define SH_PTC_0_PS_MASK                         0x00000000000000fc
+
+/*   SH_PTC_0_RID                                                       */
+/*   Description:  Region ID                                            */
+#define SH_PTC_0_RID_SHFT                        8
+#define SH_PTC_0_RID_MASK                        0x00000000ffffff00
+
+/*   SH_PTC_0_START                                                     */
+/*   Description:  Start                                                */
+#define SH_PTC_0_START_SHFT                      63
+#define SH_PTC_0_START_MASK                      0x8000000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_1"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#define SH_PTC_1                                 0x00000001101a0080
+#define SH_PTC_1_MASK                            0x9ffffffffffff000
+#define SH_PTC_1_INIT                            0x0000000000000000
+
+/*   SH_PTC_1_VPN                                                       */
+/*   Description:  Virtual page number                                  */
+#define SH_PTC_1_VPN_SHFT                        12
+#define SH_PTC_1_VPN_MASK                        0x1ffffffffffff000
+
+/*   SH_PTC_1_START                                                     */
+/*   Description:  PTC_1 Start                                          */
+#define SH_PTC_1_START_SHFT                      63
+#define SH_PTC_1_START_MASK                      0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_PTC_PARMS"                        */
+/*                       PTC Time-out parmaeters                        */
+/* ==================================================================== */
+
+#define SH_PTC_PARMS                             0x00000001101a0100
+#define SH_PTC_PARMS_MASK                        0x0000000fffffffff
+#define SH_PTC_PARMS_INIT                        0x00000007ffffffff
+
+/*   SH_PTC_PARMS_PTC_TO_WRAP                                           */
+/*   Description:  PTC time-out period                                  */
+#define SH_PTC_PARMS_PTC_TO_WRAP_SHFT            0
+#define SH_PTC_PARMS_PTC_TO_WRAP_MASK            0x0000000000ffffff
+
+/*   SH_PTC_PARMS_PTC_TO_VAL                                            */
+/*   Description:  PTC time-out valid                                   */
+#define SH_PTC_PARMS_PTC_TO_VAL_SHFT             24
+#define SH_PTC_PARMS_PTC_TO_VAL_MASK             0x0000000fff000000
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPA"                        */
+/*                  RTC Compare Value for Processor A                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPA                              0x00000001101b0000
+#define SH_INT_CMPA_MASK                         0x007fffffffffffff
+#define SH_INT_CMPA_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPA_REAL_TIME_CMPA                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPA_REAL_TIME_CMPA_SHFT          0
+#define SH_INT_CMPA_REAL_TIME_CMPA_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPB                              0x00000001101b0080
+#define SH_INT_CMPB_MASK                         0x007fffffffffffff
+#define SH_INT_CMPB_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPC                              0x00000001101b0100
+#define SH_INT_CMPC_MASK                         0x007fffffffffffff
+#define SH_INT_CMPC_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPD                              0x00000001101b0180
+#define SH_INT_CMPD_MASK                         0x007fffffffffffff
+#define SH_INT_CMPD_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_PROF"                        */
+/*                      Profile Compare Registers                       */
+/* ==================================================================== */
+
+#define SH_INT_PROF                              0x00000001101b0200
+#define SH_INT_PROF_MASK                         0x00000000ffffffff
+#define SH_INT_PROF_INIT                         0x0000000000000000
+
+/*   SH_INT_PROF_PROFILE_COMPARE                                        */
+/*   Description:  Profile Compare                                      */
+#define SH_INT_PROF_PROFILE_COMPARE_SHFT         0
+#define SH_INT_PROF_PROFILE_COMPARE_MASK         0x00000000ffffffff
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+
+#define SH_RTC                                   0x00000001101c0000
+#define SH_RTC_MASK                              0x007fffffffffffff
+#define SH_RTC_INIT                              0x0000000000000000
+
+/*   SH_RTC_REAL_TIME_CLOCK                                             */
+/*   Description:  Real-time Clock                                      */
+#define SH_RTC_REAL_TIME_CLOCK_SHFT              0
+#define SH_RTC_REAL_TIME_CLOCK_MASK              0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH0"                        */
+/*                          Scratch Register 0                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH0                              0x00000001101d0000
+#define SH_SCRATCH0_MASK                         0xffffffffffffffff
+#define SH_SCRATCH0_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH0_SCRATCH0                                               */
+/*   Description:  Scratch register 0                                   */
+#define SH_SCRATCH0_SCRATCH0_SHFT                0
+#define SH_SCRATCH0_SCRATCH0_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH0_ALIAS"                     */
+/*                   Scratch Register 0 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH0_ALIAS                        0x00000001101d0008
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH1"                        */
+/*                          Scratch Register 1                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH1                              0x00000001101d0080
+#define SH_SCRATCH1_MASK                         0xffffffffffffffff
+#define SH_SCRATCH1_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH1_SCRATCH1                                               */
+/*   Description:  Scratch register 1                                   */
+#define SH_SCRATCH1_SCRATCH1_SHFT                0
+#define SH_SCRATCH1_SCRATCH1_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH1_ALIAS"                     */
+/*                   Scratch Register 1 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH1_ALIAS                        0x00000001101d0088
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH2"                        */
+/*                          Scratch Register 2                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH2                              0x00000001101d0100
+#define SH_SCRATCH2_MASK                         0xffffffffffffffff
+#define SH_SCRATCH2_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH2_SCRATCH2                                               */
+/*   Description:  Scratch register 2                                   */
+#define SH_SCRATCH2_SCRATCH2_SHFT                0
+#define SH_SCRATCH2_SCRATCH2_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH2_ALIAS"                     */
+/*                   Scratch Register 2 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH2_ALIAS                        0x00000001101d0108
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH3"                        */
+/*                          Scratch Register 3                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH3                              0x00000001101d0180
+#define SH_SCRATCH3_MASK                         0x0000000000000001
+#define SH_SCRATCH3_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH3_SCRATCH3                                               */
+/*   Description:  Scratch register 3                                   */
+#define SH_SCRATCH3_SCRATCH3_SHFT                0
+#define SH_SCRATCH3_SCRATCH3_MASK                0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH3_ALIAS"                     */
+/*                   Scratch Register 3 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH3_ALIAS                        0x00000001101d0188
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH4"                        */
+/*                          Scratch Register 4                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH4                              0x00000001101d0200
+#define SH_SCRATCH4_MASK                         0x0000000000000001
+#define SH_SCRATCH4_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH4_SCRATCH4                                               */
+/*   Description:  Scratch register 4                                   */
+#define SH_SCRATCH4_SCRATCH4_SHFT                0
+#define SH_SCRATCH4_SCRATCH4_MASK                0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH4_ALIAS"                     */
+/*                   Scratch Register 4 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH4_ALIAS                        0x00000001101d0208
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_MESSAGE_CONTROL"                   */
+/*               Coherent Request Buffer Message Control                */
+/* ==================================================================== */
+
+#define SH_CRB_MESSAGE_CONTROL                   0x0000000120000000
+#define SH_CRB_MESSAGE_CONTROL_MASK              0xffffffff00000fff
+#define SH_CRB_MESSAGE_CONTROL_INIT              0x0000000000000006
+
+/*   SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE                     */
+/*   Description:  System Coherence Enabled                             */
+#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0
+#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001
+
+/*   SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE            */
+/*   Description:  Speculative Read Requests to Local Memory Enabled    */
+#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1
+#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002
+
+/*   SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE           */
+/*   Description:  Speculative Read Requests to Remote Memory Enabled  */
+#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2
+#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004
+
+/*   SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR                               */
+/*   Description:  Define color of message                              */
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008
+
+/*   SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE                        */
+/*   Description:  Enable color message processing                      */
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010
+
+/*   SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB RRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020
+
+/*   SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB WRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040
+
+/*   SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB IRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7
+#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080
+
+/*   SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE            */
+/*   Description:  Enable XB RRB Mismatch check                         */
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100
+
+/*   SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE            */
+/*   Description:  Enable XB WRB Mismatch check                         */
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200
+
+/*   SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES                       */
+/*   Description:  ignor residual write data                            */
+#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10
+#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400
+
+/*   SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION                  */
+/*   Description:  enable IVACK reply consolidation                     */
+#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11
+#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800
+
+/*   SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT                           */
+/*   Description:  IVACK stall counter                                  */
+#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32
+#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000
+
+/*   SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL                      */
+/*   Description:  IVACK throttling limit/timer control                 */
+#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48
+#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_CRB_NACK_LIMIT"                     */
+/*                            CRB Nack Limit                            */
+/* ==================================================================== */
+
+#define SH_CRB_NACK_LIMIT                        0x0000000120000080
+#define SH_CRB_NACK_LIMIT_MASK                   0x800000000000ffff
+#define SH_CRB_NACK_LIMIT_INIT                   0x0000000000000000
+
+/*   SH_CRB_NACK_LIMIT_LIMIT                                            */
+/*   Description:  Nack Count Limit                                     */
+#define SH_CRB_NACK_LIMIT_LIMIT_SHFT             0
+#define SH_CRB_NACK_LIMIT_LIMIT_MASK             0x0000000000000fff
+
+/*   SH_CRB_NACK_LIMIT_PRI_FREQ                                         */
+/*   Description:  Frequency at which priority count is incremented     */
+#define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT          12
+#define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK          0x000000000000f000
+
+/*   SH_CRB_NACK_LIMIT_ENABLE                                           */
+/*   Description:  Enable NACK limit detection                          */
+#define SH_CRB_NACK_LIMIT_ENABLE_SHFT            63
+#define SH_CRB_NACK_LIMIT_ENABLE_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_TIMEOUT_PRESCALE"                  */
+/*               Coherent Request Buffer Timeout Prescale               */
+/* ==================================================================== */
+
+#define SH_CRB_TIMEOUT_PRESCALE                  0x0000000120000100
+#define SH_CRB_TIMEOUT_PRESCALE_MASK             0x00000000ffffffff
+#define SH_CRB_TIMEOUT_PRESCALE_INIT             0x0000000000000000
+
+/*   SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR                             */
+/*   Description:  CRB Time-out Prescale Factor                         */
+#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0
+#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_CRB_TIMEOUT_SKID"                    */
+/*              Coherent Request Buffer Timeout Skid Limit              */
+/* ==================================================================== */
+
+#define SH_CRB_TIMEOUT_SKID                      0x0000000120000180
+#define SH_CRB_TIMEOUT_SKID_MASK                 0x800000000000003f
+#define SH_CRB_TIMEOUT_SKID_INIT                 0x0000000000000007
+
+/*   SH_CRB_TIMEOUT_SKID_SKID                                           */
+/*   Description:  CRB Time-out Skid                                    */
+#define SH_CRB_TIMEOUT_SKID_SKID_SHFT            0
+#define SH_CRB_TIMEOUT_SKID_SKID_MASK            0x000000000000003f
+
+/*   SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT                               */
+/*   Description:  Reset Skid counter                                   */
+#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63
+#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_0"                  */
+/*                    Memory Write Status for CPU 0                     */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_0                 0x0000000120070000
+#define SH_MEMORY_WRITE_STATUS_0_MASK            0x000000000000003f
+#define SH_MEMORY_WRITE_STATUS_0_INIT            0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT                       */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_1"                  */
+/*                    Memory Write Status for CPU 1                     */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_1                 0x0000000120070080
+#define SH_MEMORY_WRITE_STATUS_1_MASK            0x000000000000003f
+#define SH_MEMORY_WRITE_STATUS_1_INIT            0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT                       */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0"                   */
+/*                      PIO Write Status for CPU 0                      */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_0                    0x0000000120070200
+#define SH_PIO_WRITE_STATUS_0_MASK               0xbf03ffffffffffff
+#define SH_PIO_WRITE_STATUS_0_INIT               0x8000000000000000
+
+/*   SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR                            */
+/*   Description:  More than one PIO write error occured                */
+#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0
+#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
+/*   Description:  Deaklock response detected                           */
+#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_ERROR                                  */
+/*   Description:  Error response detected                              */
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT   2
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK   0x0000000000000004
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS                          */
+/*   Description:  Address associated with error response               */
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
+
+/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+
+/*   SH_PIO_WRITE_STATUS_0_WRITES_OK                                    */
+/*   Description:  No pending writes or errors                          */
+#define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT     63
+#define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK     0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_1"                   */
+/*                      PIO Write Status for CPU 1                      */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_1                    0x0000000120070280
+#define SH_PIO_WRITE_STATUS_1_MASK               0xbf03ffffffffffff
+#define SH_PIO_WRITE_STATUS_1_INIT               0x8000000000000000
+
+/*   SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR                            */
+/*   Description:  More than one PIO write error occured                */
+#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0
+#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK                               */
+/*   Description:  Deaklock response detected                           */
+#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_ERROR                                  */
+/*   Description:  Error response detected                              */
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT   2
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK   0x0000000000000004
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS                          */
+/*   Description:  Address associated with error response               */
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
+
+/*   SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+
+/*   SH_PIO_WRITE_STATUS_1_WRITES_OK                                    */
+/*   Description:  No pending writes or errors                          */
+#define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT     63
+#define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK     0x8000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_1_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_1_ALIAS              0x0000000120070288
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_0"             */
+/*            Memory Write Status for CPU 0. OS access only             */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0        0x0000000120070400
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK   0x800000000000003f
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT   0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT              */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR                            */
+/*   Description:  Clear pending write count                            */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_1"             */
+/*            Memory Write Status for CPU 1. OS access only             */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1        0x0000000120070480
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK   0x800000000000003f
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT   0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT              */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR                            */
+/*   Description:  Clear pending write count                            */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_ERR"                       */
+/*                  Error capture for bist read errors                  */
+/* ==================================================================== */
+
+#define SH_MMRBIST_ERR                           0x0000000100000080
+#define SH_MMRBIST_ERR_MASK                      0x00000071ffffffff
+#define SH_MMRBIST_ERR_INIT                      0x0000000000000000
+
+/*   SH_MMRBIST_ERR_ADDR                                                */
+/*   Description:  dword address of bist error                          */
+#define SH_MMRBIST_ERR_ADDR_SHFT                 0
+#define SH_MMRBIST_ERR_ADDR_MASK                 0x00000001ffffffff
+
+/*   SH_MMRBIST_ERR_DETECTED                                            */
+/*   Description:  error detected flag                                  */
+#define SH_MMRBIST_ERR_DETECTED_SHFT             36
+#define SH_MMRBIST_ERR_DETECTED_MASK             0x0000001000000000
+
+/*   SH_MMRBIST_ERR_MULTIPLE_DETECTED                                   */
+/*   Description:  multiple errors detected flag                        */
+#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT    37
+#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK    0x0000002000000000
+
+/*   SH_MMRBIST_ERR_CANCELLED                                           */
+/*   Description:  mmr/bist was cancelled                               */
+#define SH_MMRBIST_ERR_CANCELLED_SHFT            38
+#define SH_MMRBIST_ERR_CANCELLED_MASK            0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_LOWER"                   */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_MISC_ERR_HDR_LOWER                    0x0000000100000088
+#define SH_MISC_ERR_HDR_LOWER_MASK               0x93fffffffffffff8
+#define SH_MISC_ERR_HDR_LOWER_INIT               0x0000000000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_ADDR                                         */
+/*   Description:  upper bits of reference address                      */
+#define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT          3
+#define SH_MISC_ERR_HDR_LOWER_ADDR_MASK          0x0000000ffffffff8
+
+/*   SH_MISC_ERR_HDR_LOWER_CMD                                          */
+/*   Description:  command of reference                                 */
+#define SH_MISC_ERR_HDR_LOWER_CMD_SHFT           36
+#define SH_MISC_ERR_HDR_LOWER_CMD_MASK           0x00000ff000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_SRC                                          */
+/*   Description:  source node of reference                             */
+#define SH_MISC_ERR_HDR_LOWER_SRC_SHFT           44
+#define SH_MISC_ERR_HDR_LOWER_SRC_MASK           0x03fff00000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_WRITE                                        */
+/*   Description:  reference is a write                                 */
+#define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT         60
+#define SH_MISC_ERR_HDR_LOWER_WRITE_MASK         0x1000000000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_VALID                                        */
+/*   Description:  set when capture occurs                              */
+#define SH_MISC_ERR_HDR_LOWER_VALID_SHFT         63
+#define SH_MISC_ERR_HDR_LOWER_VALID_MASK         0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_UPPER"                   */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_MISC_ERR_HDR_UPPER                    0x0000000100000090
+#define SH_MISC_ERR_HDR_UPPER_MASK               0x000000001ff000ff
+#define SH_MISC_ERR_HDR_UPPER_INIT               0x0000000000000000
+
+/*   SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL                                 */
+/*   Description:  indicates a directory protocol error captured        */
+#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT  0
+#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK  0x0000000000000001
+
+/*   SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD                                  */
+/*   Description:  indicates an illegal command error captured          */
+#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT   1
+#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK   0x0000000000000002
+
+/*   SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR                                */
+/*   Description:  indicates a non-existent memory error captured       */
+#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2
+#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004
+
+/*   SH_MISC_ERR_HDR_UPPER_RMW_UC                                       */
+/*   Description:  indicates an uncorrectable store rmw                 */
+#define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT        3
+#define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK        0x0000000000000008
+
+/*   SH_MISC_ERR_HDR_UPPER_RMW_COR                                      */
+/*   Description:  indicates a correctable store rmw                    */
+#define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT       4
+#define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK       0x0000000000000010
+
+/*   SH_MISC_ERR_HDR_UPPER_DIR_ACC                                      */
+/*   Description:  indicates a data request to directory memory error   */
+/*  captured                                                            */
+#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT       5
+#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK       0x0000000000000020
+
+/*   SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE                                  */
+/*   Description:  indicates a pkt size error from pi                   */
+#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT   6
+#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK   0x0000000000000040
+
+/*   SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE                                  */
+/*   Description:  indicates a pkt size error from xn                   */
+#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT   7
+#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK   0x0000000000000080
+
+/*   SH_MISC_ERR_HDR_UPPER_ECHO                                         */
+#define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT          20
+#define SH_MISC_ERR_HDR_UPPER_ECHO_MASK          0x000000001ff00000
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_DIR_UC_ERR_HDR_LOWER                  0x0000000100000098
+#define SH_DIR_UC_ERR_HDR_LOWER_MASK             0x93fffffffffffff8
+#define SH_DIR_UC_ERR_HDR_LOWER_INIT             0x0000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_ADDR                                       */
+/*   Description:  upper bits of reference address                      */
+#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT        3
+#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK        0x0000000ffffffff8
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_CMD                                        */
+/*   Description:  command of reference                                 */
+#define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT         36
+#define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK         0x00000ff000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_SRC                                        */
+/*   Description:  source node of reference                             */
+#define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT         44
+#define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK         0x03fff00000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_WRITE                                      */
+/*   Description:  reference is a write                                 */
+#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT       60
+#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK       0x1000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_VALID                                      */
+/*   Description:  set when capture occurs                              */
+#define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT       63
+#define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_DIR_UC_ERR_HDR_UPPER                  0x00000001000000a0
+#define SH_DIR_UC_ERR_HDR_UPPER_MASK             0x000000001ff00008
+#define SH_DIR_UC_ERR_HDR_UPPER_INIT             0x0000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_UPPER_DIR_UC                                     */
+/*   Description:  indicates uncorrectable directory error captured     */
+#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT      3
+#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK      0x0000000000000008
+
+/*   SH_DIR_UC_ERR_HDR_UPPER_ECHO                                       */
+#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT        20
+#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK        0x000000001ff00000
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_DIR_COR_ERR_HDR_LOWER                 0x00000001000000a8
+#define SH_DIR_COR_ERR_HDR_LOWER_MASK            0x93fffffffffffff8
+#define SH_DIR_COR_ERR_HDR_LOWER_INIT            0x0000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_ADDR                                      */
+/*   Description:  upper bits of reference address                      */
+#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT       3
+#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK       0x0000000ffffffff8
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_CMD                                       */
+/*   Description:  command of reference                                 */
+#define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT        36
+#define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK        0x00000ff000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_SRC                                       */
+/*   Description:  source node of reference                             */
+#define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT        44
+#define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK        0x03fff00000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_WRITE                                     */
+/*   Description:  reference is a write                                 */
+#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT      60
+#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK      0x1000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_VALID                                     */
+/*   Description:  set when capture occurs                              */
+#define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT      63
+#define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_DIR_COR_ERR_HDR_UPPER                 0x00000001000000b0
+#define SH_DIR_COR_ERR_HDR_UPPER_MASK            0x000000001ff00100
+#define SH_DIR_COR_ERR_HDR_UPPER_INIT            0x0000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_UPPER_DIR_COR                                   */
+/*   Description:  indicates correctable directory error captured       */
+#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT    8
+#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK    0x0000000000000100
+
+/*   SH_DIR_COR_ERR_HDR_UPPER_ECHO                                      */
+#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT       20
+#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK       0x000000001ff00000
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_SUMMARY"                    */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_SUMMARY                     0x00000001000000b8
+#define SH_MEM_ERROR_SUMMARY_MASK                0x00000007f77777ff
+#define SH_MEM_ERROR_SUMMARY_INIT                0x0000000000000000
+
+/*   SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD                                   */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT    0
+#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK    0x0000000000000001
+
+/*   SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR                                 */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT  1
+#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK  0x0000000000000002
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR                                 */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT  2
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK  0x0000000000000004
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR                                 */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT  3
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK  0x0000000000000008
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC                                   */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT    4
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK    0x0000000000000010
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR                                  */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT   5
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK   0x0000000000000020
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC                                   */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT    6
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK    0x0000000000000040
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR                                  */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT   7
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK   0x0000000000000080
+
+/*   SH_MEM_ERROR_SUMMARY_ACX_INT_HW                                    */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT     8
+#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK     0x0000000000000100
+
+/*   SH_MEM_ERROR_SUMMARY_ACY_INT_HW                                    */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT     9
+#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK     0x0000000000000200
+
+/*   SH_MEM_ERROR_SUMMARY_DIR_ACC                                       */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT        10
+#define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK        0x0000000000000400
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT    12
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK    0x0000000000001000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_COR                                  */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT   13
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK   0x0000000000002000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_HW                                   */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT    14
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK    0x0000000000004000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT    16
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK    0x0000000000010000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_COR                                  */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT   17
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK   0x0000000000020000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_HW                                   */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT    18
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK    0x0000000000040000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT    20
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK    0x0000000000100000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_COR                                  */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT   21
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK   0x0000000000200000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_HW                                   */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT    22
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK    0x0000000000400000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT    24
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK    0x0000000001000000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_COR                                  */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT   25
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK   0x0000000002000000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_HW                                   */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT    26
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK    0x0000000004000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW                             */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW                             */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW                           */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW                           */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT                         */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE                                   */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT    33
+#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK    0x0000000200000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE                                   */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT    34
+#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK    0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_MEM_ERROR_SUMMARY_ALIAS"                 */
+/*                    Memory error flags clear alias                    */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_SUMMARY_ALIAS               0x00000001000000c0
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_OVERFLOW"                   */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_OVERFLOW                    0x00000001000000c8
+#define SH_MEM_ERROR_OVERFLOW_MASK               0x00000007f77777ff
+#define SH_MEM_ERROR_OVERFLOW_INIT               0x0000000000000000
+
+/*   SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD                                  */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT   0
+#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK   0x0000000000000001
+
+/*   SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR                                */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1
+#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR                                */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR                                */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC                                  */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT   4
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK   0x0000000000000010
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR                                 */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT  5
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK  0x0000000000000020
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC                                  */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT   6
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK   0x0000000000000040
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR                                 */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT  7
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK  0x0000000000000080
+
+/*   SH_MEM_ERROR_OVERFLOW_ACX_INT_HW                                   */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT    8
+#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK    0x0000000000000100
+
+/*   SH_MEM_ERROR_OVERFLOW_ACY_INT_HW                                   */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT    9
+#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK    0x0000000000000200
+
+/*   SH_MEM_ERROR_OVERFLOW_DIR_ACC                                      */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT       10
+#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK       0x0000000000000400
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT   12
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK   0x0000000000001000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR                                 */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT  13
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK  0x0000000000002000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW                                  */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT   14
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK   0x0000000000004000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT   16
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK   0x0000000000010000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR                                 */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT  17
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK  0x0000000000020000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW                                  */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT   18
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK   0x0000000000040000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT   20
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK   0x0000000000100000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR                                 */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT  21
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK  0x0000000000200000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW                                  */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT   22
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK   0x0000000000400000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT   24
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK   0x0000000001000000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR                                 */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT  25
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK  0x0000000002000000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW                                  */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT   26
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK   0x0000000004000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW                            */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW                            */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW                          */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW                          */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT                        */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE                                  */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT   33
+#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK   0x0000000200000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE                                  */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT   34
+#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK   0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_MEM_ERROR_OVERFLOW_ALIAS"                */
+/*                    Memory error flags clear alias                    */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_OVERFLOW_ALIAS              0x00000001000000d0
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_ERROR_MASK"                     */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_MASK                        0x00000001000000d8
+#define SH_MEM_ERROR_MASK_MASK                   0x00000007f77777ff
+#define SH_MEM_ERROR_MASK_INIT                   0x00000007f77773ff
+
+/*   SH_MEM_ERROR_MASK_ILLEGAL_CMD                                      */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT       0
+#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK       0x0000000000000001
+
+/*   SH_MEM_ERROR_MASK_NONEXIST_ADDR                                    */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT     1
+#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK     0x0000000000000002
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_PERR                                    */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT     2
+#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK     0x0000000000000004
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_PERR                                    */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT     3
+#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK     0x0000000000000008
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_UC                                      */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT       4
+#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK       0x0000000000000010
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_COR                                     */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT      5
+#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK      0x0000000000000020
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_UC                                      */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT       6
+#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK       0x0000000000000040
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_COR                                     */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT      7
+#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK      0x0000000000000080
+
+/*   SH_MEM_ERROR_MASK_ACX_INT_HW                                       */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT        8
+#define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK        0x0000000000000100
+
+/*   SH_MEM_ERROR_MASK_ACY_INT_HW                                       */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT        9
+#define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK        0x0000000000000200
+
+/*   SH_MEM_ERROR_MASK_DIR_ACC                                          */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_MASK_DIR_ACC_SHFT           10
+#define SH_MEM_ERROR_MASK_DIR_ACC_MASK           0x0000000000000400
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT       12
+#define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK       0x0000000000001000
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_COR                                     */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT      13
+#define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK      0x0000000000002000
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_HW                                      */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT       14
+#define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK       0x0000000000004000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT       16
+#define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK       0x0000000000010000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_COR                                     */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT      17
+#define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK      0x0000000000020000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_HW                                      */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT       18
+#define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK       0x0000000000040000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT       20
+#define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK       0x0000000000100000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_COR                                     */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT      21
+#define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK      0x0000000000200000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_HW                                      */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT       22
+#define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK       0x0000000000400000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT       24
+#define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK       0x0000000001000000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_COR                                     */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT      25
+#define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK      0x0000000002000000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_HW                                      */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT       26
+#define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK       0x0000000004000000
+
+/*   SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW                                */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW                                */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW                              */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW                              */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT                            */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_MASK_PI_PKT_SIZE                                      */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT       33
+#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK       0x0000000200000000
+
+/*   SH_MEM_ERROR_MASK_XN_PKT_SIZE                                      */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT       34
+#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK       0x0000000400000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_X_DIMM_CFG                            0x0000000100010000
+#define SH_X_DIMM_CFG_MASK                       0x0000000f7f7f7f7f
+#define SH_X_DIMM_CFG_INIT                       0x000000026f4f2f0f
+
+/*   SH_X_DIMM_CFG_DIMM0_SIZE                                           */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT            0
+#define SH_X_DIMM_CFG_DIMM0_SIZE_MASK            0x0000000000000007
+
+/*   SH_X_DIMM_CFG_DIMM0_2BK                                            */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM0_2BK_SHFT             3
+#define SH_X_DIMM_CFG_DIMM0_2BK_MASK             0x0000000000000008
+
+/*   SH_X_DIMM_CFG_DIMM0_REV                                            */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM0_REV_SHFT             4
+#define SH_X_DIMM_CFG_DIMM0_REV_MASK             0x0000000000000010
+
+/*   SH_X_DIMM_CFG_DIMM0_CS                                             */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM0_CS_SHFT              5
+#define SH_X_DIMM_CFG_DIMM0_CS_MASK              0x0000000000000060
+
+/*   SH_X_DIMM_CFG_DIMM1_SIZE                                           */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT            8
+#define SH_X_DIMM_CFG_DIMM1_SIZE_MASK            0x0000000000000700
+
+/*   SH_X_DIMM_CFG_DIMM1_2BK                                            */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM1_2BK_SHFT             11
+#define SH_X_DIMM_CFG_DIMM1_2BK_MASK             0x0000000000000800
+
+/*   SH_X_DIMM_CFG_DIMM1_REV                                            */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM1_REV_SHFT             12
+#define SH_X_DIMM_CFG_DIMM1_REV_MASK             0x0000000000001000
+
+/*   SH_X_DIMM_CFG_DIMM1_CS                                             */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM1_CS_SHFT              13
+#define SH_X_DIMM_CFG_DIMM1_CS_MASK              0x0000000000006000
+
+/*   SH_X_DIMM_CFG_DIMM2_SIZE                                           */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT            16
+#define SH_X_DIMM_CFG_DIMM2_SIZE_MASK            0x0000000000070000
+
+/*   SH_X_DIMM_CFG_DIMM2_2BK                                            */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM2_2BK_SHFT             19
+#define SH_X_DIMM_CFG_DIMM2_2BK_MASK             0x0000000000080000
+
+/*   SH_X_DIMM_CFG_DIMM2_REV                                            */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM2_REV_SHFT             20
+#define SH_X_DIMM_CFG_DIMM2_REV_MASK             0x0000000000100000
+
+/*   SH_X_DIMM_CFG_DIMM2_CS                                             */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM2_CS_SHFT              21
+#define SH_X_DIMM_CFG_DIMM2_CS_MASK              0x0000000000600000
+
+/*   SH_X_DIMM_CFG_DIMM3_SIZE                                           */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT            24
+#define SH_X_DIMM_CFG_DIMM3_SIZE_MASK            0x0000000007000000
+
+/*   SH_X_DIMM_CFG_DIMM3_2BK                                            */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM3_2BK_SHFT             27
+#define SH_X_DIMM_CFG_DIMM3_2BK_MASK             0x0000000008000000
+
+/*   SH_X_DIMM_CFG_DIMM3_REV                                            */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM3_REV_SHFT             28
+#define SH_X_DIMM_CFG_DIMM3_REV_MASK             0x0000000010000000
+
+/*   SH_X_DIMM_CFG_DIMM3_CS                                             */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM3_CS_SHFT              29
+#define SH_X_DIMM_CFG_DIMM3_CS_MASK              0x0000000060000000
+
+/*   SH_X_DIMM_CFG_FREQ                                                 */
+/*   Description:  DIMM frequency select                                */
+#define SH_X_DIMM_CFG_FREQ_SHFT                  32
+#define SH_X_DIMM_CFG_FREQ_MASK                  0x0000000f00000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_Y_DIMM_CFG                            0x0000000100010008
+#define SH_Y_DIMM_CFG_MASK                       0x0000000f7f7f7f7f
+#define SH_Y_DIMM_CFG_INIT                       0x000000026f4f2f0f
+
+/*   SH_Y_DIMM_CFG_DIMM0_SIZE                                           */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT            0
+#define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK            0x0000000000000007
+
+/*   SH_Y_DIMM_CFG_DIMM0_2BK                                            */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT             3
+#define SH_Y_DIMM_CFG_DIMM0_2BK_MASK             0x0000000000000008
+
+/*   SH_Y_DIMM_CFG_DIMM0_REV                                            */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM0_REV_SHFT             4
+#define SH_Y_DIMM_CFG_DIMM0_REV_MASK             0x0000000000000010
+
+/*   SH_Y_DIMM_CFG_DIMM0_CS                                             */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM0_CS_SHFT              5
+#define SH_Y_DIMM_CFG_DIMM0_CS_MASK              0x0000000000000060
+
+/*   SH_Y_DIMM_CFG_DIMM1_SIZE                                           */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT            8
+#define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK            0x0000000000000700
+
+/*   SH_Y_DIMM_CFG_DIMM1_2BK                                            */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT             11
+#define SH_Y_DIMM_CFG_DIMM1_2BK_MASK             0x0000000000000800
+
+/*   SH_Y_DIMM_CFG_DIMM1_REV                                            */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM1_REV_SHFT             12
+#define SH_Y_DIMM_CFG_DIMM1_REV_MASK             0x0000000000001000
+
+/*   SH_Y_DIMM_CFG_DIMM1_CS                                             */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM1_CS_SHFT              13
+#define SH_Y_DIMM_CFG_DIMM1_CS_MASK              0x0000000000006000
+
+/*   SH_Y_DIMM_CFG_DIMM2_SIZE                                           */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT            16
+#define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK            0x0000000000070000
+
+/*   SH_Y_DIMM_CFG_DIMM2_2BK                                            */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT             19
+#define SH_Y_DIMM_CFG_DIMM2_2BK_MASK             0x0000000000080000
+
+/*   SH_Y_DIMM_CFG_DIMM2_REV                                            */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM2_REV_SHFT             20
+#define SH_Y_DIMM_CFG_DIMM2_REV_MASK             0x0000000000100000
+
+/*   SH_Y_DIMM_CFG_DIMM2_CS                                             */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM2_CS_SHFT              21
+#define SH_Y_DIMM_CFG_DIMM2_CS_MASK              0x0000000000600000
+
+/*   SH_Y_DIMM_CFG_DIMM3_SIZE                                           */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT            24
+#define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK            0x0000000007000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_2BK                                            */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT             27
+#define SH_Y_DIMM_CFG_DIMM3_2BK_MASK             0x0000000008000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_REV                                            */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM3_REV_SHFT             28
+#define SH_Y_DIMM_CFG_DIMM3_REV_MASK             0x0000000010000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_CS                                             */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM3_CS_SHFT              29
+#define SH_Y_DIMM_CFG_DIMM3_CS_MASK              0x0000000060000000
+
+/*   SH_Y_DIMM_CFG_FREQ                                                 */
+/*   Description:  DIMM frequency select                                */
+#define SH_Y_DIMM_CFG_FREQ_SHFT                  32
+#define SH_Y_DIMM_CFG_FREQ_MASK                  0x0000000f00000000
+
+/* ==================================================================== */
+/*                      Register "SH_JNR_DIMM_CFG"                      */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_JNR_DIMM_CFG                          0x0000000100010010
+#define SH_JNR_DIMM_CFG_MASK                     0x0000000f7f7f7f7f
+#define SH_JNR_DIMM_CFG_INIT                     0x000000026f4f2f0f
+
+/*   SH_JNR_DIMM_CFG_DIMM0_SIZE                                         */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT          0
+#define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK          0x0000000000000007
+
+/*   SH_JNR_DIMM_CFG_DIMM0_2BK                                          */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT           3
+#define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK           0x0000000000000008
+
+/*   SH_JNR_DIMM_CFG_DIMM0_REV                                          */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT           4
+#define SH_JNR_DIMM_CFG_DIMM0_REV_MASK           0x0000000000000010
+
+/*   SH_JNR_DIMM_CFG_DIMM0_CS                                           */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT            5
+#define SH_JNR_DIMM_CFG_DIMM0_CS_MASK            0x0000000000000060
+
+/*   SH_JNR_DIMM_CFG_DIMM1_SIZE                                         */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT          8
+#define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK          0x0000000000000700
+
+/*   SH_JNR_DIMM_CFG_DIMM1_2BK                                          */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT           11
+#define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK           0x0000000000000800
+
+/*   SH_JNR_DIMM_CFG_DIMM1_REV                                          */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT           12
+#define SH_JNR_DIMM_CFG_DIMM1_REV_MASK           0x0000000000001000
+
+/*   SH_JNR_DIMM_CFG_DIMM1_CS                                           */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT            13
+#define SH_JNR_DIMM_CFG_DIMM1_CS_MASK            0x0000000000006000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_SIZE                                         */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT          16
+#define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK          0x0000000000070000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_2BK                                          */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT           19
+#define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK           0x0000000000080000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_REV                                          */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT           20
+#define SH_JNR_DIMM_CFG_DIMM2_REV_MASK           0x0000000000100000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_CS                                           */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT            21
+#define SH_JNR_DIMM_CFG_DIMM2_CS_MASK            0x0000000000600000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_SIZE                                         */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT          24
+#define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK          0x0000000007000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_2BK                                          */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT           27
+#define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK           0x0000000008000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_REV                                          */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT           28
+#define SH_JNR_DIMM_CFG_DIMM3_REV_MASK           0x0000000010000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_CS                                           */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT            29
+#define SH_JNR_DIMM_CFG_DIMM3_CS_MASK            0x0000000060000000
+
+/*   SH_JNR_DIMM_CFG_FREQ                                               */
+/*   Description:  DIMM frequency select                                */
+#define SH_JNR_DIMM_CFG_FREQ_SHFT                32
+#define SH_JNR_DIMM_CFG_FREQ_MASK                0x0000000f00000000
+
+/* ==================================================================== */
+/*                      Register "SH_X_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#define SH_X_PHASE_CFG                           0x0000000100010018
+#define SH_X_PHASE_CFG_MASK                      0x7fffffffffffffff
+#define SH_X_PHASE_CFG_INIT                      0x0000000000000000
+
+/*   SH_X_PHASE_CFG_LD_A                                                */
+/*   Description:  Address, control load core clock A latch             */
+#define SH_X_PHASE_CFG_LD_A_SHFT                 0
+#define SH_X_PHASE_CFG_LD_A_MASK                 0x000000000000001f
+
+/*   SH_X_PHASE_CFG_LD_B                                                */
+/*   Description:  Address, control load core clock B latch             */
+#define SH_X_PHASE_CFG_LD_B_SHFT                 5
+#define SH_X_PHASE_CFG_LD_B_MASK                 0x00000000000003e0
+
+/*   SH_X_PHASE_CFG_DQ_LD_A                                             */
+/*   Description:  DATA MCI load core clock A latch                     */
+#define SH_X_PHASE_CFG_DQ_LD_A_SHFT              10
+#define SH_X_PHASE_CFG_DQ_LD_A_MASK              0x0000000000007c00
+
+/*   SH_X_PHASE_CFG_DQ_LD_B                                             */
+/*   Description:  DATA MCI load core clock B latch                     */
+#define SH_X_PHASE_CFG_DQ_LD_B_SHFT              15
+#define SH_X_PHASE_CFG_DQ_LD_B_MASK              0x00000000000f8000
+
+/*   SH_X_PHASE_CFG_HOLD                                                */
+/*   Description:  Hold request on core clock phase                     */
+#define SH_X_PHASE_CFG_HOLD_SHFT                 20
+#define SH_X_PHASE_CFG_HOLD_MASK                 0x0000000001f00000
+
+/*   SH_X_PHASE_CFG_HOLD_REQ                                            */
+/*   Description:  Hold next request on core clock phase                */
+#define SH_X_PHASE_CFG_HOLD_REQ_SHFT             25
+#define SH_X_PHASE_CFG_HOLD_REQ_MASK             0x000000003e000000
+
+/*   SH_X_PHASE_CFG_ADD_CP                                              */
+/*   Description:  add delay clock period to dqct delay chain on phase  */
+#define SH_X_PHASE_CFG_ADD_CP_SHFT               30
+#define SH_X_PHASE_CFG_ADD_CP_MASK               0x00000007c0000000
+
+/*   SH_X_PHASE_CFG_BUBBLE_EN                                           */
+/*   Description:  bubble, idle core clock to wait for memory clock     */
+#define SH_X_PHASE_CFG_BUBBLE_EN_SHFT            35
+#define SH_X_PHASE_CFG_BUBBLE_EN_MASK            0x000000f800000000
+
+/*   SH_X_PHASE_CFG_PHA_BUBBLE                                          */
+/*   Description:  MMR phaseA bubble value                              */
+#define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT           40
+#define SH_X_PHASE_CFG_PHA_BUBBLE_MASK           0x0000070000000000
+
+/*   SH_X_PHASE_CFG_PHB_BUBBLE                                          */
+/*   Description:  MMR phaseB bubble value                              */
+#define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT           43
+#define SH_X_PHASE_CFG_PHB_BUBBLE_MASK           0x0000380000000000
+
+/*   SH_X_PHASE_CFG_PHC_BUBBLE                                          */
+/*   Description:  MMR phaseC bubble value                              */
+#define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT           46
+#define SH_X_PHASE_CFG_PHC_BUBBLE_MASK           0x0001c00000000000
+
+/*   SH_X_PHASE_CFG_PHD_BUBBLE                                          */
+/*   Description:  MMR phaseD bubble value                              */
+#define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT           49
+#define SH_X_PHASE_CFG_PHD_BUBBLE_MASK           0x000e000000000000
+
+/*   SH_X_PHASE_CFG_PHE_BUBBLE                                          */
+/*   Description:  MMR phaseE bubble value                              */
+#define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT           52
+#define SH_X_PHASE_CFG_PHE_BUBBLE_MASK           0x0070000000000000
+
+/*   SH_X_PHASE_CFG_SEL_A                                               */
+/*   Description:  address,control select A memory clock latch          */
+#define SH_X_PHASE_CFG_SEL_A_SHFT                55
+#define SH_X_PHASE_CFG_SEL_A_MASK                0x0780000000000000
+
+/*   SH_X_PHASE_CFG_DQ_SEL_A                                            */
+/*   Description:  DATA MCI select A memory clock latch                 */
+#define SH_X_PHASE_CFG_DQ_SEL_A_SHFT             59
+#define SH_X_PHASE_CFG_DQ_SEL_A_MASK             0x7800000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_X_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_X_CFG                                 0x0000000100010020
+#define SH_X_CFG_MASK                            0xffffffffffffffff
+#define SH_X_CFG_INIT                            0x108443103322100c
+
+/*   SH_X_CFG_MODE_SERIAL                                               */
+/*   Description:  Arbque arbitration in serial mode                    */
+#define SH_X_CFG_MODE_SERIAL_SHFT                0
+#define SH_X_CFG_MODE_SERIAL_MASK                0x0000000000000001
+
+/*   SH_X_CFG_DIRC_RANDOM_REPLACEMENT                                   */
+/*   Description:  Directory cache random replacement                   */
+#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT    1
+#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK    0x0000000000000002
+
+/*   SH_X_CFG_DIR_COUNTER_INIT                                          */
+/*   Description:  Dir counter initial value                            */
+#define SH_X_CFG_DIR_COUNTER_INIT_SHFT           2
+#define SH_X_CFG_DIR_COUNTER_INIT_MASK           0x00000000000000fc
+
+/*   SH_X_CFG_TA_DLYS                                                   */
+/*   Description:  Turn around delays                                   */
+#define SH_X_CFG_TA_DLYS_SHFT                    8
+#define SH_X_CFG_TA_DLYS_MASK                    0x000000ffffffff00
+
+/*   SH_X_CFG_DA_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a data read request                */
+#define SH_X_CFG_DA_BB_CLR_SHFT                  40
+#define SH_X_CFG_DA_BB_CLR_MASK                  0x00000f0000000000
+
+/*   SH_X_CFG_DC_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a directory cache read request     */
+#define SH_X_CFG_DC_BB_CLR_SHFT                  44
+#define SH_X_CFG_DC_BB_CLR_MASK                  0x0000f00000000000
+
+/*   SH_X_CFG_WT_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for all write request                  */
+#define SH_X_CFG_WT_BB_CLR_SHFT                  48
+#define SH_X_CFG_WT_BB_CLR_MASK                  0x000f000000000000
+
+/*   SH_X_CFG_SSO_WT_EN                                                 */
+/*   Description:  Simultaneous switching enabled on output data pins  */
+#define SH_X_CFG_SSO_WT_EN_SHFT                  52
+#define SH_X_CFG_SSO_WT_EN_MASK                  0x0010000000000000
+
+/*   SH_X_CFG_TRCD2_EN                                                  */
+/*   Description:  Trcd, ras to cas delay of 2 CPs enabled              */
+#define SH_X_CFG_TRCD2_EN_SHFT                   53
+#define SH_X_CFG_TRCD2_EN_MASK                   0x0020000000000000
+
+/*   SH_X_CFG_TRCD4_EN                                                  */
+/*   Description:  Trcd, ras to case delay of 4 CPs enabled             */
+#define SH_X_CFG_TRCD4_EN_SHFT                   54
+#define SH_X_CFG_TRCD4_EN_MASK                   0x0040000000000000
+
+/*   SH_X_CFG_REQ_CNTR_DIS                                              */
+/*   Description:  Request delay counter disabled                       */
+#define SH_X_CFG_REQ_CNTR_DIS_SHFT               55
+#define SH_X_CFG_REQ_CNTR_DIS_MASK               0x0080000000000000
+
+/*   SH_X_CFG_REQ_CNTR_VAL                                              */
+/*   Description:  Request counter delay value in CPs                   */
+#define SH_X_CFG_REQ_CNTR_VAL_SHFT               56
+#define SH_X_CFG_REQ_CNTR_VAL_MASK               0x3f00000000000000
+
+/*   SH_X_CFG_INV_CAS_ADDR                                              */
+/*   Description:  Invert cas address bits 3 to 7                       */
+#define SH_X_CFG_INV_CAS_ADDR_SHFT               62
+#define SH_X_CFG_INV_CAS_ADDR_MASK               0x4000000000000000
+
+/*   SH_X_CFG_CLR_DIR_CACHE                                             */
+/*   Description:  Clear directory cache tags                           */
+#define SH_X_CFG_CLR_DIR_CACHE_SHFT              63
+#define SH_X_CFG_CLR_DIR_CACHE_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_X_DQCT_CFG                            0x0000000100010028
+#define SH_X_DQCT_CFG_MASK                       0x0000000000ffffff
+#define SH_X_DQCT_CFG_INIT                       0x0000000000585418
+
+/*   SH_X_DQCT_CFG_RD_SEL                                               */
+/*   Description:  Read data select                                     */
+#define SH_X_DQCT_CFG_RD_SEL_SHFT                0
+#define SH_X_DQCT_CFG_RD_SEL_MASK                0x000000000000000f
+
+/*   SH_X_DQCT_CFG_WT_SEL                                               */
+/*   Description:  Write data select                                    */
+#define SH_X_DQCT_CFG_WT_SEL_SHFT                4
+#define SH_X_DQCT_CFG_WT_SEL_MASK                0x00000000000000f0
+
+/*   SH_X_DQCT_CFG_DTA_RD_SEL                                           */
+/*   Description:  Data ready read select                               */
+#define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT            8
+#define SH_X_DQCT_CFG_DTA_RD_SEL_MASK            0x0000000000000f00
+
+/*   SH_X_DQCT_CFG_DTA_WT_SEL                                           */
+/*   Description:  Data ready write select                              */
+#define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT            12
+#define SH_X_DQCT_CFG_DTA_WT_SEL_MASK            0x000000000000f000
+
+/*   SH_X_DQCT_CFG_DIR_RD_SEL                                           */
+/*   Description:  Dir ready read select                                */
+#define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT            16
+#define SH_X_DQCT_CFG_DIR_RD_SEL_MASK            0x00000000000f0000
+
+/*   SH_X_DQCT_CFG_MDIR_RD_SEL                                          */
+/*   Description:  Dir ready read select                                */
+#define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT           20
+#define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK           0x0000000000f00000
+
+/* ==================================================================== */
+/*                   Register "SH_X_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#define SH_X_REFRESH_CONTROL                     0x0000000100010030
+#define SH_X_REFRESH_CONTROL_MASK                0x000000000fffffff
+#define SH_X_REFRESH_CONTROL_INIT                0x00000000009cc300
+
+/*   SH_X_REFRESH_CONTROL_ENABLE                                        */
+/*   Description:  Refresh enable                                       */
+#define SH_X_REFRESH_CONTROL_ENABLE_SHFT         0
+#define SH_X_REFRESH_CONTROL_ENABLE_MASK         0x00000000000000ff
+
+/*   SH_X_REFRESH_CONTROL_INTERVAL                                      */
+/*   Description:  Refresh interval in core CPs                         */
+#define SH_X_REFRESH_CONTROL_INTERVAL_SHFT       8
+#define SH_X_REFRESH_CONTROL_INTERVAL_MASK       0x000000000001ff00
+
+/*   SH_X_REFRESH_CONTROL_HOLD                                          */
+/*   Description:  Refresh hold                                         */
+#define SH_X_REFRESH_CONTROL_HOLD_SHFT           17
+#define SH_X_REFRESH_CONTROL_HOLD_MASK           0x00000000007e0000
+
+/*   SH_X_REFRESH_CONTROL_INTERLEAVE                                    */
+/*   Description:  Refresh interleave                                   */
+#define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT     23
+#define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK     0x0000000000800000
+
+/*   SH_X_REFRESH_CONTROL_HALF_RATE                                     */
+/*   Description:  Refresh half rate                                    */
+#define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT      24
+#define SH_X_REFRESH_CONTROL_HALF_RATE_MASK      0x000000000f000000
+
+/* ==================================================================== */
+/*                      Register "SH_Y_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#define SH_Y_PHASE_CFG                           0x0000000100010038
+#define SH_Y_PHASE_CFG_MASK                      0x7fffffffffffffff
+#define SH_Y_PHASE_CFG_INIT                      0x0000000000000000
+
+/*   SH_Y_PHASE_CFG_LD_A                                                */
+/*   Description:  Address, control load core clock A latch             */
+#define SH_Y_PHASE_CFG_LD_A_SHFT                 0
+#define SH_Y_PHASE_CFG_LD_A_MASK                 0x000000000000001f
+
+/*   SH_Y_PHASE_CFG_LD_B                                                */
+/*   Description:  Address, control load core clock B latch             */
+#define SH_Y_PHASE_CFG_LD_B_SHFT                 5
+#define SH_Y_PHASE_CFG_LD_B_MASK                 0x00000000000003e0
+
+/*   SH_Y_PHASE_CFG_DQ_LD_A                                             */
+/*   Description:  DATA MCI load core clock A latch                     */
+#define SH_Y_PHASE_CFG_DQ_LD_A_SHFT              10
+#define SH_Y_PHASE_CFG_DQ_LD_A_MASK              0x0000000000007c00
+
+/*   SH_Y_PHASE_CFG_DQ_LD_B                                             */
+/*   Description:  DATA MCI load core clock B latch                     */
+#define SH_Y_PHASE_CFG_DQ_LD_B_SHFT              15
+#define SH_Y_PHASE_CFG_DQ_LD_B_MASK              0x00000000000f8000
+
+/*   SH_Y_PHASE_CFG_HOLD                                                */
+/*   Description:  Hold request on core clock phase                     */
+#define SH_Y_PHASE_CFG_HOLD_SHFT                 20
+#define SH_Y_PHASE_CFG_HOLD_MASK                 0x0000000001f00000
+
+/*   SH_Y_PHASE_CFG_HOLD_REQ                                            */
+/*   Description:  Hold next request on core clock phase                */
+#define SH_Y_PHASE_CFG_HOLD_REQ_SHFT             25
+#define SH_Y_PHASE_CFG_HOLD_REQ_MASK             0x000000003e000000
+
+/*   SH_Y_PHASE_CFG_ADD_CP                                              */
+/*   Description:  add delay clock period to dqct delay chain on phase  */
+#define SH_Y_PHASE_CFG_ADD_CP_SHFT               30
+#define SH_Y_PHASE_CFG_ADD_CP_MASK               0x00000007c0000000
+
+/*   SH_Y_PHASE_CFG_BUBBLE_EN                                           */
+/*   Description:  bubble, idle core clock to wait for memory clock     */
+#define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT            35
+#define SH_Y_PHASE_CFG_BUBBLE_EN_MASK            0x000000f800000000
+
+/*   SH_Y_PHASE_CFG_PHA_BUBBLE                                          */
+/*   Description:  MMR phaseA bubble value                              */
+#define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT           40
+#define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK           0x0000070000000000
+
+/*   SH_Y_PHASE_CFG_PHB_BUBBLE                                          */
+/*   Description:  MMR phaseB bubble value                              */
+#define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT           43
+#define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK           0x0000380000000000
+
+/*   SH_Y_PHASE_CFG_PHC_BUBBLE                                          */
+/*   Description:  MMR phaseC bubble value                              */
+#define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT           46
+#define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK           0x0001c00000000000
+
+/*   SH_Y_PHASE_CFG_PHD_BUBBLE                                          */
+/*   Description:  MMR phaseD bubble value                              */
+#define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT           49
+#define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK           0x000e000000000000
+
+/*   SH_Y_PHASE_CFG_PHE_BUBBLE                                          */
+/*   Description:  MMR phaseE bubble value                              */
+#define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT           52
+#define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK           0x0070000000000000
+
+/*   SH_Y_PHASE_CFG_SEL_A                                               */
+/*   Description:  address,control select A memory clock latch          */
+#define SH_Y_PHASE_CFG_SEL_A_SHFT                55
+#define SH_Y_PHASE_CFG_SEL_A_MASK                0x0780000000000000
+
+/*   SH_Y_PHASE_CFG_DQ_SEL_A                                            */
+/*   Description:  DATA MCI select A memory clock latch                 */
+#define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT             59
+#define SH_Y_PHASE_CFG_DQ_SEL_A_MASK             0x7800000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_Y_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_Y_CFG                                 0x0000000100010040
+#define SH_Y_CFG_MASK                            0xffffffffffffffff
+#define SH_Y_CFG_INIT                            0x108443103322100c
+
+/*   SH_Y_CFG_MODE_SERIAL                                               */
+/*   Description:  Arbque arbitration in serial mode                    */
+#define SH_Y_CFG_MODE_SERIAL_SHFT                0
+#define SH_Y_CFG_MODE_SERIAL_MASK                0x0000000000000001
+
+/*   SH_Y_CFG_DIRC_RANDOM_REPLACEMENT                                   */
+/*   Description:  Directory cache random replacement                   */
+#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT    1
+#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK    0x0000000000000002
+
+/*   SH_Y_CFG_DIR_COUNTER_INIT                                          */
+/*   Description:  Dir counter initial value                            */
+#define SH_Y_CFG_DIR_COUNTER_INIT_SHFT           2
+#define SH_Y_CFG_DIR_COUNTER_INIT_MASK           0x00000000000000fc
+
+/*   SH_Y_CFG_TA_DLYS                                                   */
+/*   Description:  Turn around delays                                   */
+#define SH_Y_CFG_TA_DLYS_SHFT                    8
+#define SH_Y_CFG_TA_DLYS_MASK                    0x000000ffffffff00
+
+/*   SH_Y_CFG_DA_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a data read request                */
+#define SH_Y_CFG_DA_BB_CLR_SHFT                  40
+#define SH_Y_CFG_DA_BB_CLR_MASK                  0x00000f0000000000
+
+/*   SH_Y_CFG_DC_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a directory cache read request     */
+#define SH_Y_CFG_DC_BB_CLR_SHFT                  44
+#define SH_Y_CFG_DC_BB_CLR_MASK                  0x0000f00000000000
+
+/*   SH_Y_CFG_WT_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for all write request                  */
+#define SH_Y_CFG_WT_BB_CLR_SHFT                  48
+#define SH_Y_CFG_WT_BB_CLR_MASK                  0x000f000000000000
+
+/*   SH_Y_CFG_SSO_WT_EN                                                 */
+/*   Description:  Simultaneous switching enabled on output data pins  */
+#define SH_Y_CFG_SSO_WT_EN_SHFT                  52
+#define SH_Y_CFG_SSO_WT_EN_MASK                  0x0010000000000000
+
+/*   SH_Y_CFG_TRCD2_EN                                                  */
+/*   Description:  Trcd, ras to cas delay of 2 CPs enabled              */
+#define SH_Y_CFG_TRCD2_EN_SHFT                   53
+#define SH_Y_CFG_TRCD2_EN_MASK                   0x0020000000000000
+
+/*   SH_Y_CFG_TRCD4_EN                                                  */
+/*   Description:  Trcd, ras to case delay of 4 CPs enabled             */
+#define SH_Y_CFG_TRCD4_EN_SHFT                   54
+#define SH_Y_CFG_TRCD4_EN_MASK                   0x0040000000000000
+
+/*   SH_Y_CFG_REQ_CNTR_DIS                                              */
+/*   Description:  Request delay counter disabled                       */
+#define SH_Y_CFG_REQ_CNTR_DIS_SHFT               55
+#define SH_Y_CFG_REQ_CNTR_DIS_MASK               0x0080000000000000
+
+/*   SH_Y_CFG_REQ_CNTR_VAL                                              */
+/*   Description:  Request counter delay value in CPs                   */
+#define SH_Y_CFG_REQ_CNTR_VAL_SHFT               56
+#define SH_Y_CFG_REQ_CNTR_VAL_MASK               0x3f00000000000000
+
+/*   SH_Y_CFG_INV_CAS_ADDR                                              */
+/*   Description:  Invert cas address bits 3 to 7                       */
+#define SH_Y_CFG_INV_CAS_ADDR_SHFT               62
+#define SH_Y_CFG_INV_CAS_ADDR_MASK               0x4000000000000000
+
+/*   SH_Y_CFG_CLR_DIR_CACHE                                             */
+/*   Description:  Clear directory cache tags                           */
+#define SH_Y_CFG_CLR_DIR_CACHE_SHFT              63
+#define SH_Y_CFG_CLR_DIR_CACHE_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_Y_DQCT_CFG                            0x0000000100010048
+#define SH_Y_DQCT_CFG_MASK                       0x0000000000ffffff
+#define SH_Y_DQCT_CFG_INIT                       0x0000000000585418
+
+/*   SH_Y_DQCT_CFG_RD_SEL                                               */
+/*   Description:  Read data select                                     */
+#define SH_Y_DQCT_CFG_RD_SEL_SHFT                0
+#define SH_Y_DQCT_CFG_RD_SEL_MASK                0x000000000000000f
+
+/*   SH_Y_DQCT_CFG_WT_SEL                                               */
+/*   Description:  Write data select                                    */
+#define SH_Y_DQCT_CFG_WT_SEL_SHFT                4
+#define SH_Y_DQCT_CFG_WT_SEL_MASK                0x00000000000000f0
+
+/*   SH_Y_DQCT_CFG_DTA_RD_SEL                                           */
+/*   Description:  Data ready read select                               */
+#define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT            8
+#define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK            0x0000000000000f00
+
+/*   SH_Y_DQCT_CFG_DTA_WT_SEL                                           */
+/*   Description:  Data ready write select                              */
+#define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT            12
+#define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK            0x000000000000f000
+
+/*   SH_Y_DQCT_CFG_DIR_RD_SEL                                           */
+/*   Description:  Dir ready read select                                */
+#define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT            16
+#define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK            0x00000000000f0000
+
+/*   SH_Y_DQCT_CFG_MDIR_RD_SEL                                          */
+/*   Description:  Dir ready read select                                */
+#define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT           20
+#define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK           0x0000000000f00000
+
+/* ==================================================================== */
+/*                   Register "SH_Y_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#define SH_Y_REFRESH_CONTROL                     0x0000000100010050
+#define SH_Y_REFRESH_CONTROL_MASK                0x000000000fffffff
+#define SH_Y_REFRESH_CONTROL_INIT                0x00000000009cc300
+
+/*   SH_Y_REFRESH_CONTROL_ENABLE                                        */
+/*   Description:  Refresh enable                                       */
+#define SH_Y_REFRESH_CONTROL_ENABLE_SHFT         0
+#define SH_Y_REFRESH_CONTROL_ENABLE_MASK         0x00000000000000ff
+
+/*   SH_Y_REFRESH_CONTROL_INTERVAL                                      */
+/*   Description:  Refresh interval in core CPs                         */
+#define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT       8
+#define SH_Y_REFRESH_CONTROL_INTERVAL_MASK       0x000000000001ff00
+
+/*   SH_Y_REFRESH_CONTROL_HOLD                                          */
+/*   Description:  Refresh hold                                         */
+#define SH_Y_REFRESH_CONTROL_HOLD_SHFT           17
+#define SH_Y_REFRESH_CONTROL_HOLD_MASK           0x00000000007e0000
+
+/*   SH_Y_REFRESH_CONTROL_INTERLEAVE                                    */
+/*   Description:  Refresh interleave                                   */
+#define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT     23
+#define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK     0x0000000000800000
+
+/*   SH_Y_REFRESH_CONTROL_HALF_RATE                                     */
+/*   Description:  Refresh half rate                                    */
+#define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT      24
+#define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK      0x000000000f000000
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_RED_BLACK"                      */
+/*                     MD fairness watchdog timers                      */
+/* ==================================================================== */
+
+#define SH_MEM_RED_BLACK                         0x0000000100010058
+#define SH_MEM_RED_BLACK_MASK                    0x000fffffffffffff
+#define SH_MEM_RED_BLACK_INIT                    0x0000000040000400
+
+/*   SH_MEM_RED_BLACK_TIME                                              */
+/*   Description:  Clocks to tag references with a given color          */
+#define SH_MEM_RED_BLACK_TIME_SHFT               0
+#define SH_MEM_RED_BLACK_TIME_MASK               0x000000000000ffff
+
+/*   SH_MEM_RED_BLACK_ERR_TIME                                          */
+/*   Description:  Max clocks to wait after red/black change for old c  */
+/*  olor to clear.                                                      */
+#define SH_MEM_RED_BLACK_ERR_TIME_SHFT           16
+#define SH_MEM_RED_BLACK_ERR_TIME_MASK           0x000fffffffff0000
+
+/* ==================================================================== */
+/*                      Register "SH_MISC_MEM_CFG"                      */
+/* ==================================================================== */
+
+#define SH_MISC_MEM_CFG                          0x0000000100010060
+#define SH_MISC_MEM_CFG_MASK                     0x0013f1f1fff3f3ff
+#define SH_MISC_MEM_CFG_INIT                     0x0000000000010107
+
+/*   SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE                              */
+/*   Description:  enables the use of express headers from md to pi     */
+#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0
+#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001
+
+/*   SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE                                 */
+/*   Description:  enables the use of speculative headers from md to p  */
+#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT  1
+#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK  0x0000000000000002
+
+/*   SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE                                  */
+/*   Description:  enables bypass path for requests going through ac    */
+#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT   2
+#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK   0x0000000000000004
+
+/*   SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI                                   */
+/*   Description:  disables a one clock delay of XN read data           */
+#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT    3
+#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK    0x0000000000000008
+
+/*   SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD                         */
+/*   Description:  point at which data writes get higher priority       */
+#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4
+#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0
+
+/*   SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD                        */
+/*   Description:  point at which dir cache writes get higher priority  */
+#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12
+#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000
+
+/*   SH_MISC_MEM_CFG_THROTTLE_CNT                                       */
+/*   Description:  number of clocks between accepting references        */
+#define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT        20
+#define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK        0x000000000ff00000
+
+/*   SH_MISC_MEM_CFG_DISABLED_READ_TNUMS                                */
+/*   Description:  number of read tnums to take out of circulation      */
+#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28
+#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000
+
+/*   SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS                               */
+/*   Description:  number of write tnums to take out of circulation     */
+#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36
+#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000
+
+/*   SH_MISC_MEM_CFG_DISABLED_VICTIMS                                   */
+/*   Description:  number of dir cache victim buffers to take out of c  */
+/*  irculation in each quadrant of the MD                               */
+#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT    44
+#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK    0x0003f00000000000
+
+/*   SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE                              */
+/*   Description:  enables plane alternating for replies to XN          */
+#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52
+#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_RQ_CRD_CTL"                     */
+/*                  pio_rq Credit Circulation Control                   */
+/* ==================================================================== */
+
+#define SH_PIO_RQ_CRD_CTL                        0x0000000100010068
+#define SH_PIO_RQ_CRD_CTL_MASK                   0x000000000000003f
+#define SH_PIO_RQ_CRD_CTL_INIT                   0x0000000000000002
+
+/*   SH_PIO_RQ_CRD_CTL_DEPTH                                            */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT             0
+#define SH_PIO_RQ_CRD_CTL_DEPTH_MASK             0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RQ_CRD_CTL"                    */
+/*                 pi_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_PI_MD_RQ_CRD_CTL                      0x0000000100010070
+#define SH_PI_MD_RQ_CRD_CTL_MASK                 0x000000000000003f
+#define SH_PI_MD_RQ_CRD_CTL_INIT                 0x0000000000000008
+
+/*   SH_PI_MD_RQ_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT           0
+#define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RP_CRD_CTL"                    */
+/*                 pi_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_PI_MD_RP_CRD_CTL                      0x0000000100010078
+#define SH_PI_MD_RP_CRD_CTL_MASK                 0x000000000000003f
+#define SH_PI_MD_RP_CRD_CTL_INIT                 0x0000000000000004
+
+/*   SH_PI_MD_RP_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT           0
+#define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RQ_CRD_CTL"                    */
+/*                 xn_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_RQ_CRD_CTL                      0x0000000100010080
+#define SH_XN_MD_RQ_CRD_CTL_MASK                 0x000000000000003f
+#define SH_XN_MD_RQ_CRD_CTL_INIT                 0x0000000000000008
+
+/*   SH_XN_MD_RQ_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT           0
+#define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RP_CRD_CTL"                    */
+/*                 xn_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_RP_CRD_CTL                      0x0000000100010088
+#define SH_XN_MD_RP_CRD_CTL_MASK                 0x000000000000003f
+#define SH_XN_MD_RP_CRD_CTL_INIT                 0x0000000000000004
+
+/*   SH_XN_MD_RP_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT           0
+#define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG0                                0x0000000100020000
+#define SH_X_TAG0_MASK                           0x00000000000fffff
+#define SH_X_TAG0_INIT                           0x0000000000000000
+
+/*   SH_X_TAG0_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG0_TAG_SHFT                       0
+#define SH_X_TAG0_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG1                                0x0000000100020008
+#define SH_X_TAG1_MASK                           0x00000000000fffff
+#define SH_X_TAG1_INIT                           0x0000000000000000
+
+/*   SH_X_TAG1_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG1_TAG_SHFT                       0
+#define SH_X_TAG1_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG2                                0x0000000100020010
+#define SH_X_TAG2_MASK                           0x00000000000fffff
+#define SH_X_TAG2_INIT                           0x0000000000000000
+
+/*   SH_X_TAG2_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG2_TAG_SHFT                       0
+#define SH_X_TAG2_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG3                                0x0000000100020018
+#define SH_X_TAG3_MASK                           0x00000000000fffff
+#define SH_X_TAG3_INIT                           0x0000000000000000
+
+/*   SH_X_TAG3_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG3_TAG_SHFT                       0
+#define SH_X_TAG3_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG4                                0x0000000100020020
+#define SH_X_TAG4_MASK                           0x00000000000fffff
+#define SH_X_TAG4_INIT                           0x0000000000000000
+
+/*   SH_X_TAG4_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG4_TAG_SHFT                       0
+#define SH_X_TAG4_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG5                                0x0000000100020028
+#define SH_X_TAG5_MASK                           0x00000000000fffff
+#define SH_X_TAG5_INIT                           0x0000000000000000
+
+/*   SH_X_TAG5_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG5_TAG_SHFT                       0
+#define SH_X_TAG5_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG6                                0x0000000100020030
+#define SH_X_TAG6_MASK                           0x00000000000fffff
+#define SH_X_TAG6_INIT                           0x0000000000000000
+
+/*   SH_X_TAG6_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG6_TAG_SHFT                       0
+#define SH_X_TAG6_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG7                                0x0000000100020038
+#define SH_X_TAG7_MASK                           0x00000000000fffff
+#define SH_X_TAG7_INIT                           0x0000000000000000
+
+/*   SH_X_TAG7_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG7_TAG_SHFT                       0
+#define SH_X_TAG7_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG0                                0x0000000100020040
+#define SH_Y_TAG0_MASK                           0x00000000000fffff
+#define SH_Y_TAG0_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG0_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG0_TAG_SHFT                       0
+#define SH_Y_TAG0_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG1                                0x0000000100020048
+#define SH_Y_TAG1_MASK                           0x00000000000fffff
+#define SH_Y_TAG1_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG1_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG1_TAG_SHFT                       0
+#define SH_Y_TAG1_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG2                                0x0000000100020050
+#define SH_Y_TAG2_MASK                           0x00000000000fffff
+#define SH_Y_TAG2_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG2_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG2_TAG_SHFT                       0
+#define SH_Y_TAG2_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG3                                0x0000000100020058
+#define SH_Y_TAG3_MASK                           0x00000000000fffff
+#define SH_Y_TAG3_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG3_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG3_TAG_SHFT                       0
+#define SH_Y_TAG3_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG4                                0x0000000100020060
+#define SH_Y_TAG4_MASK                           0x00000000000fffff
+#define SH_Y_TAG4_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG4_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG4_TAG_SHFT                       0
+#define SH_Y_TAG4_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG5                                0x0000000100020068
+#define SH_Y_TAG5_MASK                           0x00000000000fffff
+#define SH_Y_TAG5_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG5_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG5_TAG_SHFT                       0
+#define SH_Y_TAG5_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG6                                0x0000000100020070
+#define SH_Y_TAG6_MASK                           0x00000000000fffff
+#define SH_Y_TAG6_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG6_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG6_TAG_SHFT                       0
+#define SH_Y_TAG6_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG7                                0x0000000100020078
+#define SH_Y_TAG7_MASK                           0x00000000000fffff
+#define SH_Y_TAG7_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG7_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG7_TAG_SHFT                       0
+#define SH_Y_TAG7_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_BASE"                      */
+/*                        mmr/bist base address                         */
+/* ==================================================================== */
+
+#define SH_MMRBIST_BASE                          0x0000000100020080
+#define SH_MMRBIST_BASE_MASK                     0x0003fffffffffff8
+#define SH_MMRBIST_BASE_INIT                     0x0000000000000000
+
+/*   SH_MMRBIST_BASE_DWORD_ADDR                                         */
+/*   Description:  bits 49:3 of the memory address                      */
+#define SH_MMRBIST_BASE_DWORD_ADDR_SHFT          3
+#define SH_MMRBIST_BASE_DWORD_ADDR_MASK          0x0003fffffffffff8
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_CTL"                       */
+/*                          Bist base address                           */
+/* ==================================================================== */
+
+#define SH_MMRBIST_CTL                           0x0000000100020088
+#define SH_MMRBIST_CTL_MASK                      0x0000177f7fffffff
+#define SH_MMRBIST_CTL_INIT                      0x0000000000000000
+
+/*   SH_MMRBIST_CTL_BLOCK_LENGTH                                        */
+/*   Description:  number of dwords in operation                        */
+#define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT         0
+#define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK         0x000000007fffffff
+
+/*   SH_MMRBIST_CTL_CMD                                                 */
+/*   Description:  mmr/bist function                                    */
+#define SH_MMRBIST_CTL_CMD_SHFT                  32
+#define SH_MMRBIST_CTL_CMD_MASK                  0x0000007f00000000
+
+/*   SH_MMRBIST_CTL_IN_PROGRESS                                         */
+/*   Description:  writing a 1 starts operation, hardware clears on co  */
+/*  mpletion                                                            */
+#define SH_MMRBIST_CTL_IN_PROGRESS_SHFT          40
+#define SH_MMRBIST_CTL_IN_PROGRESS_MASK          0x0000010000000000
+
+/*   SH_MMRBIST_CTL_FAIL                                                */
+/*   Description:  mmr/bist had a data or address error                 */
+#define SH_MMRBIST_CTL_FAIL_SHFT                 41
+#define SH_MMRBIST_CTL_FAIL_MASK                 0x0000020000000000
+
+/*   SH_MMRBIST_CTL_MEM_IDLE                                            */
+/*   Description:  all memory activity is complete                      */
+#define SH_MMRBIST_CTL_MEM_IDLE_SHFT             42
+#define SH_MMRBIST_CTL_MEM_IDLE_MASK             0x0000040000000000
+
+/*   SH_MMRBIST_CTL_RESET_STATE                                         */
+/*   Description:  writing a 1 resets mmrbist hardware, hardware clear  */
+/*  s on completion                                                     */
+#define SH_MMRBIST_CTL_RESET_STATE_SHFT          44
+#define SH_MMRBIST_CTL_RESET_STATE_MASK          0x0000100000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_DATA_CFG"                    */
+/*                configuration for md debug data muxes                 */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_DATA_CFG                      0x0000000100020100
+#define SH_MD_DBUG_DATA_CFG_MASK                 0x7777777777777777
+#define SH_MD_DBUG_DATA_CFG_INIT                 0x0000000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble0              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT  4
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK  0x0000000000000070
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble1              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT  12
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK  0x0000000000007000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble2              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT  20
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK  0x0000000000700000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble3              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT  28
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK  0x0000000070000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble4              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT  36
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK  0x0000007000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble5              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT  44
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK  0x0000700000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble6              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT  52
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK  0x0070000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble7              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT  60
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK  0x7000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DBUG_TRIGGER_CFG"                   */
+/*                 configuration for md debug triggers                  */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_TRIGGER_CFG                   0x0000000100020108
+#define SH_MD_DBUG_TRIGGER_CFG_MASK              0xf777777777777777
+#define SH_MD_DBUG_TRIGGER_CFG_INIT              0x0000000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble0              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble1              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble2              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble3              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble4              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble5              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble6              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble7              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_ENABLE                                      */
+/*   Description:  enables triggering on pattern match                  */
+#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT       63
+#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_COMPARE"                     */
+/*                  md debug compare pattern and mask                   */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_COMPARE                       0x0000000100020110
+#define SH_MD_DBUG_COMPARE_MASK                  0xffffffffffffffff
+#define SH_MD_DBUG_COMPARE_INIT                  0x0000000000000000
+
+/*   SH_MD_DBUG_COMPARE_PATTERN                                         */
+/*   Description:  pattern against which to compare dbug data for trig  */
+#define SH_MD_DBUG_COMPARE_PATTERN_SHFT          0
+#define SH_MD_DBUG_COMPARE_PATTERN_MASK          0x00000000ffffffff
+
+/*   SH_MD_DBUG_COMPARE_MASK                                            */
+/*   Description:  bits to include in compare of dbug data for trigger  */
+#define SH_MD_DBUG_COMPARE_MASK_SHFT             32
+#define SH_MD_DBUG_COMPARE_MASK_MASK             0xffffffff00000000
+
+/* ==================================================================== */
+/*                     Register "SH_X_MOD_DBUG_SEL"                     */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#define SH_X_MOD_DBUG_SEL                        0x0000000100020118
+#define SH_X_MOD_DBUG_SEL_MASK                   0x03ffffffffffffff
+#define SH_X_MOD_DBUG_SEL_INIT                   0x0000000000000000
+
+/*   SH_X_MOD_DBUG_SEL_TAG_SEL                                          */
+/*   Description:  tagmgr select                                        */
+#define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT           0
+#define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK           0x00000000000000ff
+
+/*   SH_X_MOD_DBUG_SEL_WBQ_SEL                                          */
+/*   Description:  wbqtg select                                         */
+#define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT           8
+#define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK           0x000000000000ff00
+
+/*   SH_X_MOD_DBUG_SEL_ARB_SEL                                          */
+/*   Description:  arbque select                                        */
+#define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT           16
+#define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK           0x0000000000ff0000
+
+/*   SH_X_MOD_DBUG_SEL_ATL_SEL                                          */
+/*   Description:  aintl select                                         */
+#define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT           24
+#define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK           0x00000007ff000000
+
+/*   SH_X_MOD_DBUG_SEL_ATR_SEL                                          */
+/*   Description:  aintr select                                         */
+#define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT           35
+#define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK           0x00003ff800000000
+
+/*   SH_X_MOD_DBUG_SEL_DQL_SEL                                          */
+/*   Description:  dqctr select                                         */
+#define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT           46
+#define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK           0x000fc00000000000
+
+/*   SH_X_MOD_DBUG_SEL_DQR_SEL                                          */
+/*   Description:  dqctl select                                         */
+#define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT           52
+#define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK           0x03f0000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DBUG_SEL"                       */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#define SH_X_DBUG_SEL                            0x0000000100020120
+#define SH_X_DBUG_SEL_MASK                       0x0000000000ffffff
+#define SH_X_DBUG_SEL_INIT                       0x0000000000000000
+
+/*   SH_X_DBUG_SEL_DBG_SEL                                              */
+/*   Description:  debug select                                         */
+#define SH_X_DBUG_SEL_DBG_SEL_SHFT               0
+#define SH_X_DBUG_SEL_DBG_SEL_MASK               0x0000000000ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_X_LADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#define SH_X_LADDR_CMP                           0x0000000100020128
+#define SH_X_LADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_X_LADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_X_LADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_X_LADDR_CMP_CMP_VAL_SHFT              0
+#define SH_X_LADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_X_LADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_X_LADDR_CMP_MASK_VAL_SHFT             32
+#define SH_X_LADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                      Register "SH_X_RADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#define SH_X_RADDR_CMP                           0x0000000100020130
+#define SH_X_RADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_X_RADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_X_RADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_X_RADDR_CMP_CMP_VAL_SHFT              0
+#define SH_X_RADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_X_RADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_X_RADDR_CMP_MASK_VAL_SHFT             32
+#define SH_X_RADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_CMP"                        */
+/*                        MD acx tagmgr compare                         */
+/* ==================================================================== */
+
+#define SH_X_TAG_CMP                             0x0000000100020138
+#define SH_X_TAG_CMP_MASK                        0x007fffffffffffff
+#define SH_X_TAG_CMP_INIT                        0x0000000000000000
+
+/*   SH_X_TAG_CMP_CMD                                                   */
+/*   Description:  Command compare value                                */
+#define SH_X_TAG_CMP_CMD_SHFT                    0
+#define SH_X_TAG_CMP_CMD_MASK                    0x00000000000000ff
+
+/*   SH_X_TAG_CMP_ADDR                                                  */
+/*   Description:  Address compare value                                */
+#define SH_X_TAG_CMP_ADDR_SHFT                   8
+#define SH_X_TAG_CMP_ADDR_MASK                   0x000001ffffffff00
+
+/*   SH_X_TAG_CMP_SRC                                                   */
+/*   Description:  Source compare value                                 */
+#define SH_X_TAG_CMP_SRC_SHFT                    41
+#define SH_X_TAG_CMP_SRC_MASK                    0x007ffe0000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_MASK"                       */
+/*                          MD acx tagmgr mask                          */
+/* ==================================================================== */
+
+#define SH_X_TAG_MASK                            0x0000000100020140
+#define SH_X_TAG_MASK_MASK                       0x007fffffffffffff
+#define SH_X_TAG_MASK_INIT                       0x0000000000000000
+
+/*   SH_X_TAG_MASK_CMD                                                  */
+/*   Description:  Command compare value                                */
+#define SH_X_TAG_MASK_CMD_SHFT                   0
+#define SH_X_TAG_MASK_CMD_MASK                   0x00000000000000ff
+
+/*   SH_X_TAG_MASK_ADDR                                                 */
+/*   Description:  Address compare value                                */
+#define SH_X_TAG_MASK_ADDR_SHFT                  8
+#define SH_X_TAG_MASK_ADDR_MASK                  0x000001ffffffff00
+
+/*   SH_X_TAG_MASK_SRC                                                  */
+/*   Description:  Source compare value                                 */
+#define SH_X_TAG_MASK_SRC_SHFT                   41
+#define SH_X_TAG_MASK_SRC_MASK                   0x007ffe0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_Y_MOD_DBUG_SEL"                     */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#define SH_Y_MOD_DBUG_SEL                        0x0000000100020148
+#define SH_Y_MOD_DBUG_SEL_MASK                   0x03ffffffffffffff
+#define SH_Y_MOD_DBUG_SEL_INIT                   0x0000000000000000
+
+/*   SH_Y_MOD_DBUG_SEL_TAG_SEL                                          */
+/*   Description:  tagmgr select                                        */
+#define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT           0
+#define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK           0x00000000000000ff
+
+/*   SH_Y_MOD_DBUG_SEL_WBQ_SEL                                          */
+/*   Description:  wbqtg select                                         */
+#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT           8
+#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK           0x000000000000ff00
+
+/*   SH_Y_MOD_DBUG_SEL_ARB_SEL                                          */
+/*   Description:  arbque select                                        */
+#define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT           16
+#define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK           0x0000000000ff0000
+
+/*   SH_Y_MOD_DBUG_SEL_ATL_SEL                                          */
+/*   Description:  aintl select                                         */
+#define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT           24
+#define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK           0x00000007ff000000
+
+/*   SH_Y_MOD_DBUG_SEL_ATR_SEL                                          */
+/*   Description:  aintr select                                         */
+#define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT           35
+#define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK           0x00003ff800000000
+
+/*   SH_Y_MOD_DBUG_SEL_DQL_SEL                                          */
+/*   Description:  dqctr select                                         */
+#define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT           46
+#define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK           0x000fc00000000000
+
+/*   SH_Y_MOD_DBUG_SEL_DQR_SEL                                          */
+/*   Description:  dqctl select                                         */
+#define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT           52
+#define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK           0x03f0000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DBUG_SEL"                       */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#define SH_Y_DBUG_SEL                            0x0000000100020150
+#define SH_Y_DBUG_SEL_MASK                       0x0000000000ffffff
+#define SH_Y_DBUG_SEL_INIT                       0x0000000000000000
+
+/*   SH_Y_DBUG_SEL_DBG_SEL                                              */
+/*   Description:  debug select                                         */
+#define SH_Y_DBUG_SEL_DBG_SEL_SHFT               0
+#define SH_Y_DBUG_SEL_DBG_SEL_MASK               0x0000000000ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_Y_LADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#define SH_Y_LADDR_CMP                           0x0000000100020158
+#define SH_Y_LADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_Y_LADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_Y_LADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_Y_LADDR_CMP_CMP_VAL_SHFT              0
+#define SH_Y_LADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_Y_LADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_Y_LADDR_CMP_MASK_VAL_SHFT             32
+#define SH_Y_LADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                      Register "SH_Y_RADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#define SH_Y_RADDR_CMP                           0x0000000100020160
+#define SH_Y_RADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_Y_RADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_Y_RADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_Y_RADDR_CMP_CMP_VAL_SHFT              0
+#define SH_Y_RADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_Y_RADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_Y_RADDR_CMP_MASK_VAL_SHFT             32
+#define SH_Y_RADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_CMP"                        */
+/*                        MD acy tagmgr compare                         */
+/* ==================================================================== */
+
+#define SH_Y_TAG_CMP                             0x0000000100020168
+#define SH_Y_TAG_CMP_MASK                        0x007fffffffffffff
+#define SH_Y_TAG_CMP_INIT                        0x0000000000000000
+
+/*   SH_Y_TAG_CMP_CMD                                                   */
+/*   Description:  Command compare value                                */
+#define SH_Y_TAG_CMP_CMD_SHFT                    0
+#define SH_Y_TAG_CMP_CMD_MASK                    0x00000000000000ff
+
+/*   SH_Y_TAG_CMP_ADDR                                                  */
+/*   Description:  Address compare value                                */
+#define SH_Y_TAG_CMP_ADDR_SHFT                   8
+#define SH_Y_TAG_CMP_ADDR_MASK                   0x000001ffffffff00
+
+/*   SH_Y_TAG_CMP_SRC                                                   */
+/*   Description:  Source compare value                                 */
+#define SH_Y_TAG_CMP_SRC_SHFT                    41
+#define SH_Y_TAG_CMP_SRC_MASK                    0x007ffe0000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_MASK"                       */
+/*                          MD acy tagmgr mask                          */
+/* ==================================================================== */
+
+#define SH_Y_TAG_MASK                            0x0000000100020170
+#define SH_Y_TAG_MASK_MASK                       0x007fffffffffffff
+#define SH_Y_TAG_MASK_INIT                       0x0000000000000000
+
+/*   SH_Y_TAG_MASK_CMD                                                  */
+/*   Description:  Command compare value                                */
+#define SH_Y_TAG_MASK_CMD_SHFT                   0
+#define SH_Y_TAG_MASK_CMD_MASK                   0x00000000000000ff
+
+/*   SH_Y_TAG_MASK_ADDR                                                 */
+/*   Description:  Address compare value                                */
+#define SH_Y_TAG_MASK_ADDR_SHFT                  8
+#define SH_Y_TAG_MASK_ADDR_MASK                  0x000001ffffffff00
+
+/*   SH_Y_TAG_MASK_SRC                                                  */
+/*   Description:  Source compare value                                 */
+#define SH_Y_TAG_MASK_SRC_SHFT                   41
+#define SH_Y_TAG_MASK_SRC_MASK                   0x007ffe0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_JNR_DBUG_DATA_CFG"                  */
+/*              configuration for md jnr debug data muxes               */
+/* ==================================================================== */
+
+#define SH_MD_JNR_DBUG_DATA_CFG                  0x0000000100020178
+#define SH_MD_JNR_DBUG_DATA_CFG_MASK             0x0000000077777777
+#define SH_MD_JNR_DBUG_DATA_CFG_INIT             0x0000000000000000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL                                */
+/*   Description:  selects which nibble drives nibble0                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL                                */
+/*   Description:  selects which nibble drives nibble1                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL                                */
+/*   Description:  selects which nibble drives nibble2                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL                                */
+/*   Description:  selects which nibble drives nibble3                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL                                */
+/*   Description:  selects which nibble drives nibble4                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL                                */
+/*   Description:  selects which nibble drives nibble5                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL                                */
+/*   Description:  selects which nibble drives nibble6                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL                                */
+/*   Description:  selects which nibble drives nibble7                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LAST_CREDIT"                     */
+/*                 captures last credit values on reset                 */
+/* ==================================================================== */
+
+#define SH_MD_LAST_CREDIT                        0x0000000100020180
+#define SH_MD_LAST_CREDIT_MASK                   0x0000003f3f3f3f3f
+#define SH_MD_LAST_CREDIT_INIT                   0x0000000000000000
+
+/*   SH_MD_LAST_CREDIT_RQ_TO_PI                                         */
+/*   Description:  capture of request credits to pi                     */
+#define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT          0
+#define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK          0x000000000000003f
+
+/*   SH_MD_LAST_CREDIT_RP_TO_PI                                         */
+/*   Description:  capture of reply credits to pi                       */
+#define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT          8
+#define SH_MD_LAST_CREDIT_RP_TO_PI_MASK          0x0000000000003f00
+
+/*   SH_MD_LAST_CREDIT_RQ_TO_XN                                         */
+/*   Description:  capture of request credits to xn                     */
+#define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT          16
+#define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK          0x00000000003f0000
+
+/*   SH_MD_LAST_CREDIT_RP_TO_XN                                         */
+/*   Description:  capture of reply credits to xn                       */
+#define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT          24
+#define SH_MD_LAST_CREDIT_RP_TO_XN_MASK          0x000000003f000000
+
+/*   SH_MD_LAST_CREDIT_TO_LB                                            */
+/*   Description:  capture of credits to pi                             */
+#define SH_MD_LAST_CREDIT_TO_LB_SHFT             32
+#define SH_MD_LAST_CREDIT_TO_LB_MASK             0x0000003f00000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_ADDR"                    */
+/*                   Address capture address register                   */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_ADDR                      0x0000000100020300
+#define SH_MEM_CAPTURE_ADDR_MASK                 0x00000ffffffffff8
+#define SH_MEM_CAPTURE_ADDR_INIT                 0x0000000000000000
+
+/*   SH_MEM_CAPTURE_ADDR_ADDR                                           */
+/*   Description:  upper bits of address                                */
+#define SH_MEM_CAPTURE_ADDR_ADDR_SHFT            3
+#define SH_MEM_CAPTURE_ADDR_ADDR_MASK            0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_ADDR_CMD                                            */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_ADDR_CMD_SHFT             36
+#define SH_MEM_CAPTURE_ADDR_CMD_MASK             0x00000ff000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_MASK"                    */
+/*                    Address capture mask register                     */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_MASK                      0x0000000100020308
+#define SH_MEM_CAPTURE_MASK_MASK                 0x00003ffffffffff8
+#define SH_MEM_CAPTURE_MASK_INIT                 0x0000000000000000
+
+/*   SH_MEM_CAPTURE_MASK_ADDR                                           */
+/*   Description:  upper bits of address                                */
+#define SH_MEM_CAPTURE_MASK_ADDR_SHFT            3
+#define SH_MEM_CAPTURE_MASK_ADDR_MASK            0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_MASK_CMD                                            */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_MASK_CMD_SHFT             36
+#define SH_MEM_CAPTURE_MASK_CMD_MASK             0x00000ff000000000
+
+/*   SH_MEM_CAPTURE_MASK_ENABLE_LOCAL                                   */
+/*   Description:  capture references originating locally               */
+#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT    44
+#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK    0x0000100000000000
+
+/*   SH_MEM_CAPTURE_MASK_ENABLE_REMOTE                                  */
+/*   Description:  capture references originating remotely              */
+#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT   45
+#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK   0x0000200000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_HDR"                     */
+/*                   Address capture header register                    */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_HDR                       0x0000000100020310
+#define SH_MEM_CAPTURE_HDR_MASK                  0xfffffffffffffff8
+#define SH_MEM_CAPTURE_HDR_INIT                  0x0000000000000000
+
+/*   SH_MEM_CAPTURE_HDR_ADDR                                            */
+/*   Description:  upper bits of reference address                      */
+#define SH_MEM_CAPTURE_HDR_ADDR_SHFT             3
+#define SH_MEM_CAPTURE_HDR_ADDR_MASK             0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_HDR_CMD                                             */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_HDR_CMD_SHFT              36
+#define SH_MEM_CAPTURE_HDR_CMD_MASK              0x00000ff000000000
+
+/*   SH_MEM_CAPTURE_HDR_SRC                                             */
+/*   Description:  source node of reference                             */
+#define SH_MEM_CAPTURE_HDR_SRC_SHFT              44
+#define SH_MEM_CAPTURE_HDR_SRC_MASK              0x03fff00000000000
+
+/*   SH_MEM_CAPTURE_HDR_CNTR                                            */
+/*   Description:  increments on every capture                          */
+#define SH_MEM_CAPTURE_HDR_CNTR_SHFT             58
+#define SH_MEM_CAPTURE_HDR_CNTR_MASK             0xfc00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_CONFIG                0x0000000100030000
+#define SH_MD_DQLP_MMR_DIR_CONFIG_MASK           0x000000000000001f
+#define SH_MD_DQLP_MMR_DIR_CONFIG_INIT           0x0000000000000010
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE                                 */
+/*   Description:  system size code                                     */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT  0
+#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK  0x0000000000000007
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC                                */
+/*   Description:  enable directory ecc correction                      */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS                               */
+/*   Description:  enable local poisoning for dir table fall-through    */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0              0x0000000100030100
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1              0x0000000100030110
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2              0x0000000100030120
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3              0x0000000100030130
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0               0x0000000100030200
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1               0x0000000100030210
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2               0x0000000100030220
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3               0x0000000100030230
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4               0x0000000100030240
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5               0x0000000100030250
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6               0x0000000100030260
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7               0x0000000100030270
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0               0x0000000100030300
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC0_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1               0x0000000100030310
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC1_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2               0x0000000100030320
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC2_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3               0x0000000100030330
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC3_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4               0x0000000100030340
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC4_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5               0x0000000100030350
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC5_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6               0x0000000100030360
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC6_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7               0x0000000100030370
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC7_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TIMER                 0x0000000100030400
+#define SH_MD_DQLP_MMR_DIR_TIMER_MASK            0x00000000003fffff
+#define SH_MD_DQLP_MMR_DIR_TIMER_INIT            0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV                                 */
+/*   Description:  timer divide register                                */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT  0
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK  0x0000000000000fff
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN                                  */
+/*   Description:  timer enable                                         */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT   12
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK   0x0000000000001000
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR                                 */
+/*   Description:  value of current timer                               */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT  13
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK  0x00000000003fe000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY           0x0000000100031000
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK      0x03ffffffffffffff
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA                                */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB                                */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI                                 */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT  52
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK  0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC                                 */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT  55
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK  0x0380000000000000
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC             0x0000000100031010
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK        0x0000000000003fff
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT        0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA                                  */
+/*   Description:  XOR bits for directory ECC group 1                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT   0
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK   0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB                                  */
+/*   Description:  XOR bits for directory ECC group 2                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT   7
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK   0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY         0x0000000100032000
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC           0x0000000100032010
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY         0x0000000100032800
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC           0x0000000100032810
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XCERR1                    0x0000000100033000
+#define SH_MD_DQLP_MMR_XCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_XCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_XCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XCERR2                    0x0000000100033010
+#define SH_MD_DQLP_MMR_XCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_XCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XUERR1                    0x0000000100033020
+#define SH_MD_DQLP_MMR_XUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_XUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_XUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XUERR2                    0x0000000100033030
+#define SH_MD_DQLP_MMR_XUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_XUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPERR                     0x0000000100033040
+#define SH_MD_DQLP_MMR_XPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQLP_MMR_XPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQLP_MMR_XPERR_DIR_SHFT            0
+#define SH_MD_DQLP_MMR_XPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_XPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQLP_MMR_XPERR_CMD_SHFT            26
+#define SH_MD_DQLP_MMR_XPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQLP_MMR_XPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQLP_MMR_XPERR_SRC_SHFT            34
+#define SH_MD_DQLP_MMR_XPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQLP_MMR_XPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT          48
+#define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT           49
+#define SH_MD_DQLP_MMR_XPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_XPERR_COR_SHFT            50
+#define SH_MD_DQLP_MMR_XPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_XPERR_UNC_SHFT            51
+#define SH_MD_DQLP_MMR_XPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT          52
+#define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQLP_MMR_XPERR_VAL_SHFT            60
+#define SH_MD_DQLP_MMR_XPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQLP_MMR_XPERR_MORE_SHFT           61
+#define SH_MD_DQLP_MMR_XPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQLP_MMR_XPERR_ARM_SHFT            62
+#define SH_MD_DQLP_MMR_XPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YCERR1                    0x0000000100033800
+#define SH_MD_DQLP_MMR_YCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_YCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_YCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YCERR2                    0x0000000100033810
+#define SH_MD_DQLP_MMR_YCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_YCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YUERR1                    0x0000000100033820
+#define SH_MD_DQLP_MMR_YUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_YUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_YUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YUERR2                    0x0000000100033830
+#define SH_MD_DQLP_MMR_YUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_YUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPERR                     0x0000000100033840
+#define SH_MD_DQLP_MMR_YPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQLP_MMR_YPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQLP_MMR_YPERR_DIR_SHFT            0
+#define SH_MD_DQLP_MMR_YPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_YPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQLP_MMR_YPERR_CMD_SHFT            26
+#define SH_MD_DQLP_MMR_YPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQLP_MMR_YPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQLP_MMR_YPERR_SRC_SHFT            34
+#define SH_MD_DQLP_MMR_YPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQLP_MMR_YPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT          48
+#define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT           49
+#define SH_MD_DQLP_MMR_YPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_YPERR_COR_SHFT            50
+#define SH_MD_DQLP_MMR_YPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_YPERR_UNC_SHFT            51
+#define SH_MD_DQLP_MMR_YPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT          52
+#define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQLP_MMR_YPERR_VAL_SHFT            60
+#define SH_MD_DQLP_MMR_YPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQLP_MMR_YPERR_MORE_SHFT           61
+#define SH_MD_DQLP_MMR_YPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQLP_MMR_YPERR_ARM_SHFT            62
+#define SH_MD_DQLP_MMR_YPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG               0x0000000100034000
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK          0x00000000ffffffff
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0                                    */
+/*   Description:  command trigger 0                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK     0x00000000000000ff
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1                                    */
+/*   Description:  command trigger 1                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT     8
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK     0x000000000000ff00
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2                                    */
+/*   Description:  command trigger 2                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT     16
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK     0x0000000000ff0000
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3                                    */
+/*   Description:  command trigger 3                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT     24
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK     0x00000000ff000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG               0x0000000100034010
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK          0x000003ffffffffff
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT      22
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT    24
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT    25
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT    34
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TBLMASK               0x0000000100034020
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK          0x000003ffffffffff
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT      22
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT    24
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT    25
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT    34
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_H                   0x0000000100038000
+#define SH_MD_DQLP_MMR_XBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQLP_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQLP_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_L                   0x0000000100038010
+#define SH_MD_DQLP_MMR_XBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQLP_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_ERR_H               0x0000000100038020
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_ERR_L               0x0000000100038030
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_H                   0x0000000100038800
+#define SH_MD_DQLP_MMR_YBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQLP_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQLP_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_L                   0x0000000100038810
+#define SH_MD_DQLP_MMR_YBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQLP_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_ERR_H               0x0000000100038820
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_ERR_L               0x0000000100038830
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_H                   0x0000000100048000
+#define SH_MD_DQLS_MMR_XBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQLS_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_L                   0x0000000100048010
+#define SH_MD_DQLS_MMR_XBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQLS_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_ERR_H               0x0000000100048020
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_ERR_L               0x0000000100048030
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_H                   0x0000000100048800
+#define SH_MD_DQLS_MMR_YBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQLS_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_L                   0x0000000100048810
+#define SH_MD_DQLS_MMR_YBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQLS_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_ERR_H               0x0000000100048820
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_ERR_L               0x0000000100048830
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_JNR_DEBUG                 0x0000000100049000
+#define SH_MD_DQLS_MMR_JNR_DEBUG_MASK            0x0000000000000003
+#define SH_MD_DQLS_MMR_JNR_DEBUG_INIT            0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_JNR_DEBUG_PX                                        */
+/*   Description:  select 0=pi 1=xn side                                */
+#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT         0
+#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK         0x0000000000000001
+
+/*   SH_MD_DQLS_MMR_JNR_DEBUG_RW                                        */
+/*   Description:  select 0=read 1=write side                           */
+#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT         1
+#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK         0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_XAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XAMOPW_ERR                0x000000010004a000
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK           0x0000000103ff03ff
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT           0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN                                     */
+/*   Description:  store data syndrome                                  */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT      0
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK      0x00000000000000ff
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR                                     */
+/*   Description:  correctable ecc errror on store data                 */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT      8
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK      0x0000000000000100
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC                                     */
+/*   Description:  uncorrectable ecc errror on store data               */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT      9
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK      0x0000000000000200
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN                                     */
+/*   Description:  memory read data syndrome                            */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT      16
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK      0x0000000000ff0000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR                                     */
+/*   Description:  correctable ecc errror on read data                  */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT      24
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK      0x0000000001000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC                                     */
+/*   Description:  uncorrectable ecc errror on read data                */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT      25
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK      0x0000000002000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_ARM                                      */
+/*   Description:  writing 1 arms ecc error capture                     */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT       32
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK       0x0000000100000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_CONFIG                0x0000000100050000
+#define SH_MD_DQRP_MMR_DIR_CONFIG_MASK           0x000000000000001f
+#define SH_MD_DQRP_MMR_DIR_CONFIG_INIT           0x0000000000000010
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE                                 */
+/*   Description:  system size code                                     */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT  0
+#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK  0x0000000000000007
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC                                */
+/*   Description:  enable directory ecc correction                      */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS                               */
+/*   Description:  enable local poisoning for dir table fall-through    */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0              0x0000000100050100
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1              0x0000000100050110
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2              0x0000000100050120
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3              0x0000000100050130
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0               0x0000000100050200
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1               0x0000000100050210
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2               0x0000000100050220
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3               0x0000000100050230
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4               0x0000000100050240
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5               0x0000000100050250
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6               0x0000000100050260
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7               0x0000000100050270
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0               0x0000000100050300
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC0_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1               0x0000000100050310
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC1_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2               0x0000000100050320
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC2_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3               0x0000000100050330
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC3_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4               0x0000000100050340
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC4_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5               0x0000000100050350
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC5_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6               0x0000000100050360
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC6_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7               0x0000000100050370
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC7_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TIMER                 0x0000000100050400
+#define SH_MD_DQRP_MMR_DIR_TIMER_MASK            0x00000000003fffff
+#define SH_MD_DQRP_MMR_DIR_TIMER_INIT            0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV                                 */
+/*   Description:  timer divide register                                */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT  0
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK  0x0000000000000fff
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN                                  */
+/*   Description:  timer enable                                         */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT   12
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK   0x0000000000001000
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR                                 */
+/*   Description:  value of current timer                               */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT  13
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK  0x00000000003fe000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY           0x0000000100051000
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK      0x03ffffffffffffff
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA                                */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB                                */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI                                 */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT  52
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK  0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC                                 */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT  55
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK  0x0380000000000000
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC             0x0000000100051010
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK        0x0000000000003fff
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT        0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA                                  */
+/*   Description:  XOR bits for directory ECC group 1                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT   0
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK   0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB                                  */
+/*   Description:  XOR bits for directory ECC group 2                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT   7
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK   0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY         0x0000000100052000
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC           0x0000000100052010
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY         0x0000000100052800
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC           0x0000000100052810
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XCERR1                    0x0000000100053000
+#define SH_MD_DQRP_MMR_XCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_XCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_XCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XCERR2                    0x0000000100053010
+#define SH_MD_DQRP_MMR_XCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_XCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XUERR1                    0x0000000100053020
+#define SH_MD_DQRP_MMR_XUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_XUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_XUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XUERR2                    0x0000000100053030
+#define SH_MD_DQRP_MMR_XUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_XUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPERR                     0x0000000100053040
+#define SH_MD_DQRP_MMR_XPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQRP_MMR_XPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQRP_MMR_XPERR_DIR_SHFT            0
+#define SH_MD_DQRP_MMR_XPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_XPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQRP_MMR_XPERR_CMD_SHFT            26
+#define SH_MD_DQRP_MMR_XPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQRP_MMR_XPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQRP_MMR_XPERR_SRC_SHFT            34
+#define SH_MD_DQRP_MMR_XPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQRP_MMR_XPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT          48
+#define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT           49
+#define SH_MD_DQRP_MMR_XPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_XPERR_COR_SHFT            50
+#define SH_MD_DQRP_MMR_XPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_XPERR_UNC_SHFT            51
+#define SH_MD_DQRP_MMR_XPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT          52
+#define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQRP_MMR_XPERR_VAL_SHFT            60
+#define SH_MD_DQRP_MMR_XPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQRP_MMR_XPERR_MORE_SHFT           61
+#define SH_MD_DQRP_MMR_XPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQRP_MMR_XPERR_ARM_SHFT            62
+#define SH_MD_DQRP_MMR_XPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YCERR1                    0x0000000100053800
+#define SH_MD_DQRP_MMR_YCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_YCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_YCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YCERR2                    0x0000000100053810
+#define SH_MD_DQRP_MMR_YCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_YCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YUERR1                    0x0000000100053820
+#define SH_MD_DQRP_MMR_YUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_YUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_YUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YUERR2                    0x0000000100053830
+#define SH_MD_DQRP_MMR_YUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_YUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPERR                     0x0000000100053840
+#define SH_MD_DQRP_MMR_YPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQRP_MMR_YPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQRP_MMR_YPERR_DIR_SHFT            0
+#define SH_MD_DQRP_MMR_YPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_YPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQRP_MMR_YPERR_CMD_SHFT            26
+#define SH_MD_DQRP_MMR_YPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQRP_MMR_YPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQRP_MMR_YPERR_SRC_SHFT            34
+#define SH_MD_DQRP_MMR_YPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQRP_MMR_YPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT          48
+#define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT           49
+#define SH_MD_DQRP_MMR_YPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_YPERR_COR_SHFT            50
+#define SH_MD_DQRP_MMR_YPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_YPERR_UNC_SHFT            51
+#define SH_MD_DQRP_MMR_YPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT          52
+#define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQRP_MMR_YPERR_VAL_SHFT            60
+#define SH_MD_DQRP_MMR_YPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQRP_MMR_YPERR_MORE_SHFT           61
+#define SH_MD_DQRP_MMR_YPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQRP_MMR_YPERR_ARM_SHFT            62
+#define SH_MD_DQRP_MMR_YPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG               0x0000000100054000
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK          0x00000000ffffffff
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0                                    */
+/*   Description:  command trigger 0                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK     0x00000000000000ff
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1                                    */
+/*   Description:  command trigger 1                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT     8
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK     0x000000000000ff00
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2                                    */
+/*   Description:  command trigger 2                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT     16
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK     0x0000000000ff0000
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3                                    */
+/*   Description:  command trigger 3                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT     24
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK     0x00000000ff000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG               0x0000000100054010
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK          0x000003ffffffffff
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT      22
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT    24
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT    25
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT    34
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TBLMASK               0x0000000100054020
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK          0x000003ffffffffff
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT      22
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT    24
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT    25
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT    34
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_H                   0x0000000100058000
+#define SH_MD_DQRP_MMR_XBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQRP_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQRP_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_L                   0x0000000100058010
+#define SH_MD_DQRP_MMR_XBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQRP_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_ERR_H               0x0000000100058020
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_ERR_L               0x0000000100058030
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_H                   0x0000000100058800
+#define SH_MD_DQRP_MMR_YBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQRP_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQRP_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_L                   0x0000000100058810
+#define SH_MD_DQRP_MMR_YBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQRP_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_ERR_H               0x0000000100058820
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_ERR_L               0x0000000100058830
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_H                   0x0000000100068000
+#define SH_MD_DQRS_MMR_XBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQRS_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_L                   0x0000000100068010
+#define SH_MD_DQRS_MMR_XBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQRS_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_ERR_H               0x0000000100068020
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_ERR_L               0x0000000100068030
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_H                   0x0000000100068800
+#define SH_MD_DQRS_MMR_YBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQRS_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_L                   0x0000000100068810
+#define SH_MD_DQRS_MMR_YBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQRS_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_ERR_H               0x0000000100068820
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_ERR_L               0x0000000100068830
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_JNR_DEBUG                 0x0000000100069000
+#define SH_MD_DQRS_MMR_JNR_DEBUG_MASK            0x0000000000000003
+#define SH_MD_DQRS_MMR_JNR_DEBUG_INIT            0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_JNR_DEBUG_PX                                        */
+/*   Description:  select 0=pi 1=xn side                                */
+#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT         0
+#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK         0x0000000000000001
+
+/*   SH_MD_DQRS_MMR_JNR_DEBUG_RW                                        */
+/*   Description:  select 0=read 1=write side                           */
+#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT         1
+#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK         0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_YAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YAMOPW_ERR                0x000000010006a000
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK           0x0000000103ff03ff
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT           0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN                                     */
+/*   Description:  store data syndrome                                  */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT      0
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK      0x00000000000000ff
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR                                     */
+/*   Description:  correctable ecc errror on store data                 */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT      8
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK      0x0000000000000100
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC                                     */
+/*   Description:  uncorrectable ecc errror on store data               */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT      9
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK      0x0000000000000200
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN                                     */
+/*   Description:  memory read data syndrome                            */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT      16
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK      0x0000000000ff0000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR                                     */
+/*   Description:  correctable ecc errror on read data                  */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT      24
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK      0x0000000001000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC                                     */
+/*   Description:  uncorrectable ecc errror on read data                */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT      25
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK      0x0000000002000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_ARM                                      */
+/*   Description:  writing 1 arms ecc error capture                     */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT       32
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK       0x0000000100000000
+
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/shub_mmr_t.h lia64-2.4/include/asm-ia64/sn/sn2/shub_mmr_t.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/shub_mmr_t.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/shub_mmr_t.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,27383 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H
+#define _ASM_IA64_SN_SN2_SHUB_MMR_T_H
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_BINIT_CONTROL"                    */
+/*                          FSB BINIT# Control                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_binit_control_u {
+	mmr_t	sh_fsb_binit_control_regval;
+	struct {
+		mmr_t	binit       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_fsb_binit_control_s;
+} sh_fsb_binit_control_u_t;
+#else
+typedef union sh_fsb_binit_control_u {
+	mmr_t	sh_fsb_binit_control_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	binit       : 1;
+	} sh_fsb_binit_control_s;
+} sh_fsb_binit_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_RESET_CONTROL"                    */
+/*                          FSB Reset Control                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_reset_control_u {
+	mmr_t	sh_fsb_reset_control_regval;
+	struct {
+		mmr_t	reset       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_fsb_reset_control_s;
+} sh_fsb_reset_control_u_t;
+#else
+typedef union sh_fsb_reset_control_u {
+	mmr_t	sh_fsb_reset_control_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	reset       : 1;
+	} sh_fsb_reset_control_s;
+} sh_fsb_reset_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
+/*                    FSB System Agent Configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_system_agent_config_u {
+	mmr_t	sh_fsb_system_agent_config_regval;
+	struct {
+		mmr_t	rcnt_scnt_en        : 1;
+		mmr_t	reserved_0          : 2;
+		mmr_t	berr_assert_en      : 1;
+		mmr_t	berr_sampling_en    : 1;
+		mmr_t	binit_assert_en     : 1;
+		mmr_t	bnr_throttling_en   : 1;
+		mmr_t	short_hang_en       : 1;
+		mmr_t	inta_rsp_data       : 8;
+		mmr_t	io_trans_rsp        : 1;
+		mmr_t	xtpr_trans_rsp      : 1;
+		mmr_t	inta_trans_rsp      : 1;
+		mmr_t	reserved_1          : 4;
+		mmr_t	tdot                : 1;
+		mmr_t	serialize_fsb_en    : 1;
+		mmr_t	reserved_2          : 7;
+		mmr_t	binit_event_enables : 14;
+		mmr_t	reserved_3          : 18;
+	} sh_fsb_system_agent_config_s;
+} sh_fsb_system_agent_config_u_t;
+#else
+typedef union sh_fsb_system_agent_config_u {
+	mmr_t	sh_fsb_system_agent_config_regval;
+	struct {
+		mmr_t	reserved_3          : 18;
+		mmr_t	binit_event_enables : 14;
+		mmr_t	reserved_2          : 7;
+		mmr_t	serialize_fsb_en    : 1;
+		mmr_t	tdot                : 1;
+		mmr_t	reserved_1          : 4;
+		mmr_t	inta_trans_rsp      : 1;
+		mmr_t	xtpr_trans_rsp      : 1;
+		mmr_t	io_trans_rsp        : 1;
+		mmr_t	inta_rsp_data       : 8;
+		mmr_t	short_hang_en       : 1;
+		mmr_t	bnr_throttling_en   : 1;
+		mmr_t	binit_assert_en     : 1;
+		mmr_t	berr_sampling_en    : 1;
+		mmr_t	berr_assert_en      : 1;
+		mmr_t	reserved_0          : 2;
+		mmr_t	rcnt_scnt_en        : 1;
+	} sh_fsb_system_agent_config_s;
+} sh_fsb_system_agent_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_FSB_VGA_REMAP"                      */
+/*                     FSB VGA Address Space Remap                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_vga_remap_u {
+	mmr_t	sh_fsb_vga_remap_regval;
+	struct {
+		mmr_t	reserved_0            : 17;
+		mmr_t	offset                : 19;
+		mmr_t	asid                  : 2;
+		mmr_t	nid                   : 11;
+		mmr_t	reserved_1            : 13;
+		mmr_t	vga_remapping_enabled : 1;
+		mmr_t	reserved_2            : 1;
+	} sh_fsb_vga_remap_s;
+} sh_fsb_vga_remap_u_t;
+#else
+typedef union sh_fsb_vga_remap_u {
+	mmr_t	sh_fsb_vga_remap_regval;
+	struct {
+		mmr_t	reserved_2            : 1;
+		mmr_t	vga_remapping_enabled : 1;
+		mmr_t	reserved_1            : 13;
+		mmr_t	nid                   : 11;
+		mmr_t	asid                  : 2;
+		mmr_t	offset                : 19;
+		mmr_t	reserved_0            : 17;
+	} sh_fsb_vga_remap_s;
+} sh_fsb_vga_remap_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_FSB_RESET_STATUS"                    */
+/*                           FSB Reset Status                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_reset_status_u {
+	mmr_t	sh_fsb_reset_status_regval;
+	struct {
+		mmr_t	reset_in_progress : 1;
+		mmr_t	reserved_0        : 63;
+	} sh_fsb_reset_status_s;
+} sh_fsb_reset_status_u_t;
+#else
+typedef union sh_fsb_reset_status_u {
+	mmr_t	sh_fsb_reset_status_regval;
+	struct {
+		mmr_t	reserved_0        : 63;
+		mmr_t	reset_in_progress : 1;
+	} sh_fsb_reset_status_s;
+} sh_fsb_reset_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
+/*                      FSB Symmetric Agent Status                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_symmetric_agent_status_u {
+	mmr_t	sh_fsb_symmetric_agent_status_regval;
+	struct {
+		mmr_t	cpu_0_active : 1;
+		mmr_t	cpu_1_active : 1;
+		mmr_t	cpus_ready   : 1;
+		mmr_t	reserved_0   : 61;
+	} sh_fsb_symmetric_agent_status_s;
+} sh_fsb_symmetric_agent_status_u_t;
+#else
+typedef union sh_fsb_symmetric_agent_status_u {
+	mmr_t	sh_fsb_symmetric_agent_status_regval;
+	struct {
+		mmr_t	reserved_0   : 61;
+		mmr_t	cpus_ready   : 1;
+		mmr_t	cpu_1_active : 1;
+		mmr_t	cpu_0_active : 1;
+	} sh_fsb_symmetric_agent_status_s;
+} sh_fsb_symmetric_agent_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
+/*                Graphics-write Credit Count for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_credit_count_0_u {
+	mmr_t	sh_gfx_credit_count_0_regval;
+	struct {
+		mmr_t	count           : 20;
+		mmr_t	reserved_0      : 43;
+		mmr_t	reset_gfx_state : 1;
+	} sh_gfx_credit_count_0_s;
+} sh_gfx_credit_count_0_u_t;
+#else
+typedef union sh_gfx_credit_count_0_u {
+	mmr_t	sh_gfx_credit_count_0_regval;
+	struct {
+		mmr_t	reset_gfx_state : 1;
+		mmr_t	reserved_0      : 43;
+		mmr_t	count           : 20;
+	} sh_gfx_credit_count_0_s;
+} sh_gfx_credit_count_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
+/*                Graphics-write Credit Count for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_credit_count_1_u {
+	mmr_t	sh_gfx_credit_count_1_regval;
+	struct {
+		mmr_t	count           : 20;
+		mmr_t	reserved_0      : 43;
+		mmr_t	reset_gfx_state : 1;
+	} sh_gfx_credit_count_1_s;
+} sh_gfx_credit_count_1_u_t;
+#else
+typedef union sh_gfx_credit_count_1_u {
+	mmr_t	sh_gfx_credit_count_1_regval;
+	struct {
+		mmr_t	reset_gfx_state : 1;
+		mmr_t	reserved_0      : 43;
+		mmr_t	count           : 20;
+	} sh_gfx_credit_count_1_s;
+} sh_gfx_credit_count_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_0"                    */
+/*         Graphics credit mode amd message ordering for CPU 0          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_mode_cntrl_0_u {
+	mmr_t	sh_gfx_mode_cntrl_0_regval;
+	struct {
+		mmr_t	dword_credits      : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	reserved_0         : 61;
+	} sh_gfx_mode_cntrl_0_s;
+} sh_gfx_mode_cntrl_0_u_t;
+#else
+typedef union sh_gfx_mode_cntrl_0_u {
+	mmr_t	sh_gfx_mode_cntrl_0_regval;
+	struct {
+		mmr_t	reserved_0         : 61;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	dword_credits      : 1;
+	} sh_gfx_mode_cntrl_0_s;
+} sh_gfx_mode_cntrl_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_1"                    */
+/*         Graphics credit mode amd message ordering for CPU 1          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_mode_cntrl_1_u {
+	mmr_t	sh_gfx_mode_cntrl_1_regval;
+	struct {
+		mmr_t	dword_credits      : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	reserved_0         : 61;
+	} sh_gfx_mode_cntrl_1_s;
+} sh_gfx_mode_cntrl_1_u_t;
+#else
+typedef union sh_gfx_mode_cntrl_1_u {
+	mmr_t	sh_gfx_mode_cntrl_1_regval;
+	struct {
+		mmr_t	reserved_0         : 61;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	dword_credits      : 1;
+	} sh_gfx_mode_cntrl_1_s;
+} sh_gfx_mode_cntrl_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
+/*              Graphics-write Skid Credit Count for CPU 0              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_skid_credit_count_0_u {
+	mmr_t	sh_gfx_skid_credit_count_0_regval;
+	struct {
+		mmr_t	skid        : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_gfx_skid_credit_count_0_s;
+} sh_gfx_skid_credit_count_0_u_t;
+#else
+typedef union sh_gfx_skid_credit_count_0_u {
+	mmr_t	sh_gfx_skid_credit_count_0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	skid        : 20;
+	} sh_gfx_skid_credit_count_0_s;
+} sh_gfx_skid_credit_count_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
+/*              Graphics-write Skid Credit Count for CPU 1              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_skid_credit_count_1_u {
+	mmr_t	sh_gfx_skid_credit_count_1_regval;
+	struct {
+		mmr_t	skid        : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_gfx_skid_credit_count_1_s;
+} sh_gfx_skid_credit_count_1_u_t;
+#else
+typedef union sh_gfx_skid_credit_count_1_u {
+	mmr_t	sh_gfx_skid_credit_count_1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	skid        : 20;
+	} sh_gfx_skid_credit_count_1_s;
+} sh_gfx_skid_credit_count_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_0"                    */
+/*                 Graphics-write Stall Limit for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_limit_0_u {
+	mmr_t	sh_gfx_stall_limit_0_regval;
+	struct {
+		mmr_t	limit       : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_limit_0_s;
+} sh_gfx_stall_limit_0_u_t;
+#else
+typedef union sh_gfx_stall_limit_0_u {
+	mmr_t	sh_gfx_stall_limit_0_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	limit       : 26;
+	} sh_gfx_stall_limit_0_s;
+} sh_gfx_stall_limit_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_1"                    */
+/*                 Graphics-write Stall Limit for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_limit_1_u {
+	mmr_t	sh_gfx_stall_limit_1_regval;
+	struct {
+		mmr_t	limit       : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_limit_1_s;
+} sh_gfx_stall_limit_1_u_t;
+#else
+typedef union sh_gfx_stall_limit_1_u {
+	mmr_t	sh_gfx_stall_limit_1_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	limit       : 26;
+	} sh_gfx_stall_limit_1_s;
+} sh_gfx_stall_limit_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_0"                    */
+/*                 Graphics-write Stall Timer for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_timer_0_u {
+	mmr_t	sh_gfx_stall_timer_0_regval;
+	struct {
+		mmr_t	timer_value : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_timer_0_s;
+} sh_gfx_stall_timer_0_u_t;
+#else
+typedef union sh_gfx_stall_timer_0_u {
+	mmr_t	sh_gfx_stall_timer_0_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	timer_value : 26;
+	} sh_gfx_stall_timer_0_s;
+} sh_gfx_stall_timer_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_1"                    */
+/*                 Graphics-write Stall Timer for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_timer_1_u {
+	mmr_t	sh_gfx_stall_timer_1_regval;
+	struct {
+		mmr_t	timer_value : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_timer_1_s;
+} sh_gfx_stall_timer_1_u_t;
+#else
+typedef union sh_gfx_stall_timer_1_u {
+	mmr_t	sh_gfx_stall_timer_1_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	timer_value : 26;
+	} sh_gfx_stall_timer_1_s;
+} sh_gfx_stall_timer_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_0"                      */
+/*                   Graphics-write Window for CPU 0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_window_0_u {
+	mmr_t	sh_gfx_window_0_regval;
+	struct {
+		mmr_t	reserved_0    : 24;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_1    : 27;
+		mmr_t	gfx_window_en : 1;
+	} sh_gfx_window_0_s;
+} sh_gfx_window_0_u_t;
+#else
+typedef union sh_gfx_window_0_u {
+	mmr_t	sh_gfx_window_0_regval;
+	struct {
+		mmr_t	gfx_window_en : 1;
+		mmr_t	reserved_1    : 27;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_0    : 24;
+	} sh_gfx_window_0_s;
+} sh_gfx_window_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_1"                      */
+/*                   Graphics-write Window for CPU 1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_window_1_u {
+	mmr_t	sh_gfx_window_1_regval;
+	struct {
+		mmr_t	reserved_0    : 24;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_1    : 27;
+		mmr_t	gfx_window_en : 1;
+	} sh_gfx_window_1_s;
+} sh_gfx_window_1_u_t;
+#else
+typedef union sh_gfx_window_1_u {
+	mmr_t	sh_gfx_window_1_regval;
+	struct {
+		mmr_t	gfx_window_en : 1;
+		mmr_t	reserved_1    : 27;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_0    : 24;
+	} sh_gfx_window_1_s;
+} sh_gfx_window_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
+/*               Graphics-write Interrupt Limit for CPU 0               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_interrupt_timer_limit_0_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
+	struct {
+		mmr_t	interrupt_timer_limit : 8;
+		mmr_t	reserved_0            : 56;
+	} sh_gfx_interrupt_timer_limit_0_s;
+} sh_gfx_interrupt_timer_limit_0_u_t;
+#else
+typedef union sh_gfx_interrupt_timer_limit_0_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
+	struct {
+		mmr_t	reserved_0            : 56;
+		mmr_t	interrupt_timer_limit : 8;
+	} sh_gfx_interrupt_timer_limit_0_s;
+} sh_gfx_interrupt_timer_limit_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
+/*               Graphics-write Interrupt Limit for CPU 1               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_interrupt_timer_limit_1_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
+	struct {
+		mmr_t	interrupt_timer_limit : 8;
+		mmr_t	reserved_0            : 56;
+	} sh_gfx_interrupt_timer_limit_1_s;
+} sh_gfx_interrupt_timer_limit_1_u_t;
+#else
+typedef union sh_gfx_interrupt_timer_limit_1_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
+	struct {
+		mmr_t	reserved_0            : 56;
+		mmr_t	interrupt_timer_limit : 8;
+	} sh_gfx_interrupt_timer_limit_1_s;
+} sh_gfx_interrupt_timer_limit_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
+/*                   Graphics Write Status for CPU 0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_write_status_0_u {
+	mmr_t	sh_gfx_write_status_0_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	re_enable_gfx_stall : 1;
+	} sh_gfx_write_status_0_s;
+} sh_gfx_write_status_0_u_t;
+#else
+typedef union sh_gfx_write_status_0_u {
+	mmr_t	sh_gfx_write_status_0_regval;
+	struct {
+		mmr_t	re_enable_gfx_stall : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	busy                : 1;
+	} sh_gfx_write_status_0_s;
+} sh_gfx_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
+/*                   Graphics Write Status for CPU 1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_write_status_1_u {
+	mmr_t	sh_gfx_write_status_1_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	re_enable_gfx_stall : 1;
+	} sh_gfx_write_status_1_s;
+} sh_gfx_write_status_1_u_t;
+#else
+typedef union sh_gfx_write_status_1_u {
+	mmr_t	sh_gfx_write_status_1_regval;
+	struct {
+		mmr_t	re_enable_gfx_stall : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	busy                : 1;
+	} sh_gfx_write_status_1_s;
+} sh_gfx_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT0"                         */
+/*                    SHub II Interrupt 0 Registers                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_u {
+	mmr_t	sh_ii_int0_regval;
+	struct {
+		mmr_t	idx         : 8;
+		mmr_t	send        : 1;
+		mmr_t	reserved_0  : 55;
+	} sh_ii_int0_s;
+} sh_ii_int0_u_t;
+#else
+typedef union sh_ii_int0_u {
+	mmr_t	sh_ii_int0_regval;
+	struct {
+		mmr_t	reserved_0  : 55;
+		mmr_t	send        : 1;
+		mmr_t	idx         : 8;
+	} sh_ii_int0_s;
+} sh_ii_int0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_CONFIG"                     */
+/*                 SHub II Interrupt 0 Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_config_u {
+	mmr_t	sh_ii_int0_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 14;
+	} sh_ii_int0_config_s;
+} sh_ii_int0_config_u_t;
+#else
+typedef union sh_ii_int0_config_u {
+	mmr_t	sh_ii_int0_config_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ii_int0_config_s;
+} sh_ii_int0_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_ENABLE"                     */
+/*                 SHub II Interrupt 0 Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_enable_u {
+	mmr_t	sh_ii_int0_enable_regval;
+	struct {
+		mmr_t	ii_enable   : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ii_int0_enable_s;
+} sh_ii_int0_enable_u_t;
+#else
+typedef union sh_ii_int0_enable_u {
+	mmr_t	sh_ii_int0_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ii_enable   : 1;
+	} sh_ii_int0_enable_s;
+} sh_ii_int0_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT1"                         */
+/*                    SHub II Interrupt 1 Registers                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_u {
+	mmr_t	sh_ii_int1_regval;
+	struct {
+		mmr_t	idx         : 8;
+		mmr_t	send        : 1;
+		mmr_t	reserved_0  : 55;
+	} sh_ii_int1_s;
+} sh_ii_int1_u_t;
+#else
+typedef union sh_ii_int1_u {
+	mmr_t	sh_ii_int1_regval;
+	struct {
+		mmr_t	reserved_0  : 55;
+		mmr_t	send        : 1;
+		mmr_t	idx         : 8;
+	} sh_ii_int1_s;
+} sh_ii_int1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_CONFIG"                     */
+/*                 SHub II Interrupt 1 Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_config_u {
+	mmr_t	sh_ii_int1_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 14;
+	} sh_ii_int1_config_s;
+} sh_ii_int1_config_u_t;
+#else
+typedef union sh_ii_int1_config_u {
+	mmr_t	sh_ii_int1_config_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ii_int1_config_s;
+} sh_ii_int1_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_ENABLE"                     */
+/*                 SHub II Interrupt 1 Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_enable_u {
+	mmr_t	sh_ii_int1_enable_regval;
+	struct {
+		mmr_t	ii_enable   : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ii_int1_enable_s;
+} sh_ii_int1_enable_u_t;
+#else
+typedef union sh_ii_int1_enable_u {
+	mmr_t	sh_ii_int1_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ii_enable   : 1;
+	} sh_ii_int1_enable_s;
+} sh_ii_int1_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_INT_NODE_ID_CONFIG"                   */
+/*                 SHub Interrupt Node ID Configuration                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_node_id_config_u {
+	mmr_t	sh_int_node_id_config_regval;
+	struct {
+		mmr_t	node_id     : 11;
+		mmr_t	id_sel      : 1;
+		mmr_t	reserved_0  : 52;
+	} sh_int_node_id_config_s;
+} sh_int_node_id_config_u_t;
+#else
+typedef union sh_int_node_id_config_u {
+	mmr_t	sh_int_node_id_config_regval;
+	struct {
+		mmr_t	reserved_0  : 52;
+		mmr_t	id_sel      : 1;
+		mmr_t	node_id     : 11;
+	} sh_int_node_id_config_s;
+} sh_int_node_id_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_int_u {
+	mmr_t	sh_ipi_int_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 3;
+		mmr_t	send        : 1;
+	} sh_ipi_int_s;
+} sh_ipi_int_u_t;
+#else
+typedef union sh_ipi_int_u {
+	mmr_t	sh_ipi_int_regval;
+	struct {
+		mmr_t	send        : 1;
+		mmr_t	reserved_2  : 3;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ipi_int_s;
+} sh_ipi_int_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_IPI_INT_ENABLE"                     */
+/*           SHub Inter-Processor Interrupt Enable Registers            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_int_enable_u {
+	mmr_t	sh_ipi_int_enable_regval;
+	struct {
+		mmr_t	pio_enable  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ipi_int_enable_s;
+} sh_ipi_int_enable_u_t;
+#else
+typedef union sh_ipi_int_enable_u {
+	mmr_t	sh_ipi_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pio_enable  : 1;
+	} sh_ipi_int_enable_s;
+} sh_ipi_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_CONFIG"                    */
+/*                   SHub Local Interrupt 0 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int0_config_u {
+	mmr_t	sh_local_int0_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int0_config_s;
+} sh_local_int0_config_u_t;
+#else
+typedef union sh_local_int0_config_u {
+	mmr_t	sh_local_int0_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int0_config_s;
+} sh_local_int0_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_ENABLE"                    */
+/*                    SHub Local Interrupt 0 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int0_enable_u {
+	mmr_t	sh_local_int0_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int0_enable_s;
+} sh_local_int0_enable_u_t;
+#else
+typedef union sh_local_int0_enable_u {
+	mmr_t	sh_local_int0_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int0_enable_s;
+} sh_local_int0_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_CONFIG"                    */
+/*                   SHub Local Interrupt 1 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int1_config_u {
+	mmr_t	sh_local_int1_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int1_config_s;
+} sh_local_int1_config_u_t;
+#else
+typedef union sh_local_int1_config_u {
+	mmr_t	sh_local_int1_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int1_config_s;
+} sh_local_int1_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_ENABLE"                    */
+/*                    SHub Local Interrupt 1 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int1_enable_u {
+	mmr_t	sh_local_int1_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int1_enable_s;
+} sh_local_int1_enable_u_t;
+#else
+typedef union sh_local_int1_enable_u {
+	mmr_t	sh_local_int1_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int1_enable_s;
+} sh_local_int1_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_CONFIG"                    */
+/*                   SHub Local Interrupt 2 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int2_config_u {
+	mmr_t	sh_local_int2_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int2_config_s;
+} sh_local_int2_config_u_t;
+#else
+typedef union sh_local_int2_config_u {
+	mmr_t	sh_local_int2_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int2_config_s;
+} sh_local_int2_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_ENABLE"                    */
+/*                    SHub Local Interrupt 2 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int2_enable_u {
+	mmr_t	sh_local_int2_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int2_enable_s;
+} sh_local_int2_enable_u_t;
+#else
+typedef union sh_local_int2_enable_u {
+	mmr_t	sh_local_int2_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int2_enable_s;
+} sh_local_int2_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_CONFIG"                    */
+/*                   SHub Local Interrupt 3 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int3_config_u {
+	mmr_t	sh_local_int3_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int3_config_s;
+} sh_local_int3_config_u_t;
+#else
+typedef union sh_local_int3_config_u {
+	mmr_t	sh_local_int3_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int3_config_s;
+} sh_local_int3_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_ENABLE"                    */
+/*                    SHub Local Interrupt 3 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int3_enable_u {
+	mmr_t	sh_local_int3_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int3_enable_s;
+} sh_local_int3_enable_u_t;
+#else
+typedef union sh_local_int3_enable_u {
+	mmr_t	sh_local_int3_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int3_enable_s;
+} sh_local_int3_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_CONFIG"                    */
+/*                   SHub Local Interrupt 4 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int4_config_u {
+	mmr_t	sh_local_int4_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int4_config_s;
+} sh_local_int4_config_u_t;
+#else
+typedef union sh_local_int4_config_u {
+	mmr_t	sh_local_int4_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int4_config_s;
+} sh_local_int4_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_ENABLE"                    */
+/*                    SHub Local Interrupt 4 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int4_enable_u {
+	mmr_t	sh_local_int4_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int4_enable_s;
+} sh_local_int4_enable_u_t;
+#else
+typedef union sh_local_int4_enable_u {
+	mmr_t	sh_local_int4_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int4_enable_s;
+} sh_local_int4_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_CONFIG"                    */
+/*                   SHub Local Interrupt 5 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int5_config_u {
+	mmr_t	sh_local_int5_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int5_config_s;
+} sh_local_int5_config_u_t;
+#else
+typedef union sh_local_int5_config_u {
+	mmr_t	sh_local_int5_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int5_config_s;
+} sh_local_int5_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_ENABLE"                    */
+/*                    SHub Local Interrupt 5 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int5_enable_u {
+	mmr_t	sh_local_int5_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int5_enable_s;
+} sh_local_int5_enable_u_t;
+#else
+typedef union sh_local_int5_enable_u {
+	mmr_t	sh_local_int5_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int5_enable_s;
+} sh_local_int5_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
+/*              SHub Processor 0 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_int_config_u {
+	mmr_t	sh_proc0_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc0_err_int_config_s;
+} sh_proc0_err_int_config_u_t;
+#else
+typedef union sh_proc0_err_int_config_u {
+	mmr_t	sh_proc0_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc0_err_int_config_s;
+} sh_proc0_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
+/*              SHub Processor 1 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_int_config_u {
+	mmr_t	sh_proc1_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc1_err_int_config_s;
+} sh_proc1_err_int_config_u_t;
+#else
+typedef union sh_proc1_err_int_config_u {
+	mmr_t	sh_proc1_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc1_err_int_config_s;
+} sh_proc1_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
+/*              SHub Processor 2 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_int_config_u {
+	mmr_t	sh_proc2_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc2_err_int_config_s;
+} sh_proc2_err_int_config_u_t;
+#else
+typedef union sh_proc2_err_int_config_u {
+	mmr_t	sh_proc2_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc2_err_int_config_s;
+} sh_proc2_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
+/*              SHub Processor 3 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_int_config_u {
+	mmr_t	sh_proc3_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc3_err_int_config_s;
+} sh_proc3_err_int_config_u_t;
+#else
+typedef union sh_proc3_err_int_config_u {
+	mmr_t	sh_proc3_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc3_err_int_config_s;
+} sh_proc3_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
+/*            SHub Processor 0 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_int_config_u {
+	mmr_t	sh_proc0_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc0_adv_int_config_s;
+} sh_proc0_adv_int_config_u_t;
+#else
+typedef union sh_proc0_adv_int_config_u {
+	mmr_t	sh_proc0_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc0_adv_int_config_s;
+} sh_proc0_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
+/*            SHub Processor 1 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_int_config_u {
+	mmr_t	sh_proc1_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc1_adv_int_config_s;
+} sh_proc1_adv_int_config_u_t;
+#else
+typedef union sh_proc1_adv_int_config_u {
+	mmr_t	sh_proc1_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc1_adv_int_config_s;
+} sh_proc1_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
+/*            SHub Processor 2 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_int_config_u {
+	mmr_t	sh_proc2_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc2_adv_int_config_s;
+} sh_proc2_adv_int_config_u_t;
+#else
+typedef union sh_proc2_adv_int_config_u {
+	mmr_t	sh_proc2_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc2_adv_int_config_s;
+} sh_proc2_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
+/*            SHub Processor 3 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_int_config_u {
+	mmr_t	sh_proc3_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc3_adv_int_config_s;
+} sh_proc3_adv_int_config_u_t;
+#else
+typedef union sh_proc3_adv_int_config_u {
+	mmr_t	sh_proc3_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc3_adv_int_config_s;
+} sh_proc3_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
+/*          SHub Processor 0 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_int_enable_u {
+	mmr_t	sh_proc0_err_int_enable_regval;
+	struct {
+		mmr_t	proc0_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc0_err_int_enable_s;
+} sh_proc0_err_int_enable_u_t;
+#else
+typedef union sh_proc0_err_int_enable_u {
+	mmr_t	sh_proc0_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc0_err_enable : 1;
+	} sh_proc0_err_int_enable_s;
+} sh_proc0_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
+/*          SHub Processor 1 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_int_enable_u {
+	mmr_t	sh_proc1_err_int_enable_regval;
+	struct {
+		mmr_t	proc1_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc1_err_int_enable_s;
+} sh_proc1_err_int_enable_u_t;
+#else
+typedef union sh_proc1_err_int_enable_u {
+	mmr_t	sh_proc1_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc1_err_enable : 1;
+	} sh_proc1_err_int_enable_s;
+} sh_proc1_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
+/*          SHub Processor 2 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_int_enable_u {
+	mmr_t	sh_proc2_err_int_enable_regval;
+	struct {
+		mmr_t	proc2_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc2_err_int_enable_s;
+} sh_proc2_err_int_enable_u_t;
+#else
+typedef union sh_proc2_err_int_enable_u {
+	mmr_t	sh_proc2_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc2_err_enable : 1;
+	} sh_proc2_err_int_enable_s;
+} sh_proc2_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
+/*          SHub Processor 3 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_int_enable_u {
+	mmr_t	sh_proc3_err_int_enable_regval;
+	struct {
+		mmr_t	proc3_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc3_err_int_enable_s;
+} sh_proc3_err_int_enable_u_t;
+#else
+typedef union sh_proc3_err_int_enable_u {
+	mmr_t	sh_proc3_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc3_err_enable : 1;
+	} sh_proc3_err_int_enable_s;
+} sh_proc3_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
+/*         SHub Processor 0 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_int_enable_u {
+	mmr_t	sh_proc0_adv_int_enable_regval;
+	struct {
+		mmr_t	proc0_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc0_adv_int_enable_s;
+} sh_proc0_adv_int_enable_u_t;
+#else
+typedef union sh_proc0_adv_int_enable_u {
+	mmr_t	sh_proc0_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc0_adv_enable : 1;
+	} sh_proc0_adv_int_enable_s;
+} sh_proc0_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
+/*         SHub Processor 1 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_int_enable_u {
+	mmr_t	sh_proc1_adv_int_enable_regval;
+	struct {
+		mmr_t	proc1_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc1_adv_int_enable_s;
+} sh_proc1_adv_int_enable_u_t;
+#else
+typedef union sh_proc1_adv_int_enable_u {
+	mmr_t	sh_proc1_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc1_adv_enable : 1;
+	} sh_proc1_adv_int_enable_s;
+} sh_proc1_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
+/*         SHub Processor 2 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_int_enable_u {
+	mmr_t	sh_proc2_adv_int_enable_regval;
+	struct {
+		mmr_t	proc2_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc2_adv_int_enable_s;
+} sh_proc2_adv_int_enable_u_t;
+#else
+typedef union sh_proc2_adv_int_enable_u {
+	mmr_t	sh_proc2_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc2_adv_enable : 1;
+	} sh_proc2_adv_int_enable_s;
+} sh_proc2_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
+/*         SHub Processor 3 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_int_enable_u {
+	mmr_t	sh_proc3_adv_int_enable_regval;
+	struct {
+		mmr_t	proc3_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc3_adv_int_enable_s;
+} sh_proc3_adv_int_enable_u_t;
+#else
+typedef union sh_proc3_adv_int_enable_u {
+	mmr_t	sh_proc3_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc3_adv_enable : 1;
+	} sh_proc3_adv_int_enable_s;
+} sh_proc3_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_CONFIG"                   */
+/*            SHub Profile Interrupt Configuration Registers            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_int_config_u {
+	mmr_t	sh_profile_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_profile_int_config_s;
+} sh_profile_int_config_u_t;
+#else
+typedef union sh_profile_int_config_u {
+	mmr_t	sh_profile_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_profile_int_config_s;
+} sh_profile_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_ENABLE"                   */
+/*               SHub Profile Interrupt Enable Registers                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_int_enable_u {
+	mmr_t	sh_profile_int_enable_regval;
+	struct {
+		mmr_t	profile_enable : 1;
+		mmr_t	reserved_0     : 63;
+	} sh_profile_int_enable_s;
+} sh_profile_int_enable_u_t;
+#else
+typedef union sh_profile_int_enable_u {
+	mmr_t	sh_profile_int_enable_regval;
+	struct {
+		mmr_t	reserved_0     : 63;
+		mmr_t	profile_enable : 1;
+	} sh_profile_int_enable_s;
+} sh_profile_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_CONFIG"                     */
+/*                SHub RTC 0 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc0_int_config_u {
+	mmr_t	sh_rtc0_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc0_int_config_s;
+} sh_rtc0_int_config_u_t;
+#else
+typedef union sh_rtc0_int_config_u {
+	mmr_t	sh_rtc0_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc0_int_config_s;
+} sh_rtc0_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_ENABLE"                     */
+/*                SHub RTC 0 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc0_int_enable_u {
+	mmr_t	sh_rtc0_int_enable_regval;
+	struct {
+		mmr_t	rtc0_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc0_int_enable_s;
+} sh_rtc0_int_enable_u_t;
+#else
+typedef union sh_rtc0_int_enable_u {
+	mmr_t	sh_rtc0_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc0_enable : 1;
+	} sh_rtc0_int_enable_s;
+} sh_rtc0_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc1_int_config_u {
+	mmr_t	sh_rtc1_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc1_int_config_s;
+} sh_rtc1_int_config_u_t;
+#else
+typedef union sh_rtc1_int_config_u {
+	mmr_t	sh_rtc1_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc1_int_config_s;
+} sh_rtc1_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc1_int_enable_u {
+	mmr_t	sh_rtc1_int_enable_regval;
+	struct {
+		mmr_t	rtc1_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc1_int_enable_s;
+} sh_rtc1_int_enable_u_t;
+#else
+typedef union sh_rtc1_int_enable_u {
+	mmr_t	sh_rtc1_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc1_enable : 1;
+	} sh_rtc1_int_enable_s;
+} sh_rtc1_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc2_int_config_u {
+	mmr_t	sh_rtc2_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc2_int_config_s;
+} sh_rtc2_int_config_u_t;
+#else
+typedef union sh_rtc2_int_config_u {
+	mmr_t	sh_rtc2_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc2_int_config_s;
+} sh_rtc2_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc2_int_enable_u {
+	mmr_t	sh_rtc2_int_enable_regval;
+	struct {
+		mmr_t	rtc2_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc2_int_enable_s;
+} sh_rtc2_int_enable_u_t;
+#else
+typedef union sh_rtc2_int_enable_u {
+	mmr_t	sh_rtc2_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc2_enable : 1;
+	} sh_rtc2_int_enable_s;
+} sh_rtc2_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc3_int_config_u {
+	mmr_t	sh_rtc3_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc3_int_config_s;
+} sh_rtc3_int_config_u_t;
+#else
+typedef union sh_rtc3_int_config_u {
+	mmr_t	sh_rtc3_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc3_int_config_s;
+} sh_rtc3_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc3_int_enable_u {
+	mmr_t	sh_rtc3_int_enable_regval;
+	struct {
+		mmr_t	rtc3_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc3_int_enable_s;
+} sh_rtc3_int_enable_u_t;
+#else
+typedef union sh_rtc3_int_enable_u {
+	mmr_t	sh_rtc3_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc3_enable : 1;
+	} sh_rtc3_int_enable_s;
+} sh_rtc3_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_event_occurred_u {
+	mmr_t	sh_event_occurred_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	ipi_int             : 1;
+		mmr_t	ii_int0             : 1;
+		mmr_t	ii_int1             : 1;
+		mmr_t	reserved_0          : 33;
+	} sh_event_occurred_s;
+} sh_event_occurred_u_t;
+#else
+typedef union sh_event_occurred_u {
+	mmr_t	sh_event_occurred_regval;
+	struct {
+		mmr_t	reserved_0          : 33;
+		mmr_t	ii_int1             : 1;
+		mmr_t	ii_int0             : 1;
+		mmr_t	ipi_int             : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_event_occurred_s;
+} sh_event_occurred_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OVERFLOW"                     */
+/*                SHub Interrupt Event Occurred Overflow                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_event_overflow_u {
+	mmr_t	sh_event_overflow_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	reserved_0          : 36;
+	} sh_event_overflow_s;
+} sh_event_overflow_u_t;
+#else
+typedef union sh_event_overflow_u {
+	mmr_t	sh_event_overflow_regval;
+	struct {
+		mmr_t	reserved_0          : 36;
+		mmr_t	profile_int         : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_event_overflow_s;
+} sh_event_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_TIME"                      */
+/*                           Junk Bus Timing                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_time_u {
+	mmr_t	sh_junk_bus_time_regval;
+	struct {
+		mmr_t	fprom_setup_hold : 8;
+		mmr_t	fprom_enable     : 8;
+		mmr_t	uart_setup_hold  : 8;
+		mmr_t	uart_enable      : 8;
+		mmr_t	reserved_0       : 32;
+	} sh_junk_bus_time_s;
+} sh_junk_bus_time_u_t;
+#else
+typedef union sh_junk_bus_time_u {
+	mmr_t	sh_junk_bus_time_regval;
+	struct {
+		mmr_t	reserved_0       : 32;
+		mmr_t	uart_enable      : 8;
+		mmr_t	uart_setup_hold  : 8;
+		mmr_t	fprom_enable     : 8;
+		mmr_t	fprom_setup_hold : 8;
+	} sh_junk_bus_time_s;
+} sh_junk_bus_time_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_LATCH_TIME"                     */
+/*                        Junk Bus Latch Timing                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_latch_time_u {
+	mmr_t	sh_junk_latch_time_regval;
+	struct {
+		mmr_t	setup_hold  : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_junk_latch_time_s;
+} sh_junk_latch_time_u_t;
+#else
+typedef union sh_junk_latch_time_u {
+	mmr_t	sh_junk_latch_time_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	setup_hold  : 3;
+	} sh_junk_latch_time_s;
+} sh_junk_latch_time_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_NACK_RESET"                     */
+/*                     Junk Bus Nack Counter Reset                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_nack_reset_u {
+	mmr_t	sh_junk_nack_reset_regval;
+	struct {
+		mmr_t	pulse       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_junk_nack_reset_s;
+} sh_junk_nack_reset_u_t;
+#else
+typedef union sh_junk_nack_reset_u {
+	mmr_t	sh_junk_nack_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pulse       : 1;
+	} sh_junk_nack_reset_s;
+} sh_junk_nack_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED0"                      */
+/*                            Junk Bus LED0                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led0_u {
+	mmr_t	sh_junk_bus_led0_regval;
+	struct {
+		mmr_t	led0_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led0_s;
+} sh_junk_bus_led0_u_t;
+#else
+typedef union sh_junk_bus_led0_u {
+	mmr_t	sh_junk_bus_led0_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led0_data   : 8;
+	} sh_junk_bus_led0_s;
+} sh_junk_bus_led0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED1"                      */
+/*                            Junk Bus LED1                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led1_u {
+	mmr_t	sh_junk_bus_led1_regval;
+	struct {
+		mmr_t	led1_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led1_s;
+} sh_junk_bus_led1_u_t;
+#else
+typedef union sh_junk_bus_led1_u {
+	mmr_t	sh_junk_bus_led1_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led1_data   : 8;
+	} sh_junk_bus_led1_s;
+} sh_junk_bus_led1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED2"                      */
+/*                            Junk Bus LED2                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led2_u {
+	mmr_t	sh_junk_bus_led2_regval;
+	struct {
+		mmr_t	led2_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led2_s;
+} sh_junk_bus_led2_u_t;
+#else
+typedef union sh_junk_bus_led2_u {
+	mmr_t	sh_junk_bus_led2_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led2_data   : 8;
+	} sh_junk_bus_led2_s;
+} sh_junk_bus_led2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED3"                      */
+/*                            Junk Bus LED3                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led3_u {
+	mmr_t	sh_junk_bus_led3_regval;
+	struct {
+		mmr_t	led3_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led3_s;
+} sh_junk_bus_led3_u_t;
+#else
+typedef union sh_junk_bus_led3_u {
+	mmr_t	sh_junk_bus_led3_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led3_data   : 8;
+	} sh_junk_bus_led3_s;
+} sh_junk_bus_led3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_JUNK_ERROR_STATUS"                    */
+/*                        Junk Bus Error Status                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_error_status_u {
+	mmr_t	sh_junk_error_status_regval;
+	struct {
+		mmr_t	address     : 47;
+		mmr_t	reserved_0  : 1;
+		mmr_t	cmd         : 8;
+		mmr_t	mode        : 1;
+		mmr_t	status      : 4;
+		mmr_t	reserved_1  : 3;
+	} sh_junk_error_status_s;
+} sh_junk_error_status_u_t;
+#else
+typedef union sh_junk_error_status_u {
+	mmr_t	sh_junk_error_status_regval;
+	struct {
+		mmr_t	reserved_1  : 3;
+		mmr_t	status      : 4;
+		mmr_t	mode        : 1;
+		mmr_t	cmd         : 8;
+		mmr_t	reserved_0  : 1;
+		mmr_t	address     : 47;
+	} sh_junk_error_status_s;
+} sh_junk_error_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_stat_u {
+	mmr_t	sh_ni0_llp_stat_regval;
+	struct {
+		mmr_t	link_reset_state : 4;
+		mmr_t	reserved_0       : 60;
+	} sh_ni0_llp_stat_s;
+} sh_ni0_llp_stat_u_t;
+#else
+typedef union sh_ni0_llp_stat_u {
+	mmr_t	sh_ni0_llp_stat_regval;
+	struct {
+		mmr_t	reserved_0       : 60;
+		mmr_t	link_reset_state : 4;
+	} sh_ni0_llp_stat_s;
+} sh_ni0_llp_stat_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_reset_u {
+	mmr_t	sh_ni0_llp_reset_regval;
+	struct {
+		mmr_t	link        : 1;
+		mmr_t	warm        : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_ni0_llp_reset_s;
+} sh_ni0_llp_reset_u_t;
+#else
+typedef union sh_ni0_llp_reset_u {
+	mmr_t	sh_ni0_llp_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	warm        : 1;
+		mmr_t	link        : 1;
+	} sh_ni0_llp_reset_s;
+} sh_ni0_llp_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_reset_en_u {
+	mmr_t	sh_ni0_llp_reset_en_regval;
+	struct {
+		mmr_t	ok          : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ni0_llp_reset_en_s;
+} sh_ni0_llp_reset_en_u_t;
+#else
+typedef union sh_ni0_llp_reset_en_u {
+	mmr_t	sh_ni0_llp_reset_en_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ok          : 1;
+	} sh_ni0_llp_reset_en_s;
+} sh_ni0_llp_reset_en_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_chan_mode_u {
+	mmr_t	sh_ni0_llp_chan_mode_regval;
+	struct {
+		mmr_t	bitmode32         : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	reserved_0        : 59;
+	} sh_ni0_llp_chan_mode_s;
+} sh_ni0_llp_chan_mode_u_t;
+#else
+typedef union sh_ni0_llp_chan_mode_u {
+	mmr_t	sh_ni0_llp_chan_mode_regval;
+	struct {
+		mmr_t	reserved_0        : 59;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	bitmode32         : 1;
+	} sh_ni0_llp_chan_mode_s;
+} sh_ni0_llp_chan_mode_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_config_u {
+	mmr_t	sh_ni0_llp_config_regval;
+	struct {
+		mmr_t	maxburst    : 10;
+		mmr_t	maxretry    : 10;
+		mmr_t	nulltimeout : 6;
+		mmr_t	ftu_time    : 12;
+		mmr_t	reserved_0  : 26;
+	} sh_ni0_llp_config_s;
+} sh_ni0_llp_config_u_t;
+#else
+typedef union sh_ni0_llp_config_u {
+	mmr_t	sh_ni0_llp_config_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	ftu_time    : 12;
+		mmr_t	nulltimeout : 6;
+		mmr_t	maxretry    : 10;
+		mmr_t	maxburst    : 10;
+	} sh_ni0_llp_config_s;
+} sh_ni0_llp_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_test_ctl_u {
+	mmr_t	sh_ni0_llp_test_ctl_regval;
+	struct {
+		mmr_t	pattern        : 40;
+		mmr_t	send_test_mode : 2;
+		mmr_t	reserved_0     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	noise_mode     : 2;
+		mmr_t	armcapture     : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	captured       : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	reserved_2     : 1;
+	} sh_ni0_llp_test_ctl_s;
+} sh_ni0_llp_test_ctl_u_t;
+#else
+typedef union sh_ni0_llp_test_ctl_u {
+	mmr_t	sh_ni0_llp_test_ctl_regval;
+	struct {
+		mmr_t	reserved_2     : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	captured       : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	armcapture     : 1;
+		mmr_t	noise_mode     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	reserved_1     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	send_test_mode : 2;
+		mmr_t	pattern        : 40;
+	} sh_ni0_llp_test_ctl_s;
+} sh_ni0_llp_test_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_wd1_u {
+	mmr_t	sh_ni0_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd1_s;
+} sh_ni0_llp_capt_wd1_u_t;
+#else
+typedef union sh_ni0_llp_capt_wd1_u {
+	mmr_t	sh_ni0_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd1_s;
+} sh_ni0_llp_capt_wd1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_wd2_u {
+	mmr_t	sh_ni0_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd2_s;
+} sh_ni0_llp_capt_wd2_u_t;
+#else
+typedef union sh_ni0_llp_capt_wd2_u {
+	mmr_t	sh_ni0_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd2_s;
+} sh_ni0_llp_capt_wd2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_sbcb_u {
+	mmr_t	sh_ni0_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	capturedrcvsbsn  : 16;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	reserved_0       : 27;
+	} sh_ni0_llp_capt_sbcb_s;
+} sh_ni0_llp_capt_sbcb_u_t;
+#else
+typedef union sh_ni0_llp_capt_sbcb_u {
+	mmr_t	sh_ni0_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	reserved_0       : 27;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	capturedrcvsbsn  : 16;
+	} sh_ni0_llp_capt_sbcb_s;
+} sh_ni0_llp_capt_sbcb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_ERR"                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_err_u {
+	mmr_t	sh_ni0_llp_err_regval;
+	struct {
+		mmr_t	rx_sn_err_count : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	retry_count     : 8;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	squash          : 1;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	reserved_0      : 11;
+	} sh_ni0_llp_err_s;
+} sh_ni0_llp_err_u_t;
+#else
+typedef union sh_ni0_llp_err_u {
+	mmr_t	sh_ni0_llp_err_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	squash          : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	retry_count     : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	rx_sn_err_count : 8;
+	} sh_ni0_llp_err_s;
+} sh_ni0_llp_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_stat_u {
+	mmr_t	sh_ni1_llp_stat_regval;
+	struct {
+		mmr_t	link_reset_state : 4;
+		mmr_t	reserved_0       : 60;
+	} sh_ni1_llp_stat_s;
+} sh_ni1_llp_stat_u_t;
+#else
+typedef union sh_ni1_llp_stat_u {
+	mmr_t	sh_ni1_llp_stat_regval;
+	struct {
+		mmr_t	reserved_0       : 60;
+		mmr_t	link_reset_state : 4;
+	} sh_ni1_llp_stat_s;
+} sh_ni1_llp_stat_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_reset_u {
+	mmr_t	sh_ni1_llp_reset_regval;
+	struct {
+		mmr_t	link        : 1;
+		mmr_t	warm        : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_ni1_llp_reset_s;
+} sh_ni1_llp_reset_u_t;
+#else
+typedef union sh_ni1_llp_reset_u {
+	mmr_t	sh_ni1_llp_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	warm        : 1;
+		mmr_t	link        : 1;
+	} sh_ni1_llp_reset_s;
+} sh_ni1_llp_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_reset_en_u {
+	mmr_t	sh_ni1_llp_reset_en_regval;
+	struct {
+		mmr_t	ok          : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ni1_llp_reset_en_s;
+} sh_ni1_llp_reset_en_u_t;
+#else
+typedef union sh_ni1_llp_reset_en_u {
+	mmr_t	sh_ni1_llp_reset_en_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ok          : 1;
+	} sh_ni1_llp_reset_en_s;
+} sh_ni1_llp_reset_en_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_chan_mode_u {
+	mmr_t	sh_ni1_llp_chan_mode_regval;
+	struct {
+		mmr_t	bitmode32         : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	reserved_0        : 59;
+	} sh_ni1_llp_chan_mode_s;
+} sh_ni1_llp_chan_mode_u_t;
+#else
+typedef union sh_ni1_llp_chan_mode_u {
+	mmr_t	sh_ni1_llp_chan_mode_regval;
+	struct {
+		mmr_t	reserved_0        : 59;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	bitmode32         : 1;
+	} sh_ni1_llp_chan_mode_s;
+} sh_ni1_llp_chan_mode_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_config_u {
+	mmr_t	sh_ni1_llp_config_regval;
+	struct {
+		mmr_t	maxburst    : 10;
+		mmr_t	maxretry    : 10;
+		mmr_t	nulltimeout : 6;
+		mmr_t	ftu_time    : 12;
+		mmr_t	reserved_0  : 26;
+	} sh_ni1_llp_config_s;
+} sh_ni1_llp_config_u_t;
+#else
+typedef union sh_ni1_llp_config_u {
+	mmr_t	sh_ni1_llp_config_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	ftu_time    : 12;
+		mmr_t	nulltimeout : 6;
+		mmr_t	maxretry    : 10;
+		mmr_t	maxburst    : 10;
+	} sh_ni1_llp_config_s;
+} sh_ni1_llp_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_test_ctl_u {
+	mmr_t	sh_ni1_llp_test_ctl_regval;
+	struct {
+		mmr_t	pattern        : 40;
+		mmr_t	send_test_mode : 2;
+		mmr_t	reserved_0     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	noise_mode     : 2;
+		mmr_t	armcapture     : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	captured       : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	reserved_2     : 1;
+	} sh_ni1_llp_test_ctl_s;
+} sh_ni1_llp_test_ctl_u_t;
+#else
+typedef union sh_ni1_llp_test_ctl_u {
+	mmr_t	sh_ni1_llp_test_ctl_regval;
+	struct {
+		mmr_t	reserved_2     : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	captured       : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	armcapture     : 1;
+		mmr_t	noise_mode     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	reserved_1     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	send_test_mode : 2;
+		mmr_t	pattern        : 40;
+	} sh_ni1_llp_test_ctl_s;
+} sh_ni1_llp_test_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_wd1_u {
+	mmr_t	sh_ni1_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd1_s;
+} sh_ni1_llp_capt_wd1_u_t;
+#else
+typedef union sh_ni1_llp_capt_wd1_u {
+	mmr_t	sh_ni1_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd1_s;
+} sh_ni1_llp_capt_wd1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_wd2_u {
+	mmr_t	sh_ni1_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd2_s;
+} sh_ni1_llp_capt_wd2_u_t;
+#else
+typedef union sh_ni1_llp_capt_wd2_u {
+	mmr_t	sh_ni1_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd2_s;
+} sh_ni1_llp_capt_wd2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_sbcb_u {
+	mmr_t	sh_ni1_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	capturedrcvsbsn  : 16;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	reserved_0       : 27;
+	} sh_ni1_llp_capt_sbcb_s;
+} sh_ni1_llp_capt_sbcb_u_t;
+#else
+typedef union sh_ni1_llp_capt_sbcb_u {
+	mmr_t	sh_ni1_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	reserved_0       : 27;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	capturedrcvsbsn  : 16;
+	} sh_ni1_llp_capt_sbcb_s;
+} sh_ni1_llp_capt_sbcb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_ERR"                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_err_u {
+	mmr_t	sh_ni1_llp_err_regval;
+	struct {
+		mmr_t	rx_sn_err_count : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	retry_count     : 8;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	squash          : 1;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	reserved_0      : 11;
+	} sh_ni1_llp_err_s;
+} sh_ni1_llp_err_u_t;
+#else
+typedef union sh_ni1_llp_err_u {
+	mmr_t	sh_ni1_llp_err_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	squash          : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	retry_count     : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	rx_sn_err_count : 8;
+	} sh_ni1_llp_err_s;
+} sh_ni1_llp_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni0_llp_to_fifo02_flow_s;
+} sh_xnni0_llp_to_fifo02_flow_u_t;
+#else
+typedef union sh_xnni0_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_llp_to_fifo02_flow_s;
+} sh_xnni0_llp_to_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni0_llp_to_fifo13_flow_s;
+} sh_xnni0_llp_to_fifo13_flow_u_t;
+#else
+typedef union sh_xnni0_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_llp_to_fifo13_flow_s;
+} sh_xnni0_llp_to_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_debit_flow_u {
+	mmr_t	sh_xnni0_llp_debit_flow_regval;
+	struct {
+		mmr_t	debit_vc0_dyn : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_7    : 3;
+	} sh_xnni0_llp_debit_flow_s;
+} sh_xnni0_llp_debit_flow_u_t;
+#else
+typedef union sh_xnni0_llp_debit_flow_u {
+	mmr_t	sh_xnni0_llp_debit_flow_regval;
+	struct {
+		mmr_t	reserved_7    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_dyn : 5;
+	} sh_xnni0_llp_debit_flow_s;
+} sh_xnni0_llp_debit_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_0_flow_u {
+	mmr_t	sh_xnni0_link_0_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_0_flow_s;
+} sh_xnni0_link_0_flow_u_t;
+#else
+typedef union sh_xnni0_link_0_flow_u {
+	mmr_t	sh_xnni0_link_0_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_link_0_flow_s;
+} sh_xnni0_link_0_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_1_flow_u {
+	mmr_t	sh_xnni0_link_1_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_1_flow_s;
+} sh_xnni0_link_1_flow_u_t;
+#else
+typedef union sh_xnni0_link_1_flow_u {
+	mmr_t	sh_xnni0_link_1_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni0_link_1_flow_s;
+} sh_xnni0_link_1_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_2_flow_u {
+	mmr_t	sh_xnni0_link_2_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_2_flow_s;
+} sh_xnni0_link_2_flow_u_t;
+#else
+typedef union sh_xnni0_link_2_flow_u {
+	mmr_t	sh_xnni0_link_2_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni0_link_2_flow_s;
+} sh_xnni0_link_2_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_3_flow_u {
+	mmr_t	sh_xnni0_link_3_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_3_flow_s;
+} sh_xnni0_link_3_flow_u_t;
+#else
+typedef union sh_xnni0_link_3_flow_u {
+	mmr_t	sh_xnni0_link_3_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni0_link_3_flow_s;
+} sh_xnni0_link_3_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni1_llp_to_fifo02_flow_s;
+} sh_xnni1_llp_to_fifo02_flow_u_t;
+#else
+typedef union sh_xnni1_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_llp_to_fifo02_flow_s;
+} sh_xnni1_llp_to_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni1_llp_to_fifo13_flow_s;
+} sh_xnni1_llp_to_fifo13_flow_u_t;
+#else
+typedef union sh_xnni1_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_llp_to_fifo13_flow_s;
+} sh_xnni1_llp_to_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_debit_flow_u {
+	mmr_t	sh_xnni1_llp_debit_flow_regval;
+	struct {
+		mmr_t	debit_vc0_dyn : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_7    : 3;
+	} sh_xnni1_llp_debit_flow_s;
+} sh_xnni1_llp_debit_flow_u_t;
+#else
+typedef union sh_xnni1_llp_debit_flow_u {
+	mmr_t	sh_xnni1_llp_debit_flow_regval;
+	struct {
+		mmr_t	reserved_7    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_dyn : 5;
+	} sh_xnni1_llp_debit_flow_s;
+} sh_xnni1_llp_debit_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_0_flow_u {
+	mmr_t	sh_xnni1_link_0_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_0_flow_s;
+} sh_xnni1_link_0_flow_u_t;
+#else
+typedef union sh_xnni1_link_0_flow_u {
+	mmr_t	sh_xnni1_link_0_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_link_0_flow_s;
+} sh_xnni1_link_0_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_1_flow_u {
+	mmr_t	sh_xnni1_link_1_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_1_flow_s;
+} sh_xnni1_link_1_flow_u_t;
+#else
+typedef union sh_xnni1_link_1_flow_u {
+	mmr_t	sh_xnni1_link_1_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni1_link_1_flow_s;
+} sh_xnni1_link_1_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_2_flow_u {
+	mmr_t	sh_xnni1_link_2_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_2_flow_s;
+} sh_xnni1_link_2_flow_u_t;
+#else
+typedef union sh_xnni1_link_2_flow_u {
+	mmr_t	sh_xnni1_link_2_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni1_link_2_flow_s;
+} sh_xnni1_link_2_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_3_flow_u {
+	mmr_t	sh_xnni1_link_3_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_3_flow_s;
+} sh_xnni1_link_3_flow_u_t;
+#else
+typedef union sh_xnni1_link_3_flow_u {
+	mmr_t	sh_xnni1_link_3_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni1_link_3_flow_s;
+} sh_xnni1_link_3_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_IILB_LOCAL_TABLE"                    */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_local_table_u {
+	mmr_t	sh_iilb_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	valid       : 1;
+	} sh_iilb_local_table_s;
+} sh_iilb_local_table_u_t;
+#else
+typedef union sh_iilb_local_table_u {
+	mmr_t	sh_iilb_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_local_table_s;
+} sh_iilb_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_IILB_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_global_table_u {
+	mmr_t	sh_iilb_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	valid       : 1;
+	} sh_iilb_global_table_s;
+} sh_iilb_global_table_u_t;
+#else
+typedef union sh_iilb_global_table_u {
+	mmr_t	sh_iilb_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_global_table_s;
+} sh_iilb_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_OVER_RIDE_TABLE"                  */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_over_ride_table_u {
+	mmr_t	sh_iilb_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	enable      : 1;
+	} sh_iilb_over_ride_table_s;
+} sh_iilb_over_ride_table_u_t;
+#else
+typedef union sh_iilb_over_ride_table_u {
+	mmr_t	sh_iilb_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_over_ride_table_s;
+} sh_iilb_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_rsp_plane_hint_u {
+	mmr_t	sh_iilb_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_iilb_rsp_plane_hint_s;
+} sh_iilb_rsp_plane_hint_u_t;
+#else
+typedef union sh_iilb_rsp_plane_hint_u {
+	mmr_t	sh_iilb_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_iilb_rsp_plane_hint_s;
+} sh_iilb_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_local_table_u {
+	mmr_t	sh_pi_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_pi_local_table_s;
+} sh_pi_local_table_u_t;
+#else
+typedef union sh_pi_local_table_u {
+	mmr_t	sh_pi_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_local_table_s;
+} sh_pi_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_global_table_u {
+	mmr_t	sh_pi_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_pi_global_table_s;
+} sh_pi_global_table_u_t;
+#else
+typedef union sh_pi_global_table_u {
+	mmr_t	sh_pi_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_global_table_s;
+} sh_pi_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_over_ride_table_u {
+	mmr_t	sh_pi_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	enable      : 1;
+	} sh_pi_over_ride_table_s;
+} sh_pi_over_ride_table_u_t;
+#else
+typedef union sh_pi_over_ride_table_u {
+	mmr_t	sh_pi_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_over_ride_table_s;
+} sh_pi_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_rsp_plane_hint_u {
+	mmr_t	sh_pi_rsp_plane_hint_regval;
+	struct {
+		mmr_t	invert      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_pi_rsp_plane_hint_s;
+} sh_pi_rsp_plane_hint_u_t;
+#else
+typedef union sh_pi_rsp_plane_hint_u {
+	mmr_t	sh_pi_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	invert      : 1;
+	} sh_pi_rsp_plane_hint_s;
+} sh_pi_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_local_table_u {
+	mmr_t	sh_ni0_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni0_local_table_s;
+} sh_ni0_local_table_u_t;
+#else
+typedef union sh_ni0_local_table_u {
+	mmr_t	sh_ni0_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_local_table_s;
+} sh_ni0_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_global_table_u {
+	mmr_t	sh_ni0_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni0_global_table_s;
+} sh_ni0_global_table_u_t;
+#else
+typedef union sh_ni0_global_table_u {
+	mmr_t	sh_ni0_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_global_table_s;
+} sh_ni0_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_over_ride_table_u {
+	mmr_t	sh_ni0_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	enable      : 1;
+	} sh_ni0_over_ride_table_s;
+} sh_ni0_over_ride_table_u_t;
+#else
+typedef union sh_ni0_over_ride_table_u {
+	mmr_t	sh_ni0_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_over_ride_table_s;
+} sh_ni0_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_rsp_plane_hint_u {
+	mmr_t	sh_ni0_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni0_rsp_plane_hint_s;
+} sh_ni0_rsp_plane_hint_u_t;
+#else
+typedef union sh_ni0_rsp_plane_hint_u {
+	mmr_t	sh_ni0_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni0_rsp_plane_hint_s;
+} sh_ni0_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_local_table_u {
+	mmr_t	sh_ni1_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni1_local_table_s;
+} sh_ni1_local_table_u_t;
+#else
+typedef union sh_ni1_local_table_u {
+	mmr_t	sh_ni1_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_local_table_s;
+} sh_ni1_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_global_table_u {
+	mmr_t	sh_ni1_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni1_global_table_s;
+} sh_ni1_global_table_u_t;
+#else
+typedef union sh_ni1_global_table_u {
+	mmr_t	sh_ni1_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_global_table_s;
+} sh_ni1_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_over_ride_table_u {
+	mmr_t	sh_ni1_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	enable      : 1;
+	} sh_ni1_over_ride_table_s;
+} sh_ni1_over_ride_table_u_t;
+#else
+typedef union sh_ni1_over_ride_table_u {
+	mmr_t	sh_ni1_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_over_ride_table_s;
+} sh_ni1_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_rsp_plane_hint_u {
+	mmr_t	sh_ni1_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni1_rsp_plane_hint_s;
+} sh_ni1_rsp_plane_hint_u_t;
+#else
+typedef union sh_ni1_rsp_plane_hint_u {
+	mmr_t	sh_ni1_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni1_rsp_plane_hint_s;
+} sh_ni1_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_local_table_u {
+	mmr_t	sh_md_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_md_local_table_s;
+} sh_md_local_table_u_t;
+#else
+typedef union sh_md_local_table_u {
+	mmr_t	sh_md_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_local_table_s;
+} sh_md_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_global_table_u {
+	mmr_t	sh_md_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_md_global_table_s;
+} sh_md_global_table_u_t;
+#else
+typedef union sh_md_global_table_u {
+	mmr_t	sh_md_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_global_table_s;
+} sh_md_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_over_ride_table_u {
+	mmr_t	sh_md_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	enable      : 1;
+	} sh_md_over_ride_table_s;
+} sh_md_over_ride_table_u_t;
+#else
+typedef union sh_md_over_ride_table_u {
+	mmr_t	sh_md_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_over_ride_table_s;
+} sh_md_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_rsp_plane_hint_u {
+	mmr_t	sh_md_rsp_plane_hint_regval;
+	struct {
+		mmr_t	invert      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_md_rsp_plane_hint_s;
+} sh_md_rsp_plane_hint_u_t;
+#else
+typedef union sh_md_rsp_plane_hint_u {
+	mmr_t	sh_md_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	invert      : 1;
+	} sh_md_rsp_plane_hint_s;
+} sh_md_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LIQ_CTL"                       */
+/*                       Local Block LIQ Control                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_liq_ctl_u {
+	mmr_t	sh_lb_liq_ctl_regval;
+	struct {
+		mmr_t	liq_req_ctl        : 5;
+		mmr_t	reserved_0         : 3;
+		mmr_t	liq_rpl_ctl        : 4;
+		mmr_t	reserved_1         : 4;
+		mmr_t	force_rq_credit    : 1;
+		mmr_t	force_rp_credit    : 1;
+		mmr_t	force_linvv_credit : 1;
+		mmr_t	reserved_2         : 45;
+	} sh_lb_liq_ctl_s;
+} sh_lb_liq_ctl_u_t;
+#else
+typedef union sh_lb_liq_ctl_u {
+	mmr_t	sh_lb_liq_ctl_regval;
+	struct {
+		mmr_t	reserved_2         : 45;
+		mmr_t	force_linvv_credit : 1;
+		mmr_t	force_rp_credit    : 1;
+		mmr_t	force_rq_credit    : 1;
+		mmr_t	reserved_1         : 4;
+		mmr_t	liq_rpl_ctl        : 4;
+		mmr_t	reserved_0         : 3;
+		mmr_t	liq_req_ctl        : 5;
+	} sh_lb_liq_ctl_s;
+} sh_lb_liq_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LOQ_CTL"                       */
+/*                       Local Block LOQ Control                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_loq_ctl_u {
+	mmr_t	sh_lb_loq_ctl_regval;
+	struct {
+		mmr_t	loq_req_ctl : 1;
+		mmr_t	loq_rpl_ctl : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_lb_loq_ctl_s;
+} sh_lb_loq_ctl_u_t;
+#else
+typedef union sh_lb_loq_ctl_u {
+	mmr_t	sh_lb_loq_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	loq_rpl_ctl : 1;
+		mmr_t	loq_req_ctl : 1;
+	} sh_lb_loq_ctl_s;
+} sh_lb_loq_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REP_CREDIT_CNT"                  */
+/*               Maximum number of reply credits from XN                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_max_rep_credit_cnt_u {
+	mmr_t	sh_lb_max_rep_credit_cnt_regval;
+	struct {
+		mmr_t	max_cnt     : 5;
+		mmr_t	reserved_0  : 59;
+	} sh_lb_max_rep_credit_cnt_s;
+} sh_lb_max_rep_credit_cnt_u_t;
+#else
+typedef union sh_lb_max_rep_credit_cnt_u {
+	mmr_t	sh_lb_max_rep_credit_cnt_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	max_cnt     : 5;
+	} sh_lb_max_rep_credit_cnt_s;
+} sh_lb_max_rep_credit_cnt_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REQ_CREDIT_CNT"                  */
+/*              Maximum number of request credits from XN               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_max_req_credit_cnt_u {
+	mmr_t	sh_lb_max_req_credit_cnt_regval;
+	struct {
+		mmr_t	max_cnt     : 5;
+		mmr_t	reserved_0  : 59;
+	} sh_lb_max_req_credit_cnt_s;
+} sh_lb_max_req_credit_cnt_u_t;
+#else
+typedef union sh_lb_max_req_credit_cnt_u {
+	mmr_t	sh_lb_max_req_credit_cnt_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	max_cnt     : 5;
+	} sh_lb_max_req_credit_cnt_s;
+} sh_lb_max_req_credit_cnt_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_PIO_TIME_OUT"                      */
+/*                    Local Block PIO time out value                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_time_out_u {
+	mmr_t	sh_pio_time_out_regval;
+	struct {
+		mmr_t	value       : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_pio_time_out_s;
+} sh_pio_time_out_u_t;
+#else
+typedef union sh_pio_time_out_u {
+	mmr_t	sh_pio_time_out_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	value       : 16;
+	} sh_pio_time_out_s;
+} sh_pio_time_out_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_NACK_RESET"                     */
+/*               Local Block PIO Reset for nack counters                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_nack_reset_u {
+	mmr_t	sh_pio_nack_reset_regval;
+	struct {
+		mmr_t	pulse       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_pio_nack_reset_s;
+} sh_pio_nack_reset_u_t;
+#else
+typedef union sh_pio_nack_reset_u {
+	mmr_t	sh_pio_nack_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pulse       : 1;
+	} sh_pio_nack_reset_s;
+} sh_pio_nack_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_CONVEYOR_BELT_TIME_OUT"                 */
+/*               Local Block conveyor belt time out value               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_conveyor_belt_time_out_u {
+	mmr_t	sh_conveyor_belt_time_out_regval;
+	struct {
+		mmr_t	value       : 12;
+		mmr_t	reserved_0  : 52;
+	} sh_conveyor_belt_time_out_s;
+} sh_conveyor_belt_time_out_u_t;
+#else
+typedef union sh_conveyor_belt_time_out_u {
+	mmr_t	sh_conveyor_belt_time_out_regval;
+	struct {
+		mmr_t	reserved_0  : 52;
+		mmr_t	value       : 12;
+	} sh_conveyor_belt_time_out_s;
+} sh_conveyor_belt_time_out_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_CREDIT_STATUS"                    */
+/*                    Credit Counter Status Register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_credit_status_u {
+	mmr_t	sh_lb_credit_status_regval;
+	struct {
+		mmr_t	liq_rq_credit : 5;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_1    : 2;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	reserved_2    : 36;
+	} sh_lb_credit_status_s;
+} sh_lb_credit_status_u_t;
+#else
+typedef union sh_lb_credit_status_u {
+	mmr_t	sh_lb_credit_status_regval;
+	struct {
+		mmr_t	reserved_2    : 36;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	reserved_1    : 2;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rq_credit : 5;
+	} sh_lb_credit_status_s;
+} sh_lb_credit_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_LOCAL_SEL"                   */
+/*                         LB Debug Port Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_local_sel_u {
+	mmr_t	sh_lb_debug_local_sel_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_lb_debug_local_sel_s;
+} sh_lb_debug_local_sel_u_t;
+#else
+typedef union sh_lb_debug_local_sel_u {
+	mmr_t	sh_lb_debug_local_sel_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_lb_debug_local_sel_s;
+} sh_lb_debug_local_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_PERF_SEL"                    */
+/*                   LB Debug Port Performance Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_perf_sel_u {
+	mmr_t	sh_lb_debug_perf_sel_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_15         : 1;
+	} sh_lb_debug_perf_sel_s;
+} sh_lb_debug_perf_sel_u_t;
+#else
+typedef union sh_lb_debug_perf_sel_u {
+	mmr_t	sh_lb_debug_perf_sel_regval;
+	struct {
+		mmr_t	reserved_15         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_lb_debug_perf_sel_s;
+} sh_lb_debug_perf_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_TRIG_SEL"                    */
+/*                       LB Debug Trigger Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_trig_sel_u {
+	mmr_t	sh_lb_debug_trig_sel_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_lb_debug_trig_sel_s;
+} sh_lb_debug_trig_sel_u_t;
+#else
+typedef union sh_lb_debug_trig_sel_u {
+	mmr_t	sh_lb_debug_trig_sel_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_lb_debug_trig_sel_s;
+} sh_lb_debug_trig_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_1"                    */
+/*                  LB Error capture information: HDR1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_1_u {
+	mmr_t	sh_lb_error_detail_1_regval;
+	struct {
+		mmr_t	command     : 8;
+		mmr_t	suppl       : 14;
+		mmr_t	reserved_0  : 2;
+		mmr_t	source      : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	dest        : 3;
+		mmr_t	reserved_2  : 5;
+		mmr_t	hdr_err     : 1;
+		mmr_t	data_err    : 1;
+		mmr_t	reserved_3  : 13;
+		mmr_t	valid       : 1;
+	} sh_lb_error_detail_1_s;
+} sh_lb_error_detail_1_u_t;
+#else
+typedef union sh_lb_error_detail_1_u {
+	mmr_t	sh_lb_error_detail_1_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_3  : 13;
+		mmr_t	data_err    : 1;
+		mmr_t	hdr_err     : 1;
+		mmr_t	reserved_2  : 5;
+		mmr_t	dest        : 3;
+		mmr_t	reserved_1  : 2;
+		mmr_t	source      : 14;
+		mmr_t	reserved_0  : 2;
+		mmr_t	suppl       : 14;
+		mmr_t	command     : 8;
+	} sh_lb_error_detail_1_s;
+} sh_lb_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_2"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_2_u {
+	mmr_t	sh_lb_error_detail_2_regval;
+	struct {
+		mmr_t	address     : 47;
+		mmr_t	reserved_0  : 17;
+	} sh_lb_error_detail_2_s;
+} sh_lb_error_detail_2_u_t;
+#else
+typedef union sh_lb_error_detail_2_u {
+	mmr_t	sh_lb_error_detail_2_regval;
+	struct {
+		mmr_t	reserved_0  : 17;
+		mmr_t	address     : 47;
+	} sh_lb_error_detail_2_s;
+} sh_lb_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_3"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_3_u {
+	mmr_t	sh_lb_error_detail_3_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_lb_error_detail_3_s;
+} sh_lb_error_detail_3_u_t;
+#else
+typedef union sh_lb_error_detail_3_u {
+	mmr_t	sh_lb_error_detail_3_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_lb_error_detail_3_s;
+} sh_lb_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_4"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_4_u {
+	mmr_t	sh_lb_error_detail_4_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_lb_error_detail_4_s;
+} sh_lb_error_detail_4_u_t;
+#else
+typedef union sh_lb_error_detail_4_u {
+	mmr_t	sh_lb_error_detail_4_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_lb_error_detail_4_s;
+} sh_lb_error_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_5"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_5_u {
+	mmr_t	sh_lb_error_detail_5_regval;
+	struct {
+		mmr_t	read_retry       : 1;
+		mmr_t	ptc1_write       : 1;
+		mmr_t	write_retry      : 1;
+		mmr_t	count_a_overflow : 1;
+		mmr_t	count_b_overflow : 1;
+		mmr_t	nack_a_timeout   : 1;
+		mmr_t	nack_b_timeout   : 1;
+		mmr_t	reserved_0       : 57;
+	} sh_lb_error_detail_5_s;
+} sh_lb_error_detail_5_u_t;
+#else
+typedef union sh_lb_error_detail_5_u {
+	mmr_t	sh_lb_error_detail_5_regval;
+	struct {
+		mmr_t	reserved_0       : 57;
+		mmr_t	nack_b_timeout   : 1;
+		mmr_t	nack_a_timeout   : 1;
+		mmr_t	count_b_overflow : 1;
+		mmr_t	count_a_overflow : 1;
+		mmr_t	write_retry      : 1;
+		mmr_t	ptc1_write       : 1;
+		mmr_t	read_retry       : 1;
+	} sh_lb_error_detail_5_s;
+} sh_lb_error_detail_5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_ERROR_MASK"                      */
+/*                            LB Error Mask                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_mask_u {
+	mmr_t	sh_lb_error_mask_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_error_mask_s;
+} sh_lb_error_mask_u_t;
+#else
+typedef union sh_lb_error_mask_u {
+	mmr_t	sh_lb_error_mask_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_error_mask_s;
+} sh_lb_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_OVERFLOW"                    */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_overflow_u {
+	mmr_t	sh_lb_error_overflow_regval;
+	struct {
+		mmr_t	rq_bad_cmd_ovrfl            : 1;
+		mmr_t	rp_bad_cmd_ovrfl            : 1;
+		mmr_t	rq_short_ovrfl              : 1;
+		mmr_t	rp_short_ovrfl              : 1;
+		mmr_t	rq_long_ovrfl               : 1;
+		mmr_t	rp_long_ovrfl               : 1;
+		mmr_t	rq_bad_data_ovrfl           : 1;
+		mmr_t	rp_bad_data_ovrfl           : 1;
+		mmr_t	rq_bad_addr_ovrfl           : 1;
+		mmr_t	rq_time_out_ovrfl           : 1;
+		mmr_t	linvv_overflow_ovrfl        : 1;
+		mmr_t	unexpected_linv_ovrfl       : 1;
+		mmr_t	ptc_1_timeout_ovrfl         : 1;
+		mmr_t	junk_bus_err_ovrfl          : 1;
+		mmr_t	pio_cb_err_ovrfl            : 1;
+		mmr_t	vector_rq_route_error_ovrfl : 1;
+		mmr_t	vector_rp_route_error_ovrfl : 1;
+		mmr_t	gclk_drop_ovrfl             : 1;
+		mmr_t	rq_fifo_error_ovrfl         : 1;
+		mmr_t	rp_fifo_error_ovrfl         : 1;
+		mmr_t	unexp_valid_ovrfl           : 1;
+		mmr_t	rq_credit_overflow_ovrfl    : 1;
+		mmr_t	rp_credit_overflow_ovrfl    : 1;
+		mmr_t	reserved_0                  : 41;
+	} sh_lb_error_overflow_s;
+} sh_lb_error_overflow_u_t;
+#else
+typedef union sh_lb_error_overflow_u {
+	mmr_t	sh_lb_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 41;
+		mmr_t	rp_credit_overflow_ovrfl    : 1;
+		mmr_t	rq_credit_overflow_ovrfl    : 1;
+		mmr_t	unexp_valid_ovrfl           : 1;
+		mmr_t	rp_fifo_error_ovrfl         : 1;
+		mmr_t	rq_fifo_error_ovrfl         : 1;
+		mmr_t	gclk_drop_ovrfl             : 1;
+		mmr_t	vector_rp_route_error_ovrfl : 1;
+		mmr_t	vector_rq_route_error_ovrfl : 1;
+		mmr_t	pio_cb_err_ovrfl            : 1;
+		mmr_t	junk_bus_err_ovrfl          : 1;
+		mmr_t	ptc_1_timeout_ovrfl         : 1;
+		mmr_t	unexpected_linv_ovrfl       : 1;
+		mmr_t	linvv_overflow_ovrfl        : 1;
+		mmr_t	rq_time_out_ovrfl           : 1;
+		mmr_t	rq_bad_addr_ovrfl           : 1;
+		mmr_t	rp_bad_data_ovrfl           : 1;
+		mmr_t	rq_bad_data_ovrfl           : 1;
+		mmr_t	rp_long_ovrfl               : 1;
+		mmr_t	rq_long_ovrfl               : 1;
+		mmr_t	rp_short_ovrfl              : 1;
+		mmr_t	rq_short_ovrfl              : 1;
+		mmr_t	rp_bad_cmd_ovrfl            : 1;
+		mmr_t	rq_bad_cmd_ovrfl            : 1;
+	} sh_lb_error_overflow_s;
+} sh_lb_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_ERROR_SUMMARY"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_summary_u {
+	mmr_t	sh_lb_error_summary_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_error_summary_s;
+} sh_lb_error_summary_u_t;
+#else
+typedef union sh_lb_error_summary_u {
+	mmr_t	sh_lb_error_summary_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_error_summary_s;
+} sh_lb_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_FIRST_ERROR"                     */
+/*                            LB First Error                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_first_error_u {
+	mmr_t	sh_lb_first_error_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_first_error_s;
+} sh_lb_first_error_u_t;
+#else
+typedef union sh_lb_first_error_u {
+	mmr_t	sh_lb_first_error_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_first_error_s;
+} sh_lb_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_LAST_CREDIT"                     */
+/*                    Credit counter status register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_last_credit_u {
+	mmr_t	sh_lb_last_credit_regval;
+	struct {
+		mmr_t	liq_rq_credit : 5;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_1    : 2;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	reserved_2    : 36;
+	} sh_lb_last_credit_s;
+} sh_lb_last_credit_u_t;
+#else
+typedef union sh_lb_last_credit_u {
+	mmr_t	sh_lb_last_credit_regval;
+	struct {
+		mmr_t	reserved_2    : 36;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	reserved_1    : 2;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rq_credit : 5;
+	} sh_lb_last_credit_s;
+} sh_lb_last_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_NACK_STATUS"                     */
+/*                     Nack Counter Status Register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_nack_status_u {
+	mmr_t	sh_lb_nack_status_regval;
+	struct {
+		mmr_t	pio_nack_a       : 12;
+		mmr_t	reserved_0       : 4;
+		mmr_t	pio_nack_b       : 12;
+		mmr_t	reserved_1       : 4;
+		mmr_t	junk_nack        : 16;
+		mmr_t	cb_timeout_count : 12;
+		mmr_t	cb_state         : 2;
+		mmr_t	reserved_2       : 2;
+	} sh_lb_nack_status_s;
+} sh_lb_nack_status_u_t;
+#else
+typedef union sh_lb_nack_status_u {
+	mmr_t	sh_lb_nack_status_regval;
+	struct {
+		mmr_t	reserved_2       : 2;
+		mmr_t	cb_state         : 2;
+		mmr_t	cb_timeout_count : 12;
+		mmr_t	junk_nack        : 16;
+		mmr_t	reserved_1       : 4;
+		mmr_t	pio_nack_b       : 12;
+		mmr_t	reserved_0       : 4;
+		mmr_t	pio_nack_a       : 12;
+	} sh_lb_nack_status_s;
+} sh_lb_nack_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_TRIGGER_COMPARE"                   */
+/*                    LB Test-point Trigger Compare                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_trigger_compare_u {
+	mmr_t	sh_lb_trigger_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_lb_trigger_compare_s;
+} sh_lb_trigger_compare_u_t;
+#else
+typedef union sh_lb_trigger_compare_u {
+	mmr_t	sh_lb_trigger_compare_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_lb_trigger_compare_s;
+} sh_lb_trigger_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_TRIGGER_DATA"                     */
+/*                  LB Test-point Trigger Compare Data                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_trigger_data_u {
+	mmr_t	sh_lb_trigger_data_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_lb_trigger_data_s;
+} sh_lb_trigger_data_u_t;
+#else
+typedef union sh_lb_trigger_data_u {
+	mmr_t	sh_lb_trigger_data_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_lb_trigger_data_s;
+} sh_lb_trigger_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_CONFIG"                      */
+/*              PI Adaptive Error Correction Configuration              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_aec_config_u {
+	mmr_t	sh_pi_aec_config_regval;
+	struct {
+		mmr_t	mode        : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_aec_config_s;
+} sh_pi_aec_config_u_t;
+#else
+typedef union sh_pi_aec_config_u {
+	mmr_t	sh_pi_aec_config_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	mode        : 3;
+	} sh_pi_aec_config_s;
+} sh_pi_aec_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_ERROR_MASK"                    */
+/*                          PI AFI Error Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_error_mask_u {
+	mmr_t	sh_pi_afi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0   : 21;
+		mmr_t	hung_bus     : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	msg_len      : 1;
+		mmr_t	reserved_1   : 29;
+	} sh_pi_afi_error_mask_s;
+} sh_pi_afi_error_mask_u_t;
+#else
+typedef union sh_pi_afi_error_mask_u {
+	mmr_t	sh_pi_afi_error_mask_regval;
+	struct {
+		mmr_t	reserved_1   : 29;
+		mmr_t	msg_len      : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	hung_bus     : 1;
+		mmr_t	reserved_0   : 21;
+	} sh_pi_afi_error_mask_s;
+} sh_pi_afi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_AFI_TEST_POINT_COMPARE"                */
+/*                      PI AFI Test Point Compare                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_compare_u {
+	mmr_t	sh_pi_afi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_afi_test_point_compare_s;
+} sh_pi_afi_test_point_compare_u_t;
+#else
+typedef union sh_pi_afi_test_point_compare_u {
+	mmr_t	sh_pi_afi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_afi_test_point_compare_s;
+} sh_pi_afi_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_AFI_TEST_POINT_SELECT"                */
+/*                       PI AFI Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_select_u {
+	mmr_t	sh_pi_afi_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 4;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble1_chiplet_sel : 4;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble2_chiplet_sel : 4;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble3_chiplet_sel : 4;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble4_chiplet_sel : 4;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble5_chiplet_sel : 4;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble6_chiplet_sel : 4;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble7_chiplet_sel : 4;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_afi_test_point_select_s;
+} sh_pi_afi_test_point_select_u_t;
+#else
+typedef union sh_pi_afi_test_point_select_u {
+	mmr_t	sh_pi_afi_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble7_chiplet_sel : 4;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 4;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 4;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 4;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 4;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 4;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 4;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 4;
+	} sh_pi_afi_test_point_select_s;
+} sh_pi_afi_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_trigger_select_u {
+	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 4;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger1_chiplet_sel : 4;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger2_chiplet_sel : 4;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger3_chiplet_sel : 4;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger4_chiplet_sel : 4;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger5_chiplet_sel : 4;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger6_chiplet_sel : 4;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger7_chiplet_sel : 4;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+	} sh_pi_afi_test_point_trigger_select_s;
+} sh_pi_afi_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_afi_test_point_trigger_select_u {
+	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	trigger7_chiplet_sel : 4;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	trigger6_chiplet_sel : 4;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	trigger5_chiplet_sel : 4;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	trigger4_chiplet_sel : 4;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	trigger3_chiplet_sel : 4;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	trigger2_chiplet_sel : 4;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	trigger1_chiplet_sel : 4;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	trigger0_chiplet_sel : 4;
+	} sh_pi_afi_test_point_trigger_select_s;
+} sh_pi_afi_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_AUTO_REPLY_ENABLE"                  */
+/*                         PI Auto Reply Enable                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_auto_reply_enable_u {
+	mmr_t	sh_pi_auto_reply_enable_regval;
+	struct {
+		mmr_t	auto_reply_enable : 1;
+		mmr_t	reserved_0        : 63;
+	} sh_pi_auto_reply_enable_s;
+} sh_pi_auto_reply_enable_u_t;
+#else
+typedef union sh_pi_auto_reply_enable_u {
+	mmr_t	sh_pi_auto_reply_enable_regval;
+	struct {
+		mmr_t	reserved_0        : 63;
+		mmr_t	auto_reply_enable : 1;
+	} sh_pi_auto_reply_enable_s;
+} sh_pi_auto_reply_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_control_u {
+	mmr_t	sh_pi_cam_control_regval;
+	struct {
+		mmr_t	cam_indx          : 7;
+		mmr_t	reserved_0        : 1;
+		mmr_t	cam_write         : 1;
+		mmr_t	rrb_rd_xfer_clear : 1;
+		mmr_t	reserved_1        : 53;
+		mmr_t	start             : 1;
+	} sh_pi_cam_control_s;
+} sh_pi_cam_control_u_t;
+#else
+typedef union sh_pi_cam_control_u {
+	mmr_t	sh_pi_cam_control_regval;
+	struct {
+		mmr_t	start             : 1;
+		mmr_t	reserved_1        : 53;
+		mmr_t	rrb_rd_xfer_clear : 1;
+		mmr_t	cam_write         : 1;
+		mmr_t	reserved_0        : 1;
+		mmr_t	cam_indx          : 7;
+	} sh_pi_cam_control_s;
+} sh_pi_cam_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_COMPARE"               */
+/*                      PI CRBC Test Point Compare                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_compare_u {
+	mmr_t	sh_pi_crbc_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_crbc_test_point_compare_s;
+} sh_pi_crbc_test_point_compare_u_t;
+#else
+typedef union sh_pi_crbc_test_point_compare_u {
+	mmr_t	sh_pi_crbc_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_crbc_test_point_compare_s;
+} sh_pi_crbc_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_SELECT"                */
+/*                      PI CRBC Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_select_u {
+	mmr_t	sh_pi_crbc_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_crbc_test_point_select_s;
+} sh_pi_crbc_test_point_select_u_t;
+#else
+typedef union sh_pi_crbc_test_point_select_u {
+	mmr_t	sh_pi_crbc_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_crbc_test_point_select_s;
+} sh_pi_crbc_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_crbc_test_point_trigger_select_s;
+} sh_pi_crbc_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_crbc_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_crbc_test_point_trigger_select_s;
+} sh_pi_crbc_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_CRBP_ERROR_MASK"                   */
+/*                          PI CRBP Error Mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_error_mask_u {
+	mmr_t	sh_pi_crbp_error_mask_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	reserved_0      : 43;
+	} sh_pi_crbp_error_mask_s;
+} sh_pi_crbp_error_mask_u_t;
+#else
+typedef union sh_pi_crbp_error_mask_u {
+	mmr_t	sh_pi_crbp_error_mask_regval;
+	struct {
+		mmr_t	reserved_0      : 43;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_crbp_error_mask_s;
+} sh_pi_crbp_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_CRBP_FSB_PIPE_COMPARE"                */
+/*                        CRBP FSB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_fsb_pipe_compare_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
+	struct {
+		mmr_t	compare_address : 47;
+		mmr_t	compare_req     : 6;
+		mmr_t	reserved_0      : 11;
+	} sh_pi_crbp_fsb_pipe_compare_s;
+} sh_pi_crbp_fsb_pipe_compare_u_t;
+#else
+typedef union sh_pi_crbp_fsb_pipe_compare_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	compare_req     : 6;
+		mmr_t	compare_address : 47;
+	} sh_pi_crbp_fsb_pipe_compare_s;
+} sh_pi_crbp_fsb_pipe_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_FSB_PIPE_MASK"                  */
+/*                          CRBP Compare Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_fsb_pipe_mask_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
+	struct {
+		mmr_t	compare_address_mask : 47;
+		mmr_t	compare_req_mask     : 6;
+		mmr_t	reserved_0           : 11;
+	} sh_pi_crbp_fsb_pipe_mask_s;
+} sh_pi_crbp_fsb_pipe_mask_u_t;
+#else
+typedef union sh_pi_crbp_fsb_pipe_mask_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
+	struct {
+		mmr_t	reserved_0           : 11;
+		mmr_t	compare_req_mask     : 6;
+		mmr_t	compare_address_mask : 47;
+	} sh_pi_crbp_fsb_pipe_mask_s;
+} sh_pi_crbp_fsb_pipe_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_COMPARE"               */
+/*                      PI CRBP Test Point Compare                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_compare_u {
+	mmr_t	sh_pi_crbp_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_crbp_test_point_compare_s;
+} sh_pi_crbp_test_point_compare_u_t;
+#else
+typedef union sh_pi_crbp_test_point_compare_u {
+	mmr_t	sh_pi_crbp_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_crbp_test_point_compare_s;
+} sh_pi_crbp_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_SELECT"                */
+/*                      PI CRBP Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_select_u {
+	mmr_t	sh_pi_crbp_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_crbp_test_point_select_s;
+} sh_pi_crbp_test_point_select_u_t;
+#else
+typedef union sh_pi_crbp_test_point_select_u {
+	mmr_t	sh_pi_crbp_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_crbp_test_point_select_s;
+} sh_pi_crbp_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBP Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_crbp_test_point_trigger_select_s;
+} sh_pi_crbp_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_crbp_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_crbp_test_point_trigger_select_s;
+} sh_pi_crbp_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_0"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_compare_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
+	struct {
+		mmr_t	compare_address : 47;
+		mmr_t	compare_command : 8;
+		mmr_t	reserved_0      : 9;
+	} sh_pi_crbp_xb_pipe_compare_0_s;
+} sh_pi_crbp_xb_pipe_compare_0_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_compare_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
+	struct {
+		mmr_t	reserved_0      : 9;
+		mmr_t	compare_command : 8;
+		mmr_t	compare_address : 47;
+	} sh_pi_crbp_xb_pipe_compare_0_s;
+} sh_pi_crbp_xb_pipe_compare_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_1"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_compare_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
+	struct {
+		mmr_t	compare_source       : 14;
+		mmr_t	reserved_0           : 2;
+		mmr_t	compare_supplemental : 14;
+		mmr_t	reserved_1           : 2;
+		mmr_t	compare_echo         : 9;
+		mmr_t	reserved_2           : 23;
+	} sh_pi_crbp_xb_pipe_compare_1_s;
+} sh_pi_crbp_xb_pipe_compare_1_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_compare_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
+	struct {
+		mmr_t	reserved_2           : 23;
+		mmr_t	compare_echo         : 9;
+		mmr_t	reserved_1           : 2;
+		mmr_t	compare_supplemental : 14;
+		mmr_t	reserved_0           : 2;
+		mmr_t	compare_source       : 14;
+	} sh_pi_crbp_xb_pipe_compare_1_s;
+} sh_pi_crbp_xb_pipe_compare_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_0"                 */
+/*                     CRBP Compare Mask Register 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_mask_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
+	struct {
+		mmr_t	compare_address_mask : 47;
+		mmr_t	compare_command_mask : 8;
+		mmr_t	reserved_0           : 9;
+	} sh_pi_crbp_xb_pipe_mask_0_s;
+} sh_pi_crbp_xb_pipe_mask_0_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_mask_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
+	struct {
+		mmr_t	reserved_0           : 9;
+		mmr_t	compare_command_mask : 8;
+		mmr_t	compare_address_mask : 47;
+	} sh_pi_crbp_xb_pipe_mask_0_s;
+} sh_pi_crbp_xb_pipe_mask_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_1"                 */
+/*                 CRBP XB Pipe Compare Mask Register 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_mask_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
+	struct {
+		mmr_t	compare_source_mask       : 14;
+		mmr_t	reserved_0                : 2;
+		mmr_t	compare_supplemental_mask : 14;
+		mmr_t	reserved_1                : 2;
+		mmr_t	compare_echo_mask         : 9;
+		mmr_t	reserved_2                : 23;
+	} sh_pi_crbp_xb_pipe_mask_1_s;
+} sh_pi_crbp_xb_pipe_mask_1_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_mask_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
+	struct {
+		mmr_t	reserved_2                : 23;
+		mmr_t	compare_echo_mask         : 9;
+		mmr_t	reserved_1                : 2;
+		mmr_t	compare_supplemental_mask : 14;
+		mmr_t	reserved_0                : 2;
+		mmr_t	compare_source_mask       : 14;
+	} sh_pi_crbp_xb_pipe_mask_1_s;
+} sh_pi_crbp_xb_pipe_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_DPC_QUEUE_CONFIG"                   */
+/*                       DPC Queue Configuration                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_dpc_queue_config_u {
+	mmr_t	sh_pi_dpc_queue_config_regval;
+	struct {
+		mmr_t	dwcq_ae_level  : 5;
+		mmr_t	reserved_0     : 3;
+		mmr_t	dwcq_af_thresh : 5;
+		mmr_t	reserved_1     : 3;
+		mmr_t	fwcq_ae_level  : 5;
+		mmr_t	reserved_2     : 3;
+		mmr_t	fwcq_af_thresh : 5;
+		mmr_t	reserved_3     : 35;
+	} sh_pi_dpc_queue_config_s;
+} sh_pi_dpc_queue_config_u_t;
+#else
+typedef union sh_pi_dpc_queue_config_u {
+	mmr_t	sh_pi_dpc_queue_config_regval;
+	struct {
+		mmr_t	reserved_3     : 35;
+		mmr_t	fwcq_af_thresh : 5;
+		mmr_t	reserved_2     : 3;
+		mmr_t	fwcq_ae_level  : 5;
+		mmr_t	reserved_1     : 3;
+		mmr_t	dwcq_af_thresh : 5;
+		mmr_t	reserved_0     : 3;
+		mmr_t	dwcq_ae_level  : 5;
+	} sh_pi_dpc_queue_config_s;
+} sh_pi_dpc_queue_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_ERROR_MASK"                      */
+/*                            PI Error Mask                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_mask_u {
+	mmr_t	sh_pi_error_mask_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_mask_s;
+} sh_pi_error_mask_u_t;
+#else
+typedef union sh_pi_error_mask_u {
+	mmr_t	sh_pi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_mask_s;
+} sh_pi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_CONFIG"                 */
+/*                    PI Express Reply Configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_express_reply_config_u {
+	mmr_t	sh_pi_express_reply_config_regval;
+	struct {
+		mmr_t	mode        : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_express_reply_config_s;
+} sh_pi_express_reply_config_u_t;
+#else
+typedef union sh_pi_express_reply_config_u {
+	mmr_t	sh_pi_express_reply_config_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	mode        : 3;
+	} sh_pi_express_reply_config_s;
+} sh_pi_express_reply_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_VALUE"                  */
+/*                          FSB Compare Value                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_compare_value_u {
+	mmr_t	sh_pi_fsb_compare_value_regval;
+	struct {
+		mmr_t	compare_value : 64;
+	} sh_pi_fsb_compare_value_s;
+} sh_pi_fsb_compare_value_u_t;
+#else
+typedef union sh_pi_fsb_compare_value_u {
+	mmr_t	sh_pi_fsb_compare_value_regval;
+	struct {
+		mmr_t	compare_value : 64;
+	} sh_pi_fsb_compare_value_s;
+} sh_pi_fsb_compare_value_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_MASK"                   */
+/*                           FSB Compare Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_compare_mask_u {
+	mmr_t	sh_pi_fsb_compare_mask_regval;
+	struct {
+		mmr_t	mask_value  : 64;
+	} sh_pi_fsb_compare_mask_s;
+} sh_pi_fsb_compare_mask_u_t;
+#else
+typedef union sh_pi_fsb_compare_mask_u {
+	mmr_t	sh_pi_fsb_compare_mask_regval;
+	struct {
+		mmr_t	mask_value  : 64;
+	} sh_pi_fsb_compare_mask_s;
+} sh_pi_fsb_compare_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_FSB_ERROR_INJECTION"                 */
+/*                     Inject an Error onto the FSB                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_error_injection_u {
+	mmr_t	sh_pi_fsb_error_injection_regval;
+	struct {
+		mmr_t	rp_pe_to_fsb     : 1;
+		mmr_t	ap0_pe_to_fsb    : 1;
+		mmr_t	ap1_pe_to_fsb    : 1;
+		mmr_t	rsp_pe_to_fsb    : 1;
+		mmr_t	dw0_ce_to_fsb    : 1;
+		mmr_t	dw0_uce_to_fsb   : 1;
+		mmr_t	dw1_ce_to_fsb    : 1;
+		mmr_t	dw1_uce_to_fsb   : 1;
+		mmr_t	ip0_pe_to_fsb    : 1;
+		mmr_t	ip1_pe_to_fsb    : 1;
+		mmr_t	reserved_0       : 6;
+		mmr_t	rp_pe_from_fsb   : 1;
+		mmr_t	ap0_pe_from_fsb  : 1;
+		mmr_t	ap1_pe_from_fsb  : 1;
+		mmr_t	rsp_pe_from_fsb  : 1;
+		mmr_t	dw0_ce_from_fsb  : 1;
+		mmr_t	dw0_uce_from_fsb : 1;
+		mmr_t	dw1_ce_from_fsb  : 1;
+		mmr_t	dw1_uce_from_fsb : 1;
+		mmr_t	dw2_ce_from_fsb  : 1;
+		mmr_t	dw2_uce_from_fsb : 1;
+		mmr_t	dw3_ce_from_fsb  : 1;
+		mmr_t	dw3_uce_from_fsb : 1;
+		mmr_t	reserved_1       : 4;
+		mmr_t	ioq_overrun      : 1;
+		mmr_t	livelock         : 1;
+		mmr_t	bus_hang         : 1;
+		mmr_t	reserved_2       : 29;
+	} sh_pi_fsb_error_injection_s;
+} sh_pi_fsb_error_injection_u_t;
+#else
+typedef union sh_pi_fsb_error_injection_u {
+	mmr_t	sh_pi_fsb_error_injection_regval;
+	struct {
+		mmr_t	reserved_2       : 29;
+		mmr_t	bus_hang         : 1;
+		mmr_t	livelock         : 1;
+		mmr_t	ioq_overrun      : 1;
+		mmr_t	reserved_1       : 4;
+		mmr_t	dw3_uce_from_fsb : 1;
+		mmr_t	dw3_ce_from_fsb  : 1;
+		mmr_t	dw2_uce_from_fsb : 1;
+		mmr_t	dw2_ce_from_fsb  : 1;
+		mmr_t	dw1_uce_from_fsb : 1;
+		mmr_t	dw1_ce_from_fsb  : 1;
+		mmr_t	dw0_uce_from_fsb : 1;
+		mmr_t	dw0_ce_from_fsb  : 1;
+		mmr_t	rsp_pe_from_fsb  : 1;
+		mmr_t	ap1_pe_from_fsb  : 1;
+		mmr_t	ap0_pe_from_fsb  : 1;
+		mmr_t	rp_pe_from_fsb   : 1;
+		mmr_t	reserved_0       : 6;
+		mmr_t	ip1_pe_to_fsb    : 1;
+		mmr_t	ip0_pe_to_fsb    : 1;
+		mmr_t	dw1_uce_to_fsb   : 1;
+		mmr_t	dw1_ce_to_fsb    : 1;
+		mmr_t	dw0_uce_to_fsb   : 1;
+		mmr_t	dw0_ce_to_fsb    : 1;
+		mmr_t	rsp_pe_to_fsb    : 1;
+		mmr_t	ap1_pe_to_fsb    : 1;
+		mmr_t	ap0_pe_to_fsb    : 1;
+		mmr_t	rp_pe_to_fsb     : 1;
+	} sh_pi_fsb_error_injection_s;
+} sh_pi_fsb_error_injection_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_CONFIG"                */
+/*             MD-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_reply_vc_config_u {
+	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_md2pi_reply_vc_config_s;
+} sh_pi_md2pi_reply_vc_config_u_t;
+#else
+typedef union sh_pi_md2pi_reply_vc_config_u {
+	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_md2pi_reply_vc_config_s;
+} sh_pi_md2pi_reply_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_CONFIG"               */
+/*            MD-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_request_vc_config_u {
+	mmr_t	sh_pi_md2pi_request_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_md2pi_request_vc_config_s;
+} sh_pi_md2pi_request_vc_config_u_t;
+#else
+typedef union sh_pi_md2pi_request_vc_config_u {
+	mmr_t	sh_pi_md2pi_request_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_md2pi_request_vc_config_s;
+} sh_pi_md2pi_request_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_QUEUE_ERROR_INJECTION"                */
+/*                       PI Queue Error Injection                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_queue_error_injection_u {
+	mmr_t	sh_pi_queue_error_injection_regval;
+	struct {
+		mmr_t	dat_dfr_q      : 1;
+		mmr_t	dxb_wtl_cmnd_q : 1;
+		mmr_t	fsb_wtl_cmnd_q : 1;
+		mmr_t	mdpi_rpy_bfr   : 1;
+		mmr_t	ptc_intr       : 1;
+		mmr_t	rxl_kill_q     : 1;
+		mmr_t	rxl_rdy_q      : 1;
+		mmr_t	xnpi_rpy_bfr   : 1;
+		mmr_t	reserved_0     : 56;
+	} sh_pi_queue_error_injection_s;
+} sh_pi_queue_error_injection_u_t;
+#else
+typedef union sh_pi_queue_error_injection_u {
+	mmr_t	sh_pi_queue_error_injection_regval;
+	struct {
+		mmr_t	reserved_0     : 56;
+		mmr_t	xnpi_rpy_bfr   : 1;
+		mmr_t	rxl_rdy_q      : 1;
+		mmr_t	rxl_kill_q     : 1;
+		mmr_t	ptc_intr       : 1;
+		mmr_t	mdpi_rpy_bfr   : 1;
+		mmr_t	fsb_wtl_cmnd_q : 1;
+		mmr_t	dxb_wtl_cmnd_q : 1;
+		mmr_t	dat_dfr_q      : 1;
+	} sh_pi_queue_error_injection_s;
+} sh_pi_queue_error_injection_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_TEST_POINT_COMPARE"                  */
+/*                        PI Test Point Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_compare_u {
+	mmr_t	sh_pi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_test_point_compare_s;
+} sh_pi_test_point_compare_u_t;
+#else
+typedef union sh_pi_test_point_compare_u {
+	mmr_t	sh_pi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_test_point_compare_s;
+} sh_pi_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_TEST_POINT_SELECT"                  */
+/*                         PI Test Point Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_select_u {
+	mmr_t	sh_pi_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_test_point_select_s;
+} sh_pi_test_point_select_u_t;
+#else
+typedef union sh_pi_test_point_select_u {
+	mmr_t	sh_pi_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_test_point_select_s;
+} sh_pi_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_PI_TEST_POINT_TRIGGER_SELECT"              */
+/*                     PI Test Point Trigger Select                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_trigger_select_u {
+	mmr_t	sh_pi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_test_point_trigger_select_s;
+} sh_pi_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_test_point_trigger_select_u {
+	mmr_t	sh_pi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_test_point_trigger_select_s;
+} sh_pi_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_CONFIG"                */
+/*             XN-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_reply_vc_config_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_xn2pi_reply_vc_config_s;
+} sh_pi_xn2pi_reply_vc_config_u_t;
+#else
+typedef union sh_pi_xn2pi_reply_vc_config_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_xn2pi_reply_vc_config_s;
+} sh_pi_xn2pi_reply_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_CONFIG"               */
+/*            XN-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_request_vc_config_u {
+	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_xn2pi_request_vc_config_s;
+} sh_pi_xn2pi_request_vc_config_u_t;
+#else
+typedef union sh_pi_xn2pi_request_vc_config_u {
+	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_xn2pi_request_vc_config_s;
+} sh_pi_xn2pi_request_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_STATUS"                      */
+/*                 PI Adaptive Error Correction Status                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_aec_status_u {
+	mmr_t	sh_pi_aec_status_regval;
+	struct {
+		mmr_t	state       : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_aec_status_s;
+} sh_pi_aec_status_u_t;
+#else
+typedef union sh_pi_aec_status_u {
+	mmr_t	sh_pi_aec_status_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	state       : 3;
+	} sh_pi_aec_status_s;
+} sh_pi_aec_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_FIRST_ERROR"                   */
+/*                          PI AFI First Error                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_first_error_u {
+	mmr_t	sh_pi_afi_first_error_regval;
+	struct {
+		mmr_t	reserved_0   : 7;
+		mmr_t	fsb_shub_uce : 1;
+		mmr_t	fsb_shub_ce  : 1;
+		mmr_t	reserved_1   : 12;
+		mmr_t	hung_bus     : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	msg_len      : 1;
+		mmr_t	reserved_2   : 29;
+	} sh_pi_afi_first_error_s;
+} sh_pi_afi_first_error_u_t;
+#else
+typedef union sh_pi_afi_first_error_u {
+	mmr_t	sh_pi_afi_first_error_regval;
+	struct {
+		mmr_t	reserved_2   : 29;
+		mmr_t	msg_len      : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	hung_bus     : 1;
+		mmr_t	reserved_1   : 12;
+		mmr_t	fsb_shub_ce  : 1;
+		mmr_t	fsb_shub_uce : 1;
+		mmr_t	reserved_0   : 7;
+	} sh_pi_afi_first_error_s;
+} sh_pi_afi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_CAM_ADDRESS_READ_DATA"                */
+/*                    CRB CAM MMR Address Read Data                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_address_read_data_u {
+	mmr_t	sh_pi_cam_address_read_data_regval;
+	struct {
+		mmr_t	cam_addr     : 48;
+		mmr_t	reserved_0   : 15;
+		mmr_t	cam_addr_val : 1;
+	} sh_pi_cam_address_read_data_s;
+} sh_pi_cam_address_read_data_u_t;
+#else
+typedef union sh_pi_cam_address_read_data_u {
+	mmr_t	sh_pi_cam_address_read_data_regval;
+	struct {
+		mmr_t	cam_addr_val : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	cam_addr     : 48;
+	} sh_pi_cam_address_read_data_s;
+} sh_pi_cam_address_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_LPRA_READ_DATA"                  */
+/*                      CRB CAM MMR LPRA Read Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_lpra_read_data_u {
+	mmr_t	sh_pi_cam_lpra_read_data_regval;
+	struct {
+		mmr_t	cam_lpra    : 64;
+	} sh_pi_cam_lpra_read_data_s;
+} sh_pi_cam_lpra_read_data_u_t;
+#else
+typedef union sh_pi_cam_lpra_read_data_u {
+	mmr_t	sh_pi_cam_lpra_read_data_regval;
+	struct {
+		mmr_t	cam_lpra    : 64;
+	} sh_pi_cam_lpra_read_data_s;
+} sh_pi_cam_lpra_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_STATE_READ_DATA"                 */
+/*                     CRB CAM MMR State Read Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_state_read_data_u {
+	mmr_t	sh_pi_cam_state_read_data_regval;
+	struct {
+		mmr_t	cam_state         : 4;
+		mmr_t	cam_to            : 1;
+		mmr_t	cam_state_rd_pend : 1;
+		mmr_t	reserved_0        : 26;
+		mmr_t	cam_lpra          : 18;
+		mmr_t	reserved_1        : 13;
+		mmr_t	cam_rd_data_val   : 1;
+	} sh_pi_cam_state_read_data_s;
+} sh_pi_cam_state_read_data_u_t;
+#else
+typedef union sh_pi_cam_state_read_data_u {
+	mmr_t	sh_pi_cam_state_read_data_regval;
+	struct {
+		mmr_t	cam_rd_data_val   : 1;
+		mmr_t	reserved_1        : 13;
+		mmr_t	cam_lpra          : 18;
+		mmr_t	reserved_0        : 26;
+		mmr_t	cam_state_rd_pend : 1;
+		mmr_t	cam_to            : 1;
+		mmr_t	cam_state         : 4;
+	} sh_pi_cam_state_read_data_s;
+} sh_pi_cam_state_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_1"                  */
+/*                      PI Corrected Error Detail                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_1_u {
+	mmr_t	sh_pi_corrected_detail_1_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_corrected_detail_1_s;
+} sh_pi_corrected_detail_1_u_t;
+#else
+typedef union sh_pi_corrected_detail_1_u {
+	mmr_t	sh_pi_corrected_detail_1_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_corrected_detail_1_s;
+} sh_pi_corrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_2"                  */
+/*                     PI Corrected Error Detail 2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_2_u {
+	mmr_t	sh_pi_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_2_s;
+} sh_pi_corrected_detail_2_u_t;
+#else
+typedef union sh_pi_corrected_detail_2_u {
+	mmr_t	sh_pi_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_2_s;
+} sh_pi_corrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_3"                  */
+/*                     PI Corrected Error Detail 3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_3_u {
+	mmr_t	sh_pi_corrected_detail_3_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_corrected_detail_3_s;
+} sh_pi_corrected_detail_3_u_t;
+#else
+typedef union sh_pi_corrected_detail_3_u {
+	mmr_t	sh_pi_corrected_detail_3_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_corrected_detail_3_s;
+} sh_pi_corrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_4"                  */
+/*                     PI Corrected Error Detail 4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_4_u {
+	mmr_t	sh_pi_corrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_4_s;
+} sh_pi_corrected_detail_4_u_t;
+#else
+typedef union sh_pi_corrected_detail_4_u {
+	mmr_t	sh_pi_corrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_4_s;
+} sh_pi_corrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_CRBP_FIRST_ERROR"                   */
+/*                         PI CRBP First Error                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_first_error_u {
+	mmr_t	sh_pi_crbp_first_error_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	reserved_0      : 43;
+	} sh_pi_crbp_first_error_s;
+} sh_pi_crbp_first_error_u_t;
+#else
+typedef union sh_pi_crbp_first_error_u {
+	mmr_t	sh_pi_crbp_first_error_regval;
+	struct {
+		mmr_t	reserved_0      : 43;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_crbp_first_error_s;
+} sh_pi_crbp_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_1"                    */
+/*                          PI Error Detail 1                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_detail_1_u {
+	mmr_t	sh_pi_error_detail_1_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_1_s;
+} sh_pi_error_detail_1_u_t;
+#else
+typedef union sh_pi_error_detail_1_u {
+	mmr_t	sh_pi_error_detail_1_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_1_s;
+} sh_pi_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_2"                    */
+/*                          PI Error Detail 2                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_detail_2_u {
+	mmr_t	sh_pi_error_detail_2_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_2_s;
+} sh_pi_error_detail_2_u_t;
+#else
+typedef union sh_pi_error_detail_2_u {
+	mmr_t	sh_pi_error_detail_2_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_2_s;
+} sh_pi_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_OVERFLOW"                    */
+/*                          PI Error Overflow                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_overflow_u {
+	mmr_t	sh_pi_error_overflow_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_overflow_s;
+} sh_pi_error_overflow_u_t;
+#else
+typedef union sh_pi_error_overflow_u {
+	mmr_t	sh_pi_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_overflow_s;
+} sh_pi_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_ERROR_SUMMARY"                    */
+/*                           PI Error Summary                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_summary_u {
+	mmr_t	sh_pi_error_summary_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_summary_s;
+} sh_pi_error_summary_u_t;
+#else
+typedef union sh_pi_error_summary_u {
+	mmr_t	sh_pi_error_summary_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_summary_s;
+} sh_pi_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_STATUS"                 */
+/*                       PI Express Reply Status                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_express_reply_status_u {
+	mmr_t	sh_pi_express_reply_status_regval;
+	struct {
+		mmr_t	state       : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_express_reply_status_s;
+} sh_pi_express_reply_status_u_t;
+#else
+typedef union sh_pi_express_reply_status_u {
+	mmr_t	sh_pi_express_reply_status_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	state       : 3;
+	} sh_pi_express_reply_status_s;
+} sh_pi_express_reply_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_FIRST_ERROR"                     */
+/*                            PI First Error                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_first_error_u {
+	mmr_t	sh_pi_first_error_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_first_error_s;
+} sh_pi_first_error_u_t;
+#else
+typedef union sh_pi_first_error_u {
+	mmr_t	sh_pi_first_error_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_first_error_s;
+} sh_pi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2MD_REPLY_VC_STATUS"                */
+/*                PI-to-MD Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2md_reply_vc_status_u {
+	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2md_reply_vc_status_s;
+} sh_pi_pi2md_reply_vc_status_u_t;
+#else
+typedef union sh_pi_pi2md_reply_vc_status_u {
+	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2md_reply_vc_status_s;
+} sh_pi_pi2md_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2MD_REQUEST_VC_STATUS"               */
+/*               PI-to-MD Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2md_request_vc_status_u {
+	mmr_t	sh_pi_pi2md_request_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2md_request_vc_status_s;
+} sh_pi_pi2md_request_vc_status_u_t;
+#else
+typedef union sh_pi_pi2md_request_vc_status_u {
+	mmr_t	sh_pi_pi2md_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2md_request_vc_status_s;
+} sh_pi_pi2md_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2XN_REPLY_VC_STATUS"                */
+/*                PI-to-XN Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2xn_reply_vc_status_u {
+	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2xn_reply_vc_status_s;
+} sh_pi_pi2xn_reply_vc_status_u_t;
+#else
+typedef union sh_pi_pi2xn_reply_vc_status_u {
+	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2xn_reply_vc_status_s;
+} sh_pi_pi2xn_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2XN_REQUEST_VC_STATUS"               */
+/*               PI-to-XN Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2xn_request_vc_status_u {
+	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2xn_request_vc_status_s;
+} sh_pi_pi2xn_request_vc_status_u_t;
+#else
+typedef union sh_pi_pi2xn_request_vc_status_u {
+	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2xn_request_vc_status_s;
+} sh_pi_pi2xn_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_1"                 */
+/*                    PI Uncorrected Error Detail 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_1_u {
+	mmr_t	sh_pi_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_uncorrected_detail_1_s;
+} sh_pi_uncorrected_detail_1_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_1_u {
+	mmr_t	sh_pi_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_uncorrected_detail_1_s;
+} sh_pi_uncorrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_2"                 */
+/*                    PI Uncorrected Error Detail 2                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_2_u {
+	mmr_t	sh_pi_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_2_s;
+} sh_pi_uncorrected_detail_2_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_2_u {
+	mmr_t	sh_pi_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_2_s;
+} sh_pi_uncorrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_3"                 */
+/*                    PI Uncorrected Error Detail 3                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_3_u {
+	mmr_t	sh_pi_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_uncorrected_detail_3_s;
+} sh_pi_uncorrected_detail_3_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_3_u {
+	mmr_t	sh_pi_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_uncorrected_detail_3_s;
+} sh_pi_uncorrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_4"                 */
+/*                    PI Uncorrected Error Detail 4                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_4_u {
+	mmr_t	sh_pi_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_4_s;
+} sh_pi_uncorrected_detail_4_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_4_u {
+	mmr_t	sh_pi_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_4_s;
+} sh_pi_uncorrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_STATUS"                */
+/*                MD-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_reply_vc_status_u {
+	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_md2pi_reply_vc_status_s;
+} sh_pi_md2pi_reply_vc_status_u_t;
+#else
+typedef union sh_pi_md2pi_reply_vc_status_u {
+	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_md2pi_reply_vc_status_s;
+} sh_pi_md2pi_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_STATUS"               */
+/*               MD-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_request_vc_status_u {
+	mmr_t	sh_pi_md2pi_request_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_md2pi_request_vc_status_s;
+} sh_pi_md2pi_request_vc_status_u_t;
+#else
+typedef union sh_pi_md2pi_request_vc_status_u {
+	mmr_t	sh_pi_md2pi_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_md2pi_request_vc_status_s;
+} sh_pi_md2pi_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_STATUS"                */
+/*                XN-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_reply_vc_status_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_xn2pi_reply_vc_status_s;
+} sh_pi_xn2pi_reply_vc_status_u_t;
+#else
+typedef union sh_pi_xn2pi_reply_vc_status_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_xn2pi_reply_vc_status_s;
+} sh_pi_xn2pi_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_STATUS"               */
+/*               XN-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_request_vc_status_u {
+	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_xn2pi_request_vc_status_s;
+} sh_pi_xn2pi_request_vc_status_u_t;
+#else
+typedef union sh_pi_xn2pi_request_vc_status_u {
+	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_xn2pi_request_vc_status_s;
+} sh_pi_xn2pi_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNPI_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_sic_flow_u {
+	mmr_t	sh_xnpi_sic_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 5;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_7           : 2;
+		mmr_t	disable_bypass_out   : 1;
+	} sh_xnpi_sic_flow_s;
+} sh_xnpi_sic_flow_u_t;
+#else
+typedef union sh_xnpi_sic_flow_u {
+	mmr_t	sh_xnpi_sic_flow_regval;
+	struct {
+		mmr_t	disable_bypass_out   : 1;
+		mmr_t	reserved_7           : 2;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_withhold   : 5;
+	} sh_xnpi_sic_flow_s;
+} sh_xnpi_sic_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_ni0_port_flow_u {
+	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_ni0_port_flow_s;
+} sh_xnpi_to_ni0_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_ni0_port_flow_u {
+	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_ni0_port_flow_s;
+} sh_xnpi_to_ni0_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_ni1_port_flow_u {
+	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_ni1_port_flow_s;
+} sh_xnpi_to_ni1_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_ni1_port_flow_u {
+	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_ni1_port_flow_s;
+} sh_xnpi_to_ni1_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_iilb_port_flow_u {
+	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_iilb_port_flow_s;
+} sh_xnpi_to_iilb_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_iilb_port_flow_u {
+	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_iilb_port_flow_s;
+} sh_xnpi_to_iilb_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_ni0_port_flow_fifo_s;
+} sh_xnpi_fr_ni0_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_ni0_port_flow_fifo_s;
+} sh_xnpi_fr_ni0_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_ni1_port_flow_fifo_s;
+} sh_xnpi_fr_ni1_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_ni1_port_flow_fifo_s;
+} sh_xnpi_fr_ni1_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_iilb_port_flow_fifo_s;
+} sh_xnpi_fr_iilb_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_iilb_port_flow_fifo_s;
+} sh_xnpi_fr_iilb_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNMD_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_sic_flow_u {
+	mmr_t	sh_xnmd_sic_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 5;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_7           : 2;
+		mmr_t	disable_bypass_out   : 1;
+	} sh_xnmd_sic_flow_s;
+} sh_xnmd_sic_flow_u_t;
+#else
+typedef union sh_xnmd_sic_flow_u {
+	mmr_t	sh_xnmd_sic_flow_regval;
+	struct {
+		mmr_t	disable_bypass_out   : 1;
+		mmr_t	reserved_7           : 2;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_withhold   : 5;
+	} sh_xnmd_sic_flow_s;
+} sh_xnmd_sic_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_ni0_port_flow_u {
+	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_ni0_port_flow_s;
+} sh_xnmd_to_ni0_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_ni0_port_flow_u {
+	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_ni0_port_flow_s;
+} sh_xnmd_to_ni0_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_ni1_port_flow_u {
+	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_ni1_port_flow_s;
+} sh_xnmd_to_ni1_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_ni1_port_flow_u {
+	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_ni1_port_flow_s;
+} sh_xnmd_to_ni1_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_iilb_port_flow_u {
+	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_iilb_port_flow_s;
+} sh_xnmd_to_iilb_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_iilb_port_flow_u {
+	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_iilb_port_flow_s;
+} sh_xnmd_to_iilb_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_ni0_port_flow_fifo_s;
+} sh_xnmd_fr_ni0_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_ni0_port_flow_fifo_s;
+} sh_xnmd_fr_ni0_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_ni1_port_flow_fifo_s;
+} sh_xnmd_fr_ni1_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_ni1_port_flow_fifo_s;
+} sh_xnmd_fr_ni1_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_iilb_port_flow_fifo_s;
+} sh_xnmd_fr_iilb_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_iilb_port_flow_fifo_s;
+} sh_xnmd_fr_iilb_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNII_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnii_intra_flow_u {
+	mmr_t	sh_xnii_intra_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_7           : 1;
+	} sh_xnii_intra_flow_s;
+} sh_xnii_intra_flow_u_t;
+#else
+typedef union sh_xnii_intra_flow_u {
+	mmr_t	sh_xnii_intra_flow_regval;
+	struct {
+		mmr_t	reserved_7           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnii_intra_flow_s;
+} sh_xnii_intra_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNLB_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnlb_intra_flow_u {
+	mmr_t	sh_xnlb_intra_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	disable_bypass_in    : 1;
+	} sh_xnlb_intra_flow_s;
+} sh_xnlb_intra_flow_u_t;
+#else
+typedef union sh_xnlb_intra_flow_u {
+	mmr_t	sh_xnlb_intra_flow_regval;
+	struct {
+		mmr_t	disable_bypass_in    : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnlb_intra_flow_s;
+} sh_xnlb_intra_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_ni0_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_ni0_intra_flow_debit_s;
+} sh_xniilb_to_ni0_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_ni0_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_ni0_intra_flow_debit_s;
+} sh_xniilb_to_ni0_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_ni1_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_ni1_intra_flow_debit_s;
+} sh_xniilb_to_ni1_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_ni1_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_ni1_intra_flow_debit_s;
+} sh_xniilb_to_ni1_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_md_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_md_intra_flow_debit_s;
+} sh_xniilb_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_md_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_md_intra_flow_debit_s;
+} sh_xniilb_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_iilb_intra_flow_debit_s;
+} sh_xniilb_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_iilb_intra_flow_debit_s;
+} sh_xniilb_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_pi_intra_flow_debit_s;
+} sh_xniilb_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_pi_intra_flow_debit_s;
+} sh_xniilb_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_ni0_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_ni0_intra_flow_credit_s;
+} sh_xniilb_fr_ni0_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_ni0_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_ni0_intra_flow_credit_s;
+} sh_xniilb_fr_ni0_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_ni1_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_ni1_intra_flow_credit_s;
+} sh_xniilb_fr_ni1_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_ni1_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_ni1_intra_flow_credit_s;
+} sh_xniilb_fr_ni1_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_md_intra_flow_credit_s;
+} sh_xniilb_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_md_intra_flow_credit_s;
+} sh_xniilb_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT"            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_iilb_intra_flow_credit_s;
+} sh_xniilb_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_iilb_intra_flow_credit_s;
+} sh_xniilb_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_pi_intra_flow_credit_s;
+} sh_xniilb_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_pi_intra_flow_credit_s;
+} sh_xniilb_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_pi_intra_flow_debit_s;
+} sh_xnni0_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_pi_intra_flow_debit_s;
+} sh_xnni0_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_md_intra_flow_debit_s;
+} sh_xnni0_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_md_intra_flow_debit_s;
+} sh_xnni0_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_iilb_intra_flow_debit_s;
+} sh_xnni0_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_iilb_intra_flow_debit_s;
+} sh_xnni0_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_pi_intra_flow_credit_s;
+} sh_xnni0_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_pi_intra_flow_credit_s;
+} sh_xnni0_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_md_intra_flow_credit_s;
+} sh_xnni0_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_md_intra_flow_credit_s;
+} sh_xnni0_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_iilb_intra_flow_credit_s;
+} sh_xnni0_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_iilb_intra_flow_credit_s;
+} sh_xnni0_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_0_intrani_flow_u {
+	mmr_t	sh_xnni0_0_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_0_intrani_flow_s;
+} sh_xnni0_0_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_0_intrani_flow_u {
+	mmr_t	sh_xnni0_0_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_0_intrani_flow_s;
+} sh_xnni0_0_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_1_intrani_flow_u {
+	mmr_t	sh_xnni0_1_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_1_intrani_flow_s;
+} sh_xnni0_1_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_1_intrani_flow_u {
+	mmr_t	sh_xnni0_1_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni0_1_intrani_flow_s;
+} sh_xnni0_1_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_2_intrani_flow_u {
+	mmr_t	sh_xnni0_2_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_2_intrani_flow_s;
+} sh_xnni0_2_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_2_intrani_flow_u {
+	mmr_t	sh_xnni0_2_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni0_2_intrani_flow_s;
+} sh_xnni0_2_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_3_intrani_flow_u {
+	mmr_t	sh_xnni0_3_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_3_intrani_flow_s;
+} sh_xnni0_3_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_3_intrani_flow_u {
+	mmr_t	sh_xnni0_3_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni0_3_intrani_flow_s;
+} sh_xnni0_3_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_vcswitch_flow_u {
+	mmr_t	sh_xnni0_vcswitch_flow_regval;
+	struct {
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	reserved_4                : 29;
+	} sh_xnni0_vcswitch_flow_s;
+} sh_xnni0_vcswitch_flow_u_t;
+#else
+typedef union sh_xnni0_vcswitch_flow_u {
+	mmr_t	sh_xnni0_vcswitch_flow_regval;
+	struct {
+		mmr_t	reserved_4                : 29;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+	} sh_xnni0_vcswitch_flow_s;
+} sh_xnni0_vcswitch_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_TIMER_REG"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_timer_reg_u {
+	mmr_t	sh_xnni0_timer_reg_regval;
+	struct {
+		mmr_t	timeout_reg     : 24;
+		mmr_t	reserved_0      : 8;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_1      : 31;
+	} sh_xnni0_timer_reg_s;
+} sh_xnni0_timer_reg_u_t;
+#else
+typedef union sh_xnni0_timer_reg_u {
+	mmr_t	sh_xnni0_timer_reg_regval;
+	struct {
+		mmr_t	reserved_1      : 31;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_0      : 8;
+		mmr_t	timeout_reg     : 24;
+	} sh_xnni0_timer_reg_s;
+} sh_xnni0_timer_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fifo02_flow_u {
+	mmr_t	sh_xnni0_fifo02_flow_regval;
+	struct {
+		mmr_t	count_vc0_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni0_fifo02_flow_s;
+} sh_xnni0_fifo02_flow_u_t;
+#else
+typedef union sh_xnni0_fifo02_flow_u {
+	mmr_t	sh_xnni0_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_limit : 4;
+	} sh_xnni0_fifo02_flow_s;
+} sh_xnni0_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fifo13_flow_u {
+	mmr_t	sh_xnni0_fifo13_flow_regval;
+	struct {
+		mmr_t	count_vc1_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni0_fifo13_flow_s;
+} sh_xnni0_fifo13_flow_u_t;
+#else
+typedef union sh_xnni0_fifo13_flow_u {
+	mmr_t	sh_xnni0_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_limit : 4;
+	} sh_xnni0_fifo13_flow_s;
+} sh_xnni0_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI0_NI_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_ni_flow_u {
+	mmr_t	sh_xnni0_ni_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni0_ni_flow_s;
+} sh_xnni0_ni_flow_u_t;
+#else
+typedef union sh_xnni0_ni_flow_u {
+	mmr_t	sh_xnni0_ni_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni0_ni_flow_s;
+} sh_xnni0_ni_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_dead_flow_u {
+	mmr_t	sh_xnni0_dead_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni0_dead_flow_s;
+} sh_xnni0_dead_flow_u_t;
+#else
+typedef union sh_xnni0_dead_flow_u {
+	mmr_t	sh_xnni0_dead_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni0_dead_flow_s;
+} sh_xnni0_dead_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_inject_age_u {
+	mmr_t	sh_xnni0_inject_age_regval;
+	struct {
+		mmr_t	request_inject : 8;
+		mmr_t	reply_inject   : 8;
+		mmr_t	reserved_0     : 48;
+	} sh_xnni0_inject_age_s;
+} sh_xnni0_inject_age_u_t;
+#else
+typedef union sh_xnni0_inject_age_u {
+	mmr_t	sh_xnni0_inject_age_regval;
+	struct {
+		mmr_t	reserved_0     : 48;
+		mmr_t	reply_inject   : 8;
+		mmr_t	request_inject : 8;
+	} sh_xnni0_inject_age_s;
+} sh_xnni0_inject_age_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_pi_intra_flow_debit_s;
+} sh_xnni1_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_pi_intra_flow_debit_s;
+} sh_xnni1_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_md_intra_flow_debit_s;
+} sh_xnni1_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_md_intra_flow_debit_s;
+} sh_xnni1_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_iilb_intra_flow_debit_s;
+} sh_xnni1_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_iilb_intra_flow_debit_s;
+} sh_xnni1_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_pi_intra_flow_credit_s;
+} sh_xnni1_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_pi_intra_flow_credit_s;
+} sh_xnni1_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_md_intra_flow_credit_s;
+} sh_xnni1_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_md_intra_flow_credit_s;
+} sh_xnni1_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_iilb_intra_flow_credit_s;
+} sh_xnni1_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_iilb_intra_flow_credit_s;
+} sh_xnni1_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_0_intrani_flow_u {
+	mmr_t	sh_xnni1_0_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_0_intrani_flow_s;
+} sh_xnni1_0_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_0_intrani_flow_u {
+	mmr_t	sh_xnni1_0_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_0_intrani_flow_s;
+} sh_xnni1_0_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_1_intrani_flow_u {
+	mmr_t	sh_xnni1_1_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_1_intrani_flow_s;
+} sh_xnni1_1_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_1_intrani_flow_u {
+	mmr_t	sh_xnni1_1_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni1_1_intrani_flow_s;
+} sh_xnni1_1_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_2_intrani_flow_u {
+	mmr_t	sh_xnni1_2_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_2_intrani_flow_s;
+} sh_xnni1_2_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_2_intrani_flow_u {
+	mmr_t	sh_xnni1_2_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni1_2_intrani_flow_s;
+} sh_xnni1_2_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_3_intrani_flow_u {
+	mmr_t	sh_xnni1_3_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_3_intrani_flow_s;
+} sh_xnni1_3_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_3_intrani_flow_u {
+	mmr_t	sh_xnni1_3_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni1_3_intrani_flow_s;
+} sh_xnni1_3_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_vcswitch_flow_u {
+	mmr_t	sh_xnni1_vcswitch_flow_regval;
+	struct {
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	reserved_4                : 29;
+	} sh_xnni1_vcswitch_flow_s;
+} sh_xnni1_vcswitch_flow_u_t;
+#else
+typedef union sh_xnni1_vcswitch_flow_u {
+	mmr_t	sh_xnni1_vcswitch_flow_regval;
+	struct {
+		mmr_t	reserved_4                : 29;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+	} sh_xnni1_vcswitch_flow_s;
+} sh_xnni1_vcswitch_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_TIMER_REG"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_timer_reg_u {
+	mmr_t	sh_xnni1_timer_reg_regval;
+	struct {
+		mmr_t	timeout_reg     : 24;
+		mmr_t	reserved_0      : 8;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_1      : 31;
+	} sh_xnni1_timer_reg_s;
+} sh_xnni1_timer_reg_u_t;
+#else
+typedef union sh_xnni1_timer_reg_u {
+	mmr_t	sh_xnni1_timer_reg_regval;
+	struct {
+		mmr_t	reserved_1      : 31;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_0      : 8;
+		mmr_t	timeout_reg     : 24;
+	} sh_xnni1_timer_reg_s;
+} sh_xnni1_timer_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fifo02_flow_u {
+	mmr_t	sh_xnni1_fifo02_flow_regval;
+	struct {
+		mmr_t	count_vc0_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni1_fifo02_flow_s;
+} sh_xnni1_fifo02_flow_u_t;
+#else
+typedef union sh_xnni1_fifo02_flow_u {
+	mmr_t	sh_xnni1_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_limit : 4;
+	} sh_xnni1_fifo02_flow_s;
+} sh_xnni1_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fifo13_flow_u {
+	mmr_t	sh_xnni1_fifo13_flow_regval;
+	struct {
+		mmr_t	count_vc1_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni1_fifo13_flow_s;
+} sh_xnni1_fifo13_flow_u_t;
+#else
+typedef union sh_xnni1_fifo13_flow_u {
+	mmr_t	sh_xnni1_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_limit : 4;
+	} sh_xnni1_fifo13_flow_s;
+} sh_xnni1_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI1_NI_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_ni_flow_u {
+	mmr_t	sh_xnni1_ni_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni1_ni_flow_s;
+} sh_xnni1_ni_flow_u_t;
+#else
+typedef union sh_xnni1_ni_flow_u {
+	mmr_t	sh_xnni1_ni_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni1_ni_flow_s;
+} sh_xnni1_ni_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_dead_flow_u {
+	mmr_t	sh_xnni1_dead_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni1_dead_flow_s;
+} sh_xnni1_dead_flow_u_t;
+#else
+typedef union sh_xnni1_dead_flow_u {
+	mmr_t	sh_xnni1_dead_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni1_dead_flow_s;
+} sh_xnni1_dead_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_inject_age_u {
+	mmr_t	sh_xnni1_inject_age_regval;
+	struct {
+		mmr_t	request_inject : 8;
+		mmr_t	reply_inject   : 8;
+		mmr_t	reserved_0     : 48;
+	} sh_xnni1_inject_age_s;
+} sh_xnni1_inject_age_u_t;
+#else
+typedef union sh_xnni1_inject_age_u {
+	mmr_t	sh_xnni1_inject_age_regval;
+	struct {
+		mmr_t	reserved_0     : 48;
+		mmr_t	reply_inject   : 8;
+		mmr_t	request_inject : 8;
+	} sh_xnni1_inject_age_s;
+} sh_xnni1_inject_age_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_XN_DEBUG_SEL"                      */
+/*                         XN Debug Port Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_sel_u {
+	mmr_t	sh_xn_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_rlm_sel    : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_rlm_sel    : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_rlm_sel    : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_rlm_sel    : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_rlm_sel    : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_rlm_sel    : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_rlm_sel    : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_rlm_sel    : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	trigger_enable     : 1;
+	} sh_xn_debug_sel_s;
+} sh_xn_debug_sel_u_t;
+#else
+typedef union sh_xn_debug_sel_u {
+	mmr_t	sh_xn_debug_sel_regval;
+	struct {
+		mmr_t	trigger_enable     : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_rlm_sel    : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_rlm_sel    : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_rlm_sel    : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_rlm_sel    : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_rlm_sel    : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_rlm_sel    : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_rlm_sel    : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_rlm_sel    : 3;
+	} sh_xn_debug_sel_s;
+} sh_xn_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_DEBUG_TRIG_SEL"                    */
+/*                       XN Debug trigger Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_trig_sel_u {
+	mmr_t	sh_xn_debug_trig_sel_regval;
+	struct {
+		mmr_t	trigger0_rlm_sel    : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	trigger0_nibble_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	trigger1_rlm_sel    : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	trigger1_nibble_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	trigger2_rlm_sel    : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	trigger2_nibble_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	trigger3_rlm_sel    : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	trigger3_nibble_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	trigger4_rlm_sel    : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	trigger4_nibble_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	trigger5_rlm_sel    : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	trigger5_nibble_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	trigger6_rlm_sel    : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	trigger6_nibble_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	trigger7_rlm_sel    : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	trigger7_nibble_sel : 3;
+		mmr_t	reserved_15         : 1;
+	} sh_xn_debug_trig_sel_s;
+} sh_xn_debug_trig_sel_u_t;
+#else
+typedef union sh_xn_debug_trig_sel_u {
+	mmr_t	sh_xn_debug_trig_sel_regval;
+	struct {
+		mmr_t	reserved_15         : 1;
+		mmr_t	trigger7_nibble_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	trigger7_rlm_sel    : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	trigger6_nibble_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	trigger6_rlm_sel    : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	trigger5_nibble_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	trigger5_rlm_sel    : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	trigger4_nibble_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	trigger4_rlm_sel    : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	trigger3_nibble_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	trigger3_rlm_sel    : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	trigger2_nibble_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	trigger2_rlm_sel    : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	trigger1_nibble_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	trigger1_rlm_sel    : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	trigger0_nibble_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	trigger0_rlm_sel    : 3;
+	} sh_xn_debug_trig_sel_s;
+} sh_xn_debug_trig_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_TRIGGER_COMPARE"                   */
+/*                           XN Debug Compare                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_trigger_compare_u {
+	mmr_t	sh_xn_trigger_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_xn_trigger_compare_s;
+} sh_xn_trigger_compare_u_t;
+#else
+typedef union sh_xn_trigger_compare_u {
+	mmr_t	sh_xn_trigger_compare_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_xn_trigger_compare_s;
+} sh_xn_trigger_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_TRIGGER_DATA"                     */
+/*                        XN Debug Compare Data                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_trigger_data_u {
+	mmr_t	sh_xn_trigger_data_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_xn_trigger_data_s;
+} sh_xn_trigger_data_u_t;
+#else
+typedef union sh_xn_trigger_data_u {
+	mmr_t	sh_xn_trigger_data_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_xn_trigger_data_s;
+} sh_xn_trigger_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_IILB_DEBUG_SEL"                    */
+/*                      XN IILB Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_debug_sel_u {
+	mmr_t	sh_xn_iilb_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_iilb_debug_sel_s;
+} sh_xn_iilb_debug_sel_u_t;
+#else
+typedef union sh_xn_iilb_debug_sel_u {
+	mmr_t	sh_xn_iilb_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_iilb_debug_sel_s;
+} sh_xn_iilb_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_PI_DEBUG_SEL"                     */
+/*                       XN PI Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_debug_sel_u {
+	mmr_t	sh_xn_pi_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_pi_debug_sel_s;
+} sh_xn_pi_debug_sel_u_t;
+#else
+typedef union sh_xn_pi_debug_sel_u {
+	mmr_t	sh_xn_pi_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_pi_debug_sel_s;
+} sh_xn_pi_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_DEBUG_SEL"                     */
+/*                       XN MD Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_debug_sel_u {
+	mmr_t	sh_xn_md_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_md_debug_sel_s;
+} sh_xn_md_debug_sel_u_t;
+#else
+typedef union sh_xn_md_debug_sel_u {
+	mmr_t	sh_xn_md_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_md_debug_sel_s;
+} sh_xn_md_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI0_DEBUG_SEL"                    */
+/*                       XN NI0 Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_debug_sel_u {
+	mmr_t	sh_xn_ni0_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_ni0_debug_sel_s;
+} sh_xn_ni0_debug_sel_u_t;
+#else
+typedef union sh_xn_ni0_debug_sel_u {
+	mmr_t	sh_xn_ni0_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_ni0_debug_sel_s;
+} sh_xn_ni0_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI1_DEBUG_SEL"                    */
+/*                       XN NI1 Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_debug_sel_u {
+	mmr_t	sh_xn_ni1_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_ni1_debug_sel_s;
+} sh_xn_ni1_debug_sel_u_t;
+#else
+typedef union sh_xn_ni1_debug_sel_u {
+	mmr_t	sh_xn_ni1_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_ni1_debug_sel_s;
+} sh_xn_ni1_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA0"                */
+/*                 IILB compare LB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data0_s;
+} sh_xn_iilb_lb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data0_s;
+} sh_xn_iilb_lb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA1"                */
+/*                 IILB compare LB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data1_s;
+} sh_xn_iilb_lb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data1_s;
+} sh_xn_iilb_lb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE0"                 */
+/*                    IILB compare LB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable0_s;
+} sh_xn_iilb_lb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable0_s;
+} sh_xn_iilb_lb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE1"                 */
+/*                    IILB compare LB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable1_s;
+} sh_xn_iilb_lb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable1_s;
+} sh_xn_iilb_lb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA0"                */
+/*                 IILB compare II input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data0_s;
+} sh_xn_iilb_ii_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data0_s;
+} sh_xn_iilb_ii_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA1"                */
+/*                 IILB compare II input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data1_s;
+} sh_xn_iilb_ii_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data1_s;
+} sh_xn_iilb_ii_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE0"                 */
+/*                    IILB compare II input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable0_s;
+} sh_xn_iilb_ii_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable0_s;
+} sh_xn_iilb_ii_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE1"                 */
+/*                    IILB compare II input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable1_s;
+} sh_xn_iilb_ii_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable1_s;
+} sh_xn_iilb_ii_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA0"                */
+/*                 IILB compare MD input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data0_s;
+} sh_xn_iilb_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data0_s;
+} sh_xn_iilb_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA1"                */
+/*                 IILB compare MD input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data1_s;
+} sh_xn_iilb_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data1_s;
+} sh_xn_iilb_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE0"                 */
+/*                    IILB compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable0_s;
+} sh_xn_iilb_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable0_s;
+} sh_xn_iilb_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE1"                 */
+/*                    IILB compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable1_s;
+} sh_xn_iilb_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable1_s;
+} sh_xn_iilb_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA0"                */
+/*                 IILB compare PI input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data0_s;
+} sh_xn_iilb_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data0_s;
+} sh_xn_iilb_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA1"                */
+/*                 IILB compare PI input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data1_s;
+} sh_xn_iilb_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data1_s;
+} sh_xn_iilb_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE0"                 */
+/*                    IILB compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable0_s;
+} sh_xn_iilb_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable0_s;
+} sh_xn_iilb_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE1"                 */
+/*                    IILB compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable1_s;
+} sh_xn_iilb_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable1_s;
+} sh_xn_iilb_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA0"                */
+/*                IILB compare NI0 input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data0_s;
+} sh_xn_iilb_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data0_s;
+} sh_xn_iilb_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA1"                */
+/*                IILB compare NI0 input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data1_s;
+} sh_xn_iilb_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data1_s;
+} sh_xn_iilb_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE0"                 */
+/*                    IILB compare NI0 input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable0_s;
+} sh_xn_iilb_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable0_s;
+} sh_xn_iilb_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE1"                 */
+/*                    IILB compare NI0 input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable1_s;
+} sh_xn_iilb_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable1_s;
+} sh_xn_iilb_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA0"                */
+/*                IILB compare NI1 input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data0_s;
+} sh_xn_iilb_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data0_s;
+} sh_xn_iilb_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA1"                */
+/*                IILB compare NI1 input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data1_s;
+} sh_xn_iilb_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data1_s;
+} sh_xn_iilb_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE0"                 */
+/*                    IILB compare NI1 input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable0_s;
+} sh_xn_iilb_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable0_s;
+} sh_xn_iilb_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE1"                 */
+/*                    IILB compare NI1 input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable1_s;
+} sh_xn_iilb_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable1_s;
+} sh_xn_iilb_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA0"                */
+/*                 MD compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data0_s;
+} sh_xn_md_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data0_s;
+} sh_xn_md_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA1"                */
+/*                 MD compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data1_s;
+} sh_xn_md_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data1_s;
+} sh_xn_md_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE0"                 */
+/*                    MD compare IILB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable0_s;
+} sh_xn_md_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable0_s;
+} sh_xn_md_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE1"                 */
+/*                    MD compare IILB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable1_s;
+} sh_xn_md_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable1_s;
+} sh_xn_md_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA0"                 */
+/*                 MD compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data0_s;
+} sh_xn_md_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data0_s;
+} sh_xn_md_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA1"                 */
+/*                 MD compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data1_s;
+} sh_xn_md_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data1_s;
+} sh_xn_md_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE0"                  */
+/*                     MD compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable0_s;
+} sh_xn_md_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable0_s;
+} sh_xn_md_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE1"                  */
+/*                     MD compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable1_s;
+} sh_xn_md_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable1_s;
+} sh_xn_md_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA0"                 */
+/*                 MD compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data0_s;
+} sh_xn_md_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data0_s;
+} sh_xn_md_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA1"                 */
+/*                 MD compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data1_s;
+} sh_xn_md_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data1_s;
+} sh_xn_md_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE0"                  */
+/*                     MD compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable0_s;
+} sh_xn_md_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable0_s;
+} sh_xn_md_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE1"                  */
+/*                     MD compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable1_s;
+} sh_xn_md_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable1_s;
+} sh_xn_md_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR0"                 */
+/*                MD compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_sic_cmp_exp_hdr0_s;
+} sh_xn_md_sic_cmp_exp_hdr0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_sic_cmp_exp_hdr0_s;
+} sh_xn_md_sic_cmp_exp_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR1"                 */
+/*                MD compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	data        : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_md_sic_cmp_exp_hdr1_s;
+} sh_xn_md_sic_cmp_exp_hdr1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	data        : 42;
+	} sh_xn_md_sic_cmp_exp_hdr1_s;
+} sh_xn_md_sic_cmp_exp_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0"                */
+/*                    MD compare SIC header enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_sic_cmp_hdr_enable0_s;
+} sh_xn_md_sic_cmp_hdr_enable0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_sic_cmp_hdr_enable0_s;
+} sh_xn_md_sic_cmp_hdr_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1"                */
+/*                    MD compare SIC header enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	enable      : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_md_sic_cmp_hdr_enable1_s;
+} sh_xn_md_sic_cmp_hdr_enable1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	enable      : 42;
+	} sh_xn_md_sic_cmp_hdr_enable1_s;
+} sh_xn_md_sic_cmp_hdr_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA0"                   */
+/*                         MD compare SIC data0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data0_u {
+	mmr_t	sh_xn_md_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_md_sic_cmp_data0_s;
+} sh_xn_md_sic_cmp_data0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data0_u {
+	mmr_t	sh_xn_md_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_md_sic_cmp_data0_s;
+} sh_xn_md_sic_cmp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA1"                   */
+/*                         MD compare SIC data1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data1_u {
+	mmr_t	sh_xn_md_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_md_sic_cmp_data1_s;
+} sh_xn_md_sic_cmp_data1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data1_u {
+	mmr_t	sh_xn_md_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_md_sic_cmp_data1_s;
+} sh_xn_md_sic_cmp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA2"                   */
+/*                         MD compare SIC data2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data2_u {
+	mmr_t	sh_xn_md_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_md_sic_cmp_data2_s;
+} sh_xn_md_sic_cmp_data2_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data2_u {
+	mmr_t	sh_xn_md_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_md_sic_cmp_data2_s;
+} sh_xn_md_sic_cmp_data2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA3"                   */
+/*                         MD compare SIC data3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data3_u {
+	mmr_t	sh_xn_md_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_md_sic_cmp_data3_s;
+} sh_xn_md_sic_cmp_data3_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data3_u {
+	mmr_t	sh_xn_md_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_md_sic_cmp_data3_s;
+} sh_xn_md_sic_cmp_data3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0"               */
+/*                     MD enable compare SIC data0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_md_sic_cmp_data_enable0_s;
+} sh_xn_md_sic_cmp_data_enable0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_md_sic_cmp_data_enable0_s;
+} sh_xn_md_sic_cmp_data_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1"               */
+/*                     MD enable compare SIC data1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_md_sic_cmp_data_enable1_s;
+} sh_xn_md_sic_cmp_data_enable1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_md_sic_cmp_data_enable1_s;
+} sh_xn_md_sic_cmp_data_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2"               */
+/*                     MD enable compare SIC data2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_md_sic_cmp_data_enable2_s;
+} sh_xn_md_sic_cmp_data_enable2_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_md_sic_cmp_data_enable2_s;
+} sh_xn_md_sic_cmp_data_enable2_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3"               */
+/*                     MD enable compare SIC data3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_md_sic_cmp_data_enable3_s;
+} sh_xn_md_sic_cmp_data_enable3_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_md_sic_cmp_data_enable3_s;
+} sh_xn_md_sic_cmp_data_enable3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA0"                */
+/*                 PI compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data0_s;
+} sh_xn_pi_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data0_s;
+} sh_xn_pi_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA1"                */
+/*                 PI compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data1_s;
+} sh_xn_pi_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data1_s;
+} sh_xn_pi_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE0"                 */
+/*                    PI compare IILB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable0_s;
+} sh_xn_pi_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable0_s;
+} sh_xn_pi_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE1"                 */
+/*                    PI compare IILB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable1_s;
+} sh_xn_pi_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable1_s;
+} sh_xn_pi_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA0"                 */
+/*                 PI compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data0_s;
+} sh_xn_pi_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data0_s;
+} sh_xn_pi_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA1"                 */
+/*                 PI compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data1_s;
+} sh_xn_pi_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data1_s;
+} sh_xn_pi_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE0"                  */
+/*                     PI compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable0_s;
+} sh_xn_pi_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable0_s;
+} sh_xn_pi_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE1"                  */
+/*                     PI compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable1_s;
+} sh_xn_pi_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable1_s;
+} sh_xn_pi_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA0"                 */
+/*                 PI compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data0_s;
+} sh_xn_pi_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data0_s;
+} sh_xn_pi_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA1"                 */
+/*                 PI compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data1_s;
+} sh_xn_pi_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data1_s;
+} sh_xn_pi_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE0"                  */
+/*                     PI compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable0_s;
+} sh_xn_pi_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable0_s;
+} sh_xn_pi_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE1"                  */
+/*                     PI compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable1_s;
+} sh_xn_pi_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable1_s;
+} sh_xn_pi_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR0"                 */
+/*                PI compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_sic_cmp_exp_hdr0_s;
+} sh_xn_pi_sic_cmp_exp_hdr0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_sic_cmp_exp_hdr0_s;
+} sh_xn_pi_sic_cmp_exp_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR1"                 */
+/*                PI compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	data        : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_pi_sic_cmp_exp_hdr1_s;
+} sh_xn_pi_sic_cmp_exp_hdr1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	data        : 42;
+	} sh_xn_pi_sic_cmp_exp_hdr1_s;
+} sh_xn_pi_sic_cmp_exp_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0"                */
+/*                    PI compare SIC header enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_sic_cmp_hdr_enable0_s;
+} sh_xn_pi_sic_cmp_hdr_enable0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_sic_cmp_hdr_enable0_s;
+} sh_xn_pi_sic_cmp_hdr_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1"                */
+/*                    PI compare SIC header enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	enable      : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_pi_sic_cmp_hdr_enable1_s;
+} sh_xn_pi_sic_cmp_hdr_enable1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	enable      : 42;
+	} sh_xn_pi_sic_cmp_hdr_enable1_s;
+} sh_xn_pi_sic_cmp_hdr_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA0"                   */
+/*                         PI compare SIC data0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_pi_sic_cmp_data0_s;
+} sh_xn_pi_sic_cmp_data0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_pi_sic_cmp_data0_s;
+} sh_xn_pi_sic_cmp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA1"                   */
+/*                         PI compare SIC data1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_pi_sic_cmp_data1_s;
+} sh_xn_pi_sic_cmp_data1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_pi_sic_cmp_data1_s;
+} sh_xn_pi_sic_cmp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA2"                   */
+/*                         PI compare SIC data2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_pi_sic_cmp_data2_s;
+} sh_xn_pi_sic_cmp_data2_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_pi_sic_cmp_data2_s;
+} sh_xn_pi_sic_cmp_data2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA3"                   */
+/*                         PI compare SIC data3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_pi_sic_cmp_data3_s;
+} sh_xn_pi_sic_cmp_data3_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_pi_sic_cmp_data3_s;
+} sh_xn_pi_sic_cmp_data3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0"               */
+/*                     PI enable compare SIC data0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_pi_sic_cmp_data_enable0_s;
+} sh_xn_pi_sic_cmp_data_enable0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_pi_sic_cmp_data_enable0_s;
+} sh_xn_pi_sic_cmp_data_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1"               */
+/*                     PI enable compare SIC data1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_pi_sic_cmp_data_enable1_s;
+} sh_xn_pi_sic_cmp_data_enable1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_pi_sic_cmp_data_enable1_s;
+} sh_xn_pi_sic_cmp_data_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2"               */
+/*                     PI enable compare SIC data2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_pi_sic_cmp_data_enable2_s;
+} sh_xn_pi_sic_cmp_data_enable2_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_pi_sic_cmp_data_enable2_s;
+} sh_xn_pi_sic_cmp_data_enable2_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3"               */
+/*                     PI enable compare SIC data3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_pi_sic_cmp_data_enable3_s;
+} sh_xn_pi_sic_cmp_data_enable3_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_pi_sic_cmp_data_enable3_s;
+} sh_xn_pi_sic_cmp_data_enable3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA0"                */
+/*                NI0 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data0_s;
+} sh_xn_ni0_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data0_s;
+} sh_xn_ni0_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA1"                */
+/*                NI0 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data1_s;
+} sh_xn_ni0_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data1_s;
+} sh_xn_ni0_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE0"                 */
+/*                    NI0 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable0_s;
+} sh_xn_ni0_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable0_s;
+} sh_xn_ni0_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE1"                 */
+/*                    NI0 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable1_s;
+} sh_xn_ni0_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable1_s;
+} sh_xn_ni0_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data0_s;
+} sh_xn_ni0_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data0_s;
+} sh_xn_ni0_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data1_s;
+} sh_xn_ni0_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data1_s;
+} sh_xn_ni0_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE0"                  */
+/*                     NI0 compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable0_s;
+} sh_xn_ni0_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable0_s;
+} sh_xn_ni0_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE1"                  */
+/*                     NI0 compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable1_s;
+} sh_xn_ni0_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable1_s;
+} sh_xn_ni0_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA0"                 */
+/*                 NI0 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data0_s;
+} sh_xn_ni0_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data0_s;
+} sh_xn_ni0_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA1"                 */
+/*                 NI0 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data1_s;
+} sh_xn_ni0_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data1_s;
+} sh_xn_ni0_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE0"                  */
+/*                     NI0 compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable0_s;
+} sh_xn_ni0_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable0_s;
+} sh_xn_ni0_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE1"                  */
+/*                     NI0 compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable1_s;
+} sh_xn_ni0_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable1_s;
+} sh_xn_ni0_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data0_s;
+} sh_xn_ni0_ni_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data0_s;
+} sh_xn_ni0_ni_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data1_s;
+} sh_xn_ni0_ni_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data1_s;
+} sh_xn_ni0_ni_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE0"                  */
+/*                     NI0 compare NI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable0_s;
+} sh_xn_ni0_ni_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable0_s;
+} sh_xn_ni0_ni_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE1"                  */
+/*                     NI0 compare NI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable1_s;
+} sh_xn_ni0_ni_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable1_s;
+} sh_xn_ni0_ni_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA0"                */
+/*                 NI0 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data0_s;
+} sh_xn_ni0_llp_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data0_s;
+} sh_xn_ni0_llp_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA1"                */
+/*                 NI0 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data1_s;
+} sh_xn_ni0_llp_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data1_s;
+} sh_xn_ni0_llp_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE0"                 */
+/*                    NI0 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable0_s;
+} sh_xn_ni0_llp_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable0_s;
+} sh_xn_ni0_llp_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE1"                 */
+/*                    NI0 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable1_s;
+} sh_xn_ni0_llp_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable1_s;
+} sh_xn_ni0_llp_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA0"                */
+/*                NI1 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data0_s;
+} sh_xn_ni1_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data0_s;
+} sh_xn_ni1_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA1"                */
+/*                NI1 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data1_s;
+} sh_xn_ni1_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data1_s;
+} sh_xn_ni1_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE0"                 */
+/*                    NI1 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable0_s;
+} sh_xn_ni1_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable0_s;
+} sh_xn_ni1_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE1"                 */
+/*                    NI1 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable1_s;
+} sh_xn_ni1_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable1_s;
+} sh_xn_ni1_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data0_s;
+} sh_xn_ni1_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data0_s;
+} sh_xn_ni1_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data1_s;
+} sh_xn_ni1_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data1_s;
+} sh_xn_ni1_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE0"                  */
+/*                     NI1 compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable0_s;
+} sh_xn_ni1_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable0_s;
+} sh_xn_ni1_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE1"                  */
+/*                     NI1 compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable1_s;
+} sh_xn_ni1_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable1_s;
+} sh_xn_ni1_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA0"                 */
+/*                 NI1 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data0_s;
+} sh_xn_ni1_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data0_s;
+} sh_xn_ni1_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA1"                 */
+/*                 NI1 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data1_s;
+} sh_xn_ni1_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data1_s;
+} sh_xn_ni1_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE0"                  */
+/*                     NI1 compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable0_s;
+} sh_xn_ni1_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable0_s;
+} sh_xn_ni1_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE1"                  */
+/*                     NI1 compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable1_s;
+} sh_xn_ni1_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable1_s;
+} sh_xn_ni1_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data0_s;
+} sh_xn_ni1_ni_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data0_s;
+} sh_xn_ni1_ni_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data1_s;
+} sh_xn_ni1_ni_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data1_s;
+} sh_xn_ni1_ni_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE0"                  */
+/*                     NI1 compare NI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable0_s;
+} sh_xn_ni1_ni_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable0_s;
+} sh_xn_ni1_ni_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE1"                  */
+/*                     NI1 compare NI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable1_s;
+} sh_xn_ni1_ni_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable1_s;
+} sh_xn_ni1_ni_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA0"                */
+/*                 NI1 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data0_s;
+} sh_xn_ni1_llp_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data0_s;
+} sh_xn_ni1_llp_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA1"                */
+/*                 NI1 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data1_s;
+} sh_xn_ni1_llp_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data1_s;
+} sh_xn_ni1_llp_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE0"                 */
+/*                    NI1 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable0_s;
+} sh_xn_ni1_llp_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable0_s;
+} sh_xn_ni1_llp_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE1"                 */
+/*                    NI1 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable1_s;
+} sh_xn_ni1_llp_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable1_s;
+} sh_xn_ni1_llp_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc_inj_reg_u {
+	mmr_t	sh_xnpi_ecc_inj_reg_regval;
+	struct {
+		mmr_t	byte0          : 8;
+		mmr_t	reserved_0     : 4;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	byte1          : 8;
+		mmr_t	reserved_1     : 4;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	byte2          : 8;
+		mmr_t	reserved_2     : 4;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	byte3          : 8;
+		mmr_t	reserved_3     : 4;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cb_cont3  : 1;
+	} sh_xnpi_ecc_inj_reg_s;
+} sh_xnpi_ecc_inj_reg_u_t;
+#else
+typedef union sh_xnpi_ecc_inj_reg_u {
+	mmr_t	sh_xnpi_ecc_inj_reg_regval;
+	struct {
+		mmr_t	data_cb_cont3  : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	reserved_3     : 4;
+		mmr_t	byte3          : 8;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	reserved_2     : 4;
+		mmr_t	byte2          : 8;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	reserved_1     : 4;
+		mmr_t	byte1          : 8;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	reserved_0     : 4;
+		mmr_t	byte0          : 8;
+	} sh_xnpi_ecc_inj_reg_s;
+} sh_xnpi_ecc_inj_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnpi_ecc0_inj_mask_reg_s;
+} sh_xnpi_ecc0_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnpi_ecc0_inj_mask_reg_s;
+} sh_xnpi_ecc0_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnpi_ecc1_inj_mask_reg_s;
+} sh_xnpi_ecc1_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnpi_ecc1_inj_mask_reg_s;
+} sh_xnpi_ecc1_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnpi_ecc2_inj_mask_reg_s;
+} sh_xnpi_ecc2_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnpi_ecc2_inj_mask_reg_s;
+} sh_xnpi_ecc2_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnpi_ecc3_inj_mask_reg_s;
+} sh_xnpi_ecc3_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnpi_ecc3_inj_mask_reg_s;
+} sh_xnpi_ecc3_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc_inj_reg_u {
+	mmr_t	sh_xnmd_ecc_inj_reg_regval;
+	struct {
+		mmr_t	byte0          : 8;
+		mmr_t	reserved_0     : 4;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	byte1          : 8;
+		mmr_t	reserved_1     : 4;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	byte2          : 8;
+		mmr_t	reserved_2     : 4;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	byte3          : 8;
+		mmr_t	reserved_3     : 4;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cb_cont3  : 1;
+	} sh_xnmd_ecc_inj_reg_s;
+} sh_xnmd_ecc_inj_reg_u_t;
+#else
+typedef union sh_xnmd_ecc_inj_reg_u {
+	mmr_t	sh_xnmd_ecc_inj_reg_regval;
+	struct {
+		mmr_t	data_cb_cont3  : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	reserved_3     : 4;
+		mmr_t	byte3          : 8;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	reserved_2     : 4;
+		mmr_t	byte2          : 8;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	reserved_1     : 4;
+		mmr_t	byte1          : 8;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	reserved_0     : 4;
+		mmr_t	byte0          : 8;
+	} sh_xnmd_ecc_inj_reg_s;
+} sh_xnmd_ecc_inj_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnmd_ecc0_inj_mask_reg_s;
+} sh_xnmd_ecc0_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnmd_ecc0_inj_mask_reg_s;
+} sh_xnmd_ecc0_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnmd_ecc1_inj_mask_reg_s;
+} sh_xnmd_ecc1_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnmd_ecc1_inj_mask_reg_s;
+} sh_xnmd_ecc1_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnmd_ecc2_inj_mask_reg_s;
+} sh_xnmd_ecc2_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnmd_ecc2_inj_mask_reg_s;
+} sh_xnmd_ecc2_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnmd_ecc3_inj_mask_reg_s;
+} sh_xnmd_ecc3_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnmd_ecc3_inj_mask_reg_s;
+} sh_xnmd_ecc3_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ECC_ERR_REPORT"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc_err_report_u {
+	mmr_t	sh_xnmd_ecc_err_report_regval;
+	struct {
+		mmr_t	ecc_disable0 : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	ecc_disable1 : 1;
+		mmr_t	reserved_1   : 15;
+		mmr_t	ecc_disable2 : 1;
+		mmr_t	reserved_2   : 15;
+		mmr_t	ecc_disable3 : 1;
+		mmr_t	reserved_3   : 15;
+	} sh_xnmd_ecc_err_report_s;
+} sh_xnmd_ecc_err_report_u_t;
+#else
+typedef union sh_xnmd_ecc_err_report_u {
+	mmr_t	sh_xnmd_ecc_err_report_regval;
+	struct {
+		mmr_t	reserved_3   : 15;
+		mmr_t	ecc_disable3 : 1;
+		mmr_t	reserved_2   : 15;
+		mmr_t	ecc_disable2 : 1;
+		mmr_t	reserved_1   : 15;
+		mmr_t	ecc_disable1 : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	ecc_disable0 : 1;
+	} sh_xnmd_ecc_err_report_s;
+} sh_xnmd_ecc_err_report_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_1"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_summary_1_u {
+	mmr_t	sh_ni0_error_summary_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_summary_1_s;
+} sh_ni0_error_summary_1_u_t;
+#else
+typedef union sh_ni0_error_summary_1_u {
+	mmr_t	sh_ni0_error_summary_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_summary_1_s;
+} sh_ni0_error_summary_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_2"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_summary_2_u {
+	mmr_t	sh_ni0_error_summary_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_summary_2_s;
+} sh_ni0_error_summary_2_u_t;
+#else
+typedef union sh_ni0_error_summary_2_u {
+	mmr_t	sh_ni0_error_summary_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_summary_2_s;
+} sh_ni0_error_summary_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_1"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_overflow_1_u {
+	mmr_t	sh_ni0_error_overflow_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_overflow_1_s;
+} sh_ni0_error_overflow_1_u_t;
+#else
+typedef union sh_ni0_error_overflow_1_u {
+	mmr_t	sh_ni0_error_overflow_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_overflow_1_s;
+} sh_ni0_error_overflow_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_2"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_overflow_2_u {
+	mmr_t	sh_ni0_error_overflow_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_overflow_2_s;
+} sh_ni0_error_overflow_2_u_t;
+#else
+typedef union sh_ni0_error_overflow_2_u {
+	mmr_t	sh_ni0_error_overflow_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_overflow_2_s;
+} sh_ni0_error_overflow_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_1"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_mask_1_u {
+	mmr_t	sh_ni0_error_mask_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_mask_1_s;
+} sh_ni0_error_mask_1_u_t;
+#else
+typedef union sh_ni0_error_mask_1_u {
+	mmr_t	sh_ni0_error_mask_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_mask_1_s;
+} sh_ni0_error_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_2"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_mask_2_u {
+	mmr_t	sh_ni0_error_mask_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_mask_2_s;
+} sh_ni0_error_mask_2_u_t;
+#else
+typedef union sh_ni0_error_mask_2_u {
+	mmr_t	sh_ni0_error_mask_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_mask_2_s;
+} sh_ni0_error_mask_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_1"                    */
+/*                        ni0  First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_first_error_1_u {
+	mmr_t	sh_ni0_first_error_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_first_error_1_s;
+} sh_ni0_first_error_1_u_t;
+#else
+typedef union sh_ni0_first_error_1_u {
+	mmr_t	sh_ni0_first_error_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_first_error_1_s;
+} sh_ni0_first_error_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_2"                    */
+/*                         ni0 First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_first_error_2_u {
+	mmr_t	sh_ni0_first_error_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_first_error_2_s;
+} sh_ni0_first_error_2_u_t;
+#else
+typedef union sh_ni0_first_error_2_u {
+	mmr_t	sh_ni0_first_error_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_first_error_2_s;
+} sh_ni0_first_error_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_1"                   */
+/*                ni0 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_1_u {
+	mmr_t	sh_ni0_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_1_s;
+} sh_ni0_error_detail_1_u_t;
+#else
+typedef union sh_ni0_error_detail_1_u {
+	mmr_t	sh_ni0_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_1_s;
+} sh_ni0_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_2"                   */
+/*               ni0 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_2_u {
+	mmr_t	sh_ni0_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_2_s;
+} sh_ni0_error_detail_2_u_t;
+#else
+typedef union sh_ni0_error_detail_2_u {
+	mmr_t	sh_ni0_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_2_s;
+} sh_ni0_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_1"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_summary_1_u {
+	mmr_t	sh_ni1_error_summary_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_summary_1_s;
+} sh_ni1_error_summary_1_u_t;
+#else
+typedef union sh_ni1_error_summary_1_u {
+	mmr_t	sh_ni1_error_summary_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_summary_1_s;
+} sh_ni1_error_summary_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_2"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_summary_2_u {
+	mmr_t	sh_ni1_error_summary_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_summary_2_s;
+} sh_ni1_error_summary_2_u_t;
+#else
+typedef union sh_ni1_error_summary_2_u {
+	mmr_t	sh_ni1_error_summary_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_summary_2_s;
+} sh_ni1_error_summary_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_1"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_overflow_1_u {
+	mmr_t	sh_ni1_error_overflow_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_overflow_1_s;
+} sh_ni1_error_overflow_1_u_t;
+#else
+typedef union sh_ni1_error_overflow_1_u {
+	mmr_t	sh_ni1_error_overflow_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_overflow_1_s;
+} sh_ni1_error_overflow_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_2"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_overflow_2_u {
+	mmr_t	sh_ni1_error_overflow_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_overflow_2_s;
+} sh_ni1_error_overflow_2_u_t;
+#else
+typedef union sh_ni1_error_overflow_2_u {
+	mmr_t	sh_ni1_error_overflow_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_overflow_2_s;
+} sh_ni1_error_overflow_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_1"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_mask_1_u {
+	mmr_t	sh_ni1_error_mask_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_mask_1_s;
+} sh_ni1_error_mask_1_u_t;
+#else
+typedef union sh_ni1_error_mask_1_u {
+	mmr_t	sh_ni1_error_mask_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_mask_1_s;
+} sh_ni1_error_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_2"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_mask_2_u {
+	mmr_t	sh_ni1_error_mask_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_mask_2_s;
+} sh_ni1_error_mask_2_u_t;
+#else
+typedef union sh_ni1_error_mask_2_u {
+	mmr_t	sh_ni1_error_mask_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_mask_2_s;
+} sh_ni1_error_mask_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_1"                    */
+/*                        ni1  First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_first_error_1_u {
+	mmr_t	sh_ni1_first_error_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_first_error_1_s;
+} sh_ni1_first_error_1_u_t;
+#else
+typedef union sh_ni1_first_error_1_u {
+	mmr_t	sh_ni1_first_error_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_first_error_1_s;
+} sh_ni1_first_error_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_2"                    */
+/*                         ni1 First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_first_error_2_u {
+	mmr_t	sh_ni1_first_error_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_first_error_2_s;
+} sh_ni1_first_error_2_u_t;
+#else
+typedef union sh_ni1_first_error_2_u {
+	mmr_t	sh_ni1_first_error_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_first_error_2_s;
+} sh_ni1_first_error_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_1"                   */
+/*                ni1 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_1_u {
+	mmr_t	sh_ni1_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_1_s;
+} sh_ni1_error_detail_1_u_t;
+#else
+typedef union sh_ni1_error_detail_1_u {
+	mmr_t	sh_ni1_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_1_s;
+} sh_ni1_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_2"                   */
+/*               ni1 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_2_u {
+	mmr_t	sh_ni1_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_2_s;
+} sh_ni1_error_detail_2_u_t;
+#else
+typedef union sh_ni1_error_detail_2_u {
+	mmr_t	sh_ni1_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_2_s;
+} sh_ni1_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_1"                  */
+/*                       Corrected error details                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_1_u {
+	mmr_t	sh_xn_corrected_detail_1_regval;
+	struct {
+		mmr_t	ecc0_syndrome : 8;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	reserved_3    : 4;
+	} sh_xn_corrected_detail_1_s;
+} sh_xn_corrected_detail_1_u_t;
+#else
+typedef union sh_xn_corrected_detail_1_u {
+	mmr_t	sh_xn_corrected_detail_1_regval;
+	struct {
+		mmr_t	reserved_3    : 4;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_syndrome : 8;
+	} sh_xn_corrected_detail_1_s;
+} sh_xn_corrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_2"                  */
+/*                         Corrected error data                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_2_u {
+	mmr_t	sh_xn_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_corrected_detail_2_s;
+} sh_xn_corrected_detail_2_u_t;
+#else
+typedef union sh_xn_corrected_detail_2_u {
+	mmr_t	sh_xn_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_corrected_detail_2_s;
+} sh_xn_corrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_3"                  */
+/*                       Corrected error header0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_3_u {
+	mmr_t	sh_xn_corrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_corrected_detail_3_s;
+} sh_xn_corrected_detail_3_u_t;
+#else
+typedef union sh_xn_corrected_detail_3_u {
+	mmr_t	sh_xn_corrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_corrected_detail_3_s;
+} sh_xn_corrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_4"                  */
+/*                       Corrected error header1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_4_u {
+	mmr_t	sh_xn_corrected_detail_4_regval;
+	struct {
+		mmr_t	header1     : 42;
+		mmr_t	reserved_0  : 20;
+		mmr_t	err_group   : 2;
+	} sh_xn_corrected_detail_4_s;
+} sh_xn_corrected_detail_4_u_t;
+#else
+typedef union sh_xn_corrected_detail_4_u {
+	mmr_t	sh_xn_corrected_detail_4_regval;
+	struct {
+		mmr_t	err_group   : 2;
+		mmr_t	reserved_0  : 20;
+		mmr_t	header1     : 42;
+	} sh_xn_corrected_detail_4_s;
+} sh_xn_corrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_1"                 */
+/*                      Uncorrected error details                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_1_u {
+	mmr_t	sh_xn_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	ecc0_syndrome : 8;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	reserved_3    : 4;
+	} sh_xn_uncorrected_detail_1_s;
+} sh_xn_uncorrected_detail_1_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_1_u {
+	mmr_t	sh_xn_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	reserved_3    : 4;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_syndrome : 8;
+	} sh_xn_uncorrected_detail_1_s;
+} sh_xn_uncorrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_2"                 */
+/*                        Uncorrected error data                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_2_u {
+	mmr_t	sh_xn_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_uncorrected_detail_2_s;
+} sh_xn_uncorrected_detail_2_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_2_u {
+	mmr_t	sh_xn_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_uncorrected_detail_2_s;
+} sh_xn_uncorrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_3"                 */
+/*                      Uncorrected error header0                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_3_u {
+	mmr_t	sh_xn_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_uncorrected_detail_3_s;
+} sh_xn_uncorrected_detail_3_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_3_u {
+	mmr_t	sh_xn_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_uncorrected_detail_3_s;
+} sh_xn_uncorrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_4"                 */
+/*                      Uncorrected error header1                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_4_u {
+	mmr_t	sh_xn_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	header1     : 42;
+		mmr_t	reserved_0  : 20;
+		mmr_t	err_group   : 2;
+	} sh_xn_uncorrected_detail_4_s;
+} sh_xn_uncorrected_detail_4_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_4_u {
+	mmr_t	sh_xn_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	err_group   : 2;
+		mmr_t	reserved_0  : 20;
+		mmr_t	header1     : 42;
+	} sh_xn_uncorrected_detail_4_s;
+} sh_xn_uncorrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (md)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_detail_1_u {
+	mmr_t	sh_xnmd_error_detail_1_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xnmd_error_detail_1_s;
+} sh_xnmd_error_detail_1_u_t;
+#else
+typedef union sh_xnmd_error_detail_1_u {
+	mmr_t	sh_xnmd_error_detail_1_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xnmd_error_detail_1_s;
+} sh_xnmd_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (pi)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_detail_1_u {
+	mmr_t	sh_xnpi_error_detail_1_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xnpi_error_detail_1_s;
+} sh_xnpi_error_detail_1_u_t;
+#else
+typedef union sh_xnpi_error_detail_1_u {
+	mmr_t	sh_xnpi_error_detail_1_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xnpi_error_detail_1_s;
+} sh_xnpi_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_1"                  */
+/*                    Chiplet NoMatch header [63:0]                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_1_u {
+	mmr_t	sh_xniilb_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_1_s;
+} sh_xniilb_error_detail_1_u_t;
+#else
+typedef union sh_xniilb_error_detail_1_u {
+	mmr_t	sh_xniilb_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_1_s;
+} sh_xniilb_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_2"                  */
+/*                   Chiplet NoMatch header [127:64]                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_2_u {
+	mmr_t	sh_xniilb_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_2_s;
+} sh_xniilb_error_detail_2_u_t;
+#else
+typedef union sh_xniilb_error_detail_2_u {
+	mmr_t	sh_xniilb_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_2_s;
+} sh_xniilb_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_3"                  */
+/*                     Look Up Table Address (iilb)                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_3_u {
+	mmr_t	sh_xniilb_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xniilb_error_detail_3_s;
+} sh_xniilb_error_detail_3_u_t;
+#else
+typedef union sh_xniilb_error_detail_3_u {
+	mmr_t	sh_xniilb_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xniilb_error_detail_3_s;
+} sh_xniilb_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni0)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_3_u {
+	mmr_t	sh_ni0_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_ni0_error_detail_3_s;
+} sh_ni0_error_detail_3_u_t;
+#else
+typedef union sh_ni0_error_detail_3_u {
+	mmr_t	sh_ni0_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_ni0_error_detail_3_s;
+} sh_ni0_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni1)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_3_u {
+	mmr_t	sh_ni1_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_ni1_error_detail_3_s;
+} sh_ni1_error_detail_3_u_t;
+#else
+typedef union sh_ni1_error_detail_3_u {
+	mmr_t	sh_ni1_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_ni1_error_detail_3_s;
+} sh_ni1_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERROR_SUMMARY"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_summary_u {
+	mmr_t	sh_xn_error_summary_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_summary_s;
+} sh_xn_error_summary_u_t;
+#else
+typedef union sh_xn_error_summary_u {
+	mmr_t	sh_xn_error_summary_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_summary_s;
+} sh_xn_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_ERROR_OVERFLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_overflow_u {
+	mmr_t	sh_xn_error_overflow_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_overflow_s;
+} sh_xn_error_overflow_u_t;
+#else
+typedef union sh_xn_error_overflow_u {
+	mmr_t	sh_xn_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_overflow_s;
+} sh_xn_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_ERROR_MASK"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_mask_u {
+	mmr_t	sh_xn_error_mask_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_mask_s;
+} sh_xn_error_mask_u_t;
+#else
+typedef union sh_xn_error_mask_u {
+	mmr_t	sh_xn_error_mask_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_mask_s;
+} sh_xn_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_FIRST_ERROR"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_first_error_u {
+	mmr_t	sh_xn_first_error_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_first_error_s;
+} sh_xn_first_error_u_t;
+#else
+typedef union sh_xn_first_error_u {
+	mmr_t	sh_xn_first_error_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_first_error_s;
+} sh_xn_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERROR_SUMMARY"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_summary_u {
+	mmr_t	sh_xniilb_error_summary_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_summary_s;
+} sh_xniilb_error_summary_u_t;
+#else
+typedef union sh_xniilb_error_summary_u {
+	mmr_t	sh_xniilb_error_summary_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_summary_s;
+} sh_xniilb_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_OVERFLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_overflow_u {
+	mmr_t	sh_xniilb_error_overflow_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_overflow_s;
+} sh_xniilb_error_overflow_u_t;
+#else
+typedef union sh_xniilb_error_overflow_u {
+	mmr_t	sh_xniilb_error_overflow_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_overflow_s;
+} sh_xniilb_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_ERROR_MASK"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_mask_u {
+	mmr_t	sh_xniilb_error_mask_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_mask_s;
+} sh_xniilb_error_mask_u_t;
+#else
+typedef union sh_xniilb_error_mask_u {
+	mmr_t	sh_xniilb_error_mask_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_mask_s;
+} sh_xniilb_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_FIRST_ERROR"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_first_error_u {
+	mmr_t	sh_xniilb_first_error_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_first_error_s;
+} sh_xniilb_first_error_u_t;
+#else
+typedef union sh_xniilb_first_error_u {
+	mmr_t	sh_xniilb_first_error_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_first_error_s;
+} sh_xniilb_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_summary_u {
+	mmr_t	sh_xnpi_error_summary_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_summary_s;
+} sh_xnpi_error_summary_u_t;
+#else
+typedef union sh_xnpi_error_summary_u {
+	mmr_t	sh_xnpi_error_summary_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_summary_s;
+} sh_xnpi_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_overflow_u {
+	mmr_t	sh_xnpi_error_overflow_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_overflow_s;
+} sh_xnpi_error_overflow_u_t;
+#else
+typedef union sh_xnpi_error_overflow_u {
+	mmr_t	sh_xnpi_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_overflow_s;
+} sh_xnpi_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_mask_u {
+	mmr_t	sh_xnpi_error_mask_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_mask_s;
+} sh_xnpi_error_mask_u_t;
+#else
+typedef union sh_xnpi_error_mask_u {
+	mmr_t	sh_xnpi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_mask_s;
+} sh_xnpi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_first_error_u {
+	mmr_t	sh_xnpi_first_error_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_first_error_s;
+} sh_xnpi_first_error_u_t;
+#else
+typedef union sh_xnpi_first_error_u {
+	mmr_t	sh_xnpi_first_error_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_first_error_s;
+} sh_xnpi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_summary_u {
+	mmr_t	sh_xnmd_error_summary_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_summary_s;
+} sh_xnmd_error_summary_u_t;
+#else
+typedef union sh_xnmd_error_summary_u {
+	mmr_t	sh_xnmd_error_summary_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_summary_s;
+} sh_xnmd_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_overflow_u {
+	mmr_t	sh_xnmd_error_overflow_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_overflow_s;
+} sh_xnmd_error_overflow_u_t;
+#else
+typedef union sh_xnmd_error_overflow_u {
+	mmr_t	sh_xnmd_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_overflow_s;
+} sh_xnmd_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_mask_u {
+	mmr_t	sh_xnmd_error_mask_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_mask_s;
+} sh_xnmd_error_mask_u_t;
+#else
+typedef union sh_xnmd_error_mask_u {
+	mmr_t	sh_xnmd_error_mask_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_mask_s;
+} sh_xnmd_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_first_error_u {
+	mmr_t	sh_xnmd_first_error_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_first_error_s;
+} sh_xnmd_first_error_u_t;
+#else
+typedef union sh_xnmd_first_error_u {
+	mmr_t	sh_xnmd_first_error_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_first_error_s;
+} sh_xnmd_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE0"                   */
+/*                 Automatic Maintenance Reply Enable 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_enable0_u {
+	mmr_t	sh_auto_reply_enable0_regval;
+	struct {
+		mmr_t	enable0     : 64;
+	} sh_auto_reply_enable0_s;
+} sh_auto_reply_enable0_u_t;
+#else
+typedef union sh_auto_reply_enable0_u {
+	mmr_t	sh_auto_reply_enable0_regval;
+	struct {
+		mmr_t	enable0     : 64;
+	} sh_auto_reply_enable0_s;
+} sh_auto_reply_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE1"                   */
+/*                 Automatic Maintenance Reply Enable 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_enable1_u {
+	mmr_t	sh_auto_reply_enable1_regval;
+	struct {
+		mmr_t	enable1     : 64;
+	} sh_auto_reply_enable1_s;
+} sh_auto_reply_enable1_u_t;
+#else
+typedef union sh_auto_reply_enable1_u {
+	mmr_t	sh_auto_reply_enable1_regval;
+	struct {
+		mmr_t	enable1     : 64;
+	} sh_auto_reply_enable1_s;
+} sh_auto_reply_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER0"                   */
+/*                 Automatic Maintenance Reply Header 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_header0_u {
+	mmr_t	sh_auto_reply_header0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_auto_reply_header0_s;
+} sh_auto_reply_header0_u_t;
+#else
+typedef union sh_auto_reply_header0_u {
+	mmr_t	sh_auto_reply_header0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_auto_reply_header0_s;
+} sh_auto_reply_header0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER1"                   */
+/*                 Automatic Maintenance Reply Header 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_header1_u {
+	mmr_t	sh_auto_reply_header1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_auto_reply_header1_s;
+} sh_auto_reply_header1_u_t;
+#else
+typedef union sh_auto_reply_header1_u {
+	mmr_t	sh_auto_reply_header1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_auto_reply_header1_s;
+} sh_auto_reply_header1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RP_AUTO_REPLY"                  */
+/*         Enable Automatic Maintenance Reply From Reply Queue          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_enable_rp_auto_reply_u {
+	mmr_t	sh_enable_rp_auto_reply_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_enable_rp_auto_reply_s;
+} sh_enable_rp_auto_reply_u_t;
+#else
+typedef union sh_enable_rp_auto_reply_u {
+	mmr_t	sh_enable_rp_auto_reply_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	enable      : 1;
+	} sh_enable_rp_auto_reply_s;
+} sh_enable_rp_auto_reply_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RQ_AUTO_REPLY"                  */
+/*        Enable Automatic Maintenance Reply From Request Queue         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_enable_rq_auto_reply_u {
+	mmr_t	sh_enable_rq_auto_reply_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_enable_rq_auto_reply_s;
+} sh_enable_rq_auto_reply_u_t;
+#else
+typedef union sh_enable_rq_auto_reply_u {
+	mmr_t	sh_enable_rq_auto_reply_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	enable      : 1;
+	} sh_enable_rq_auto_reply_s;
+} sh_enable_rq_auto_reply_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_REDIRECT_INVAL"                     */
+/*               Redirect invalidate to LB instead of PI                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_redirect_inval_u {
+	mmr_t	sh_redirect_inval_regval;
+	struct {
+		mmr_t	redirect    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_redirect_inval_s;
+} sh_redirect_inval_u_t;
+#else
+typedef union sh_redirect_inval_u {
+	mmr_t	sh_redirect_inval_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	redirect    : 1;
+	} sh_redirect_inval_s;
+} sh_redirect_inval_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_CNTRL"                     */
+/*                 Diagnostic Message Control Register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_cntrl_u {
+	mmr_t	sh_diag_msg_cntrl_regval;
+	struct {
+		mmr_t	msg_length          : 6;
+		mmr_t	error_inject_point  : 6;
+		mmr_t	error_inject_enable : 1;
+		mmr_t	port                : 1;
+		mmr_t	reserved_0          : 48;
+		mmr_t	start               : 1;
+		mmr_t	busy                : 1;
+	} sh_diag_msg_cntrl_s;
+} sh_diag_msg_cntrl_u_t;
+#else
+typedef union sh_diag_msg_cntrl_u {
+	mmr_t	sh_diag_msg_cntrl_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	start               : 1;
+		mmr_t	reserved_0          : 48;
+		mmr_t	port                : 1;
+		mmr_t	error_inject_enable : 1;
+		mmr_t	error_inject_point  : 6;
+		mmr_t	msg_length          : 6;
+	} sh_diag_msg_cntrl_s;
+} sh_diag_msg_cntrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data0l_u {
+	mmr_t	sh_diag_msg_data0l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data0l_s;
+} sh_diag_msg_data0l_u_t;
+#else
+typedef union sh_diag_msg_data0l_u {
+	mmr_t	sh_diag_msg_data0l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data0l_s;
+} sh_diag_msg_data0l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data0u_u {
+	mmr_t	sh_diag_msg_data0u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data0u_s;
+} sh_diag_msg_data0u_u_t;
+#else
+typedef union sh_diag_msg_data0u_u {
+	mmr_t	sh_diag_msg_data0u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data0u_s;
+} sh_diag_msg_data0u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data1l_u {
+	mmr_t	sh_diag_msg_data1l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data1l_s;
+} sh_diag_msg_data1l_u_t;
+#else
+typedef union sh_diag_msg_data1l_u {
+	mmr_t	sh_diag_msg_data1l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data1l_s;
+} sh_diag_msg_data1l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data1u_u {
+	mmr_t	sh_diag_msg_data1u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data1u_s;
+} sh_diag_msg_data1u_u_t;
+#else
+typedef union sh_diag_msg_data1u_u {
+	mmr_t	sh_diag_msg_data1u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data1u_s;
+} sh_diag_msg_data1u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data2l_u {
+	mmr_t	sh_diag_msg_data2l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data2l_s;
+} sh_diag_msg_data2l_u_t;
+#else
+typedef union sh_diag_msg_data2l_u {
+	mmr_t	sh_diag_msg_data2l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data2l_s;
+} sh_diag_msg_data2l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data2u_u {
+	mmr_t	sh_diag_msg_data2u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data2u_s;
+} sh_diag_msg_data2u_u_t;
+#else
+typedef union sh_diag_msg_data2u_u {
+	mmr_t	sh_diag_msg_data2u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data2u_s;
+} sh_diag_msg_data2u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data3l_u {
+	mmr_t	sh_diag_msg_data3l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data3l_s;
+} sh_diag_msg_data3l_u_t;
+#else
+typedef union sh_diag_msg_data3l_u {
+	mmr_t	sh_diag_msg_data3l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data3l_s;
+} sh_diag_msg_data3l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data3u_u {
+	mmr_t	sh_diag_msg_data3u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data3u_s;
+} sh_diag_msg_data3u_u_t;
+#else
+typedef union sh_diag_msg_data3u_u {
+	mmr_t	sh_diag_msg_data3u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data3u_s;
+} sh_diag_msg_data3u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data4l_u {
+	mmr_t	sh_diag_msg_data4l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data4l_s;
+} sh_diag_msg_data4l_u_t;
+#else
+typedef union sh_diag_msg_data4l_u {
+	mmr_t	sh_diag_msg_data4l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data4l_s;
+} sh_diag_msg_data4l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data4u_u {
+	mmr_t	sh_diag_msg_data4u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data4u_s;
+} sh_diag_msg_data4u_u_t;
+#else
+typedef union sh_diag_msg_data4u_u {
+	mmr_t	sh_diag_msg_data4u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data4u_s;
+} sh_diag_msg_data4u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data5l_u {
+	mmr_t	sh_diag_msg_data5l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data5l_s;
+} sh_diag_msg_data5l_u_t;
+#else
+typedef union sh_diag_msg_data5l_u {
+	mmr_t	sh_diag_msg_data5l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data5l_s;
+} sh_diag_msg_data5l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data5u_u {
+	mmr_t	sh_diag_msg_data5u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data5u_s;
+} sh_diag_msg_data5u_u_t;
+#else
+typedef union sh_diag_msg_data5u_u {
+	mmr_t	sh_diag_msg_data5u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data5u_s;
+} sh_diag_msg_data5u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data6l_u {
+	mmr_t	sh_diag_msg_data6l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data6l_s;
+} sh_diag_msg_data6l_u_t;
+#else
+typedef union sh_diag_msg_data6l_u {
+	mmr_t	sh_diag_msg_data6l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data6l_s;
+} sh_diag_msg_data6l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data6u_u {
+	mmr_t	sh_diag_msg_data6u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data6u_s;
+} sh_diag_msg_data6u_u_t;
+#else
+typedef union sh_diag_msg_data6u_u {
+	mmr_t	sh_diag_msg_data6u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data6u_s;
+} sh_diag_msg_data6u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data7l_u {
+	mmr_t	sh_diag_msg_data7l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data7l_s;
+} sh_diag_msg_data7l_u_t;
+#else
+typedef union sh_diag_msg_data7l_u {
+	mmr_t	sh_diag_msg_data7l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data7l_s;
+} sh_diag_msg_data7l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data7u_u {
+	mmr_t	sh_diag_msg_data7u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data7u_s;
+} sh_diag_msg_data7u_u_t;
+#else
+typedef union sh_diag_msg_data7u_u {
+	mmr_t	sh_diag_msg_data7u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data7u_s;
+} sh_diag_msg_data7u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data8l_u {
+	mmr_t	sh_diag_msg_data8l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data8l_s;
+} sh_diag_msg_data8l_u_t;
+#else
+typedef union sh_diag_msg_data8l_u {
+	mmr_t	sh_diag_msg_data8l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data8l_s;
+} sh_diag_msg_data8l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data8u_u {
+	mmr_t	sh_diag_msg_data8u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data8u_s;
+} sh_diag_msg_data8u_u_t;
+#else
+typedef union sh_diag_msg_data8u_u {
+	mmr_t	sh_diag_msg_data8u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data8u_s;
+} sh_diag_msg_data8u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR0"                      */
+/*              Diagnostice Data, lower 64 bits of header               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_hdr0_u {
+	mmr_t	sh_diag_msg_hdr0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_diag_msg_hdr0_s;
+} sh_diag_msg_hdr0_u_t;
+#else
+typedef union sh_diag_msg_hdr0_u {
+	mmr_t	sh_diag_msg_hdr0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_diag_msg_hdr0_s;
+} sh_diag_msg_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR1"                      */
+/*              Diagnostice Data, upper 64 bits of header               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_hdr1_u {
+	mmr_t	sh_diag_msg_hdr1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_diag_msg_hdr1_s;
+} sh_diag_msg_hdr1_u_t;
+#else
+typedef union sh_diag_msg_hdr1_u {
+	mmr_t	sh_diag_msg_hdr1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_diag_msg_hdr1_s;
+} sh_diag_msg_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_DEBUG_SELECT"                      */
+/*                        SHub Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_debug_select_u {
+	mmr_t	sh_debug_select_regval;
+	struct {
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	debug_ii_sel        : 3;
+		mmr_t	sel_ii              : 9;
+		mmr_t	reserved_0          : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_debug_select_s;
+} sh_debug_select_u_t;
+#else
+typedef union sh_debug_select_u {
+	mmr_t	sh_debug_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	reserved_0          : 3;
+		mmr_t	sel_ii              : 9;
+		mmr_t	debug_ii_sel        : 3;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	nibble0_nibble_sel  : 3;
+	} sh_debug_select_s;
+} sh_debug_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TRIGGER_COMPARE_MASK"                  */
+/*                      SHub Trigger Compare Mask                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_compare_mask_u {
+	mmr_t	sh_trigger_compare_mask_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_trigger_compare_mask_s;
+} sh_trigger_compare_mask_u_t;
+#else
+typedef union sh_trigger_compare_mask_u {
+	mmr_t	sh_trigger_compare_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_trigger_compare_mask_s;
+} sh_trigger_compare_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_TRIGGER_COMPARE_PATTERN"                 */
+/*                     SHub Trigger Compare Pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_compare_pattern_u {
+	mmr_t	sh_trigger_compare_pattern_regval;
+	struct {
+		mmr_t	data        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_trigger_compare_pattern_s;
+} sh_trigger_compare_pattern_u_t;
+#else
+typedef union sh_trigger_compare_pattern_u {
+	mmr_t	sh_trigger_compare_pattern_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	data        : 32;
+	} sh_trigger_compare_pattern_s;
+} sh_trigger_compare_pattern_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_TRIGGER_SEL"                       */
+/*                  Trigger select for SHUB debug port                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_sel_u {
+	mmr_t	sh_trigger_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_trigger_sel_s;
+} sh_trigger_sel_u_t;
+#else
+typedef union sh_trigger_sel_u {
+	mmr_t	sh_trigger_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_trigger_sel_s;
+} sh_trigger_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_STOP_CLK_CONTROL"                    */
+/*                          Stop Clock Control                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_stop_clk_control_u {
+	mmr_t	sh_stop_clk_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_stop_clk_control_s;
+} sh_stop_clk_control_u_t;
+#else
+typedef union sh_stop_clk_control_u {
+	mmr_t	sh_stop_clk_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_stop_clk_control_s;
+} sh_stop_clk_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_STOP_CLK_DELAY_PHASE"                  */
+/*                        Stop Clock Delay Phase                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_stop_clk_delay_phase_u {
+	mmr_t	sh_stop_clk_delay_phase_regval;
+	struct {
+		mmr_t	delay       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_stop_clk_delay_phase_s;
+} sh_stop_clk_delay_phase_u_t;
+#else
+typedef union sh_stop_clk_delay_phase_u {
+	mmr_t	sh_stop_clk_delay_phase_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	delay       : 8;
+	} sh_stop_clk_delay_phase_s;
+} sh_stop_clk_delay_phase_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_TSF_ARM_MASK"                      */
+/*                 Trigger sequencing facility arm mask                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_arm_mask_u {
+	mmr_t	sh_tsf_arm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_arm_mask_s;
+} sh_tsf_arm_mask_u_t;
+#else
+typedef union sh_tsf_arm_mask_u {
+	mmr_t	sh_tsf_arm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_arm_mask_s;
+} sh_tsf_arm_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_COUNTER_PRESETS"                   */
+/*             Trigger sequencing facility counter presets              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_counter_presets_u {
+	mmr_t	sh_tsf_counter_presets_regval;
+	struct {
+		mmr_t	count_32    : 32;
+		mmr_t	count_16    : 16;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_8a    : 8;
+	} sh_tsf_counter_presets_s;
+} sh_tsf_counter_presets_u_t;
+#else
+typedef union sh_tsf_counter_presets_u {
+	mmr_t	sh_tsf_counter_presets_regval;
+	struct {
+		mmr_t	count_8a    : 8;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_16    : 16;
+		mmr_t	count_32    : 32;
+	} sh_tsf_counter_presets_s;
+} sh_tsf_counter_presets_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_DECREMENT_CTL"                    */
+/*        Trigger sequencing facility counter decrement control         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_decrement_ctl_u {
+	mmr_t	sh_tsf_decrement_ctl_regval;
+	struct {
+		mmr_t	ctl         : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_tsf_decrement_ctl_s;
+} sh_tsf_decrement_ctl_u_t;
+#else
+typedef union sh_tsf_decrement_ctl_u {
+	mmr_t	sh_tsf_decrement_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	ctl         : 16;
+	} sh_tsf_decrement_ctl_s;
+} sh_tsf_decrement_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DIAG_MSG_CTL"                    */
+/*        Trigger sequencing facility diagnostic message control        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_diag_msg_ctl_u {
+	mmr_t	sh_tsf_diag_msg_ctl_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_diag_msg_ctl_s;
+} sh_tsf_diag_msg_ctl_u_t;
+#else
+typedef union sh_tsf_diag_msg_ctl_u {
+	mmr_t	sh_tsf_diag_msg_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	enable      : 8;
+	} sh_tsf_diag_msg_ctl_s;
+} sh_tsf_diag_msg_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DISARM_MASK"                     */
+/*               Trigger sequencing facility disarm mask                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_disarm_mask_u {
+	mmr_t	sh_tsf_disarm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_disarm_mask_s;
+} sh_tsf_disarm_mask_u_t;
+#else
+typedef union sh_tsf_disarm_mask_u {
+	mmr_t	sh_tsf_disarm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_disarm_mask_s;
+} sh_tsf_disarm_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_TSF_ENABLE_CTL"                     */
+/*          Trigger sequencing facility counter enable control          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_enable_ctl_u {
+	mmr_t	sh_tsf_enable_ctl_regval;
+	struct {
+		mmr_t	ctl         : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_tsf_enable_ctl_s;
+} sh_tsf_enable_ctl_u_t;
+#else
+typedef union sh_tsf_enable_ctl_u {
+	mmr_t	sh_tsf_enable_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	ctl         : 16;
+	} sh_tsf_enable_ctl_s;
+} sh_tsf_enable_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_SOFTWARE_ARM"                    */
+/*               Trigger sequencing facility software arm               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_arm_u {
+	mmr_t	sh_tsf_software_arm_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_arm_s;
+} sh_tsf_software_arm_u_t;
+#else
+typedef union sh_tsf_software_arm_u {
+	mmr_t	sh_tsf_software_arm_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_arm_s;
+} sh_tsf_software_arm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_SOFTWARE_DISARM"                   */
+/*             Trigger sequencing facility software disarm              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_disarm_u {
+	mmr_t	sh_tsf_software_disarm_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_disarm_s;
+} sh_tsf_software_disarm_u_t;
+#else
+typedef union sh_tsf_software_disarm_u {
+	mmr_t	sh_tsf_software_disarm_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_disarm_s;
+} sh_tsf_software_disarm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_TSF_SOFTWARE_TRIGGERED"                 */
+/*            Trigger sequencing facility software triggered            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_triggered_u {
+	mmr_t	sh_tsf_software_triggered_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_triggered_s;
+} sh_tsf_software_triggered_u_t;
+#else
+typedef union sh_tsf_software_triggered_u {
+	mmr_t	sh_tsf_software_triggered_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_triggered_s;
+} sh_tsf_software_triggered_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_TRIGGER_MASK"                    */
+/*               Trigger sequencing facility trigger mask               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_trigger_mask_u {
+	mmr_t	sh_tsf_trigger_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_trigger_mask_s;
+} sh_tsf_trigger_mask_u_t;
+#else
+typedef union sh_tsf_trigger_mask_u {
+	mmr_t	sh_tsf_trigger_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_trigger_mask_s;
+} sh_tsf_trigger_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_VEC_DATA"                        */
+/*                  Vector Write Request Message Data                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_data_u {
+	mmr_t	sh_vec_data_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_data_s;
+} sh_vec_data_u_t;
+#else
+typedef union sh_vec_data_u {
+	mmr_t	sh_vec_data_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_data_s;
+} sh_vec_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_PARMS"                        */
+/*                  Vector Message Parameters Register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_parms_u {
+	mmr_t	sh_vec_parms_regval;
+	struct {
+		mmr_t	type        : 1;
+		mmr_t	ni_port     : 1;
+		mmr_t	reserved_0  : 1;
+		mmr_t	address     : 32;
+		mmr_t	pio_id      : 11;
+		mmr_t	reserved_1  : 16;
+		mmr_t	start       : 1;
+		mmr_t	busy        : 1;
+	} sh_vec_parms_s;
+} sh_vec_parms_u_t;
+#else
+typedef union sh_vec_parms_u {
+	mmr_t	sh_vec_parms_regval;
+	struct {
+		mmr_t	busy        : 1;
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 16;
+		mmr_t	pio_id      : 11;
+		mmr_t	address     : 32;
+		mmr_t	reserved_0  : 1;
+		mmr_t	ni_port     : 1;
+		mmr_t	type        : 1;
+	} sh_vec_parms_s;
+} sh_vec_parms_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_ROUTE"                        */
+/*                     Vector Request Message Route                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_route_u {
+	mmr_t	sh_vec_route_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_route_s;
+} sh_vec_route_u_t;
+#else
+typedef union sh_vec_route_u {
+	mmr_t	sh_vec_route_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_route_s;
+} sh_vec_route_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_CPU_PERM"                        */
+/*                    CPU MMR Access Permission Bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_cpu_perm_u {
+	mmr_t	sh_cpu_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_cpu_perm_s;
+} sh_cpu_perm_u_t;
+#else
+typedef union sh_cpu_perm_u {
+	mmr_t	sh_cpu_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_cpu_perm_s;
+} sh_cpu_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_CPU_PERM_OVR"                      */
+/*                  CPU MMR Access Permission Override                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_cpu_perm_ovr_u {
+	mmr_t	sh_cpu_perm_ovr_regval;
+	struct {
+		mmr_t	override    : 64;
+	} sh_cpu_perm_ovr_s;
+} sh_cpu_perm_ovr_u_t;
+#else
+typedef union sh_cpu_perm_ovr_u {
+	mmr_t	sh_cpu_perm_ovr_regval;
+	struct {
+		mmr_t	override    : 64;
+	} sh_cpu_perm_ovr_s;
+} sh_cpu_perm_ovr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_EXT_IO_PERM"                       */
+/*                External IO MMR Access Permission Bits                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ext_io_perm_u {
+	mmr_t	sh_ext_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_io_perm_s;
+} sh_ext_io_perm_u_t;
+#else
+typedef union sh_ext_io_perm_u {
+	mmr_t	sh_ext_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_io_perm_s;
+} sh_ext_io_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EXT_IOI_ACCESS"                     */
+/*             External IO Interrupt Access Permission Bits             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ext_ioi_access_u {
+	mmr_t	sh_ext_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_ioi_access_s;
+} sh_ext_ioi_access_u_t;
+#else
+typedef union sh_ext_ioi_access_u {
+	mmr_t	sh_ext_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_ioi_access_s;
+} sh_ext_ioi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GC_FIL_CTRL"                       */
+/*                   SHub Global Clock Filter Control                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gc_fil_ctrl_u {
+	mmr_t	sh_gc_fil_ctrl_regval;
+	struct {
+		mmr_t	offset          : 5;
+		mmr_t	reserved_0      : 3;
+		mmr_t	mask_counter    : 12;
+		mmr_t	mask_enable     : 1;
+		mmr_t	reserved_1      : 3;
+		mmr_t	dropout_counter : 10;
+		mmr_t	reserved_2      : 2;
+		mmr_t	dropout_thresh  : 10;
+		mmr_t	reserved_3      : 2;
+		mmr_t	error_counter   : 10;
+		mmr_t	reserved_4      : 6;
+	} sh_gc_fil_ctrl_s;
+} sh_gc_fil_ctrl_u_t;
+#else
+typedef union sh_gc_fil_ctrl_u {
+	mmr_t	sh_gc_fil_ctrl_regval;
+	struct {
+		mmr_t	reserved_4      : 6;
+		mmr_t	error_counter   : 10;
+		mmr_t	reserved_3      : 2;
+		mmr_t	dropout_thresh  : 10;
+		mmr_t	reserved_2      : 2;
+		mmr_t	dropout_counter : 10;
+		mmr_t	reserved_1      : 3;
+		mmr_t	mask_enable     : 1;
+		mmr_t	mask_counter    : 12;
+		mmr_t	reserved_0      : 3;
+		mmr_t	offset          : 5;
+	} sh_gc_fil_ctrl_s;
+} sh_gc_fil_ctrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GC_SRC_CTRL"                       */
+/*                      SHub Global Clock Control                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gc_src_ctrl_u {
+	mmr_t	sh_gc_src_ctrl_regval;
+	struct {
+		mmr_t	enable_counter : 1;
+		mmr_t	reserved_0     : 3;
+		mmr_t	max_count      : 10;
+		mmr_t	reserved_1     : 2;
+		mmr_t	counter        : 10;
+		mmr_t	reserved_2     : 2;
+		mmr_t	toggle_bit     : 1;
+		mmr_t	reserved_3     : 3;
+		mmr_t	source_sel     : 2;
+		mmr_t	reserved_4     : 30;
+	} sh_gc_src_ctrl_s;
+} sh_gc_src_ctrl_u_t;
+#else
+typedef union sh_gc_src_ctrl_u {
+	mmr_t	sh_gc_src_ctrl_regval;
+	struct {
+		mmr_t	reserved_4     : 30;
+		mmr_t	source_sel     : 2;
+		mmr_t	reserved_3     : 3;
+		mmr_t	toggle_bit     : 1;
+		mmr_t	reserved_2     : 2;
+		mmr_t	counter        : 10;
+		mmr_t	reserved_1     : 2;
+		mmr_t	max_count      : 10;
+		mmr_t	reserved_0     : 3;
+		mmr_t	enable_counter : 1;
+	} sh_gc_src_ctrl_s;
+} sh_gc_src_ctrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_HARD_RESET"                       */
+/*                           SHub Hard Reset                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_hard_reset_u {
+	mmr_t	sh_hard_reset_regval;
+	struct {
+		mmr_t	hard_reset  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_hard_reset_s;
+} sh_hard_reset_u_t;
+#else
+typedef union sh_hard_reset_u {
+	mmr_t	sh_hard_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	hard_reset  : 1;
+	} sh_hard_reset_s;
+} sh_hard_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_IO_PERM"                         */
+/*                    II MMR Access Permission Bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_io_perm_u {
+	mmr_t	sh_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_io_perm_s;
+} sh_io_perm_u_t;
+#else
+typedef union sh_io_perm_u {
+	mmr_t	sh_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_io_perm_s;
+} sh_io_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_IOI_ACCESS"                       */
+/*                 II Interrupt Access Permission Bits                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ioi_access_u {
+	mmr_t	sh_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ioi_access_s;
+} sh_ioi_access_u_t;
+#else
+typedef union sh_ioi_access_u {
+	mmr_t	sh_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ioi_access_s;
+} sh_ioi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_access_u {
+	mmr_t	sh_ipi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ipi_access_s;
+} sh_ipi_access_u_t;
+#else
+typedef union sh_ipi_access_u {
+	mmr_t	sh_ipi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ipi_access_s;
+} sh_ipi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_JTAG_CONFIG"                       */
+/*                       SHub JTAG configuration                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_jtag_config_u {
+	mmr_t	sh_jtag_config_regval;
+	struct {
+		mmr_t	md_clk_sel                    : 2;
+		mmr_t	ni_clk_sel                    : 1;
+		mmr_t	ii_clk_sel                    : 2;
+		mmr_t	wrt90_target                  : 14;
+		mmr_t	wrt90_overrider               : 1;
+		mmr_t	wrt90_override                : 1;
+		mmr_t	jtag_mci_reset_delay          : 4;
+		mmr_t	jtag_mci_target               : 14;
+		mmr_t	jtag_mci_override             : 1;
+		mmr_t	fsb_config_ioq_depth          : 1;
+		mmr_t	fsb_config_sample_binit       : 1;
+		mmr_t	fsb_config_enable_bus_parking : 1;
+		mmr_t	fsb_config_clock_ratio        : 5;
+		mmr_t	fsb_config_output_tristate    : 4;
+		mmr_t	fsb_config_enable_bist        : 1;
+		mmr_t	fsb_config_aux                : 2;
+		mmr_t	gtl_config_re                 : 1;
+		mmr_t	reserved_0                    : 8;
+	} sh_jtag_config_s;
+} sh_jtag_config_u_t;
+#else
+typedef union sh_jtag_config_u {
+	mmr_t	sh_jtag_config_regval;
+	struct {
+		mmr_t	reserved_0                    : 8;
+		mmr_t	gtl_config_re                 : 1;
+		mmr_t	fsb_config_aux                : 2;
+		mmr_t	fsb_config_enable_bist        : 1;
+		mmr_t	fsb_config_output_tristate    : 4;
+		mmr_t	fsb_config_clock_ratio        : 5;
+		mmr_t	fsb_config_enable_bus_parking : 1;
+		mmr_t	fsb_config_sample_binit       : 1;
+		mmr_t	fsb_config_ioq_depth          : 1;
+		mmr_t	jtag_mci_override             : 1;
+		mmr_t	jtag_mci_target               : 14;
+		mmr_t	jtag_mci_reset_delay          : 4;
+		mmr_t	wrt90_override                : 1;
+		mmr_t	wrt90_overrider               : 1;
+		mmr_t	wrt90_target                  : 14;
+		mmr_t	ii_clk_sel                    : 2;
+		mmr_t	ni_clk_sel                    : 1;
+		mmr_t	md_clk_sel                    : 2;
+	} sh_jtag_config_s;
+} sh_jtag_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shub_id_u {
+	mmr_t	sh_shub_id_regval;
+	struct {
+		mmr_t	force1        : 1;
+		mmr_t	manufacturer  : 11;
+		mmr_t	part_number   : 16;
+		mmr_t	revision      : 4;
+		mmr_t	node_id       : 11;
+		mmr_t	reserved_0    : 1;
+		mmr_t	sharing_mode  : 2;
+		mmr_t	reserved_1    : 2;
+		mmr_t	nodes_per_bit : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	ni_port       : 1;
+		mmr_t	reserved_3    : 7;
+	} sh_shub_id_s;
+} sh_shub_id_u_t;
+#else
+typedef union sh_shub_id_u {
+	mmr_t	sh_shub_id_regval;
+	struct {
+		mmr_t	reserved_3    : 7;
+		mmr_t	ni_port       : 1;
+		mmr_t	reserved_2    : 3;
+		mmr_t	nodes_per_bit : 5;
+		mmr_t	reserved_1    : 2;
+		mmr_t	sharing_mode  : 2;
+		mmr_t	reserved_0    : 1;
+		mmr_t	node_id       : 11;
+		mmr_t	revision      : 4;
+		mmr_t	part_number   : 16;
+		mmr_t	manufacturer  : 11;
+		mmr_t	force1        : 1;
+	} sh_shub_id_s;
+} sh_shub_id_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT0"                     */
+/*         Shubs 0 - 63 Present. Used for invalidate generation         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present0_u {
+	mmr_t	sh_shubs_present0_regval;
+	struct {
+		mmr_t	shubs_present0 : 64;
+	} sh_shubs_present0_s;
+} sh_shubs_present0_u_t;
+#else
+typedef union sh_shubs_present0_u {
+	mmr_t	sh_shubs_present0_regval;
+	struct {
+		mmr_t	shubs_present0 : 64;
+	} sh_shubs_present0_s;
+} sh_shubs_present0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT1"                     */
+/*        Shubs 64 - 127 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present1_u {
+	mmr_t	sh_shubs_present1_regval;
+	struct {
+		mmr_t	shubs_present1 : 64;
+	} sh_shubs_present1_s;
+} sh_shubs_present1_u_t;
+#else
+typedef union sh_shubs_present1_u {
+	mmr_t	sh_shubs_present1_regval;
+	struct {
+		mmr_t	shubs_present1 : 64;
+	} sh_shubs_present1_s;
+} sh_shubs_present1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT2"                     */
+/*       Shubs 128 - 191 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present2_u {
+	mmr_t	sh_shubs_present2_regval;
+	struct {
+		mmr_t	shubs_present2 : 64;
+	} sh_shubs_present2_s;
+} sh_shubs_present2_u_t;
+#else
+typedef union sh_shubs_present2_u {
+	mmr_t	sh_shubs_present2_regval;
+	struct {
+		mmr_t	shubs_present2 : 64;
+	} sh_shubs_present2_s;
+} sh_shubs_present2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT3"                     */
+/*       Shubs 192 - 255 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present3_u {
+	mmr_t	sh_shubs_present3_regval;
+	struct {
+		mmr_t	shubs_present3 : 64;
+	} sh_shubs_present3_s;
+} sh_shubs_present3_u_t;
+#else
+typedef union sh_shubs_present3_u {
+	mmr_t	sh_shubs_present3_regval;
+	struct {
+		mmr_t	shubs_present3 : 64;
+	} sh_shubs_present3_s;
+} sh_shubs_present3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_SOFT_RESET"                       */
+/*                           SHub Soft Reset                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_soft_reset_u {
+	mmr_t	sh_soft_reset_regval;
+	struct {
+		mmr_t	soft_reset  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_soft_reset_s;
+} sh_soft_reset_u_t;
+#else
+typedef union sh_soft_reset_u {
+	mmr_t	sh_soft_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	soft_reset  : 1;
+	} sh_soft_reset_s;
+} sh_soft_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_FIRST_ERROR"                       */
+/*                    Shub Global First Error Flags                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_first_error_u {
+	mmr_t	sh_first_error_regval;
+	struct {
+		mmr_t	first_error : 19;
+		mmr_t	reserved_0  : 45;
+	} sh_first_error_s;
+} sh_first_error_u_t;
+#else
+typedef union sh_first_error_u {
+	mmr_t	sh_first_error_regval;
+	struct {
+		mmr_t	reserved_0  : 45;
+		mmr_t	first_error : 19;
+	} sh_first_error_s;
+} sh_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_II_HW_TIME_STAMP"                    */
+/*                     II hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_hw_time_stamp_u {
+	mmr_t	sh_ii_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_ii_hw_time_stamp_s;
+} sh_ii_hw_time_stamp_u_t;
+#else
+typedef union sh_ii_hw_time_stamp_u {
+	mmr_t	sh_ii_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_ii_hw_time_stamp_s;
+} sh_ii_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_HW_TIME_STAMP"                    */
+/*                     LB hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_hw_time_stamp_u {
+	mmr_t	sh_lb_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_lb_hw_time_stamp_s;
+} sh_lb_hw_time_stamp_u_t;
+#else
+typedef union sh_lb_hw_time_stamp_u {
+	mmr_t	sh_lb_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_lb_hw_time_stamp_s;
+} sh_lb_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_COR_TIME_STAMP"                    */
+/*                   MD correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_cor_time_stamp_u {
+	mmr_t	sh_md_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_cor_time_stamp_s;
+} sh_md_cor_time_stamp_u_t;
+#else
+typedef union sh_md_cor_time_stamp_u {
+	mmr_t	sh_md_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_cor_time_stamp_s;
+} sh_md_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_HW_TIME_STAMP"                    */
+/*                     MD hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_hw_time_stamp_u {
+	mmr_t	sh_md_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_hw_time_stamp_s;
+} sh_md_hw_time_stamp_u_t;
+#else
+typedef union sh_md_hw_time_stamp_u {
+	mmr_t	sh_md_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_hw_time_stamp_s;
+} sh_md_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_UNCOR_TIME_STAMP"                   */
+/*                  MD uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_uncor_time_stamp_u {
+	mmr_t	sh_md_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_uncor_time_stamp_s;
+} sh_md_uncor_time_stamp_u_t;
+#else
+typedef union sh_md_uncor_time_stamp_u {
+	mmr_t	sh_md_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_uncor_time_stamp_s;
+} sh_md_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_COR_TIME_STAMP"                    */
+/*                   PI correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cor_time_stamp_u {
+	mmr_t	sh_pi_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_cor_time_stamp_s;
+} sh_pi_cor_time_stamp_u_t;
+#else
+typedef union sh_pi_cor_time_stamp_u {
+	mmr_t	sh_pi_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_cor_time_stamp_s;
+} sh_pi_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_HW_TIME_STAMP"                    */
+/*                     PI hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_hw_time_stamp_u {
+	mmr_t	sh_pi_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_hw_time_stamp_s;
+} sh_pi_hw_time_stamp_u_t;
+#else
+typedef union sh_pi_hw_time_stamp_u {
+	mmr_t	sh_pi_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_hw_time_stamp_s;
+} sh_pi_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_UNCOR_TIME_STAMP"                   */
+/*                  PI uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncor_time_stamp_u {
+	mmr_t	sh_pi_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_uncor_time_stamp_s;
+} sh_pi_uncor_time_stamp_u_t;
+#else
+typedef union sh_pi_uncor_time_stamp_u {
+	mmr_t	sh_pi_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_uncor_time_stamp_s;
+} sh_pi_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_TIME_STAMP"                  */
+/*                      Proc 0 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_time_stamp_u {
+	mmr_t	sh_proc0_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc0_adv_time_stamp_s;
+} sh_proc0_adv_time_stamp_u_t;
+#else
+typedef union sh_proc0_adv_time_stamp_u {
+	mmr_t	sh_proc0_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc0_adv_time_stamp_s;
+} sh_proc0_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_TIME_STAMP"                  */
+/*                       Proc 0 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_time_stamp_u {
+	mmr_t	sh_proc0_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc0_err_time_stamp_s;
+} sh_proc0_err_time_stamp_u_t;
+#else
+typedef union sh_proc0_err_time_stamp_u {
+	mmr_t	sh_proc0_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc0_err_time_stamp_s;
+} sh_proc0_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_TIME_STAMP"                  */
+/*                      Proc 1 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_time_stamp_u {
+	mmr_t	sh_proc1_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc1_adv_time_stamp_s;
+} sh_proc1_adv_time_stamp_u_t;
+#else
+typedef union sh_proc1_adv_time_stamp_u {
+	mmr_t	sh_proc1_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc1_adv_time_stamp_s;
+} sh_proc1_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_TIME_STAMP"                  */
+/*                       Proc 1 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_time_stamp_u {
+	mmr_t	sh_proc1_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc1_err_time_stamp_s;
+} sh_proc1_err_time_stamp_u_t;
+#else
+typedef union sh_proc1_err_time_stamp_u {
+	mmr_t	sh_proc1_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc1_err_time_stamp_s;
+} sh_proc1_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_TIME_STAMP"                  */
+/*                      Proc 2 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_time_stamp_u {
+	mmr_t	sh_proc2_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc2_adv_time_stamp_s;
+} sh_proc2_adv_time_stamp_u_t;
+#else
+typedef union sh_proc2_adv_time_stamp_u {
+	mmr_t	sh_proc2_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc2_adv_time_stamp_s;
+} sh_proc2_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_TIME_STAMP"                  */
+/*                       Proc 2 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_time_stamp_u {
+	mmr_t	sh_proc2_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc2_err_time_stamp_s;
+} sh_proc2_err_time_stamp_u_t;
+#else
+typedef union sh_proc2_err_time_stamp_u {
+	mmr_t	sh_proc2_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc2_err_time_stamp_s;
+} sh_proc2_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_TIME_STAMP"                  */
+/*                      Proc 3 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_time_stamp_u {
+	mmr_t	sh_proc3_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc3_adv_time_stamp_s;
+} sh_proc3_adv_time_stamp_u_t;
+#else
+typedef union sh_proc3_adv_time_stamp_u {
+	mmr_t	sh_proc3_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc3_adv_time_stamp_s;
+} sh_proc3_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_TIME_STAMP"                  */
+/*                       Proc 3 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_time_stamp_u {
+	mmr_t	sh_proc3_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc3_err_time_stamp_s;
+} sh_proc3_err_time_stamp_u_t;
+#else
+typedef union sh_proc3_err_time_stamp_u {
+	mmr_t	sh_proc3_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc3_err_time_stamp_s;
+} sh_proc3_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_COR_TIME_STAMP"                    */
+/*                   XN correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_cor_time_stamp_u {
+	mmr_t	sh_xn_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_cor_time_stamp_s;
+} sh_xn_cor_time_stamp_u_t;
+#else
+typedef union sh_xn_cor_time_stamp_u {
+	mmr_t	sh_xn_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_cor_time_stamp_s;
+} sh_xn_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_HW_TIME_STAMP"                    */
+/*                     XN hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_hw_time_stamp_u {
+	mmr_t	sh_xn_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_hw_time_stamp_s;
+} sh_xn_hw_time_stamp_u_t;
+#else
+typedef union sh_xn_hw_time_stamp_u {
+	mmr_t	sh_xn_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_hw_time_stamp_s;
+} sh_xn_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_UNCOR_TIME_STAMP"                   */
+/*                  XN uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncor_time_stamp_u {
+	mmr_t	sh_xn_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_uncor_time_stamp_s;
+} sh_xn_uncor_time_stamp_u_t;
+#else
+typedef union sh_xn_uncor_time_stamp_u {
+	mmr_t	sh_xn_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_uncor_time_stamp_s;
+} sh_xn_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_DEBUG_PORT"                       */
+/*                           SHub Debug Port                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_debug_port_u {
+	mmr_t	sh_debug_port_regval;
+	struct {
+		mmr_t	debug_nibble0 : 4;
+		mmr_t	debug_nibble1 : 4;
+		mmr_t	debug_nibble2 : 4;
+		mmr_t	debug_nibble3 : 4;
+		mmr_t	debug_nibble4 : 4;
+		mmr_t	debug_nibble5 : 4;
+		mmr_t	debug_nibble6 : 4;
+		mmr_t	debug_nibble7 : 4;
+		mmr_t	reserved_0    : 32;
+	} sh_debug_port_s;
+} sh_debug_port_u_t;
+#else
+typedef union sh_debug_port_u {
+	mmr_t	sh_debug_port_regval;
+	struct {
+		mmr_t	reserved_0    : 32;
+		mmr_t	debug_nibble7 : 4;
+		mmr_t	debug_nibble6 : 4;
+		mmr_t	debug_nibble5 : 4;
+		mmr_t	debug_nibble4 : 4;
+		mmr_t	debug_nibble3 : 4;
+		mmr_t	debug_nibble2 : 4;
+		mmr_t	debug_nibble1 : 4;
+		mmr_t	debug_nibble0 : 4;
+	} sh_debug_port_s;
+} sh_debug_port_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_DEBUG_DATA"                      */
+/*                            II Debug Data                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_debug_data_u {
+	mmr_t	sh_ii_debug_data_regval;
+	struct {
+		mmr_t	ii_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_ii_debug_data_s;
+} sh_ii_debug_data_u_t;
+#else
+typedef union sh_ii_debug_data_u {
+	mmr_t	sh_ii_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	ii_data     : 32;
+	} sh_ii_debug_data_s;
+} sh_ii_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_II_WRAP_DEBUG_DATA"                   */
+/*                      SHub II Wrapper Debug Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_wrap_debug_data_u {
+	mmr_t	sh_ii_wrap_debug_data_regval;
+	struct {
+		mmr_t	ii_wrap_data : 32;
+		mmr_t	reserved_0   : 32;
+	} sh_ii_wrap_debug_data_s;
+} sh_ii_wrap_debug_data_u_t;
+#else
+typedef union sh_ii_wrap_debug_data_u {
+	mmr_t	sh_ii_wrap_debug_data_regval;
+	struct {
+		mmr_t	reserved_0   : 32;
+		mmr_t	ii_wrap_data : 32;
+	} sh_ii_wrap_debug_data_s;
+} sh_ii_wrap_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_DEBUG_DATA"                      */
+/*                          SHub LB Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_data_u {
+	mmr_t	sh_lb_debug_data_regval;
+	struct {
+		mmr_t	lb_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_lb_debug_data_s;
+} sh_lb_debug_data_u_t;
+#else
+typedef union sh_lb_debug_data_u {
+	mmr_t	sh_lb_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	lb_data     : 32;
+	} sh_lb_debug_data_s;
+} sh_lb_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_DEBUG_DATA"                      */
+/*                          SHub MD Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_debug_data_u {
+	mmr_t	sh_md_debug_data_regval;
+	struct {
+		mmr_t	md_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_md_debug_data_s;
+} sh_md_debug_data_u_t;
+#else
+typedef union sh_md_debug_data_u {
+	mmr_t	sh_md_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	md_data     : 32;
+	} sh_md_debug_data_s;
+} sh_md_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_DEBUG_DATA"                      */
+/*                          SHub PI Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_debug_data_u {
+	mmr_t	sh_pi_debug_data_regval;
+	struct {
+		mmr_t	pi_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_pi_debug_data_s;
+} sh_pi_debug_data_u_t;
+#else
+typedef union sh_pi_debug_data_u {
+	mmr_t	sh_pi_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	pi_data     : 32;
+	} sh_pi_debug_data_s;
+} sh_pi_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_DEBUG_DATA"                      */
+/*                          SHub XN Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_data_u {
+	mmr_t	sh_xn_debug_data_regval;
+	struct {
+		mmr_t	xn_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_xn_debug_data_s;
+} sh_xn_debug_data_u_t;
+#else
+typedef union sh_xn_debug_data_u {
+	mmr_t	sh_xn_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	xn_data     : 32;
+	} sh_xn_debug_data_s;
+} sh_xn_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_ARMED_STATE"                     */
+/*                Trigger sequencing facility arm state                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_armed_state_u {
+	mmr_t	sh_tsf_armed_state_regval;
+	struct {
+		mmr_t	state       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_armed_state_s;
+} sh_tsf_armed_state_u_t;
+#else
+typedef union sh_tsf_armed_state_u {
+	mmr_t	sh_tsf_armed_state_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	state       : 8;
+	} sh_tsf_armed_state_s;
+} sh_tsf_armed_state_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_COUNTER_VALUE"                    */
+/*              Trigger sequencing facility counter value               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_counter_value_u {
+	mmr_t	sh_tsf_counter_value_regval;
+	struct {
+		mmr_t	count_32    : 32;
+		mmr_t	count_16    : 16;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_8a    : 8;
+	} sh_tsf_counter_value_s;
+} sh_tsf_counter_value_u_t;
+#else
+typedef union sh_tsf_counter_value_u {
+	mmr_t	sh_tsf_counter_value_regval;
+	struct {
+		mmr_t	count_8a    : 8;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_16    : 16;
+		mmr_t	count_32    : 32;
+	} sh_tsf_counter_value_s;
+} sh_tsf_counter_value_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_TRIGGERED_STATE"                   */
+/*             Trigger sequencing facility triggered state              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_triggered_state_u {
+	mmr_t	sh_tsf_triggered_state_regval;
+	struct {
+		mmr_t	state       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_triggered_state_s;
+} sh_tsf_triggered_state_u_t;
+#else
+typedef union sh_tsf_triggered_state_u {
+	mmr_t	sh_tsf_triggered_state_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	state       : 8;
+	} sh_tsf_triggered_state_s;
+} sh_tsf_triggered_state_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RDDATA"                       */
+/*                      Vector Reply Message Data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_rddata_u {
+	mmr_t	sh_vec_rddata_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_rddata_s;
+} sh_vec_rddata_u_t;
+#else
+typedef union sh_vec_rddata_u {
+	mmr_t	sh_vec_rddata_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_rddata_s;
+} sh_vec_rddata_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RETURN"                       */
+/*                  Vector Reply Message Return Route                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_return_u {
+	mmr_t	sh_vec_return_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_return_s;
+} sh_vec_return_u_t;
+#else
+typedef union sh_vec_return_u {
+	mmr_t	sh_vec_return_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_return_s;
+} sh_vec_return_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_STATUS"                       */
+/*                     Vector Reply Message Status                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_status_u {
+	mmr_t	sh_vec_status_regval;
+	struct {
+		mmr_t	type         : 3;
+		mmr_t	address      : 32;
+		mmr_t	pio_id       : 11;
+		mmr_t	source       : 14;
+		mmr_t	reserved_0   : 2;
+		mmr_t	overrun      : 1;
+		mmr_t	status_valid : 1;
+	} sh_vec_status_s;
+} sh_vec_status_u_t;
+#else
+typedef union sh_vec_status_u {
+	mmr_t	sh_vec_status_regval;
+	struct {
+		mmr_t	status_valid : 1;
+		mmr_t	overrun      : 1;
+		mmr_t	reserved_0   : 2;
+		mmr_t	source       : 14;
+		mmr_t	pio_id       : 11;
+		mmr_t	address      : 32;
+		mmr_t	type         : 3;
+	} sh_vec_status_s;
+} sh_vec_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT0_CONTROL"               */
+/*                    Performance Counter 0 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count0_control_u {
+	mmr_t	sh_performance_count0_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count0_control_s;
+} sh_performance_count0_control_u_t;
+#else
+typedef union sh_performance_count0_control_u {
+	mmr_t	sh_performance_count0_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count0_control_s;
+} sh_performance_count0_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT1_CONTROL"               */
+/*                    Performance Counter 1 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count1_control_u {
+	mmr_t	sh_performance_count1_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count1_control_s;
+} sh_performance_count1_control_u_t;
+#else
+typedef union sh_performance_count1_control_u {
+	mmr_t	sh_performance_count1_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count1_control_s;
+} sh_performance_count1_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT2_CONTROL"               */
+/*                    Performance Counter 2 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count2_control_u {
+	mmr_t	sh_performance_count2_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count2_control_s;
+} sh_performance_count2_control_u_t;
+#else
+typedef union sh_performance_count2_control_u {
+	mmr_t	sh_performance_count2_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count2_control_s;
+} sh_performance_count2_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT3_CONTROL"               */
+/*                    Performance Counter 3 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count3_control_u {
+	mmr_t	sh_performance_count3_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count3_control_s;
+} sh_performance_count3_control_u_t;
+#else
+typedef union sh_performance_count3_control_u {
+	mmr_t	sh_performance_count3_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count3_control_s;
+} sh_performance_count3_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT4_CONTROL"               */
+/*                    Performance Counter 4 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count4_control_u {
+	mmr_t	sh_performance_count4_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count4_control_s;
+} sh_performance_count4_control_u_t;
+#else
+typedef union sh_performance_count4_control_u {
+	mmr_t	sh_performance_count4_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count4_control_s;
+} sh_performance_count4_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT5_CONTROL"               */
+/*                    Performance Counter 5 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count5_control_u {
+	mmr_t	sh_performance_count5_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count5_control_s;
+} sh_performance_count5_control_u_t;
+#else
+typedef union sh_performance_count5_control_u {
+	mmr_t	sh_performance_count5_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count5_control_s;
+} sh_performance_count5_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT6_CONTROL"               */
+/*                    Performance Counter 6 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count6_control_u {
+	mmr_t	sh_performance_count6_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count6_control_s;
+} sh_performance_count6_control_u_t;
+#else
+typedef union sh_performance_count6_control_u {
+	mmr_t	sh_performance_count6_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count6_control_s;
+} sh_performance_count6_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT7_CONTROL"               */
+/*                    Performance Counter 7 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count7_control_u {
+	mmr_t	sh_performance_count7_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count7_control_s;
+} sh_performance_count7_control_u_t;
+#else
+typedef union sh_performance_count7_control_u {
+	mmr_t	sh_performance_count7_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count7_control_s;
+} sh_performance_count7_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_DN_CONTROL"                   */
+/*                     Profile Counter Down Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_dn_control_u {
+	mmr_t	sh_profile_dn_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_dn_control_s;
+} sh_profile_dn_control_u_t;
+#else
+typedef union sh_profile_dn_control_u {
+	mmr_t	sh_profile_dn_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_profile_dn_control_s;
+} sh_profile_dn_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROFILE_PEAK_CONTROL"                  */
+/*                     Profile Counter Peak Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_peak_control_u {
+	mmr_t	sh_profile_peak_control_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	stimulus    : 1;
+		mmr_t	reserved_1  : 1;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	reserved_2  : 57;
+	} sh_profile_peak_control_s;
+} sh_profile_peak_control_u_t;
+#else
+typedef union sh_profile_peak_control_u {
+	mmr_t	sh_profile_peak_control_regval;
+	struct {
+		mmr_t	reserved_2  : 57;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	reserved_1  : 1;
+		mmr_t	stimulus    : 1;
+		mmr_t	reserved_0  : 3;
+	} sh_profile_peak_control_s;
+} sh_profile_peak_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PROFILE_RANGE"                      */
+/*                        Profile Counter Range                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_range_u {
+	mmr_t	sh_profile_range_regval;
+	struct {
+		mmr_t	range0      : 8;
+		mmr_t	range1      : 8;
+		mmr_t	range2      : 8;
+		mmr_t	range3      : 8;
+		mmr_t	range4      : 8;
+		mmr_t	range5      : 8;
+		mmr_t	range6      : 8;
+		mmr_t	range7      : 8;
+	} sh_profile_range_s;
+} sh_profile_range_u_t;
+#else
+typedef union sh_profile_range_u {
+	mmr_t	sh_profile_range_regval;
+	struct {
+		mmr_t	range7      : 8;
+		mmr_t	range6      : 8;
+		mmr_t	range5      : 8;
+		mmr_t	range4      : 8;
+		mmr_t	range3      : 8;
+		mmr_t	range2      : 8;
+		mmr_t	range1      : 8;
+		mmr_t	range0      : 8;
+	} sh_profile_range_s;
+} sh_profile_range_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_UP_CONTROL"                   */
+/*                      Profile Counter Up Control                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_up_control_u {
+	mmr_t	sh_profile_up_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_up_control_s;
+} sh_profile_up_control_u_t;
+#else
+typedef union sh_profile_up_control_u {
+	mmr_t	sh_profile_up_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_profile_up_control_s;
+} sh_profile_up_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER0"                  */
+/*                        Performance Counter 0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter0_u {
+	mmr_t	sh_performance_counter0_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter0_s;
+} sh_performance_counter0_u_t;
+#else
+typedef union sh_performance_counter0_u {
+	mmr_t	sh_performance_counter0_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter0_s;
+} sh_performance_counter0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER1"                  */
+/*                        Performance Counter 1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter1_u {
+	mmr_t	sh_performance_counter1_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter1_s;
+} sh_performance_counter1_u_t;
+#else
+typedef union sh_performance_counter1_u {
+	mmr_t	sh_performance_counter1_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter1_s;
+} sh_performance_counter1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER2"                  */
+/*                        Performance Counter 2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter2_u {
+	mmr_t	sh_performance_counter2_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter2_s;
+} sh_performance_counter2_u_t;
+#else
+typedef union sh_performance_counter2_u {
+	mmr_t	sh_performance_counter2_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter2_s;
+} sh_performance_counter2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER3"                  */
+/*                        Performance Counter 3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter3_u {
+	mmr_t	sh_performance_counter3_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter3_s;
+} sh_performance_counter3_u_t;
+#else
+typedef union sh_performance_counter3_u {
+	mmr_t	sh_performance_counter3_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter3_s;
+} sh_performance_counter3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER4"                  */
+/*                        Performance Counter 4                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter4_u {
+	mmr_t	sh_performance_counter4_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter4_s;
+} sh_performance_counter4_u_t;
+#else
+typedef union sh_performance_counter4_u {
+	mmr_t	sh_performance_counter4_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter4_s;
+} sh_performance_counter4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER5"                  */
+/*                        Performance Counter 5                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter5_u {
+	mmr_t	sh_performance_counter5_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter5_s;
+} sh_performance_counter5_u_t;
+#else
+typedef union sh_performance_counter5_u {
+	mmr_t	sh_performance_counter5_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter5_s;
+} sh_performance_counter5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER6"                  */
+/*                        Performance Counter 6                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter6_u {
+	mmr_t	sh_performance_counter6_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter6_s;
+} sh_performance_counter6_u_t;
+#else
+typedef union sh_performance_counter6_u {
+	mmr_t	sh_performance_counter6_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter6_s;
+} sh_performance_counter6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER7"                  */
+/*                        Performance Counter 7                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter7_u {
+	mmr_t	sh_performance_counter7_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter7_s;
+} sh_performance_counter7_u_t;
+#else
+typedef union sh_performance_counter7_u {
+	mmr_t	sh_performance_counter7_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter7_s;
+} sh_performance_counter7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PROFILE_COUNTER"                     */
+/*                           Profile Counter                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_counter_u {
+	mmr_t	sh_profile_counter_regval;
+	struct {
+		mmr_t	counter     : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_counter_s;
+} sh_profile_counter_u_t;
+#else
+typedef union sh_profile_counter_u {
+	mmr_t	sh_profile_counter_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	counter     : 8;
+	} sh_profile_counter_s;
+} sh_profile_counter_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_PROFILE_PEAK"                      */
+/*                         Profile Peak Counter                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_peak_u {
+	mmr_t	sh_profile_peak_regval;
+	struct {
+		mmr_t	counter     : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_peak_s;
+} sh_profile_peak_u_t;
+#else
+typedef union sh_profile_peak_u {
+	mmr_t	sh_profile_peak_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	counter     : 8;
+	} sh_profile_peak_s;
+} sh_profile_peak_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_0"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_0_u {
+	mmr_t	sh_ptc_0_regval;
+	struct {
+		mmr_t	a           : 1;
+		mmr_t	reserved_0  : 1;
+		mmr_t	ps          : 6;
+		mmr_t	rid         : 24;
+		mmr_t	reserved_1  : 31;
+		mmr_t	start       : 1;
+	} sh_ptc_0_s;
+} sh_ptc_0_u_t;
+#else
+typedef union sh_ptc_0_u {
+	mmr_t	sh_ptc_0_regval;
+	struct {
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 31;
+		mmr_t	rid         : 24;
+		mmr_t	ps          : 6;
+		mmr_t	reserved_0  : 1;
+		mmr_t	a           : 1;
+	} sh_ptc_0_s;
+} sh_ptc_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_1"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_1_u {
+	mmr_t	sh_ptc_1_regval;
+	struct {
+		mmr_t	reserved_0  : 12;
+		mmr_t	vpn         : 49;
+		mmr_t	reserved_1  : 2;
+		mmr_t	start       : 1;
+	} sh_ptc_1_s;
+} sh_ptc_1_u_t;
+#else
+typedef union sh_ptc_1_u {
+	mmr_t	sh_ptc_1_regval;
+	struct {
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	vpn         : 49;
+		mmr_t	reserved_0  : 12;
+	} sh_ptc_1_s;
+} sh_ptc_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_PTC_PARMS"                        */
+/*                       PTC Time-out parmaeters                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_parms_u {
+	mmr_t	sh_ptc_parms_regval;
+	struct {
+		mmr_t	ptc_to_wrap : 24;
+		mmr_t	ptc_to_val  : 12;
+		mmr_t	reserved_0  : 28;
+	} sh_ptc_parms_s;
+} sh_ptc_parms_u_t;
+#else
+typedef union sh_ptc_parms_u {
+	mmr_t	sh_ptc_parms_regval;
+	struct {
+		mmr_t	reserved_0  : 28;
+		mmr_t	ptc_to_val  : 12;
+		mmr_t	ptc_to_wrap : 24;
+	} sh_ptc_parms_s;
+} sh_ptc_parms_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPA"                        */
+/*                  RTC Compare Value for Processor A                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpa_u {
+	mmr_t	sh_int_cmpa_regval;
+	struct {
+		mmr_t	real_time_cmpa : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpa_s;
+} sh_int_cmpa_u_t;
+#else
+typedef union sh_int_cmpa_u {
+	mmr_t	sh_int_cmpa_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpa : 55;
+	} sh_int_cmpa_s;
+} sh_int_cmpa_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpb_u {
+	mmr_t	sh_int_cmpb_regval;
+	struct {
+		mmr_t	real_time_cmpb : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpb_s;
+} sh_int_cmpb_u_t;
+#else
+typedef union sh_int_cmpb_u {
+	mmr_t	sh_int_cmpb_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpb : 55;
+	} sh_int_cmpb_s;
+} sh_int_cmpb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpc_u {
+	mmr_t	sh_int_cmpc_regval;
+	struct {
+		mmr_t	real_time_cmpc : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpc_s;
+} sh_int_cmpc_u_t;
+#else
+typedef union sh_int_cmpc_u {
+	mmr_t	sh_int_cmpc_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpc : 55;
+	} sh_int_cmpc_s;
+} sh_int_cmpc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpd_u {
+	mmr_t	sh_int_cmpd_regval;
+	struct {
+		mmr_t	real_time_cmpd : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpd_s;
+} sh_int_cmpd_u_t;
+#else
+typedef union sh_int_cmpd_u {
+	mmr_t	sh_int_cmpd_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpd : 55;
+	} sh_int_cmpd_s;
+} sh_int_cmpd_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_PROF"                        */
+/*                      Profile Compare Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_prof_u {
+	mmr_t	sh_int_prof_regval;
+	struct {
+		mmr_t	profile_compare : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_int_prof_s;
+} sh_int_prof_u_t;
+#else
+typedef union sh_int_prof_u {
+	mmr_t	sh_int_prof_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	profile_compare : 32;
+	} sh_int_prof_s;
+} sh_int_prof_u_t;
+#endif
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc_u {
+	mmr_t	sh_rtc_regval;
+	struct {
+		mmr_t	real_time_clock : 55;
+		mmr_t	reserved_0      : 9;
+	} sh_rtc_s;
+} sh_rtc_u_t;
+#else
+typedef union sh_rtc_u {
+	mmr_t	sh_rtc_regval;
+	struct {
+		mmr_t	reserved_0      : 9;
+		mmr_t	real_time_clock : 55;
+	} sh_rtc_s;
+} sh_rtc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH0"                        */
+/*                          Scratch Register 0                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch0_u {
+	mmr_t	sh_scratch0_regval;
+	struct {
+		mmr_t	scratch0    : 64;
+	} sh_scratch0_s;
+} sh_scratch0_u_t;
+#else
+typedef union sh_scratch0_u {
+	mmr_t	sh_scratch0_regval;
+	struct {
+		mmr_t	scratch0    : 64;
+	} sh_scratch0_s;
+} sh_scratch0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH1"                        */
+/*                          Scratch Register 1                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch1_u {
+	mmr_t	sh_scratch1_regval;
+	struct {
+		mmr_t	scratch1    : 64;
+	} sh_scratch1_s;
+} sh_scratch1_u_t;
+#else
+typedef union sh_scratch1_u {
+	mmr_t	sh_scratch1_regval;
+	struct {
+		mmr_t	scratch1    : 64;
+	} sh_scratch1_s;
+} sh_scratch1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH2"                        */
+/*                          Scratch Register 2                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch2_u {
+	mmr_t	sh_scratch2_regval;
+	struct {
+		mmr_t	scratch2    : 64;
+	} sh_scratch2_s;
+} sh_scratch2_u_t;
+#else
+typedef union sh_scratch2_u {
+	mmr_t	sh_scratch2_regval;
+	struct {
+		mmr_t	scratch2    : 64;
+	} sh_scratch2_s;
+} sh_scratch2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH3"                        */
+/*                          Scratch Register 3                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch3_u {
+	mmr_t	sh_scratch3_regval;
+	struct {
+		mmr_t	scratch3    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_scratch3_s;
+} sh_scratch3_u_t;
+#else
+typedef union sh_scratch3_u {
+	mmr_t	sh_scratch3_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	scratch3    : 1;
+	} sh_scratch3_s;
+} sh_scratch3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH4"                        */
+/*                          Scratch Register 4                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch4_u {
+	mmr_t	sh_scratch4_regval;
+	struct {
+		mmr_t	scratch4    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_scratch4_s;
+} sh_scratch4_u_t;
+#else
+typedef union sh_scratch4_u {
+	mmr_t	sh_scratch4_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	scratch4    : 1;
+	} sh_scratch4_s;
+} sh_scratch4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_MESSAGE_CONTROL"                   */
+/*               Coherent Request Buffer Message Control                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_message_control_u {
+	mmr_t	sh_crb_message_control_regval;
+	struct {
+		mmr_t	system_coherence_enable           : 1;
+		mmr_t	local_speculative_message_enable  : 1;
+		mmr_t	remote_speculative_message_enable : 1;
+		mmr_t	message_color                     : 1;
+		mmr_t	message_color_enable              : 1;
+		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	suppress_bogus_writes             : 1;
+		mmr_t	enable_ivack_consolidation        : 1;
+		mmr_t	reserved_0                        : 20;
+		mmr_t	ivack_stall_count                 : 16;
+		mmr_t	ivack_throttle_control            : 16;
+	} sh_crb_message_control_s;
+} sh_crb_message_control_u_t;
+#else
+typedef union sh_crb_message_control_u {
+	mmr_t	sh_crb_message_control_regval;
+	struct {
+		mmr_t	ivack_throttle_control            : 16;
+		mmr_t	ivack_stall_count                 : 16;
+		mmr_t	reserved_0                        : 20;
+		mmr_t	enable_ivack_consolidation        : 1;
+		mmr_t	suppress_bogus_writes             : 1;
+		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	message_color_enable              : 1;
+		mmr_t	message_color                     : 1;
+		mmr_t	remote_speculative_message_enable : 1;
+		mmr_t	local_speculative_message_enable  : 1;
+		mmr_t	system_coherence_enable           : 1;
+	} sh_crb_message_control_s;
+} sh_crb_message_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_CRB_NACK_LIMIT"                     */
+/*                            CRB Nack Limit                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_nack_limit_u {
+	mmr_t	sh_crb_nack_limit_regval;
+	struct {
+		mmr_t	limit       : 12;
+		mmr_t	pri_freq    : 4;
+		mmr_t	reserved_0  : 47;
+		mmr_t	enable      : 1;
+	} sh_crb_nack_limit_s;
+} sh_crb_nack_limit_u_t;
+#else
+typedef union sh_crb_nack_limit_u {
+	mmr_t	sh_crb_nack_limit_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 47;
+		mmr_t	pri_freq    : 4;
+		mmr_t	limit       : 12;
+	} sh_crb_nack_limit_s;
+} sh_crb_nack_limit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_TIMEOUT_PRESCALE"                  */
+/*               Coherent Request Buffer Timeout Prescale               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_timeout_prescale_u {
+	mmr_t	sh_crb_timeout_prescale_regval;
+	struct {
+		mmr_t	scaling_factor : 32;
+		mmr_t	reserved_0     : 32;
+	} sh_crb_timeout_prescale_s;
+} sh_crb_timeout_prescale_u_t;
+#else
+typedef union sh_crb_timeout_prescale_u {
+	mmr_t	sh_crb_timeout_prescale_regval;
+	struct {
+		mmr_t	reserved_0     : 32;
+		mmr_t	scaling_factor : 32;
+	} sh_crb_timeout_prescale_s;
+} sh_crb_timeout_prescale_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_CRB_TIMEOUT_SKID"                    */
+/*              Coherent Request Buffer Timeout Skid Limit              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_timeout_skid_u {
+	mmr_t	sh_crb_timeout_skid_regval;
+	struct {
+		mmr_t	skid             : 6;
+		mmr_t	reserved_0       : 57;
+		mmr_t	reset_skid_count : 1;
+	} sh_crb_timeout_skid_s;
+} sh_crb_timeout_skid_u_t;
+#else
+typedef union sh_crb_timeout_skid_u {
+	mmr_t	sh_crb_timeout_skid_regval;
+	struct {
+		mmr_t	reset_skid_count : 1;
+		mmr_t	reserved_0       : 57;
+		mmr_t	skid             : 6;
+	} sh_crb_timeout_skid_s;
+} sh_crb_timeout_skid_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_0"                  */
+/*                    Memory Write Status for CPU 0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_0_u {
+	mmr_t	sh_memory_write_status_0_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 58;
+	} sh_memory_write_status_0_s;
+} sh_memory_write_status_0_u_t;
+#else
+typedef union sh_memory_write_status_0_u {
+	mmr_t	sh_memory_write_status_0_regval;
+	struct {
+		mmr_t	reserved_0          : 58;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_0_s;
+} sh_memory_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_1"                  */
+/*                    Memory Write Status for CPU 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_1_u {
+	mmr_t	sh_memory_write_status_1_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 58;
+	} sh_memory_write_status_1_s;
+} sh_memory_write_status_1_u_t;
+#else
+typedef union sh_memory_write_status_1_u {
+	mmr_t	sh_memory_write_status_1_regval;
+	struct {
+		mmr_t	reserved_0          : 58;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_1_s;
+} sh_memory_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0"                   */
+/*                      PIO Write Status for CPU 0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_write_status_0_u {
+	mmr_t	sh_pio_write_status_0_regval;
+	struct {
+		mmr_t	multi_write_error   : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	write_error         : 1;
+		mmr_t	write_error_address : 47;
+		mmr_t	reserved_0          : 6;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_1          : 1;
+		mmr_t	writes_ok           : 1;
+	} sh_pio_write_status_0_s;
+} sh_pio_write_status_0_u_t;
+#else
+typedef union sh_pio_write_status_0_u {
+	mmr_t	sh_pio_write_status_0_regval;
+	struct {
+		mmr_t	writes_ok           : 1;
+		mmr_t	reserved_1          : 1;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 6;
+		mmr_t	write_error_address : 47;
+		mmr_t	write_error         : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	multi_write_error   : 1;
+	} sh_pio_write_status_0_s;
+} sh_pio_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_1"                   */
+/*                      PIO Write Status for CPU 1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_write_status_1_u {
+	mmr_t	sh_pio_write_status_1_regval;
+	struct {
+		mmr_t	multi_write_error   : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	write_error         : 1;
+		mmr_t	write_error_address : 47;
+		mmr_t	reserved_0          : 6;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_1          : 1;
+		mmr_t	writes_ok           : 1;
+	} sh_pio_write_status_1_s;
+} sh_pio_write_status_1_u_t;
+#else
+typedef union sh_pio_write_status_1_u {
+	mmr_t	sh_pio_write_status_1_regval;
+	struct {
+		mmr_t	writes_ok           : 1;
+		mmr_t	reserved_1          : 1;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 6;
+		mmr_t	write_error_address : 47;
+		mmr_t	write_error         : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	multi_write_error   : 1;
+	} sh_pio_write_status_1_s;
+} sh_pio_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_0"             */
+/*            Memory Write Status for CPU 0. OS access only             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_non_user_0_u {
+	mmr_t	sh_memory_write_status_non_user_0_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 57;
+		mmr_t	clear               : 1;
+	} sh_memory_write_status_non_user_0_s;
+} sh_memory_write_status_non_user_0_u_t;
+#else
+typedef union sh_memory_write_status_non_user_0_u {
+	mmr_t	sh_memory_write_status_non_user_0_regval;
+	struct {
+		mmr_t	clear               : 1;
+		mmr_t	reserved_0          : 57;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_non_user_0_s;
+} sh_memory_write_status_non_user_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_1"             */
+/*            Memory Write Status for CPU 1. OS access only             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_non_user_1_u {
+	mmr_t	sh_memory_write_status_non_user_1_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 57;
+		mmr_t	clear               : 1;
+	} sh_memory_write_status_non_user_1_s;
+} sh_memory_write_status_non_user_1_u_t;
+#else
+typedef union sh_memory_write_status_non_user_1_u {
+	mmr_t	sh_memory_write_status_non_user_1_regval;
+	struct {
+		mmr_t	clear               : 1;
+		mmr_t	reserved_0          : 57;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_non_user_1_s;
+} sh_memory_write_status_non_user_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_ERR"                       */
+/*                  Error capture for bist read errors                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_err_u {
+	mmr_t	sh_mmrbist_err_regval;
+	struct {
+		mmr_t	addr              : 33;
+		mmr_t	reserved_0        : 3;
+		mmr_t	detected          : 1;
+		mmr_t	multiple_detected : 1;
+		mmr_t	cancelled         : 1;
+		mmr_t	reserved_1        : 25;
+	} sh_mmrbist_err_s;
+} sh_mmrbist_err_u_t;
+#else
+typedef union sh_mmrbist_err_u {
+	mmr_t	sh_mmrbist_err_regval;
+	struct {
+		mmr_t	reserved_1        : 25;
+		mmr_t	cancelled         : 1;
+		mmr_t	multiple_detected : 1;
+		mmr_t	detected          : 1;
+		mmr_t	reserved_0        : 3;
+		mmr_t	addr              : 33;
+	} sh_mmrbist_err_s;
+} sh_mmrbist_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_LOWER"                   */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_err_hdr_lower_u {
+	mmr_t	sh_misc_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_misc_err_hdr_lower_s;
+} sh_misc_err_hdr_lower_u_t;
+#else
+typedef union sh_misc_err_hdr_lower_u {
+	mmr_t	sh_misc_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_misc_err_hdr_lower_s;
+} sh_misc_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_UPPER"                   */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_err_hdr_upper_u {
+	mmr_t	sh_misc_err_hdr_upper_regval;
+	struct {
+		mmr_t	dir_protocol  : 1;
+		mmr_t	illegal_cmd   : 1;
+		mmr_t	nonexist_addr : 1;
+		mmr_t	rmw_uc        : 1;
+		mmr_t	rmw_cor       : 1;
+		mmr_t	dir_acc       : 1;
+		mmr_t	pi_pkt_size   : 1;
+		mmr_t	xn_pkt_size   : 1;
+		mmr_t	reserved_0    : 12;
+		mmr_t	echo          : 9;
+		mmr_t	reserved_1    : 35;
+	} sh_misc_err_hdr_upper_s;
+} sh_misc_err_hdr_upper_u_t;
+#else
+typedef union sh_misc_err_hdr_upper_u {
+	mmr_t	sh_misc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_1    : 35;
+		mmr_t	echo          : 9;
+		mmr_t	reserved_0    : 12;
+		mmr_t	xn_pkt_size   : 1;
+		mmr_t	pi_pkt_size   : 1;
+		mmr_t	dir_acc       : 1;
+		mmr_t	rmw_cor       : 1;
+		mmr_t	rmw_uc        : 1;
+		mmr_t	nonexist_addr : 1;
+		mmr_t	illegal_cmd   : 1;
+		mmr_t	dir_protocol  : 1;
+	} sh_misc_err_hdr_upper_s;
+} sh_misc_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_uc_err_hdr_lower_u {
+	mmr_t	sh_dir_uc_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_dir_uc_err_hdr_lower_s;
+} sh_dir_uc_err_hdr_lower_u_t;
+#else
+typedef union sh_dir_uc_err_hdr_lower_u {
+	mmr_t	sh_dir_uc_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_uc_err_hdr_lower_s;
+} sh_dir_uc_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_uc_err_hdr_upper_u {
+	mmr_t	sh_dir_uc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	dir_uc      : 1;
+		mmr_t	reserved_1  : 16;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_2  : 35;
+	} sh_dir_uc_err_hdr_upper_s;
+} sh_dir_uc_err_hdr_upper_u_t;
+#else
+typedef union sh_dir_uc_err_hdr_upper_u {
+	mmr_t	sh_dir_uc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_2  : 35;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_1  : 16;
+		mmr_t	dir_uc      : 1;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_uc_err_hdr_upper_s;
+} sh_dir_uc_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_cor_err_hdr_lower_u {
+	mmr_t	sh_dir_cor_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_dir_cor_err_hdr_lower_s;
+} sh_dir_cor_err_hdr_lower_u_t;
+#else
+typedef union sh_dir_cor_err_hdr_lower_u {
+	mmr_t	sh_dir_cor_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_cor_err_hdr_lower_s;
+} sh_dir_cor_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_cor_err_hdr_upper_u {
+	mmr_t	sh_dir_cor_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_0  : 8;
+		mmr_t	dir_cor     : 1;
+		mmr_t	reserved_1  : 11;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_2  : 35;
+	} sh_dir_cor_err_hdr_upper_s;
+} sh_dir_cor_err_hdr_upper_u_t;
+#else
+typedef union sh_dir_cor_err_hdr_upper_u {
+	mmr_t	sh_dir_cor_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_2  : 35;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_1  : 11;
+		mmr_t	dir_cor     : 1;
+		mmr_t	reserved_0  : 8;
+	} sh_dir_cor_err_hdr_upper_s;
+} sh_dir_cor_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_SUMMARY"                    */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_summary_u {
+	mmr_t	sh_mem_error_summary_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_summary_s;
+} sh_mem_error_summary_u_t;
+#else
+typedef union sh_mem_error_summary_u {
+	mmr_t	sh_mem_error_summary_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_summary_s;
+} sh_mem_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_OVERFLOW"                   */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_overflow_u {
+	mmr_t	sh_mem_error_overflow_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_overflow_s;
+} sh_mem_error_overflow_u_t;
+#else
+typedef union sh_mem_error_overflow_u {
+	mmr_t	sh_mem_error_overflow_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_overflow_s;
+} sh_mem_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_ERROR_MASK"                     */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_mask_u {
+	mmr_t	sh_mem_error_mask_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_mask_s;
+} sh_mem_error_mask_u_t;
+#else
+typedef union sh_mem_error_mask_u {
+	mmr_t	sh_mem_error_mask_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_mask_s;
+} sh_mem_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dimm_cfg_u {
+	mmr_t	sh_x_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_x_dimm_cfg_s;
+} sh_x_dimm_cfg_u_t;
+#else
+typedef union sh_x_dimm_cfg_u {
+	mmr_t	sh_x_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_x_dimm_cfg_s;
+} sh_x_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dimm_cfg_u {
+	mmr_t	sh_y_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_y_dimm_cfg_s;
+} sh_y_dimm_cfg_u_t;
+#else
+typedef union sh_y_dimm_cfg_u {
+	mmr_t	sh_y_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_y_dimm_cfg_s;
+} sh_y_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_JNR_DIMM_CFG"                      */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_jnr_dimm_cfg_u {
+	mmr_t	sh_jnr_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_jnr_dimm_cfg_s;
+} sh_jnr_dimm_cfg_u_t;
+#else
+typedef union sh_jnr_dimm_cfg_u {
+	mmr_t	sh_jnr_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_jnr_dimm_cfg_s;
+} sh_jnr_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_phase_cfg_u {
+	mmr_t	sh_x_phase_cfg_regval;
+	struct {
+		mmr_t	ld_a        : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	hold        : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	bubble_en   : 5;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	sel_a       : 4;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	reserved_0  : 1;
+	} sh_x_phase_cfg_s;
+} sh_x_phase_cfg_u_t;
+#else
+typedef union sh_x_phase_cfg_u {
+	mmr_t	sh_x_phase_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	sel_a       : 4;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	bubble_en   : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	hold        : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	ld_a        : 5;
+	} sh_x_phase_cfg_s;
+} sh_x_phase_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_cfg_u {
+	mmr_t	sh_x_cfg_regval;
+	struct {
+		mmr_t	mode_serial             : 1;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	clr_dir_cache           : 1;
+	} sh_x_cfg_s;
+} sh_x_cfg_u_t;
+#else
+typedef union sh_x_cfg_u {
+	mmr_t	sh_x_cfg_regval;
+	struct {
+		mmr_t	clr_dir_cache           : 1;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	mode_serial             : 1;
+	} sh_x_cfg_s;
+} sh_x_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dqct_cfg_u {
+	mmr_t	sh_x_dqct_cfg_regval;
+	struct {
+		mmr_t	rd_sel      : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	reserved_0  : 40;
+	} sh_x_dqct_cfg_s;
+} sh_x_dqct_cfg_u_t;
+#else
+typedef union sh_x_dqct_cfg_u {
+	mmr_t	sh_x_dqct_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	rd_sel      : 4;
+	} sh_x_dqct_cfg_s;
+} sh_x_dqct_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_X_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_refresh_control_u {
+	mmr_t	sh_x_refresh_control_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	interval    : 9;
+		mmr_t	hold        : 6;
+		mmr_t	interleave  : 1;
+		mmr_t	half_rate   : 4;
+		mmr_t	reserved_0  : 36;
+	} sh_x_refresh_control_s;
+} sh_x_refresh_control_u_t;
+#else
+typedef union sh_x_refresh_control_u {
+	mmr_t	sh_x_refresh_control_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	half_rate   : 4;
+		mmr_t	interleave  : 1;
+		mmr_t	hold        : 6;
+		mmr_t	interval    : 9;
+		mmr_t	enable      : 8;
+	} sh_x_refresh_control_s;
+} sh_x_refresh_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_phase_cfg_u {
+	mmr_t	sh_y_phase_cfg_regval;
+	struct {
+		mmr_t	ld_a        : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	hold        : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	bubble_en   : 5;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	sel_a       : 4;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	reserved_0  : 1;
+	} sh_y_phase_cfg_s;
+} sh_y_phase_cfg_u_t;
+#else
+typedef union sh_y_phase_cfg_u {
+	mmr_t	sh_y_phase_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	sel_a       : 4;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	bubble_en   : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	hold        : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	ld_a        : 5;
+	} sh_y_phase_cfg_s;
+} sh_y_phase_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_cfg_u {
+	mmr_t	sh_y_cfg_regval;
+	struct {
+		mmr_t	mode_serial             : 1;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	clr_dir_cache           : 1;
+	} sh_y_cfg_s;
+} sh_y_cfg_u_t;
+#else
+typedef union sh_y_cfg_u {
+	mmr_t	sh_y_cfg_regval;
+	struct {
+		mmr_t	clr_dir_cache           : 1;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	mode_serial             : 1;
+	} sh_y_cfg_s;
+} sh_y_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dqct_cfg_u {
+	mmr_t	sh_y_dqct_cfg_regval;
+	struct {
+		mmr_t	rd_sel      : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	reserved_0  : 40;
+	} sh_y_dqct_cfg_s;
+} sh_y_dqct_cfg_u_t;
+#else
+typedef union sh_y_dqct_cfg_u {
+	mmr_t	sh_y_dqct_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	rd_sel      : 4;
+	} sh_y_dqct_cfg_s;
+} sh_y_dqct_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_Y_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_refresh_control_u {
+	mmr_t	sh_y_refresh_control_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	interval    : 9;
+		mmr_t	hold        : 6;
+		mmr_t	interleave  : 1;
+		mmr_t	half_rate   : 4;
+		mmr_t	reserved_0  : 36;
+	} sh_y_refresh_control_s;
+} sh_y_refresh_control_u_t;
+#else
+typedef union sh_y_refresh_control_u {
+	mmr_t	sh_y_refresh_control_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	half_rate   : 4;
+		mmr_t	interleave  : 1;
+		mmr_t	hold        : 6;
+		mmr_t	interval    : 9;
+		mmr_t	enable      : 8;
+	} sh_y_refresh_control_s;
+} sh_y_refresh_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_RED_BLACK"                      */
+/*                     MD fairness watchdog timers                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_red_black_u {
+	mmr_t	sh_mem_red_black_regval;
+	struct {
+		mmr_t	time        : 16;
+		mmr_t	err_time    : 36;
+		mmr_t	reserved_0  : 12;
+	} sh_mem_red_black_s;
+} sh_mem_red_black_u_t;
+#else
+typedef union sh_mem_red_black_u {
+	mmr_t	sh_mem_red_black_regval;
+	struct {
+		mmr_t	reserved_0  : 12;
+		mmr_t	err_time    : 36;
+		mmr_t	time        : 16;
+	} sh_mem_red_black_s;
+} sh_mem_red_black_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MISC_MEM_CFG"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_mem_cfg_u {
+	mmr_t	sh_misc_mem_cfg_regval;
+	struct {
+		mmr_t	express_header_enable       : 1;
+		mmr_t	spec_header_enable          : 1;
+		mmr_t	jnr_bypass_enable           : 1;
+		mmr_t	xn_rd_same_as_pi            : 1;
+		mmr_t	low_write_buffer_threshold  : 6;
+		mmr_t	reserved_0                  : 2;
+		mmr_t	low_victim_buffer_threshold : 6;
+		mmr_t	reserved_1                  : 2;
+		mmr_t	throttle_cnt                : 8;
+		mmr_t	disabled_read_tnums         : 5;
+		mmr_t	reserved_2                  : 3;
+		mmr_t	disabled_write_tnums        : 5;
+		mmr_t	reserved_3                  : 3;
+		mmr_t	disabled_victims            : 6;
+		mmr_t	reserved_4                  : 2;
+		mmr_t	alternate_xn_rp_plane       : 1;
+		mmr_t	reserved_5                  : 11;
+	} sh_misc_mem_cfg_s;
+} sh_misc_mem_cfg_u_t;
+#else
+typedef union sh_misc_mem_cfg_u {
+	mmr_t	sh_misc_mem_cfg_regval;
+	struct {
+		mmr_t	reserved_5                  : 11;
+		mmr_t	alternate_xn_rp_plane       : 1;
+		mmr_t	reserved_4                  : 2;
+		mmr_t	disabled_victims            : 6;
+		mmr_t	reserved_3                  : 3;
+		mmr_t	disabled_write_tnums        : 5;
+		mmr_t	reserved_2                  : 3;
+		mmr_t	disabled_read_tnums         : 5;
+		mmr_t	throttle_cnt                : 8;
+		mmr_t	reserved_1                  : 2;
+		mmr_t	low_victim_buffer_threshold : 6;
+		mmr_t	reserved_0                  : 2;
+		mmr_t	low_write_buffer_threshold  : 6;
+		mmr_t	xn_rd_same_as_pi            : 1;
+		mmr_t	jnr_bypass_enable           : 1;
+		mmr_t	spec_header_enable          : 1;
+		mmr_t	express_header_enable       : 1;
+	} sh_misc_mem_cfg_s;
+} sh_misc_mem_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_RQ_CRD_CTL"                     */
+/*                  pio_rq Credit Circulation Control                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_rq_crd_ctl_u {
+	mmr_t	sh_pio_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pio_rq_crd_ctl_s;
+} sh_pio_rq_crd_ctl_u_t;
+#else
+typedef union sh_pio_rq_crd_ctl_u {
+	mmr_t	sh_pio_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pio_rq_crd_ctl_s;
+} sh_pio_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RQ_CRD_CTL"                    */
+/*                 pi_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md_rq_crd_ctl_u {
+	mmr_t	sh_pi_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pi_md_rq_crd_ctl_s;
+} sh_pi_md_rq_crd_ctl_u_t;
+#else
+typedef union sh_pi_md_rq_crd_ctl_u {
+	mmr_t	sh_pi_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pi_md_rq_crd_ctl_s;
+} sh_pi_md_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RP_CRD_CTL"                    */
+/*                 pi_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md_rp_crd_ctl_u {
+	mmr_t	sh_pi_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pi_md_rp_crd_ctl_s;
+} sh_pi_md_rp_crd_ctl_u_t;
+#else
+typedef union sh_pi_md_rp_crd_ctl_u {
+	mmr_t	sh_pi_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pi_md_rp_crd_ctl_s;
+} sh_pi_md_rp_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RQ_CRD_CTL"                    */
+/*                 xn_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_rq_crd_ctl_u {
+	mmr_t	sh_xn_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_xn_md_rq_crd_ctl_s;
+} sh_xn_md_rq_crd_ctl_u_t;
+#else
+typedef union sh_xn_md_rq_crd_ctl_u {
+	mmr_t	sh_xn_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_xn_md_rq_crd_ctl_s;
+} sh_xn_md_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RP_CRD_CTL"                    */
+/*                 xn_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_rp_crd_ctl_u {
+	mmr_t	sh_xn_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_xn_md_rp_crd_ctl_s;
+} sh_xn_md_rp_crd_ctl_u_t;
+#else
+typedef union sh_xn_md_rp_crd_ctl_u {
+	mmr_t	sh_xn_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_xn_md_rp_crd_ctl_s;
+} sh_xn_md_rp_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag0_u {
+	mmr_t	sh_x_tag0_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag0_s;
+} sh_x_tag0_u_t;
+#else
+typedef union sh_x_tag0_u {
+	mmr_t	sh_x_tag0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag0_s;
+} sh_x_tag0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag1_u {
+	mmr_t	sh_x_tag1_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag1_s;
+} sh_x_tag1_u_t;
+#else
+typedef union sh_x_tag1_u {
+	mmr_t	sh_x_tag1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag1_s;
+} sh_x_tag1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag2_u {
+	mmr_t	sh_x_tag2_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag2_s;
+} sh_x_tag2_u_t;
+#else
+typedef union sh_x_tag2_u {
+	mmr_t	sh_x_tag2_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag2_s;
+} sh_x_tag2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag3_u {
+	mmr_t	sh_x_tag3_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag3_s;
+} sh_x_tag3_u_t;
+#else
+typedef union sh_x_tag3_u {
+	mmr_t	sh_x_tag3_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag3_s;
+} sh_x_tag3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag4_u {
+	mmr_t	sh_x_tag4_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag4_s;
+} sh_x_tag4_u_t;
+#else
+typedef union sh_x_tag4_u {
+	mmr_t	sh_x_tag4_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag4_s;
+} sh_x_tag4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag5_u {
+	mmr_t	sh_x_tag5_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag5_s;
+} sh_x_tag5_u_t;
+#else
+typedef union sh_x_tag5_u {
+	mmr_t	sh_x_tag5_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag5_s;
+} sh_x_tag5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag6_u {
+	mmr_t	sh_x_tag6_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag6_s;
+} sh_x_tag6_u_t;
+#else
+typedef union sh_x_tag6_u {
+	mmr_t	sh_x_tag6_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag6_s;
+} sh_x_tag6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag7_u {
+	mmr_t	sh_x_tag7_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag7_s;
+} sh_x_tag7_u_t;
+#else
+typedef union sh_x_tag7_u {
+	mmr_t	sh_x_tag7_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag7_s;
+} sh_x_tag7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag0_u {
+	mmr_t	sh_y_tag0_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag0_s;
+} sh_y_tag0_u_t;
+#else
+typedef union sh_y_tag0_u {
+	mmr_t	sh_y_tag0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag0_s;
+} sh_y_tag0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag1_u {
+	mmr_t	sh_y_tag1_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag1_s;
+} sh_y_tag1_u_t;
+#else
+typedef union sh_y_tag1_u {
+	mmr_t	sh_y_tag1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag1_s;
+} sh_y_tag1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag2_u {
+	mmr_t	sh_y_tag2_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag2_s;
+} sh_y_tag2_u_t;
+#else
+typedef union sh_y_tag2_u {
+	mmr_t	sh_y_tag2_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag2_s;
+} sh_y_tag2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag3_u {
+	mmr_t	sh_y_tag3_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag3_s;
+} sh_y_tag3_u_t;
+#else
+typedef union sh_y_tag3_u {
+	mmr_t	sh_y_tag3_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag3_s;
+} sh_y_tag3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag4_u {
+	mmr_t	sh_y_tag4_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag4_s;
+} sh_y_tag4_u_t;
+#else
+typedef union sh_y_tag4_u {
+	mmr_t	sh_y_tag4_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag4_s;
+} sh_y_tag4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag5_u {
+	mmr_t	sh_y_tag5_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag5_s;
+} sh_y_tag5_u_t;
+#else
+typedef union sh_y_tag5_u {
+	mmr_t	sh_y_tag5_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag5_s;
+} sh_y_tag5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag6_u {
+	mmr_t	sh_y_tag6_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag6_s;
+} sh_y_tag6_u_t;
+#else
+typedef union sh_y_tag6_u {
+	mmr_t	sh_y_tag6_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag6_s;
+} sh_y_tag6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag7_u {
+	mmr_t	sh_y_tag7_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag7_s;
+} sh_y_tag7_u_t;
+#else
+typedef union sh_y_tag7_u {
+	mmr_t	sh_y_tag7_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag7_s;
+} sh_y_tag7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_BASE"                      */
+/*                        mmr/bist base address                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_base_u {
+	mmr_t	sh_mmrbist_base_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	dword_addr  : 47;
+		mmr_t	reserved_1  : 14;
+	} sh_mmrbist_base_s;
+} sh_mmrbist_base_u_t;
+#else
+typedef union sh_mmrbist_base_u {
+	mmr_t	sh_mmrbist_base_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	dword_addr  : 47;
+		mmr_t	reserved_0  : 3;
+	} sh_mmrbist_base_s;
+} sh_mmrbist_base_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_CTL"                       */
+/*                          Bist base address                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_ctl_u {
+	mmr_t	sh_mmrbist_ctl_regval;
+	struct {
+		mmr_t	block_length : 31;
+		mmr_t	reserved_0   : 1;
+		mmr_t	cmd          : 7;
+		mmr_t	reserved_1   : 1;
+		mmr_t	in_progress  : 1;
+		mmr_t	fail         : 1;
+		mmr_t	mem_idle     : 1;
+		mmr_t	reserved_2   : 1;
+		mmr_t	reset_state  : 1;
+		mmr_t	reserved_3   : 19;
+	} sh_mmrbist_ctl_s;
+} sh_mmrbist_ctl_u_t;
+#else
+typedef union sh_mmrbist_ctl_u {
+	mmr_t	sh_mmrbist_ctl_regval;
+	struct {
+		mmr_t	reserved_3   : 19;
+		mmr_t	reset_state  : 1;
+		mmr_t	reserved_2   : 1;
+		mmr_t	mem_idle     : 1;
+		mmr_t	fail         : 1;
+		mmr_t	in_progress  : 1;
+		mmr_t	reserved_1   : 1;
+		mmr_t	cmd          : 7;
+		mmr_t	reserved_0   : 1;
+		mmr_t	block_length : 31;
+	} sh_mmrbist_ctl_s;
+} sh_mmrbist_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_DATA_CFG"                    */
+/*                configuration for md debug data muxes                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_data_cfg_u {
+	mmr_t	sh_md_dbug_data_cfg_regval;
+	struct {
+		mmr_t	nibble0_chiplet : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_15     : 1;
+	} sh_md_dbug_data_cfg_s;
+} sh_md_dbug_data_cfg_u_t;
+#else
+typedef union sh_md_dbug_data_cfg_u {
+	mmr_t	sh_md_dbug_data_cfg_regval;
+	struct {
+		mmr_t	reserved_15     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_chiplet : 3;
+	} sh_md_dbug_data_cfg_s;
+} sh_md_dbug_data_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DBUG_TRIGGER_CFG"                   */
+/*                 configuration for md debug triggers                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_trigger_cfg_u {
+	mmr_t	sh_md_dbug_trigger_cfg_regval;
+	struct {
+		mmr_t	nibble0_chiplet : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	enable          : 1;
+	} sh_md_dbug_trigger_cfg_s;
+} sh_md_dbug_trigger_cfg_u_t;
+#else
+typedef union sh_md_dbug_trigger_cfg_u {
+	mmr_t	sh_md_dbug_trigger_cfg_regval;
+	struct {
+		mmr_t	enable          : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_chiplet : 3;
+	} sh_md_dbug_trigger_cfg_s;
+} sh_md_dbug_trigger_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_COMPARE"                     */
+/*                  md debug compare pattern and mask                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_compare_u {
+	mmr_t	sh_md_dbug_compare_regval;
+	struct {
+		mmr_t	pattern     : 32;
+		mmr_t	mask        : 32;
+	} sh_md_dbug_compare_s;
+} sh_md_dbug_compare_u_t;
+#else
+typedef union sh_md_dbug_compare_u {
+	mmr_t	sh_md_dbug_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	pattern     : 32;
+	} sh_md_dbug_compare_s;
+} sh_md_dbug_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_X_MOD_DBUG_SEL"                     */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_mod_dbug_sel_u {
+	mmr_t	sh_x_mod_dbug_sel_regval;
+	struct {
+		mmr_t	tag_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	arb_sel     : 8;
+		mmr_t	atl_sel     : 11;
+		mmr_t	atr_sel     : 11;
+		mmr_t	dql_sel     : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	reserved_0  : 6;
+	} sh_x_mod_dbug_sel_s;
+} sh_x_mod_dbug_sel_u_t;
+#else
+typedef union sh_x_mod_dbug_sel_u {
+	mmr_t	sh_x_mod_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	dql_sel     : 6;
+		mmr_t	atr_sel     : 11;
+		mmr_t	atl_sel     : 11;
+		mmr_t	arb_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	tag_sel     : 8;
+	} sh_x_mod_dbug_sel_s;
+} sh_x_mod_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DBUG_SEL"                       */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dbug_sel_u {
+	mmr_t	sh_x_dbug_sel_regval;
+	struct {
+		mmr_t	dbg_sel     : 24;
+		mmr_t	reserved_0  : 40;
+	} sh_x_dbug_sel_s;
+} sh_x_dbug_sel_u_t;
+#else
+typedef union sh_x_dbug_sel_u {
+	mmr_t	sh_x_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	dbg_sel     : 24;
+	} sh_x_dbug_sel_s;
+} sh_x_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_LADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_laddr_cmp_u {
+	mmr_t	sh_x_laddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_x_laddr_cmp_s;
+} sh_x_laddr_cmp_u_t;
+#else
+typedef union sh_x_laddr_cmp_u {
+	mmr_t	sh_x_laddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_x_laddr_cmp_s;
+} sh_x_laddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_RADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_raddr_cmp_u {
+	mmr_t	sh_x_raddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_x_raddr_cmp_s;
+} sh_x_raddr_cmp_u_t;
+#else
+typedef union sh_x_raddr_cmp_u {
+	mmr_t	sh_x_raddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_x_raddr_cmp_s;
+} sh_x_raddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_CMP"                        */
+/*                        MD acx tagmgr compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag_cmp_u {
+	mmr_t	sh_x_tag_cmp_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_x_tag_cmp_s;
+} sh_x_tag_cmp_u_t;
+#else
+typedef union sh_x_tag_cmp_u {
+	mmr_t	sh_x_tag_cmp_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_x_tag_cmp_s;
+} sh_x_tag_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_MASK"                       */
+/*                          MD acx tagmgr mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag_mask_u {
+	mmr_t	sh_x_tag_mask_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_x_tag_mask_s;
+} sh_x_tag_mask_u_t;
+#else
+typedef union sh_x_tag_mask_u {
+	mmr_t	sh_x_tag_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_x_tag_mask_s;
+} sh_x_tag_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_Y_MOD_DBUG_SEL"                     */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_mod_dbug_sel_u {
+	mmr_t	sh_y_mod_dbug_sel_regval;
+	struct {
+		mmr_t	tag_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	arb_sel     : 8;
+		mmr_t	atl_sel     : 11;
+		mmr_t	atr_sel     : 11;
+		mmr_t	dql_sel     : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	reserved_0  : 6;
+	} sh_y_mod_dbug_sel_s;
+} sh_y_mod_dbug_sel_u_t;
+#else
+typedef union sh_y_mod_dbug_sel_u {
+	mmr_t	sh_y_mod_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	dql_sel     : 6;
+		mmr_t	atr_sel     : 11;
+		mmr_t	atl_sel     : 11;
+		mmr_t	arb_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	tag_sel     : 8;
+	} sh_y_mod_dbug_sel_s;
+} sh_y_mod_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DBUG_SEL"                       */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dbug_sel_u {
+	mmr_t	sh_y_dbug_sel_regval;
+	struct {
+		mmr_t	dbg_sel     : 24;
+		mmr_t	reserved_0  : 40;
+	} sh_y_dbug_sel_s;
+} sh_y_dbug_sel_u_t;
+#else
+typedef union sh_y_dbug_sel_u {
+	mmr_t	sh_y_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	dbg_sel     : 24;
+	} sh_y_dbug_sel_s;
+} sh_y_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_LADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_laddr_cmp_u {
+	mmr_t	sh_y_laddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_y_laddr_cmp_s;
+} sh_y_laddr_cmp_u_t;
+#else
+typedef union sh_y_laddr_cmp_u {
+	mmr_t	sh_y_laddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_y_laddr_cmp_s;
+} sh_y_laddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_RADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_raddr_cmp_u {
+	mmr_t	sh_y_raddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_y_raddr_cmp_s;
+} sh_y_raddr_cmp_u_t;
+#else
+typedef union sh_y_raddr_cmp_u {
+	mmr_t	sh_y_raddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_y_raddr_cmp_s;
+} sh_y_raddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_CMP"                        */
+/*                        MD acy tagmgr compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag_cmp_u {
+	mmr_t	sh_y_tag_cmp_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_y_tag_cmp_s;
+} sh_y_tag_cmp_u_t;
+#else
+typedef union sh_y_tag_cmp_u {
+	mmr_t	sh_y_tag_cmp_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_y_tag_cmp_s;
+} sh_y_tag_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_MASK"                       */
+/*                          MD acy tagmgr mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag_mask_u {
+	mmr_t	sh_y_tag_mask_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_y_tag_mask_s;
+} sh_y_tag_mask_u_t;
+#else
+typedef union sh_y_tag_mask_u {
+	mmr_t	sh_y_tag_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_y_tag_mask_s;
+} sh_y_tag_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_JNR_DBUG_DATA_CFG"                  */
+/*              configuration for md jnr debug data muxes               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_jnr_dbug_data_cfg_u {
+	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
+	struct {
+		mmr_t	nibble0_sel : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	nibble1_sel : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	nibble2_sel : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	nibble3_sel : 3;
+		mmr_t	reserved_3  : 1;
+		mmr_t	nibble4_sel : 3;
+		mmr_t	reserved_4  : 1;
+		mmr_t	nibble5_sel : 3;
+		mmr_t	reserved_5  : 1;
+		mmr_t	nibble6_sel : 3;
+		mmr_t	reserved_6  : 1;
+		mmr_t	nibble7_sel : 3;
+		mmr_t	reserved_7  : 33;
+	} sh_md_jnr_dbug_data_cfg_s;
+} sh_md_jnr_dbug_data_cfg_u_t;
+#else
+typedef union sh_md_jnr_dbug_data_cfg_u {
+	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
+	struct {
+		mmr_t	reserved_7  : 33;
+		mmr_t	nibble7_sel : 3;
+		mmr_t	reserved_6  : 1;
+		mmr_t	nibble6_sel : 3;
+		mmr_t	reserved_5  : 1;
+		mmr_t	nibble5_sel : 3;
+		mmr_t	reserved_4  : 1;
+		mmr_t	nibble4_sel : 3;
+		mmr_t	reserved_3  : 1;
+		mmr_t	nibble3_sel : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	nibble2_sel : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	nibble1_sel : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	nibble0_sel : 3;
+	} sh_md_jnr_dbug_data_cfg_s;
+} sh_md_jnr_dbug_data_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LAST_CREDIT"                     */
+/*                 captures last credit values on reset                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_last_credit_u {
+	mmr_t	sh_md_last_credit_regval;
+	struct {
+		mmr_t	rq_to_pi    : 6;
+		mmr_t	reserved_0  : 2;
+		mmr_t	rp_to_pi    : 6;
+		mmr_t	reserved_1  : 2;
+		mmr_t	rq_to_xn    : 6;
+		mmr_t	reserved_2  : 2;
+		mmr_t	rp_to_xn    : 6;
+		mmr_t	reserved_3  : 2;
+		mmr_t	to_lb       : 6;
+		mmr_t	reserved_4  : 26;
+	} sh_md_last_credit_s;
+} sh_md_last_credit_u_t;
+#else
+typedef union sh_md_last_credit_u {
+	mmr_t	sh_md_last_credit_regval;
+	struct {
+		mmr_t	reserved_4  : 26;
+		mmr_t	to_lb       : 6;
+		mmr_t	reserved_3  : 2;
+		mmr_t	rp_to_xn    : 6;
+		mmr_t	reserved_2  : 2;
+		mmr_t	rq_to_xn    : 6;
+		mmr_t	reserved_1  : 2;
+		mmr_t	rp_to_pi    : 6;
+		mmr_t	reserved_0  : 2;
+		mmr_t	rq_to_pi    : 6;
+	} sh_md_last_credit_s;
+} sh_md_last_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_ADDR"                    */
+/*                   Address capture address register                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_addr_u {
+	mmr_t	sh_mem_capture_addr_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	reserved_1  : 20;
+	} sh_mem_capture_addr_s;
+} sh_mem_capture_addr_u_t;
+#else
+typedef union sh_mem_capture_addr_u {
+	mmr_t	sh_mem_capture_addr_regval;
+	struct {
+		mmr_t	reserved_1  : 20;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_mem_capture_addr_s;
+} sh_mem_capture_addr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_MASK"                    */
+/*                    Address capture mask register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_mask_u {
+	mmr_t	sh_mem_capture_mask_regval;
+	struct {
+		mmr_t	reserved_0    : 3;
+		mmr_t	addr          : 33;
+		mmr_t	cmd           : 8;
+		mmr_t	enable_local  : 1;
+		mmr_t	enable_remote : 1;
+		mmr_t	reserved_1    : 18;
+	} sh_mem_capture_mask_s;
+} sh_mem_capture_mask_u_t;
+#else
+typedef union sh_mem_capture_mask_u {
+	mmr_t	sh_mem_capture_mask_regval;
+	struct {
+		mmr_t	reserved_1    : 18;
+		mmr_t	enable_remote : 1;
+		mmr_t	enable_local  : 1;
+		mmr_t	cmd           : 8;
+		mmr_t	addr          : 33;
+		mmr_t	reserved_0    : 3;
+	} sh_mem_capture_mask_s;
+} sh_mem_capture_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_HDR"                     */
+/*                   Address capture header register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_hdr_u {
+	mmr_t	sh_mem_capture_hdr_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	cntr        : 6;
+	} sh_mem_capture_hdr_s;
+} sh_mem_capture_hdr_u_t;
+#else
+typedef union sh_mem_capture_hdr_u {
+	mmr_t	sh_mem_capture_hdr_regval;
+	struct {
+		mmr_t	cntr        : 6;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_mem_capture_hdr_s;
+} sh_mem_capture_hdr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_config_u {
+	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
+	struct {
+		mmr_t	sys_size    : 3;
+		mmr_t	en_direcc   : 1;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	reserved_0  : 59;
+	} sh_md_dqlp_mmr_dir_config_s;
+} sh_md_dqlp_mmr_dir_config_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_config_u {
+	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	en_direcc   : 1;
+		mmr_t	sys_size    : 3;
+	} sh_md_dqlp_mmr_dir_config_s;
+} sh_md_dqlp_mmr_dir_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec0_s;
+} sh_md_dqlp_mmr_dir_presvec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec0_s;
+} sh_md_dqlp_mmr_dir_presvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec1_s;
+} sh_md_dqlp_mmr_dir_presvec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec1_s;
+} sh_md_dqlp_mmr_dir_presvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec2_s;
+} sh_md_dqlp_mmr_dir_presvec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec2_s;
+} sh_md_dqlp_mmr_dir_presvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec3_s;
+} sh_md_dqlp_mmr_dir_presvec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec3_s;
+} sh_md_dqlp_mmr_dir_presvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec0_s;
+} sh_md_dqlp_mmr_dir_locvec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec0_s;
+} sh_md_dqlp_mmr_dir_locvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec1_s;
+} sh_md_dqlp_mmr_dir_locvec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec1_s;
+} sh_md_dqlp_mmr_dir_locvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec2_s;
+} sh_md_dqlp_mmr_dir_locvec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec2_s;
+} sh_md_dqlp_mmr_dir_locvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec3_s;
+} sh_md_dqlp_mmr_dir_locvec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec3_s;
+} sh_md_dqlp_mmr_dir_locvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec4_s;
+} sh_md_dqlp_mmr_dir_locvec4_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec4_s;
+} sh_md_dqlp_mmr_dir_locvec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec5_s;
+} sh_md_dqlp_mmr_dir_locvec5_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec5_s;
+} sh_md_dqlp_mmr_dir_locvec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec6_s;
+} sh_md_dqlp_mmr_dir_locvec6_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec6_s;
+} sh_md_dqlp_mmr_dir_locvec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec7_s;
+} sh_md_dqlp_mmr_dir_locvec7_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec7_s;
+} sh_md_dqlp_mmr_dir_locvec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec0_s;
+} sh_md_dqlp_mmr_dir_privec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec0_s;
+} sh_md_dqlp_mmr_dir_privec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec1_s;
+} sh_md_dqlp_mmr_dir_privec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec1_s;
+} sh_md_dqlp_mmr_dir_privec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec2_s;
+} sh_md_dqlp_mmr_dir_privec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec2_s;
+} sh_md_dqlp_mmr_dir_privec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec3_s;
+} sh_md_dqlp_mmr_dir_privec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec3_s;
+} sh_md_dqlp_mmr_dir_privec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec4_s;
+} sh_md_dqlp_mmr_dir_privec4_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec4_s;
+} sh_md_dqlp_mmr_dir_privec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec5_s;
+} sh_md_dqlp_mmr_dir_privec5_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec5_s;
+} sh_md_dqlp_mmr_dir_privec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec6_s;
+} sh_md_dqlp_mmr_dir_privec6_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec6_s;
+} sh_md_dqlp_mmr_dir_privec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec7_s;
+} sh_md_dqlp_mmr_dir_privec7_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec7_s;
+} sh_md_dqlp_mmr_dir_privec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	timer_div   : 12;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_cur   : 9;
+		mmr_t	reserved_0  : 42;
+	} sh_md_dqlp_mmr_dir_timer_s;
+} sh_md_dqlp_mmr_dir_timer_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	reserved_0  : 42;
+		mmr_t	timer_cur   : 9;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_div   : 12;
+	} sh_md_dqlp_mmr_dir_timer_s;
+} sh_md_dqlp_mmr_dir_timer_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	reserved_0  : 6;
+	} sh_md_dqlp_mmr_piowd_dir_entry_s;
+} sh_md_dqlp_mmr_piowd_dir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_piowd_dir_entry_s;
+} sh_md_dqlp_mmr_piowd_dir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_piowd_dir_ecc_s;
+} sh_md_dqlp_mmr_piowd_dir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_piowd_dir_ecc_s;
+} sh_md_dqlp_mmr_piowd_dir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqlp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqlp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_xcerr1_s;
+} sh_md_dqlp_mmr_xcerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_xcerr1_s;
+} sh_md_dqlp_mmr_xcerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_xcerr2_s;
+} sh_md_dqlp_mmr_xcerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_xcerr2_s;
+} sh_md_dqlp_mmr_xcerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_xuerr1_s;
+} sh_md_dqlp_mmr_xuerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_xuerr1_s;
+} sh_md_dqlp_mmr_xuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_xuerr2_s;
+} sh_md_dqlp_mmr_xuerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_xuerr2_s;
+} sh_md_dqlp_mmr_xuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xperr_u {
+	mmr_t	sh_md_dqlp_mmr_xperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqlp_mmr_xperr_s;
+} sh_md_dqlp_mmr_xperr_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xperr_u {
+	mmr_t	sh_md_dqlp_mmr_xperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqlp_mmr_xperr_s;
+} sh_md_dqlp_mmr_xperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_ycerr1_s;
+} sh_md_dqlp_mmr_ycerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_ycerr1_s;
+} sh_md_dqlp_mmr_ycerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_ycerr2_s;
+} sh_md_dqlp_mmr_ycerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_ycerr2_s;
+} sh_md_dqlp_mmr_ycerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_yuerr1_s;
+} sh_md_dqlp_mmr_yuerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_yuerr1_s;
+} sh_md_dqlp_mmr_yuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_yuerr2_s;
+} sh_md_dqlp_mmr_yuerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_yuerr2_s;
+} sh_md_dqlp_mmr_yuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yperr_u {
+	mmr_t	sh_md_dqlp_mmr_yperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqlp_mmr_yperr_s;
+} sh_md_dqlp_mmr_yperr_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yperr_u {
+	mmr_t	sh_md_dqlp_mmr_yperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqlp_mmr_yperr_s;
+} sh_md_dqlp_mmr_yperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	cmd0        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd3        : 8;
+		mmr_t	reserved_0  : 32;
+	} sh_md_dqlp_mmr_dir_cmdtrig_s;
+} sh_md_dqlp_mmr_dir_cmdtrig_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	cmd3        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd0        : 8;
+	} sh_md_dqlp_mmr_dir_cmdtrig_s;
+} sh_md_dqlp_mmr_dir_cmdtrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqlp_mmr_dir_tbltrig_s;
+} sh_md_dqlp_mmr_dir_tbltrig_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqlp_mmr_dir_tbltrig_s;
+} sh_md_dqlp_mmr_dir_tbltrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqlp_mmr_dir_tblmask_s;
+} sh_md_dqlp_mmr_dir_tblmask_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqlp_mmr_dir_tblmask_s;
+} sh_md_dqlp_mmr_dir_tblmask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqlp_mmr_xbist_h_s;
+} sh_md_dqlp_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_h_s;
+} sh_md_dqlp_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_l_s;
+} sh_md_dqlp_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_l_s;
+} sh_md_dqlp_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_err_h_s;
+} sh_md_dqlp_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_err_h_s;
+} sh_md_dqlp_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_err_l_s;
+} sh_md_dqlp_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_err_l_s;
+} sh_md_dqlp_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqlp_mmr_ybist_h_s;
+} sh_md_dqlp_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_h_s;
+} sh_md_dqlp_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_l_s;
+} sh_md_dqlp_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_l_s;
+} sh_md_dqlp_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_err_h_s;
+} sh_md_dqlp_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_err_h_s;
+} sh_md_dqlp_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_err_l_s;
+} sh_md_dqlp_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_err_l_s;
+} sh_md_dqlp_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqls_mmr_xbist_h_s;
+} sh_md_dqls_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_h_s;
+} sh_md_dqls_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_l_s;
+} sh_md_dqls_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_l_s;
+} sh_md_dqls_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_err_h_s;
+} sh_md_dqls_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_err_h_s;
+} sh_md_dqls_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_err_l_s;
+} sh_md_dqls_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_err_l_s;
+} sh_md_dqls_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqls_mmr_ybist_h_s;
+} sh_md_dqls_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_h_s;
+} sh_md_dqls_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_l_s;
+} sh_md_dqls_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_l_s;
+} sh_md_dqls_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_err_h_s;
+} sh_md_dqls_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_err_h_s;
+} sh_md_dqls_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_err_l_s;
+} sh_md_dqls_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_err_l_s;
+} sh_md_dqls_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	px          : 1;
+		mmr_t	rw          : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_md_dqls_mmr_jnr_debug_s;
+} sh_md_dqls_mmr_jnr_debug_u_t;
+#else
+typedef union sh_md_dqls_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	rw          : 1;
+		mmr_t	px          : 1;
+	} sh_md_dqls_mmr_jnr_debug_s;
+} sh_md_dqls_mmr_jnr_debug_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_XAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xamopw_err_u {
+	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
+	struct {
+		mmr_t	ssyn        : 8;
+		mmr_t	scor        : 1;
+		mmr_t	sunc        : 1;
+		mmr_t	reserved_0  : 6;
+		mmr_t	rsyn        : 8;
+		mmr_t	rcor        : 1;
+		mmr_t	runc        : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_2  : 31;
+	} sh_md_dqls_mmr_xamopw_err_s;
+} sh_md_dqls_mmr_xamopw_err_u_t;
+#else
+typedef union sh_md_dqls_mmr_xamopw_err_u {
+	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
+	struct {
+		mmr_t	reserved_2  : 31;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	runc        : 1;
+		mmr_t	rcor        : 1;
+		mmr_t	rsyn        : 8;
+		mmr_t	reserved_0  : 6;
+		mmr_t	sunc        : 1;
+		mmr_t	scor        : 1;
+		mmr_t	ssyn        : 8;
+	} sh_md_dqls_mmr_xamopw_err_s;
+} sh_md_dqls_mmr_xamopw_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_config_u {
+	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
+	struct {
+		mmr_t	sys_size    : 3;
+		mmr_t	en_direcc   : 1;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	reserved_0  : 59;
+	} sh_md_dqrp_mmr_dir_config_s;
+} sh_md_dqrp_mmr_dir_config_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_config_u {
+	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	en_direcc   : 1;
+		mmr_t	sys_size    : 3;
+	} sh_md_dqrp_mmr_dir_config_s;
+} sh_md_dqrp_mmr_dir_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec0_s;
+} sh_md_dqrp_mmr_dir_presvec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec0_s;
+} sh_md_dqrp_mmr_dir_presvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec1_s;
+} sh_md_dqrp_mmr_dir_presvec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec1_s;
+} sh_md_dqrp_mmr_dir_presvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec2_s;
+} sh_md_dqrp_mmr_dir_presvec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec2_s;
+} sh_md_dqrp_mmr_dir_presvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec3_s;
+} sh_md_dqrp_mmr_dir_presvec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec3_s;
+} sh_md_dqrp_mmr_dir_presvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec0_s;
+} sh_md_dqrp_mmr_dir_locvec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec0_s;
+} sh_md_dqrp_mmr_dir_locvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec1_s;
+} sh_md_dqrp_mmr_dir_locvec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec1_s;
+} sh_md_dqrp_mmr_dir_locvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec2_s;
+} sh_md_dqrp_mmr_dir_locvec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec2_s;
+} sh_md_dqrp_mmr_dir_locvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec3_s;
+} sh_md_dqrp_mmr_dir_locvec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec3_s;
+} sh_md_dqrp_mmr_dir_locvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec4_s;
+} sh_md_dqrp_mmr_dir_locvec4_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec4_s;
+} sh_md_dqrp_mmr_dir_locvec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec5_s;
+} sh_md_dqrp_mmr_dir_locvec5_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec5_s;
+} sh_md_dqrp_mmr_dir_locvec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec6_s;
+} sh_md_dqrp_mmr_dir_locvec6_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec6_s;
+} sh_md_dqrp_mmr_dir_locvec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec7_s;
+} sh_md_dqrp_mmr_dir_locvec7_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec7_s;
+} sh_md_dqrp_mmr_dir_locvec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec0_s;
+} sh_md_dqrp_mmr_dir_privec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec0_s;
+} sh_md_dqrp_mmr_dir_privec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec1_s;
+} sh_md_dqrp_mmr_dir_privec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec1_s;
+} sh_md_dqrp_mmr_dir_privec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec2_s;
+} sh_md_dqrp_mmr_dir_privec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec2_s;
+} sh_md_dqrp_mmr_dir_privec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec3_s;
+} sh_md_dqrp_mmr_dir_privec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec3_s;
+} sh_md_dqrp_mmr_dir_privec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec4_s;
+} sh_md_dqrp_mmr_dir_privec4_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec4_s;
+} sh_md_dqrp_mmr_dir_privec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec5_s;
+} sh_md_dqrp_mmr_dir_privec5_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec5_s;
+} sh_md_dqrp_mmr_dir_privec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec6_s;
+} sh_md_dqrp_mmr_dir_privec6_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec6_s;
+} sh_md_dqrp_mmr_dir_privec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec7_s;
+} sh_md_dqrp_mmr_dir_privec7_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec7_s;
+} sh_md_dqrp_mmr_dir_privec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	timer_div   : 12;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_cur   : 9;
+		mmr_t	reserved_0  : 42;
+	} sh_md_dqrp_mmr_dir_timer_s;
+} sh_md_dqrp_mmr_dir_timer_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	reserved_0  : 42;
+		mmr_t	timer_cur   : 9;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_div   : 12;
+	} sh_md_dqrp_mmr_dir_timer_s;
+} sh_md_dqrp_mmr_dir_timer_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	reserved_0  : 6;
+	} sh_md_dqrp_mmr_piowd_dir_entry_s;
+} sh_md_dqrp_mmr_piowd_dir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_piowd_dir_entry_s;
+} sh_md_dqrp_mmr_piowd_dir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_piowd_dir_ecc_s;
+} sh_md_dqrp_mmr_piowd_dir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_piowd_dir_ecc_s;
+} sh_md_dqrp_mmr_piowd_dir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqrp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqrp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_xcerr1_s;
+} sh_md_dqrp_mmr_xcerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_xcerr1_s;
+} sh_md_dqrp_mmr_xcerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_xcerr2_s;
+} sh_md_dqrp_mmr_xcerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_xcerr2_s;
+} sh_md_dqrp_mmr_xcerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_xuerr1_s;
+} sh_md_dqrp_mmr_xuerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_xuerr1_s;
+} sh_md_dqrp_mmr_xuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_xuerr2_s;
+} sh_md_dqrp_mmr_xuerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_xuerr2_s;
+} sh_md_dqrp_mmr_xuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xperr_u {
+	mmr_t	sh_md_dqrp_mmr_xperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqrp_mmr_xperr_s;
+} sh_md_dqrp_mmr_xperr_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xperr_u {
+	mmr_t	sh_md_dqrp_mmr_xperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqrp_mmr_xperr_s;
+} sh_md_dqrp_mmr_xperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_ycerr1_s;
+} sh_md_dqrp_mmr_ycerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_ycerr1_s;
+} sh_md_dqrp_mmr_ycerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_ycerr2_s;
+} sh_md_dqrp_mmr_ycerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_ycerr2_s;
+} sh_md_dqrp_mmr_ycerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_yuerr1_s;
+} sh_md_dqrp_mmr_yuerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_yuerr1_s;
+} sh_md_dqrp_mmr_yuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_yuerr2_s;
+} sh_md_dqrp_mmr_yuerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_yuerr2_s;
+} sh_md_dqrp_mmr_yuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yperr_u {
+	mmr_t	sh_md_dqrp_mmr_yperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqrp_mmr_yperr_s;
+} sh_md_dqrp_mmr_yperr_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yperr_u {
+	mmr_t	sh_md_dqrp_mmr_yperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqrp_mmr_yperr_s;
+} sh_md_dqrp_mmr_yperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	cmd0        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd3        : 8;
+		mmr_t	reserved_0  : 32;
+	} sh_md_dqrp_mmr_dir_cmdtrig_s;
+} sh_md_dqrp_mmr_dir_cmdtrig_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	cmd3        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd0        : 8;
+	} sh_md_dqrp_mmr_dir_cmdtrig_s;
+} sh_md_dqrp_mmr_dir_cmdtrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrp_mmr_dir_tbltrig_s;
+} sh_md_dqrp_mmr_dir_tbltrig_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqrp_mmr_dir_tbltrig_s;
+} sh_md_dqrp_mmr_dir_tbltrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrp_mmr_dir_tblmask_s;
+} sh_md_dqrp_mmr_dir_tblmask_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqrp_mmr_dir_tblmask_s;
+} sh_md_dqrp_mmr_dir_tblmask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqrp_mmr_xbist_h_s;
+} sh_md_dqrp_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_h_s;
+} sh_md_dqrp_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_l_s;
+} sh_md_dqrp_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_l_s;
+} sh_md_dqrp_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_err_h_s;
+} sh_md_dqrp_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_err_h_s;
+} sh_md_dqrp_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_err_l_s;
+} sh_md_dqrp_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_err_l_s;
+} sh_md_dqrp_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqrp_mmr_ybist_h_s;
+} sh_md_dqrp_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_h_s;
+} sh_md_dqrp_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_l_s;
+} sh_md_dqrp_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_l_s;
+} sh_md_dqrp_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_err_h_s;
+} sh_md_dqrp_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_err_h_s;
+} sh_md_dqrp_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_err_l_s;
+} sh_md_dqrp_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_err_l_s;
+} sh_md_dqrp_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqrs_mmr_xbist_h_s;
+} sh_md_dqrs_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_h_s;
+} sh_md_dqrs_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_l_s;
+} sh_md_dqrs_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_l_s;
+} sh_md_dqrs_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_err_h_s;
+} sh_md_dqrs_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_err_h_s;
+} sh_md_dqrs_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_err_l_s;
+} sh_md_dqrs_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_err_l_s;
+} sh_md_dqrs_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqrs_mmr_ybist_h_s;
+} sh_md_dqrs_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_h_s;
+} sh_md_dqrs_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_l_s;
+} sh_md_dqrs_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_l_s;
+} sh_md_dqrs_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_err_h_s;
+} sh_md_dqrs_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_err_h_s;
+} sh_md_dqrs_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_err_l_s;
+} sh_md_dqrs_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_err_l_s;
+} sh_md_dqrs_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	px          : 1;
+		mmr_t	rw          : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_md_dqrs_mmr_jnr_debug_s;
+} sh_md_dqrs_mmr_jnr_debug_u_t;
+#else
+typedef union sh_md_dqrs_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	rw          : 1;
+		mmr_t	px          : 1;
+	} sh_md_dqrs_mmr_jnr_debug_s;
+} sh_md_dqrs_mmr_jnr_debug_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_YAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_yamopw_err_u {
+	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
+	struct {
+		mmr_t	ssyn        : 8;
+		mmr_t	scor        : 1;
+		mmr_t	sunc        : 1;
+		mmr_t	reserved_0  : 6;
+		mmr_t	rsyn        : 8;
+		mmr_t	rcor        : 1;
+		mmr_t	runc        : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_2  : 31;
+	} sh_md_dqrs_mmr_yamopw_err_s;
+} sh_md_dqrs_mmr_yamopw_err_u_t;
+#else
+typedef union sh_md_dqrs_mmr_yamopw_err_u {
+	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
+	struct {
+		mmr_t	reserved_2  : 31;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	runc        : 1;
+		mmr_t	rcor        : 1;
+		mmr_t	rsyn        : 8;
+		mmr_t	reserved_0  : 6;
+		mmr_t	sunc        : 1;
+		mmr_t	scor        : 1;
+		mmr_t	ssyn        : 8;
+	} sh_md_dqrs_mmr_yamopw_err_s;
+} sh_md_dqrs_mmr_yamopw_err_u_t;
+#endif
+
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/shubio.h lia64-2.4/include/asm-ia64/sn/sn2/shubio.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/shubio.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/shubio.h	Mon Nov 26 18:07:20 2001
@@ -0,0 +1,3619 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_SHUBIO_H
+#define _ASM_IA64_SN_SN2_SHUBIO_H
+
+#define HUB_WIDGET_ID_MAX 0xf
+#define IIO_NUM_ITTES   7
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
+                                                   /* This register is also accessible from
+                                                    * Crosstalk at address 0x0.  */
+#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
+#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
+#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
+#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
+#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
+#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
+#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
+#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
+#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
+#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
+
+#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
+#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
+
+#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
+#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
+
+#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
+#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
+#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
+#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
+#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
+#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
+#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
+
+#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
+#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
+#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
+#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
+#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
+#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
+#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
+#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
+#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
+
+#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
+#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
+#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
+#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
+#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
+
+#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
+#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
+
+#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
+
+#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
+#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
+
+
+#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
+#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
+
+#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
+#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
+#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
+#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
+#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
+
+#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
+
+#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
+#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
+#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
+#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
+#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
+#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
+#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
+#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
+
+#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
+#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
+#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
+#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
+#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
+#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
+#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
+#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
+
+#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
+#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
+#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
+#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
+#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
+#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
+#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
+#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
+
+#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
+#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
+#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
+#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
+#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
+
+#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
+#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
+#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
+#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
+#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
+
+#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
+#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
+#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
+#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
+#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
+
+#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
+#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
+#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
+#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
+#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
+
+#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
+#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
+#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
+#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
+#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
+
+#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
+#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
+#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
+#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
+#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
+
+#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
+#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
+#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
+#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
+#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
+
+#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
+#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
+#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
+#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
+#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
+
+#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
+#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
+#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
+#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
+#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
+
+#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
+#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
+#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
+#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
+#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
+
+#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
+#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
+#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
+#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
+#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
+
+#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
+#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
+#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
+#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
+#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
+
+#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
+#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
+#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
+#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
+#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
+
+#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
+#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
+#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
+#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
+#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
+
+#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
+#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
+#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
+#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
+#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
+
+#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
+#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
+#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
+
+#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
+
+#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
+#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
+#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
+#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
+#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
+#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
+#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
+#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
+#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
+#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
+#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
+#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
+
+#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
+#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
+
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register echoes some information from the         *
+ * LB_REV_ID register. It is available through Crosstalk as described   *
+ * above. The REV_NUM and MFG_NUM fields receive their values from      *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
+ * The PART_NUM field's value is the Crosstalk device ID number that    *
+ * Steve Miller assigned to the SHub chip.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wid_u {
+	shubreg_t	ii_wid_regval;
+	struct	{
+		shubreg_t	w_rsvd_1		  :	 1;
+		shubreg_t	w_mfg_num		  :	11;
+		shubreg_t	w_part_num		  :	16;
+		shubreg_t	w_rev_num		  :	 4;
+		shubreg_t	w_rsvd			  :	32;
+	} ii_wid_fld_s;
+} ii_wid_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The fields in this register are set upon detection of an error      *
+ * and cleared by various mechanisms, as explained in the               *
+ * description.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wstat_u {
+	shubreg_t	ii_wstat_regval;
+	struct	{
+		shubreg_t	w_pending		  :	 4;
+		shubreg_t	w_xt_crd_to		  :	 1;
+		shubreg_t	w_xt_tail_to		  :	 1;
+		shubreg_t	w_rsvd_3		  :	 3;
+		shubreg_t       w_tx_mx_rty               :      1;
+		shubreg_t	w_rsvd_2		  :	 6;
+		shubreg_t	w_llp_tx_cnt		  :	 8;
+		shubreg_t	w_rsvd_1		  :	 8;
+		shubreg_t	w_crazy			  :	 1;
+		shubreg_t	w_rsvd			  :	31;
+	} ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This is a read-write enabled register. It controls     *
+ * various aspects of the Crosstalk flow control.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wcr_u {
+	shubreg_t	ii_wcr_regval;
+	struct	{
+		shubreg_t	w_wid			  :	 4;
+		shubreg_t	w_tag			  :	 1;
+		shubreg_t	w_rsvd_1		  :	 8;
+		shubreg_t	w_dst_crd		  :	 3;
+		shubreg_t	w_f_bad_pkt		  :	 1;
+		shubreg_t	w_dir_con		  :	 1;
+		shubreg_t	w_e_thresh		  :	 5;
+		shubreg_t	w_rsvd			  :	41;
+	} ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register's value is a bit vector that guards      *
+ * access to local registers within the II as well as to external       *
+ * Crosstalk widgets. Each bit in the register corresponds to a         *
+ * particular region in the system; a region consists of one, two or    *
+ * four nodes (depending on the value of the REGION_SIZE field in the   *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
+ * protection provided by this register applies to PIO read             *
+ * operations as well as PIO write operations. The II will perform a    *
+ * PIO read or write request only if the bit for the requestor's        *
+ * region is set; otherwise, the II will not perform the requested      *
+ * operation and will return an error response. When a PIO read or      *
+ * write request targets an external Crosstalk widget, then not only    *
+ * must the bit for the requestor's region be set in the ILAPR, but     *
+ * also the target widget's bit in the IOWA register must be set in     *
+ * order for the II to perform the requested operation; otherwise,      *
+ * the II will return an error response. Hence, the protection          *
+ * provided by the IOWA register supplements the protection provided    *
+ * by the ILAPR for requests that target external Crosstalk widgets.    *
+ * This register itself can be accessed only by the nodes whose         *
+ * region ID bits are enabled in this same register. It can also be     *
+ * accessed through the IAlias space by the local processors.           *
+ * The reset value of this register allows access by all nodes.         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapr_u {
+	shubreg_t	ii_ilapr_regval;
+	struct  {
+		shubreg_t	i_region                  :	64;
+	} ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A write to this register of the 64-bit value           *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
+ * corresponding to the region of the requestor to be set (allow        *
+ * access). A write of any other value will be ignored. Access          *
+ * protection for this register is "SGIrules".                          *
+ * This register can also be accessed through the IAlias space.         *
+ * However, this access will not change the access permissions in the   *
+ * ILAPR.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapo_u {
+	shubreg_t	ii_ilapo_regval;
+	struct	{
+		shubreg_t	i_io_ovrride            :	64;
+	} ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register qualifies all the PIO and Graphics writes launched    *
+ * from the SHUB towards a widget.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iowa_u {
+	shubreg_t	ii_iowa_regval;
+	struct	{
+		shubreg_t	i_w0_oac		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 7;
+                shubreg_t       i_wx_oac                  :      8;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the requests launched      *
+ * from a widget towards the Shub. This register is intended to be      *
+ * used by software in case of misbehaving widgets.                     *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiwa_u {
+	shubreg_t	ii_iiwa_regval;
+	struct  {
+		shubreg_t	i_w0_iac                  :	 1;
+		shubreg_t	i_rsvd_1		  :	 7;
+		shubreg_t	i_wx_iac		  :	 8;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the operations launched    *
+ * from a widget towards the SHub. It allows individual access          *
+ * control for up to 8 devices per widget. A device refers to           *
+ * individual DMA master hosted by a widget.                            *
+ * The bits in each field of this register are cleared by the Shub      *
+ * upon detection of an error which requires the device to be           *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
+ * Crosstalk). Whether or not a device has access rights to this        *
+ * Shub is determined by an AND of the device enable bit in the         *
+ * appropriate field of this register and the corresponding bit in      *
+ * the Wx_IAC field (for the widget which this device belongs to).      *
+ * The bits in this field are set by writing a 1 to them. Incoming      *
+ * replies from Crosstalk are not subject to this access control        *
+ * mechanism.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidem_u {
+	shubreg_t	ii_iidem_regval;
+	struct	{
+		shubreg_t	i_w8_dxs		  :	 8;
+		shubreg_t	i_w9_dxs		  :	 8;
+		shubreg_t	i_wa_dxs		  :	 8;
+		shubreg_t	i_wb_dxs		  :	 8;
+		shubreg_t	i_wc_dxs		  :	 8;
+		shubreg_t	i_wd_dxs		  :	 8;
+		shubreg_t	i_we_dxs		  :	 8;
+		shubreg_t	i_wf_dxs		  :	 8;
+	} ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the various programmable fields necessary    *
+ * for controlling and observing the LLP signals.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilcsr_u {
+	shubreg_t	ii_ilcsr_regval;
+	struct  {
+		shubreg_t	i_nullto                  :	 6;
+		shubreg_t	i_rsvd_4		  :	 2;
+		shubreg_t	i_wrmrst		  :	 1;
+		shubreg_t	i_rsvd_3		  :	 1;
+		shubreg_t	i_llp_en		  :	 1;
+		shubreg_t	i_bm8			  :	 1;
+		shubreg_t	i_llp_stat		  :	 2;
+		shubreg_t	i_remote_power		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 1;
+		shubreg_t	i_maxrtry		  :	10;
+		shubreg_t	i_d_avail_sel		  :	 2;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_maxbrst		  :	10;
+                shubreg_t       i_rsvd                    :     22;
+
+	} ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This is simply a status registers that monitors the LLP error       *
+ * rate.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_illr_u {
+	shubreg_t	ii_illr_regval;
+	struct	{
+		shubreg_t	i_sn_cnt		  :	16;
+		shubreg_t	i_cb_cnt		  :	16;
+		shubreg_t	i_rsvd			  :	32;
+	} ii_illr_fld_s;
+} ii_illr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  All II-detected non-BTE error interrupts are           *
+ * specified via this register.                                         *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If   *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
+ * packet) to address offset 0x0180_0090 within the local register      *
+ * address space of PI0 on the node specified by the NODE field. If     *
+ * PI_ID==1, then the II sends the interrupt request to address         *
+ * offset 0x01A0_0090 within the local register address space of PI1    *
+ * on the node specified by the NODE field.                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidsr_u {
+	shubreg_t	ii_iidsr_regval;
+	struct  {
+		shubreg_t	i_level                   :	 8;
+		shubreg_t	i_pi_id			  :	 1;
+		shubreg_t	i_node			  :	11;
+		shubreg_t       i_rsvd_3                  :      4;
+		shubreg_t	i_enable		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_int_sent		  :	 1;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t	i_pi0_forward_int	  :	 1;
+		shubreg_t	i_pi1_forward_int	  :	 1;
+		shubreg_t	i_rsvd			  :	30;
+	} ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx0_u {
+	shubreg_t	ii_igfx0_regval;
+	struct	{
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t       i_pi_id                   :      1;
+		shubreg_t	i_n_num			  :	12;
+		shubreg_t       i_p_num                   :      1;
+		shubreg_t       i_rsvd                    :     46;
+	} ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx1_u {
+	shubreg_t	ii_igfx1_regval;
+	struct  {
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t       i_pi_id                   :      1;
+		shubreg_t	i_n_num			  :	12;
+		shubreg_t       i_p_num                   :      1;
+		shubreg_t       i_rsvd                    :     46;
+	} ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr0_u {
+	shubreg_t	ii_iscr0_regval;
+	struct  {
+		shubreg_t	i_scratch                 :	64;
+	} ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr1_u {
+	shubreg_t	ii_iscr1_regval;
+	struct  {
+		shubreg_t	i_scratch                 :	64;
+	} ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       * 
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte1_u {
+	shubreg_t	ii_itte1_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t	i_iosp			  :	 1;
+		shubreg_t	i_rsvd			  :	51;
+	} ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte2_u {
+	shubreg_t	ii_itte2_regval;
+	struct	{
+		shubreg_t	i_offset		  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t	i_iosp			  :	 1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte3_u {
+	shubreg_t	ii_itte3_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte4_u {
+	shubreg_t	ii_itte4_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte5_u {
+	shubreg_t	ii_itte5_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte6_u {
+	shubreg_t	ii_itte6_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte7_u {
+	shubreg_t	ii_itte7_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb0_u {
+	shubreg_t	ii_iprb0_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb8_u {
+	shubreg_t	ii_iprb8_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t       i_rsvd_1                  :      2;
+		shubreg_t       i_m                       :      2;
+		shubreg_t       i_f                       :      1;
+		shubreg_t       i_of_cnt                  :      5;
+		shubreg_t       i_error                   :      1;
+		shubreg_t       i_rd_to                   :      1;
+		shubreg_t       i_spur_wr                 :      1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t       i_rsvd                    :     11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb9_u {
+	shubreg_t	ii_iprb9_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprba_u {
+	shubreg_t	ii_iprba_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbb_u {
+	shubreg_t	ii_iprbb_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbc_u {
+	shubreg_t	ii_iprbc_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbd_u {
+	shubreg_t	ii_iprbd_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbe_u {
+	shubreg_t	ii_iprbe_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Shub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbf_u {
+        shubreg_t       ii_iprbf_regval;
+        struct  {
+                shubreg_t       i_c                       :      8;
+                shubreg_t       i_na                      :     14;
+                shubreg_t       i_rsvd_2                  :      2;
+                shubreg_t       i_nb                      :     14;
+                shubreg_t       i_rsvd_1                  :      2;
+                shubreg_t       i_m                       :      2;
+                shubreg_t       i_f                       :      1;
+                shubreg_t       i_of_cnt                  :      5;
+                shubreg_t       i_error                   :      1;
+                shubreg_t       i_rd_to                   :      1;
+                shubreg_t       i_spur_wr                 :      1;
+                shubreg_t       i_spur_rd                 :      1;
+                shubreg_t       i_rsvd                    :     11;
+                shubreg_t       i_mult_err                :      1;
+        } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register specifies the timeout value to use for monitoring     *
+ * Crosstalk credits which are used outbound to Crosstalk. An           *
+ * internal counter called the Crosstalk Credit Timeout Counter         *
+ * increments every 128 II clocks. The counter starts counting          *
+ * anytime the credit count drops below a threshold, and resets to      *
+ * zero (stops counting) anytime the credit count is at or above the    *
+ * threshold. The threshold is 1 credit in direct connect mode and 2    *
+ * in Crossbow connect mode. When the internal Crosstalk Credit         *
+ * Timeout Counter reaches the value programmed in this register, a     *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not   *
+ * readable from software, and stops counting at its maximum value,     *
+ * so it cannot cause more than one interrupt.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixcc_u {
+	shubreg_t	ii_ixcc_regval;
+	struct  {
+		shubreg_t	i_time_out                :	26;
+		shubreg_t	i_rsvd			  :	38;
+	} ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the PIO and DMA            *
+ * operations launched from widget 0 towards the SHub. In               *
+ * addition, it also qualifies accesses by the BTE streams.             *
+ * The bits in each field of this register are cleared by the SHub      *
+ * upon detection of an error which requires widget 0 or the BTE        *
+ * streams to be terminated. Whether or not widget x has access         *
+ * rights to this SHub is determined by an AND of the device            *
+ * enable bit in the appropriate field of this register and bit 0 in    *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
+ * them. Incoming replies from Crosstalk are not subject to this        *
+ * access control mechanism.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_imem_u {
+	shubreg_t	ii_imem_regval;
+	struct  {
+		shubreg_t	i_w0_esd                  :	 1;
+		shubreg_t	i_rsvd_3		  :	 3;
+		shubreg_t	i_b0_esd		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_b1_esd		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_clr_precise		  :	 1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_imem_fld_s;
+} ii_imem_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register specifies the timeout value to use for   *
+ * monitoring Crosstalk tail flits coming into the Shub in the          *
+ * TAIL_TO field. An internal counter associated with this register     *
+ * is incremented every 128 II internal clocks (7 bits). The counter    *
+ * starts counting anytime a header micropacket is received and stops   *
+ * counting (and resets to zero) any time a micropacket with a Tail     *
+ * bit is received. Once the counter reaches the threshold value        *
+ * programmed in this register, it generates an interrupt to the        *
+ * processor that is programmed into the IIDSR. The counter saturates   *
+ * (does not roll over) at its maximum value, so it cannot cause        *
+ * another interrupt until after it is cleared.                         *
+ * The register also contains the Read Response Timeout values. The     *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter      *
+ * increments on every II clock and when it reaches the value in the    *
+ * Prescalar field, all IPRTE registers with their valid bits set       *
+ * have their Read Response timers bumped. Whenever any of them match   *
+ * the value in the RRSP_TO field, a Read Response Timeout has          *
+ * occurred, and error handling occurs as described in the Error        *
+ * Handling section of this document.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixtt_u {
+	shubreg_t	ii_ixtt_regval;
+	struct  {
+		shubreg_t	i_tail_to                 :	26;
+		shubreg_t	i_rsvd_1		  :	 6;
+		shubreg_t	i_rrsp_ps		  :	23;
+		shubreg_t	i_rrsp_to		  :	 5;
+		shubreg_t	i_rsvd			  :	 4;
+	} ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing a 1 to the fields of this register clears the appropriate   *
+ * error bits in other areas of SHub. Note that when the                *
+ * E_PRB_x bits are used to clear error bits in PRB registers,          *
+ * SPUR_RD and SPUR_WR may persist, because they require additional     *
+ * action to clear them. See the IPRBx and IXSS Register                *
+ * specifications.                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ieclr_u {
+	shubreg_t	ii_ieclr_regval;
+	struct  {
+		shubreg_t	i_e_prb_0                 :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_e_prb_8		  :	 1;
+		shubreg_t	i_e_prb_9		  :	 1;
+		shubreg_t	i_e_prb_a		  :	 1;
+		shubreg_t	i_e_prb_b		  :	 1;
+		shubreg_t	i_e_prb_c		  :	 1;
+		shubreg_t	i_e_prb_d		  :	 1;
+		shubreg_t	i_e_prb_e		  :	 1;
+		shubreg_t	i_e_prb_f		  :	 1;
+		shubreg_t	i_e_crazy		  :	 1;
+		shubreg_t	i_e_bte_0		  :	 1;
+		shubreg_t	i_e_bte_1		  :	 1;
+		shubreg_t	i_reserved_1		  :	10;
+		shubreg_t	i_spur_rd_hdr		  :	 1;
+		shubreg_t	i_cam_intr_to		  :	 1;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_ii_xn_rep_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_req_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_reserved_2		  :	21;
+	} ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls both BTEs. SOFT_RESET is intended for        *
+ * recovery after an error. COUNT controls the total number of CRBs     *
+ * that both BTEs (combined) can use, which affects total BTE           *
+ * bandwidth.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibcr_u {
+	shubreg_t	ii_ibcr_regval;
+	struct  {
+		shubreg_t	i_count                   :	 4;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_soft_reset		  :	 1;
+		shubreg_t	i_rsvd			  :	55;
+	} ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the header of a spurious read response       *
+ * received from Crosstalk. A spurious read response is defined as a    *
+ * read response received by II from a widget for which (1) the SIDN    *
+ * has a value between 1 and 7, inclusive (II never sends requests to   *
+ * these widgets (2) there is no valid IPRTE register which             *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
+ * not the same as the widget recorded in the IPRTE register            *
+ * referenced by the TNUM. If this condition is true, and if the        *
+ * IXSS[VALID] bit is clear, then the header of the spurious read       *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
+ * errant header is thereby captured, and no further spurious read      *
+ * respones are captured until IXSS[VALID] is cleared by setting the    *
+ * appropriate bit in IECLR.Everytime a spurious read response is       *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
+ * message's SIDN field is set. This always happens, regarless of       *
+ * whether a header is captured. The programmer should check            *
+ * IXSM[SIDN] to determine which widget sent the spurious response,     *
+ * because there may be more than one SPUR_RD bit set in the PRB        *
+ * registers. The widget indicated by IXSM[SIDN] was the first          *
+ * spurious read response to be received since the last time            *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
+ * spurious messages from other widets which were detected after the    *
+ * header was captured..                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixsm_u {
+	shubreg_t	ii_ixsm_regval;
+	struct  {
+		shubreg_t	i_byte_en                 :	32;
+		shubreg_t	i_reserved		  :	 1;
+		shubreg_t	i_tag			  :	 3;
+		shubreg_t	i_alt_pactyp		  :	 4;
+		shubreg_t	i_bo			  :	 1;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_vbpm			  :	 1;
+		shubreg_t	i_gbr			  :	 1;
+		shubreg_t	i_ds			  :	 2;
+		shubreg_t	i_ct			  :	 1;
+		shubreg_t	i_tnum			  :	 5;
+		shubreg_t	i_pactyp		  :	 4;
+		shubreg_t	i_sidn			  :	 4;
+		shubreg_t	i_didn			  :	 4;
+	} ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the sideband bits of a spurious read         *
+ * response received from Crosstalk.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixss_u {
+	shubreg_t	ii_ixss_regval;
+	struct  {
+		shubreg_t	i_sideband                :	 8;
+		shubreg_t	i_rsvd			  :	55;
+		shubreg_t	i_valid			  :	 1;
+	} ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to access the II LLP's test port.    *
+ * Refer to the LLP 2.5 documentation for an explanation of the test    *
+ * port. Software can write to this register to program the values      *
+ * for the control fields (TestErrCapture, TestClear, TestFlit,         *
+ * TestMask and TestSeed). Similarly, software can read from this       *
+ * register to obtain the values of the test port's status outputs      *
+ * (TestCBerr, TestValid and TestData).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilct_u {
+	shubreg_t	ii_ilct_regval;
+	struct  {
+		shubreg_t	i_test_seed               :	20;
+		shubreg_t	i_test_mask               :	 8;
+		shubreg_t	i_test_data               :	20;
+		shubreg_t	i_test_valid              :	 1;
+		shubreg_t	i_test_cberr              :	 1;
+		shubreg_t	i_test_flit               :	 3;
+		shubreg_t	i_test_clear              :	 1;
+		shubreg_t	i_test_err_capture        :	 1;
+		shubreg_t	i_rsvd                    :	 9;
+	} ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  If the II detects an illegal incoming Duplonet packet (request or   *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
+ * and assigns a value to the ERR_TYPE field which indicates the        *
+ * specific nature of the error. The II recognizes four different       *
+ * types of errors: short request packets (ERR_TYPE==2), short reply    *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
+ * reply packets (ERR_TYPE==5). The encodings for these types of        *
+ * errors were chosen to be consistent with the same types of errors    *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
+ * the LB unit). If the II detects an illegal incoming Duplonet         *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
+ * the OVERRUN bit to indicate that a subsequent error has happened,    *
+ * and does nothing further.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph1_u {
+	shubreg_t	ii_iieph1_regval;
+	struct	{
+		shubreg_t	i_command		  :	 7;
+		shubreg_t	i_rsvd_5		  :	 1;
+		shubreg_t	i_suppl			  :	14;
+		shubreg_t	i_rsvd_4		  :	 1;
+		shubreg_t	i_source		  :	14;
+		shubreg_t	i_rsvd_3		  :	 1;
+		shubreg_t	i_err_type		  :	 4;
+		shubreg_t	i_rsvd_2		  :	 4;
+		shubreg_t	i_overrun		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_valid			  :	 1;
+		shubreg_t	i_rsvd			  :	13;
+	} ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register holds the Address field from the header flit of an    *
+ * incoming erroneous Duplonet packet, along with the tail bit which    *
+ * accompanied this header flit. This register is essentially an        *
+ * extension of IIEPH1. Two registers were necessary because the 64     *
+ * bits available in only a single register were insufficient to        *
+ * capture the entire header flit of an erroneous packet.               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph2_u {
+	shubreg_t	ii_iieph2_regval;
+	struct  {
+		shubreg_t	i_rsvd_0		  :	 3;
+		shubreg_t	i_address                 :	47;
+		shubreg_t	i_rsvd_1		  :	10;
+		shubreg_t	i_tail			  :	 1;
+		shubreg_t	i_rsvd			  :	 3;
+	} ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+
+/******************************/
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register's value is a bit vector that guards access from SXBs  *
+ * to local registers within the II as well as to external Crosstalk    *
+ * widgets								*
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapr_u {
+	shubreg_t	ii_islapr_regval;
+	struct  {
+		shubreg_t	i_region		  :	64;
+	} ii_islapr_fld_s;
+} ii_islapr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register of the 56-bit value "Pup+Bun" will cause	*
+ * the bit in the ISLAPR register corresponding to the region of the	*
+ * requestor to be set (access allowed).				(
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapo_u {
+	shubreg_t	ii_islapo_regval;
+	struct  {
+		shubreg_t	i_io_sbx_ovrride	  :	56;
+		shubreg_t	i_rsvd			  :	 8;
+	} ii_islapo_fld_s;
+} ii_islapo_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Determines how long the wrapper will wait aftr an interrupt is	*
+ * initially issued from the II before it times out the outstanding	*
+ * interrupt and drops it from the interrupt queue.			* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwi_u {
+	shubreg_t	ii_iwi_regval;
+	struct  {
+		shubreg_t	i_prescale		  :	24;
+		shubreg_t	i_rsvd			  :	 8;
+		shubreg_t	i_timeout		  :	 8;
+		shubreg_t	i_rsvd1			  :	 8;
+		shubreg_t	i_intrpt_retry_period	  :	 8;
+		shubreg_t	i_rsvd2			  :	 8;
+	} ii_iwi_fld_s;
+} ii_iwi_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Log errors which have occurred in the II wrapper. The errors are	*
+ * cleared by writing to the IECLR register.				* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwel_u {
+	shubreg_t	ii_iwel_regval;
+	struct  {
+		shubreg_t	i_intr_timed_out	  :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_rsvd1			  :	 2;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_rsvd2			  :	 6;
+		shubreg_t	i_ii_xn_rep_cred_over_under:	 1;
+		shubreg_t	i_ii_xn_req_cred_over_under:	 1;
+		shubreg_t	i_rsvd3			  :	 6;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_rsvd4			  :	30;
+	} ii_iwel_fld_s;
+} ii_iwel_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the II wrapper.						* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwc_u {
+	shubreg_t	ii_iwc_regval;
+	struct  {
+		shubreg_t	i_dma_byte_swap		  :	 1;
+		shubreg_t	i_rsvd			  :	 3;
+		shubreg_t	i_cam_read_lines_reset	  :	 1;
+		shubreg_t	i_rsvd1			  :	 3;
+		shubreg_t	i_ii_xn_cred_over_under_log:	 1;
+		shubreg_t	i_rsvd2			  :	19;
+		shubreg_t	i_xn_rep_iq_depth	  :	 5;
+		shubreg_t	i_rsvd3			  :	 3;
+		shubreg_t	i_xn_req_iq_depth	  :	 5;
+		shubreg_t	i_rsvd4			  :	 3;
+		shubreg_t	i_iiq_depth		  :	 6;
+		shubreg_t	i_rsvd5			  :	12;
+		shubreg_t	i_force_rep_cred	  :	 1;
+		shubreg_t	i_force_req_cred	  :	 1;
+	} ii_iwc_fld_s;
+} ii_iwc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Status in the II wrapper.						* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iws_u {
+	shubreg_t	ii_iws_regval;
+	struct  {
+		shubreg_t	i_xn_rep_iq_credits	  :	 5;
+		shubreg_t	i_rsvd			  :	 3;
+		shubreg_t	i_xn_req_iq_credits	  :	 5;
+		shubreg_t	i_rsvd1			  :	51;
+	} ii_iws_fld_s;
+} ii_iws_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Masks errors in the IWEL register.					*
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iweim_u {
+	shubreg_t	ii_iweim_regval;
+	struct  {
+		shubreg_t	i_intr_timed_out	  :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_rsvd1			  :	 2;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_rsvd2			  :	 6;
+		shubreg_t	i_ii_xn_rep_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_req_cred_overflow :	 1;
+		shubreg_t	i_rsvd3			  :	 6;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_rsvd4			  :	30;
+	} ii_iweim_fld_s;
+} ii_iweim_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a particular field in the           *
+ * corresponding widget's PRB entry to be adjusted up or down by 1.     *
+ * This counter should be used when recovering from error and reset     *
+ * conditions. Note that software would be capable of causing           *
+ * inadvertent overflow or underflow of these counters.                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipca_u {
+	shubreg_t	ii_ipca_regval;
+	struct  {
+		shubreg_t	i_wid                     :	 4;
+		shubreg_t	i_adjust		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_field			  :	 2;
+		shubreg_t	i_rsvd			  :	54;
+	} ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0a_u {
+	shubreg_t	ii_iprte0a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte0a_fld_s;
+} ii_iprte0a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1a_u {
+	shubreg_t	ii_iprte1a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte1a_fld_s;
+} ii_iprte1a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2a_u {
+	shubreg_t	ii_iprte2a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte2a_fld_s;
+} ii_iprte2a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3a_u {
+	shubreg_t	ii_iprte3a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte3a_fld_s;
+} ii_iprte3a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4a_u {
+	shubreg_t	ii_iprte4a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte4a_fld_s;
+} ii_iprte4a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5a_u {
+	shubreg_t	ii_iprte5a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte5a_fld_s;
+} ii_iprte5a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6a_u {
+	shubreg_t	ii_iprte6a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte6a_fld_s;
+} ii_iprte6a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7a_u {
+        shubreg_t       ii_iprte7a_regval;
+        struct  {
+                shubreg_t       i_rsvd_1                  :     54;
+                shubreg_t       i_widget                  :      4;
+                shubreg_t       i_to_cnt                  :      5;
+                shubreg_t       i_vld                     :      1;
+        } ii_iprtea7_fld_s;
+} ii_iprte7a_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0b_u {
+	shubreg_t	ii_iprte0b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte0b_fld_s;
+} ii_iprte0b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1b_u {
+	shubreg_t	ii_iprte1b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte1b_fld_s;
+} ii_iprte1b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2b_u {
+	shubreg_t	ii_iprte2b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte2b_fld_s;
+} ii_iprte2b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3b_u {
+	shubreg_t	ii_iprte3b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte3b_fld_s;
+} ii_iprte3b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4b_u {
+	shubreg_t	ii_iprte4b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte4b_fld_s;
+} ii_iprte4b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5b_u {
+	shubreg_t	ii_iprte5b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte5b_fld_s;
+} ii_iprte5b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6b_u {
+	shubreg_t	ii_iprte6b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+
+	} ii_iprte6b_fld_s;
+} ii_iprte6b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7b_u {
+        shubreg_t       ii_iprte7b_regval;
+        struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+        } ii_iprte7b_fld_s;
+} ii_iprte7b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  SHub II contains a feature which did not exist in      *
+ * the Hub which automatically cleans up after a Read Response          *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf    *
+ * space. The inclusion of this register in SHub is for backward        *
+ * compatibility                                                        *
+ * A write to this register causes an entry from the table of           *
+ * outstanding PIO Read Requests to be freed and returned to the        *
+ * stack of free entries. This register is used in handling the         *
+ * timeout errors that result in a PIO Reply never returning from       *
+ * Crosstalk.                                                           *
+ * Note that this register does not affect the contents of the IPRTE    *
+ * registers. The Valid bits in those registers have to be              *
+ * specifically turned off by software.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipdr_u {
+	shubreg_t	ii_ipdr_regval;
+	struct  {
+		shubreg_t	i_te                      :	 3;
+		shubreg_t	i_rsvd_1		  :	 1;
+		shubreg_t	i_pnd			  :	 1;
+		shubreg_t	i_init_rpcnt		  :	 1;
+		shubreg_t	i_rsvd			  :	58;
+	} ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a CRB entry to be returned to the   *
+ * queue of free CRBs. The entry should have previously been cleared    *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *
+ * register is used in the last step of handling the errors that are    *
+ * captured and marked in CRB entries.  Briefly: 1) first error for     *
+ * DMA write from a particular device, and first error for a            *
+ * particular BTE stream, lead to a marked CRB entry, and processor     *
+ * interrupt, 2) software reads the error information captured in the   *
+ * CRB entry, and presumably takes some corrective action, 3)           *
+ * software clears the mark bit, and finally 4) software writes to      *
+ * the ICDR register to return the CRB entry to the list of free CRB    *
+ * entries.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icdr_u {
+	shubreg_t	ii_icdr_regval;
+	struct  {
+		shubreg_t	i_crb_num                 :	 4;
+		shubreg_t	i_pnd			  :	 1;
+		shubreg_t       i_rsvd                    :     59;
+	} ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides debug access to two FIFOs inside of II.      *
+ * Both IOQ_MAX* fields of this register contain the instantaneous      *
+ * depth (in units of the number of available entries) of the           *
+ * associated IOQ FIFO.  A read of this register will return the        *
+ * number of free entries on each FIFO at the time of the read.  So     *
+ * when a FIFO is idle, the associated field contains the maximum       *
+ * depth of the FIFO.  This register is writable for debug reasons      *
+ * and is intended to be written with the maximum desired FIFO depth    *
+ * while the FIFO is idle. Software must assure that II is idle when    *
+ * this register is written. If there are any active entries in any     *
+ * of these FIFOs when this register is written, the results are        *
+ * undefined.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ifdr_u {
+	shubreg_t	ii_ifdr_regval;
+	struct  {
+		shubreg_t	i_ioq_max_rq              :	 7;
+		shubreg_t	i_set_ioq_rq		  :	 1;
+		shubreg_t	i_ioq_max_rp		  :	 7;
+		shubreg_t	i_set_ioq_rp		  :	 1;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the II to become sluggish in removing          *
+ * messages from its inbound queue (IIQ). This will cause messages to   *
+ * back up in either virtual channel. Disabling the "molasses" mode     *
+ * subsequently allows the II to be tested under stress. In the         *
+ * sluggish ("Molasses") mode, the localized effects of congestion      *
+ * can be observed.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiap_u {
+        shubreg_t       ii_iiap_regval;
+        struct  {
+                shubreg_t       i_rq_mls                  :      6;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_rp_mls		  :	 6;
+		shubreg_t       i_rsvd                    :     50;
+        } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows several parameters of CRB operation to be      *
+ * set. Note that writing to this register can have catastrophic side   *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is             *
+ * processing protocol messages when the write occurs.                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icmr_u {
+	shubreg_t	ii_icmr_regval;
+	struct  {
+		shubreg_t	i_sp_msg                  :	 1;
+		shubreg_t	i_rd_hdr		  :	 1;
+		shubreg_t	i_rsvd_4		  :	 2;
+		shubreg_t	i_c_cnt			  :	 4;
+		shubreg_t	i_rsvd_3		  :	 4;
+		shubreg_t	i_clr_rqpd		  :	 1;
+		shubreg_t	i_clr_rppd		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_fc_cnt		  :	 4;
+		shubreg_t	i_crb_vld		  :	15;
+		shubreg_t	i_crb_mark		  :	15;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_precise		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+	} ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows control of the table portion of the CRB        *
+ * logic via software. Control operations from this register have       *
+ * priority over all incoming Crosstalk or BTE requests.                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iccr_u {
+	shubreg_t	ii_iccr_regval;
+	struct  {
+		shubreg_t	i_crb_num                 :	 4;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_cmd			  :	 8;
+		shubreg_t	i_pending		  :	 1;
+		shubreg_t	i_rsvd			  :	47;
+	} ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the maximum timeout value to be programmed.    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icto_u {
+	shubreg_t	ii_icto_regval;
+	struct  {
+		shubreg_t	i_timeout                 :	 8;
+		shubreg_t	i_rsvd			  :	56;
+	} ii_icto_fld_s;
+} ii_icto_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the timeout prescalar to be programmed. An     *
+ * internal counter is associated with this register. When the          *
+ * internal counter reaches the value of the PRESCALE field, the        *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
+ * field). The internal counter resets to zero, and then continues      *
+ * counting.                                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ictp_u {
+	shubreg_t	ii_ictp_regval;
+	struct  {
+		shubreg_t	i_prescale                :	24;
+		shubreg_t	i_rsvd			  :	40;
+	} ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ * The CRB Entry registers can be conceptualized as rows and columns    *
+ * (illustrated in the table above). Each row contains the 4            *
+ * registers required for a single CRB Entry. The first doubleword      *
+ * (column) for each entry is labeled A, and the second doubleword      *
+ * (higher address) is labeled B, the third doubleword is labeled C,    *
+ * the fourth doubleword is labeled D and the fifth doubleword is       *
+ * labeled E. All CRB entries have their addresses on a quarter         *
+ * cacheline aligned boundary.                   *
+ * Upon reset, only the following fields are initialized: valid         *
+ * (VLD), priority count, timeout, timeout valid, and context valid.    *
+ * All other bits should be cleared by software before use (after       *
+ * recovering any potential error state from before the reset).         *
+ * The following four tables summarize the format for the four          *
+ * registers that are used for each ICRB# Entry.                        *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_a_u {
+	shubreg_t	ii_icrb0_a_regval;
+	struct  {
+		shubreg_t	ia_iow                    :	 1;
+		shubreg_t	ia_vld			  :	 1;
+		shubreg_t	ia_addr			  :	47;
+		shubreg_t	ia_tnum			  :	 5;
+		shubreg_t	ia_sidn			  :	 4;
+		shubreg_t       ia_rsvd                   :      6;
+	} ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_b_u {
+	shubreg_t	ii_icrb0_b_regval;
+	struct	{
+		shubreg_t	ib_xt_err		  :	 1;
+		shubreg_t	ib_mark			  :	 1;
+		shubreg_t	ib_ln_uce		  :	 1;
+		shubreg_t	ib_errcode		  :	 3;
+		shubreg_t	ib_error		  :	 1;
+		shubreg_t	ib_stall__bte_1		  :	 1;
+		shubreg_t	ib_stall__bte_0		  :	 1;
+		shubreg_t	ib_stall__intr		  :	 1;
+		shubreg_t	ib_stall_ib		  :	 1;
+		shubreg_t	ib_intvn		  :	 1;
+		shubreg_t	ib_wb			  :	 1;
+		shubreg_t	ib_hold			  :	 1;
+		shubreg_t	ib_ack			  :	 1;
+		shubreg_t	ib_resp			  :	 1;
+		shubreg_t	ib_ack_cnt		  :	11;
+		shubreg_t	ib_rsvd			  :	 7;
+		shubreg_t	ib_exc			  :	 5;
+		shubreg_t	ib_init			  :	 3;
+		shubreg_t	ib_imsg			  :	 8;
+		shubreg_t	ib_imsgtype		  :	 2;
+		shubreg_t	ib_use_old		  :	 1;
+		shubreg_t	ib_rsvd_1		  :	11;
+	} ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_c_u {
+	shubreg_t	ii_icrb0_c_regval;
+	struct	{
+		shubreg_t	ic_source		  :	15;
+		shubreg_t	ic_size			  :	 2;
+		shubreg_t	ic_ct			  :	 1;
+		shubreg_t	ic_bte_num		  :	 1;
+		shubreg_t	ic_gbr			  :	 1;
+		shubreg_t	ic_resprqd		  :	 1;
+		shubreg_t	ic_bo			  :	 1;
+		shubreg_t	ic_suppl		  :	15;
+		shubreg_t	ic_rsvd			  :	27;
+	} ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_d_u {
+	shubreg_t	ii_icrb0_d_regval;
+	struct  {
+		shubreg_t	id_pa_be                  :	43;
+		shubreg_t	id_bte_op		  :	 1;
+		shubreg_t	id_pr_psc		  :	 4;
+		shubreg_t	id_pr_cnt		  :	 4;
+		shubreg_t	id_sleep		  :	 1;
+		shubreg_t	id_rsvd			  :	11;
+	} ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_e_u {
+	shubreg_t	ii_icrb0_e_regval;
+	struct  {
+		shubreg_t	ie_timeout                :	 8;
+		shubreg_t	ie_context		  :	15;
+		shubreg_t	ie_rsvd			  :	 1;
+		shubreg_t	ie_tvld			  :	 1;
+		shubreg_t	ie_cvld			  :	 1;
+		shubreg_t	ie_rsvd_0		  :	38;
+	} ii_icrb0_e_fld_s;
+} ii_icrb0_e_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the lower 64 bits of the header of the       *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsml_u {
+	shubreg_t	ii_icsml_regval;
+	struct  {
+		shubreg_t	i_tt_addr                 :	47;
+		shubreg_t	i_newsuppl_ex		  :	14;
+		shubreg_t	i_reserved		  :	 2;
+		shubreg_t       i_overflow                :      1;
+	} ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the middle 64 bits of the header of the      *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmm_u {
+	shubreg_t	ii_icsmm_regval;
+	struct  {
+		shubreg_t	i_tt_ack_cnt              :	11;
+		shubreg_t	i_reserved		  :	53;
+	} ii_icsmm_fld_s;
+} ii_icsmm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the microscopic state, all the inputs to     *
+ * the protocol table, captured with the spurious message. Valid when   *
+ * the SP_MSG bit in the ICMR register is set.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmh_u {
+	shubreg_t	ii_icsmh_regval;
+	struct  {
+		shubreg_t	i_tt_vld                  :	 1;
+		shubreg_t	i_xerr			  :	 1;
+		shubreg_t	i_ft_cwact_o		  :	 1;
+		shubreg_t	i_ft_wact_o		  :	 1;
+		shubreg_t       i_ft_active_o             :      1;
+		shubreg_t	i_sync			  :	 1;
+		shubreg_t	i_mnusg			  :	 1;
+		shubreg_t	i_mnusz			  :	 1;
+		shubreg_t	i_plusz			  :	 1;
+		shubreg_t	i_plusg			  :	 1;
+		shubreg_t	i_tt_exc		  :	 5;
+		shubreg_t	i_tt_wb			  :	 1;
+		shubreg_t	i_tt_hold		  :	 1;
+		shubreg_t	i_tt_ack		  :	 1;
+		shubreg_t	i_tt_resp		  :	 1;
+		shubreg_t	i_tt_intvn		  :	 1;
+		shubreg_t	i_g_stall_bte1		  :	 1;
+		shubreg_t	i_g_stall_bte0		  :	 1;
+		shubreg_t	i_g_stall_il		  :	 1;
+		shubreg_t	i_g_stall_ib		  :	 1;
+		shubreg_t	i_tt_imsg		  :	 8;
+		shubreg_t	i_tt_imsgtype		  :	 2;
+		shubreg_t	i_tt_use_old		  :	 1;
+		shubreg_t	i_tt_respreqd		  :	 1;
+		shubreg_t	i_tt_bte_num		  :	 1;
+		shubreg_t	i_cbn			  :	 1;
+		shubreg_t	i_match			  :	 1;
+		shubreg_t	i_rpcnt_lt_34		  :	 1;
+		shubreg_t	i_rpcnt_ge_34		  :	 1;
+		shubreg_t	i_rpcnt_lt_18		  :	 1;
+		shubreg_t	i_rpcnt_ge_18		  :	 1;
+		shubreg_t       i_rpcnt_lt_2              :      1;
+		shubreg_t	i_rpcnt_ge_2		  :	 1;
+		shubreg_t	i_rqcnt_lt_18		  :	 1;
+		shubreg_t	i_rqcnt_ge_18		  :	 1;
+		shubreg_t	i_rqcnt_lt_2		  :	 1;
+		shubreg_t	i_rqcnt_ge_2		  :	 1;
+		shubreg_t	i_tt_device		  :	 7;
+		shubreg_t	i_tt_init		  :	 3;
+		shubreg_t	i_reserved		  :	 5;
+	} ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
+ * II core and a 3-bit selection signal to the fsbclk domain in the II  *
+ * wrapper.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_idbss_u {
+	shubreg_t	ii_idbss_regval;
+	struct  {
+		shubreg_t	i_iioclk_core_submenu     :	 3;
+		shubreg_t	i_rsvd			  :	 5;
+		shubreg_t	i_fsbclk_wrapper_submenu  :	 3;
+		shubreg_t	i_rsvd_1		  :	 5;
+		shubreg_t	i_iioclk_menu		  :	 5;
+		shubreg_t	i_rsvd_2		  :	43;
+	} ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls0_u {
+	shubreg_t	ii_ibls0_regval;
+	struct	{
+		shubreg_t	i_length		  :	16;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_busy			  :	 1;
+		shubreg_t       i_rsvd                    :     43;
+	} ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa0_u {
+	shubreg_t	ii_ibsa0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t       i_rsvd                    :     15;
+	} ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda0_u {
+	shubreg_t	ii_ibda0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t	i_rsvd			  :	15;
+	} ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct0_u {
+	shubreg_t	ii_ibct0_regval;
+	struct  {
+		shubreg_t	i_zerofill                :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_notify		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_poison                  :      1;
+		shubreg_t       i_rsvd                    :     55;
+	} ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna0_u {
+	shubreg_t	ii_ibna0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t	i_rsvd			  :	15;
+	} ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia0_u {
+	shubreg_t	ii_ibia0_regval;
+	struct  {
+		shubreg_t	i_rsvd_2                   :	 1;
+		shubreg_t	i_node_id		  :	11;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_level			  :	 7;
+		shubreg_t       i_rsvd                    :     41;
+	} ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls1_u {
+	shubreg_t	ii_ibls1_regval;
+	struct  {
+		shubreg_t	i_length                  :	16;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_busy			  :	 1;
+		shubreg_t       i_rsvd                    :     43;
+	} ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa1_u {
+	shubreg_t	ii_ibsa1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t	i_rsvd			  :	24;
+	} ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda1_u {
+	shubreg_t	ii_ibda1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t	i_rsvd			  :	24;
+	} ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct1_u {
+	shubreg_t	ii_ibct1_regval;
+	struct  {
+		shubreg_t	i_zerofill                :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_notify		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_poison		  :	 1;
+		shubreg_t	i_rsvd			  :	55;
+	} ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna1_u {
+	shubreg_t	ii_ibna1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t       i_rsvd                    :     24;
+	} ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia1_u {
+	shubreg_t	ii_ibia1_regval;
+	struct  {
+		shubreg_t	i_pi_id                   :	 1;
+		shubreg_t	i_node_id		  :	 8;
+		shubreg_t	i_rsvd_1		  :	 7;
+		shubreg_t	i_level			  :	 7;
+		shubreg_t	i_rsvd			  :	41;
+	} ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register defines the resources that feed information into      *
+ * the two performance counters located in the IO Performance           *
+ * Profiling Register. There are 17 different quantities that can be    *
+ * measured. Given these 17 different options, the two performance      *
+ * counters have 15 of them in common; menu selections 0 through 0xE    *
+ * are identical for each performance counter. As for the other two     *
+ * options, one is available from one performance counter and the       *
+ * other is available from the other performance counter. Hence, the    *
+ * II supports all 17*16=272 possible combinations of quantities to     *
+ * measure.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipcr_u {
+	shubreg_t	ii_ipcr_regval;
+	struct  {
+		shubreg_t	i_ippr0_c                 :	 4;
+		shubreg_t	i_ippr1_c		  :	 4;
+		shubreg_t	i_icct			  :	 8;
+		shubreg_t       i_rsvd                    :     48;
+	} ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ippr_u {
+	shubreg_t	ii_ippr_regval;
+	struct  {
+		shubreg_t	i_ippr0                   :	32;
+		shubreg_t	i_ippr1			  :	32;
+	} ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+
+#endif /* __ASSEMBLY__ */
+
+/**************************************************************************
+ *                                                                        *
+ * The following defines which were not formed into structures are        *
+ * probably indentical to another register, and the name of the           *
+ * register is provided against each of these registers. This             *
+ * information needs to be checked carefully                              *
+ *                                                                        *
+ *           IIO_ICRB1_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB1_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB1_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB1_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB1_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB2_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB2_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB2_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB2_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB2_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB3_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB3_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB3_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB3_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB3_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB4_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB4_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB4_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB4_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB4_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB5_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB5_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB5_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB5_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB5_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB6_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB6_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB6_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB6_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB6_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB7_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB7_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB7_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB7_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB7_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB8_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB8_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB8_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB8_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB8_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB9_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB9_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB9_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB9_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB9_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBA_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBA_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBA_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBA_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBA_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBB_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBB_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBB_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBB_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBB_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBC_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBC_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBC_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBC_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBC_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBD_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBD_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBD_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBD_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBD_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBE_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBE_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBE_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBE_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBE_E                IIO_ICRB0_E                       *
+ *                                                                        *
+ **************************************************************************/
+
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_IGFX_0 		IIO_IGFX0
+#define IIO_IGFX_1 		IIO_IGFX1
+#define IIO_IBCT_0		IIO_IBCT0
+#define IIO_IBCT_1		IIO_IBCT1
+#define IIO_IBLS_0		IIO_IBLS0
+#define IIO_IBLS_1		IIO_IBLS1
+#define IIO_IBSA_0		IIO_IBSA0
+#define IIO_IBSA_1		IIO_IBSA1
+#define IIO_IBDA_0		IIO_IBDA0
+#define IIO_IBDA_1		IIO_IBDA1
+#define IIO_IBNA_0		IIO_IBNA0
+#define IIO_IBNA_1		IIO_IBNA1
+#define IIO_IBIA_0		IIO_IBIA0
+#define IIO_IBIA_1		IIO_IBIA1
+#define IIO_IOPRB_0		IIO_IPRB0
+
+#define IIO_PRTE_A(_x)		(IIO_IPRTE0_A + (8 * (_x)))
+#define IIO_PRTE_B(_x)		(IIO_IPRTE0_B + (8 * (_x)))
+#define IIO_NUM_PRTES		8	/* Total number of PRB table entries */
+#define IIO_WIDPRTE_A(x)	IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)	IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+
+#define IIO_NUM_IPRBS 		(9) 
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+#define IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   	IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/* names used in shub diags */
+#define IIO_BASE_BTE0   IIO_IBLS_0		
+#define IIO_BASE_BTE1   IIO_IBLS_1		
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS	4	/* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT	0
+#define IIO_IGFX_PI_NUM_BITS	1	/* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT	4
+#define IIO_IGFX_N_NUM_BITS	8	/* size of node num field */
+#define IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT	5
+#define IIO_IGFX_P_NUM_BITS	1	/* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT	16
+#define IIO_IGFX_INIT(widget, pi, node, cpu)				(\
+	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \
+	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \
+	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \
+	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0        IIO_ISCR0
+#define IIO_SCRATCH_REG1        IIO_ISCR1
+#define IIO_SCRATCH_MASK        0xffffffffffffffff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000000000001
+#define IIO_SCRATCH_BIT0_1      0x0000000000000002
+#define IIO_SCRATCH_BIT0_2      0x0000000000000004
+#define IIO_SCRATCH_BIT0_3      0x0000000000000008
+#define IIO_SCRATCH_BIT0_4      0x0000000000000010
+#define IIO_SCRATCH_BIT0_5      0x0000000000000020
+#define IIO_SCRATCH_BIT0_6      0x0000000000000040
+#define IIO_SCRATCH_BIT0_7      0x0000000000000080
+#define IIO_SCRATCH_BIT0_8      0x0000000000000100
+#define IIO_SCRATCH_BIT0_9      0x0000000000000200
+#define IIO_SCRATCH_BIT0_A      0x0000000000000400
+
+#define IIO_SCRATCH_BIT1_0      0x0000000000000001
+#define IIO_SCRATCH_BIT1_1      0x0000000000000002
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the shub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+#define IIO_ICRB_E(_x)  (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)
+
+#define TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+/*
+ * Number of credits that xtalk devices should use when communicating
+ * with a SHub (depth of SHub's queue).
+ */
+#define HUB_CREDIT 4
+
+/*
+ * Some IIO_PRB fields
+ */
+#define IIO_PRB_MULTI_ERR	(1LL << 63)
+#define IIO_PRB_SPUR_RD		(1LL << 51)
+#define IIO_PRB_SPUR_WR		(1LL << 50)
+#define IIO_PRB_RD_TO		(1LL << 49)
+#define IIO_PRB_ERROR		(1LL << 48)
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+ 
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in SHub)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock?  See the manual.
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/* 
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY		(0x1 << 20)
+#define IBLS_ERROR_SHFT		16
+#define IBLS_ERROR		(0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK	0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON		(0x1 << 8)
+#define IBCT_NOTIFY		(0x1 << 4)
+#define IBCT_ZFIL_MODE		(0x1 << 0)
+
+/*
+ * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
+ */
+#define IIEPH1_VALID		(1 << 44)
+#define IIEPH1_OVERRUN		(1 << 40)
+#define IIEPH1_ERR_TYPE_SHFT	32
+#define IIEPH1_ERR_TYPE_MASK	0xf
+#define IIEPH1_SOURCE_SHFT	20
+#define IIEPH1_SOURCE_MASK	11
+#define IIEPH1_SUPPL_SHFT	8
+#define IIEPH1_SUPPL_MASK	11
+#define IIEPH1_CMD_SHFT		0
+#define IIEPH1_CMD_MASK		7
+
+#define IIEPH2_TAIL		(1 << 40)
+#define IIEPH2_ADDRESS_SHFT	0
+#define IIEPH2_ADDRESS_MASK	38
+
+#define IIEPH1_ERR_SHORT_REQ	2
+#define IIEPH1_ERR_SHORT_REPLY	3
+#define IIEPH1_ERR_LONG_REQ	4
+#define IIEPH1_ERR_LONG_REPLY	5
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT	(1 << 31)  /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT	(1 << 30)  /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR	(1 << 29)  /* clear valid bit in ixss reg */
+#define IECLR_BTE1		(1 << 18)  /* clear bte error 1 */
+#define IECLR_BTE0		(1 << 17)  /* clear bte error 0 */
+#define IECLR_CRAZY		(1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F		(1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E		(1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D		(1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C		(1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B		(1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A		(1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9		(1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8		(1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0		(1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR 
+ */
+#define	IIO_ICCR_PENDING	(0x10000)
+#define	IIO_ICCR_CMD_MASK	(0xFF)
+#define	IIO_ICCR_CMD_SHFT	(7)
+#define	IIO_ICCR_CMD_NOP	(0x0)	/* No Op */
+#define	IIO_ICCR_CMD_WAKE	(0x100) /* Reactivate CRB entry and process */
+#define	IIO_ICCR_CMD_TIMEOUT	(0x200)	/* Make CRB timeout & mark invalid */
+#define	IIO_ICCR_CMD_EJECT	(0x400)	/* Contents of entry written to memory 
+					 * via a WB
+					 */
+#define	IIO_ICCR_CMD_FLUSH	(0x800)
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to shub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Easy access macros for CRBs, all 4 registers (A-D)
+ */
+#define a_error         ii_icrb0_a_fld_s.ia_error
+#define a_ecode         ii_icrb0_a_fld_s.ia_errcode
+#define a_lnetuce       ii_icrb0_a_fld_s.ia_ln_uce
+#define a_mark          ii_icrb0_a_fld_s.ia_mark
+#define a_xerr          ii_icrb0_a_fld_s.ia_xt_err
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_addr          ii_icrb0_a_fld_s.ia_addr
+#define a_valid         ii_icrb0_a_fld_s.ia_vld
+#define a_iow           ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue	ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_btenum        ii_icrb0_b_fld_s.ib_bte_num
+#define b_cohtrans      ii_icrb0_b_fld_s.ib_ct
+#define b_xtsize        ii_icrb0_b_fld_s.ib_size
+#define b_source        ii_icrb0_b_fld_s.ib_source
+#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator     ii_icrb0_b_fld_s.ib_init
+#define b_regvalue	ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_pricnt        ii_icrb0_c_fld_s.ic_pr_cnt
+#define c_pripsc        ii_icrb0_c_fld_s.ic_pr_psc
+#define c_bteop         ii_icrb0_c_fld_s.ic_bte_op
+#define c_bteaddr       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_benable       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop        ii_icrb0_c_fld_s.ic_bo
+#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
+#define c_regvalue	ii_icrb0_c_regval
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define icrbd_ctxtvld   ii_icrb0_d_fld_s.id_cvld
+#define icrbd_toutvld   ii_icrb0_d_fld_s.id_tvld
+#define icrbd_context   ii_icrb0_d_fld_s.id_context
+#define d_regvalue	ii_icrb0_d_regval
+
+#endif /* __ASSEMBLY__ */
+
+/* Number of widgets supported by shub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc120
+#define MAX_HUBS_PER_XBOW       2
+
+#ifndef __ASSEMBLY__
+/* A few more #defines for backwards compatibility */
+#define iprb_t          ii_iprb0_u_t
+#define iprb_regval     ii_iprb0_regval
+#define iprb_mult_err	ii_iprb0_fld_s.i_mult_err
+#define iprb_spur_rd	ii_iprb0_fld_s.i_spur_rd
+#define iprb_spur_wr	ii_iprb0_fld_s.i_spur_wr
+#define iprb_rd_to	ii_iprb0_fld_s.i_rd_to
+#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
+#define iprb_error      ii_iprb0_fld_s.i_error
+#define iprb_ff         ii_iprb0_fld_s.i_f
+#define iprb_mode       ii_iprb0_fld_s.i_m
+#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
+#define iprb_anakctr    ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
+#endif
+
+#define LNK_STAT_WORKING        0x2		/* LLP is working */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS	32
+
+#if __KERNEL__
+#ifndef __ASSEMBLY__
+#include <asm/sn/alenlist.h>
+#include <asm/sn/dmamap.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/xtalk/xtalk.h>
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_PI_ID_SHIFT   8
+#define IIO_IIDSR_PI_ID_MASK    0x00000010
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000007f
+
+/* Xtalk timeout threshhold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT	55	   /* read response timeout */
+#define IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT	32	   /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT	0	   /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+typedef union hubii_wcr_u {
+        uint64_t      wcr_reg_value;
+        struct {
+	  uint64_t	wcr_widget_id:   4,     /* LLP crossbar credit */
+			wcr_tag_mode:	 1,	/* Tag mode */
+			wcr_rsvd1:	 8,	/* Reserved */
+			wcr_xbar_crd:	 3,	/* LLP crossbar credit */
+			wcr_f_bad_pkt:	 1,	/* Force bad llp pkt enable */
+			wcr_dir_con:	 1,	/* widget direct connect */
+			wcr_e_thresh:	 5,	/* elasticity threshold */
+			wcr_rsvd:	41;	/* unused */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+
+typedef union io_perf_sel {
+        uint64_t perf_sel_reg;
+        struct {
+               uint64_t	perf_ippr0 :  4,
+				perf_ippr1 :  4,
+				perf_icct  :  8,
+				perf_rsvd  : 48;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the shub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        uint64_t      perf_cnt;
+        struct {
+               uint64_t	perf_cnt   : 20,
+				perf_rsvd2 : 12,
+				perf_rsvd1 : 32;
+        } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+typedef union iprte_a {
+	shubreg_t	entry;
+	struct {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_addr			  :	38;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t	i_source		  :	 8;
+		shubreg_t	i_rsvd			  :	 2;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} iprte_fields;
+} iprte_a_t;
+
+
+/* PIO MANAGEMENT */
+typedef struct hub_piomap_s *hub_piomap_t;
+
+extern hub_piomap_t
+hub_piomap_alloc(devfs_handle_t dev,      /* set up mapping for this device */
+                device_desc_t dev_desc, /* device descriptor */
+                iopaddr_t xtalk_addr,   /* map for this xtalk_addr range */
+                size_t byte_count,
+                size_t byte_count_max,  /* maximum size of a mapping */
+                unsigned flags);                /* defined in sys/pio.h */
+
+extern void hub_piomap_free(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piomap_addr(hub_piomap_t hub_piomap,        /* mapping resources */
+                iopaddr_t xtalk_addr,           /* map for this xtalk addr */
+                size_t byte_count);             /* map this many bytes */
+
+extern void
+hub_piomap_done(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piotrans_addr(      devfs_handle_t dev,       /* translate to this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        iopaddr_t xtalk_addr,   /* Crosstalk address */
+                        size_t byte_count,      /* map this many bytes */
+                        unsigned flags);        /* (currently unused) */
+
+/* DMA MANAGEMENT */
+typedef struct hub_dmamap_s *hub_dmamap_t;
+
+extern hub_dmamap_t
+hub_dmamap_alloc(       devfs_handle_t dev,       /* set up mappings for dev */
+                        device_desc_t dev_desc, /* device descriptor */
+                        size_t byte_count_max,  /* max size of a mapping */
+                        unsigned flags);        /* defined in dma.h */
+
+extern void
+hub_dmamap_free(hub_dmamap_t dmamap);
+
+extern iopaddr_t
+hub_dmamap_addr(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        paddr_t paddr,          /* map for this address */
+                        size_t byte_count);     /* map this many bytes */
+
+extern alenlist_t
+hub_dmamap_list(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        alenlist_t alenlist,    /* map this Addr/Length List */
+                        unsigned flags);
+
+extern void
+hub_dmamap_done(        hub_dmamap_t dmamap);   /* done w/ mapping resources */
+
+extern iopaddr_t
+hub_dmatrans_addr(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        paddr_t paddr,          /* system physical address */
+                        size_t byte_count,      /* length */
+                        unsigned flags);                /* defined in dma.h */
+
+extern alenlist_t
+hub_dmatrans_list(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        alenlist_t palenlist,   /* system addr/length list */
+                        unsigned flags);                /* defined in dma.h */
+
+extern void
+hub_dmamap_drain(       hub_dmamap_t map);
+
+extern void
+hub_dmaaddr_drain(      devfs_handle_t vhdl,
+                        paddr_t addr,
+                        size_t bytes);
+
+extern void
+hub_dmalist_drain(      devfs_handle_t vhdl,
+                        alenlist_t list);
+
+
+/* INTERRUPT MANAGEMENT */
+typedef struct hub_intr_s *hub_intr_t;
+
+extern hub_intr_t
+hub_intr_alloc( devfs_handle_t dev,               /* which device */
+                device_desc_t dev_desc,         /* device descriptor */
+                devfs_handle_t owner_dev);        /* owner of this interrupt */
+
+extern hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,          /* which device */
+                device_desc_t dev_desc,         /* device descriptor */
+                devfs_handle_t owner_dev);        /* owner of this interrupt */
+
+extern void
+hub_intr_free(hub_intr_t intr_hdl);
+
+extern int
+hub_intr_connect(       hub_intr_t intr_hdl,    /* xtalk intr resource hndl */
+                        xtalk_intr_setfunc_t setfunc,
+                                                /* func to set intr hw */
+                        void *setfunc_arg);     /* arg to setfunc */
+
+extern void
+hub_intr_disconnect(hub_intr_t intr_hdl);
+
+extern devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl);
+
+/* CONFIGURATION MANAGEMENT */
+
+extern void
+hub_provider_startup(devfs_handle_t hub);
+
+extern void
+hub_provider_shutdown(devfs_handle_t hub);
+
+#define HUB_PIO_CONVEYOR        0x1     /* PIO in conveyor belt mode */
+#define HUB_PIO_FIRE_N_FORGET   0x2     /* PIO in fire-and-forget mode */
+
+/* Flags that make sense to hub_widget_flags_set */
+#define HUB_WIDGET_FLAGS        (                               \
+				 HUB_PIO_CONVEYOR       |       \
+				 HUB_PIO_FIRE_N_FORGET          \
+				)
+
+
+typedef int     hub_widget_flags_t;
+
+/* Set the PIO mode for a widget.  These two functions perform the
+ * same operation, but hub_device_flags_set() takes a hardware graph
+ * vertex while hub_widget_flags_set() takes a nasid and widget
+ * number.  In most cases, hub_device_flags_set() should be used.
+ */
+extern int      hub_widget_flags_set(nasid_t            nasid,
+                                     xwidgetnum_t       widget_num,
+                                     hub_widget_flags_t flags);
+
+/* Depending on the flags set take the appropriate actions */
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+                                                    
+
+/* Error Handling. */
+extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *);
+extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t,
+                              int, paddr_t, caddr_t, ioerror_mode_t);
+extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t);
+extern int hub_error_devenable(devfs_handle_t, int, int);
+extern void hub_widgetdev_enable(devfs_handle_t, int);
+extern void hub_widgetdev_shutdown(devfs_handle_t, int);
+extern int  hub_dma_enabled(devfs_handle_t);
+
+/* hubdev */
+extern void hubdev_init(void);
+extern void hubdev_register(int (*attach_method)(devfs_handle_t));
+extern int hubdev_unregister(int (*attach_method)(devfs_handle_t));
+extern int hubdev_docallouts(devfs_handle_t hub);
+
+extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
+extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _KERNEL */
+#endif /* _ASM_IA64_SN_SN2_SHUBIO_H */
+
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/slotnum.h lia64-2.4/include/asm-ia64/sn/sn2/slotnum.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/slotnum.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/slotnum.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,41 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1992 - 1997,2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_SLOTNUM_H
+#define _ASM_IA64_SN_SN2_SLOTNUM_H
+
+#define SLOTNUM_MAXLENGTH	16
+
+/*
+ * This file defines IO widget to slot/device assignments.
+ */
+
+
+/* This determines module to pnode mapping. */
+
+#define NODESLOTS_PER_MODULE		1
+#define NODESLOTS_PER_MODULE_SHFT	1
+
+#define SLOTNUM_NODE_CLASS	0x00	/* Node   */
+#define SLOTNUM_ROUTER_CLASS	0x10	/* Router */
+#define SLOTNUM_XTALK_CLASS	0x20	/* Xtalk  */
+#define SLOTNUM_MIDPLANE_CLASS	0x30	/* Midplane */
+#define SLOTNUM_XBOW_CLASS	0x40	/* Xbow  */
+#define SLOTNUM_KNODE_CLASS	0x50	/* Kego node */
+#define SLOTNUM_PCI_CLASS	0x60	/* PCI widgets on XBridge */
+#define SLOTNUM_INVALID_CLASS	0xf0	/* Invalid */
+
+#define SLOTNUM_CLASS_MASK	0xf0
+#define SLOTNUM_SLOT_MASK	0x0f
+
+#define SLOTNUM_GETCLASS(_sn)	((_sn) & SLOTNUM_CLASS_MASK)
+#define SLOTNUM_GETSLOT(_sn)	((_sn) & SLOTNUM_SLOT_MASK)
+
+
+#endif /* _ASM_IA64_SN_SN2_SLOTNUM_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn2/sn_private.h lia64-2.4/include/asm-ia64/sn/sn2/sn_private.h
--- linux-2.4.16/include/asm-ia64/sn/sn2/sn_private.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sn2/sn_private.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,250 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN2_SN_PRIVATE_H
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk_private.h>
+
+extern nasid_t master_nasid;
+
+/* promif.c */
+extern void he_arcs_set_vectors(void);
+extern void mem_init(void);
+extern void cpu_unenable(cpuid_t);
+extern nasid_t get_lowest_nasid(void);
+extern __psunsigned_t get_master_bridge_base(void);
+extern void set_master_bridge_base(void);
+extern int check_nasid_equiv(nasid_t, nasid_t);
+extern nasid_t get_console_nasid(void);
+extern char get_console_pcislot(void);
+
+extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
+
+/* memsupport.c */
+extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
+extern int memory_present(paddr_t);
+extern int memory_read_accessible(paddr_t);
+extern int memory_write_accessible(paddr_t);
+extern void memory_set_access(paddr_t, int, int);
+extern void show_dir_state(paddr_t, void (*)(char *, ...));
+extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
+extern void set_dir_owner(paddr_t, int);
+extern void set_dir_state(paddr_t, int);
+extern void set_dir_state_POISONED(paddr_t);
+extern void set_dir_state_UNOWNED(paddr_t);
+extern int is_POISONED_dir_state(paddr_t);
+extern int is_UNOWNED_dir_state(paddr_t);
+extern void get_dir_ent(paddr_t paddr, int *state,
+			uint64_t *vec_ptr, hubreg_t *elo);
+
+/* intr.c */
+extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
+extern void intr_unreserve_level(cpuid_t cpu, int level);
+extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
+			intr_func_t intr_prefunc);
+extern int intr_disconnect_level(cpuid_t cpu, int bit);
+extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
+			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
+			      char *intr_name,int *resp_bit);
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+extern void setrtvector(intr_func_t);
+extern void install_cpuintr(cpuid_t cpu);
+extern void install_dbgintr(cpuid_t cpu);
+extern void install_tlbintr(cpuid_t cpu);
+extern void hub_migrintr_init(cnodeid_t /*cnode*/);
+extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
+extern int cause_intr_disconnect(int level);
+extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
+
+/* error_dump.c */
+extern char *hub_rrb_err_type[];
+extern char *hub_wrb_err_type[];
+
+void nmi_dump(void);
+void install_cpu_nmi_handler(int slice);
+
+/* klclock.c */
+extern void hub_rtc_init(cnodeid_t);
+
+/* bte.c */
+void bte_lateinit(void);
+void bte_wait_for_xfer_completion(void *);
+
+/* klgraph.c */
+void klhwg_add_all_nodes(devfs_handle_t);
+void klhwg_add_all_modules(devfs_handle_t);
+
+/* klidbg.c */
+void install_klidbg_functions(void);
+
+/* klnuma.c */
+extern void replicate_kernel_text(int numnodes);
+extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
+extern void setup_replication_mask(int maxnodes);
+
+/* init.c */
+extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
+extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
+extern void init_platform_pda(cpuid_t cpu);
+extern void per_cpu_init(void);
+extern int is_fine_dirmode(void);
+extern void update_node_information(cnodeid_t);
+ 
+/* shubio.c */
+extern void hubio_init(void);
+extern void hub_merge_clean(nasid_t nasid);
+extern void hub_set_piomode(nasid_t nasid, int conveyor);
+
+/* shuberror.c */
+extern void hub_error_init(cnodeid_t);
+extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
+extern void hubni_error_handler(char *, int);
+extern int check_ni_errors(void);
+
+/* Used for debugger to signal upper software a breakpoint has taken place */
+
+extern void		*debugger_update;
+extern __psunsigned_t	debugger_stopped;
+
+/* 
+ * piomap, created by shub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_piomap_s by generic xtalk routines.
+ */
+struct hub_piomap_s {
+	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
+	devfs_handle_t		hpio_hub;	/* which shub's mapping registers are set up */
+	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
+	char			hpio_bigwin_num;/* if big window map, which one */
+	int 			hpio_flags;	/* defined below */
+};
+/* hub_piomap flags */
+#define HUB_PIOMAP_IS_VALID		0x1
+#define HUB_PIOMAP_IS_BIGWINDOW		0x2
+#define HUB_PIOMAP_IS_FIXED		0x4
+
+#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
+#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
+#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
+
+/* 
+ * dmamap, created by shub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_dmamap_s by generic xtalk routines.
+ */
+struct hub_dmamap_s {
+	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
+	devfs_handle_t		hdma_hub;	/* which shub we go through */
+	int			hdma_flags;	/* defined below */
+};
+/* shub_dmamap flags */
+#define HUB_DMAMAP_IS_VALID		0x1
+#define HUB_DMAMAP_USED			0x2
+#define	HUB_DMAMAP_IS_FIXED		0x4
+
+/* 
+ * interrupt handle, created by shub_intr_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_intr_s by generic xtalk routines.
+ */
+struct hub_intr_s {
+	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
+	ilvl_t			i_swlevel;	/* software level for blocking intr */
+	cpuid_t			i_cpuid;	/* which cpu */
+	int			i_bit;		/* which bit */
+	int			i_flags;
+};
+/* flag values */
+#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
+#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
+
+typedef struct hubinfo_s {
+	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
+	cnodeid_t			h_cnodeid;	/* compact nodeid */
+	nasid_t				h_nasid;	/* nasid */
+
+	/* structures for PIO management */
+	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
+	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
+	sv_t				h_bwwait;	/* wait for big window to free */
+	spinlock_t			h_bwlock;	/* guard big window piomap's */
+	spinlock_t			h_crblock;      /* gaurd CRB error handling */
+	int				h_num_big_window_fixed;	/* count number of FIXED maps */
+	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
+	hub_intr_t			hub_ii_errintr;
+} *hubinfo_t;
+
+#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
+
+#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
+
+#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
+
+/*
+ * Hub info PIO map access functions.
+ */
+#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
+			(&hinfo->h_big_window_piomap[win])
+#define	hubinfo_swin_piomap_get(hinfo, win)	\
+			(&hinfo->h_small_window_piomap[win])
+	
+/* cpu-specific information stored under INFO_LBL_CPU_INFO */
+typedef struct cpuinfo_s {
+	cpuid_t		ci_cpuid;	/* CPU ID */
+} *cpuinfo_t;
+
+#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
+
+#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
+
+/* Special initialization function for xswitch vertices created during startup. */
+extern void xswitch_vertex_init(devfs_handle_t xswitch);
+
+extern xtalk_provider_t hub_provider;
+
+/* du.c */
+int ducons_write(char *buf, int len);
+
+/* memerror.c */
+
+extern void install_eccintr(cpuid_t cpu);
+extern void memerror_get_stats(cnodeid_t cnode,
+			       int *bank_stats, int *bank_stats_max);
+extern void probe_md_errors(nasid_t);
+/* sysctlr.c */
+extern void sysctlr_init(void);
+extern void sysctlr_power_off(int sdonly);
+extern void sysctlr_keepalive(void);
+
+#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
+
+/* Useful definitions to get the memory dimm given a physical
+ * address.
+ */
+#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
+extern void membank_pathname_get(paddr_t,char *);
+
+/* To redirect the output into the error buffer */
+#define errbuf_print(_s)	printf("#%s",_s)
+
+extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
+void bootstrap(void);
+
+/* sndrv.c */
+extern int sndrv_attach(devfs_handle_t vertex);
+
+#endif /* _ASM_IA64_SN_SN2_SN_PRIVATE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn_cpuid.h lia64-2.4/include/asm-ia64/sn/sn_cpuid.h
--- linux-2.4.16/include/asm-ia64/sn/sn_cpuid.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn_cpuid.h	Mon Nov 26 18:05:56 2001
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -13,8 +12,12 @@
 #define _ASM_IA64_SN_SN_CPUID_H
 
 #include <linux/config.h>
-#include <asm/processor.h>
-#include <asm/sn/mmzone_sn1.h>
+#include <linux/smp.h>
+#include <linux/sched.h>
+#include <linux/mmzone.h>
+#include <asm/sn/types.h>
+#include <asm/current.h>
+
 
 /*
  * Functions for converting between cpuids, nodeids and NASIDs.
@@ -46,10 +49,15 @@
  *				* not real efficient - dont use in perf critical code
  *
  *         LID - processor defined register (see PRM V2).
+ *
+ *           On SN1
  *		31:24 - id   Contains the NASID
  *		23:16 - eid  Contains 0-3 to identify the cpu on the node
  *				bit 17 - synergy number
  *				bit 16 - FSB slot number 
+ *           On SN2
+ *		31:28 - id   Contains 0-3 to identify the cpu on the node
+ *		27:16 - eid  Contains the NASID
  *
  *
  *
@@ -70,15 +78,15 @@
  *                |                       |
  *             -------                 -------
  *             |     |                 |     |
- *             |  0  |                 |  1  |         SYNERGY
+ *             |  0  |                 |  1  |         SYNERGY (SN1 only)
  *             |     |                 |     |
  *             -------                 -------
  *                |                       |
  *                |                       |
  *             -------------------------------
  *             |                             |
- *             |         BEDROCK             |        NASID   (0..127)
- *             |                             |        CNODEID (0..numnodes-1)
+ *             |         BEDROCK / SHUB      |        NASID   (0..MAX_NASIDS)
+ *             |                             |        CNODEID (0..num_compact_nodes-1)
  *             |                             |
  *             |                             |
  *             -------------------------------
@@ -91,10 +99,25 @@
 #define cpu_physical_id(cpuid)			((ia64_get_lid() >> 16) & 0xffff)
 #endif
 
+#ifdef CONFIG_IA64_SGI_SN1
+/*
+ * macros for some of these exist in sn/addrs.h & sn/arch.h, etc. However, 
+ * trying #include these files here causes circular dependencies.
+ */
 #define cpu_physical_id_to_nasid(cpi)		((cpi) >> 8)
 #define cpu_physical_id_to_synergy(cpi)		(((cpi) >> 1) & 1)
 #define cpu_physical_id_to_fsb_slot(cpi)	((cpi) & 1)
 #define cpu_physical_id_to_slice(cpi)		((cpi) & 3)
+#define get_nasid()				((ia64_get_lid() >> 24))
+#define get_slice()				((ia64_get_lid() >> 16) & 3)
+#define get_node_number(addr)			(((unsigned long)(addr)>>33) & 0x7f)
+#else
+#define cpu_physical_id_to_nasid(cpi)		((cpi) &0xfff)
+#define cpu_physical_id_to_slice(cpi)		((cpi>>12) & 3)
+#define get_nasid()				((ia64_get_lid() >> 16) & 0xfff)
+#define get_slice()				((ia64_get_lid() >> 28) & 0xf)
+#define get_node_number(addr)			(((unsigned long)(addr)>>38) & 0x7ff)
+#endif
 
 /*
  * NOTE: id & eid refer to Intels definitions of the LID register
@@ -118,15 +141,12 @@
 
 
 
+#ifdef CONFIG_IA64_SGI_SN1
 /*
  * cpuid_to_fsb_slot  - convert a cpuid to the fsb slot number that it is in.
  *   (there are 2 cpus per FSB. This function returns 0 or 1)
  */
-static __inline__ int
-cpuid_to_fsb_slot(int cpuid)
-{
-	return cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid));
-}
+#define cpuid_to_fsb_slot(cpuid)	(cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid)))
 
 
 /*
@@ -134,108 +154,75 @@
  *   (there are 2 synergies per node. Function returns 0 or 1 to
  *    specify which synergy the cpu is on)
  */
-static __inline__ int
-cpuid_to_synergy(int cpuid)
-{
-	return cpu_physical_id_to_synergy(cpu_physical_id(cpuid));
-}
+#define cpuid_to_synergy(cpuid)		(cpu_physical_id_to_synergy(cpu_physical_id(cpuid)))
 
+#endif
 
 /*
  * cpuid_to_slice  - convert a cpuid to the slice that it resides on
  *  There are 4 cpus per node. This function returns 0 .. 3)
  */
-static __inline__ int
-cpuid_to_slice(int cpuid)
-{
-	return cpu_physical_id_to_slice(cpu_physical_id(cpuid));
-}
+#define cpuid_to_slice(cpuid)		(cpu_physical_id_to_slice(cpu_physical_id(cpuid)))
 
 
 /*
  * cpuid_to_nasid  - convert a cpuid to the NASID that it resides on
  */
-static __inline__ int
-cpuid_to_nasid(int cpuid)
-{
-	return cpu_physical_id_to_nasid(cpu_physical_id(cpuid));
-}
+#define cpuid_to_nasid(cpuid)		(cpu_physical_id_to_nasid(cpu_physical_id(cpuid)))
 
 
 /*
  * cpuid_to_cnodeid  - convert a cpuid to the cnode that it resides on
  */
-static __inline__ int
-cpuid_to_cnodeid(int cpuid)
-{
-	return nasid_map[cpuid_to_nasid(cpuid)];
-}
+#define cpuid_to_cnodeid(cpuid)		(NODEDIR->physical_node_map[cpuid_to_nasid(cpuid)])
+
 
 /*
  * cnodeid_to_nasid - convert a cnodeid to a NASID
+ *	Macro relies on pg_data for a node being on the node itself.
+ *	Just extract the NASID from the pointer.
+ *
  */
-static __inline__ int
-cnodeid_to_nasid(int cnodeid)
-{
-	if (nasid_map[cnodeid_map[cnodeid]] != cnodeid)
-		panic("cnodeid_to_nasid, cnode = %d", cnodeid);
-	return cnodeid_map[cnodeid];
-}
+#define cnodeid_to_nasid(cnodeid)	(get_node_number(NODEDIR->pg_data_ptrs[cnodeid]))
+ 
 
 /*
  * nasid_to_cnodeid - convert a NASID to a cnodeid
  */
-static __inline__ int
-nasid_to_cnodeid(int nasid)
-{
-	if (cnodeid_map[nasid_map[nasid]] != nasid)
-		panic("nasid_to_cnodeid");
-	return nasid_map[nasid];
-}
+#define nasid_to_cnodeid(nasid)		(NODEDIR->physical_node_map[nasid])
 
 
 /*
  * cnode_slice_to_cpuid - convert a codeid & slice to a cpuid
  */
-static __inline__ int
-cnode_slice_to_cpuid(int cnodeid, int slice) {
-	return(id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),slice));
-}
+#define cnode_slice_to_cpuid(cnodeid,slice) (id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),(slice)))
+ 
 
 /*
  * cpuid_to_subnode - convert a cpuid to the subnode it resides on.
  *   slice 0 & 1 are on subnode 0
  *   slice 2 & 3 are on subnode 1.
  */
-static __inline__ int
-cpuid_to_subnode(int cpuid) {
-	int ret = cpuid_to_slice(cpuid);
-	if (ret < 2) return 0;
-	else return 1;
-}
+#define cpuid_to_subnode(cpuid)		((cpuid_to_slice(cpuid)<2) ? 0 : 1)
+ 
 
 /*
  * cpuid_to_localslice - convert a cpuid to a local slice
  *    slice 0 & 2 are local slice 0
  *    slice 1 & 3 are local slice 1
  */
-static __inline__ int
-cpuid_to_localslice(int cpuid) {
-	return(cpuid_to_slice(cpuid) & 1);
-}
-
-static __inline__ int
-cnodeid_to_cpuid(int cnode) {
-	int cpu;
-
-	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
-		if (cpuid_to_cnodeid(cpu) == cnode) {
-			break;
-		}
-	}
-	if (cpu == smp_num_cpus) cpu = -1;
-	return cpu;
-}
+#define cpuid_to_localslice(cpuid)	(cpuid_to_slice(cpuid) & 1)
+ 
+
+#define smp_physical_node_id()			(cpuid_to_nasid(smp_processor_id()))
+
+
+/*
+ * cnodeid_to_cpuid - convert a cnode  to a cpuid of a cpu on the node.
+ *	returns -1 if no cpus exist on the node
+ */
+extern int cnodeid_to_cpuid(int cnode);
 
 
 #endif /* _ASM_IA64_SN_SN_CPUID_H */
+
diff -urN linux-2.4.16/include/asm-ia64/sn/sn_fru.h lia64-2.4/include/asm-ia64/sn/sn_fru.h
--- linux-2.4.16/include/asm-ia64/sn/sn_fru.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn_fru.h	Mon Nov 19 23:23:00 2001
@@ -4,11 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 1999-2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Patrick Gefre
+ * Copyright (C) 1992 - 1997, 1999-2001 Silicon Graphics, Inc. 
+ * All rights reserved.
  */
-#ifndef _ASM_SN_SN_FRU_H
-#define _ASM_SN_SN_FRU_H
+#ifndef _ASM_IA64_SN_SN_FRU_H
+#define _ASM_IA64_SN_SN_FRU_H
 
 #define MAX_DIMMS			8	 /* max # of dimm banks */
 #define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
@@ -42,5 +42,5 @@
 } kf_pci_bus_t;
 
 
-#endif	/* _ASM_SN_SN_FRU_H */
+#endif /* _ASM_IA64_SN_SN_FRU_H */
 
diff -urN linux-2.4.16/include/asm-ia64/sn/sn_private.h lia64-2.4/include/asm-ia64/sn/sn_private.h
--- linux-2.4.16/include/asm-ia64/sn/sn_private.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn_private.h	Mon Nov 19 23:23:00 2001
@@ -4,299 +4,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PRIVATE_H
-#define _ASM_SN_PRIVATE_H
+#ifndef _ASM_IA64_SN_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN_PRIVATE_H
 
+#include <linux/config.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/xtalk/xwidget.h>
 #include <asm/sn/xtalk/xtalk_private.h>
 
-extern nasid_t master_nasid;
-
-extern hubreg_t get_region(cnodeid_t);
-extern hubreg_t	nasid_to_region(nasid_t);
-/* promif.c */
-#ifdef	LATER
-extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes);
-#endif
-extern void he_arcs_set_vectors(void);
-extern void mem_init(void);
-#ifdef	LATER
-extern int cpu_enabled(cpuid_t);
-#endif
-extern void cpu_unenable(cpuid_t);
-extern nasid_t get_lowest_nasid(void);
-extern __psunsigned_t get_master_bridge_base(void);
-extern void set_master_bridge_base(void);
-extern int check_nasid_equiv(nasid_t, nasid_t);
-extern nasid_t get_console_nasid(void);
-extern char get_console_pcislot(void);
-#ifdef	LATER
-extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
-#endif
-
-extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
-
-/* memsupport.c */
-extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
-extern int memory_present(paddr_t);
-extern int memory_read_accessible(paddr_t);
-extern int memory_write_accessible(paddr_t);
-extern void memory_set_access(paddr_t, int, int);
-extern void show_dir_state(paddr_t, void (*)(char *, ...));
-extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
-extern void set_dir_owner(paddr_t, int);
-extern void set_dir_state(paddr_t, int);
-extern void set_dir_state_POISONED(paddr_t);
-extern void set_dir_state_UNOWNED(paddr_t);
-extern int is_POISONED_dir_state(paddr_t);
-extern int is_UNOWNED_dir_state(paddr_t);
-extern void get_dir_ent(paddr_t paddr, int *state,
-			uint64_t *vec_ptr, hubreg_t *elo);
-
-/* intr.c */
-#if defined(NEW_INTERRUPTS)
-extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
-extern void intr_unreserve_level(cpuid_t cpu, int level);
-extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
-			intr_func_t intr_func, void *intr_arg,
-			intr_func_t intr_prefunc);
-extern int intr_disconnect_level(cpuid_t cpu, int bit);
-extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
-			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
-			      char *intr_name,int *resp_bit);
-#endif	/* NEW_INTERRUPTS */
-extern void intr_block_bit(cpuid_t cpu, int bit);
-extern void intr_unblock_bit(cpuid_t cpu, int bit);
-extern void setrtvector(intr_func_t);
-extern void install_cpuintr(cpuid_t cpu);
-extern void install_dbgintr(cpuid_t cpu);
-extern void install_tlbintr(cpuid_t cpu);
-extern void hub_migrintr_init(cnodeid_t /*cnode*/);
-extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
-extern int cause_intr_disconnect(int level);
-extern void intr_reserve_hardwired(cnodeid_t);
-extern void intr_clear_all(nasid_t);
-extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
-extern int protected_broadcast(hubreg_t intrbit);
-
-/* error_dump.c */
-extern char *hub_rrb_err_type[];
-extern char *hub_wrb_err_type[];
-
-void nmi_dump(void);
-void install_cpu_nmi_handler(int slice);
-
-/* klclock.c */
-extern void hub_rtc_init(cnodeid_t);
-
-/* bte.c */
-void bte_lateinit(void);
-void bte_wait_for_xfer_completion(void *);
-
-/* klgraph.c */
-void klhwg_add_all_nodes(devfs_handle_t);
-void klhwg_add_all_modules(devfs_handle_t);
-
-/* klidbg.c */
-void install_klidbg_functions(void);
-
-/* klnuma.c */
-extern void replicate_kernel_text(int numnodes);
-extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
-extern void setup_replication_mask(int maxnodes);
-
-/* init.c */
-extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
-#ifdef	LATER
-extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
-extern void init_platform_pda(pda_t *ppda, cpuid_t cpu);
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/sn_private.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/sn_private.h>
 #endif
-extern void per_cpu_init(void);
-extern void per_hub_init(cnodeid_t);
-#ifdef	LATER
-extern cpumask_t boot_cpumask;
-#endif
-extern int is_fine_dirmode(void);
-extern void update_node_information(cnodeid_t);
- 
-#ifdef	LATER
-/* clksupport.c */
-extern void early_counter_intr(eframe_t *);
-#endif
-
-/* hubio.c */
-extern void hubio_init(void);
-extern void hub_merge_clean(nasid_t nasid);
-extern void hub_set_piomode(nasid_t nasid, int conveyor);
-
-/* huberror.c */
-extern void hub_error_init(cnodeid_t);
-extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
-extern void hubni_error_handler(char *, int);
-extern int check_ni_errors(void);
-
-/* Used for debugger to signal upper software a breakpoint has taken place */
-
-extern void		*debugger_update;
-extern __psunsigned_t	debugger_stopped;
-
-/* 
- * IP27 piomap, created by hub_pio_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_piomap_s by generic xtalk routines.
- */
-struct hub_piomap_s {
-	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
-	devfs_handle_t		hpio_hub;	/* which hub's mapping registers are set up */
-	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
-	char			hpio_bigwin_num;/* if big window map, which one */
-	int 			hpio_flags;	/* defined below */
-};
-/* hub_piomap flags */
-#define HUB_PIOMAP_IS_VALID		0x1
-#define HUB_PIOMAP_IS_BIGWINDOW		0x2
-#define HUB_PIOMAP_IS_FIXED		0x4
-
-#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
-#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
-#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
-
-#if TBD
- /* Ensure that hpio_xtalk_info is first */
- #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0)
-#endif
-
-
-/* 
- * IP27 dmamap, created by hub_pio_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_dmamap_s by generic xtalk routines.
- */
-struct hub_dmamap_s {
-	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
-	devfs_handle_t		hdma_hub;	/* which hub we go through */
-	int			hdma_flags;	/* defined below */
-};
-/* hub_dmamap flags */
-#define HUB_DMAMAP_IS_VALID		0x1
-#define HUB_DMAMAP_USED			0x2
-#define	HUB_DMAMAP_IS_FIXED		0x4
-
-#if TBD
- /* Ensure that hdma_xtalk_info is first */
- #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0)
-#endif
-
-/* 
- * IP27 interrupt handle, created by hub_intr_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_intr_s by generic xtalk routines.
- */
-struct hub_intr_s {
-	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
-	ilvl_t			i_swlevel;	/* software level for blocking intr */
-	cpuid_t			i_cpuid;	/* which cpu */
-	int			i_bit;		/* which bit */
-	int			i_flags;
-};
-/* flag values */
-#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
-#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
-
-#if TBD
- /* Ensure that i_xtalk_info is first */
- #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0)
-#endif
-
-
-/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */
-/* TBD: IP27-dependent stuff currently in nodepda.h should be here */
-typedef struct hubinfo_s {
-	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
-	cnodeid_t			h_cnodeid;	/* compact nodeid */
-	nasid_t				h_nasid;	/* nasid */
-
-	/* structures for PIO management */
-	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
-	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
-	sv_t				h_bwwait;	/* wait for big window to free */
-	spinlock_t			h_bwlock;	/* guard big window piomap's */
-	spinlock_t			h_crblock;      /* gaurd CRB error handling */
-	int				h_num_big_window_fixed;	/* count number of FIXED maps */
-	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
-	hub_intr_t			hub_ii_errintr;
-} *hubinfo_t;
-
-#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
-	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
-
-#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
-	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
-
-#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
-
-/*
- * Hub info PIO map access functions.
- */
-#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
-			(&hinfo->h_big_window_piomap[win])
-#define	hubinfo_swin_piomap_get(hinfo, win)	\
-			(&hinfo->h_small_window_piomap[win])
-	
-/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */
-/* TBD: IP27-dependent stuff currently in pda.h should be here */
-typedef struct cpuinfo_s {
-#ifdef	LATER
-	pda_t		*ci_cpupda;	/* pointer to CPU's private data area */
-#endif
-	cpuid_t		ci_cpuid;	/* CPU ID */
-} *cpuinfo_t;
-
-#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
-	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
-
-#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
-	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
-
-/* Special initialization function for xswitch vertices created during startup. */
-extern void xswitch_vertex_init(devfs_handle_t xswitch);
-
-extern xtalk_provider_t hub_provider;
-
-/* du.c */
-int ducons_write(char *buf, int len);
-
-/* memerror.c */
-
-extern void install_eccintr(cpuid_t cpu);
-extern void memerror_get_stats(cnodeid_t cnode,
-			       int *bank_stats, int *bank_stats_max);
-extern void probe_md_errors(nasid_t);
-/* sysctlr.c */
-extern void sysctlr_init(void);
-extern void sysctlr_power_off(int sdonly);
-extern void sysctlr_keepalive(void);
-
-#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
-
-/* Useful definitions to get the memory dimm given a physical
- * address.
- */
-#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
-#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
-extern void membank_pathname_get(paddr_t,char *);
-
-/* To redirect the output into the error buffer */
-#define errbuf_print(_s)	printf("#%s",_s)
-
-extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
-void bootstrap(void);
-
-/* sndrv.c */
-extern int sndrv_attach(devfs_handle_t vertex);
 
-#endif /* _ASM_SN_PRIVATE_H */
+#endif /* _ASM_IA64_SN_SN_PRIVATE_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sn_sal.h lia64-2.4/include/asm-ia64/sn/sn_sal.h
--- linux-2.4.16/include/asm-ia64/sn/sn_sal.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sn_sal.h	Mon Nov 19 23:23:00 2001
@@ -1,25 +1,74 @@
-#ifndef _ASM_IA64_SN_SAL_H
-#define _ASM_IA64_SN_SAL_H
+#ifndef _ASM_IA64_SN_SN_SAL_H
+#define _ASM_IA64_SN_SN_SAL_H
 
 /*
  * System Abstraction Layer definitions for IA64
  *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * Copyright (C) 2000, Silicon Graphics.
- * Copyright (C) 2000. Jack Steiner (steiner@sgi.com)
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
  */
 
 
 #include <asm/sal.h>
+#include <asm/sn/sn_cpuid.h>
 
 
 // SGI Specific Calls
 #define  SN_SAL_POD_MODE                           0x02000001
 #define  SN_SAL_SYSTEM_RESET                       0x02000002
 #define  SN_SAL_PROBE                              0x02000003
+#define  SN_SAL_GET_CONSOLE_NASID                  0x02000004
+#define	 SN_SAL_GET_KLCONFIG_ADDR		   0x02000005
+#define  SN_SAL_LOG_CE				   0x02000006
+#define  SN_SAL_REGISTER_CE			   0x02000007
 
 
 u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr);
 
-
-#endif /* _ASM_IA64_SN_SN1_SAL_H */
+/*
+ * Returns the master console nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_console_nasid(void)
+{
+	struct ia64_sal_retval ret_stuff;
+
+	ret_stuff.status = (uint64_t)0;
+	ret_stuff.v0 = (uint64_t)0;
+	ret_stuff.v1 = (uint64_t)0;
+	ret_stuff.v2 = (uint64_t)0;
+	SAL_CALL(ret_stuff, SN_SAL_GET_CONSOLE_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+	if (ret_stuff.status < 0)
+		return ret_stuff.status;
+
+	/* Master console nasid is in 'v0' */
+	return ret_stuff.v0;
+}
+
+static inline u64
+ia64_sn_get_klconfig_addr(nasid_t nasid)
+{
+	struct ia64_sal_retval ret_stuff;
+
+	ret_stuff.status = (uint64_t)0;
+	ret_stuff.v0 = (uint64_t)0;
+	ret_stuff.v1 = (uint64_t)0;
+	ret_stuff.v2 = (uint64_t)0;
+	SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
+
+	/*
+	 * We should panic if a valid cnode nasid does not produce
+	 * a klconfig address.
+	 */
+	if (ret_stuff.status != 0) {
+		panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status);
+	}
+
+	return ret_stuff.v0;
+}
+#endif /* _ASM_IA64_SN_SN_SAL_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/snconfig.h lia64-2.4/include/asm-ia64/sn/snconfig.h
--- linux-2.4.16/include/asm-ia64/sn/snconfig.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/snconfig.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_IA64_SN_SNCONFIG_H
+#define _ASM_IA64_SN_SNCONFIG_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/ip27config.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#endif
+
+#endif /* _ASM_IA64_SN_SNCONFIG_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sndrv.h lia64-2.4/include/asm-ia64/sn/sndrv.h
--- linux-2.4.16/include/asm-ia64/sn/sndrv.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/sndrv.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,39 @@
+#ifndef _ASM_IA64_SN_SNDRV_H
+#define _ASM_IA64_SN_SNDRV_H
+
+/* ioctl commands */
+#define SNDRV_GET_ROUTERINFO		1
+#define SNDRV_GET_INFOSIZE		2
+#define SNDRV_GET_HUBINFO		3
+#define SNDRV_GET_FLASHLOGSIZE		4
+#define SNDRV_SET_FLASHSYNC		5
+#define SNDRV_GET_FLASHLOGDATA		6
+#define SNDRV_GET_FLASHLOGALL		7
+
+#define SNDRV_SET_HISTOGRAM_TYPE	14
+
+#define SNDRV_ELSC_COMMAND		19
+#define	SNDRV_CLEAR_LOG			20
+#define	SNDRV_INIT_LOG			21
+#define	SNDRV_GET_PIMM_PSC		22
+#define SNDRV_SET_PARTITION		23
+#define SNDRV_GET_PARTITION		24
+
+/* see synergy_perf_ioctl() */
+#define SNDRV_GET_SYNERGY_VERSION	30
+#define SNDRV_GET_SYNERGY_STATUS	31
+#define SNDRV_GET_SYNERGYINFO		32
+#define SNDRV_SYNERGY_APPEND		33
+#define SNDRV_SYNERGY_ENABLE		34
+#define SNDRV_SYNERGY_FREQ		35
+
+/* Devices */
+#define SNDRV_UKNOWN_DEVICE		-1
+#define SNDRV_ROUTER_DEVICE		1
+#define SNDRV_HUB_DEVICE		2
+#define SNDRV_ELSC_NVRAM_DEVICE		3
+#define SNDRV_ELSC_CONTROLLER_DEVICE	4
+#define SNDRV_SYSCTL_SUBCH		5
+#define SNDRV_SYNERGY_DEVICE		6
+
+#endif /* _ASM_IA64_SN_SNDRV_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/sv.h lia64-2.4/include/asm-ia64/sn/sv.h
--- linux-2.4.16/include/asm-ia64/sn/sv.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/sv.h	Mon Nov 26 18:05:56 2001
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.  All rights reserved
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved
  *
  * This implemenation of synchronization variables is heavily based on
  * one done by Steve Lord <lord@sgi.com>
@@ -11,8 +11,8 @@
  * Paul Cassella <pwc@sgi.com>
  */
 
-#ifndef SV_H
-#define SV_H
+#ifndef _ASM_IA64_SN_SV_H
+#define _ASM_IA64_SN_SV_H
 
 #include <linux/spinlock.h>
 #include <asm/semaphore.h>
@@ -150,4 +150,4 @@
 #undef _SV_ASSERT
 #endif
 
-#endif
+#endif /* _ASM_IA64_SN_SV_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/synergy.h lia64-2.4/include/asm-ia64/sn/synergy.h
--- linux-2.4.16/include/asm-ia64/sn/synergy.h	Thu Apr 12 12:16:36 2001
+++ lia64-2.4/include/asm-ia64/sn/synergy.h	Wed Dec 31 16:00:00 1969
@@ -1,168 +0,0 @@
-#ifndef ASM_IA64_SN_SYNERGY_H
-#define ASM_IA64_SN_SYNERGY_H
-
-#include <linux/config.h>
-
-#include "asm/io.h"
-#include "asm/sn/nodepda.h"
-#include "asm/sn/intr_public.h"
-
-
-/*
- * Definitions for the synergy asic driver
- * 
- * These are for SGI platforms only.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc
- * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
- */
-
-
-#define SSPEC_BASE	(0xe0000000000)
-#define LB_REG_BASE	(SSPEC_BASE + 0x0)
-
-#define VEC_MASK3A_ADDR	(0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK3B_ADDR	(0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK3A	(0x2a0)
-#define VEC_MASK3B	(0x2a8)
-
-#define VEC_MASK2A_ADDR	(0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK2B_ADDR	(0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK2A	(0x2b0)
-#define VEC_MASK2B	(0x2b8)
-
-#define VEC_MASK1A_ADDR	(0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK1B_ADDR	(0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK1A	(0x2c0)
-#define VEC_MASK1B	(0x2c8)
-
-#define VEC_MASK0A_ADDR	(0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK0B_ADDR	(0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK0A	(0x2d0)
-#define VEC_MASK0B	(0x2d8)
-
-#define WRITE_LOCAL_SYNERGY_REG(addr, value)	__synergy_out(addr, value)
-
-#define HUBREG_CAST             (volatile hubreg_t *)
-#define HUB_L(_a)               *(_a)
-#define HUB_S(_a, _d)           *(_a) = (_d)
-
-#define HSPEC_SYNERGY0_0        0x04000000    /* Synergy0 Registers     */
-#define HSPEC_SYNERGY1_0        0x05000000    /* Synergy1 Registers     */
-#define HS_SYNERGY_STRIDE       (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
-#define REMOTE_HSPEC(_n, _x)    (HUBREG_CAST (RREG_BASE(_n) + (_x)))
-
-#define RREG_BASE(_n)           (NODE_LREG_BASE(_n))
-#define NODE_LREG_BASE(_n)      (NODE_HSPEC_BASE(_n) + 0x30000000)
-#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
-#ifndef HSPEC_BASE
-#define HSPEC_BASE              (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN)
-#endif
-#define SYN_UNCACHED_SPACE      0xc000000000000000
-#define HSPEC_BASE_SYN          0x00000b0000000000
-#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
-#define NODE_SIZE_BITS		33
-
-
-#define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg))
-
-#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg)  __remote_synergy_in(nasid, fsb, reg)
-#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
-
-extern inline uint64_t
-__remote_synergy_in(int nasid, int fsb, uint64_t reg) {
-	volatile uint64_t *addr;
-
-	addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg));
-	return (*addr);
-}
-
-extern inline void
-__remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) {
-	volatile uint64_t *addr;
-
-        addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2)));
-        *(addr+0) = value >> 48;
-        *(addr+1) = value >> 32;
-        *(addr+2) = value >> 16;
-        *(addr+3) = value;
-        __ia64_mf_a();
-}
-
-/* XX this doesn't make a lot of sense. Which fsb?  */
-extern inline void
-__synergy_out(unsigned long addr, unsigned long value)
-{
-	volatile unsigned long *adr = (unsigned long *)
-			(addr | __IA64_UNCACHED_OFFSET);
-
-	*adr = value;
-	__ia64_mf_a();
-}
-
-#define READ_LOCAL_SYNERGY_REG(addr)	__synergy_in(addr)
-
-/* XX this doesn't make a lot of sense. Which fsb? */
-extern inline unsigned long
-__synergy_in(unsigned long addr)
-{
-	unsigned long ret, *adr = (unsigned long *)
-			(addr | __IA64_UNCACHED_OFFSET);
-
-	ret = *adr;
-	__ia64_mf_a();
-	return ret;
-}
-
-struct sn1_intr_action {
-	void (*handler)(int, void *, struct pt_regs *);
-	void *intr_arg;
-	unsigned long flags;
-	struct sn1_intr_action * next;
-};
-
-typedef struct synergy_da_s {
-	hub_intmasks_t	s_intmasks;
-}synergy_da_t;
-
-struct sn1_cnode_action_list {
-	spinlock_t action_list_lock;
-	struct sn1_intr_action *action_list;
-};
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-
-/* multiplex the counters every 10 timer interrupts */ 
-#define SYNERGY_PERF_FREQ_DEFAULT 10
-
-/* synergy perf control registers */
-#define PERF_CNTL0_A            0xab0UL /* control A on FSB0 */
-#define PERF_CNTL0_B            0xab8UL /* control B on FSB0 */
-#define PERF_CNTL1_A            0xac0UL /* control A on FSB1 */
-#define PERF_CNTL1_B            0xac8UL /* control B on FSB1 */
-
-/* synergy perf counters */
-#define PERF_CNTR0_A            0xad0UL /* counter A on FSB0 */
-#define PERF_CNTR0_B            0xad8UL /* counter B on FSB0 */
-#define PERF_CNTR1_A            0xaf0UL /* counter A on FSB1 */
-#define PERF_CNTR1_B            0xaf8UL /* counter B on FSB1 */
-
-/* Synergy perf data. Each nodepda keeps a list of these */
-struct synergy_perf_s {
-        uint64_t        intervals;      /* count of active intervals for this event */
-        uint64_t        modesel;        /* mode and sel bits, both A and B registers */
-        struct synergy_perf_s *next;	/* next in circular linked list */
-        uint64_t        counts[2];      /* [0] is synergy-A counter, [1] synergy-B counter */
-};
-
-typedef struct synergy_perf_s synergy_perf_t;
-
-extern void synergy_perf_init(void);
-extern void synergy_perf_update(int);
-
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
-
-/* Temporary defintions for testing: */
-
-#endif ASM_IA64_SN_SYNERGY_H
diff -urN linux-2.4.16/include/asm-ia64/sn/systeminfo.h lia64-2.4/include/asm-ia64/sn/systeminfo.h
--- linux-2.4.16/include/asm-ia64/sn/systeminfo.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/systeminfo.h	Mon Nov 19 23:23:00 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SYSTEMINFO_H
-#define _ASM_SN_SYSTEMINFO_H
+#ifndef _ASM_IA64_SN_SYSTEMINFO_H
+#define _ASM_IA64_SN_SYSTEMINFO_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -69,4 +68,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_SYSTEMINFO_H */
+#endif /* _ASM_IA64_SN_SYSTEMINFO_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/types.h lia64-2.4/include/asm-ia64/sn/types.h
--- linux-2.4.16/include/asm-ia64/sn/types.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/types.h	Mon Nov 19 23:23:00 2001
@@ -3,17 +3,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999,2001 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_TYPES_H
-#define _ASM_SN_TYPES_H
+#ifndef _ASM_IA64_SN_TYPES_H
+#define _ASM_IA64_SN_TYPES_H
 
 #include <linux/types.h>
 
 typedef unsigned long 	cpuid_t;
 typedef unsigned long 	cpumask_t;
-/* typedef unsigned long	cnodemask_t; */
 typedef signed short	nasid_t;	/* node id in numa-as-id space */
 typedef signed short	cnodeid_t;	/* node id in compact-id space */
 typedef signed char	partid_t;	/* partition ID type */
@@ -22,11 +21,10 @@
 typedef unsigned char	clusterid_t;	/* Clusterid of the cell */
 
 #define __psunsigned_t uint64_t
-#define lock_t uint64_t
 
 typedef unsigned long iopaddr_t;
 typedef unsigned char uchar_t;
 typedef unsigned long paddr_t;
 typedef unsigned long pfn_t;
 
-#endif /* _ASM_SN_TYPES_H */
+#endif /* _ASM_IA64_SN_TYPES_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/uart16550.h lia64-2.4/include/asm-ia64/sn/uart16550.h
--- linux-2.4.16/include/asm-ia64/sn/uart16550.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/asm-ia64/sn/uart16550.h	Mon Nov 19 23:23:00 2001
@@ -0,0 +1,227 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_UART16550_H
+#define _ASM_IA64_SN_UART16550_H
+
+
+/*
+ * Definitions for 16550  chip
+ */
+
+	/* defined as offsets from the data register */
+#define REG_DAT     0   /* receive/transmit data */
+#define REG_ICR     1   /* interrupt control register */
+#define REG_ISR     2   /* interrupt status register */
+#define REG_FCR     2   /* fifo control register */
+#define REG_LCR     3   /* line control register */
+#define REG_MCR     4   /* modem control register */
+#define REG_LSR     5   /* line status register */
+#define REG_MSR     6   /* modem status register */
+#define REG_SCR     7   /* Scratch register      */
+#define REG_DLL     0   /* divisor latch (lsb) */
+#define REG_DLH     1   /* divisor latch (msb) */
+#define REG_EFR		2	/* 16650 enhanced feature register */
+
+/*
+ * 16450/16550 Registers Structure.
+ */
+
+/* Line Control Register */
+#define		LCR_WLS0	0x01	/*word length select bit 0 */	
+#define		LCR_WLS1	0x02	/*word length select bit 2 */	
+#define		LCR_STB	0x04		/* number of stop bits */
+#define		LCR_PEN	0x08		/* parity enable */
+#define		LCR_EPS	0x10		/* even parity select */
+#define		LCR_SETBREAK 0x40	/* break key */
+#define		LCR_DLAB	0x80	/* divisor latch access bit */
+#define 	LCR_RXLEN   0x03    /* # of data bits per received/xmitted char */
+#define 	LCR_STOP1   0x00
+#define 	LCR_STOP2   0x04
+#define 	LCR_PAREN   0x08
+#define 	LCR_PAREVN  0x10
+#define 	LCR_PARMARK 0x20
+#define 	LCR_SNDBRK  0x40
+#define 	LCR_DLAB    0x80
+
+
+#define		LCR_BITS5	0x00	/* 5 bits per char */
+#define		LCR_BITS6	0x01	/* 6 bits per char */
+#define		LCR_BITS7	0x02	/* 7 bits per char */
+#define		LCR_BITS8	0x03	/* 8 bits per char */
+
+#define		LCR_MASK_BITS_CHAR 		0x03
+#define 	LCR_MASK_STOP_BITS		0x04
+#define		LCR_MASK_PARITY_BITS	0x18
+
+
+/* Line Status Register */
+#define		LSR_RCA	0x01		/* data ready */
+#define		LSR_OVRRUN	0x02	/* overrun error */
+#define		LSR_PARERR	0x04	/* parity error */
+#define		LSR_FRMERR	0x08	/* framing error */
+#define		LSR_BRKDET 	0x10	/* a break has arrived */
+#define		LSR_XHRE	0x20	/* tx hold reg is now empty */
+#define		LSR_XSRE	0x40	/* tx shift reg is now empty */
+#define		LSR_RFBE	0x80	/* rx FIFO Buffer error */
+
+/* Interrupt Status Regisger */
+#define		ISR_MSTATUS	0x00
+#define		ISR_TxRDY	0x02
+#define		ISR_RxRDY	0x04
+#define		ISR_ERROR_INTR	0x08
+#define		ISR_FFTMOUT 0x0c	/* FIFO Timeout */
+#define		ISR_RSTATUS 0x06	/* Receiver Line status */
+
+/* Interrupt Enable Register */
+#define		ICR_RIEN	0x01	/* Received Data Ready */
+#define		ICR_TIEN	0x02	/* Tx Hold Register Empty */
+#define		ICR_SIEN	0x04	/* Receiver Line Status */
+#define		ICR_MIEN	0x08	/* Modem Status */
+
+/* Modem Control Register */
+#define		MCR_DTR		0x01	/* Data Terminal Ready */
+#define		MCR_RTS		0x02	/* Request To Send */
+#define		MCR_OUT1	0x04	/* Aux output - not used */
+#define		MCR_OUT2	0x08	/* turns intr to 386 on/off */	
+#define		MCR_LOOP	0x10	/* loopback for diagnostics */
+#define		MCR_AFE 	0x20	/* Auto flow control enable */
+
+/* Modem Status Register */
+#define		MSR_DCTS	0x01	/* Delta Clear To Send */
+#define		MSR_DDSR	0x02	/* Delta Data Set Ready */
+#define		MSR_DRI		0x04	/* Trail Edge Ring Indicator */
+#define		MSR_DDCD	0x08	/* Delta Data Carrier Detect */
+#define		MSR_CTS		0x10	/* Clear To Send */
+#define		MSR_DSR		0x20	/* Data Set Ready */
+#define		MSR_RI		0x40	/* Ring Indicator */
+#define		MSR_DCD		0x80	/* Data Carrier Detect */
+
+#define 	DELTAS(x) 	((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD))
+#define 	STATES(x) 	((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD))
+
+
+#define		FCR_FIFOEN	0x01	/* enable receive/transmit fifo */
+#define		FCR_RxFIFO	0x02	/* enable receive fifo */
+#define		FCR_TxFIFO	0x04	/* enable transmit fifo */
+#define 	FCR_MODE1	0x08	/* change to mode 1 */
+#define		RxLVL0		0x00	/* Rx fifo level at 1	*/
+#define		RxLVL1		0x40	/* Rx fifo level at 4 */
+#define		RxLVL2		0x80	/* Rx fifo level at 8 */
+#define		RxLVL3		0xc0	/* Rx fifo level at 14 */
+
+#define 	FIFOEN		(FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 
+
+#define		FCT_TxMASK	0x30	/* mask for Tx trigger */
+#define		FCT_RxMASK	0xc0	/* mask for Rx trigger */
+
+/* enhanced festures register */
+#define		EFR_SFLOW	0x0f	/* various S/w Flow Controls */
+#define 	EFR_EIC		0x10	/* Enhanced Interrupt Control bit */
+#define 	EFR_SCD		0x20	/* Special Character Detect */
+#define 	EFR_RTS		0x40	/* RTS flow control */
+#define 	EFR_CTS		0x80	/* CTS flow control */
+
+/* Rx Tx software flow controls in 16650 enhanced mode */
+#define		SFLOW_Tx0	0x00	/* no Xmit flow control */
+#define		SFLOW_Tx1	0x08	/* Transmit Xon1, Xoff1 */
+#define		SFLOW_Tx2	0x04	/* Transmit Xon2, Xoff2 */
+#define		SFLOW_Tx3	0x0c	/* Transmit Xon1,Xon2, Xoff1,Xoff2 */
+#define		SFLOW_Rx0	0x00	/* no Rcv flow control */
+#define		SFLOW_Rx1	0x02	/* Receiver compares Xon1, Xoff1 */
+#define		SFLOW_Rx2	0x01	/* Receiver compares Xon2, Xoff2 */
+
+#define	ASSERT_DTR(x)		(x |= MCR_DTR)
+#define	ASSERT_RTS(x)		(x |= MCR_RTS)
+#define DU_RTS_ASSERTED(x)  (((x) & MCR_RTS) != 0)
+#define DU_RTS_ASSERT(x)    ((x) |= MCR_RTS)
+#define DU_RTS_DEASSERT(x)  ((x) &= ~MCR_RTS)
+
+
+/*
+ * ioctl(fd, I_STR, arg)
+ * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI
+ */
+#define SIOC        ('z' << 8)  /* z for z85130 */
+#define SIOC_EXTCLK (SIOC | 1)  /* select/de-select external clock */
+#define SIOC_RS422  (SIOC | 2)  /* select/de-select RS422 protocol */
+#define SIOC_ITIMER (SIOC | 3)  /* upstream timer adjustment */
+#define SIOC_LOOPBACK   (SIOC | 4)  /* diagnostic loopback test mode */
+
+
+/* channel control register */
+#define	DMA_INT_MASK		0xe0	/* ring intr mask */
+#define DMA_INT_TH25		0x20	/* 25% threshold */
+#define DMA_INT_TH50		0x40	/* 50% threshold */
+#define DMA_INT_TH75		0x60	/* 75% threshold */
+#define DMA_INT_EMPTY		0x80	/* ring buffer empty */
+#define DMA_INT_NEMPTY		0xa0	/* ring buffer not empty */
+#define DMA_INT_FULL		0xc0	/* ring buffer full */
+#define DMA_INT_NFULL		0xe0	/* ring buffer not full */
+
+#define DMA_CHANNEL_RESET	0x400	/* reset dma channel */
+#define DMA_ENABLE			0x200	/* enable DMA */
+
+/* peripheral controller intr status bits applicable to serial ports */
+#define ISA_SERIAL0_MASK 		0x03f00000	/* mask for port #1 intrs */
+#define ISA_SERIAL0_DIR			0x00100000	/* device intr request */
+#define ISA_SERIAL0_Tx_THIR		0x00200000	/* Transmit DMA threshold */
+#define ISA_SERIAL0_Tx_PREQ		0x00400000	/* Transmit DMA pair req */
+#define ISA_SERIAL0_Tx_MEMERR	0x00800000	/* Transmit DMA memory err */
+#define ISA_SERIAL0_Rx_THIR		0x01000000	/* Receive DMA threshold  */
+#define ISA_SERIAL0_Rx_OVERRUN	0x02000000	/* Receive DMA over-run  */
+
+#define ISA_SERIAL1_MASK 		0xfc000000	/* mask for port #1 intrs */
+#define ISA_SERIAL1_DIR			0x04000000	/* device intr request */
+#define ISA_SERIAL1_Tx_THIR		0x08000000	/* Transmit DMA threshold */
+#define ISA_SERIAL1_Tx_PREQ		0x10000000	/* Transmit DMA pair req */
+#define ISA_SERIAL1_Tx_MEMERR	0x20000000	/* Transmit DMA memory err */
+#define ISA_SERIAL1_Rx_THIR		0x40000000	/* Receive DMA threshold  */
+#define ISA_SERIAL1_Rx_OVERRUN	0x80000000	/* Receive DMA over-run  */
+
+#define MAX_RING_BLOCKS		128			/* 4096/32 */
+#define MAX_RING_SIZE		4096
+
+/* DMA Input Control Byte */
+#define	DMA_IC_OVRRUN	0x01	/* overrun error */
+#define	DMA_IC_PARERR	0x02	/* parity error */
+#define	DMA_IC_FRMERR	0x04	/* framing error */
+#define	DMA_IC_BRKDET 	0x08	/* a break has arrived */
+#define DMA_IC_VALID	0x80	/* pair is valid */
+
+/* DMA Output Control Byte */
+#define DMA_OC_TxINTR	0x20	/* set Tx intr after processing byte */
+#define DMA_OC_INVALID	0x00	/* invalid pair */
+#define DMA_OC_WTHR		0x40	/* Write byte to THR */
+#define DMA_OC_WMCR		0x80	/* Write byte to MCR */
+#define DMA_OC_DELAY	0xc0	/* time delay before next xmit */
+
+/* ring id's */
+#define RID_SERIAL0_TX	0x4		/* serial port 0, transmit ring buffer */
+#define RID_SERIAL0_RX	0x5		/* serial port 0, receive ring buffer */
+#define RID_SERIAL1_TX	0x6		/* serial port 1, transmit ring buffer */
+#define RID_SERIAL1_RX	0x7		/* serial port 1, receive ring buffer */
+
+#define CLOCK_XIN			22
+#define PRESCALER_DIVISOR	3
+#define CLOCK_ACE			7333333
+
+/*
+ * increment the ring offset. One way to do this would be to add b'100000.
+ * this would let the offset value roll over automatically when it reaches
+ * its maximum value (127). However when we use the offset, we must use
+ * the appropriate bits only by masking with 0xfe0.
+ * The other option is to shift the offset right by 5 bits and look at its
+ * value. Then increment if required and shift back
+ * note: 127 * 2^5 = 4064
+ */
+#define INC_RING_POINTER(x) \
+	( ((x & 0xffe0) < 4064) ? (x += 32) : 0 )
+
+#endif /* _ASM_IA64_SN_UART16550_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/vector.h lia64-2.4/include/asm-ia64/sn/vector.h
--- linux-2.4.16/include/asm-ia64/sn/vector.h	Thu Jan  4 15:25:55 2001
+++ lia64-2.4/include/asm-ia64/sn/vector.h	Mon Nov 19 23:23:00 2001
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_VECTOR_H
-#define _ASM_SN_VECTOR_H
+#ifndef _ASM_IA64_SN_VECTOR_H
+#define _ASM_IA64_SN_VECTOR_H
 
 #include <linux/config.h>
 
@@ -37,7 +36,7 @@
 
 #endif /* RTL */
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #define VECTOR_PARMS		LB_VECTOR_PARMS
 #define VECTOR_ROUTE		LB_VECTOR_ROUTE
 #define VECTOR_DATA		LB_VECTOR_DATA
@@ -78,7 +77,7 @@
 #define NET_ERROR_ROUTERLOCK   -9       /* Timeout locking rtr  */
 #define NET_ERROR_INVAL	       -10	/* Invalid vector request */
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 typedef uint64_t              net_reg_t;
 typedef uint64_t              net_vec_t;
 
@@ -114,6 +113,6 @@
 	int addr, net_reg_t *value);
 #endif
 
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_VECTOR_H */
+#endif /* _ASM_IA64_SN_VECTOR_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xbow.h lia64-2.4/include/asm-ia64/sn/xtalk/xbow.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xbow.h	Tue Mar  6 19:44:34 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xbow.h	Mon Nov 19 23:23:00 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_SN_XTALK_XBOW_H
@@ -17,7 +17,7 @@
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/xtalk/xwidget.h>
 #include <asm/sn/xtalk/xswitch.h>
-#ifdef LANGUAGE_C
+#ifndef __ASSEMBLY__
 #include <asm/sn/xtalk/xbow_info.h>
 #endif
 
@@ -46,7 +46,7 @@
 
 #define MAX_XBOW_NAME 	16
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef uint32_t      xbowreg_t;
 
 #define XBOWCONST	(xbowreg_t)
@@ -236,7 +236,7 @@
 /* offset of arbitration register, given source widget id */
 #define XBOW_ARB_OFF(wid) 	(XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
 
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define	XBOW_WID_ID		WIDGET_ID
 #define	XBOW_WID_STAT		WIDGET_STATUS
@@ -402,7 +402,7 @@
 	(XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM)
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /*
  * XBOW Widget 0 Register formats.
  * Format for many of these registers are similar to the standard
@@ -891,5 +891,5 @@
 
 #endif				/* MACROFIELD_LINE */
 
-#endif				/* _LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 #endif                          /* _ASM_SN_SN_XTALK_XBOW_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xbow_info.h lia64-2.4/include/asm-ia64/sn/xtalk/xbow_info.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xbow_info.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xbow_info.h	Mon Nov 19 23:23:00 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XBOW_INFO_H
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xswitch.h lia64-2.4/include/asm-ia64/sn/xtalk/xswitch.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xswitch.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xswitch.h	Mon Nov 19 23:23:00 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XSWITCH_H
@@ -16,7 +16,7 @@
  * xtalk bus providers.
  */
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 typedef struct xswitch_info_s *xswitch_info_t;
 
@@ -54,6 +54,6 @@
 extern int		xswitch_id_get(devfs_handle_t vhdl);
 extern void		xswitch_id_set(devfs_handle_t vhdl,int xbow_num);
 
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #endif				/* _ASM_SN_XTALK_XSWITCH_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xtalk.h lia64-2.4/include/asm-ia64/sn/xtalk/xtalk.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xtalk.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xtalk.h	Mon Nov 26 18:07:20 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XTALK_H
@@ -57,7 +57,7 @@
 #include <asm/sn/types.h>
 #include <asm/sn/alenlist.h>
 #include <asm/sn/ioerror.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/dmamap.h>
 
 struct xwidget_hwid_s;
@@ -205,14 +205,8 @@
 
 typedef int
 xtalk_intr_connect_f    (xtalk_intr_t intr_hdl,		/* xtalk intr resource handle */
-			 intr_func_t intr_func,		/* xtalk intr handler */
-			 void *intr_arg,	/* arg to intr handler */
 			 xtalk_intr_setfunc_f *setfunc,		/* func to set intr hw */
-			 void *setfunc_arg,	/* arg to setfunc. This must be */
-							/* sufficient to determine which */
-							/* interrupt on which board needs */
-							/* to be set. */
-			 void *thread);		/* which intr thread to use */
+			 void *setfunc_arg);	/* arg to setfunc */
 
 typedef void
 xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl);
@@ -400,7 +394,6 @@
 
 extern int		xtalk_device_powerup(devfs_handle_t, xwidgetnum_t);
 extern int		xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t);
-extern int		xtalk_device_inquiry(devfs_handle_t, xwidgetnum_t);
 
 #endif				/* __KERNEL__ */
 #endif				/* _ASM_SN_XTALK_XTALK_H */
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xtalk_private.h lia64-2.4/include/asm-ia64/sn/xtalk/xtalk_private.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xtalk_private.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xtalk_private.h	Mon Nov 19 23:23:00 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xtalkaddrs.h lia64-2.4/include/asm-ia64/sn/xtalk/xtalkaddrs.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xtalkaddrs.h	Thu Apr  5 12:51:47 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xtalkaddrs.h	Mon Nov 19 23:23:00 2001
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XTALKADDRS_H
 #define _ASM_SN_XTALK_XTALKADDRS_H
 
-#include <linux/config.h>
 
 /*
  * CrossTalk to SN0 Hub addressing support
@@ -60,19 +59,15 @@
  * This looks very much like a REMOTE_HUB access, except the nodeID
  * is in a different place, and the highest xtalk bit is set.
  */
-
 /* Hub-specific xtalk definitions */
 
 #define HX_MEM_BIT		0L	/* Hub's idea of xtalk memory access */
 #define HX_IO_BIT		1L	/* Hub's idea of xtalk register access */
 #define HX_ACCTYPE_SHIFT	47
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
 #define HX_NODE_SHIFT		39
-#endif
 
 #define HX_BIGWIN_SHIFT		28
-
 #define HX_SWIN_SHIFT		23
 
 #define HX_LOCACC		0L	/* local access */
diff -urN linux-2.4.16/include/asm-ia64/sn/xtalk/xwidget.h lia64-2.4/include/asm-ia64/sn/xtalk/xwidget.h
--- linux-2.4.16/include/asm-ia64/sn/xtalk/xwidget.h	Thu Jan  4 13:00:15 2001
+++ lia64-2.4/include/asm-ia64/sn/xtalk/xwidget.h	Mon Nov 19 23:23:00 2001
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef __ASM_SN_XTALK_XWIDGET_H__
@@ -15,9 +15,9 @@
  */
 
 #include <asm/sn/xtalk/xtalk.h>
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 #include <asm/sn/cdl.h>
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 #ifdef LITTLE_ENDIAN
 #define WIDGET_ID			0x00
@@ -115,7 +115,7 @@
  * widget target flush register are widget dependent thus will not be
  * defined here
  */
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef uint32_t      widgetreg_t;
 
 /* widget configuration registers */
@@ -267,9 +267,6 @@
 					 async_attach_t aa);
 
 extern int		xwidget_unregister(devfs_handle_t);
-extern void	        xwidget_error_register(devfs_handle_t xwidget,
-						error_handler_f * efunc,
-						error_handler_arg_t einfo);
 
 extern void             xwidget_reset(devfs_handle_t xwidget);
 extern void             xwidget_gfx_reset(devfs_handle_t xwidget);
@@ -289,6 +286,9 @@
 extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info);
 extern xwidget_mfg_num_t xwidget_info_mfg_num_get(xwidget_info_t xwidget_info);
 
+extern xwidgetnum_t hub_widget_id(nasid_t);
+
+
 
 /*
  * TBD: DELETE THIS ENTIRE STRUCTURE!  Equivalent is now in
@@ -303,6 +303,6 @@
 } v_widget_t;
 #endif				/* _KERNEL */
 
-#endif				/* _LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #endif				/* __ASM_SN_XTALK_XWIDGET_H__ */
diff -urN linux-2.4.16/include/asm-ia64/spinlock.h lia64-2.4/include/asm-ia64/spinlock.h
--- linux-2.4.16/include/asm-ia64/spinlock.h	Mon Nov 26 11:19:18 2001
+++ lia64-2.4/include/asm-ia64/spinlock.h	Mon Nov 26 18:05:56 2001
@@ -93,7 +93,7 @@
 	"cmp4.eq p0,p7 = r0, r2\n"				\
 	"(p7) br.cond.spnt.few 1b\n"				\
 	";;\n"							\
-	:: "r"(&(x)->lock) : "r2", "r29", "memory")
+	:: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory")
 
 #define spin_is_locked(x)	((x)->lock != 0)
 #define spin_unlock(x)		do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
@@ -128,7 +128,7 @@
 			      ";;\n"						\
 			      ".previous\n"					\
 			      : "=&r" (tmp)					\
-			      : "r" (rw): "memory");				\
+			      : "r" (rw) : "p6", "memory");			\
 } while(0)
 
 #define read_unlock(rw)								\
@@ -156,7 +156,7 @@
 		"cmp4.eq p0,p7 = r0, r2\n"					\
 		"(p7) br.cond.spnt.few 1b\n"					\
 		";;\n"								\
-		:: "r"(rw) : "r2", "r29", "memory");				\
+		:: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");		\
 } while(0)
 
 /*
diff -urN linux-2.4.16/include/linux/agp_backend.h lia64-2.4/include/linux/agp_backend.h
--- linux-2.4.16/include/linux/agp_backend.h	Mon Nov 26 11:19:19 2001
+++ lia64-2.4/include/linux/agp_backend.h	Mon Nov 26 11:26:35 2001
@@ -27,6 +27,8 @@
 #ifndef _AGP_BACKEND_H
 #define _AGP_BACKEND_H 1
 
+#include <linux/config.h>
+
 #ifndef TRUE
 #define TRUE 1
 #endif
@@ -52,6 +54,7 @@
 	INTEL_I845,
 	INTEL_I850,
 	INTEL_I860,
+	INTEL_460GX,
 	VIA_GENERIC,
 	VIA_VP3,
 	VIA_MVP3,
@@ -115,6 +118,7 @@
 	size_t page_count;
 	int num_scratch_pages;
 	unsigned long *memory;
+	void *vmptr;
 	off_t pg_start;
 	u32 type;
 	u32 physical;
diff -urN linux-2.4.16/include/linux/crc32.h lia64-2.4/include/linux/crc32.h
--- linux-2.4.16/include/linux/crc32.h	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/include/linux/crc32.h	Wed Dec  6 22:40:05 2000
@@ -0,0 +1,17 @@
+/*
+ * crc32.h
+ * See linux/lib/crc32.c for license and changes
+ */
+#ifndef _LINUX_CRC32_H
+#define _LINUX_CRC32_H
+
+#include <linux/types.h>
+
+/*
+ * This computes a 32 bit CRC of the data in the buffer, and returns the CRC.
+ * The polynomial used is 0xedb88320.
+ */
+
+extern u32 crc32 (const void *buf, unsigned long len, u32 seed);
+
+#endif /* _LINUX_CRC32_H */
diff -urN linux-2.4.16/include/linux/devfs_fs_kernel.h lia64-2.4/include/linux/devfs_fs_kernel.h
--- linux-2.4.16/include/linux/devfs_fs_kernel.h	Mon Sep 24 15:08:33 2001
+++ lia64-2.4/include/linux/devfs_fs_kernel.h	Mon Nov 26 18:07:20 2001
@@ -97,6 +97,9 @@
 extern devfs_handle_t devfs_get_next_sibling (devfs_handle_t de);
 extern void devfs_auto_unregister (devfs_handle_t master,devfs_handle_t slave);
 extern devfs_handle_t devfs_get_unregister_slave (devfs_handle_t master);
+#ifdef CONFIG_DEVFS_GUID
+extern void devfs_unregister_slave (devfs_handle_t master);
+#endif
 extern const char *devfs_get_name (devfs_handle_t de, unsigned int *namelen);
 extern int devfs_register_chrdev (unsigned int major, const char *name,
 				  struct file_operations *fops);
diff -urN linux-2.4.16/include/linux/genhd.h lia64-2.4/include/linux/genhd.h
--- linux-2.4.16/include/linux/genhd.h	Wed Oct 24 10:18:08 2001
+++ lia64-2.4/include/linux/genhd.h	Mon Nov 26 18:07:20 2001
@@ -13,6 +13,10 @@
 #include <linux/types.h>
 #include <linux/major.h>
 
+#ifdef CONFIG_DEVFS_GUID
+#include <asm-ia64/efi.h>
+#endif
+
 enum {
 /* These three have identical behaviour; use the second one if DOS fdisk gets
    confused about extended/logical partitions starting past cylinder 1023. */
@@ -62,6 +66,9 @@
 	unsigned long nr_sects;
 	devfs_handle_t de;              /* primary (master) devfs entry  */
 	int number;                     /* stupid old code wastes space  */
+#ifdef CONFIG_DEVFS_GUID
+	efi_guid_t *guid;
+#endif
 };
 
 #define GENHD_FL_REMOVABLE  1
diff -urN linux-2.4.16/include/linux/highmem.h lia64-2.4/include/linux/highmem.h
--- linux-2.4.16/include/linux/highmem.h	Mon Sep 24 15:08:33 2001
+++ lia64-2.4/include/linux/highmem.h	Mon Nov 26 18:06:05 2001
@@ -46,7 +46,7 @@
 static inline void clear_user_highpage(struct page *page, unsigned long vaddr)
 {
 	void *addr = kmap_atomic(page, KM_USER0);
-	clear_user_page(addr, vaddr);
+	clear_user_page(addr, vaddr, page);
 	kunmap_atomic(addr, KM_USER0);
 }
 
@@ -88,7 +88,7 @@
 
 	vfrom = kmap_atomic(from, KM_USER0);
 	vto = kmap_atomic(to, KM_USER1);
-	copy_user_page(vto, vfrom, vaddr);
+	copy_user_page(vto, vfrom, vaddr, to);
 	kunmap_atomic(vfrom, KM_USER0);
 	kunmap_atomic(vto, KM_USER1);
 }
diff -urN linux-2.4.16/include/linux/irq.h lia64-2.4/include/linux/irq.h
--- linux-2.4.16/include/linux/irq.h	Mon Sep 24 15:08:33 2001
+++ lia64-2.4/include/linux/irq.h	Mon Nov 26 18:05:58 2001
@@ -56,15 +56,13 @@
  *
  * Pad this out to 32 bytes for cache and indexing reasons.
  */
-typedef struct {
+typedef struct irq_desc {
 	unsigned int status;		/* IRQ status */
 	hw_irq_controller *handler;
 	struct irqaction *action;	/* IRQ action list */
 	unsigned int depth;		/* nested irq disables */
 	spinlock_t lock;
 } ____cacheline_aligned irq_desc_t;
-
-extern irq_desc_t irq_desc [NR_IRQS];
 
 #include <asm/hw_irq.h> /* the arch dependent stuff */
 
diff -urN linux-2.4.16/include/linux/irq_cpustat.h lia64-2.4/include/linux/irq_cpustat.h
--- linux-2.4.16/include/linux/irq_cpustat.h	Fri Aug 10 18:13:47 2001
+++ lia64-2.4/include/linux/irq_cpustat.h	Mon Jul 23 14:21:12 2001
@@ -23,12 +23,12 @@
 #define __IRQ_STAT(cpu, member)	(irq_stat[cpu].member)
 #else
 #define __IRQ_STAT(cpu, member)	((void)(cpu), irq_stat[0].member)
-#endif	
+#endif
 
   /* arch independent irq_stat fields */
 #define softirq_pending(cpu)	__IRQ_STAT((cpu), __softirq_pending)
-#define local_irq_count(cpu)	__IRQ_STAT((cpu), __local_irq_count)
-#define local_bh_count(cpu)	__IRQ_STAT((cpu), __local_bh_count)
+#define irq_count(cpu)		__IRQ_STAT((cpu), __irq_count)
+#define bh_count(cpu)		__IRQ_STAT((cpu), __bh_count)
 #define syscall_count(cpu)	__IRQ_STAT((cpu), __syscall_count)
 #define ksoftirqd_task(cpu)	__IRQ_STAT((cpu), __ksoftirqd_task)
   /* arch dependent irq_stat fields */
diff -urN linux-2.4.16/include/linux/kernel.h lia64-2.4/include/linux/kernel.h
--- linux-2.4.16/include/linux/kernel.h	Mon Nov 26 11:19:22 2001
+++ lia64-2.4/include/linux/kernel.h	Mon Nov 26 11:22:44 2001
@@ -36,6 +36,13 @@
 #define	KERN_INFO	"<6>"	/* informational			*/
 #define	KERN_DEBUG	"<7>"	/* debug-level messages			*/
 
+extern int console_printk[];
+
+#define console_loglevel (console_printk[0])
+#define default_message_loglevel (console_printk[1])
+#define minimum_console_loglevel (console_printk[2])
+#define default_console_loglevel (console_printk[3])
+
 # define NORET_TYPE    /**/
 # define ATTRIB_NORET  __attribute__((noreturn))
 # define NORET_AND     noreturn,
@@ -81,8 +88,6 @@
 
 asmlinkage int printk(const char * fmt, ...)
 	__attribute__ ((format (printf, 1, 2)));
-
-extern int console_loglevel;
 
 static inline void console_silent(void)
 {
diff -urN linux-2.4.16/include/linux/mm.h lia64-2.4/include/linux/mm.h
--- linux-2.4.16/include/linux/mm.h	Mon Nov 26 11:19:36 2001
+++ lia64-2.4/include/linux/mm.h	Mon Nov 26 18:06:04 2001
@@ -102,6 +102,8 @@
 #define VM_DONTCOPY	0x00020000      /* Do not copy this vma on fork */
 #define VM_DONTEXPAND	0x00040000	/* Cannot expand with mremap() */
 #define VM_RESERVED	0x00080000	/* Don't unmap it from swap_out */
+#define VM_WRITECOMBINED 0x00100000	/* Write-combined */
+#define VM_NONCACHED	0x00200000	/* Noncached access */
 
 #define VM_STACK_FLAGS	0x00000177
 
diff -urN linux-2.4.16/include/linux/prctl.h lia64-2.4/include/linux/prctl.h
--- linux-2.4.16/include/linux/prctl.h	Thu Jul 19 20:39:57 2001
+++ lia64-2.4/include/linux/prctl.h	Wed Oct 10 15:56:53 2001
@@ -20,4 +20,10 @@
 #define PR_GET_KEEPCAPS   7
 #define PR_SET_KEEPCAPS   8
 
+/* Get/set floating-point emulation control bits (if meaningful) */
+#define PR_GET_FPEMU  9
+#define PR_SET_FPEMU 10
+# define PR_FPEMU_NOPRINT	1	/* silently emulate fp operations accesses */
+# define PR_FPEMU_SIGFPE	2	/* don't emulate fp operations, send SIGFPE instead */
+
 #endif /* _LINUX_PRCTL_H */
diff -urN linux-2.4.16/include/linux/smp.h lia64-2.4/include/linux/smp.h
--- linux-2.4.16/include/linux/smp.h	Fri Aug 10 18:13:47 2001
+++ lia64-2.4/include/linux/smp.h	Mon Nov 26 18:05:56 2001
@@ -35,11 +35,6 @@
 extern void smp_boot_cpus(void);
 
 /*
- * Processor call in. Must hold processors until ..
- */
-extern void smp_callin(void);
-
-/*
  * Multiprocessors may now schedule
  */
 extern void smp_commence(void);
@@ -53,13 +48,9 @@
 /*
  * True once the per process idle is forked
  */
-extern int smp_threads_ready;
+extern volatile int smp_threads_ready;
 
 extern int smp_num_cpus;
-
-extern volatile unsigned long smp_msg_data;
-extern volatile int smp_src_cpu;
-extern volatile int smp_msg_id;
 
 #define MSG_ALL_BUT_SELF	0x8000	/* Assume <32768 CPU's */
 #define MSG_ALL			0x8001
diff -urN linux-2.4.16/include/linux/time.h lia64-2.4/include/linux/time.h
--- linux-2.4.16/include/linux/time.h	Fri Aug 10 18:13:46 2001
+++ lia64-2.4/include/linux/time.h	Mon Nov 26 18:05:56 2001
@@ -101,7 +101,10 @@
 extern void do_gettimeofday(struct timeval *tv);
 extern void do_settimeofday(struct timeval *tv);
 extern void get_fast_time(struct timeval *tv);
-extern void (*do_get_fast_time)(struct timeval *);
+# ifdef __ia64__
+   /* XXX clean this up: this should be platform-specific... */
+   extern void (*do_get_fast_time)(struct timeval *);
+# endif
 #endif
 
 #define FD_SETSIZE		__FD_SETSIZE
diff -urN linux-2.4.16/include/net/inetpeer.h lia64-2.4/include/net/inetpeer.h
--- linux-2.4.16/include/net/inetpeer.h	Fri Aug 10 18:13:48 2001
+++ lia64-2.4/include/net/inetpeer.h	Mon Nov 26 18:07:10 2001
@@ -38,7 +38,7 @@
 extern struct inet_peer *inet_peer_unused_head;
 extern struct inet_peer **inet_peer_unused_tailp;
 /* can be called from BH context or outside */
-extern inline void	inet_putpeer(struct inet_peer *p)
+static inline void	inet_putpeer(struct inet_peer *p)
 {
 	spin_lock_bh(&inet_peer_unused_lock);
 	if (atomic_dec_and_test(&p->refcnt)) {
@@ -53,7 +53,7 @@
 
 extern spinlock_t inet_peer_idlock;
 /* can be called with or without local BH being disabled */
-extern inline __u16	inet_getid(struct inet_peer *p)
+static inline __u16	inet_getid(struct inet_peer *p)
 {
 	__u16 id;
 
diff -urN linux-2.4.16/init/main.c lia64-2.4/init/main.c
--- linux-2.4.16/init/main.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/init/main.c	Mon Nov 26 17:14:21 2001
@@ -106,6 +106,9 @@
 #if defined(CONFIG_SYSVIPC)
 extern void ipc_init(void);
 #endif
+#ifdef CONFIG_PERFMON
+extern void perfmon_init(void);
+#endif
 
 /*
  * Boot command-line arguments
@@ -591,6 +594,9 @@
 #endif
 	mem_init();
 	kmem_cache_sizes_init();
+#ifdef CONFIG_PERFMON
+	perfmon_init();
+#endif
 	mempages = num_physpages;
 
 	fork_init(mempages);
diff -urN linux-2.4.16/kernel/exec_domain.c lia64-2.4/kernel/exec_domain.c
--- linux-2.4.16/kernel/exec_domain.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/kernel/exec_domain.c	Mon Nov 26 11:22:46 2001
@@ -198,8 +198,10 @@
 
 	put_exec_domain(oep);
 
+#if 0
 	printk(KERN_DEBUG "[%s:%d]: set personality to %lx\n",
 			current->comm, current->pid, personality);
+#endif
 	return 0;
 }
 
diff -urN linux-2.4.16/kernel/ksyms.c lia64-2.4/kernel/ksyms.c
--- linux-2.4.16/kernel/ksyms.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/kernel/ksyms.c	Mon Nov 26 18:00:06 2001
@@ -353,7 +353,7 @@
 EXPORT_SYMBOL(del_timer);
 EXPORT_SYMBOL(request_irq);
 EXPORT_SYMBOL(free_irq);
-#if !defined(CONFIG_ARCH_S390)
+#if !defined(CONFIG_ARCH_S390) && !defined(CONFIG_IA64)
 EXPORT_SYMBOL(irq_stat);	/* No separate irq_stat for s390, it is part of PSA */
 #endif
 
diff -urN linux-2.4.16/kernel/pm.c lia64-2.4/kernel/pm.c
--- linux-2.4.16/kernel/pm.c	Fri Apr  6 10:51:19 2001
+++ lia64-2.4/kernel/pm.c	Mon Jul 23 14:22:24 2001
@@ -162,7 +162,7 @@
 	case PM_SUSPEND:
 	case PM_RESUME:
 		prev_state = dev->state;
-		next_state = (int) data;
+		next_state = (long) data;
 		if (prev_state != next_state) {
 			if (dev->callback)
 				status = (*dev->callback)(dev, rqst, data);
@@ -197,7 +197,7 @@
 			 */
 			pm_request_t undo = (dev->prev_state
 					     ? PM_SUSPEND:PM_RESUME);
-			pm_send(dev, undo, (void*) dev->prev_state);
+			pm_send(dev, undo, (void*) (long) dev->prev_state);
 		}
 		entry = entry->prev;
 	}
diff -urN linux-2.4.16/kernel/printk.c lia64-2.4/kernel/printk.c
--- linux-2.4.16/kernel/printk.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/kernel/printk.c	Mon Nov 26 11:22:47 2001
@@ -16,6 +16,7 @@
  *	01Mar01 Andrew Morton <andrewm@uow.edu.au>
  */
 
+#include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/tty_driver.h>
@@ -24,11 +25,10 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>			/* For in_interrupt() */
-#include <linux/config.h>
 
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_MULTIQUAD
+#if defined(CONFIG_MULTIQUAD) || defined(CONFIG_IA64)
 #define LOG_BUF_LEN	(65536)
 #elif defined(CONFIG_SMP)
 #define LOG_BUF_LEN	(32768)
@@ -47,11 +47,12 @@
 
 DECLARE_WAIT_QUEUE_HEAD(log_wait);
 
-/* Keep together for sysctl support */
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
-int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL;
-int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
-int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_printk[4] = {
+	DEFAULT_CONSOLE_LOGLEVEL,	/* console_loglevel */
+	DEFAULT_MESSAGE_LOGLEVEL,	/* default_message_loglevel */
+	MINIMUM_CONSOLE_LOGLEVEL,	/* minimum_console_loglevel */
+	DEFAULT_CONSOLE_LOGLEVEL,	/* default_console_loglevel */
+};
 
 int oops_in_progress;
 
@@ -318,6 +319,12 @@
 			__call_console_drivers(start, end);
 		}
 	}
+#ifdef CONFIG_IA64_EARLY_PRINTK
+	if (!console_drivers) {
+		static void early_printk (const char *str, size_t len);
+		early_printk(&LOG_BUF(start), end - start);
+	}
+#endif
 }
 
 /*
@@ -668,3 +675,50 @@
 		tty->driver.write(tty, 0, msg, strlen(msg));
 	return;
 }
+
+#ifdef CONFIG_IA64_EARLY_PRINTK
+
+#include <asm/io.h>
+
+#define VGABASE		((char *)0xc0000000000b8000)
+#define VGALINES	24
+#define VGACOLS		80
+
+static int current_ypos = VGALINES, current_xpos = 0;
+
+void
+early_printk (const char *str, size_t len)
+{
+	char c;
+	int  i, k, j;
+
+	while (len-- > 0) {
+		c = *str++;
+		if (current_ypos >= VGALINES) {
+			/* scroll 1 line up */
+			for (k = 1, j = 0; k < VGALINES; k++, j++) {
+				for (i = 0; i < VGACOLS; i++) {
+					writew(readw(VGABASE + 2*(VGACOLS*k + i)),
+					       VGABASE + 2*(VGACOLS*j + i));
+				}
+			}
+			for (i = 0; i < VGACOLS; i++) {
+				writew(0x720, VGABASE + 2*(VGACOLS*j + i));
+			}
+			current_ypos = VGALINES-1;
+		}
+		if (c == '\n') {
+			current_xpos = 0;
+			current_ypos++;
+		} else if (c != '\r')  {
+			writew(((0x7 << 8) | (unsigned short) c),
+			       VGABASE + 2*(VGACOLS*current_ypos + current_xpos++));
+			if (current_xpos >= VGACOLS) {
+				current_xpos = 0;
+				current_ypos++;
+			}
+		}
+	}
+}
+
+#endif /* CONFIG_IA64_EARLY_PRINTK */
diff -urN linux-2.4.16/kernel/ptrace.c lia64-2.4/kernel/ptrace.c
--- linux-2.4.16/kernel/ptrace.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/kernel/ptrace.c	Mon Nov 26 11:22:47 2001
@@ -162,14 +162,14 @@
 	flush_cache_page(vma, addr);
 
 	if (write) {
-		maddr = kmap(page);
-		memcpy(maddr + (addr & ~PAGE_MASK), buf, len);
+		maddr = kmap(page) + (addr & ~PAGE_MASK);
+		memcpy(maddr, buf, len);
 		flush_page_to_ram(page);
-		flush_icache_page(vma, page);
+		flush_icache_range((unsigned long) maddr, (unsigned long)maddr + len);
 		kunmap(page);
 	} else {
-		maddr = kmap(page);
-		memcpy(buf, maddr + (addr & ~PAGE_MASK), len);
+		maddr = kmap(page) + (addr & ~PAGE_MASK);
+		memcpy(buf, maddr, len);
 		flush_page_to_ram(page);
 		kunmap(page);
 	}
@@ -179,7 +179,7 @@
 fault_in_page:
 	spin_unlock(&mm->page_table_lock);
 	/* -1: out of memory. 0 - unmapped page */
-	if (handle_mm_fault(mm, vma, addr, write) > 0)
+	if (handle_mm_fault(mm, vma, addr, write ? VM_WRITE : VM_READ) > 0)
 		goto repeat;
 	return 0;
 
diff -urN linux-2.4.16/kernel/signal.c lia64-2.4/kernel/signal.c
--- linux-2.4.16/kernel/signal.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/kernel/signal.c	Mon Nov 26 11:22:47 2001
@@ -1104,8 +1104,19 @@
 			ss_sp = NULL;
 		} else {
 			error = -ENOMEM;
+#ifdef __ia64__
+			/*
+			 * XXX fix me: due to an oversight, MINSIGSTKSZ used to be defined
+			 * as 2KB, which is far too small.  This was after Linux kernel
+			 * 2.4.9 but since there are a fair number of ia64 apps out there,
+			 * we continue to allow "too" small sigaltstacks for a while.
+			 */
+			if (ss_size < 2048)
+				goto out;
+#else
 			if (ss_size < MINSIGSTKSZ)
 				goto out;
+#endif
 		}
 
 		current->sas_ss_sp = (unsigned long) ss_sp;
diff -urN linux-2.4.16/kernel/softirq.c lia64-2.4/kernel/softirq.c
--- linux-2.4.16/kernel/softirq.c	Mon Nov  5 18:29:05 2001
+++ lia64-2.4/kernel/softirq.c	Mon Nov  5 18:34:17 2001
@@ -40,7 +40,10 @@
    - Bottom halves: globally serialized, grr...
  */
 
+/* No separate irq_stat for ia64, it is part of PSA */
+#if !defined(CONFIG_IA64)
 irq_cpustat_t irq_stat[NR_CPUS];
+#endif	/* CONFIG_IA64 */
 
 static struct softirq_action softirq_vec[32] __cacheline_aligned;
 
@@ -60,7 +63,6 @@
 
 asmlinkage void do_softirq()
 {
-	int cpu = smp_processor_id();
 	__u32 pending;
 	long flags;
 	__u32 mask;
@@ -70,7 +72,7 @@
 
 	local_irq_save(flags);
 
-	pending = softirq_pending(cpu);
+	pending = local_softirq_pending();
 
 	if (pending) {
 		struct softirq_action *h;
@@ -79,7 +81,7 @@
 		local_bh_disable();
 restart:
 		/* Reset the pending bitmask before enabling irqs */
-		softirq_pending(cpu) = 0;
+		local_softirq_pending() = 0;
 
 		local_irq_enable();
 
@@ -94,7 +96,7 @@
 
 		local_irq_disable();
 
-		pending = softirq_pending(cpu);
+		pending = local_softirq_pending();
 		if (pending & mask) {
 			mask &= ~pending;
 			goto restart;
@@ -102,7 +104,7 @@
 		__local_bh_enable();
 
 		if (pending)
-			wakeup_softirqd(cpu);
+			wakeup_softirqd(smp_processor_id());
 	}
 
 	local_irq_restore(flags);
@@ -124,7 +126,7 @@
 	 * Otherwise we wake up ksoftirqd to make sure we
 	 * schedule the softirq soon.
 	 */
-	if (!(local_irq_count(cpu) | local_bh_count(cpu)))
+	if (!(irq_count(cpu) | bh_count(cpu)))
 		wakeup_softirqd(cpu);
 }
 
@@ -288,18 +290,16 @@
 
 static void bh_action(unsigned long nr)
 {
-	int cpu = smp_processor_id();
-
 	if (!spin_trylock(&global_bh_lock))
 		goto resched;
 
-	if (!hardirq_trylock(cpu))
+	if (!local_hardirq_trylock())
 		goto resched_unlock;
 
 	if (bh_base[nr])
 		bh_base[nr]();
 
-	hardirq_endlock(cpu);
+	local_hardirq_endlock();
 	spin_unlock(&global_bh_lock);
 	return;
 
@@ -378,15 +378,15 @@
 	__set_current_state(TASK_INTERRUPTIBLE);
 	mb();
 
-	ksoftirqd_task(cpu) = current;
+	local_ksoftirqd_task() = current;
 
 	for (;;) {
-		if (!softirq_pending(cpu))
+		if (!local_softirq_pending())
 			schedule();
 
 		__set_current_state(TASK_RUNNING);
 
-		while (softirq_pending(cpu)) {
+		while (local_softirq_pending()) {
 			do_softirq();
 			if (current->need_resched)
 				schedule();
diff -urN linux-2.4.16/kernel/sys.c lia64-2.4/kernel/sys.c
--- linux-2.4.16/kernel/sys.c	Mon Sep 24 15:08:39 2001
+++ lia64-2.4/kernel/sys.c	Wed Oct 10 15:57:24 2001
@@ -1245,6 +1245,22 @@
 #endif
 			break;
 
+	        case PR_SET_FPEMU:
+#ifdef SET_FPEMU_CTL
+			error = SET_FPEMU_CTL(current, arg2);
+#else
+			error = -EINVAL;
+#endif
+			break;
+
+	        case PR_GET_FPEMU:
+#ifdef GET_FPEMU_CTL
+			error = GET_FPEMU_CTL(current, arg2);
+#else
+			error = -EINVAL;
+#endif
+			break;
+
 		case PR_GET_KEEPCAPS:
 			if (current->keep_capabilities)
 				error = 1;
diff -urN linux-2.4.16/kernel/time.c lia64-2.4/kernel/time.c
--- linux-2.4.16/kernel/time.c	Mon Oct 16 12:58:51 2000
+++ lia64-2.4/kernel/time.c	Tue Aug 14 00:08:58 2001
@@ -36,11 +36,16 @@
  */
 struct timezone sys_tz;
 
+#ifndef __ia64__
+
 static void do_normal_gettime(struct timeval * tm)
 {
         *tm=xtime;
 }
 
+/* This indirection is needed only for x86 and other architectures
+   which do not have uniform support for cycle counters... */
+
 void (*do_get_fast_time)(struct timeval *) = do_normal_gettime;
 
 /*
@@ -54,9 +59,12 @@
 	do_get_fast_time(t);
 }
 
+#endif /* !__ia64__ */
+
 /* The xtime_lock is not only serializing the xtime read/writes but it's also
    serializing all accesses to the global NTP variables now. */
 extern rwlock_t xtime_lock;
+extern unsigned long last_time_offset;
 
 #if !defined(__alpha__) && !defined(__ia64__)
 
@@ -100,6 +108,7 @@
 	write_lock_irq(&xtime_lock);
 	xtime.tv_sec = value;
 	xtime.tv_usec = 0;
+	last_time_offset = 0;
 	time_adjust = 0;	/* stop active adjtime() */
 	time_status |= STA_UNSYNC;
 	time_maxerror = NTP_PHASE_LIMIT;
@@ -145,6 +154,7 @@
 {
 	write_lock_irq(&xtime_lock);
 	xtime.tv_sec += sys_tz.tz_minuteswest * 60;
+	last_time_offset = 0;
 	write_unlock_irq(&xtime_lock);
 }
 
@@ -231,13 +241,13 @@
 	/* In order to modify anything, you gotta be super-user! */
 	if (txc->modes && !capable(CAP_SYS_TIME))
 		return -EPERM;
-		
+
 	/* Now we validate the data before disabling interrupts */
 
 	if (txc->modes != ADJ_OFFSET_SINGLESHOT && (txc->modes & ADJ_OFFSET))
 	  /* adjustment Offset limited to +- .512 seconds */
 		if (txc->offset <= - MAXPHASE || txc->offset >= MAXPHASE )
-			return -EINVAL;	
+			return -EINVAL;
 
 	/* if the quartz is off by more than 10% something is VERY wrong ! */
 	if (txc->modes & ADJ_TICK)
@@ -374,7 +384,7 @@
 		&& (time_status & (STA_PPSWANDER|STA_PPSERROR)) != 0))
 	    /* p. 24, (d) */
 		result = TIME_ERROR;
-	
+
 	if ((txc->modes & ADJ_OFFSET_SINGLESHOT) == ADJ_OFFSET_SINGLESHOT)
 	    txc->offset	   = save_adjust;
 	else {
@@ -399,6 +409,7 @@
 	txc->calcnt	   = pps_calcnt;
 	txc->errcnt	   = pps_errcnt;
 	txc->stbcnt	   = pps_stbcnt;
+	last_time_offset = 0;
 	write_unlock_irq(&xtime_lock);
 	do_gettimeofday(&txc->time);
 	return(result);
diff -urN linux-2.4.16/kernel/timer.c lia64-2.4/kernel/timer.c
--- linux-2.4.16/kernel/timer.c	Wed Oct 10 16:32:16 2001
+++ lia64-2.4/kernel/timer.c	Wed Oct 10 16:35:15 2001
@@ -592,7 +592,7 @@
 		else
 			kstat.per_cpu_user[cpu] += user_tick;
 		kstat.per_cpu_system[cpu] += system;
-	} else if (local_bh_count(cpu) || local_irq_count(cpu) > 1)
+	} else if (local_bh_count() || local_irq_count() > 1)
 		kstat.per_cpu_system[cpu] += system;
 }
 
@@ -644,6 +644,7 @@
  * This spinlock protect us from races in SMP while playing with xtime. -arca
  */
 rwlock_t xtime_lock = RW_LOCK_UNLOCKED;
+unsigned long last_time_offset;
 
 static inline void update_times(void)
 {
@@ -661,6 +662,7 @@
 		wall_jiffies += ticks;
 		update_wall_time(ticks);
 	}
+	last_time_offset = 0;
 	write_unlock_irq(&xtime_lock);
 	calc_load(ticks);
 }
@@ -673,7 +675,7 @@
 
 void do_timer(struct pt_regs *regs)
 {
-	(*(unsigned long *)&jiffies)++;
+	(*(volatile unsigned long *)&jiffies)++;
 #ifndef CONFIG_SMP
 	/* SMP process accounting uses the local APIC timer */
 
@@ -811,7 +813,7 @@
 	if (t.tv_nsec >= 1000000000L || t.tv_nsec < 0 || t.tv_sec < 0)
 		return -EINVAL;
 
-
+#if !defined(__ia64__)
 	if (t.tv_sec == 0 && t.tv_nsec <= 2000000L &&
 	    current->policy != SCHED_OTHER)
 	{
@@ -824,6 +826,7 @@
 		udelay((t.tv_nsec + 999) / 1000);
 		return 0;
 	}
+#endif
 
 	expire = timespec_to_jiffies(&t) + (t.tv_sec || t.tv_nsec);
 
diff -urN linux-2.4.16/lib/Makefile lia64-2.4/lib/Makefile
--- linux-2.4.16/lib/Makefile	Mon Sep 24 15:08:39 2001
+++ lia64-2.4/lib/Makefile	Mon Sep 24 21:29:52 2001
@@ -10,7 +10,7 @@
 
 export-objs := cmdline.o dec_and_lock.o rwsem-spinlock.o rwsem.o
 
-obj-y := errno.o ctype.o string.o vsprintf.o brlock.o cmdline.o bust_spinlocks.o rbtree.o
+obj-y := errno.o ctype.o string.o vsprintf.o brlock.o cmdline.o bust_spinlocks.o rbtree.o crc32.o
 
 obj-$(CONFIG_RWSEM_GENERIC_SPINLOCK) += rwsem-spinlock.o
 obj-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
diff -urN linux-2.4.16/lib/crc32.c lia64-2.4/lib/crc32.c
--- linux-2.4.16/lib/crc32.c	Wed Dec 31 16:00:00 1969
+++ lia64-2.4/lib/crc32.c	Wed Dec  6 22:41:15 2000
@@ -0,0 +1,125 @@
+/* 
+ * Dec 5, 2000 Matt Domsch <Matt_Domsch@dell.com>
+ * - Copied crc32.c from the linux/drivers/net/cipe directory.
+ * - Now pass seed as an arg
+ * - changed unsigned long to u32, added #include<linux/types.h>
+ * - changed len to be an unsigned long
+ * - changed crc32val to be a register
+ * - License remains unchanged!  It's still GPL-compatable!
+ */
+
+  /* ============================================================= */
+  /*  COPYRIGHT (C) 1986 Gary S. Brown.  You may use this program, or       */
+  /*  code or tables extracted from it, as desired without restriction.     */
+  /*                                                                        */
+  /*  First, the polynomial itself and its table of feedback terms.  The    */
+  /*  polynomial is                                                         */
+  /*  X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0   */
+  /*                                                                        */
+  /*  Note that we take it "backwards" and put the highest-order term in    */
+  /*  the lowest-order bit.  The X^32 term is "implied"; the LSB is the     */
+  /*  X^31 term, etc.  The X^0 term (usually shown as "+1") results in      */
+  /*  the MSB being 1.                                                      */
+  /*                                                                        */
+  /*  Note that the usual hardware shift register implementation, which     */
+  /*  is what we're using (we're merely optimizing it by doing eight-bit    */
+  /*  chunks at a time) shifts bits into the lowest-order term.  In our     */
+  /*  implementation, that means shifting towards the right.  Why do we     */
+  /*  do it this way?  Because the calculated CRC must be transmitted in    */
+  /*  order from highest-order term to lowest-order term.  UARTs transmit   */
+  /*  characters in order from LSB to MSB.  By storing the CRC this way,    */
+  /*  we hand it to the UART in the order low-byte to high-byte; the UART   */
+  /*  sends each low-bit to hight-bit; and the result is transmission bit   */
+  /*  by bit from highest- to lowest-order term without requiring any bit   */
+  /*  shuffling on our part.  Reception works similarly.                    */
+  /*                                                                        */
+  /*  The feedback terms table consists of 256, 32-bit entries.  Notes:     */
+  /*                                                                        */
+  /*      The table can be generated at runtime if desired; code to do so   */
+  /*      is shown later.  It might not be obvious, but the feedback        */
+  /*      terms simply represent the results of eight shift/xor opera-      */
+  /*      tions for all combinations of data and CRC register values.       */
+  /*                                                                        */
+  /*      The values must be right-shifted by eight bits by the "updcrc"    */
+  /*      logic; the shift must be unsigned (bring in zeroes).  On some     */
+  /*      hardware you could probably optimize the shift in assembler by    */
+  /*      using byte-swap instructions.                                     */
+  /*      polynomial $edb88320                                              */
+  /*                                                                        */
+  /*  --------------------------------------------------------------------  */
+
+#include <linux/crc32.h>
+
+static u32 crc32_tab[] = {
+      0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+      0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+      0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+      0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+      0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+      0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+      0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+      0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+      0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+      0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+      0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+      0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+      0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+      0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+      0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+      0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+      0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+      0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+      0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+      0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+      0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+      0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+      0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+      0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+      0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+      0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+      0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+      0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+      0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+      0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+      0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+      0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+      0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+      0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+      0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+      0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+      0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+      0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+      0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+      0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+      0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+      0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+      0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+      0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+      0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+      0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+      0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+      0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+      0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+      0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+      0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+      0x2d02ef8dL
+   };
+
+/* Return a 32-bit CRC of the contents of the buffer. */
+
+u32
+crc32(const void *buf, unsigned long len, u32 seed)
+{
+  unsigned long i;
+  register u32 crc32val;
+  const unsigned char *s = buf;
+
+  crc32val = seed;
+  for (i = 0;  i < len;  i ++)
+    {
+      crc32val =
+	crc32_tab[(crc32val ^ s[i]) & 0xff] ^
+	  (crc32val >> 8);
+    }
+  return crc32val;
+}
diff -urN linux-2.4.16/mm/memory.c lia64-2.4/mm/memory.c
--- linux-2.4.16/mm/memory.c	Mon Nov 26 11:19:24 2001
+++ lia64-2.4/mm/memory.c	Mon Nov 26 11:22:47 2001
@@ -44,6 +44,7 @@
 #include <linux/iobuf.h>
 #include <linux/highmem.h>
 #include <linux/pagemap.h>
+#include <linux/prefetch.h>
 
 #include <asm/pgalloc.h>
 #include <asm/uaccess.h>
@@ -119,7 +120,7 @@
 	pmd = pmd_offset(dir, 0);
 	pgd_clear(dir);
 	for (j = 0; j < PTRS_PER_PMD ; j++) {
-		prefetchw(pmd+j+(PREFETCH_STRIDE/16));
+		prefetchw(pmd + j + PREFETCH_STRIDE/sizeof(*pmd));
 		free_one_pmd(pmd+j);
 	}
 	pmd_free(pmd);
@@ -506,7 +507,7 @@
 			int ret;
 
 			spin_unlock(&mm->page_table_lock);
-			ret = handle_mm_fault(current->mm, vma, ptr, datain);
+			ret = handle_mm_fault(current->mm, vma, ptr, datain ? VM_WRITE : VM_READ);
 			if (ret <= 0) {
 				if (!ret)
 					goto out_unlock;
@@ -1131,7 +1132,6 @@
 	unlock_page(page);
 
 	flush_page_to_ram(page);
-	flush_icache_page(vma, page);
 	set_pte(page_table, pte);
 
 	/* No need to invalidate - it was non-present before */
@@ -1244,7 +1244,6 @@
 	if (pte_none(*page_table)) {
 		++mm->rss;
 		flush_page_to_ram(new_page);
-		flush_icache_page(vma, new_page);
 		entry = mk_pte(new_page, vma->vm_page_prot);
 		if (write_access)
 			entry = pte_mkwrite(pte_mkdirty(entry));
@@ -1285,8 +1284,10 @@
  */
 static inline int handle_pte_fault(struct mm_struct *mm,
 	struct vm_area_struct * vma, unsigned long address,
-	int write_access, pte_t * pte)
+	int access_type, pte_t * pte)
 {
+	int write_access = is_write_access(access_type);
+	int exec_access = is_exec_access(access_type);
 	pte_t entry;
 
 	entry = *pte;
@@ -1307,6 +1308,8 @@
 
 		entry = pte_mkdirty(entry);
 	}
+	if (exec_access)
+		entry = pte_mkexec(entry);
 	entry = pte_mkyoung(entry);
 	establish_pte(vma, address, pte, entry);
 	spin_unlock(&mm->page_table_lock);
@@ -1317,7 +1320,7 @@
  * By the time we get here, we already hold the mm semaphore
  */
 int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct * vma,
-	unsigned long address, int write_access)
+	unsigned long address, int access_type)
 {
 	pgd_t *pgd;
 	pmd_t *pmd;
@@ -1335,7 +1338,7 @@
 	if (pmd) {
 		pte_t * pte = pte_alloc(mm, pmd, address);
 		if (pte)
-			return handle_pte_fault(mm, vma, address, write_access, pte);
+			return handle_pte_fault(mm, vma, address, access_type, pte);
 	}
 	spin_unlock(&mm->page_table_lock);
 	return -1;
@@ -1426,7 +1429,7 @@
 	if (addr >= end)
 		BUG();
 	do {
-		if (handle_mm_fault(mm, vma, addr, write) < 0)
+		if (handle_mm_fault(mm, vma, addr, write ? VM_WRITE : VM_READ) < 0)
 			return -1;
 		addr += PAGE_SIZE;
 	} while (addr < end);
diff -urN linux-2.4.16/mm/mmap.c lia64-2.4/mm/mmap.c
--- linux-2.4.16/mm/mmap.c	Mon Nov  5 18:29:05 2001
+++ lia64-2.4/mm/mmap.c	Mon Nov  5 18:34:17 2001
@@ -204,6 +204,12 @@
 		_trans(prot, PROT_WRITE, VM_WRITE) |
 		_trans(prot, PROT_EXEC, VM_EXEC);
 	flag_bits =
+#ifdef MAP_WRITECOMBINED
+		_trans(flags, MAP_WRITECOMBINED, VM_WRITECOMBINED) |
+#endif
+#ifdef MAP_NONCACHED
+		_trans(flags, MAP_NONCACHED, VM_NONCACHED) |
+#endif
 		_trans(flags, MAP_GROWSDOWN, VM_GROWSDOWN) |
 		_trans(flags, MAP_DENYWRITE, VM_DENYWRITE) |
 		_trans(flags, MAP_EXECUTABLE, VM_EXECUTABLE);
diff -urN linux-2.4.16/mm/numa.c lia64-2.4/mm/numa.c
--- linux-2.4.16/mm/numa.c	Mon Sep 24 15:08:39 2001
+++ lia64-2.4/mm/numa.c	Mon Nov 19 23:23:01 2001
@@ -9,7 +9,7 @@
 #include <linux/mmzone.h>
 #include <linux/spinlock.h>
 
-int numnodes = 1;	/* Initialized for UMA platforms */
+int num_compact_nodes = 1;	/* Initialized for UMA platforms */
 
 static bootmem_data_t contig_bootmem_data;
 pg_data_t contig_page_data = { bdata: &contig_bootmem_data };
diff -urN linux-2.4.16/net/ipv4/fib_semantics.c lia64-2.4/net/ipv4/fib_semantics.c
--- linux-2.4.16/net/ipv4/fib_semantics.c	Tue Aug 22 08:59:00 2000
+++ lia64-2.4/net/ipv4/fib_semantics.c	Tue Aug 14 00:53:33 2001
@@ -155,7 +155,7 @@
 	return 0;
 }
 
-extern __inline__ struct fib_info * fib_find_info(const struct fib_info *nfi)
+static __inline__ struct fib_info * fib_find_info(const struct fib_info *nfi)
 {
 	for_fib_info() {
 		if (fi->fib_nhs != nfi->fib_nhs)
diff -urN linux-2.4.16/net/ipv4/ip_fragment.c lia64-2.4/net/ipv4/ip_fragment.c
--- linux-2.4.16/net/ipv4/ip_fragment.c	Mon Sep 24 15:08:41 2001
+++ lia64-2.4/net/ipv4/ip_fragment.c	Mon Sep 24 15:24:16 2001
@@ -130,19 +130,19 @@
 atomic_t ip_frag_mem = ATOMIC_INIT(0);	/* Memory used for fragments */
 
 /* Memory Tracking Functions. */
-extern __inline__ void frag_kfree_skb(struct sk_buff *skb)
+static __inline__ void frag_kfree_skb(struct sk_buff *skb)
 {
 	atomic_sub(skb->truesize, &ip_frag_mem);
 	kfree_skb(skb);
 }
 
-extern __inline__ void frag_free_queue(struct ipq *qp)
+static __inline__ void frag_free_queue(struct ipq *qp)
 {
 	atomic_sub(sizeof(struct ipq), &ip_frag_mem);
 	kfree(qp);
 }
 
-extern __inline__ struct ipq *frag_alloc_queue(void)
+static __inline__ struct ipq *frag_alloc_queue(void)
 {
 	struct ipq *qp = kmalloc(sizeof(struct ipq), GFP_ATOMIC);